2 * arizona.c - Wolfson Arizona class device shared support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/gcd.h>
14 #include <linux/module.h>
15 #include <linux/pm_runtime.h>
16 #include <sound/pcm.h>
17 #include <sound/pcm_params.h>
18 #include <sound/tlv.h>
20 #include <linux/mfd/arizona/core.h>
21 #include <linux/mfd/arizona/registers.h>
25 #define ARIZONA_AIF_BCLK_CTRL 0x00
26 #define ARIZONA_AIF_TX_PIN_CTRL 0x01
27 #define ARIZONA_AIF_RX_PIN_CTRL 0x02
28 #define ARIZONA_AIF_RATE_CTRL 0x03
29 #define ARIZONA_AIF_FORMAT 0x04
30 #define ARIZONA_AIF_TX_BCLK_RATE 0x05
31 #define ARIZONA_AIF_RX_BCLK_RATE 0x06
32 #define ARIZONA_AIF_FRAME_CTRL_1 0x07
33 #define ARIZONA_AIF_FRAME_CTRL_2 0x08
34 #define ARIZONA_AIF_FRAME_CTRL_3 0x09
35 #define ARIZONA_AIF_FRAME_CTRL_4 0x0A
36 #define ARIZONA_AIF_FRAME_CTRL_5 0x0B
37 #define ARIZONA_AIF_FRAME_CTRL_6 0x0C
38 #define ARIZONA_AIF_FRAME_CTRL_7 0x0D
39 #define ARIZONA_AIF_FRAME_CTRL_8 0x0E
40 #define ARIZONA_AIF_FRAME_CTRL_9 0x0F
41 #define ARIZONA_AIF_FRAME_CTRL_10 0x10
42 #define ARIZONA_AIF_FRAME_CTRL_11 0x11
43 #define ARIZONA_AIF_FRAME_CTRL_12 0x12
44 #define ARIZONA_AIF_FRAME_CTRL_13 0x13
45 #define ARIZONA_AIF_FRAME_CTRL_14 0x14
46 #define ARIZONA_AIF_FRAME_CTRL_15 0x15
47 #define ARIZONA_AIF_FRAME_CTRL_16 0x16
48 #define ARIZONA_AIF_FRAME_CTRL_17 0x17
49 #define ARIZONA_AIF_FRAME_CTRL_18 0x18
50 #define ARIZONA_AIF_TX_ENABLES 0x19
51 #define ARIZONA_AIF_RX_ENABLES 0x1A
52 #define ARIZONA_AIF_FORCE_WRITE 0x1B
54 #define arizona_fll_err(_fll, fmt, ...) \
55 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
56 #define arizona_fll_warn(_fll, fmt, ...) \
57 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
58 #define arizona_fll_dbg(_fll, fmt, ...) \
59 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
61 #define arizona_aif_err(_dai, fmt, ...) \
62 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
63 #define arizona_aif_warn(_dai, fmt, ...) \
64 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
65 #define arizona_aif_dbg(_dai, fmt, ...) \
66 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
68 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
145 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
147 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
153 0x0c, /* Noise mixer */
154 0x0d, /* Comfort noise */
224 EXPORT_SYMBOL_GPL(arizona_mixer_values);
226 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
227 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
229 static const char *arizona_vol_ramp_text[] = {
230 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
231 "15ms/6dB", "30ms/6dB",
234 const struct soc_enum arizona_in_vd_ramp =
235 SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP,
236 ARIZONA_IN_VD_RAMP_SHIFT, 7, arizona_vol_ramp_text);
237 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
239 const struct soc_enum arizona_in_vi_ramp =
240 SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP,
241 ARIZONA_IN_VI_RAMP_SHIFT, 7, arizona_vol_ramp_text);
242 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
244 const struct soc_enum arizona_out_vd_ramp =
245 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP,
246 ARIZONA_OUT_VD_RAMP_SHIFT, 7, arizona_vol_ramp_text);
247 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
249 const struct soc_enum arizona_out_vi_ramp =
250 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP,
251 ARIZONA_OUT_VI_RAMP_SHIFT, 7, arizona_vol_ramp_text);
252 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
254 static const char *arizona_lhpf_mode_text[] = {
255 "Low-pass", "High-pass"
258 const struct soc_enum arizona_lhpf1_mode =
259 SOC_ENUM_SINGLE(ARIZONA_HPLPF1_1, ARIZONA_LHPF1_MODE_SHIFT, 2,
260 arizona_lhpf_mode_text);
261 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
263 const struct soc_enum arizona_lhpf2_mode =
264 SOC_ENUM_SINGLE(ARIZONA_HPLPF2_1, ARIZONA_LHPF2_MODE_SHIFT, 2,
265 arizona_lhpf_mode_text);
266 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
268 const struct soc_enum arizona_lhpf3_mode =
269 SOC_ENUM_SINGLE(ARIZONA_HPLPF3_1, ARIZONA_LHPF3_MODE_SHIFT, 2,
270 arizona_lhpf_mode_text);
271 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
273 const struct soc_enum arizona_lhpf4_mode =
274 SOC_ENUM_SINGLE(ARIZONA_HPLPF4_1, ARIZONA_LHPF4_MODE_SHIFT, 2,
275 arizona_lhpf_mode_text);
276 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
278 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
283 EXPORT_SYMBOL_GPL(arizona_in_ev);
285 int arizona_out_ev(struct snd_soc_dapm_widget *w,
286 struct snd_kcontrol *kcontrol,
291 EXPORT_SYMBOL_GPL(arizona_out_ev);
293 static unsigned int arizona_sysclk_48k_rates[] = {
303 static unsigned int arizona_sysclk_44k1_rates[] = {
313 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
316 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
319 int ref, div, refclk;
322 case ARIZONA_CLK_OPCLK:
323 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
324 refclk = priv->sysclk;
326 case ARIZONA_CLK_ASYNC_OPCLK:
327 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
328 refclk = priv->asyncclk;
335 rates = arizona_sysclk_44k1_rates;
337 rates = arizona_sysclk_48k_rates;
339 for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
340 rates[ref] <= refclk; ref++) {
342 while (rates[ref] / div >= freq && div < 32) {
343 if (rates[ref] / div == freq) {
344 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
346 snd_soc_update_bits(codec, reg,
347 ARIZONA_OPCLK_DIV_MASK |
348 ARIZONA_OPCLK_SEL_MASK,
350 ARIZONA_OPCLK_DIV_SHIFT) |
358 dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
362 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
363 int source, unsigned int freq, int dir)
365 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
366 struct arizona *arizona = priv->arizona;
369 unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
370 unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
374 case ARIZONA_CLK_SYSCLK:
376 reg = ARIZONA_SYSTEM_CLOCK_1;
378 mask |= ARIZONA_SYSCLK_FRAC;
380 case ARIZONA_CLK_ASYNCCLK:
382 reg = ARIZONA_ASYNC_CLOCK_1;
383 clk = &priv->asyncclk;
385 case ARIZONA_CLK_OPCLK:
386 case ARIZONA_CLK_ASYNC_OPCLK:
387 return arizona_set_opclk(codec, clk_id, freq);
398 val |= 1 << ARIZONA_SYSCLK_FREQ_SHIFT;
402 val |= 2 << ARIZONA_SYSCLK_FREQ_SHIFT;
406 val |= 3 << ARIZONA_SYSCLK_FREQ_SHIFT;
410 val |= 4 << ARIZONA_SYSCLK_FREQ_SHIFT;
414 val |= 5 << ARIZONA_SYSCLK_FREQ_SHIFT;
418 val |= 6 << ARIZONA_SYSCLK_FREQ_SHIFT;
427 val |= ARIZONA_SYSCLK_FRAC;
429 dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
431 return regmap_update_bits(arizona->regmap, reg, mask, val);
433 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
435 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
437 struct snd_soc_codec *codec = dai->codec;
438 int lrclk, bclk, mode, base;
440 base = dai->driver->base;
445 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
446 case SND_SOC_DAIFMT_DSP_A:
449 case SND_SOC_DAIFMT_DSP_B:
452 case SND_SOC_DAIFMT_I2S:
455 case SND_SOC_DAIFMT_LEFT_J:
459 arizona_aif_err(dai, "Unsupported DAI format %d\n",
460 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
464 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
465 case SND_SOC_DAIFMT_CBS_CFS:
467 case SND_SOC_DAIFMT_CBS_CFM:
468 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
470 case SND_SOC_DAIFMT_CBM_CFS:
471 bclk |= ARIZONA_AIF1_BCLK_MSTR;
473 case SND_SOC_DAIFMT_CBM_CFM:
474 bclk |= ARIZONA_AIF1_BCLK_MSTR;
475 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
478 arizona_aif_err(dai, "Unsupported master mode %d\n",
479 fmt & SND_SOC_DAIFMT_MASTER_MASK);
483 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
484 case SND_SOC_DAIFMT_NB_NF:
486 case SND_SOC_DAIFMT_IB_IF:
487 bclk |= ARIZONA_AIF1_BCLK_INV;
488 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
490 case SND_SOC_DAIFMT_IB_NF:
491 bclk |= ARIZONA_AIF1_BCLK_INV;
493 case SND_SOC_DAIFMT_NB_IF:
494 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
500 snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
501 ARIZONA_AIF1_BCLK_INV | ARIZONA_AIF1_BCLK_MSTR,
503 snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_PIN_CTRL,
504 ARIZONA_AIF1TX_LRCLK_INV |
505 ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
506 snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_PIN_CTRL,
507 ARIZONA_AIF1RX_LRCLK_INV |
508 ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
509 snd_soc_update_bits(codec, base + ARIZONA_AIF_FORMAT,
510 ARIZONA_AIF1_FMT_MASK, mode);
515 static const int arizona_48k_bclk_rates[] = {
537 static const unsigned int arizona_48k_rates[] = {
555 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
556 .count = ARRAY_SIZE(arizona_48k_rates),
557 .list = arizona_48k_rates,
560 static const int arizona_44k1_bclk_rates[] = {
582 static const unsigned int arizona_44k1_rates[] = {
592 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
593 .count = ARRAY_SIZE(arizona_44k1_rates),
594 .list = arizona_44k1_rates,
597 static int arizona_sr_vals[] = {
624 static int arizona_startup(struct snd_pcm_substream *substream,
625 struct snd_soc_dai *dai)
627 struct snd_soc_codec *codec = dai->codec;
628 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
629 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
630 const struct snd_pcm_hw_constraint_list *constraint;
631 unsigned int base_rate;
633 switch (dai_priv->clk) {
634 case ARIZONA_CLK_SYSCLK:
635 base_rate = priv->sysclk;
637 case ARIZONA_CLK_ASYNCCLK:
638 base_rate = priv->asyncclk;
644 if (base_rate % 8000)
645 constraint = &arizona_44k1_constraint;
647 constraint = &arizona_48k_constraint;
649 return snd_pcm_hw_constraint_list(substream->runtime, 0,
650 SNDRV_PCM_HW_PARAM_RATE,
654 static int arizona_hw_params(struct snd_pcm_substream *substream,
655 struct snd_pcm_hw_params *params,
656 struct snd_soc_dai *dai)
658 struct snd_soc_codec *codec = dai->codec;
659 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
660 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
661 int base = dai->driver->base;
664 int bclk, lrclk, wl, frame, sr_val;
666 if (params_rate(params) % 8000)
667 rates = &arizona_44k1_bclk_rates[0];
669 rates = &arizona_48k_bclk_rates[0];
671 for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
672 if (rates[i] >= snd_soc_params_to_bclk(params) &&
673 rates[i] % params_rate(params) == 0) {
678 if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
679 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
680 params_rate(params));
684 for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
685 if (arizona_sr_vals[i] == params_rate(params))
687 if (i == ARRAY_SIZE(arizona_sr_vals)) {
688 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
689 params_rate(params));
694 lrclk = snd_soc_params_to_bclk(params) / params_rate(params);
696 arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
697 rates[bclk], rates[bclk] / lrclk);
699 wl = snd_pcm_format_width(params_format(params));
700 frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl;
703 * We will need to be more flexible than this in future,
704 * currently we use a single sample rate for SYSCLK.
706 switch (dai_priv->clk) {
707 case ARIZONA_CLK_SYSCLK:
708 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
709 ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
710 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
711 ARIZONA_AIF1_RATE_MASK, 0);
713 case ARIZONA_CLK_ASYNCCLK:
714 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
715 ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
716 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
717 ARIZONA_AIF1_RATE_MASK, 8);
720 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
724 snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
725 ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
726 snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_BCLK_RATE,
727 ARIZONA_AIF1TX_BCPF_MASK, lrclk);
728 snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_BCLK_RATE,
729 ARIZONA_AIF1RX_BCPF_MASK, lrclk);
730 snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_1,
731 ARIZONA_AIF1TX_WL_MASK |
732 ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
733 snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_2,
734 ARIZONA_AIF1RX_WL_MASK |
735 ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
740 static const char *arizona_dai_clk_str(int clk_id)
743 case ARIZONA_CLK_SYSCLK:
745 case ARIZONA_CLK_ASYNCCLK:
748 return "Unknown clock";
752 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
753 int clk_id, unsigned int freq, int dir)
755 struct snd_soc_codec *codec = dai->codec;
756 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
757 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
758 struct snd_soc_dapm_route routes[2];
761 case ARIZONA_CLK_SYSCLK:
762 case ARIZONA_CLK_ASYNCCLK:
768 if (clk_id == dai_priv->clk)
772 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
777 dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
778 arizona_dai_clk_str(clk_id));
780 memset(&routes, 0, sizeof(routes));
781 routes[0].sink = dai->driver->capture.stream_name;
782 routes[1].sink = dai->driver->playback.stream_name;
784 routes[0].source = arizona_dai_clk_str(dai_priv->clk);
785 routes[1].source = arizona_dai_clk_str(dai_priv->clk);
786 snd_soc_dapm_del_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
788 routes[0].source = arizona_dai_clk_str(clk_id);
789 routes[1].source = arizona_dai_clk_str(clk_id);
790 snd_soc_dapm_add_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
792 dai_priv->clk = clk_id;
794 return snd_soc_dapm_sync(&codec->dapm);
797 const struct snd_soc_dai_ops arizona_dai_ops = {
798 .startup = arizona_startup,
799 .set_fmt = arizona_set_fmt,
800 .hw_params = arizona_hw_params,
801 .set_sysclk = arizona_dai_set_sysclk,
803 EXPORT_SYMBOL_GPL(arizona_dai_ops);
805 int arizona_init_dai(struct arizona_priv *priv, int id)
807 struct arizona_dai_priv *dai_priv = &priv->dai[id];
809 dai_priv->clk = ARIZONA_CLK_SYSCLK;
813 EXPORT_SYMBOL_GPL(arizona_init_dai);
815 static irqreturn_t arizona_fll_lock(int irq, void *data)
817 struct arizona_fll *fll = data;
819 arizona_fll_dbg(fll, "Lock status changed\n");
821 complete(&fll->lock);
826 static irqreturn_t arizona_fll_clock_ok(int irq, void *data)
828 struct arizona_fll *fll = data;
830 arizona_fll_dbg(fll, "clock OK\n");
844 { 64000, 128000, 3, 8 },
845 { 128000, 256000, 2, 4 },
846 { 256000, 1000000, 1, 2 },
847 { 1000000, 13500000, 0, 1 },
850 struct arizona_fll_cfg {
859 static int arizona_calc_fll(struct arizona_fll *fll,
860 struct arizona_fll_cfg *cfg,
864 unsigned int target, div, gcd_fll;
867 arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, Fout);
869 /* Fref must be <=13.5MHz */
872 while ((Fref / div) > 13500000) {
878 "Can't scale %dMHz in to <=13.5MHz\n",
884 /* Apply the division for our remaining calculations */
887 /* Fvco should be over the targt; don't check the upper bound */
889 while (Fout * div < 90000000 * fll->vco_mult) {
892 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
897 target = Fout * div / fll->vco_mult;
900 arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
902 /* Find an appropraite FLL_FRATIO and factor it out of the target */
903 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
904 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
905 cfg->fratio = fll_fratios[i].fratio;
906 ratio = fll_fratios[i].ratio;
910 if (i == ARRAY_SIZE(fll_fratios)) {
911 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
916 cfg->n = target / (ratio * Fref);
919 gcd_fll = gcd(target, ratio * Fref);
920 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
922 cfg->theta = (target - (cfg->n * ratio * Fref))
924 cfg->lambda = (ratio * Fref) / gcd_fll;
930 arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
931 cfg->n, cfg->theta, cfg->lambda);
932 arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
933 cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
939 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
940 struct arizona_fll_cfg *cfg, int source)
942 regmap_update_bits(arizona->regmap, base + 3,
943 ARIZONA_FLL1_THETA_MASK, cfg->theta);
944 regmap_update_bits(arizona->regmap, base + 4,
945 ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
946 regmap_update_bits(arizona->regmap, base + 5,
947 ARIZONA_FLL1_FRATIO_MASK,
948 cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
949 regmap_update_bits(arizona->regmap, base + 6,
950 ARIZONA_FLL1_CLK_REF_DIV_MASK |
951 ARIZONA_FLL1_CLK_REF_SRC_MASK,
952 cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
953 source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
955 regmap_update_bits(arizona->regmap, base + 2,
956 ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
957 ARIZONA_FLL1_CTRL_UPD | cfg->n);
960 int arizona_set_fll(struct arizona_fll *fll, int source,
961 unsigned int Fref, unsigned int Fout)
963 struct arizona *arizona = fll->arizona;
964 struct arizona_fll_cfg cfg, sync;
965 unsigned int reg, val;
970 if (fll->fref == Fref && fll->fout == Fout)
973 ret = regmap_read(arizona->regmap, fll->base + 1, ®);
975 arizona_fll_err(fll, "Failed to read current state: %d\n",
979 ena = reg & ARIZONA_FLL1_ENA;
982 /* Do we have a 32kHz reference? */
983 regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
984 switch (val & ARIZONA_CLK_32K_SRC_MASK) {
985 case ARIZONA_CLK_SRC_MCLK1:
986 case ARIZONA_CLK_SRC_MCLK2:
987 syncsrc = val & ARIZONA_CLK_32K_SRC_MASK;
993 if (source == syncsrc)
997 ret = arizona_calc_fll(fll, &sync, Fref, Fout);
1001 ret = arizona_calc_fll(fll, &cfg, 32768, Fout);
1005 ret = arizona_calc_fll(fll, &cfg, Fref, Fout);
1010 regmap_update_bits(arizona->regmap, fll->base + 1,
1011 ARIZONA_FLL1_ENA, 0);
1012 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1013 ARIZONA_FLL1_SYNC_ENA, 0);
1016 pm_runtime_put_autosuspend(arizona->dev);
1024 regmap_update_bits(arizona->regmap, fll->base + 5,
1025 ARIZONA_FLL1_OUTDIV_MASK,
1026 cfg.outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1029 arizona_apply_fll(arizona, fll->base, &cfg, syncsrc);
1030 arizona_apply_fll(arizona, fll->base + 0x10, &sync, source);
1032 arizona_apply_fll(arizona, fll->base, &cfg, source);
1036 pm_runtime_get(arizona->dev);
1038 /* Clear any pending completions */
1039 try_wait_for_completion(&fll->ok);
1041 regmap_update_bits(arizona->regmap, fll->base + 1,
1042 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
1044 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1045 ARIZONA_FLL1_SYNC_ENA,
1046 ARIZONA_FLL1_SYNC_ENA);
1048 ret = wait_for_completion_timeout(&fll->ok,
1049 msecs_to_jiffies(250));
1051 arizona_fll_warn(fll, "Timed out waiting for lock\n");
1058 EXPORT_SYMBOL_GPL(arizona_set_fll);
1060 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1061 int ok_irq, struct arizona_fll *fll)
1065 init_completion(&fll->lock);
1066 init_completion(&fll->ok);
1070 fll->arizona = arizona;
1072 snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
1073 snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
1074 "FLL%d clock OK", id);
1076 ret = arizona_request_irq(arizona, lock_irq, fll->lock_name,
1077 arizona_fll_lock, fll);
1079 dev_err(arizona->dev, "Failed to get FLL%d lock IRQ: %d\n",
1083 ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name,
1084 arizona_fll_clock_ok, fll);
1086 dev_err(arizona->dev, "Failed to get FLL%d clock OK IRQ: %d\n",
1092 EXPORT_SYMBOL_GPL(arizona_init_fll);
1094 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
1095 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1096 MODULE_LICENSE("GPL");