2 * cs42l52.c -- CS42L52 ALSA SoC audio driver
4 * Copyright 2012 CirrusLogic, Inc.
6 * Author: Georgi Vlaev <joe@nucleusys.com>
7 * Author: Brian Austin <brian.austin@cirrus.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/of_gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/input.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26 #include <linux/workqueue.h>
27 #include <linux/platform_device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
35 #include <sound/cs42l52.h>
43 struct cs42l52_private {
44 struct regmap *regmap;
45 struct snd_soc_codec *codec;
47 struct sp_config config;
48 struct cs42l52_platform_data pdata;
53 #if IS_ENABLED(CONFIG_INPUT)
54 struct input_dev *beep;
55 struct work_struct beep_work;
60 static const struct reg_default cs42l52_reg_defaults[] = {
61 { CS42L52_PWRCTL1, 0x9F }, /* r02 PWRCTL 1 */
62 { CS42L52_PWRCTL2, 0x07 }, /* r03 PWRCTL 2 */
63 { CS42L52_PWRCTL3, 0xFF }, /* r04 PWRCTL 3 */
64 { CS42L52_CLK_CTL, 0xA0 }, /* r05 Clocking Ctl */
65 { CS42L52_IFACE_CTL1, 0x00 }, /* r06 Interface Ctl 1 */
66 { CS42L52_ADC_PGA_A, 0x80 }, /* r08 Input A Select */
67 { CS42L52_ADC_PGA_B, 0x80 }, /* r09 Input B Select */
68 { CS42L52_ANALOG_HPF_CTL, 0xA5 }, /* r0A Analog HPF Ctl */
69 { CS42L52_ADC_HPF_FREQ, 0x00 }, /* r0B ADC HPF Corner Freq */
70 { CS42L52_ADC_MISC_CTL, 0x00 }, /* r0C Misc. ADC Ctl */
71 { CS42L52_PB_CTL1, 0x60 }, /* r0D Playback Ctl 1 */
72 { CS42L52_MISC_CTL, 0x02 }, /* r0E Misc. Ctl */
73 { CS42L52_PB_CTL2, 0x00 }, /* r0F Playback Ctl 2 */
74 { CS42L52_MICA_CTL, 0x00 }, /* r10 MICA Amp Ctl */
75 { CS42L52_MICB_CTL, 0x00 }, /* r11 MICB Amp Ctl */
76 { CS42L52_PGAA_CTL, 0x00 }, /* r12 PGAA Vol, Misc. */
77 { CS42L52_PGAB_CTL, 0x00 }, /* r13 PGAB Vol, Misc. */
78 { CS42L52_PASSTHRUA_VOL, 0x00 }, /* r14 Bypass A Vol */
79 { CS42L52_PASSTHRUB_VOL, 0x00 }, /* r15 Bypass B Vol */
80 { CS42L52_ADCA_VOL, 0x00 }, /* r16 ADCA Volume */
81 { CS42L52_ADCB_VOL, 0x00 }, /* r17 ADCB Volume */
82 { CS42L52_ADCA_MIXER_VOL, 0x80 }, /* r18 ADCA Mixer Volume */
83 { CS42L52_ADCB_MIXER_VOL, 0x80 }, /* r19 ADCB Mixer Volume */
84 { CS42L52_PCMA_MIXER_VOL, 0x00 }, /* r1A PCMA Mixer Volume */
85 { CS42L52_PCMB_MIXER_VOL, 0x00 }, /* r1B PCMB Mixer Volume */
86 { CS42L52_BEEP_FREQ, 0x00 }, /* r1C Beep Freq on Time */
87 { CS42L52_BEEP_VOL, 0x00 }, /* r1D Beep Volume off Time */
88 { CS42L52_BEEP_TONE_CTL, 0x00 }, /* r1E Beep Tone Cfg. */
89 { CS42L52_TONE_CTL, 0x00 }, /* r1F Tone Ctl */
90 { CS42L52_MASTERA_VOL, 0x00 }, /* r20 Master A Volume */
91 { CS42L52_MASTERB_VOL, 0x00 }, /* r21 Master B Volume */
92 { CS42L52_HPA_VOL, 0x00 }, /* r22 Headphone A Volume */
93 { CS42L52_HPB_VOL, 0x00 }, /* r23 Headphone B Volume */
94 { CS42L52_SPKA_VOL, 0x00 }, /* r24 Speaker A Volume */
95 { CS42L52_SPKB_VOL, 0x00 }, /* r25 Speaker B Volume */
96 { CS42L52_ADC_PCM_MIXER, 0x00 }, /* r26 Channel Mixer and Swap */
97 { CS42L52_LIMITER_CTL1, 0x00 }, /* r27 Limit Ctl 1 Thresholds */
98 { CS42L52_LIMITER_CTL2, 0x7F }, /* r28 Limit Ctl 2 Release Rate */
99 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
100 { CS42L52_ALC_CTL, 0x00 }, /* r2A ALC Ctl 1 Attack Rate */
101 { CS42L52_ALC_RATE, 0x3F }, /* r2B ALC Release Rate */
102 { CS42L52_ALC_THRESHOLD, 0x3f }, /* r2C ALC Thresholds */
103 { CS42L52_NOISE_GATE_CTL, 0x00 }, /* r2D Noise Gate Ctl */
104 { CS42L52_CLK_STATUS, 0x00 }, /* r2E Overflow and Clock Status */
105 { CS42L52_BATT_COMPEN, 0x00 }, /* r2F battery Compensation */
106 { CS42L52_BATT_LEVEL, 0x00 }, /* r30 VP Battery Level */
107 { CS42L52_SPK_STATUS, 0x00 }, /* r31 Speaker Status */
108 { CS42L52_TEM_CTL, 0x3B }, /* r32 Temp Ctl */
109 { CS42L52_THE_FOLDBACK, 0x00 }, /* r33 Foldback */
112 static bool cs42l52_readable_register(struct device *dev, unsigned int reg)
116 case CS42L52_PWRCTL1:
117 case CS42L52_PWRCTL2:
118 case CS42L52_PWRCTL3:
119 case CS42L52_CLK_CTL:
120 case CS42L52_IFACE_CTL1:
121 case CS42L52_IFACE_CTL2:
122 case CS42L52_ADC_PGA_A:
123 case CS42L52_ADC_PGA_B:
124 case CS42L52_ANALOG_HPF_CTL:
125 case CS42L52_ADC_HPF_FREQ:
126 case CS42L52_ADC_MISC_CTL:
127 case CS42L52_PB_CTL1:
128 case CS42L52_MISC_CTL:
129 case CS42L52_PB_CTL2:
130 case CS42L52_MICA_CTL:
131 case CS42L52_MICB_CTL:
132 case CS42L52_PGAA_CTL:
133 case CS42L52_PGAB_CTL:
134 case CS42L52_PASSTHRUA_VOL:
135 case CS42L52_PASSTHRUB_VOL:
136 case CS42L52_ADCA_VOL:
137 case CS42L52_ADCB_VOL:
138 case CS42L52_ADCA_MIXER_VOL:
139 case CS42L52_ADCB_MIXER_VOL:
140 case CS42L52_PCMA_MIXER_VOL:
141 case CS42L52_PCMB_MIXER_VOL:
142 case CS42L52_BEEP_FREQ:
143 case CS42L52_BEEP_VOL:
144 case CS42L52_BEEP_TONE_CTL:
145 case CS42L52_TONE_CTL:
146 case CS42L52_MASTERA_VOL:
147 case CS42L52_MASTERB_VOL:
148 case CS42L52_HPA_VOL:
149 case CS42L52_HPB_VOL:
150 case CS42L52_SPKA_VOL:
151 case CS42L52_SPKB_VOL:
152 case CS42L52_ADC_PCM_MIXER:
153 case CS42L52_LIMITER_CTL1:
154 case CS42L52_LIMITER_CTL2:
155 case CS42L52_LIMITER_AT_RATE:
156 case CS42L52_ALC_CTL:
157 case CS42L52_ALC_RATE:
158 case CS42L52_ALC_THRESHOLD:
159 case CS42L52_NOISE_GATE_CTL:
160 case CS42L52_CLK_STATUS:
161 case CS42L52_BATT_COMPEN:
162 case CS42L52_BATT_LEVEL:
163 case CS42L52_SPK_STATUS:
164 case CS42L52_TEM_CTL:
165 case CS42L52_THE_FOLDBACK:
166 case CS42L52_CHARGE_PUMP:
173 static bool cs42l52_volatile_register(struct device *dev, unsigned int reg)
176 case CS42L52_IFACE_CTL2:
177 case CS42L52_CLK_STATUS:
178 case CS42L52_BATT_LEVEL:
179 case CS42L52_SPK_STATUS:
180 case CS42L52_CHARGE_PUMP:
187 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
189 static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
191 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
193 static DECLARE_TLV_DB_SCALE(mic_tlv, 1600, 100, 0);
195 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
197 static DECLARE_TLV_DB_SCALE(mix_tlv, -50, 50, 0);
199 static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
201 static const unsigned int limiter_tlv[] = {
202 TLV_DB_RANGE_HEAD(2),
203 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
204 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
207 static const char * const cs42l52_adca_text[] = {
208 "Input1A", "Input2A", "Input3A", "Input4A", "PGA Input Left"};
210 static const char * const cs42l52_adcb_text[] = {
211 "Input1B", "Input2B", "Input3B", "Input4B", "PGA Input Right"};
213 static SOC_ENUM_SINGLE_DECL(adca_enum,
214 CS42L52_ADC_PGA_A, 5, cs42l52_adca_text);
216 static SOC_ENUM_SINGLE_DECL(adcb_enum,
217 CS42L52_ADC_PGA_B, 5, cs42l52_adcb_text);
219 static const struct snd_kcontrol_new adca_mux =
220 SOC_DAPM_ENUM("Left ADC Input Capture Mux", adca_enum);
222 static const struct snd_kcontrol_new adcb_mux =
223 SOC_DAPM_ENUM("Right ADC Input Capture Mux", adcb_enum);
225 static const char * const mic_bias_level_text[] = {
226 "0.5 +VA", "0.6 +VA", "0.7 +VA",
227 "0.8 +VA", "0.83 +VA", "0.91 +VA"
230 static SOC_ENUM_SINGLE_DECL(mic_bias_level_enum,
231 CS42L52_IFACE_CTL2, 0, mic_bias_level_text);
233 static const char * const cs42l52_mic_text[] = { "MIC1", "MIC2" };
235 static SOC_ENUM_SINGLE_DECL(mica_enum,
236 CS42L52_MICA_CTL, 5, cs42l52_mic_text);
238 static SOC_ENUM_SINGLE_DECL(micb_enum,
239 CS42L52_MICB_CTL, 5, cs42l52_mic_text);
241 static const char * const digital_output_mux_text[] = {"ADC", "DSP"};
243 static SOC_ENUM_SINGLE_DECL(digital_output_mux_enum,
244 CS42L52_ADC_MISC_CTL, 6,
245 digital_output_mux_text);
247 static const struct snd_kcontrol_new digital_output_mux =
248 SOC_DAPM_ENUM("Digital Output Mux", digital_output_mux_enum);
250 static const char * const hp_gain_num_text[] = {
251 "0.3959", "0.4571", "0.5111", "0.6047",
252 "0.7099", "0.8399", "1.000", "1.1430"
255 static SOC_ENUM_SINGLE_DECL(hp_gain_enum,
259 static const char * const beep_pitch_text[] = {
260 "C4", "C5", "D5", "E5", "F5", "G5", "A5", "B5",
261 "C6", "D6", "E6", "F6", "G6", "A6", "B6", "C7"
264 static SOC_ENUM_SINGLE_DECL(beep_pitch_enum,
265 CS42L52_BEEP_FREQ, 4,
268 static const char * const beep_ontime_text[] = {
269 "86 ms", "430 ms", "780 ms", "1.20 s", "1.50 s",
270 "1.80 s", "2.20 s", "2.50 s", "2.80 s", "3.20 s",
271 "3.50 s", "3.80 s", "4.20 s", "4.50 s", "4.80 s", "5.20 s"
274 static SOC_ENUM_SINGLE_DECL(beep_ontime_enum,
275 CS42L52_BEEP_FREQ, 0,
278 static const char * const beep_offtime_text[] = {
279 "1.23 s", "2.58 s", "3.90 s", "5.20 s",
280 "6.60 s", "8.05 s", "9.35 s", "10.80 s"
283 static SOC_ENUM_SINGLE_DECL(beep_offtime_enum,
287 static const char * const beep_config_text[] = {
288 "Off", "Single", "Multiple", "Continuous"
291 static SOC_ENUM_SINGLE_DECL(beep_config_enum,
292 CS42L52_BEEP_TONE_CTL, 6,
295 static const char * const beep_bass_text[] = {
296 "50 Hz", "100 Hz", "200 Hz", "250 Hz"
299 static SOC_ENUM_SINGLE_DECL(beep_bass_enum,
300 CS42L52_BEEP_TONE_CTL, 1,
303 static const char * const beep_treble_text[] = {
304 "5 kHz", "7 kHz", "10 kHz", " 15 kHz"
307 static SOC_ENUM_SINGLE_DECL(beep_treble_enum,
308 CS42L52_BEEP_TONE_CTL, 3,
311 static const char * const ng_threshold_text[] = {
312 "-34dB", "-37dB", "-40dB", "-43dB",
313 "-46dB", "-52dB", "-58dB", "-64dB"
316 static SOC_ENUM_SINGLE_DECL(ng_threshold_enum,
317 CS42L52_NOISE_GATE_CTL, 2,
320 static const char * const cs42l52_ng_delay_text[] = {
321 "50ms", "100ms", "150ms", "200ms"};
323 static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
324 CS42L52_NOISE_GATE_CTL, 0,
325 cs42l52_ng_delay_text);
327 static const char * const cs42l52_ng_type_text[] = {
328 "Apply Specific", "Apply All"
331 static SOC_ENUM_SINGLE_DECL(ng_type_enum,
332 CS42L52_NOISE_GATE_CTL, 6,
333 cs42l52_ng_type_text);
335 static const char * const left_swap_text[] = {
336 "Left", "LR 2", "Right"};
338 static const char * const right_swap_text[] = {
339 "Right", "LR 2", "Left"};
341 static const unsigned int swap_values[] = { 0, 1, 3 };
343 static const struct soc_enum adca_swap_enum =
344 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 3,
345 ARRAY_SIZE(left_swap_text),
349 static const struct snd_kcontrol_new adca_mixer =
350 SOC_DAPM_ENUM("Route", adca_swap_enum);
352 static const struct soc_enum pcma_swap_enum =
353 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 3,
354 ARRAY_SIZE(left_swap_text),
358 static const struct snd_kcontrol_new pcma_mixer =
359 SOC_DAPM_ENUM("Route", pcma_swap_enum);
361 static const struct soc_enum adcb_swap_enum =
362 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 3,
363 ARRAY_SIZE(right_swap_text),
367 static const struct snd_kcontrol_new adcb_mixer =
368 SOC_DAPM_ENUM("Route", adcb_swap_enum);
370 static const struct soc_enum pcmb_swap_enum =
371 SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 3,
372 ARRAY_SIZE(right_swap_text),
376 static const struct snd_kcontrol_new pcmb_mixer =
377 SOC_DAPM_ENUM("Route", pcmb_swap_enum);
380 static const struct snd_kcontrol_new passthrul_ctl =
381 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 6, 1, 0);
383 static const struct snd_kcontrol_new passthrur_ctl =
384 SOC_DAPM_SINGLE("Switch", CS42L52_MISC_CTL, 7, 1, 0);
386 static const struct snd_kcontrol_new spkl_ctl =
387 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 0, 1, 1);
389 static const struct snd_kcontrol_new spkr_ctl =
390 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 2, 1, 1);
392 static const struct snd_kcontrol_new hpl_ctl =
393 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 4, 1, 1);
395 static const struct snd_kcontrol_new hpr_ctl =
396 SOC_DAPM_SINGLE("Switch", CS42L52_PWRCTL3, 6, 1, 1);
398 static const struct snd_kcontrol_new cs42l52_snd_controls[] = {
400 SOC_DOUBLE_R_SX_TLV("Master Volume", CS42L52_MASTERA_VOL,
401 CS42L52_MASTERB_VOL, 0, 0x34, 0xE4, hl_tlv),
403 SOC_DOUBLE_R_SX_TLV("Headphone Volume", CS42L52_HPA_VOL,
404 CS42L52_HPB_VOL, 0, 0x34, 0xCC, hpd_tlv),
406 SOC_ENUM("Headphone Analog Gain", hp_gain_enum),
408 SOC_DOUBLE_R_SX_TLV("Speaker Volume", CS42L52_SPKA_VOL,
409 CS42L52_SPKB_VOL, 0, 0x1, 0xff, hl_tlv),
411 SOC_DOUBLE_R_SX_TLV("Bypass Volume", CS42L52_PASSTHRUA_VOL,
412 CS42L52_PASSTHRUB_VOL, 6, 0x18, 0x90, pga_tlv),
414 SOC_DOUBLE("Bypass Mute", CS42L52_MISC_CTL, 4, 5, 1, 0),
416 SOC_DOUBLE_R_TLV("MIC Gain Volume", CS42L52_MICA_CTL,
417 CS42L52_MICB_CTL, 0, 0x10, 0, mic_tlv),
419 SOC_ENUM("MIC Bias Level", mic_bias_level_enum),
421 SOC_DOUBLE_R_SX_TLV("ADC Volume", CS42L52_ADCA_VOL,
422 CS42L52_ADCB_VOL, 7, 0x80, 0xA0, ipd_tlv),
423 SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume",
424 CS42L52_ADCA_MIXER_VOL, CS42L52_ADCB_MIXER_VOL,
425 6, 0x7f, 0x19, ipd_tlv),
427 SOC_DOUBLE("ADC Switch", CS42L52_ADC_MISC_CTL, 0, 1, 1, 0),
429 SOC_DOUBLE_R("ADC Mixer Switch", CS42L52_ADCA_MIXER_VOL,
430 CS42L52_ADCB_MIXER_VOL, 7, 1, 1),
432 SOC_DOUBLE_R_SX_TLV("PGA Volume", CS42L52_PGAA_CTL,
433 CS42L52_PGAB_CTL, 0, 0x28, 0x30, pga_tlv),
435 SOC_DOUBLE_R_SX_TLV("PCM Mixer Volume",
436 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL,
437 0, 0x7f, 0x19, mix_tlv),
438 SOC_DOUBLE_R("PCM Mixer Switch",
439 CS42L52_PCMA_MIXER_VOL, CS42L52_PCMB_MIXER_VOL, 7, 1, 1),
441 SOC_ENUM("Beep Config", beep_config_enum),
442 SOC_ENUM("Beep Pitch", beep_pitch_enum),
443 SOC_ENUM("Beep on Time", beep_ontime_enum),
444 SOC_ENUM("Beep off Time", beep_offtime_enum),
445 SOC_SINGLE_SX_TLV("Beep Volume", CS42L52_BEEP_VOL,
446 0, 0x07, 0x1f, beep_tlv),
447 SOC_SINGLE("Beep Mixer Switch", CS42L52_BEEP_TONE_CTL, 5, 1, 1),
448 SOC_ENUM("Beep Treble Corner Freq", beep_treble_enum),
449 SOC_ENUM("Beep Bass Corner Freq", beep_bass_enum),
451 SOC_SINGLE("Tone Control Switch", CS42L52_BEEP_TONE_CTL, 0, 1, 1),
452 SOC_SINGLE_TLV("Treble Gain Volume",
453 CS42L52_TONE_CTL, 4, 15, 1, hl_tlv),
454 SOC_SINGLE_TLV("Bass Gain Volume",
455 CS42L52_TONE_CTL, 0, 15, 1, hl_tlv),
458 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
459 CS42L52_LIMITER_CTL1, 5, 7, 0, limiter_tlv),
460 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
461 CS42L52_LIMITER_CTL1, 2, 7, 0, limiter_tlv),
462 SOC_SINGLE_TLV("Limiter Release Rate Volume",
463 CS42L52_LIMITER_CTL2, 0, 63, 0, limiter_tlv),
464 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
465 CS42L52_LIMITER_AT_RATE, 0, 63, 0, limiter_tlv),
467 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
468 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
469 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
472 SOC_SINGLE_TLV("ALC Attack Rate Volume", CS42L52_ALC_CTL,
473 0, 63, 0, limiter_tlv),
474 SOC_SINGLE_TLV("ALC Release Rate Volume", CS42L52_ALC_RATE,
475 0, 63, 0, limiter_tlv),
476 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L52_ALC_THRESHOLD,
477 5, 7, 0, limiter_tlv),
478 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L52_ALC_THRESHOLD,
479 2, 7, 0, limiter_tlv),
481 SOC_DOUBLE_R("ALC SR Capture Switch", CS42L52_PGAA_CTL,
482 CS42L52_PGAB_CTL, 7, 1, 1),
483 SOC_DOUBLE_R("ALC ZC Capture Switch", CS42L52_PGAA_CTL,
484 CS42L52_PGAB_CTL, 6, 1, 1),
485 SOC_DOUBLE("ALC Capture Switch", CS42L52_ALC_CTL, 6, 7, 1, 0),
488 SOC_ENUM("NG Type Switch", ng_type_enum),
489 SOC_SINGLE("NG Enable Switch", CS42L52_NOISE_GATE_CTL, 6, 1, 0),
490 SOC_SINGLE("NG Boost Switch", CS42L52_NOISE_GATE_CTL, 5, 1, 1),
491 SOC_ENUM("NG Threshold", ng_threshold_enum),
492 SOC_ENUM("NG Delay", ng_delay_enum),
494 SOC_DOUBLE("HPF Switch", CS42L52_ANALOG_HPF_CTL, 5, 7, 1, 0),
496 SOC_DOUBLE("Analog SR Switch", CS42L52_ANALOG_HPF_CTL, 1, 3, 1, 1),
497 SOC_DOUBLE("Analog ZC Switch", CS42L52_ANALOG_HPF_CTL, 0, 2, 1, 1),
498 SOC_SINGLE("Digital SR Switch", CS42L52_MISC_CTL, 1, 1, 0),
499 SOC_SINGLE("Digital ZC Switch", CS42L52_MISC_CTL, 0, 1, 0),
500 SOC_SINGLE("Deemphasis Switch", CS42L52_MISC_CTL, 2, 1, 0),
502 SOC_SINGLE("Batt Compensation Switch", CS42L52_BATT_COMPEN, 7, 1, 0),
503 SOC_SINGLE("Batt VP Monitor Switch", CS42L52_BATT_COMPEN, 6, 1, 0),
504 SOC_SINGLE("Batt VP ref", CS42L52_BATT_COMPEN, 0, 0x0f, 0),
506 SOC_SINGLE("PGA AIN1L Switch", CS42L52_ADC_PGA_A, 0, 1, 0),
507 SOC_SINGLE("PGA AIN1R Switch", CS42L52_ADC_PGA_B, 0, 1, 0),
508 SOC_SINGLE("PGA AIN2L Switch", CS42L52_ADC_PGA_A, 1, 1, 0),
509 SOC_SINGLE("PGA AIN2R Switch", CS42L52_ADC_PGA_B, 1, 1, 0),
511 SOC_SINGLE("PGA AIN3L Switch", CS42L52_ADC_PGA_A, 2, 1, 0),
512 SOC_SINGLE("PGA AIN3R Switch", CS42L52_ADC_PGA_B, 2, 1, 0),
514 SOC_SINGLE("PGA AIN4L Switch", CS42L52_ADC_PGA_A, 3, 1, 0),
515 SOC_SINGLE("PGA AIN4R Switch", CS42L52_ADC_PGA_B, 3, 1, 0),
517 SOC_SINGLE("PGA MICA Switch", CS42L52_ADC_PGA_A, 4, 1, 0),
518 SOC_SINGLE("PGA MICB Switch", CS42L52_ADC_PGA_B, 4, 1, 0),
522 static const struct snd_kcontrol_new cs42l52_mica_controls[] = {
523 SOC_ENUM("MICA Select", mica_enum),
526 static const struct snd_kcontrol_new cs42l52_micb_controls[] = {
527 SOC_ENUM("MICB Select", micb_enum),
530 static int cs42l52_add_mic_controls(struct snd_soc_codec *codec)
532 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
533 struct cs42l52_platform_data *pdata = &cs42l52->pdata;
535 if (!pdata->mica_diff_cfg)
536 snd_soc_add_codec_controls(codec, cs42l52_mica_controls,
537 ARRAY_SIZE(cs42l52_mica_controls));
539 if (!pdata->micb_diff_cfg)
540 snd_soc_add_codec_controls(codec, cs42l52_micb_controls,
541 ARRAY_SIZE(cs42l52_micb_controls));
546 static const struct snd_soc_dapm_widget cs42l52_dapm_widgets[] = {
548 SND_SOC_DAPM_INPUT("AIN1L"),
549 SND_SOC_DAPM_INPUT("AIN1R"),
550 SND_SOC_DAPM_INPUT("AIN2L"),
551 SND_SOC_DAPM_INPUT("AIN2R"),
552 SND_SOC_DAPM_INPUT("AIN3L"),
553 SND_SOC_DAPM_INPUT("AIN3R"),
554 SND_SOC_DAPM_INPUT("AIN4L"),
555 SND_SOC_DAPM_INPUT("AIN4R"),
556 SND_SOC_DAPM_INPUT("MICA"),
557 SND_SOC_DAPM_INPUT("MICB"),
558 SND_SOC_DAPM_SIGGEN("Beep"),
560 SND_SOC_DAPM_AIF_OUT("AIFOUTL", NULL, 0,
562 SND_SOC_DAPM_AIF_OUT("AIFOUTR", NULL, 0,
565 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L52_PWRCTL1, 1, 1),
566 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L52_PWRCTL1, 2, 1),
567 SND_SOC_DAPM_PGA("PGA Left", CS42L52_PWRCTL1, 3, 1, NULL, 0),
568 SND_SOC_DAPM_PGA("PGA Right", CS42L52_PWRCTL1, 4, 1, NULL, 0),
570 SND_SOC_DAPM_MUX("ADC Left Mux", SND_SOC_NOPM, 0, 0, &adca_mux),
571 SND_SOC_DAPM_MUX("ADC Right Mux", SND_SOC_NOPM, 0, 0, &adcb_mux),
573 SND_SOC_DAPM_MUX("ADC Left Swap", SND_SOC_NOPM,
575 SND_SOC_DAPM_MUX("ADC Right Swap", SND_SOC_NOPM,
578 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM,
579 0, 0, &digital_output_mux),
581 SND_SOC_DAPM_PGA("PGA MICA", CS42L52_PWRCTL2, 1, 1, NULL, 0),
582 SND_SOC_DAPM_PGA("PGA MICB", CS42L52_PWRCTL2, 2, 1, NULL, 0),
584 SND_SOC_DAPM_SUPPLY("Mic Bias", CS42L52_PWRCTL2, 0, 1, NULL, 0),
585 SND_SOC_DAPM_SUPPLY("Charge Pump", CS42L52_PWRCTL1, 7, 1, NULL, 0),
587 SND_SOC_DAPM_AIF_IN("AIFINL", NULL, 0,
589 SND_SOC_DAPM_AIF_IN("AIFINR", NULL, 0,
592 SND_SOC_DAPM_DAC("DAC Left", NULL, SND_SOC_NOPM, 0, 0),
593 SND_SOC_DAPM_DAC("DAC Right", NULL, SND_SOC_NOPM, 0, 0),
595 SND_SOC_DAPM_SWITCH("Bypass Left", CS42L52_MISC_CTL,
596 6, 0, &passthrul_ctl),
597 SND_SOC_DAPM_SWITCH("Bypass Right", CS42L52_MISC_CTL,
598 7, 0, &passthrur_ctl),
600 SND_SOC_DAPM_MUX("PCM Left Swap", SND_SOC_NOPM,
602 SND_SOC_DAPM_MUX("PCM Right Swap", SND_SOC_NOPM,
605 SND_SOC_DAPM_SWITCH("HP Left Amp", SND_SOC_NOPM, 0, 0, &hpl_ctl),
606 SND_SOC_DAPM_SWITCH("HP Right Amp", SND_SOC_NOPM, 0, 0, &hpr_ctl),
608 SND_SOC_DAPM_SWITCH("SPK Left Amp", SND_SOC_NOPM, 0, 0, &spkl_ctl),
609 SND_SOC_DAPM_SWITCH("SPK Right Amp", SND_SOC_NOPM, 0, 0, &spkr_ctl),
611 SND_SOC_DAPM_OUTPUT("HPOUTA"),
612 SND_SOC_DAPM_OUTPUT("HPOUTB"),
613 SND_SOC_DAPM_OUTPUT("SPKOUTA"),
614 SND_SOC_DAPM_OUTPUT("SPKOUTB"),
618 static const struct snd_soc_dapm_route cs42l52_audio_map[] = {
620 {"Capture", NULL, "AIFOUTL"},
621 {"Capture", NULL, "AIFOUTL"},
623 {"AIFOUTL", NULL, "Output Mux"},
624 {"AIFOUTR", NULL, "Output Mux"},
626 {"Output Mux", "ADC", "ADC Left"},
627 {"Output Mux", "ADC", "ADC Right"},
629 {"ADC Left", NULL, "Charge Pump"},
630 {"ADC Right", NULL, "Charge Pump"},
632 {"Charge Pump", NULL, "ADC Left Mux"},
633 {"Charge Pump", NULL, "ADC Right Mux"},
635 {"ADC Left Mux", "Input1A", "AIN1L"},
636 {"ADC Right Mux", "Input1B", "AIN1R"},
637 {"ADC Left Mux", "Input2A", "AIN2L"},
638 {"ADC Right Mux", "Input2B", "AIN2R"},
639 {"ADC Left Mux", "Input3A", "AIN3L"},
640 {"ADC Right Mux", "Input3B", "AIN3R"},
641 {"ADC Left Mux", "Input4A", "AIN4L"},
642 {"ADC Right Mux", "Input4B", "AIN4R"},
643 {"ADC Left Mux", "PGA Input Left", "PGA Left"},
644 {"ADC Right Mux", "PGA Input Right" , "PGA Right"},
646 {"PGA Left", "Switch", "AIN1L"},
647 {"PGA Right", "Switch", "AIN1R"},
648 {"PGA Left", "Switch", "AIN2L"},
649 {"PGA Right", "Switch", "AIN2R"},
650 {"PGA Left", "Switch", "AIN3L"},
651 {"PGA Right", "Switch", "AIN3R"},
652 {"PGA Left", "Switch", "AIN4L"},
653 {"PGA Right", "Switch", "AIN4R"},
655 {"PGA Left", "Switch", "PGA MICA"},
656 {"PGA MICA", NULL, "MICA"},
658 {"PGA Right", "Switch", "PGA MICB"},
659 {"PGA MICB", NULL, "MICB"},
661 {"HPOUTA", NULL, "HP Left Amp"},
662 {"HPOUTB", NULL, "HP Right Amp"},
663 {"HP Left Amp", NULL, "Bypass Left"},
664 {"HP Right Amp", NULL, "Bypass Right"},
665 {"Bypass Left", "Switch", "PGA Left"},
666 {"Bypass Right", "Switch", "PGA Right"},
667 {"HP Left Amp", "Switch", "DAC Left"},
668 {"HP Right Amp", "Switch", "DAC Right"},
670 {"SPKOUTA", NULL, "SPK Left Amp"},
671 {"SPKOUTB", NULL, "SPK Right Amp"},
673 {"SPK Left Amp", NULL, "Beep"},
674 {"SPK Right Amp", NULL, "Beep"},
675 {"SPK Left Amp", "Switch", "Playback"},
676 {"SPK Right Amp", "Switch", "Playback"},
678 {"DAC Left", NULL, "Beep"},
679 {"DAC Right", NULL, "Beep"},
680 {"DAC Left", NULL, "Playback"},
681 {"DAC Right", NULL, "Playback"},
683 {"Output Mux", "DSP", "Playback"},
684 {"Output Mux", "DSP", "Playback"},
686 {"AIFINL", NULL, "Playback"},
687 {"AIFINR", NULL, "Playback"},
691 struct cs42l52_clk_para {
701 static const struct cs42l52_clk_para clk_map_table[] = {
703 {12288000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
704 {18432000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
705 {12000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
706 {24000000, 8000, CLK_QS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
707 {27000000, 8000, CLK_QS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
710 {11289600, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
711 {16934400, 11025, CLK_QS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
714 {12288000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
715 {18432000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
716 {12000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
717 {24000000, 16000, CLK_HS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
718 {27000000, 16000, CLK_HS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 1},
721 {11289600, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
722 {16934400, 22050, CLK_HS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
725 {12288000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
726 {18432000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_128, 0},
727 {12000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 0},
728 {24000000, 32000, CLK_SS_MODE, CLK_32K, CLK_NO_27M, CLK_R_125, 1},
729 {27000000, 32000, CLK_SS_MODE, CLK_32K, CLK_27M_MCLK, CLK_R_125, 0},
732 {11289600, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
733 {16934400, 44100, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
736 {12288000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
737 {18432000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
738 {12000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
739 {24000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
740 {27000000, 48000, CLK_SS_MODE, CLK_NO_32K, CLK_27M_MCLK, CLK_R_125, 1},
743 {11289600, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
744 {16934400, 88200, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
747 {12288000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
748 {18432000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_128, 0},
749 {12000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 0},
750 {24000000, 96000, CLK_DS_MODE, CLK_NO_32K, CLK_NO_27M, CLK_R_125, 1},
753 static int cs42l52_get_clk(int mclk, int rate)
755 int i, ret = -EINVAL;
756 u_int mclk1, mclk2 = 0;
758 for (i = 0; i < ARRAY_SIZE(clk_map_table); i++) {
759 if (clk_map_table[i].rate == rate) {
760 mclk1 = clk_map_table[i].mclk;
761 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
770 static int cs42l52_set_sysclk(struct snd_soc_dai *codec_dai,
771 int clk_id, unsigned int freq, int dir)
773 struct snd_soc_codec *codec = codec_dai->codec;
774 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
776 if ((freq >= CS42L52_MIN_CLK) && (freq <= CS42L52_MAX_CLK)) {
777 cs42l52->sysclk = freq;
779 dev_err(codec->dev, "Invalid freq parameter\n");
785 static int cs42l52_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
787 struct snd_soc_codec *codec = codec_dai->codec;
788 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
791 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
792 case SND_SOC_DAIFMT_CBM_CFM:
793 iface = CS42L52_IFACE_CTL1_MASTER;
795 case SND_SOC_DAIFMT_CBS_CFS:
796 iface = CS42L52_IFACE_CTL1_SLAVE;
802 /* interface format */
803 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
804 case SND_SOC_DAIFMT_I2S:
805 iface |= CS42L52_IFACE_CTL1_ADC_FMT_I2S |
806 CS42L52_IFACE_CTL1_DAC_FMT_I2S;
808 case SND_SOC_DAIFMT_RIGHT_J:
809 iface |= CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J;
811 case SND_SOC_DAIFMT_LEFT_J:
812 iface |= CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J |
813 CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J;
815 case SND_SOC_DAIFMT_DSP_A:
816 iface |= CS42L52_IFACE_CTL1_DSP_MODE_EN;
818 case SND_SOC_DAIFMT_DSP_B:
824 /* clock inversion */
825 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
826 case SND_SOC_DAIFMT_NB_NF:
828 case SND_SOC_DAIFMT_IB_IF:
829 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
831 case SND_SOC_DAIFMT_IB_NF:
832 iface |= CS42L52_IFACE_CTL1_INV_SCLK;
834 case SND_SOC_DAIFMT_NB_IF:
839 cs42l52->config.format = iface;
840 snd_soc_write(codec, CS42L52_IFACE_CTL1, cs42l52->config.format);
845 static int cs42l52_digital_mute(struct snd_soc_dai *dai, int mute)
847 struct snd_soc_codec *codec = dai->codec;
850 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
851 CS42L52_PB_CTL1_MUTE_MASK,
852 CS42L52_PB_CTL1_MUTE);
854 snd_soc_update_bits(codec, CS42L52_PB_CTL1,
855 CS42L52_PB_CTL1_MUTE_MASK,
856 CS42L52_PB_CTL1_UNMUTE);
861 static int cs42l52_pcm_hw_params(struct snd_pcm_substream *substream,
862 struct snd_pcm_hw_params *params,
863 struct snd_soc_dai *dai)
865 struct snd_soc_codec *codec = dai->codec;
866 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
870 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
872 cs42l52->sysclk = clk_map_table[index].mclk;
874 clk |= (clk_map_table[index].speed << CLK_SPEED_SHIFT) |
875 (clk_map_table[index].group << CLK_32K_SR_SHIFT) |
876 (clk_map_table[index].videoclk << CLK_27M_MCLK_SHIFT) |
877 (clk_map_table[index].ratio << CLK_RATIO_SHIFT) |
878 clk_map_table[index].mclkdiv2;
880 snd_soc_write(codec, CS42L52_CLK_CTL, clk);
882 dev_err(codec->dev, "can't get correct mclk\n");
889 static int cs42l52_set_bias_level(struct snd_soc_codec *codec,
890 enum snd_soc_bias_level level)
892 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
895 case SND_SOC_BIAS_ON:
897 case SND_SOC_BIAS_PREPARE:
898 snd_soc_update_bits(codec, CS42L52_PWRCTL1,
899 CS42L52_PWRCTL1_PDN_CODEC, 0);
901 case SND_SOC_BIAS_STANDBY:
902 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
903 regcache_cache_only(cs42l52->regmap, false);
904 regcache_sync(cs42l52->regmap);
906 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
908 case SND_SOC_BIAS_OFF:
909 snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL);
910 regcache_cache_only(cs42l52->regmap, true);
913 codec->dapm.bias_level = level;
918 #define CS42L52_RATES (SNDRV_PCM_RATE_8000_96000)
920 #define CS42L52_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE | \
921 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_U18_3LE | \
922 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_U20_3LE | \
923 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_U24_LE)
925 static struct snd_soc_dai_ops cs42l52_ops = {
926 .hw_params = cs42l52_pcm_hw_params,
927 .digital_mute = cs42l52_digital_mute,
928 .set_fmt = cs42l52_set_fmt,
929 .set_sysclk = cs42l52_set_sysclk,
932 static struct snd_soc_dai_driver cs42l52_dai = {
935 .stream_name = "Playback",
938 .rates = CS42L52_RATES,
939 .formats = CS42L52_FORMATS,
942 .stream_name = "Capture",
945 .rates = CS42L52_RATES,
946 .formats = CS42L52_FORMATS,
951 static int cs42l52_suspend(struct snd_soc_codec *codec)
953 cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
958 static int cs42l52_resume(struct snd_soc_codec *codec)
960 cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
965 #if IS_ENABLED(CONFIG_INPUT)
966 static int beep_rates[] = {
967 261, 522, 585, 667, 706, 774, 889, 1000,
968 1043, 1200, 1333, 1412, 1600, 1714, 2000, 2182
971 static void cs42l52_beep_work(struct work_struct *work)
973 struct cs42l52_private *cs42l52 =
974 container_of(work, struct cs42l52_private, beep_work);
975 struct snd_soc_codec *codec = cs42l52->codec;
976 struct snd_soc_dapm_context *dapm = &codec->dapm;
981 if (cs42l52->beep_rate) {
982 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
983 if (abs(cs42l52->beep_rate - beep_rates[i]) <
984 abs(cs42l52->beep_rate - beep_rates[best]))
988 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
989 beep_rates[best], cs42l52->beep_rate);
991 val = (best << CS42L52_BEEP_RATE_SHIFT);
993 snd_soc_dapm_enable_pin(dapm, "Beep");
995 dev_dbg(codec->dev, "Disabling beep\n");
996 snd_soc_dapm_disable_pin(dapm, "Beep");
999 snd_soc_update_bits(codec, CS42L52_BEEP_FREQ,
1000 CS42L52_BEEP_RATE_MASK, val);
1002 snd_soc_dapm_sync(dapm);
1005 /* For usability define a way of injecting beep events for the device -
1006 * many systems will not have a keyboard.
1008 static int cs42l52_beep_event(struct input_dev *dev, unsigned int type,
1009 unsigned int code, int hz)
1011 struct snd_soc_codec *codec = input_get_drvdata(dev);
1012 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1014 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1026 /* Kick the beep from a workqueue */
1027 cs42l52->beep_rate = hz;
1028 schedule_work(&cs42l52->beep_work);
1032 static ssize_t cs42l52_beep_set(struct device *dev,
1033 struct device_attribute *attr,
1034 const char *buf, size_t count)
1036 struct cs42l52_private *cs42l52 = dev_get_drvdata(dev);
1040 ret = kstrtol(buf, 10, &time);
1044 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
1049 static DEVICE_ATTR(beep, 0200, NULL, cs42l52_beep_set);
1051 static void cs42l52_init_beep(struct snd_soc_codec *codec)
1053 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1056 cs42l52->beep = devm_input_allocate_device(codec->dev);
1057 if (!cs42l52->beep) {
1058 dev_err(codec->dev, "Failed to allocate beep device\n");
1062 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
1063 cs42l52->beep_rate = 0;
1065 cs42l52->beep->name = "CS42L52 Beep Generator";
1066 cs42l52->beep->phys = dev_name(codec->dev);
1067 cs42l52->beep->id.bustype = BUS_I2C;
1069 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1070 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1071 cs42l52->beep->event = cs42l52_beep_event;
1072 cs42l52->beep->dev.parent = codec->dev;
1073 input_set_drvdata(cs42l52->beep, codec);
1075 ret = input_register_device(cs42l52->beep);
1077 cs42l52->beep = NULL;
1078 dev_err(codec->dev, "Failed to register beep device\n");
1081 ret = device_create_file(codec->dev, &dev_attr_beep);
1083 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1088 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1090 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1092 device_remove_file(codec->dev, &dev_attr_beep);
1093 cancel_work_sync(&cs42l52->beep_work);
1094 cs42l52->beep = NULL;
1096 snd_soc_update_bits(codec, CS42L52_BEEP_TONE_CTL,
1097 CS42L52_BEEP_EN_MASK, 0);
1100 static void cs42l52_init_beep(struct snd_soc_codec *codec)
1104 static void cs42l52_free_beep(struct snd_soc_codec *codec)
1109 static int cs42l52_probe(struct snd_soc_codec *codec)
1111 struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec);
1113 regcache_cache_only(cs42l52->regmap, true);
1115 cs42l52_add_mic_controls(codec);
1117 cs42l52_init_beep(codec);
1119 cs42l52_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1121 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1122 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1127 static int cs42l52_remove(struct snd_soc_codec *codec)
1129 cs42l52_free_beep(codec);
1130 cs42l52_set_bias_level(codec, SND_SOC_BIAS_OFF);
1135 static struct snd_soc_codec_driver soc_codec_dev_cs42l52 = {
1136 .probe = cs42l52_probe,
1137 .remove = cs42l52_remove,
1138 .suspend = cs42l52_suspend,
1139 .resume = cs42l52_resume,
1140 .set_bias_level = cs42l52_set_bias_level,
1142 .dapm_widgets = cs42l52_dapm_widgets,
1143 .num_dapm_widgets = ARRAY_SIZE(cs42l52_dapm_widgets),
1144 .dapm_routes = cs42l52_audio_map,
1145 .num_dapm_routes = ARRAY_SIZE(cs42l52_audio_map),
1147 .controls = cs42l52_snd_controls,
1148 .num_controls = ARRAY_SIZE(cs42l52_snd_controls),
1151 /* Current and threshold powerup sequence Pg37 */
1152 static const struct reg_default cs42l52_threshold_patch[] = {
1163 static struct regmap_config cs42l52_regmap = {
1167 .max_register = CS42L52_MAX_REGISTER,
1168 .reg_defaults = cs42l52_reg_defaults,
1169 .num_reg_defaults = ARRAY_SIZE(cs42l52_reg_defaults),
1170 .readable_reg = cs42l52_readable_register,
1171 .volatile_reg = cs42l52_volatile_register,
1172 .cache_type = REGCACHE_RBTREE,
1175 static int cs42l52_i2c_probe(struct i2c_client *i2c_client,
1176 const struct i2c_device_id *id)
1178 struct cs42l52_private *cs42l52;
1179 struct cs42l52_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1181 unsigned int devid = 0;
1185 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l52_private),
1187 if (cs42l52 == NULL)
1189 cs42l52->dev = &i2c_client->dev;
1191 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
1192 if (IS_ERR(cs42l52->regmap)) {
1193 ret = PTR_ERR(cs42l52->regmap);
1194 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1198 cs42l52->pdata = *pdata;
1200 pdata = devm_kzalloc(&i2c_client->dev,
1201 sizeof(struct cs42l52_platform_data),
1204 dev_err(&i2c_client->dev, "could not allocate pdata\n");
1207 if (i2c_client->dev.of_node) {
1208 if (of_property_read_bool(i2c_client->dev.of_node,
1209 "cirrus,mica-differential-cfg"))
1210 pdata->mica_diff_cfg = true;
1212 if (of_property_read_bool(i2c_client->dev.of_node,
1213 "cirrus,micb-differential-cfg"))
1214 pdata->micb_diff_cfg = true;
1216 if (of_property_read_u32(i2c_client->dev.of_node,
1217 "cirrus,micbias-lvl", &val32) >= 0)
1218 pdata->micbias_lvl = val32;
1220 if (of_property_read_u32(i2c_client->dev.of_node,
1221 "cirrus,chgfreq-divisor", &val32) >= 0)
1222 pdata->chgfreq = val32;
1225 of_get_named_gpio(i2c_client->dev.of_node,
1226 "cirrus,reset-gpio", 0);
1228 cs42l52->pdata = *pdata;
1231 if (cs42l52->pdata.reset_gpio) {
1232 ret = gpio_request_one(cs42l52->pdata.reset_gpio,
1233 GPIOF_OUT_INIT_HIGH, "CS42L52 /RST");
1235 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1236 cs42l52->pdata.reset_gpio, ret);
1239 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1240 gpio_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1243 i2c_set_clientdata(i2c_client, cs42l52);
1245 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1246 ARRAY_SIZE(cs42l52_threshold_patch));
1248 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1251 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, ®);
1252 devid = reg & CS42L52_CHIP_ID_MASK;
1253 if (devid != CS42L52_CHIP_ID) {
1255 dev_err(&i2c_client->dev,
1256 "CS42L52 Device ID (%X). Expected %X\n",
1257 devid, CS42L52_CHIP_ID);
1261 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1262 reg & CS42L52_CHIP_REV_MASK);
1264 /* Set Platform Data */
1265 if (cs42l52->pdata.mica_diff_cfg)
1266 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1267 CS42L52_MIC_CTL_TYPE_MASK,
1268 cs42l52->pdata.mica_diff_cfg <<
1269 CS42L52_MIC_CTL_TYPE_SHIFT);
1271 if (cs42l52->pdata.micb_diff_cfg)
1272 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1273 CS42L52_MIC_CTL_TYPE_MASK,
1274 cs42l52->pdata.micb_diff_cfg <<
1275 CS42L52_MIC_CTL_TYPE_SHIFT);
1277 if (cs42l52->pdata.chgfreq)
1278 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1279 CS42L52_CHARGE_PUMP_MASK,
1280 cs42l52->pdata.chgfreq <<
1281 CS42L52_CHARGE_PUMP_SHIFT);
1283 if (cs42l52->pdata.micbias_lvl)
1284 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1285 CS42L52_IFACE_CTL2_BIAS_LVL,
1286 cs42l52->pdata.micbias_lvl);
1288 ret = snd_soc_register_codec(&i2c_client->dev,
1289 &soc_codec_dev_cs42l52, &cs42l52_dai, 1);
1295 static int cs42l52_i2c_remove(struct i2c_client *client)
1297 snd_soc_unregister_codec(&client->dev);
1301 static const struct of_device_id cs42l52_of_match[] = {
1302 { .compatible = "cirrus,cs42l52", },
1305 MODULE_DEVICE_TABLE(of, cs42l52_of_match);
1308 static const struct i2c_device_id cs42l52_id[] = {
1312 MODULE_DEVICE_TABLE(i2c, cs42l52_id);
1314 static struct i2c_driver cs42l52_i2c_driver = {
1317 .owner = THIS_MODULE,
1318 .of_match_table = cs42l52_of_match,
1320 .id_table = cs42l52_id,
1321 .probe = cs42l52_i2c_probe,
1322 .remove = cs42l52_i2c_remove,
1325 module_i2c_driver(cs42l52_i2c_driver);
1327 MODULE_DESCRIPTION("ASoC CS42L52 driver");
1328 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1329 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1330 MODULE_LICENSE("GPL");