2 * cs42l73.c -- CS42L73 ALSA Soc Audio driver
4 * Copyright 2011 Cirrus Logic, Inc.
6 * Authors: Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>
7 * Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/of_gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <sound/cs42l73.h>
39 struct cs42l73_private {
40 struct cs42l73_platform_data pdata;
41 struct sp_config config[3];
42 struct regmap *regmap;
49 static const struct reg_default cs42l73_reg_defaults[] = {
50 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
51 { 7, 0xDF }, /* r07 - Power Ctl 2 */
52 { 8, 0x3F }, /* r08 - Power Ctl 3 */
53 { 9, 0x50 }, /* r09 - Charge Pump Freq */
54 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
55 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
56 { 12, 0x00 }, /* r0C - Aux PCM Ctl */
57 { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */
58 { 14, 0x00 }, /* r0E - Audio PCM Ctl */
59 { 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */
60 { 16, 0x00 }, /* r10 - Voice PCM Ctl */
61 { 17, 0x15 }, /* r11 - Voice PCM Master Clock Ctl */
62 { 18, 0x00 }, /* r12 - Voice/Aux Sample Rate */
63 { 19, 0x06 }, /* r13 - Misc I/O Path Ctl */
64 { 20, 0x00 }, /* r14 - ADC Input Path Ctl */
65 { 21, 0x00 }, /* r15 - MICA Preamp, PGA Volume */
66 { 22, 0x00 }, /* r16 - MICB Preamp, PGA Volume */
67 { 23, 0x00 }, /* r17 - Input Path A Digital Volume */
68 { 24, 0x00 }, /* r18 - Input Path B Digital Volume */
69 { 25, 0x00 }, /* r19 - Playback Digital Ctl */
70 { 26, 0x00 }, /* r1A - HP/LO Left Digital Volume */
71 { 27, 0x00 }, /* r1B - HP/LO Right Digital Volume */
72 { 28, 0x00 }, /* r1C - Speakerphone Digital Volume */
73 { 29, 0x00 }, /* r1D - Ear/SPKLO Digital Volume */
74 { 30, 0x00 }, /* r1E - HP Left Analog Volume */
75 { 31, 0x00 }, /* r1F - HP Right Analog Volume */
76 { 32, 0x00 }, /* r20 - LO Left Analog Volume */
77 { 33, 0x00 }, /* r21 - LO Right Analog Volume */
78 { 34, 0x00 }, /* r22 - Stereo Input Path Advisory Volume */
79 { 35, 0x00 }, /* r23 - Aux PCM Input Advisory Volume */
80 { 36, 0x00 }, /* r24 - Audio PCM Input Advisory Volume */
81 { 37, 0x00 }, /* r25 - Voice PCM Input Advisory Volume */
82 { 38, 0x00 }, /* r26 - Limiter Attack Rate HP/LO */
83 { 39, 0x7F }, /* r27 - Limter Ctl, Release Rate HP/LO */
84 { 40, 0x00 }, /* r28 - Limter Threshold HP/LO */
85 { 41, 0x00 }, /* r29 - Limiter Attack Rate Speakerphone */
86 { 42, 0x3F }, /* r2A - Limter Ctl, Release Rate Speakerphone */
87 { 43, 0x00 }, /* r2B - Limter Threshold Speakerphone */
88 { 44, 0x00 }, /* r2C - Limiter Attack Rate Ear/SPKLO */
89 { 45, 0x3F }, /* r2D - Limter Ctl, Release Rate Ear/SPKLO */
90 { 46, 0x00 }, /* r2E - Limter Threshold Ear/SPKLO */
91 { 47, 0x00 }, /* r2F - ALC Enable, Attack Rate Left/Right */
92 { 48, 0x3F }, /* r30 - ALC Release Rate Left/Right */
93 { 49, 0x00 }, /* r31 - ALC Threshold Left/Right */
94 { 50, 0x00 }, /* r32 - Noise Gate Ctl Left/Right */
95 { 51, 0x00 }, /* r33 - ALC/NG Misc Ctl */
96 { 52, 0x18 }, /* r34 - Mixer Ctl */
97 { 53, 0x3F }, /* r35 - HP/LO Left Mixer Input Path Volume */
98 { 54, 0x3F }, /* r36 - HP/LO Right Mixer Input Path Volume */
99 { 55, 0x3F }, /* r37 - HP/LO Left Mixer Aux PCM Volume */
100 { 56, 0x3F }, /* r38 - HP/LO Right Mixer Aux PCM Volume */
101 { 57, 0x3F }, /* r39 - HP/LO Left Mixer Audio PCM Volume */
102 { 58, 0x3F }, /* r3A - HP/LO Right Mixer Audio PCM Volume */
103 { 59, 0x3F }, /* r3B - HP/LO Left Mixer Voice PCM Mono Volume */
104 { 60, 0x3F }, /* r3C - HP/LO Right Mixer Voice PCM Mono Volume */
105 { 61, 0x3F }, /* r3D - Aux PCM Left Mixer Input Path Volume */
106 { 62, 0x3F }, /* r3E - Aux PCM Right Mixer Input Path Volume */
107 { 63, 0x3F }, /* r3F - Aux PCM Left Mixer Volume */
108 { 64, 0x3F }, /* r40 - Aux PCM Left Mixer Volume */
109 { 65, 0x3F }, /* r41 - Aux PCM Left Mixer Audio PCM L Volume */
110 { 66, 0x3F }, /* r42 - Aux PCM Right Mixer Audio PCM R Volume */
111 { 67, 0x3F }, /* r43 - Aux PCM Left Mixer Voice PCM Volume */
112 { 68, 0x3F }, /* r44 - Aux PCM Right Mixer Voice PCM Volume */
113 { 69, 0x3F }, /* r45 - Audio PCM Left Input Path Volume */
114 { 70, 0x3F }, /* r46 - Audio PCM Right Input Path Volume */
115 { 71, 0x3F }, /* r47 - Audio PCM Left Mixer Aux PCM L Volume */
116 { 72, 0x3F }, /* r48 - Audio PCM Right Mixer Aux PCM R Volume */
117 { 73, 0x3F }, /* r49 - Audio PCM Left Mixer Volume */
118 { 74, 0x3F }, /* r4A - Audio PCM Right Mixer Volume */
119 { 75, 0x3F }, /* r4B - Audio PCM Left Mixer Voice PCM Volume */
120 { 76, 0x3F }, /* r4C - Audio PCM Right Mixer Voice PCM Volume */
121 { 77, 0x3F }, /* r4D - Voice PCM Left Input Path Volume */
122 { 78, 0x3F }, /* r4E - Voice PCM Right Input Path Volume */
123 { 79, 0x3F }, /* r4F - Voice PCM Left Mixer Aux PCM L Volume */
124 { 80, 0x3F }, /* r50 - Voice PCM Right Mixer Aux PCM R Volume */
125 { 81, 0x3F }, /* r51 - Voice PCM Left Mixer Audio PCM L Volume */
126 { 82, 0x3F }, /* r52 - Voice PCM Right Mixer Audio PCM R Volume */
127 { 83, 0x3F }, /* r53 - Voice PCM Left Mixer Voice PCM Volume */
128 { 84, 0x3F }, /* r54 - Voice PCM Right Mixer Voice PCM Volume */
129 { 85, 0xAA }, /* r55 - Mono Mixer Ctl */
130 { 86, 0x3F }, /* r56 - SPK Mono Mixer Input Path Volume */
131 { 87, 0x3F }, /* r57 - SPK Mono Mixer Aux PCM Mono/L/R Volume */
132 { 88, 0x3F }, /* r58 - SPK Mono Mixer Audio PCM Mono/L/R Volume */
133 { 89, 0x3F }, /* r59 - SPK Mono Mixer Voice PCM Mono Volume */
134 { 90, 0x3F }, /* r5A - SPKLO Mono Mixer Input Path Mono Volume */
135 { 91, 0x3F }, /* r5B - SPKLO Mono Mixer Aux Mono/L/R Volume */
136 { 92, 0x3F }, /* r5C - SPKLO Mono Mixer Audio Mono/L/R Volume */
137 { 93, 0x3F }, /* r5D - SPKLO Mono Mixer Voice Mono Volume */
138 { 94, 0x00 }, /* r5E - Interrupt Mask 1 */
139 { 95, 0x00 }, /* r5F - Interrupt Mask 2 */
142 static bool cs42l73_volatile_register(struct device *dev, unsigned int reg)
153 static bool cs42l73_readable_register(struct device *dev, unsigned int reg)
156 case CS42L73_DEVID_AB ... CS42L73_DEVID_E:
157 case CS42L73_REVID ... CS42L73_IM2:
164 static const unsigned int hpaloa_tlv[] = {
165 TLV_DB_RANGE_HEAD(2),
166 0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0),
167 14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0),
170 static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0);
172 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
174 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
176 static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0);
178 static const unsigned int limiter_tlv[] = {
179 TLV_DB_RANGE_HEAD(2),
180 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
181 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0),
184 static const DECLARE_TLV_DB_SCALE(attn_tlv, -6300, 100, 1);
186 static const char * const cs42l73_pgaa_text[] = { "Line A", "Mic 1" };
187 static const char * const cs42l73_pgab_text[] = { "Line B", "Mic 2" };
189 static SOC_ENUM_SINGLE_DECL(pgaa_enum,
193 static SOC_ENUM_SINGLE_DECL(pgab_enum,
197 static const struct snd_kcontrol_new pgaa_mux =
198 SOC_DAPM_ENUM("Left Analog Input Capture Mux", pgaa_enum);
200 static const struct snd_kcontrol_new pgab_mux =
201 SOC_DAPM_ENUM("Right Analog Input Capture Mux", pgab_enum);
203 static const struct snd_kcontrol_new input_left_mixer[] = {
204 SOC_DAPM_SINGLE("ADC Left Input", CS42L73_PWRCTL1,
206 SOC_DAPM_SINGLE("DMIC Left Input", CS42L73_PWRCTL1,
210 static const struct snd_kcontrol_new input_right_mixer[] = {
211 SOC_DAPM_SINGLE("ADC Right Input", CS42L73_PWRCTL1,
213 SOC_DAPM_SINGLE("DMIC Right Input", CS42L73_PWRCTL1,
217 static const char * const cs42l73_ng_delay_text[] = {
218 "50ms", "100ms", "150ms", "200ms" };
220 static SOC_ENUM_SINGLE_DECL(ng_delay_enum,
222 cs42l73_ng_delay_text);
224 static const char * const cs42l73_mono_mix_texts[] = {
225 "Left", "Right", "Mono Mix"};
227 static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 };
229 static const struct soc_enum spk_asp_enum =
230 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 3,
231 ARRAY_SIZE(cs42l73_mono_mix_texts),
232 cs42l73_mono_mix_texts,
233 cs42l73_mono_mix_values);
235 static const struct snd_kcontrol_new spk_asp_mixer =
236 SOC_DAPM_ENUM("Route", spk_asp_enum);
238 static const struct soc_enum spk_xsp_enum =
239 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 4, 3,
240 ARRAY_SIZE(cs42l73_mono_mix_texts),
241 cs42l73_mono_mix_texts,
242 cs42l73_mono_mix_values);
244 static const struct snd_kcontrol_new spk_xsp_mixer =
245 SOC_DAPM_ENUM("Route", spk_xsp_enum);
247 static const struct soc_enum esl_asp_enum =
248 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 3,
249 ARRAY_SIZE(cs42l73_mono_mix_texts),
250 cs42l73_mono_mix_texts,
251 cs42l73_mono_mix_values);
253 static const struct snd_kcontrol_new esl_asp_mixer =
254 SOC_DAPM_ENUM("Route", esl_asp_enum);
256 static const struct soc_enum esl_xsp_enum =
257 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 3,
258 ARRAY_SIZE(cs42l73_mono_mix_texts),
259 cs42l73_mono_mix_texts,
260 cs42l73_mono_mix_values);
262 static const struct snd_kcontrol_new esl_xsp_mixer =
263 SOC_DAPM_ENUM("Route", esl_xsp_enum);
265 static const char * const cs42l73_ip_swap_text[] = {
266 "Stereo", "Mono A", "Mono B", "Swap A-B"};
268 static SOC_ENUM_SINGLE_DECL(ip_swap_enum,
270 cs42l73_ip_swap_text);
272 static const char * const cs42l73_spo_mixer_text[] = {"Mono", "Stereo"};
274 static SOC_ENUM_SINGLE_DECL(vsp_output_mux_enum,
276 cs42l73_spo_mixer_text);
278 static SOC_ENUM_SINGLE_DECL(xsp_output_mux_enum,
280 cs42l73_spo_mixer_text);
282 static const struct snd_kcontrol_new vsp_output_mux =
283 SOC_DAPM_ENUM("Route", vsp_output_mux_enum);
285 static const struct snd_kcontrol_new xsp_output_mux =
286 SOC_DAPM_ENUM("Route", xsp_output_mux_enum);
288 static const struct snd_kcontrol_new hp_amp_ctl =
289 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1);
291 static const struct snd_kcontrol_new lo_amp_ctl =
292 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 1, 1, 1);
294 static const struct snd_kcontrol_new spk_amp_ctl =
295 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 2, 1, 1);
297 static const struct snd_kcontrol_new spklo_amp_ctl =
298 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 4, 1, 1);
300 static const struct snd_kcontrol_new ear_amp_ctl =
301 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 3, 1, 1);
303 static const struct snd_kcontrol_new cs42l73_snd_controls[] = {
304 SOC_DOUBLE_R_SX_TLV("Headphone Analog Playback Volume",
305 CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0,
306 0x41, 0x4B, hpaloa_tlv),
308 SOC_DOUBLE_R_SX_TLV("LineOut Analog Playback Volume", CS42L73_LOAAVOL,
309 CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv),
311 SOC_DOUBLE_R_SX_TLV("Input PGA Analog Volume", CS42L73_MICAPREPGAAVOL,
312 CS42L73_MICBPREPGABVOL, 0, 0x34,
315 SOC_DOUBLE_R("MIC Preamp Switch", CS42L73_MICAPREPGAAVOL,
316 CS42L73_MICBPREPGABVOL, 6, 1, 1),
318 SOC_DOUBLE_R_SX_TLV("Input Path Digital Volume", CS42L73_IPADVOL,
319 CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv),
321 SOC_DOUBLE_R_SX_TLV("HL Digital Playback Volume",
322 CS42L73_HLADVOL, CS42L73_HLBDVOL,
323 0, 0x34, 0xE4, hl_tlv),
325 SOC_SINGLE_TLV("ADC A Boost Volume",
326 CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv),
328 SOC_SINGLE_TLV("ADC B Boost Volume",
329 CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv),
331 SOC_SINGLE_SX_TLV("Speakerphone Digital Volume",
332 CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv),
334 SOC_SINGLE_SX_TLV("Ear Speaker Digital Volume",
335 CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv),
337 SOC_DOUBLE_R("Headphone Analog Playback Switch", CS42L73_HPAAVOL,
338 CS42L73_HPBAVOL, 7, 1, 1),
340 SOC_DOUBLE_R("LineOut Analog Playback Switch", CS42L73_LOAAVOL,
341 CS42L73_LOBAVOL, 7, 1, 1),
342 SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1),
343 SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0,
345 SOC_SINGLE("Speakerphone Digital Playback Switch", CS42L73_PBDC, 2, 1,
347 SOC_SINGLE("Ear Speaker Digital Playback Switch", CS42L73_PBDC, 3, 1,
350 SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0),
351 SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0),
352 SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0),
353 SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0),
355 SOC_DOUBLE("ADC Signal Polarity Switch", CS42L73_ADCIPC, 1, 5, 1,
358 SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F,
360 SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0,
364 SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0),
365 SOC_SINGLE("HL Limiter All Channels Switch", CS42L73_LIMRRATEHL, 6, 1,
368 SOC_SINGLE_TLV("HL Limiter Max Threshold Volume", CS42L73_LMAXHL, 5, 7,
371 SOC_SINGLE_TLV("HL Limiter Cushion Volume", CS42L73_LMAXHL, 2, 7, 1,
374 SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0,
376 SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0,
378 SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0),
379 SOC_SINGLE("SPK Limiter All Channels Switch", CS42L73_LIMRRATESPK,
381 SOC_SINGLE_TLV("SPK Limiter Max Threshold Volume", CS42L73_LMAXSPK, 5,
384 SOC_SINGLE_TLV("SPK Limiter Cushion Volume", CS42L73_LMAXSPK, 2, 7, 1,
387 SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0,
389 SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0,
391 SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0),
392 SOC_SINGLE_TLV("ESL Limiter Max Threshold Volume", CS42L73_LMAXESL, 5,
395 SOC_SINGLE_TLV("ESL Limiter Cushion Volume", CS42L73_LMAXESL, 2, 7, 1,
398 SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0),
399 SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0),
400 SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0),
401 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0,
403 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0,
406 SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0),
407 SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0),
409 NG Threshold depends on NG_BOOTSAB, which selects
410 between two threshold scales in decibels.
411 Set linear values for now ..
413 SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
414 SOC_ENUM("NG Delay", ng_delay_enum),
416 SOC_DOUBLE_R_TLV("XSP-IP Volume",
417 CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
419 SOC_DOUBLE_R_TLV("XSP-XSP Volume",
420 CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1,
422 SOC_DOUBLE_R_TLV("XSP-ASP Volume",
423 CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1,
425 SOC_DOUBLE_R_TLV("XSP-VSP Volume",
426 CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1,
429 SOC_DOUBLE_R_TLV("ASP-IP Volume",
430 CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1,
432 SOC_DOUBLE_R_TLV("ASP-XSP Volume",
433 CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1,
435 SOC_DOUBLE_R_TLV("ASP-ASP Volume",
436 CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1,
438 SOC_DOUBLE_R_TLV("ASP-VSP Volume",
439 CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1,
442 SOC_DOUBLE_R_TLV("VSP-IP Volume",
443 CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1,
445 SOC_DOUBLE_R_TLV("VSP-XSP Volume",
446 CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1,
448 SOC_DOUBLE_R_TLV("VSP-ASP Volume",
449 CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1,
451 SOC_DOUBLE_R_TLV("VSP-VSP Volume",
452 CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1,
455 SOC_DOUBLE_R_TLV("HL-IP Volume",
456 CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1,
458 SOC_DOUBLE_R_TLV("HL-XSP Volume",
459 CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1,
461 SOC_DOUBLE_R_TLV("HL-ASP Volume",
462 CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1,
464 SOC_DOUBLE_R_TLV("HL-VSP Volume",
465 CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1,
468 SOC_SINGLE_TLV("SPK-IP Mono Volume",
469 CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv),
470 SOC_SINGLE_TLV("SPK-XSP Mono Volume",
471 CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv),
472 SOC_SINGLE_TLV("SPK-ASP Mono Volume",
473 CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv),
474 SOC_SINGLE_TLV("SPK-VSP Mono Volume",
475 CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv),
477 SOC_SINGLE_TLV("ESL-IP Mono Volume",
478 CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv),
479 SOC_SINGLE_TLV("ESL-XSP Mono Volume",
480 CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv),
481 SOC_SINGLE_TLV("ESL-ASP Mono Volume",
482 CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv),
483 SOC_SINGLE_TLV("ESL-VSP Mono Volume",
484 CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv),
486 SOC_ENUM("IP Digital Swap/Mono Select", ip_swap_enum),
488 SOC_ENUM("VSPOUT Mono/Stereo Select", vsp_output_mux_enum),
489 SOC_ENUM("XSPOUT Mono/Stereo Select", xsp_output_mux_enum),
492 static int cs42l73_spklo_spk_amp_event(struct snd_soc_dapm_widget *w,
493 struct snd_kcontrol *kcontrol, int event)
495 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
496 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
498 case SND_SOC_DAPM_POST_PMD:
499 /* 150 ms delay between setting PDN and MCLKDIS */
500 priv->shutdwn_delay = 150;
503 pr_err("Invalid event = 0x%x\n", event);
508 static int cs42l73_ear_amp_event(struct snd_soc_dapm_widget *w,
509 struct snd_kcontrol *kcontrol, int event)
511 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
512 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
514 case SND_SOC_DAPM_POST_PMD:
515 /* 50 ms delay between setting PDN and MCLKDIS */
516 if (priv->shutdwn_delay < 50)
517 priv->shutdwn_delay = 50;
520 pr_err("Invalid event = 0x%x\n", event);
526 static int cs42l73_hp_amp_event(struct snd_soc_dapm_widget *w,
527 struct snd_kcontrol *kcontrol, int event)
529 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
530 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
532 case SND_SOC_DAPM_POST_PMD:
533 /* 30 ms delay between setting PDN and MCLKDIS */
534 if (priv->shutdwn_delay < 30)
535 priv->shutdwn_delay = 30;
538 pr_err("Invalid event = 0x%x\n", event);
543 static const struct snd_soc_dapm_widget cs42l73_dapm_widgets[] = {
544 SND_SOC_DAPM_INPUT("DMICA"),
545 SND_SOC_DAPM_INPUT("DMICB"),
546 SND_SOC_DAPM_INPUT("LINEINA"),
547 SND_SOC_DAPM_INPUT("LINEINB"),
548 SND_SOC_DAPM_INPUT("MIC1"),
549 SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0),
550 SND_SOC_DAPM_INPUT("MIC2"),
551 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0),
553 SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0,
554 CS42L73_PWRCTL2, 1, 1),
555 SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0,
556 CS42L73_PWRCTL2, 1, 1),
557 SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0,
558 CS42L73_PWRCTL2, 3, 1),
559 SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0,
560 CS42L73_PWRCTL2, 3, 1),
561 SND_SOC_DAPM_AIF_OUT("VSPINOUT", NULL, 0,
562 CS42L73_PWRCTL2, 4, 1),
564 SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0),
565 SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0),
567 SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux),
568 SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux),
570 SND_SOC_DAPM_ADC("ADC Left", NULL, CS42L73_PWRCTL1, 7, 1),
571 SND_SOC_DAPM_ADC("ADC Right", NULL, CS42L73_PWRCTL1, 5, 1),
572 SND_SOC_DAPM_ADC("DMIC Left", NULL, CS42L73_PWRCTL1, 6, 1),
573 SND_SOC_DAPM_ADC("DMIC Right", NULL, CS42L73_PWRCTL1, 4, 1),
575 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Left Capture", SND_SOC_NOPM,
576 0, 0, input_left_mixer,
577 ARRAY_SIZE(input_left_mixer)),
579 SND_SOC_DAPM_MIXER_NAMED_CTL("Input Right Capture", SND_SOC_NOPM,
580 0, 0, input_right_mixer,
581 ARRAY_SIZE(input_right_mixer)),
583 SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
584 SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
585 SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
586 SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
587 SND_SOC_DAPM_MIXER("VSP Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
589 SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0,
590 CS42L73_PWRCTL2, 0, 1),
591 SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0,
592 CS42L73_PWRCTL2, 0, 1),
593 SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0,
594 CS42L73_PWRCTL2, 0, 1),
596 SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0,
597 CS42L73_PWRCTL2, 2, 1),
598 SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0,
599 CS42L73_PWRCTL2, 2, 1),
600 SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0,
601 CS42L73_PWRCTL2, 2, 1),
603 SND_SOC_DAPM_AIF_IN("VSPINOUT", NULL, 0,
604 CS42L73_PWRCTL2, 4, 1),
606 SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
607 SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
608 SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
609 SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
611 SND_SOC_DAPM_MUX("ESL-XSP Mux", SND_SOC_NOPM,
612 0, 0, &esl_xsp_mixer),
614 SND_SOC_DAPM_MUX("ESL-ASP Mux", SND_SOC_NOPM,
615 0, 0, &esl_asp_mixer),
617 SND_SOC_DAPM_MUX("SPK-ASP Mux", SND_SOC_NOPM,
618 0, 0, &spk_asp_mixer),
620 SND_SOC_DAPM_MUX("SPK-XSP Mux", SND_SOC_NOPM,
621 0, 0, &spk_xsp_mixer),
623 SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
624 SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
625 SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
626 SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
628 SND_SOC_DAPM_SWITCH_E("HP Amp", CS42L73_PWRCTL3, 0, 1,
629 &hp_amp_ctl, cs42l73_hp_amp_event,
630 SND_SOC_DAPM_POST_PMD),
631 SND_SOC_DAPM_SWITCH("LO Amp", CS42L73_PWRCTL3, 1, 1,
633 SND_SOC_DAPM_SWITCH_E("SPK Amp", CS42L73_PWRCTL3, 2, 1,
634 &spk_amp_ctl, cs42l73_spklo_spk_amp_event,
635 SND_SOC_DAPM_POST_PMD),
636 SND_SOC_DAPM_SWITCH_E("EAR Amp", CS42L73_PWRCTL3, 3, 1,
637 &ear_amp_ctl, cs42l73_ear_amp_event,
638 SND_SOC_DAPM_POST_PMD),
639 SND_SOC_DAPM_SWITCH_E("SPKLO Amp", CS42L73_PWRCTL3, 4, 1,
640 &spklo_amp_ctl, cs42l73_spklo_spk_amp_event,
641 SND_SOC_DAPM_POST_PMD),
643 SND_SOC_DAPM_OUTPUT("HPOUTA"),
644 SND_SOC_DAPM_OUTPUT("HPOUTB"),
645 SND_SOC_DAPM_OUTPUT("LINEOUTA"),
646 SND_SOC_DAPM_OUTPUT("LINEOUTB"),
647 SND_SOC_DAPM_OUTPUT("EAROUT"),
648 SND_SOC_DAPM_OUTPUT("SPKOUT"),
649 SND_SOC_DAPM_OUTPUT("SPKLINEOUT"),
652 static const struct snd_soc_dapm_route cs42l73_audio_map[] = {
654 /* SPKLO EARSPK Paths */
655 {"EAROUT", NULL, "EAR Amp"},
656 {"SPKLINEOUT", NULL, "SPKLO Amp"},
658 {"EAR Amp", "Switch", "ESL DAC"},
659 {"SPKLO Amp", "Switch", "ESL DAC"},
661 {"ESL DAC", "ESL-ASP Mono Volume", "ESL Mixer"},
662 {"ESL DAC", "ESL-XSP Mono Volume", "ESL Mixer"},
663 {"ESL DAC", "ESL-VSP Mono Volume", "VSPINOUT"},
665 {"ESL DAC", "ESL-IP Mono Volume", "Input Left Capture"},
666 {"ESL DAC", "ESL-IP Mono Volume", "Input Right Capture"},
668 {"ESL Mixer", NULL, "ESL-ASP Mux"},
669 {"ESL Mixer", NULL, "ESL-XSP Mux"},
671 {"ESL-ASP Mux", "Left", "ASPINL"},
672 {"ESL-ASP Mux", "Right", "ASPINR"},
673 {"ESL-ASP Mux", "Mono Mix", "ASPINM"},
675 {"ESL-XSP Mux", "Left", "XSPINL"},
676 {"ESL-XSP Mux", "Right", "XSPINR"},
677 {"ESL-XSP Mux", "Mono Mix", "XSPINM"},
679 /* Speakerphone Paths */
680 {"SPKOUT", NULL, "SPK Amp"},
681 {"SPK Amp", "Switch", "SPK DAC"},
683 {"SPK DAC", "SPK-ASP Mono Volume", "SPK Mixer"},
684 {"SPK DAC", "SPK-XSP Mono Volume", "SPK Mixer"},
685 {"SPK DAC", "SPK-VSP Mono Volume", "VSPINOUT"},
687 {"SPK DAC", "SPK-IP Mono Volume", "Input Left Capture"},
688 {"SPK DAC", "SPK-IP Mono Volume", "Input Right Capture"},
690 {"SPK Mixer", NULL, "SPK-ASP Mux"},
691 {"SPK Mixer", NULL, "SPK-XSP Mux"},
693 {"SPK-ASP Mux", "Left", "ASPINL"},
694 {"SPK-ASP Mux", "Mono Mix", "ASPINM"},
695 {"SPK-ASP Mux", "Right", "ASPINR"},
697 {"SPK-XSP Mux", "Left", "XSPINL"},
698 {"SPK-XSP Mux", "Mono Mix", "XSPINM"},
699 {"SPK-XSP Mux", "Right", "XSPINR"},
701 /* HP LineOUT Paths */
702 {"HPOUTA", NULL, "HP Amp"},
703 {"HPOUTB", NULL, "HP Amp"},
704 {"LINEOUTA", NULL, "LO Amp"},
705 {"LINEOUTB", NULL, "LO Amp"},
707 {"HP Amp", "Switch", "HL Left DAC"},
708 {"HP Amp", "Switch", "HL Right DAC"},
709 {"LO Amp", "Switch", "HL Left DAC"},
710 {"LO Amp", "Switch", "HL Right DAC"},
712 {"HL Left DAC", "HL-XSP Volume", "HL Left Mixer"},
713 {"HL Right DAC", "HL-XSP Volume", "HL Right Mixer"},
714 {"HL Left DAC", "HL-ASP Volume", "HL Left Mixer"},
715 {"HL Right DAC", "HL-ASP Volume", "HL Right Mixer"},
716 {"HL Left DAC", "HL-VSP Volume", "HL Left Mixer"},
717 {"HL Right DAC", "HL-VSP Volume", "HL Right Mixer"},
719 {"HL Left DAC", "HL-IP Volume", "HL Left Mixer"},
720 {"HL Right DAC", "HL-IP Volume", "HL Right Mixer"},
721 {"HL Left Mixer", NULL, "Input Left Capture"},
722 {"HL Right Mixer", NULL, "Input Right Capture"},
724 {"HL Left Mixer", NULL, "ASPINL"},
725 {"HL Right Mixer", NULL, "ASPINR"},
726 {"HL Left Mixer", NULL, "XSPINL"},
727 {"HL Right Mixer", NULL, "XSPINR"},
728 {"HL Left Mixer", NULL, "VSPINOUT"},
729 {"HL Right Mixer", NULL, "VSPINOUT"},
731 {"ASPINL", NULL, "ASP Playback"},
732 {"ASPINM", NULL, "ASP Playback"},
733 {"ASPINR", NULL, "ASP Playback"},
734 {"XSPINL", NULL, "XSP Playback"},
735 {"XSPINM", NULL, "XSP Playback"},
736 {"XSPINR", NULL, "XSP Playback"},
737 {"VSPINOUT", NULL, "VSP Playback"},
740 {"MIC1", NULL, "MIC1 Bias"},
741 {"PGA Left Mux", "Mic 1", "MIC1"},
742 {"MIC2", NULL, "MIC2 Bias"},
743 {"PGA Right Mux", "Mic 2", "MIC2"},
745 {"PGA Left Mux", "Line A", "LINEINA"},
746 {"PGA Right Mux", "Line B", "LINEINB"},
748 {"PGA Left", NULL, "PGA Left Mux"},
749 {"PGA Right", NULL, "PGA Right Mux"},
751 {"ADC Left", NULL, "PGA Left"},
752 {"ADC Right", NULL, "PGA Right"},
753 {"DMIC Left", NULL, "DMICA"},
754 {"DMIC Right", NULL, "DMICB"},
756 {"Input Left Capture", "ADC Left Input", "ADC Left"},
757 {"Input Right Capture", "ADC Right Input", "ADC Right"},
758 {"Input Left Capture", "DMIC Left Input", "DMIC Left"},
759 {"Input Right Capture", "DMIC Right Input", "DMIC Right"},
762 {"ASPL Output Mixer", NULL, "Input Left Capture"},
763 {"ASPR Output Mixer", NULL, "Input Right Capture"},
765 {"ASPOUTL", "ASP-IP Volume", "ASPL Output Mixer"},
766 {"ASPOUTR", "ASP-IP Volume", "ASPR Output Mixer"},
768 /* Auxillary Capture */
769 {"XSPL Output Mixer", NULL, "Input Left Capture"},
770 {"XSPR Output Mixer", NULL, "Input Right Capture"},
772 {"XSPOUTL", "XSP-IP Volume", "XSPL Output Mixer"},
773 {"XSPOUTR", "XSP-IP Volume", "XSPR Output Mixer"},
775 {"XSPOUTL", NULL, "XSPL Output Mixer"},
776 {"XSPOUTR", NULL, "XSPR Output Mixer"},
779 {"VSP Output Mixer", NULL, "Input Left Capture"},
780 {"VSP Output Mixer", NULL, "Input Right Capture"},
782 {"VSPINOUT", "VSP-IP Volume", "VSP Output Mixer"},
784 {"VSPINOUT", NULL, "VSP Output Mixer"},
786 {"ASP Capture", NULL, "ASPOUTL"},
787 {"ASP Capture", NULL, "ASPOUTR"},
788 {"XSP Capture", NULL, "XSPOUTL"},
789 {"XSP Capture", NULL, "XSPOUTR"},
790 {"VSP Capture", NULL, "VSPINOUT"},
793 struct cs42l73_mclk_div {
799 static struct cs42l73_mclk_div cs42l73_mclk_coeffs[] = {
800 /* MCLK, Sample Rate, xMMCC[5:0] */
801 {5644800, 11025, 0x30},
802 {5644800, 22050, 0x20},
803 {5644800, 44100, 0x10},
805 {6000000, 8000, 0x39},
806 {6000000, 11025, 0x33},
807 {6000000, 12000, 0x31},
808 {6000000, 16000, 0x29},
809 {6000000, 22050, 0x23},
810 {6000000, 24000, 0x21},
811 {6000000, 32000, 0x19},
812 {6000000, 44100, 0x13},
813 {6000000, 48000, 0x11},
815 {6144000, 8000, 0x38},
816 {6144000, 12000, 0x30},
817 {6144000, 16000, 0x28},
818 {6144000, 24000, 0x20},
819 {6144000, 32000, 0x18},
820 {6144000, 48000, 0x10},
822 {6500000, 8000, 0x3C},
823 {6500000, 11025, 0x35},
824 {6500000, 12000, 0x34},
825 {6500000, 16000, 0x2C},
826 {6500000, 22050, 0x25},
827 {6500000, 24000, 0x24},
828 {6500000, 32000, 0x1C},
829 {6500000, 44100, 0x15},
830 {6500000, 48000, 0x14},
832 {6400000, 8000, 0x3E},
833 {6400000, 11025, 0x37},
834 {6400000, 12000, 0x36},
835 {6400000, 16000, 0x2E},
836 {6400000, 22050, 0x27},
837 {6400000, 24000, 0x26},
838 {6400000, 32000, 0x1E},
839 {6400000, 44100, 0x17},
840 {6400000, 48000, 0x16},
843 struct cs42l73_mclkx_div {
849 static struct cs42l73_mclkx_div cs42l73_mclkx_coeffs[] = {
850 {5644800, 1, 0}, /* 5644800 */
851 {6000000, 1, 0}, /* 6000000 */
852 {6144000, 1, 0}, /* 6144000 */
853 {11289600, 2, 2}, /* 5644800 */
854 {12288000, 2, 2}, /* 6144000 */
855 {12000000, 2, 2}, /* 6000000 */
856 {13000000, 2, 2}, /* 6500000 */
857 {19200000, 3, 3}, /* 6400000 */
858 {24000000, 4, 4}, /* 6000000 */
859 {26000000, 4, 4}, /* 6500000 */
860 {38400000, 6, 5} /* 6400000 */
863 static int cs42l73_get_mclkx_coeff(int mclkx)
867 for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) {
868 if (cs42l73_mclkx_coeffs[i].mclkx == mclkx)
874 static int cs42l73_get_mclk_coeff(int mclk, int srate)
878 for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) {
879 if (cs42l73_mclk_coeffs[i].mclk == mclk &&
880 cs42l73_mclk_coeffs[i].srate == srate)
887 static int cs42l73_set_mclk(struct snd_soc_dai *dai, unsigned int freq)
889 struct snd_soc_codec *codec = dai->codec;
890 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
897 mclkx_coeff = cs42l73_get_mclkx_coeff(freq);
901 mclk = cs42l73_mclkx_coeffs[mclkx_coeff].mclkx /
902 cs42l73_mclkx_coeffs[mclkx_coeff].ratio;
904 dev_dbg(codec->dev, "MCLK%u %u <-> internal MCLK %u\n",
905 priv->mclksel + 1, cs42l73_mclkx_coeffs[mclkx_coeff].mclkx,
908 dmmcc = (priv->mclksel << 4) |
909 (cs42l73_mclkx_coeffs[mclkx_coeff].mclkdiv << 1);
911 snd_soc_write(codec, CS42L73_DMMCC, dmmcc);
913 priv->sysclk = mclkx_coeff;
919 static int cs42l73_set_sysclk(struct snd_soc_dai *dai,
920 int clk_id, unsigned int freq, int dir)
922 struct snd_soc_codec *codec = dai->codec;
923 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
926 case CS42L73_CLKID_MCLK1:
928 case CS42L73_CLKID_MCLK2:
934 if ((cs42l73_set_mclk(dai, freq)) < 0) {
935 dev_err(codec->dev, "Unable to set MCLK for dai %s\n",
940 priv->mclksel = clk_id;
945 static int cs42l73_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
947 struct snd_soc_codec *codec = codec_dai->codec;
948 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
949 u8 id = codec_dai->id;
950 unsigned int inv, format;
953 spc = snd_soc_read(codec, CS42L73_SPC(id));
954 mmcc = snd_soc_read(codec, CS42L73_MMCC(id));
956 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
957 case SND_SOC_DAIFMT_CBM_CFM:
958 mmcc |= CS42L73_MS_MASTER;
961 case SND_SOC_DAIFMT_CBS_CFS:
962 mmcc &= ~CS42L73_MS_MASTER;
969 format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
970 inv = (fmt & SND_SOC_DAIFMT_INV_MASK);
973 case SND_SOC_DAIFMT_I2S:
974 spc &= ~CS42L73_SPDIF_PCM;
976 case SND_SOC_DAIFMT_DSP_A:
977 case SND_SOC_DAIFMT_DSP_B:
978 if (mmcc & CS42L73_MS_MASTER) {
980 "PCM format in slave mode only\n");
983 if (id == CS42L73_ASP) {
985 "PCM format is not supported on ASP port\n");
988 spc |= CS42L73_SPDIF_PCM;
994 if (spc & CS42L73_SPDIF_PCM) {
995 /* Clear PCM mode, clear PCM_BIT_ORDER bit for MSB->LSB */
996 spc &= ~(CS42L73_PCM_MODE_MASK | CS42L73_PCM_BIT_ORDER);
998 case SND_SOC_DAIFMT_DSP_B:
999 if (inv == SND_SOC_DAIFMT_IB_IF)
1000 spc |= CS42L73_PCM_MODE0;
1001 if (inv == SND_SOC_DAIFMT_IB_NF)
1002 spc |= CS42L73_PCM_MODE1;
1004 case SND_SOC_DAIFMT_DSP_A:
1005 if (inv == SND_SOC_DAIFMT_IB_IF)
1006 spc |= CS42L73_PCM_MODE1;
1013 priv->config[id].spc = spc;
1014 priv->config[id].mmcc = mmcc;
1019 static const unsigned int cs42l73_asrc_rates[] = {
1020 8000, 11025, 12000, 16000, 22050,
1021 24000, 32000, 44100, 48000
1024 static unsigned int cs42l73_get_xspfs_coeff(u32 rate)
1027 for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) {
1028 if (cs42l73_asrc_rates[i] == rate)
1031 return 0; /* 0 = Don't know */
1034 static void cs42l73_update_asrc(struct snd_soc_codec *codec, int id, int srate)
1039 spfs = cs42l73_get_xspfs_coeff(srate);
1043 snd_soc_update_bits(codec, CS42L73_VXSPFS, 0x0f, spfs);
1046 snd_soc_update_bits(codec, CS42L73_ASPC, 0x3c, spfs << 2);
1049 snd_soc_update_bits(codec, CS42L73_VXSPFS, 0xf0, spfs << 4);
1056 static int cs42l73_pcm_hw_params(struct snd_pcm_substream *substream,
1057 struct snd_pcm_hw_params *params,
1058 struct snd_soc_dai *dai)
1060 struct snd_soc_codec *codec = dai->codec;
1061 struct cs42l73_private *priv = snd_soc_codec_get_drvdata(codec);
1064 int srate = params_rate(params);
1066 if (priv->config[id].mmcc & CS42L73_MS_MASTER) {
1067 /* CS42L73 Master */
1070 cs42l73_get_mclk_coeff(priv->mclk, srate);
1076 "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n",
1077 id, priv->mclk, srate,
1078 cs42l73_mclk_coeffs[mclk_coeff].mmcc);
1080 priv->config[id].mmcc &= 0xC0;
1081 priv->config[id].mmcc |= cs42l73_mclk_coeffs[mclk_coeff].mmcc;
1082 priv->config[id].spc &= 0xFC;
1083 /* Use SCLK=64*Fs if internal MCLK >= 6.4MHz */
1084 if (priv->mclk >= 6400000)
1085 priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
1087 priv->config[id].spc |= CS42L73_MCK_SCLK_MCLK;
1090 priv->config[id].spc &= 0xFC;
1091 priv->config[id].spc |= CS42L73_MCK_SCLK_64FS;
1094 priv->config[id].srate = srate;
1096 snd_soc_write(codec, CS42L73_SPC(id), priv->config[id].spc);
1097 snd_soc_write(codec, CS42L73_MMCC(id), priv->config[id].mmcc);
1099 cs42l73_update_asrc(codec, id, srate);
1104 static int cs42l73_set_bias_level(struct snd_soc_codec *codec,
1105 enum snd_soc_bias_level level)
1107 struct cs42l73_private *cs42l73 = snd_soc_codec_get_drvdata(codec);
1110 case SND_SOC_BIAS_ON:
1111 snd_soc_update_bits(codec, CS42L73_DMMCC, CS42L73_MCLKDIS, 0);
1112 snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 0);
1115 case SND_SOC_BIAS_PREPARE:
1118 case SND_SOC_BIAS_STANDBY:
1119 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1120 regcache_cache_only(cs42l73->regmap, false);
1121 regcache_sync(cs42l73->regmap);
1123 snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 1);
1126 case SND_SOC_BIAS_OFF:
1127 snd_soc_update_bits(codec, CS42L73_PWRCTL1, CS42L73_PDN, 1);
1128 if (cs42l73->shutdwn_delay > 0) {
1129 mdelay(cs42l73->shutdwn_delay);
1130 cs42l73->shutdwn_delay = 0;
1132 mdelay(15); /* Min amount of time requred to power
1136 snd_soc_update_bits(codec, CS42L73_DMMCC, CS42L73_MCLKDIS, 1);
1142 static int cs42l73_set_tristate(struct snd_soc_dai *dai, int tristate)
1144 struct snd_soc_codec *codec = dai->codec;
1147 return snd_soc_update_bits(codec, CS42L73_SPC(id), CS42L73_SP_3ST,
1151 static const struct snd_pcm_hw_constraint_list constraints_12_24 = {
1152 .count = ARRAY_SIZE(cs42l73_asrc_rates),
1153 .list = cs42l73_asrc_rates,
1156 static int cs42l73_pcm_startup(struct snd_pcm_substream *substream,
1157 struct snd_soc_dai *dai)
1159 snd_pcm_hw_constraint_list(substream->runtime, 0,
1160 SNDRV_PCM_HW_PARAM_RATE,
1161 &constraints_12_24);
1166 #define CS42L73_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1167 SNDRV_PCM_FMTBIT_S24_LE)
1169 static const struct snd_soc_dai_ops cs42l73_ops = {
1170 .startup = cs42l73_pcm_startup,
1171 .hw_params = cs42l73_pcm_hw_params,
1172 .set_fmt = cs42l73_set_dai_fmt,
1173 .set_sysclk = cs42l73_set_sysclk,
1174 .set_tristate = cs42l73_set_tristate,
1177 static struct snd_soc_dai_driver cs42l73_dai[] = {
1179 .name = "cs42l73-xsp",
1182 .stream_name = "XSP Playback",
1185 .rates = SNDRV_PCM_RATE_KNOT,
1186 .formats = CS42L73_FORMATS,
1189 .stream_name = "XSP Capture",
1192 .rates = SNDRV_PCM_RATE_KNOT,
1193 .formats = CS42L73_FORMATS,
1195 .ops = &cs42l73_ops,
1196 .symmetric_rates = 1,
1199 .name = "cs42l73-asp",
1202 .stream_name = "ASP Playback",
1205 .rates = SNDRV_PCM_RATE_KNOT,
1206 .formats = CS42L73_FORMATS,
1209 .stream_name = "ASP Capture",
1212 .rates = SNDRV_PCM_RATE_KNOT,
1213 .formats = CS42L73_FORMATS,
1215 .ops = &cs42l73_ops,
1216 .symmetric_rates = 1,
1219 .name = "cs42l73-vsp",
1222 .stream_name = "VSP Playback",
1225 .rates = SNDRV_PCM_RATE_KNOT,
1226 .formats = CS42L73_FORMATS,
1229 .stream_name = "VSP Capture",
1232 .rates = SNDRV_PCM_RATE_KNOT,
1233 .formats = CS42L73_FORMATS,
1235 .ops = &cs42l73_ops,
1236 .symmetric_rates = 1,
1240 static int cs42l73_probe(struct snd_soc_codec *codec)
1242 struct cs42l73_private *cs42l73 = snd_soc_codec_get_drvdata(codec);
1244 /* Set Charge Pump Frequency */
1245 if (cs42l73->pdata.chgfreq)
1246 snd_soc_update_bits(codec, CS42L73_CPFCHC,
1247 CS42L73_CHARGEPUMP_MASK,
1248 cs42l73->pdata.chgfreq << 4);
1250 /* MCLK1 as master clk */
1251 cs42l73->mclksel = CS42L73_CLKID_MCLK1;
1257 static const struct snd_soc_codec_driver soc_codec_dev_cs42l73 = {
1258 .probe = cs42l73_probe,
1259 .set_bias_level = cs42l73_set_bias_level,
1260 .suspend_bias_off = true,
1262 .dapm_widgets = cs42l73_dapm_widgets,
1263 .num_dapm_widgets = ARRAY_SIZE(cs42l73_dapm_widgets),
1264 .dapm_routes = cs42l73_audio_map,
1265 .num_dapm_routes = ARRAY_SIZE(cs42l73_audio_map),
1267 .controls = cs42l73_snd_controls,
1268 .num_controls = ARRAY_SIZE(cs42l73_snd_controls),
1271 static const struct regmap_config cs42l73_regmap = {
1275 .max_register = CS42L73_MAX_REGISTER,
1276 .reg_defaults = cs42l73_reg_defaults,
1277 .num_reg_defaults = ARRAY_SIZE(cs42l73_reg_defaults),
1278 .volatile_reg = cs42l73_volatile_register,
1279 .readable_reg = cs42l73_readable_register,
1280 .cache_type = REGCACHE_RBTREE,
1283 static int cs42l73_i2c_probe(struct i2c_client *i2c_client,
1284 const struct i2c_device_id *id)
1286 struct cs42l73_private *cs42l73;
1287 struct cs42l73_platform_data *pdata = dev_get_platdata(&i2c_client->dev);
1289 unsigned int devid = 0;
1293 cs42l73 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l73_private),
1298 cs42l73->regmap = devm_regmap_init_i2c(i2c_client, &cs42l73_regmap);
1299 if (IS_ERR(cs42l73->regmap)) {
1300 ret = PTR_ERR(cs42l73->regmap);
1301 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1306 cs42l73->pdata = *pdata;
1308 pdata = devm_kzalloc(&i2c_client->dev,
1309 sizeof(struct cs42l73_platform_data),
1312 dev_err(&i2c_client->dev, "could not allocate pdata\n");
1315 if (i2c_client->dev.of_node) {
1316 if (of_property_read_u32(i2c_client->dev.of_node,
1317 "chgfreq", &val32) >= 0)
1318 pdata->chgfreq = val32;
1320 pdata->reset_gpio = of_get_named_gpio(i2c_client->dev.of_node,
1322 cs42l73->pdata = *pdata;
1325 i2c_set_clientdata(i2c_client, cs42l73);
1327 if (cs42l73->pdata.reset_gpio) {
1328 ret = devm_gpio_request_one(&i2c_client->dev,
1329 cs42l73->pdata.reset_gpio,
1330 GPIOF_OUT_INIT_HIGH,
1333 dev_err(&i2c_client->dev, "Failed to request /RST %d: %d\n",
1334 cs42l73->pdata.reset_gpio, ret);
1337 gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0);
1338 gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 1);
1341 regcache_cache_bypass(cs42l73->regmap, true);
1343 /* initialize codec */
1344 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_AB, ®);
1345 devid = (reg & 0xFF) << 12;
1347 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_CD, ®);
1348 devid |= (reg & 0xFF) << 4;
1350 ret = regmap_read(cs42l73->regmap, CS42L73_DEVID_E, ®);
1351 devid |= (reg & 0xF0) >> 4;
1353 if (devid != CS42L73_DEVID) {
1355 dev_err(&i2c_client->dev,
1356 "CS42L73 Device ID (%X). Expected %X\n",
1357 devid, CS42L73_DEVID);
1361 ret = regmap_read(cs42l73->regmap, CS42L73_REVID, ®);
1363 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
1367 dev_info(&i2c_client->dev,
1368 "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF);
1370 regcache_cache_bypass(cs42l73->regmap, false);
1372 ret = snd_soc_register_codec(&i2c_client->dev,
1373 &soc_codec_dev_cs42l73, cs42l73_dai,
1374 ARRAY_SIZE(cs42l73_dai));
1380 static int cs42l73_i2c_remove(struct i2c_client *client)
1382 snd_soc_unregister_codec(&client->dev);
1386 static const struct of_device_id cs42l73_of_match[] = {
1387 { .compatible = "cirrus,cs42l73", },
1390 MODULE_DEVICE_TABLE(of, cs42l73_of_match);
1392 static const struct i2c_device_id cs42l73_id[] = {
1397 MODULE_DEVICE_TABLE(i2c, cs42l73_id);
1399 static struct i2c_driver cs42l73_i2c_driver = {
1402 .of_match_table = cs42l73_of_match,
1404 .id_table = cs42l73_id,
1405 .probe = cs42l73_i2c_probe,
1406 .remove = cs42l73_i2c_remove,
1410 module_i2c_driver(cs42l73_i2c_driver);
1412 MODULE_DESCRIPTION("ASoC CS42L73 driver");
1413 MODULE_AUTHOR("Georgi Vlaev, Nucleus Systems Ltd, <joe@nucleusys.com>");
1414 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
1415 MODULE_LICENSE("GPL");