2 * ALSA SoC CX20721/cx20723 Solana codec driver
3 * Copyright: (C) 2016 Conexant Systems, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 *************************************************************************
10 * Modified Date: 7/11/16
11 * File Version: 4.4.20
12 *************************************************************************
16 /* #define INTEL_MCLK_CONTROL */
17 /* #define ENABLE_MIC_POP_WA */
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <linux/of_gpio.h>
32 #include <linux/gpio.h>
33 #include <sound/jack.h>
34 #include <linux/slab.h>
35 #include <linux/clk.h>
36 #include <linux/i2c.h>
37 #include <linux/firmware.h>
38 #include <linux/regmap.h>
39 #include <linux/proc_fs.h>
40 #include <linux/interrupt.h>
41 #include <linux/irq.h>
42 #include <linux/acpi.h>
43 #include <linux/version.h>
44 #ifdef INTEL_MCLK_CONTROL
45 #include <linux/vlv2_plat_clock.h>
48 #define PLL_OUT_HZ_48 (1024 * 3 * 48000)
49 #define SUPPORT_RKI2S_FORMAT
50 #define CX2072X_REV_A2 0x00100002
51 #define CXDBG_REG_DUMP
53 #ifdef INTEL_MCLK_CONTROL
54 #define VLV2_PLAT_CLK_AUDIO 3
55 #define PLAT_CLK_FORCE_ON 1
56 #define PLAT_CLK_FORCE_OFF 2
59 static struct snd_soc_codec *cx2072x_codec;
61 /* FIXME: need to move the EQ/DRC setting to device tree */
62 static unsigned char cx2072x_eq_coeff_array[MAX_EQ_BAND][MAC_EQ_COEFF] = {
63 {0x77, 0x26, 0x13, 0xb3, 0x76, 0x26, 0x0a, 0x3d, 0xd4, 0xe2, 0x04},
64 {0x97, 0x3e, 0xb3, 0x86, 0xc2, 0x3b, 0x4d, 0x79, 0xa7, 0xc5, 0x03},
65 {0x0f, 0x39, 0x76, 0xa3, 0x1b, 0x2b, 0x89, 0x5c, 0xd7, 0xdb, 0x03},
66 {0x21, 0x46, 0xfe, 0xa6, 0xec, 0x24, 0x01, 0x59, 0xf4, 0xd4, 0x03},
67 {0xe9, 0x78, 0x9c, 0xb0, 0x8a, 0x56, 0x64, 0x4f, 0x8d, 0xb0, 0x02},
68 {0x60, 0x6e, 0x57, 0xee, 0xec, 0x18, 0xa8, 0x11, 0xb5, 0xf8, 0x02},
69 {0x5a, 0x14, 0x68, 0xe9, 0x1d, 0x06, 0xb9, 0x5f, 0x68, 0xdc, 0x03},
72 static unsigned char cx2072x_drc_array[MAX_DRC_REGS] = {
73 0x65, 0x55, 0x3C, 0x01, 0x05, 0x39, 0x76, 0x1A, 0x00
76 /* #define CXDBG_REG_DUMP */
79 #define CX2072X_FORMATS (SNDRV_PCM_FMTBIT_S24_LE \
80 | SNDRV_PCM_FMTBIT_S16_LE)
81 #define BITS_PER_SLOT 8
83 #define _REG(_name_, _size_, _access_, _volatile_) { \
84 #_name_, _name_, (_size_) | (_access_) | (_volatile_)}
86 struct CX2072X_REG_DEF {
97 #define REGISTER_SIZE_MASK 0x000F
98 #define REGISTER_ASSCESS_MASK 0x0F00
99 #define REGISTER_VOLATILE_MASK 0x8000
100 #define UNAVAILABLE 0
102 static const struct CX2072X_REG_DEF cx2072x_regs[] = {
103 _REG(CX2072X_VENDOR_ID, 4, RO, VO),
104 _REG(CX2072X_REVISION_ID, 4, RO, VO),
105 _REG(CX2072X_CURRENT_BCLK_FREQUENCY, 4, RO, VO),
106 _REG(CX2072X_AFG_POWER_STATE, 1, RW, NV),
107 _REG(CX2072X_UM_RESPONSE, 1, RW, NV),
108 _REG(CX2072X_GPIO_DATA, 1, RW, NV),
109 _REG(CX2072X_GPIO_ENABLE, 1, RW, NV),
110 _REG(CX2072X_GPIO_DIRECTION, 1, RW, NV),
111 _REG(CX2072X_GPIO_WAKE, 1, RW, NV),
112 _REG(CX2072X_GPIO_UM_ENABLE, 1, RW, NV),
113 _REG(CX2072X_GPIO_STICKY_MASK, 1, RW, NV),
114 _REG(CX2072X_AFG_FUNCTION_RESET, 1, WO, NV),
115 _REG(CX2072X_DAC1_CONVERTER_FORMAT, 2, RW, NV),
116 _REG(CX2072X_DAC1_AMP_GAIN_RIGHT, 1, RW, NV),
117 _REG(CX2072X_DAC1_AMP_GAIN_LEFT, 1, RW, NV),
118 _REG(CX2072X_DAC1_POWER_STATE, 1, RW, NV),
119 _REG(CX2072X_DAC1_CONVERTER_STREAM_CHANNEL, 1, RW, NV),
120 _REG(CX2072X_DAC1_EAPD_ENABLE, 1, RW, NV),
121 _REG(CX2072X_DAC2_CONVERTER_FORMAT, 2, RW, NV),
122 _REG(CX2072X_DAC2_AMP_GAIN_RIGHT, 1, RW, NV),
123 _REG(CX2072X_DAC2_AMP_GAIN_LEFT, 1, RW, NV),
124 _REG(CX2072X_DAC2_POWER_STATE, 1, RW, NV),
125 _REG(CX2072X_DAC2_CONVERTER_STREAM_CHANNEL, 1, RW, NV),
126 _REG(CX2072X_ADC1_CONVERTER_FORMAT, 2, RW, NV),
127 _REG(CX2072X_ADC1_AMP_GAIN_RIGHT_0, 1, RW, NV),
128 _REG(CX2072X_ADC1_AMP_GAIN_LEFT_0, 1, RW, NV),
129 _REG(CX2072X_ADC1_AMP_GAIN_RIGHT_1, 1, RW, NV),
130 _REG(CX2072X_ADC1_AMP_GAIN_LEFT_1, 1, RW, NV),
131 _REG(CX2072X_ADC1_AMP_GAIN_RIGHT_2, 1, RW, NV),
132 _REG(CX2072X_ADC1_AMP_GAIN_LEFT_2, 1, RW, NV),
133 _REG(CX2072X_ADC1_AMP_GAIN_RIGHT_3, 1, RW, NV),
134 _REG(CX2072X_ADC1_AMP_GAIN_LEFT_3, 1, RW, NV),
135 _REG(CX2072X_ADC1_AMP_GAIN_RIGHT_4, 1, RW, NV),
136 _REG(CX2072X_ADC1_AMP_GAIN_LEFT_4, 1, RW, NV),
137 _REG(CX2072X_ADC1_AMP_GAIN_RIGHT_5, 1, RW, NV),
138 _REG(CX2072X_ADC1_AMP_GAIN_LEFT_5, 1, RW, NV),
139 _REG(CX2072X_ADC1_AMP_GAIN_RIGHT_6, 1, RW, NV),
140 _REG(CX2072X_ADC1_AMP_GAIN_LEFT_6, 1, RW, NV),
141 _REG(CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 1, RW, NV),
142 _REG(CX2072X_ADC1_POWER_STATE, 1, RW, NV),
143 _REG(CX2072X_ADC1_CONVERTER_STREAM_CHANNEL, 1, RW, NV),
144 _REG(CX2072X_ADC2_CONVERTER_FORMAT, 2, WO, NV),
145 _REG(CX2072X_ADC2_AMP_GAIN_RIGHT_0, 1, RW, NV),
146 _REG(CX2072X_ADC2_AMP_GAIN_LEFT_0, 1, RW, NV),
147 _REG(CX2072X_ADC2_AMP_GAIN_RIGHT_1, 1, RW, NV),
148 _REG(CX2072X_ADC2_AMP_GAIN_LEFT_1, 1, RW, NV),
149 _REG(CX2072X_ADC2_AMP_GAIN_RIGHT_2, 1, RW, NV),
150 _REG(CX2072X_ADC2_AMP_GAIN_LEFT_2, 1, RW, NV),
151 _REG(CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 1, RW, NV),
152 _REG(CX2072X_ADC2_POWER_STATE, 1, RW, NV),
153 _REG(CX2072X_ADC2_CONVERTER_STREAM_CHANNEL, 1, RW, NV),
154 _REG(CX2072X_PORTA_CONNECTION_SELECT_CTRL, 1, RW, NV),
155 _REG(CX2072X_PORTA_POWER_STATE, 1, RW, NV),
156 _REG(CX2072X_PORTA_PIN_CTRL, 1, RW, NV),
157 _REG(CX2072X_PORTA_UNSOLICITED_RESPONSE, 1, RW, NV),
158 _REG(CX2072X_PORTA_PIN_SENSE, 4, RO, VO),
159 _REG(CX2072X_PORTA_EAPD_BTL, 1, RW, NV),
160 _REG(CX2072X_PORTB_POWER_STATE, 1, RW, NV),
161 _REG(CX2072X_PORTB_PIN_CTRL, 1, RW, NV),
162 _REG(CX2072X_PORTB_UNSOLICITED_RESPONSE, 1, RW, NV),
163 _REG(CX2072X_PORTB_PIN_SENSE, 4, RO, VO),
164 _REG(CX2072X_PORTB_EAPD_BTL, 1, RW, NV),
165 _REG(CX2072X_PORTB_GAIN_RIGHT, 1, RW, NV),
166 _REG(CX2072X_PORTB_GAIN_LEFT, 1, RW, NV),
167 _REG(CX2072X_PORTC_POWER_STATE, 1, RW, NV),
168 _REG(CX2072X_PORTC_PIN_CTRL, 1, RW, NV),
169 _REG(CX2072X_PORTC_GAIN_RIGHT, 1, RW, NV),
170 _REG(CX2072X_PORTC_GAIN_LEFT, 1, RW, NV),
171 _REG(CX2072X_PORTD_POWER_STATE, 1, RW, NV),
172 _REG(CX2072X_PORTD_PIN_CTRL, 1, RW, NV),
173 _REG(CX2072X_PORTD_UNSOLICITED_RESPONSE, 1, RW, NV),
174 _REG(CX2072X_PORTD_PIN_SENSE, 4, RO, VO),
175 _REG(CX2072X_PORTD_GAIN_RIGHT, 1, RW, NV),
176 _REG(CX2072X_PORTD_GAIN_LEFT, 1, RW, NV),
177 _REG(CX2072X_PORTE_CONNECTION_SELECT_CTRL, 1, RW, NV),
178 _REG(CX2072X_PORTE_POWER_STATE, 1, RW, NV),
179 _REG(CX2072X_PORTE_PIN_CTRL, 1, RW, NV),
180 _REG(CX2072X_PORTE_UNSOLICITED_RESPONSE, 1, RW, NV),
181 _REG(CX2072X_PORTE_PIN_SENSE, 4, RO, VO),
182 _REG(CX2072X_PORTE_EAPD_BTL, 1, RW, NV),
183 _REG(CX2072X_PORTE_GAIN_RIGHT, 1, RW, NV),
184 _REG(CX2072X_PORTE_GAIN_LEFT, 1, RW, NV),
185 _REG(CX2072X_PORTF_POWER_STATE, 1, RW, NV),
186 _REG(CX2072X_PORTF_PIN_CTRL, 1, RW, NV),
187 _REG(CX2072X_PORTF_UNSOLICITED_RESPONSE, 1, RW, NV),
188 _REG(CX2072X_PORTF_PIN_SENSE, 4, RO, VO),
189 _REG(CX2072X_PORTF_GAIN_RIGHT, 1, RW, NV),
190 _REG(CX2072X_PORTF_GAIN_LEFT, 1, RW, NV),
191 _REG(CX2072X_PORTG_POWER_STATE, 1, RW, NV),
192 _REG(CX2072X_PORTG_PIN_CTRL, 1, RW, NV),
193 _REG(CX2072X_PORTG_CONNECTION_SELECT_CTRL, 1, RW, NV),
194 _REG(CX2072X_PORTG_EAPD_BTL, 1, RW, NV),
195 _REG(CX2072X_PORTM_POWER_STATE, 1, RW, NV),
196 _REG(CX2072X_PORTM_PIN_CTRL, 1, RW, NV),
197 _REG(CX2072X_PORTM_CONNECTION_SELECT_CTRL, 1, RW, NV),
198 _REG(CX2072X_PORTM_EAPD_BTL, 1, RW, NV),
199 _REG(CX2072X_MIXER_POWER_STATE, 1, RW, NV),
200 _REG(CX2072X_MIXER_GAIN_RIGHT_0, 1, RW, NV),
201 _REG(CX2072X_MIXER_GAIN_LEFT_0, 1, WO, NV),
202 _REG(CX2072X_MIXER_GAIN_RIGHT_1, 1, RW, NV),
203 _REG(CX2072X_MIXER_GAIN_LEFT_1, 1, RW, NV),
204 _REG(CX2072X_EQ_ENABLE_BYPASS, 2, RW, NV),
205 _REG(CX2072X_EQ_B0_COEFF, 2, WO, VO),
206 _REG(CX2072X_EQ_B1_COEFF, 2, WO, VO),
207 _REG(CX2072X_EQ_B2_COEFF, 2, WO, VO),
208 _REG(CX2072X_EQ_A1_COEFF, 2, WO, VO),
209 _REG(CX2072X_EQ_A2_COEFF, 2, WO, VO),
210 _REG(CX2072X_EQ_G_COEFF, 1, WO, VO),
211 _REG(CX2072X_EQ_BAND, 1, WO, VO),
212 _REG(CX2072X_SPKR_DRC_ENABLE_STEP, 1, RW, NV),
213 _REG(CX2072X_SPKR_DRC_CONTROL, 4, RW, NV),
214 _REG(CX2072X_SPKR_DRC_TEST, 4, RW, NV),
215 _REG(CX2072X_DIGITAL_BIOS_TEST0, 4, RW, NV),
216 _REG(CX2072X_DIGITAL_BIOS_TEST2, 4, RW, NV),
217 _REG(CX2072X_I2SPCM_CONTROL1, 4, RW, NV),
218 _REG(CX2072X_I2SPCM_CONTROL2, 4, RW, NV),
219 _REG(CX2072X_I2SPCM_CONTROL3, 4, RW, NV),
220 _REG(CX2072X_I2SPCM_CONTROL4, 4, RW, NV),
221 _REG(CX2072X_I2SPCM_CONTROL5, 4, RW, NV),
222 _REG(CX2072X_I2SPCM_CONTROL6, 4, RW, NV),
223 _REG(CX2072X_UM_INTERRUPT_CRTL_E, 4, RW, NV),
224 _REG(CX2072X_CODEC_TEST20, 2, RW, NV),
225 _REG(CX2072X_CODEC_TEST26, 2, RW, NV),
226 _REG(CX2072X_ANALOG_TEST4, 2, RW, NV),
227 _REG(CX2072X_ANALOG_TEST5, 2, RW, NV),
228 _REG(CX2072X_ANALOG_TEST6, 2, WO, NV),
229 _REG(CX2072X_ANALOG_TEST7, 2, RW, NV),
230 _REG(CX2072X_ANALOG_TEST8, 2, RW, NV),
231 _REG(CX2072X_ANALOG_TEST9, 2, RW, NV),
232 _REG(CX2072X_ANALOG_TEST10, 2, RW, NV),
233 _REG(CX2072X_ANALOG_TEST11, 2, RW, NV),
234 _REG(CX2072X_ANALOG_TEST12, 2, RW, NV),
235 _REG(CX2072X_ANALOG_TEST13, 2, RW, NV),
236 _REG(CX2072X_DIGITAL_TEST0, 2, RW, NV),
237 _REG(CX2072X_DIGITAL_TEST1, 2, RW, NV),
238 _REG(CX2072X_DIGITAL_TEST11, 2, RW, NV),
239 _REG(CX2072X_DIGITAL_TEST12, 2, RW, NV),
240 _REG(CX2072X_DIGITAL_TEST15, 2, RW, NV),
241 _REG(CX2072X_DIGITAL_TEST16, 2, RW, NV),
242 _REG(CX2072X_DIGITAL_TEST17, 2, RW, NV),
243 _REG(CX2072X_DIGITAL_TEST18, 2, RW, NV),
244 _REG(CX2072X_DIGITAL_TEST19, 2, RW, NV),
245 _REG(CX2072X_DIGITAL_TEST20, 2, RW, NV),
249 /* codec private data */
250 struct cx2072x_priv {
251 struct regmap *regmap;
254 struct snd_soc_codec *codec;
255 struct snd_soc_dai_driver *dai_drv;
257 struct snd_soc_jack *jack;
262 unsigned int jack_state;
266 unsigned int bclk_ratio;
268 #ifdef ENABLE_MIC_POP_WA
269 struct delayed_work mic_pop_workq;
272 bool plbk_dsp_changed;
276 int sample_size; /* used for non-PCM mode */
277 int frame_size; /* used for non-PCM mode */
279 unsigned int dai_fmt;
287 int spk_active_level;
288 struct clk *mclk_clock;
298 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7400, 100, 0);
299 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7400, 100, 0);
300 static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 1200, 0);
302 #define get_cx2072x_priv(_codec_) \
303 ((struct cx2072x_priv *)snd_soc_codec_get_drvdata(_codec_))
305 /* Lookup table for PRE_DIV */
316 { 36864000, 7 },/* Don't use div 7 */
322 * cx2072x register cache.
324 static const struct reg_default cx2072x_reg_defaults[] = {
325 { 0x0414, 0x00000003 }, /* 2072X_AFG_POWER_STATE */
326 { 0x0420, 0x00000000 }, /* 2072X_UM_RESPONSE */
327 { 0x0454, 0x00000000 }, /* 2072X_GPIO_DATA */
328 { 0x0458, 0x00000000 }, /* 2072X_GPIO_ENABLE */
329 { 0x045c, 0x00000000 }, /* 2072X_GPIO_DIRECTION */
330 { 0x0460, 0x00000000 }, /* 2072X_GPIO_WAKE */
331 { 0x0464, 0x00000000 }, /* 2072X_GPIO_UM_ENABLE */
332 { 0x0468, 0x00000000 }, /* 2072X_GPIO_STICKY_MASK */
333 { 0x43c8, 0x00000031 }, /* 2072X_DAC1_CONVERTER_FORMAT */
334 { 0x41c0, 0x0000004a }, /* 2072X_DAC1_AMP_GAIN_RIGHT */
335 { 0x41e0, 0x0000004a }, /* 2072X_DAC1_AMP_GAIN_LEFT */
336 { 0x4014, 0x00000433 }, /* 2072X_DAC1_POWER_STATE */
337 { 0x4018, 0x00000000 }, /* 2072X_DAC1_CONVERTER_STREAM_CHANNEL */
338 { 0x4030, 0x00000000 }, /* 2072X_DAC1_EAPD_ENABLE */
339 { 0x47c8, 0x00000031 }, /* 2072X_DAC2_CONVERTER_FORMAT */
340 { 0x45c0, 0x0000004a }, /* 2072X_DAC2_AMP_GAIN_RIGHT */
341 { 0x45e0, 0x0000004a }, /* 2072X_DAC2_AMP_GAIN_LEFT */
342 { 0x4414, 0x00000433 }, /* 2072X_DAC2_POWER_STATE */
343 { 0x4418, 0x00000000 }, /* 2072X_DAC2_CONVERTER_STREAM_CHANNEL */
344 { 0x4fc8, 0x00000031 }, /* 2072X_ADC1_CONVERTER_FORMAT */
345 { 0x4d80, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_RIGHT_0 */
346 { 0x4da0, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_LEFT_0 */
347 { 0x4d84, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_RIGHT_1 */
348 { 0x4da4, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_LEFT_1 */
349 { 0x4d88, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_RIGHT_2 */
350 { 0x4da8, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_LEFT_2 */
351 { 0x4d8c, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_RIGHT_3 */
352 { 0x4dac, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_LEFT_3 */
353 { 0x4d90, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_RIGHT_4 */
354 { 0x4db0, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_LEFT_4 */
355 { 0x4d94, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_RIGHT_5 */
356 { 0x4db4, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_LEFT_5 */
357 { 0x4d98, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_RIGHT_6 */
358 { 0x4db8, 0x0000004a }, /* 2072X_ADC1_AMP_GAIN_LEFT_6 */
359 { 0x4c04, 0x00000000 }, /* 2072X_ADC1_CONNECTION_SELECT_CONTROL */
360 { 0x4c14, 0x00000433 }, /* 2072X_ADC1_POWER_STATE */
361 { 0x4c18, 0x00000000 }, /* 2072X_ADC1_CONVERTER_STREAM_CHANNEL */
362 { 0x53c8, 0x00000031 }, /* 2072X_ADC2_CONVERTER_FORMAT */
363 { 0x5180, 0x0000004a }, /* 2072X_ADC2_AMP_GAIN_RIGHT_0 */
364 { 0x51a0, 0x0000004a }, /* 2072X_ADC2_AMP_GAIN_LEFT_0 */
365 { 0x5184, 0x0000004a }, /* 2072X_ADC2_AMP_GAIN_RIGHT_1 */
366 { 0x51a4, 0x0000004a }, /* 2072X_ADC2_AMP_GAIN_LEFT_1 */
367 { 0x5188, 0x0000004a }, /* 2072X_ADC2_AMP_GAIN_RIGHT_2 */
368 { 0x51a8, 0x0000004a }, /* 2072X_ADC2_AMP_GAIN_LEFT_2 */
369 { 0x5004, 0x00000000 }, /* 2072X_ADC2_CONNECTION_SELECT_CONTROL */
370 { 0x5014, 0x00000433 }, /* 2072X_ADC2_POWER_STATE */
371 { 0x5018, 0x00000000 }, /* 2072X_ADC2_CONVERTER_STREAM_CHANNEL */
372 { 0x5804, 0x00000000 }, /* 2072X_PORTA_CONNECTION_SELECT_CTRL */
373 { 0x5814, 0x00000433 }, /* 2072X_PORTA_POWER_STATE */
374 { 0x581c, 0x000000c0 }, /* 2072X_PORTA_PIN_CTRL */
375 { 0x5820, 0x00000000 }, /* 2072X_PORTA_UNSOLICITED_RESPONSE */
376 { 0x5824, 0x00000000 }, /* 2072X_PORTA_PIN_SENSE */
377 { 0x5830, 0x00000002 }, /* 2072X_PORTA_EAPD_BTL */
378 { 0x6014, 0x00000433 }, /* 2072X_PORTB_POWER_STATE */
379 { 0x601c, 0x00000000 }, /* 2072X_PORTB_PIN_CTRL */
380 { 0x6020, 0x00000000 }, /* 2072X_PORTB_UNSOLICITED_RESPONSE */
381 { 0x6024, 0x00000000 }, /* 2072X_PORTB_PIN_SENSE */
382 { 0x6030, 0x00000002 }, /* 2072X_PORTB_EAPD_BTL */
383 { 0x6180, 0x00000000 }, /* 2072X_PORTB_GAIN_RIGHT */
384 { 0x61a0, 0x00000000 }, /* 2072X_PORTB_GAIN_LEFT */
385 { 0x6814, 0x00000433 }, /* 2072X_PORTC_POWER_STATE */
386 { 0x681c, 0x00000000 }, /* 2072X_PORTC_PIN_CTRL */
387 { 0x6980, 0x00000000 }, /* 2072X_PORTC_GAIN_RIGHT */
388 { 0x69a0, 0x00000000 }, /* 2072X_PORTC_GAIN_LEFT */
389 { 0x6414, 0x00000433 }, /* 2072X_PORTD_POWER_STATE */
390 { 0x641c, 0x00000020 }, /* 2072X_PORTD_PIN_CTRL */
391 { 0x6420, 0x00000000 }, /* 2072X_PORTD_UNSOLICITED_RESPONSE */
392 { 0x6424, 0x00000000 }, /* 2072X_PORTD_PIN_SENSE */
393 { 0x6580, 0x00000000 }, /* 2072X_PORTD_GAIN_RIGHT */
394 { 0x65a0, 0x00000000 }, /* 2072X_PORTD_GAIN_LEFT */
395 { 0x7404, 0x00000000 }, /* 2072X_PORTE_CONNECTION_SELECT_CTRL */
396 { 0x7414, 0x00000433 }, /* 2072X_PORTE_POWER_STATE */
397 { 0x741c, 0x00000040 }, /* 2072X_PORTE_PIN_CTRL */
398 { 0x7420, 0x00000000 }, /* 2072X_PORTE_UNSOLICITED_RESPONSE */
399 { 0x7424, 0x00000000 }, /* 2072X_PORTE_PIN_SENSE */
400 { 0x7430, 0x00000002 }, /* 2072X_PORTE_EAPD_BTL */
401 { 0x7580, 0x00000000 }, /* 2072X_PORTE_GAIN_RIGHT */
402 { 0x75a0, 0x00000000 }, /* 2072X_PORTE_GAIN_LEFT */
403 { 0x7814, 0x00000433 }, /* 2072X_PORTF_POWER_STATE */
404 { 0x781c, 0x00000000 }, /* 2072X_PORTF_PIN_CTRL */
405 { 0x7820, 0x00000000 }, /* 2072X_PORTF_UNSOLICITED_RESPONSE */
406 { 0x7824, 0x00000000 }, /* 2072X_PORTF_PIN_SENSE */
407 { 0x7980, 0x00000000 }, /* 2072X_PORTF_GAIN_RIGHT */
408 { 0x79a0, 0x00000000 }, /* 2072X_PORTF_GAIN_LEFT */
409 { 0x5c14, 0x00000433 }, /* 2072X_PORTG_POWER_STATE */
410 { 0x5c1c, 0x00000040 }, /* 2072X_PORTG_PIN_CTRL */
411 { 0x5c04, 0x00000000 }, /* 2072X_PORTG_CONNECTION_SELECT_CTRL */
412 { 0x5c30, 0x00000002 }, /* 2072X_PORTG_EAPD_BTL */
413 { 0x8814, 0x00000433 }, /* 2072X_PORTM_POWER_STATE */
414 { 0x881c, 0x00000000 }, /* 2072X_PORTM_PIN_CTRL */
415 { 0x8804, 0x00000000 }, /* 2072X_PORTM_CONNECTION_SELECT_CTRL */
416 { 0x8830, 0x00000002 }, /* 2072X_PORTM_EAPD_BTL */
417 { 0x5414, 0x00000433 }, /* 2072X_MIXER_POWER_STATE */
418 { 0x5580, 0x0000004a }, /* 2072X_MIXER_GAIN_RIGHT_0 */
419 { 0x55a0, 0x0000004a }, /* 2072X_MIXER_GAIN_LEFT_0 */
420 { 0x5584, 0x0000004a }, /* 2072X_MIXER_GAIN_RIGHT_1 */
421 { 0x55a4, 0x0000004a }, /* 2072X_MIXER_GAIN_LEFT_1 */
422 { 0x6d00, 0x0000720c }, /* 2072X_EQ_ENABLE_BYPASS */
423 { 0x6d10, 0x040065a4 }, /* 2072X_SPKR_DRC_ENABLE_STEP */
424 { 0x6d14, 0x007b0024 }, /* 2072X_SPKR_DRC_CONTROL */
425 { 0X6D18, 0x00000000 }, /* 2072X_SPKR_DRC_TEST */
426 { 0x6d80, 0x001f008a }, /* 2072X_DIGITAL_BIOS_TEST0 */
427 { 0x6d84, 0x00990026 }, /* 2072X_DIGITAL_BIOS_TEST2 */
428 { 0x6e00, 0x00010001 }, /* 2072X_I2SPCM_CONTROL1 */
429 { 0x6e04, 0x00000000 }, /* 2072X_I2SPCM_CONTROL2 */
430 { 0x6e08, 0x00000000 }, /* 2072X_I2SPCM_CONTROL3 */
431 { 0x6e0c, 0x00000000 }, /* 2072X_I2SPCM_CONTROL4 */
432 { 0x6e10, 0x00000000 }, /* 2072X_I2SPCM_CONTROL5 */
433 { 0x6e18, 0x00000000 }, /* 2072X_I2SPCM_CONTROL6 */
434 { 0x6e14, 0x00000000 }, /* 2072X_UM_INTERRUPT_CRTL_E */
435 { 0x7108, 0x00000000 }, /*2072X_CODEC_TEST2 */
436 { 0x7124, 0x00000004 }, /*2072X_CODEC_TEST9 */
437 { 0x7310, 0x00000600 }, /* 2072X_CODEC_TEST20 */
438 { 0x7328, 0x00000208 }, /* 2072X_CODEC_TEST26 */
439 { 0x7190, 0x00000000 }, /* 2072X_ANALOG_TEST4 */
440 { 0x7194, 0x00000000 }, /* 2072X_ANALOG_TEST5 */
441 { 0x7198, 0x0000059a }, /* 2072X_ANALOG_TEST6 */
442 { 0x719c, 0x000000a7 }, /* 2072X_ANALOG_TEST7 */
443 { 0x71a0, 0x00000017 }, /* 2072X_ANALOG_TEST8 */
444 { 0x71a4, 0x00000000 }, /* 2072X_ANALOG_TEST9 */
445 { 0x71a8, 0x00000285 }, /* 2072X_ANALOG_TEST10 */
446 { 0x71ac, 0x00000000 }, /* 2072X_ANALOG_TEST11 */
447 { 0x71b0, 0x00000000 }, /* 2072X_ANALOG_TEST12 */
448 { 0x71b4, 0x00000000 }, /* 2072X_ANALOG_TEST13 */
449 { 0x7204, 0x00000242 }, /* 2072X_DIGITAL_TEST1 */
450 { 0x7224, 0x00000000 }, /* 2072X_DIGITAL_TEST11 */
451 { 0x7230, 0x00000084 }, /* 2072X_DIGITAL_TEST12 */
452 { 0x723c, 0x00000077 }, /* 2072X_DIGITAL_TEST15 */
453 { 0x7080, 0x00000021 }, /* 2072X_DIGITAL_TEST16 */
454 { 0x7084, 0x00000018 }, /* 2072X_DIGITAL_TEST17 */
455 { 0x7088, 0x00000024 }, /* 2072X_DIGITAL_TEST18 */
456 { 0x708c, 0x00000001 }, /* 2072X_DIGITAL_TEST19 */
457 { 0x7090, 0x00000002 }, /* 2072X_DIGITAL_TEST20 */
463 #if (KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE)
464 static const struct reg_sequence cx2072x_patch[] = {
466 static const struct reg_default cx2072x_patch[] = {
468 { 0x71A4, 0x080 }, /* DC offset Calibration */
469 { 0x71a8, 0x287 }, /* Set max spk power to 1.5 W */
470 { 0x7328, 0xa8c }, /* Set average spk power to 1.5W*/
471 { 0x7310, 0xf01 }, /* */
472 { 0x7328, 0xa8f }, /* */
473 { 0x7124, 0x001 }, /* Enable 30 Hz High pass filter*/
474 { 0x718c, 0x300 }, /* Disable PCBEEP pad */
475 { 0x731c, 0x100 }, /* Disable SnM mode */
476 { 0x641c, 0x020 }, /* Enable PortD input */
477 { 0x0458, 0x040 }, /* Enable GPIO7 pin for button */
478 { 0x0464, 0x040 }, /* Enable UM for GPIO7 */
479 { 0x0420, 0x080 }, /* Enable button response */
480 { 0x7230, 0x0c4 }, /* Enable headset button */
481 { 0x7200, 0x415 }, /* Power down class-d during idle*/
484 /* return register size */
485 static unsigned int cx2072x_register_size(struct device *dev,
489 case CX2072X_VENDOR_ID:
490 case CX2072X_REVISION_ID:
491 case CX2072X_PORTA_PIN_SENSE:
492 case CX2072X_PORTB_PIN_SENSE:
493 case CX2072X_PORTD_PIN_SENSE:
494 case CX2072X_PORTE_PIN_SENSE:
495 case CX2072X_PORTF_PIN_SENSE:
496 case CX2072X_I2SPCM_CONTROL1:
497 case CX2072X_I2SPCM_CONTROL2:
498 case CX2072X_I2SPCM_CONTROL3:
499 case CX2072X_I2SPCM_CONTROL4:
500 case CX2072X_I2SPCM_CONTROL5:
501 case CX2072X_I2SPCM_CONTROL6:
502 case CX2072X_UM_INTERRUPT_CRTL_E:
503 case CX2072X_EQ_G_COEFF:
504 /* case CX2072X_SPKR_DRC_ENABLE_STEP: */
505 case CX2072X_SPKR_DRC_CONTROL:
506 case CX2072X_SPKR_DRC_TEST:
507 case CX2072X_DIGITAL_BIOS_TEST0:
508 case CX2072X_DIGITAL_BIOS_TEST2:
510 case CX2072X_EQ_ENABLE_BYPASS:
511 case CX2072X_EQ_B0_COEFF:
512 case CX2072X_EQ_B1_COEFF:
513 case CX2072X_EQ_B2_COEFF:
514 case CX2072X_EQ_A1_COEFF:
515 case CX2072X_EQ_A2_COEFF:
516 case CX2072X_DAC1_CONVERTER_FORMAT:
517 case CX2072X_DAC2_CONVERTER_FORMAT:
518 case CX2072X_ADC1_CONVERTER_FORMAT:
519 case CX2072X_ADC2_CONVERTER_FORMAT:
520 case CX2072X_CODEC_TEST2:
521 case CX2072X_CODEC_TEST9:
522 case CX2072X_CODEC_TEST20:
523 case CX2072X_CODEC_TEST26:
524 case CX2072X_ANALOG_TEST3:
525 case CX2072X_ANALOG_TEST4:
526 case CX2072X_ANALOG_TEST5:
527 case CX2072X_ANALOG_TEST6:
528 case CX2072X_ANALOG_TEST7:
529 case CX2072X_ANALOG_TEST8:
530 case CX2072X_ANALOG_TEST9:
531 case CX2072X_ANALOG_TEST10:
532 case CX2072X_ANALOG_TEST11:
533 case CX2072X_ANALOG_TEST12:
534 case CX2072X_ANALOG_TEST13:
535 case CX2072X_DIGITAL_TEST0:
536 case CX2072X_DIGITAL_TEST1:
537 case CX2072X_DIGITAL_TEST11:
538 case CX2072X_DIGITAL_TEST12:
539 case CX2072X_DIGITAL_TEST15:
540 case CX2072X_DIGITAL_TEST16:
541 case CX2072X_DIGITAL_TEST17:
542 case CX2072X_DIGITAL_TEST18:
543 case CX2072X_DIGITAL_TEST19:
544 case CX2072X_DIGITAL_TEST20:
551 #ifdef CXDBG_REG_DUMP
552 static const char *cx2072x_get_reg_name(struct device *dev, unsigned int reg)
556 for (i = 0; i < ARRAY_SIZE(cx2072x_regs); i++)
557 if (cx2072x_regs[i].addr == reg)
558 return cx2072x_regs[i].name;
560 dev_err(dev, "Unknown reg %08x\n", reg);
562 return "Unknown reg";
566 static int cx2072x_reg_write(void *context, unsigned int reg,
569 struct i2c_client *client = context;
574 struct device *dev = &client->dev;
576 size = cx2072x_register_size(dev, reg);
579 #ifdef CXDBG_REG_DUMP
580 dev_dbg(dev, "I2C write address %40s,%d <= %08x\n",
581 cx2072x_get_reg_name(dev, reg), size, value);
584 if (reg == CX2072X_UM_INTERRUPT_CRTL_E) {
585 /* workaround to update the MSB byte only */
594 for (i = 2; i < (size + 2); ++i) {
599 ret = i2c_master_send(client, buf, size + 2);
600 if (ret == size + 2) {
602 } else if (ret < 0) {
604 "I2C write address failed\n");
607 "I2C write failed\n");
613 static int cx2072x_reg_bulk_write(struct snd_soc_codec *codec,
614 unsigned int reg, const void *val,
618 struct i2c_client *client = to_i2c_client(codec->dev);
619 u8 buf[2 + MAC_EQ_COEFF];
621 struct device *dev = &client->dev;
623 #ifdef CXDBG_REG_DUMP
624 dev_dbg(dev, "I2C bulk write address %40s,%ld\n",
625 cx2072x_get_reg_name(dev, reg), val_count);
628 if (val_count > MAC_EQ_COEFF) {
630 "cx2072x_reg_bulk_write failed, writing count = %ld\n",
638 memcpy(&buf[2], val, val_count);
640 ret = i2c_master_send(client, buf, val_count + 2);
641 if (ret == val_count + 2) {
643 } else if (ret < 0) {
645 "I2C bulk write address failed\n");
648 "I2C bulk write address failed\n");
654 /* get suggested pre_div valuce from mclk frequency */
655 static unsigned int get_div_from_mclk(unsigned int mclk)
657 unsigned int div = 8;
660 for (i = 0; i < ARRAY_SIZE(MCLK_PRE_DIV); i++) {
661 if (mclk <= MCLK_PRE_DIV[i].mclk) {
662 div = MCLK_PRE_DIV[i].div;
669 static int cx2072x_reg_read(void *context, unsigned int reg,
675 unsigned int recv_buf = 0;
676 struct i2c_client *client = context;
677 struct i2c_msg msgs[2];
678 struct device *dev = &client->dev;
680 size = cx2072x_register_size(dev, reg);
684 send_buf[0] = reg >> 8;
685 send_buf[1] = reg & 0xff;
687 msgs[0].addr = client->addr;
688 msgs[0].len = sizeof(send_buf);
689 msgs[0].buf = send_buf;
692 msgs[1].addr = client->addr;
694 msgs[1].buf = (uint8_t *)&recv_buf;
695 msgs[1].flags = I2C_M_RD;
697 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
700 "Failed to register codec: %d\n", ret);
702 } else if (ret != ARRAY_SIZE(msgs)) {
704 "Failed to register codec: %d\n", ret);
710 #ifdef CXDBG_REG_DUMP
712 "I2C read address %40s,%d => %08x\n",
713 cx2072x_get_reg_name(dev, reg), size, *value);
718 static int cx2072x_config_headset_det(struct cx2072x_priv *cx2072x)
720 const int interrupt_gpio_pin = 1;
722 dev_dbg(cx2072x->dev,
723 "Configure interrupt pin: %d\n", interrupt_gpio_pin);
724 /* No-sticky input type */
725 regmap_write(cx2072x->regmap, CX2072X_GPIO_STICKY_MASK, 0x1f);
726 /* Use GPOI0 as interrupt output pin */
727 regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0x12 << 24);
729 /* Enables unsolitited message on PortA */
730 regmap_write(cx2072x->regmap, CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x80);
732 /* support both nokia and apple headset set. Monitor time = 275 ms */
733 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST15, 0x73);
735 /* Disable TIP detection*/
736 regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST12, 0x300);
738 /* Switch MusicD3Live pin to GPIO */
739 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST1, 0);
742 * invert JSENSE if necessary
743 * regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_TEST12,
750 static int cx2072x_config_pll(struct cx2072x_priv *cx2072x)
752 struct device *dev = cx2072x->dev;
753 unsigned int pre_div;
754 unsigned int pre_div_val;
755 unsigned int pll_input;
756 unsigned int pll_output;
757 unsigned int int_div;
758 unsigned int frac_div;
759 unsigned long int frac_num = 0;
760 unsigned int sample_rate = cx2072x->sample_rate;
761 int pt_sample_per_sync = 2;
762 int pt_clock_per_sample = 96;
764 switch (sample_rate) {
771 pt_sample_per_sync = 1;
772 pt_clock_per_sample = 48;
775 pt_sample_per_sync = 0;
776 pt_clock_per_sample = 24;
779 dev_err(dev, "Unsupported sample rate %d\n", sample_rate);
783 /* Configure PLL settings */
784 pre_div = get_div_from_mclk(cx2072x->mclk);
785 pll_input = cx2072x->mclk / pre_div;
786 pll_output = sample_rate * 3072;
787 int_div = pll_output / pll_input;
788 frac_div = pll_output - (int_div * pll_input);
792 frac_div /= pll_input;
793 frac_num = ((4000 + frac_div) * ((1 << 20) - 4));
795 frac_num = (frac_num + 499) / 1000;
797 pre_div_val = (pre_div - 1) * 2;
799 regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST4, 0X40 |
803 regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7, 0x100);
806 regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST6,
808 regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7,
809 (unsigned char)(frac_num >> 12));
812 regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST8,
813 (unsigned char)int_div & 0xffff);
815 /* configure PLL tracking */
817 /* disable PLL tracking */
818 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16, 0x00);
820 /* configure and enable PLL tracking */
821 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16,
822 (pt_sample_per_sync << 4) & 0xf0);
823 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST17,
824 pt_clock_per_sample);
825 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST18,
826 pt_clock_per_sample * 3 / 2);
827 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST19, 0x01);
828 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST20, 0x02);
829 regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_TEST16,
835 static int cx2072x_config_i2spcm(struct cx2072x_priv *cx2072x)
837 struct device *dev = cx2072x->dev;
838 unsigned int bclk_rate = 0;
840 int has_one_bit_delay = 0;
842 int is_frame_inv = 0;
845 int frame_len = cx2072x->frame_size;
846 int sample_size = cx2072x->sample_size;
848 int i2s_right_pause_interval = 0;
849 int i2s_right_pause_pos;
850 int is_big_endian = 1;
851 const int slots_per_channel = cx2072x->tdm_slot_width / BITS_PER_SLOT;
852 const unsigned int fmt = cx2072x->dai_fmt;
853 unsigned long int mod, div;
854 union REG_I2SPCM_CTRL_REG1 reg1;
855 union REG_I2SPCM_CTRL_REG2 reg2;
856 union REG_I2SPCM_CTRL_REG3 reg3;
857 union REG_I2SPCM_CTRL_REG4 reg4;
858 union REG_I2SPCM_CTRL_REG5 reg5;
859 union REG_I2SPCM_CTRL_REG6 reg6;
860 union REG_DIGITAL_BIOS_TEST2 regDBT2;
862 if (frame_len <= 0) {
863 dev_err(dev, "Incorrect frame len %d\n", frame_len);
867 if (sample_size <= 0) {
868 dev_err(dev, "Incorrect sample size %d\n", sample_size);
873 regDBT2.ulval = 0xac;
875 /* set master/slave */
876 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
877 case SND_SOC_DAIFMT_CBM_CFM:
878 reg2.r.tx_master = 1;
879 reg3.r.rx_master = 1;
881 case SND_SOC_DAIFMT_CBS_CFS:
882 reg2.r.tx_master = 0;
883 reg3.r.rx_master = 0;
886 dev_err(dev, "Unsupported DAI master mode\n");
891 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
892 case SND_SOC_DAIFMT_I2S:
894 has_one_bit_delay = 1;
895 pulse_len = frame_len / 2;
897 case SND_SOC_DAIFMT_RIGHT_J:
900 pulse_len = frame_len / 2;
902 case SND_SOC_DAIFMT_LEFT_J:
904 pulse_len = frame_len / 2;
906 case SND_SOC_DAIFMT_DSP_A:
907 has_one_bit_delay = 1;
909 case SND_SOC_DAIFMT_DSP_B:
912 dev_err(dev, "Unsupported DAI format\n");
916 /* clock inversion */
917 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
918 case SND_SOC_DAIFMT_NB_NF:
919 is_frame_inv = is_i2s ? 1 : 0;
920 is_bclk_inv = is_i2s ? 1 : 0;
922 case SND_SOC_DAIFMT_IB_IF:
923 is_frame_inv = is_i2s ? 0 : 1;
924 is_bclk_inv = is_i2s ? 0 : 1;
926 case SND_SOC_DAIFMT_IB_NF:
927 is_frame_inv = is_i2s ? 1 : 0;
928 is_bclk_inv = is_i2s ? 0 : 1;
930 case SND_SOC_DAIFMT_NB_IF:
931 is_frame_inv = is_i2s ? 0 : 1;
932 is_bclk_inv = is_i2s ? 1 : 0;
935 dev_err(dev, "Unsupported DAI clock inversion\n");
939 cx2072x->dai_fmt = fmt;
941 reg1.r.rx_data_one_line = 1;
942 reg1.r.tx_data_one_line = 1;
945 i2s_right_slot = (frame_len / 2) / BITS_PER_SLOT;
946 i2s_right_pause_interval = (frame_len / 2) % BITS_PER_SLOT;
947 i2s_right_pause_pos = i2s_right_slot * BITS_PER_SLOT;
950 reg1.r.rx_ws_pol = is_frame_inv;
951 reg1.r.rx_ws_wid = pulse_len - 1;
953 reg1.r.rx_frm_len = frame_len / BITS_PER_SLOT - 1;
954 reg1.r.rx_sa_size = (sample_size / BITS_PER_SLOT) - 1;
956 reg1.r.tx_ws_pol = reg1.r.rx_ws_pol;
957 reg1.r.tx_ws_wid = pulse_len - 1;
958 reg1.r.tx_frm_len = reg1.r.rx_frm_len;
959 reg1.r.tx_sa_size = reg1.r.rx_sa_size;
961 reg2.r.tx_endian_sel = is_big_endian ? 0 : 1;
962 reg2.r.tx_dstart_dly = has_one_bit_delay;
964 reg3.r.rx_endian_sel = is_big_endian ? 0 : 1;
965 reg3.r.rx_dstart_dly = has_one_bit_delay;
968 reg2.r.tx_en_ch1 = 1;
969 reg2.r.tx_en_ch2 = 1;
970 reg2.r.tx_slot_1 = 0;
971 reg2.r.tx_slot_2 = i2s_right_slot;
972 reg3.r.rx_en_ch1 = 1;
973 reg3.r.rx_en_ch2 = 1;
974 reg3.r.rx_slot_1 = 0;
975 reg3.r.rx_slot_2 = i2s_right_slot;
976 reg6.r.rx_pause_start_pos = i2s_right_pause_pos;
977 reg6.r.rx_pause_cycles = i2s_right_pause_interval;
978 reg6.r.tx_pause_start_pos = i2s_right_pause_pos;
979 reg6.r.tx_pause_cycles = i2s_right_pause_interval;
981 reg2.r.tx_en_ch1 = cx2072x->tdm_tx_mask & 0x01 ? 1 : 0;
982 reg2.r.tx_en_ch2 = cx2072x->tdm_tx_mask & 0x02 ? 1 : 0;
983 reg2.r.tx_en_ch3 = cx2072x->tdm_tx_mask & 0x04 ? 1 : 0;
984 reg2.r.tx_en_ch4 = cx2072x->tdm_tx_mask & 0x08 ? 1 : 0;
985 reg2.r.tx_slot_1 = 0;
986 reg2.r.tx_slot_2 = slots_per_channel * 1;
987 reg2.r.tx_slot_3 = slots_per_channel * 2;
988 reg2.r.tx_slot_4 = slots_per_channel * 3;
990 reg3.r.rx_en_ch1 = cx2072x->tdm_rx_mask & 0x01 ? 1 : 0;
991 reg3.r.rx_en_ch2 = cx2072x->tdm_rx_mask & 0x02 ? 1 : 0;
992 reg3.r.rx_en_ch3 = cx2072x->tdm_rx_mask & 0x04 ? 1 : 0;
993 reg3.r.rx_en_ch4 = cx2072x->tdm_rx_mask & 0x08 ? 1 : 0;
994 reg3.r.rx_slot_1 = 0;
995 reg3.r.rx_slot_2 = slots_per_channel * 1;
996 reg3.r.rx_slot_3 = slots_per_channel * 2;
997 reg3.r.rx_slot_4 = slots_per_channel * 3;
999 regDBT2.r.i2s_bclk_invert = is_bclk_inv;
1001 reg1.r.rx_data_one_line = 1;
1002 reg1.r.tx_data_one_line = 1;
1004 #ifdef ENABLE_MIC_POP_WA
1008 /* Configure the BCLK output */
1009 bclk_rate = cx2072x->sample_rate * frame_len;
1010 reg5.r.i2s_pcm_clk_div_chan_en = 0;
1011 /* disable bclk output before setting new value */
1012 regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, 0);
1013 if (reg2.r.tx_master == 1) {
1014 /* Sets codec as Master mode */
1015 div = PLL_OUT_HZ_48;
1016 mod = do_div(div, bclk_rate);
1018 dev_err(dev, "Unsupported BCLK %dHz\n", bclk_rate);
1021 reg5.r.i2s_pcm_clk_div = div - 1;
1024 regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL1, reg1.ulval);
1025 regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL2, reg2.ulval);
1026 regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL3, reg3.ulval);
1027 regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL4, reg4.ulval);
1028 regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL6, reg6.ulval);
1029 regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, reg5.ulval);
1030 /* enable bclk and EAPD input */
1031 if (cx2072x->rev_id == CX2072X_REV_A2)
1032 regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST2,
1035 regmap_write(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST2,
1041 static void cx2072x_dsp_init(struct snd_soc_codec *codec)
1043 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1045 unsigned char *pcoef = &cx2072x_eq_coeff_array[0][0];
1047 regmap_write(cx2072x->regmap, CX2072X_EQ_ENABLE_BYPASS, 0x6e0f);
1049 for (i = 0; i < MAX_EQ_BAND; i++) {
1050 for (j = 0; j < 2; j++) {
1051 cx2072x_reg_bulk_write(codec, CX2072X_EQ_B0_COEFF,
1052 pcoef + (MAC_EQ_COEFF * i),
1054 band = i + (j << 3) + (1 << 6);
1055 regmap_write(cx2072x->regmap, CX2072X_EQ_BAND, band);
1060 cx2072x_reg_bulk_write(codec, CX2072X_SPKR_DRC_ENABLE_STEP,
1061 cx2072x_drc_array, MAX_DRC_REGS);
1064 static void cx2072x_update_dsp(struct snd_soc_codec *codec)
1066 unsigned int afg_reg;
1067 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1069 regmap_read(cx2072x->regmap, CX2072X_AFG_POWER_STATE, &afg_reg);
1071 if (!cx2072x->plbk_dsp_changed) {
1072 /* nothing change */
1076 if ((afg_reg & 0xf) != 0) {
1077 /* skip since device is on D3 mode */
1081 if (cx2072x->plbk_dsp_en && !cx2072x->plbk_dsp_init) {
1082 cx2072x_dsp_init(codec);
1083 cx2072x->plbk_dsp_init = true;
1086 if (cx2072x->plbk_dsp_en) {
1087 regmap_write(cx2072x->regmap, CX2072X_EQ_ENABLE_BYPASS,
1089 regmap_write(cx2072x->regmap, CX2072X_SPKR_DRC_ENABLE_STEP,
1092 /* By pass DRC and EQ */
1093 regmap_write(cx2072x->regmap, CX2072X_EQ_ENABLE_BYPASS,
1095 regmap_write(cx2072x->regmap, CX2072X_SPKR_DRC_ENABLE_STEP,
1098 cx2072x->plbk_dsp_changed = false;
1101 static int afg_power_ev(struct snd_soc_dapm_widget *w,
1102 struct snd_kcontrol *kcontrol, int event)
1104 #if (KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE)
1105 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1107 struct snd_soc_codec *codec = w->codec;
1109 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1112 case SND_SOC_DAPM_POST_PMU:
1113 regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST0,
1117 case SND_SOC_DAPM_PRE_PMD:
1118 regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST0,
1125 #ifdef ENABLE_MIC_POP_WA
1127 * This work will be called at ADC widget power on time.
1128 * to reduce initial mic pop noise caused by hardware
1131 static void cx2072x_anit_mic_pop_work(struct work_struct *work)
1133 struct snd_soc_dapm_context *dapm =
1134 container_of(work, struct snd_soc_dapm_context,
1136 #if (KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE)
1137 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
1139 struct snd_soc_codec *codec = dapm->codec;
1141 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1143 dev_dbg(cx2072x->dev, "Unmute I2S TX\n");
1146 regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL4,
1151 static int adc1_power_ev(struct snd_soc_dapm_widget *w,
1152 struct snd_kcontrol *kcontrol, int event)
1154 #ifdef ENABLE_MIC_POP_WA
1155 #if (KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE)
1156 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1158 struct snd_soc_codec *codec = w->codec;
1160 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1163 case SND_SOC_DAPM_POST_PMU:
1165 * Umute I2S TX after 300 ms to get around the mic
1168 schedule_delayed_work(&codec->dapm.delayed_work,
1169 msecs_to_jiffies(300));
1172 case SND_SOC_DAPM_POST_PMD:
1174 regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL4,
1182 static int portg_power_ev(struct snd_soc_dapm_widget *w,
1183 struct snd_kcontrol *kcontrol, int event)
1185 #if (KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE)
1186 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1188 struct snd_soc_codec *codec = w->codec;
1192 case SND_SOC_DAPM_POST_PMU:
1193 cx2072x_update_dsp(codec);
1201 static int cx2072x_plbk_dsp_info(struct snd_kcontrol *kcontrol,
1202 struct snd_ctl_elem_info *uinfo)
1204 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1206 uinfo->value.integer.min = 0;
1207 uinfo->value.integer.max = 1;
1211 static int cx2072x_plbk_dsp_get(struct snd_kcontrol *kcontrol,
1212 struct snd_ctl_elem_value *ucontrol)
1214 #if (KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE)
1215 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1217 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1219 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1221 ucontrol->value.integer.value[0] = cx2072x->plbk_dsp_en;
1226 static int cx2072x_plbk_dsp_put(struct snd_kcontrol *kcontrol,
1227 struct snd_ctl_elem_value *ucontrol)
1229 #if (KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE)
1230 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1232 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1234 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1235 const bool en_dsp = ucontrol->value.integer.value[0];
1237 if (ucontrol->value.integer.value[0] > 1)
1240 if (cx2072x->plbk_dsp_en != en_dsp) {
1241 cx2072x->plbk_dsp_en = en_dsp;
1242 cx2072x->plbk_dsp_changed = true;
1243 cx2072x_update_dsp(codec);
1248 #define CX2072X_PLBK_DSP_SWITCH(xname) {\
1249 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
1250 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
1251 .info = cx2072x_plbk_dsp_info, \
1252 .get = cx2072x_plbk_dsp_get, .put = cx2072x_plbk_dsp_put}
1254 static const struct snd_kcontrol_new cx2072x_snd_controls[] = {
1255 SOC_DOUBLE_R_TLV("PortD Boost", CX2072X_PORTD_GAIN_LEFT,
1256 CX2072X_PORTD_GAIN_RIGHT, 0, 3, 0, boost_tlv),
1257 SOC_DOUBLE_R_TLV("PortC Boost", CX2072X_PORTC_GAIN_LEFT,
1258 CX2072X_PORTC_GAIN_RIGHT, 0, 3, 0, boost_tlv),
1259 SOC_DOUBLE_R_TLV("PortB Boost", CX2072X_PORTB_GAIN_LEFT,
1260 CX2072X_PORTB_GAIN_RIGHT, 0, 3, 0, boost_tlv),
1262 SOC_DOUBLE_R_TLV("PortD ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_1,
1263 CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0, 0x4a, 0, adc_tlv),
1264 SOC_DOUBLE_R_TLV("PortC ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_2,
1265 CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0, 0x4a, 0, adc_tlv),
1266 SOC_DOUBLE_R_TLV("PortB ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_0,
1267 CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0, 0x4a, 0, adc_tlv),
1269 SOC_DOUBLE_R_TLV("DAC1 Volume", CX2072X_DAC1_AMP_GAIN_LEFT,
1270 CX2072X_DAC1_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
1272 SOC_DOUBLE_R("DAC1 Mute", CX2072X_DAC1_AMP_GAIN_LEFT,
1273 CX2072X_DAC1_AMP_GAIN_RIGHT, 7, 1, 0),
1275 SOC_DOUBLE_R_TLV("DAC2 Volume", CX2072X_DAC2_AMP_GAIN_LEFT,
1276 CX2072X_DAC2_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
1278 CX2072X_PLBK_DSP_SWITCH("Playback DSP Switch"),
1282 * cx2072x_hs_jack_report: Report jack notification to upper layer
1283 * @codec : pointer variable to codec having information related to codec
1284 * @jack : Pointer variable to snd_soc_jack having information of codec
1286 * @report : Provides informaton of whether it is headphone or microphone
1288 int cx2072x_hs_jack_report(struct snd_soc_codec *codec)
1291 unsigned int type = 0;
1293 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1295 regcache_cache_bypass(cx2072x->regmap, true);
1296 cx2072x->jack_state = CX_JACK_NONE;
1297 regmap_read(cx2072x->regmap, CX2072X_PORTA_PIN_SENSE, &jack);
1299 regmap_read(cx2072x->regmap, CX2072X_DIGITAL_TEST11, &type);
1300 regcache_cache_bypass(cx2072x->regmap, false);
1305 state |= SND_JACK_HEADSET;
1306 cx2072x->jack_state = CX_JACK_APPLE_HEADSET;
1308 state |= SND_JACK_BTN_0;
1309 } else if (type & 0x4) {
1310 state |= SND_JACK_HEADPHONE;
1311 cx2072x->jack_state = CX_JACK_NOKIE_HEADSET;
1313 state |= SND_JACK_HEADPHONE;
1314 cx2072x->jack_state = CX_JACK_HEADPHONE;
1317 /* clear interrupt */
1318 regmap_write(cx2072x->regmap, CX2072X_UM_INTERRUPT_CRTL_E, 0x12 << 24);
1320 dev_err(codec->dev, "CX2072X_HSDETECT type=0x%X,Jack state = %x\n",
1325 int cx2072x_jack_report(void)
1327 u32 state, old_state;
1335 old_state = cx2072x_hs_jack_report(cx2072x_codec);
1337 state = cx2072x_hs_jack_report(cx2072x_codec);
1338 } while (state != old_state);
1342 EXPORT_SYMBOL_GPL(cx2072x_jack_report);
1344 static int cx2072x_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1345 unsigned int rx_mask, int slots, int slot_width)
1347 struct snd_soc_codec *codec = dai->codec;
1348 struct cx2072x_priv *cx2072x = snd_soc_codec_get_drvdata(codec);
1367 cx2072x->tdm_rx_mask = rx_mask;
1368 cx2072x->tdm_tx_mask = tx_mask;
1369 cx2072x->tdm_slot_width = slot_width;
1370 cx2072x->tdm_slots = slots;
1374 static int cx2072x_hw_params(struct snd_pcm_substream *substream,
1375 struct snd_pcm_hw_params *params,
1376 struct snd_soc_dai *dai)
1378 struct snd_soc_codec *codec = dai->codec;
1379 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1380 struct device *dev = codec->dev;
1381 const unsigned int sample_rate = params_rate(params);
1382 int sample_size, frame_size;
1384 /* Data sizes if not using TDM */
1385 sample_size = params_width(params);
1387 if (sample_size < 0)
1390 frame_size = snd_soc_params_to_frame_size(params);
1394 if (cx2072x->bclk_ratio)
1395 frame_size = cx2072x->bclk_ratio;
1397 switch (sample_rate) {
1406 dev_err(dev, "Unsupported sample rate %d\n", sample_rate);
1410 dev_dbg(dev, "Sample size %d bits, frame = %d bits, rate = %d Hz\n",
1411 sample_size, frame_size, sample_rate);
1413 cx2072x->frame_size = frame_size;
1414 cx2072x->sample_size = sample_size;
1415 cx2072x->sample_rate = sample_rate;
1417 if (cx2072x->pll_changed) {
1418 cx2072x_config_pll(cx2072x);
1419 cx2072x->pll_changed = false;
1421 if (cx2072x->i2spcm_changed) {
1422 cx2072x_config_i2spcm(cx2072x);
1423 cx2072x->i2spcm_changed = false;
1428 static int cx2072x_digital_mute(struct snd_soc_dai *dai, int mute)
1433 static int cx2072x_set_dai_bclk_ratio(struct snd_soc_dai *dai,
1436 struct snd_soc_codec *codec = dai->codec;
1437 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1439 cx2072x->bclk_ratio = ratio;
1443 static int cx2072x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1444 unsigned int freq, int dir)
1446 struct snd_soc_codec *codec = dai->codec;
1447 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1448 struct device *dev = codec->dev;
1451 dev_dbg(dev, "MCLK: Switch to internal OSC\n");
1455 cx2072x->mclk = freq;
1458 case CX2072X_MCLK_EXTERNAL_PLL:
1459 dev_dbg(dev, "MCLK: Switch to external PLL\n");
1461 case CX2072X_MCLK_INTERNAL_OSC:
1462 dev_err(dev, "Unsupported DAI format\n");
1465 dev_dbg(dev, "the MCLK is not configured\n");
1472 static int cx2072x_set_dai_fmt(struct snd_soc_dai *dai,
1475 struct snd_soc_codec *codec = dai->codec;
1476 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1477 struct device *dev = codec->dev;
1479 /* set master/slave */
1480 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1481 case SND_SOC_DAIFMT_CBM_CFM:
1482 case SND_SOC_DAIFMT_CBS_CFS:
1485 dev_err(dev, "Unsupported DAI master mode\n");
1490 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1491 case SND_SOC_DAIFMT_I2S:
1492 case SND_SOC_DAIFMT_RIGHT_J:
1493 case SND_SOC_DAIFMT_LEFT_J:
1494 case SND_SOC_DAIFMT_DSP_A:
1495 case SND_SOC_DAIFMT_DSP_B:
1498 dev_err(dev, "Unsupported DAI format\n");
1502 /* clock inversion */
1503 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1504 case SND_SOC_DAIFMT_NB_NF:
1505 case SND_SOC_DAIFMT_IB_IF:
1506 case SND_SOC_DAIFMT_IB_NF:
1507 case SND_SOC_DAIFMT_NB_IF:
1510 dev_err(dev, "Unsupported DAI clock inversion\n");
1513 cx2072x->dai_fmt = fmt;
1518 static const char * const dac_enum_text[] = {
1519 "DAC1 Switch", "DAC2 Switch",
1522 static const struct soc_enum porta_dac_enum =
1523 SOC_ENUM_SINGLE(CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1525 static const struct snd_kcontrol_new porta_mux =
1526 SOC_DAPM_ENUM("PortA Mux", porta_dac_enum);
1528 static const struct soc_enum portg_dac_enum =
1529 SOC_ENUM_SINGLE(CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1531 static const struct snd_kcontrol_new portg_mux =
1532 SOC_DAPM_ENUM("PortG Mux", portg_dac_enum);
1534 static const struct soc_enum porte_dac_enum =
1535 SOC_ENUM_SINGLE(CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0, 2, dac_enum_text);
1537 static const struct snd_kcontrol_new porte_mux =
1538 SOC_DAPM_ENUM("PortE Mux", porte_dac_enum);
1540 static const char * const adc1in_sel_text[] = {
1541 "PortB Switch", "PortD Switch", "PortC Switch", "Widget15 Switch",
1542 "PortE Switch", "PortF Switch", "PortH Switch"
1545 static const struct soc_enum adc1in_sel_enum =
1546 SOC_ENUM_SINGLE(CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0, 7, adc1in_sel_text);
1548 static const struct snd_kcontrol_new adc1_mux =
1549 SOC_DAPM_ENUM("ADC1 Mux", adc1in_sel_enum);
1551 #define CX2072X_DAPM_SUPPLY_S(wname, wsubseq, wreg, wshift, wmask, won_val, \
1552 woff_val, wevent, wflags) \
1553 {.id = snd_soc_dapm_supply, .name = wname, .kcontrol_news = NULL, \
1554 .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1555 .on_val = won_val, .off_val = woff_val, \
1556 .subseq = wsubseq, .event = wevent, .event_flags = wflags}
1558 #define CX2072X_DAPM_SWITCH(wname, wreg, wshift, wmask, won_val, woff_val, \
1560 {.id = snd_soc_dapm_switch, .name = wname, .kcontrol_news = NULL, \
1561 .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1562 .on_val = won_val, .off_val = woff_val, \
1563 .event = wevent, .event_flags = wflags}
1565 #define CX2072X_DAPM_SWITCH(wname, wreg, wshift, wmask, won_val, woff_val, \
1567 {.id = snd_soc_dapm_switch, .name = wname, .kcontrol_news = NULL, \
1568 .num_kcontrols = 0, .reg = wreg, .shift = wshift, .mask = wmask, \
1569 .on_val = won_val, .off_val = woff_val, \
1570 .event = wevent, .event_flags = wflags}
1572 #define CX2072X_DAPM_REG_E(wid, wname, wreg, wshift, wmask, won_val, woff_val, \
1574 {.id = wid, .name = wname, .kcontrol_news = NULL, .num_kcontrols = 0, \
1575 .reg = wreg, .shift = wshift, .mask = wmask, \
1576 .on_val = won_val, .off_val = woff_val, \
1577 .event = wevent, .event_flags = wflags}
1579 static const struct snd_soc_dapm_widget cx2072x_dapm_widgets[] = {
1581 SND_SOC_DAPM_AIF_IN("In AIF", "Playback", 0, SND_SOC_NOPM, 0, 0),
1583 SND_SOC_DAPM_REG(snd_soc_dapm_dac, "DAC1", CX2072X_DAC1_POWER_STATE,
1584 0, 0xFFF, 0x00, 0x03),
1586 SND_SOC_DAPM_REG(snd_soc_dapm_dac, "DAC2", CX2072X_DAC2_POWER_STATE,
1587 0, 0xFFF, 0x00, 0x03),
1589 SND_SOC_DAPM_MUX("PortA Mux", SND_SOC_NOPM, 0, 0, &porta_mux),
1590 SND_SOC_DAPM_MUX("PortG Mux", SND_SOC_NOPM, 0, 0, &portg_mux),
1591 SND_SOC_DAPM_MUX("PortE Mux", SND_SOC_NOPM, 0, 0, &porte_mux),
1593 SND_SOC_DAPM_REG(snd_soc_dapm_switch, "PortA",
1594 CX2072X_PORTA_POWER_STATE, 0, 0xFFF, 0x00, 0x03),
1595 SND_SOC_DAPM_REG(snd_soc_dapm_switch, "PortG",
1596 CX2072X_PORTG_POWER_STATE, 0, 0xFFF, 0x00, 0x03),
1597 CX2072X_DAPM_SWITCH("PortG", CX2072X_PORTG_POWER_STATE, 0, 0xFF,
1598 0x00, 0x03, portg_power_ev, SND_SOC_DAPM_POST_PMU),
1600 CX2072X_DAPM_SUPPLY_S("AFG Power", 0, CX2072X_AFG_POWER_STATE,
1601 0, 0xFFF, 0x00, 0x03, afg_power_ev,
1602 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1604 SND_SOC_DAPM_OUTPUT("PORTA"),
1605 SND_SOC_DAPM_OUTPUT("PORTG"),
1606 SND_SOC_DAPM_OUTPUT("PORTE"),
1607 SND_SOC_DAPM_OUTPUT("AEC REF"),
1610 SND_SOC_DAPM_AIF_OUT("Out AIF", "Capture", 0, SND_SOC_NOPM, 0, 0),
1612 CX2072X_DAPM_REG_E(snd_soc_dapm_adc, "ADC1", CX2072X_ADC1_POWER_STATE,
1613 0, 0xFF, 0x00, 0x03, adc1_power_ev,
1614 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1616 SND_SOC_DAPM_REG(snd_soc_dapm_adc, "ADC2", CX2072X_ADC2_POWER_STATE,
1617 0, 0xFF, 0x00, 0x03),
1619 SND_SOC_DAPM_MUX("ADC1 Mux", SND_SOC_NOPM, 0, 0, &adc1_mux),
1621 SND_SOC_DAPM_REG(snd_soc_dapm_switch, "PortB",
1622 CX2072X_PORTB_POWER_STATE, 0, 0xFFF, 0x00, 0x03),
1623 SND_SOC_DAPM_REG(snd_soc_dapm_switch, "PortC",
1624 CX2072X_PORTC_POWER_STATE, 0, 0xFFF, 0x00, 0x03),
1625 SND_SOC_DAPM_REG(snd_soc_dapm_switch, "PortD",
1626 CX2072X_PORTD_POWER_STATE, 0, 0xFFF, 0x00, 0x03),
1627 SND_SOC_DAPM_REG(snd_soc_dapm_switch, "PortE",
1628 CX2072X_PORTE_POWER_STATE, 0, 0xFFF, 0x00, 0x03),
1629 SND_SOC_DAPM_REG(snd_soc_dapm_switch, "Widget15",
1630 CX2072X_MIXER_POWER_STATE, 0, 0xFFF, 0x00, 0x03),
1632 SND_SOC_DAPM_INPUT("PORTB"),
1633 SND_SOC_DAPM_INPUT("PORTC"),
1634 SND_SOC_DAPM_INPUT("PORTD"),
1636 SND_SOC_DAPM_MICBIAS("Headset Bias", CX2072X_ANALOG_TEST11, 1, 0),
1637 SND_SOC_DAPM_MICBIAS("PortD Mic Bias", CX2072X_PORTD_PIN_CTRL, 2, 0),
1638 SND_SOC_DAPM_MICBIAS("PortB Mic Bias", CX2072X_PORTB_PIN_CTRL, 2, 0),
1641 static const struct snd_soc_dapm_route cx2072x_intercon[] = {
1643 {"In AIF", NULL, "AFG Power"},
1644 {"DAC1", NULL, "In AIF"},
1645 {"DAC2", NULL, "In AIF"},
1646 {"PortA Mux", "DAC1 Switch", "DAC1"},
1647 {"PortA Mux", "DAC2 Switch", "DAC2"},
1648 {"PortG Mux", "DAC1 Switch", "DAC1"},
1649 {"PortG Mux", "DAC2 Switch", "DAC2"},
1650 {"PortE Mux", "DAC1 Switch", "DAC1"},
1651 {"PortE Mux", "DAC2 Switch", "DAC2"},
1652 {"Widget15", NULL, "DAC1"},
1653 {"Widget15", NULL, "DAC2"},
1654 {"PortA", NULL, "PortA Mux"},
1655 {"PortG", NULL, "PortG Mux"},
1656 {"PortE", NULL, "PortE Mux"},
1657 {"PORTA", NULL, "PortA"},
1658 {"PORTG", NULL, "PortG"},
1659 {"PORTE", NULL, "PortE"},
1662 {"PORTD", NULL, "PortD Mic Bias"},
1663 {"PortD", NULL, "PORTD"},
1664 {"PortC", NULL, "PORTC"},
1665 {"PortB", NULL, "PORTB"},
1666 {"ADC1 Mux", "PortD Switch", "PortD"},
1667 {"ADC1 Mux", "PortC Switch", "PortC"},
1668 {"ADC1 Mux", "PortB Switch", "PortB"},
1669 {"ADC1 Mux", "Widget15 Switch", "Widget15"},
1670 {"ADC1", NULL, "ADC1 Mux"},
1671 {"Out AIF", NULL, "ADC1"},
1672 {"Out AIF", NULL, "AFG Power"},
1673 {"AEC REF", NULL, "ADC1"},
1676 static void cx2072x_sw_reset(struct cx2072x_priv *cx2072x)
1678 regmap_write(cx2072x->regmap, CX2072X_AFG_FUNCTION_RESET, 0x01);
1679 regmap_write(cx2072x->regmap, CX2072X_AFG_FUNCTION_RESET, 0x01);
1682 static int cx2072x_init(struct snd_soc_codec *codec)
1684 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1686 cx2072x->plbk_dsp_changed = true;
1687 cx2072x->plbk_dsp_init = false;
1689 regmap_write(cx2072x->regmap, CX2072X_AFG_POWER_STATE, 0);
1690 regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_TEST15,
1691 0x00, 0x06); /* reduce the monitor time */
1693 cx2072x_config_headset_det(cx2072x);
1695 regmap_update_bits(cx2072x->regmap, CX2072X_PORTC_PIN_CTRL,
1696 0x20, 0x20); /* reduce the monitor time */
1698 /* enable bclk and EAPD input */
1699 if (cx2072x->rev_id == CX2072X_REV_A2)
1700 regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST2,
1706 static int cx2072x_set_bias_level(struct snd_soc_codec *codec,
1707 enum snd_soc_bias_level level)
1709 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1711 #if (KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE)
1712 const enum snd_soc_bias_level old_level =
1713 snd_soc_codec_get_bias_level(codec);
1715 const enum snd_soc_bias_level old_level = codec->dapm.bias_level;
1718 case SND_SOC_BIAS_ON:
1719 dev_dbg(cx2072x->dev, "SND_SOC_BIAS_ON\n");
1720 /* Enable Headset Mic Bias */
1721 if (cx2072x->is_biason == 0)
1722 cx2072x->is_biason = 1;
1724 case SND_SOC_BIAS_PREPARE:
1725 dev_dbg(cx2072x->dev, "SND_SOC_BIAS_PREPARE\n");
1726 if (old_level == SND_SOC_BIAS_STANDBY) {
1727 dev_dbg(cx2072x->dev,
1728 "SND_SOC_BIAS_STANDBY = > SND_SOC_BIAS_PREPARE\n");
1731 case SND_SOC_BIAS_STANDBY:
1732 dev_dbg(cx2072x->dev, "SND_SOC_BIAS_STANDBY\n");
1733 if (old_level == SND_SOC_BIAS_OFF) {
1734 if (cx2072x->mclk_clock) {
1735 dev_dbg(cx2072x->dev, "Turn on MCLK\n");
1736 ret = clk_prepare_enable(cx2072x->mclk_clock);
1740 dev_dbg(codec->dev, "cache only =>false\n");
1741 regcache_cache_only(cx2072x->regmap, false);
1742 dev_dbg(codec->dev, "regcache_sync\n");
1743 regmap_write(cx2072x->regmap,
1744 CX2072X_AFG_POWER_STATE, 0);
1745 regcache_sync(cx2072x->regmap);
1746 dev_dbg(codec->dev, "regcache_sync done\n");
1749 case SND_SOC_BIAS_OFF:
1750 dev_dbg(cx2072x->dev, "SND_SOC_BIAS_OFF\n");
1751 /* Shutdown codec completely */
1752 cx2072x_sw_reset(cx2072x);
1753 dev_dbg(codec->dev, "cache only\n");
1754 regcache_mark_dirty(cx2072x->regmap);
1755 regcache_cache_only(cx2072x->regmap, true);
1756 if (cx2072x->mclk_clock) {
1757 dev_dbg(cx2072x->dev, "Turn off MCLK\n");
1758 clk_disable_unprepare(cx2072x->mclk_clock);
1762 #if (KERNEL_VERSION(4, 0, 0) > LINUX_VERSION_CODE)
1763 codec->dapm.bias_level = level;
1768 static int cx2072x_probe(struct snd_soc_codec *codec)
1770 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1772 unsigned int ven_id;
1774 cx2072x_codec = codec;
1775 cx2072x->codec = codec;
1776 codec->control_data = cx2072x->regmap;
1778 cx2072x->mclk_clock = devm_clk_get(codec->dev, "mclk");
1779 if (PTR_ERR(cx2072x->mclk_clock) == -EPROBE_DEFER)
1780 return -EPROBE_DEFER;
1782 ret = clk_set_rate(cx2072x->mclk_clock, CX2072X_RATES_MCLK);
1784 dev_err(codec->dev, "clk_set_rate is fail!\n");
1788 ret = clk_prepare_enable(cx2072x->mclk_clock);
1790 dev_err(codec->dev, "clk_prepare_enable is fail!\n");
1794 cx2072x_init(codec);
1796 ret = regmap_register_patch(cx2072x->regmap, cx2072x_patch,
1797 ARRAY_SIZE(cx2072x_patch));
1801 dev_dbg(codec->dev, "codec version: 4.4.20\n");
1802 regmap_read(cx2072x->regmap, CX2072X_VENDOR_ID, &ven_id);
1803 regmap_read(cx2072x->regmap, CX2072X_REVISION_ID, &cx2072x->rev_id);
1804 dev_err(codec->dev, "codec version: %08x,%08x\n", ven_id,
1806 #ifdef ENABLE_MIC_POP_WA
1807 INIT_DELAYED_WORK(&codec->dapm.delayed_work,
1808 cx2072x_anit_mic_pop_work);
1813 static int cx2072x_remove(struct snd_soc_codec *codec)
1815 struct cx2072x_priv *cx2072x = get_cx2072x_priv(codec);
1816 /* power off device */
1817 cx2072x_set_bias_level(cx2072x->codec, SND_SOC_BIAS_OFF);
1822 static int cx2072x_runtime_suspend(struct device *dev)
1824 struct cx2072x_priv *cx2072x = dev_get_drvdata(dev);
1826 dev_dbg(cx2072x->codec->dev, "%s----%d\n", __func__, __LINE__);
1827 cx2072x_set_bias_level(cx2072x->codec, SND_SOC_BIAS_OFF);
1832 static int cx2072x_runtime_resume(struct device *dev)
1834 struct cx2072x_priv *cx2072x = dev_get_drvdata(dev);
1836 dev_dbg(cx2072x->codec->dev, "%s----%d\n", __func__, __LINE__);
1837 cx2072x_set_bias_level(cx2072x->codec, SND_SOC_BIAS_STANDBY);
1841 #define cx2072x_suspend NULL
1842 #define cx2072x_resume NULL
1845 static bool cx2072x_readable_register(struct device *dev, unsigned int reg)
1848 case CX2072X_VENDOR_ID:
1849 case CX2072X_REVISION_ID:
1850 case CX2072X_CURRENT_BCLK_FREQUENCY:
1851 case CX2072X_AFG_POWER_STATE:
1852 case CX2072X_UM_RESPONSE:
1853 case CX2072X_GPIO_DATA:
1854 case CX2072X_GPIO_ENABLE:
1855 case CX2072X_GPIO_DIRECTION:
1856 case CX2072X_GPIO_WAKE:
1857 case CX2072X_GPIO_UM_ENABLE:
1858 case CX2072X_GPIO_STICKY_MASK:
1859 case CX2072X_DAC1_CONVERTER_FORMAT:
1860 case CX2072X_DAC1_AMP_GAIN_RIGHT:
1861 case CX2072X_DAC1_AMP_GAIN_LEFT:
1862 case CX2072X_DAC1_POWER_STATE:
1863 case CX2072X_DAC1_CONVERTER_STREAM_CHANNEL:
1864 case CX2072X_DAC1_EAPD_ENABLE:
1865 case CX2072X_DAC2_CONVERTER_FORMAT:
1866 case CX2072X_DAC2_AMP_GAIN_RIGHT:
1867 case CX2072X_DAC2_AMP_GAIN_LEFT:
1868 case CX2072X_DAC2_POWER_STATE:
1869 case CX2072X_DAC2_CONVERTER_STREAM_CHANNEL:
1870 case CX2072X_ADC1_CONVERTER_FORMAT:
1871 case CX2072X_ADC1_AMP_GAIN_RIGHT_0:
1872 case CX2072X_ADC1_AMP_GAIN_LEFT_0:
1873 case CX2072X_ADC1_AMP_GAIN_RIGHT_1:
1874 case CX2072X_ADC1_AMP_GAIN_LEFT_1:
1875 case CX2072X_ADC1_AMP_GAIN_RIGHT_2:
1876 case CX2072X_ADC1_AMP_GAIN_LEFT_2:
1877 case CX2072X_ADC1_AMP_GAIN_RIGHT_3:
1878 case CX2072X_ADC1_AMP_GAIN_LEFT_3:
1879 case CX2072X_ADC1_AMP_GAIN_RIGHT_4:
1880 case CX2072X_ADC1_AMP_GAIN_LEFT_4:
1881 case CX2072X_ADC1_AMP_GAIN_RIGHT_5:
1882 case CX2072X_ADC1_AMP_GAIN_LEFT_5:
1883 case CX2072X_ADC1_AMP_GAIN_RIGHT_6:
1884 case CX2072X_ADC1_AMP_GAIN_LEFT_6:
1885 case CX2072X_ADC1_CONNECTION_SELECT_CONTROL:
1886 case CX2072X_ADC1_POWER_STATE:
1887 case CX2072X_ADC1_CONVERTER_STREAM_CHANNEL:
1888 case CX2072X_ADC2_CONVERTER_FORMAT:
1889 case CX2072X_ADC2_AMP_GAIN_RIGHT_0:
1890 case CX2072X_ADC2_AMP_GAIN_LEFT_0:
1891 case CX2072X_ADC2_AMP_GAIN_RIGHT_1:
1892 case CX2072X_ADC2_AMP_GAIN_LEFT_1:
1893 case CX2072X_ADC2_AMP_GAIN_RIGHT_2:
1894 case CX2072X_ADC2_AMP_GAIN_LEFT_2:
1895 case CX2072X_ADC2_CONNECTION_SELECT_CONTROL:
1896 case CX2072X_ADC2_POWER_STATE:
1897 case CX2072X_ADC2_CONVERTER_STREAM_CHANNEL:
1898 case CX2072X_PORTA_CONNECTION_SELECT_CTRL:
1899 case CX2072X_PORTA_POWER_STATE:
1900 case CX2072X_PORTA_PIN_CTRL:
1901 case CX2072X_PORTA_UNSOLICITED_RESPONSE:
1902 case CX2072X_PORTA_PIN_SENSE:
1903 case CX2072X_PORTA_EAPD_BTL:
1904 case CX2072X_PORTB_POWER_STATE:
1905 case CX2072X_PORTB_PIN_CTRL:
1906 case CX2072X_PORTB_UNSOLICITED_RESPONSE:
1907 case CX2072X_PORTB_PIN_SENSE:
1908 case CX2072X_PORTB_EAPD_BTL:
1909 case CX2072X_PORTB_GAIN_RIGHT:
1910 case CX2072X_PORTB_GAIN_LEFT:
1911 case CX2072X_PORTC_POWER_STATE:
1912 case CX2072X_PORTC_PIN_CTRL:
1913 case CX2072X_PORTC_GAIN_RIGHT:
1914 case CX2072X_PORTC_GAIN_LEFT:
1915 case CX2072X_PORTD_POWER_STATE:
1916 case CX2072X_PORTD_PIN_CTRL:
1917 case CX2072X_PORTD_UNSOLICITED_RESPONSE:
1918 case CX2072X_PORTD_PIN_SENSE:
1919 case CX2072X_PORTD_GAIN_RIGHT:
1920 case CX2072X_PORTD_GAIN_LEFT:
1921 case CX2072X_PORTE_CONNECTION_SELECT_CTRL:
1922 case CX2072X_PORTE_POWER_STATE:
1923 case CX2072X_PORTE_PIN_CTRL:
1924 case CX2072X_PORTE_UNSOLICITED_RESPONSE:
1925 case CX2072X_PORTE_PIN_SENSE:
1926 case CX2072X_PORTE_EAPD_BTL:
1927 case CX2072X_PORTE_GAIN_RIGHT:
1928 case CX2072X_PORTE_GAIN_LEFT:
1929 case CX2072X_PORTF_POWER_STATE:
1930 case CX2072X_PORTF_PIN_CTRL:
1931 case CX2072X_PORTF_UNSOLICITED_RESPONSE:
1932 case CX2072X_PORTF_PIN_SENSE:
1933 case CX2072X_PORTF_GAIN_RIGHT:
1934 case CX2072X_PORTF_GAIN_LEFT:
1935 case CX2072X_PORTG_POWER_STATE:
1936 case CX2072X_PORTG_PIN_CTRL:
1937 case CX2072X_PORTG_CONNECTION_SELECT_CTRL:
1938 case CX2072X_PORTG_EAPD_BTL:
1939 case CX2072X_PORTM_POWER_STATE:
1940 case CX2072X_PORTM_PIN_CTRL:
1941 case CX2072X_PORTM_CONNECTION_SELECT_CTRL:
1942 case CX2072X_PORTM_EAPD_BTL:
1943 case CX2072X_MIXER_POWER_STATE:
1944 case CX2072X_MIXER_GAIN_RIGHT_0:
1945 case CX2072X_MIXER_GAIN_LEFT_0:
1946 case CX2072X_MIXER_GAIN_RIGHT_1:
1947 case CX2072X_MIXER_GAIN_LEFT_1:
1948 case CX2072X_EQ_ENABLE_BYPASS:
1949 case CX2072X_EQ_B0_COEFF:
1950 case CX2072X_EQ_B1_COEFF:
1951 case CX2072X_EQ_B2_COEFF:
1952 case CX2072X_EQ_A1_COEFF:
1953 case CX2072X_EQ_A2_COEFF:
1954 case CX2072X_EQ_G_COEFF:
1955 case CX2072X_SPKR_DRC_ENABLE_STEP:
1956 case CX2072X_SPKR_DRC_CONTROL:
1957 case CX2072X_SPKR_DRC_TEST:
1958 case CX2072X_DIGITAL_BIOS_TEST0:
1959 case CX2072X_DIGITAL_BIOS_TEST2:
1960 case CX2072X_I2SPCM_CONTROL1:
1961 case CX2072X_I2SPCM_CONTROL2:
1962 case CX2072X_I2SPCM_CONTROL3:
1963 case CX2072X_I2SPCM_CONTROL4:
1964 case CX2072X_I2SPCM_CONTROL5:
1965 case CX2072X_I2SPCM_CONTROL6:
1966 case CX2072X_UM_INTERRUPT_CRTL_E:
1967 case CX2072X_CODEC_TEST2:
1968 case CX2072X_CODEC_TEST20:
1969 case CX2072X_CODEC_TEST26:
1970 case CX2072X_ANALOG_TEST4:
1971 case CX2072X_ANALOG_TEST5:
1972 case CX2072X_ANALOG_TEST6:
1973 case CX2072X_ANALOG_TEST7:
1974 case CX2072X_ANALOG_TEST8:
1975 case CX2072X_ANALOG_TEST9:
1976 case CX2072X_ANALOG_TEST10:
1977 case CX2072X_ANALOG_TEST11:
1978 case CX2072X_ANALOG_TEST12:
1979 case CX2072X_ANALOG_TEST13:
1980 case CX2072X_DIGITAL_TEST0:
1981 case CX2072X_DIGITAL_TEST1:
1982 case CX2072X_DIGITAL_TEST11:
1983 case CX2072X_DIGITAL_TEST12:
1984 case CX2072X_DIGITAL_TEST15:
1985 case CX2072X_DIGITAL_TEST16:
1986 case CX2072X_DIGITAL_TEST17:
1987 case CX2072X_DIGITAL_TEST18:
1988 case CX2072X_DIGITAL_TEST19:
1989 case CX2072X_DIGITAL_TEST20:
1996 static bool cx2072x_volatile_register(struct device *dev, unsigned int reg)
1999 case CX2072X_VENDOR_ID:
2000 case CX2072X_REVISION_ID:
2001 case CX2072X_UM_INTERRUPT_CRTL_E:
2002 case CX2072X_DIGITAL_TEST11:
2003 case CX2072X_PORTA_PIN_SENSE:
2004 case CX2072X_PORTB_PIN_SENSE:
2005 case CX2072X_PORTD_PIN_SENSE:
2006 case CX2072X_PORTE_PIN_SENSE:
2007 case CX2072X_PORTF_PIN_SENSE:
2008 case CX2072X_EQ_G_COEFF:
2009 case CX2072X_EQ_BAND:
2016 static struct snd_soc_codec_driver soc_codec_driver_cx2072x = {
2017 .probe = cx2072x_probe,
2018 .remove = cx2072x_remove,
2019 .set_bias_level = cx2072x_set_bias_level,
2020 .suspend_bias_off = true,
2021 .idle_bias_off = true,
2022 #if (KERNEL_VERSION(4, 9, 0) <= LINUX_VERSION_CODE)
2023 .component_driver = {
2024 .controls = cx2072x_snd_controls,
2025 .num_controls = ARRAY_SIZE(cx2072x_snd_controls),
2026 .dapm_widgets = cx2072x_dapm_widgets,
2027 .num_dapm_widgets = ARRAY_SIZE(cx2072x_dapm_widgets),
2028 .dapm_routes = cx2072x_intercon,
2029 .num_dapm_routes = ARRAY_SIZE(cx2072x_intercon),
2032 .controls = cx2072x_snd_controls,
2033 .num_controls = ARRAY_SIZE(cx2072x_snd_controls),
2034 .dapm_widgets = cx2072x_dapm_widgets,
2035 .num_dapm_widgets = ARRAY_SIZE(cx2072x_dapm_widgets),
2036 .dapm_routes = cx2072x_intercon,
2037 .num_dapm_routes = ARRAY_SIZE(cx2072x_intercon),
2044 static struct snd_soc_dai_ops cx2072x_dai_ops = {
2045 .set_sysclk = cx2072x_set_dai_sysclk,
2046 .set_fmt = cx2072x_set_dai_fmt,
2047 .set_tdm_slot = cx2072x_set_tdm_slot,
2048 .hw_params = cx2072x_hw_params,
2049 .digital_mute = cx2072x_digital_mute,
2050 .set_bclk_ratio = cx2072x_set_dai_bclk_ratio,
2056 static struct snd_soc_dai_driver soc_codec_cx2072x_dai[] = {
2057 { /* playback and capture */
2058 .name = "cx2072x-hifi",
2059 .id = CX2072X_DAI_HIFI,
2061 .stream_name = "Playback",
2064 .rates = CX2072X_RATES_DSP, /* CX2072X_RATES */
2065 .formats = CX2072X_FORMATS,
2068 .stream_name = "Capture",
2071 .rates = CX2072X_RATES_DSP,
2072 .formats = CX2072X_FORMATS,
2074 .ops = &cx2072x_dai_ops,
2075 .symmetric_rates = 1,
2077 { /* plabayck only, return echo reference through I2S TX */
2078 .name = "cx2072x-dsp",
2079 .id = CX2072X_DAI_DSP,
2081 .stream_name = "Playback",
2084 .rates = CX2072X_RATES_DSP,
2085 .formats = CX2072X_FORMATS,
2087 .ops = &cx2072x_dai_ops,
2090 EXPORT_SYMBOL_GPL(soc_codec_cx2072x_dai);
2092 static const struct regmap_config cx2072x_regmap = {
2095 .max_register = CX2072X_REG_MAX,
2096 .reg_defaults = cx2072x_reg_defaults,
2097 .num_reg_defaults = ARRAY_SIZE(cx2072x_reg_defaults),
2098 .cache_type = REGCACHE_RBTREE,
2099 .readable_reg = cx2072x_readable_register,
2100 .volatile_reg = cx2072x_volatile_register,
2101 .reg_read = cx2072x_reg_read,
2102 .reg_write = cx2072x_reg_write,
2105 static void cx2072x_enable_spk(struct cx2072x_priv *cx2072x, bool enable)
2109 level = enable ? cx2072x->spk_active_level : !cx2072x->spk_active_level;
2110 gpio_set_value(cx2072x->spk_ctl_gpio, level);
2113 static int cx2072x_i2c_probe(struct i2c_client *i2c,
2114 const struct i2c_device_id *id)
2117 struct cx2072x_priv *cx2072x;
2118 enum of_gpio_flags flags;
2119 struct device_node *np = i2c->dev.of_node;
2121 dev_dbg(&i2c->dev, "CX2072X codec driver i2c probe() is called\n");
2122 cx2072x = (struct cx2072x_priv *)devm_kzalloc(
2123 &i2c->dev, sizeof(struct cx2072x_priv), GFP_KERNEL);
2125 dev_err(&i2c->dev, "Out of memory!\n");
2129 mutex_init(&cx2072x->lock);
2131 cx2072x->regmap = devm_regmap_init(&i2c->dev, NULL, i2c,
2133 if (IS_ERR(&cx2072x->regmap)) {
2134 ret = PTR_ERR(cx2072x->regmap);
2135 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
2138 i2c_set_clientdata(i2c, cx2072x);
2140 cx2072x->spk_ctl_gpio = of_get_named_gpio_flags(np, "spk-con-gpio",
2143 if (cx2072x->spk_ctl_gpio < 0) {
2144 dev_info(&i2c->dev, "Can not read property spk_ctl_gpio\n");
2145 cx2072x->spk_ctl_gpio = INVALID_GPIO;
2147 cx2072x->spk_active_level = !(flags & OF_GPIO_ACTIVE_LOW);
2148 ret = devm_gpio_request_one(&i2c->dev, cx2072x->spk_ctl_gpio,
2149 GPIOF_DIR_OUT, NULL);
2151 dev_err(&i2c->dev, "Failed to request spk_ctl_gpio\n");
2154 cx2072x_enable_spk(cx2072x, true);
2157 cx2072x->dev = &i2c->dev;
2158 cx2072x->pll_changed = true;
2159 cx2072x->i2spcm_changed = true;
2162 * sets the frame size to
2163 * Frame size = number of channel * sample width
2165 cx2072x->bclk_ratio = 0;
2167 ret = snd_soc_register_codec(cx2072x->dev,
2168 &soc_codec_driver_cx2072x,
2169 soc_codec_cx2072x_dai,
2170 ARRAY_SIZE(soc_codec_cx2072x_dai));
2172 dev_err(cx2072x->dev, "Failed to register codec: %d\n", ret);
2174 dev_dbg(cx2072x->dev, "%s: Register codec.\n", __func__);
2179 static int cx2072x_i2c_remove(struct i2c_client *client)
2181 snd_soc_unregister_codec(&client->dev);
2185 static void cx2072x_i2c_shutdown(struct i2c_client *client)
2187 struct cx2072x_priv *cx2072x = i2c_get_clientdata(client);
2189 cx2072x_set_bias_level(cx2072x->codec, SND_SOC_BIAS_OFF);
2192 const struct dev_pm_ops cx2072x_pm_ops = {
2193 SET_RUNTIME_PM_OPS(cx2072x_runtime_suspend, cx2072x_runtime_resume,
2197 static const struct i2c_device_id cx2072x_i2c_id[] = {
2203 MODULE_DEVICE_TABLE(i2c, cx2072x_i2c_id);
2205 static const struct of_device_id cx2072x_of_match[] = {
2206 { .compatible = "cnxt,cx20721", },
2207 { .compatible = "cnxt,cx20723", },
2208 { .compatible = "cnxt,cx7601", },
2211 MODULE_DEVICE_TABLE(of, cx2072x_of_match);
2213 static struct acpi_device_id cx2072x_acpi_match[] = {
2217 MODULE_DEVICE_TABLE(acpi, cx2072x_acpi_match);
2220 static struct i2c_driver cx2072x_i2c_driver = {
2221 .probe = cx2072x_i2c_probe,
2222 .remove = cx2072x_i2c_remove,
2223 .shutdown = cx2072x_i2c_shutdown,
2224 .id_table = cx2072x_i2c_id,
2227 .owner = THIS_MODULE,
2228 .of_match_table = cx2072x_of_match,
2230 .acpi_match_table = ACPI_PTR(cx2072x_acpi_match),
2232 .pm = &cx2072x_pm_ops,
2236 module_i2c_driver(cx2072x_i2c_driver);
2238 MODULE_DESCRIPTION("ASoC cx2072x Codec Driver");
2239 MODULE_AUTHOR("Simon Ho <simon.ho@conexant.com>");
2240 MODULE_LICENSE("GPL");