2 * es8316.c -- es8316 ALSA SoC audio driver
3 * Copyright Everest Semiconductor Co.,Ltd
5 * Author: David Yang <yangxiaohua@everest-semi.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/spi/spi.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/of_gpio.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/tlv.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <linux/proc_fs.h>
32 #include <linux/gpio.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
35 #include <linux/regmap.h>
38 #define INVALID_GPIO -1
41 #define es8316_DEF_VOL 0x1e
43 static const struct reg_default es8316_reg_defaults[] = {
44 {0x00, 0x03}, {0x01, 0x03}, {0x02, 0x00}, {0x03, 0x20},
45 {0x04, 0x11}, {0x05, 0x00}, {0x06, 0x11}, {0x07, 0x00},
46 {0x08, 0x00}, {0x09, 0x01}, {0x0a, 0x00}, {0x0b, 0x00},
47 {0x0c, 0xf8}, {0x0d, 0x3f}, {0x0e, 0x00}, {0x0f, 0x00},
48 {0x10, 0x01}, {0x11, 0xfc}, {0x12, 0x28}, {0x13, 0x00},
49 {0x14, 0x00}, {0x15, 0x33}, {0x16, 0x00}, {0x17, 0x00},
50 {0x18, 0x88}, {0x19, 0x06}, {0x1a, 0x22}, {0x1b, 0x03},
51 {0x1c, 0x0f}, {0x1d, 0x00}, {0x1e, 0x80}, {0x1f, 0x80},
52 {0x20, 0x00}, {0x21, 0x00}, {0x22, 0xc0}, {0x23, 0x00},
53 {0x24, 0x01}, {0x25, 0x08}, {0x26, 0x10}, {0x27, 0xc0},
54 {0x28, 0x00}, {0x29, 0x1c}, {0x2a, 0x00}, {0x2b, 0xb0},
55 {0x2c, 0x32}, {0x2d, 0x03}, {0x2e, 0x00}, {0x2f, 0x11},
56 {0x30, 0x10}, {0x31, 0x00}, {0x32, 0x00}, {0x33, 0xc0},
57 {0x34, 0xc0}, {0x35, 0x1f}, {0x36, 0xf7}, {0x37, 0xfd},
58 {0x38, 0xff}, {0x39, 0x1f}, {0x3a, 0xf7}, {0x3b, 0xfd},
59 {0x3c, 0xff}, {0x3d, 0x1f}, {0x3e, 0xf7}, {0x3f, 0xfd},
60 {0x40, 0xff}, {0x41, 0x1f}, {0x42, 0xf7}, {0x43, 0xfd},
61 {0x44, 0xff}, {0x45, 0x1f}, {0x46, 0xf7}, {0x47, 0xfd},
62 {0x48, 0xff}, {0x49, 0x1f}, {0x4a, 0xf7}, {0x4b, 0xfd},
63 {0x4c, 0xff}, {0x4d, 0x00}, {0x4e, 0x00}, {0x4f, 0xff},
64 {0x50, 0x00}, {0x51, 0x00}, {0x52, 0x00}, {0x53, 0x00},
67 /* codec private data */
69 struct regmap *regmap;
70 unsigned int dmic_amic;
72 struct snd_pcm_hw_constraint_list *sysclk_constraints;
76 struct delayed_work work;
82 bool spk_active_level;
89 * write value 0xff to reg0x00, the chip will be in reset mode
90 * then, writer 0x00 to reg0x00, unreset the chip
92 static int es8316_reset(struct snd_soc_codec *codec)
94 snd_soc_write(codec, ES8316_RESET_REG00, 0x3F);
95 usleep_range(5000, 5500);
96 return snd_soc_write(codec, ES8316_RESET_REG00, 0x03);
99 static void es8316_enable_spk(struct es8316_priv *es8316, bool enable)
103 level = enable ? es8316->spk_active_level : !es8316->spk_active_level;
104 gpio_set_value(es8316->spk_ctl_gpio, level);
107 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9600, 50, 1);
108 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -9600, 50, 1);
109 static const DECLARE_TLV_DB_SCALE(hpmixer_gain_tlv, -1200, 150, 0);
110 static const DECLARE_TLV_DB_SCALE(mic_bst_tlv, 0, 1200, 0);
112 static unsigned int linin_pga_tlv[] = {
113 TLV_DB_RANGE_HEAD(12),
114 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
115 1, 1, TLV_DB_SCALE_ITEM(300, 0, 0),
116 2, 2, TLV_DB_SCALE_ITEM(600, 0, 0),
117 3, 3, TLV_DB_SCALE_ITEM(900, 0, 0),
118 4, 4, TLV_DB_SCALE_ITEM(1200, 0, 0),
119 5, 5, TLV_DB_SCALE_ITEM(1500, 0, 0),
120 6, 6, TLV_DB_SCALE_ITEM(1800, 0, 0),
121 7, 7, TLV_DB_SCALE_ITEM(2100, 0, 0),
122 8, 8, TLV_DB_SCALE_ITEM(2400, 0, 0),
125 static unsigned int hpout_vol_tlv[] = {
126 TLV_DB_RANGE_HEAD(1),
127 0, 3, TLV_DB_SCALE_ITEM(-4800, 1200, 0),
130 static const char *const alc_func_txt[] = { "Off", "On" };
132 static const struct soc_enum alc_func =
133 SOC_ENUM_SINGLE(ES8316_ADC_ALC1_REG29, 6, 2, alc_func_txt);
135 static const char *const ng_type_txt[] = {
136 "Constant PGA Gain", "Mute ADC Output" };
138 static const struct soc_enum ng_type =
139 SOC_ENUM_SINGLE(ES8316_ADC_ALC6_REG2E, 6, 2, ng_type_txt);
141 static const char *const adcpol_txt[] = { "Normal", "Invert" };
143 static const struct soc_enum adcpol =
144 SOC_ENUM_SINGLE(ES8316_ADC_MUTE_REG26, 1, 2, adcpol_txt);
146 static const char *const dacpol_txt[] = {
147 "Normal", "R Invert", "L Invert", "L + R Invert" };
149 static const struct soc_enum dacpol =
150 SOC_ENUM_SINGLE(ES8316_DAC_SET1_REG30, 0, 4, dacpol_txt);
152 static const struct snd_kcontrol_new es8316_snd_controls[] = {
154 SOC_DOUBLE_TLV("HP Playback Volume", ES8316_CPHP_ICAL_VOL_REG18,
155 4, 0, 0, 1, hpout_vol_tlv),
156 /* HPMIXER VOLUME Control */
157 SOC_DOUBLE_TLV("HPMixer Gain", ES8316_HPMIX_VOL_REG16,
158 0, 4, 7, 0, hpmixer_gain_tlv),
160 /* DAC Digital controls */
161 SOC_DOUBLE_R_TLV("DAC Playback Volume", ES8316_DAC_VOLL_REG33,
162 ES8316_DAC_VOLR_REG34, 0, 0xC0, 1, dac_vol_tlv),
164 SOC_SINGLE("Enable DAC Soft Ramp", ES8316_DAC_SET1_REG30, 4, 1, 1),
165 SOC_SINGLE("DAC Soft Ramp Rate", ES8316_DAC_SET1_REG30, 2, 4, 0),
167 SOC_ENUM("Playback Polarity", dacpol),
168 SOC_SINGLE("DAC Notch Filter", ES8316_DAC_SET2_REG31, 6, 1, 0),
169 SOC_SINGLE("DAC Double Fs Mode", ES8316_DAC_SET2_REG31, 7, 1, 0),
170 SOC_SINGLE("DAC Volume Control-LeR", ES8316_DAC_SET2_REG31, 2, 1, 0),
171 SOC_SINGLE("DAC Stereo Enhancement", ES8316_DAC_SET3_REG32, 0, 7, 0),
173 /* +20dB D2SE PGA Control */
174 SOC_SINGLE_TLV("MIC Boost", ES8316_ADC_D2SEPGA_REG24,
175 0, 1, 0, mic_bst_tlv),
176 /* 0-+24dB Lineinput PGA Control */
177 SOC_SINGLE_TLV("Input PGA", ES8316_ADC_PGAGAIN_REG23,
178 4, 8, 0, linin_pga_tlv),
180 /* ADC Digital Control */
181 SOC_SINGLE_TLV("ADC Capture Volume", ES8316_ADC_VOLUME_REG27,
182 0, 0xC0, 1, adc_vol_tlv),
183 SOC_SINGLE("ADC Soft Ramp", ES8316_ADC_MUTE_REG26, 4, 1, 0),
184 SOC_ENUM("Capture Polarity", adcpol),
185 SOC_SINGLE("ADC Double FS Mode", ES8316_ADC_DMIC_REG25, 4, 1, 0),
186 /* ADC ALC Control */
187 SOC_SINGLE("ALC Capture Target Volume",
188 ES8316_ADC_ALC3_REG2B, 4, 10, 0),
189 SOC_SINGLE("ALC Capture Max PGA", ES8316_ADC_ALC1_REG29, 0, 28, 0),
190 SOC_SINGLE("ALC Capture Min PGA", ES8316_ADC_ALC2_REG2A, 0, 28, 0),
191 SOC_ENUM("ALC Capture Function", alc_func),
192 SOC_SINGLE("ALC Capture Hold Time", ES8316_ADC_ALC3_REG2B, 0, 10, 0),
193 SOC_SINGLE("ALC Capture Decay Time", ES8316_ADC_ALC4_REG2C, 4, 10, 0),
194 SOC_SINGLE("ALC Capture Attack Time", ES8316_ADC_ALC4_REG2C, 0, 10, 0),
195 SOC_SINGLE("ALC Capture NG Threshold", ES8316_ADC_ALC6_REG2E, 0, 31, 0),
196 SOC_ENUM("ALC Capture NG Type", ng_type),
197 SOC_SINGLE("ALC Capture NG Switch", ES8316_ADC_ALC6_REG2E, 5, 1, 0),
200 /* Analog Input MUX */
201 static const char * const es8316_analog_in_txt[] = {
204 "lin1-rin1 with 20db Boost",
205 "lin2-rin2 with 20db Boost"
208 static const unsigned int es8316_analog_in_values[] = { 0, 1, 2, 3 };
210 static const struct soc_enum es8316_analog_input_enum =
211 SOC_VALUE_ENUM_SINGLE(ES8316_ADC_PDN_LINSEL_REG22, 4, 3,
212 ARRAY_SIZE(es8316_analog_in_txt),
213 es8316_analog_in_txt,
214 es8316_analog_in_values);
216 static const struct snd_kcontrol_new es8316_analog_in_mux_controls =
217 SOC_DAPM_ENUM("Route", es8316_analog_input_enum);
220 static const char * const es8316_dmic_txt[] = {
222 "dmic data at high level",
223 "dmic data at low level",
226 static const unsigned int es8316_dmic_values[] = { 0, 1, 2 };
228 static const struct soc_enum es8316_dmic_src_enum =
229 SOC_VALUE_ENUM_SINGLE(ES8316_ADC_DMIC_REG25, 0, 3,
230 ARRAY_SIZE(es8316_dmic_txt),
234 static const struct snd_kcontrol_new es8316_dmic_src_controls =
235 SOC_DAPM_ENUM("Route", es8316_dmic_src_enum);
238 static const char *const es8316_hpmux_texts[] = {
241 "lin-rin with Boost",
242 "lin-rin with Boost and PGA"
245 static const unsigned int es8316_hpmux_values[] = { 0, 1, 2, 3 };
247 static const struct soc_enum es8316_left_hpmux_enum =
248 SOC_VALUE_ENUM_SINGLE(ES8316_HPMIX_SEL_REG13, 4, 7,
249 ARRAY_SIZE(es8316_hpmux_texts),
251 es8316_hpmux_values);
253 static const struct snd_kcontrol_new es8316_left_hpmux_controls =
254 SOC_DAPM_ENUM("Route", es8316_left_hpmux_enum);
256 static const struct soc_enum es8316_right_hpmux_enum =
257 SOC_VALUE_ENUM_SINGLE(ES8316_HPMIX_SEL_REG13, 0, 7,
258 ARRAY_SIZE(es8316_hpmux_texts),
260 es8316_hpmux_values);
262 static const struct snd_kcontrol_new es8316_right_hpmux_controls =
263 SOC_DAPM_ENUM("Route", es8316_right_hpmux_enum);
265 /* headphone Output Mixer */
266 static const struct snd_kcontrol_new es8316_out_left_mix[] = {
267 SOC_DAPM_SINGLE("LLIN Switch", ES8316_HPMIX_SWITCH_REG14,
269 SOC_DAPM_SINGLE("Left DAC Switch", ES8316_HPMIX_SWITCH_REG14,
273 static const struct snd_kcontrol_new es8316_out_right_mix[] = {
274 SOC_DAPM_SINGLE("RLIN Switch", ES8316_HPMIX_SWITCH_REG14,
276 SOC_DAPM_SINGLE("Right DAC Switch", ES8316_HPMIX_SWITCH_REG14,
280 /* DAC data source mux */
281 static const char * const es8316_dacsrc_texts[] = {
282 "LDATA TO LDAC, RDATA TO RDAC",
283 "LDATA TO LDAC, LDATA TO RDAC",
284 "RDATA TO LDAC, RDATA TO RDAC",
285 "RDATA TO LDAC, LDATA TO RDAC",
288 static const unsigned int es8316_dacsrc_values[] = { 0, 1, 2, 3 };
290 static const struct soc_enum es8316_dacsrc_mux_enum =
291 SOC_VALUE_ENUM_SINGLE(ES8316_DAC_SET1_REG30, 6, 4,
292 ARRAY_SIZE(es8316_dacsrc_texts),
294 es8316_dacsrc_values);
295 static const struct snd_kcontrol_new es8316_dacsrc_mux_controls =
296 SOC_DAPM_ENUM("Route", es8316_dacsrc_mux_enum);
298 static const struct snd_soc_dapm_widget es8316_dapm_widgets[] = {
300 SND_SOC_DAPM_INPUT("DMIC"),
301 SND_SOC_DAPM_INPUT("MIC1"),
302 SND_SOC_DAPM_INPUT("MIC2"),
304 SND_SOC_DAPM_MICBIAS("micbias", SND_SOC_NOPM,
307 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
308 &es8316_analog_in_mux_controls),
310 SND_SOC_DAPM_PGA("Line input PGA", ES8316_ADC_PDN_LINSEL_REG22,
314 SND_SOC_DAPM_ADC("Mono ADC", NULL, ES8316_ADC_PDN_LINSEL_REG22, 6, 1),
317 SND_SOC_DAPM_MUX("Digital Mic Mux", SND_SOC_NOPM, 0, 0,
318 &es8316_dmic_src_controls),
320 /* Digital Interface */
321 SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 1,
322 ES8316_SDP_ADCFMT_REG0A, 6, 0),
324 SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0,
327 /* DACs DATA SRC MUX */
328 SND_SOC_DAPM_MUX("DAC SRC Mux", SND_SOC_NOPM, 0, 0,
329 &es8316_dacsrc_mux_controls),
331 SND_SOC_DAPM_DAC("Right DAC", NULL, ES8316_DAC_PDN_REG2F, 0, 1),
332 SND_SOC_DAPM_DAC("Left DAC", NULL, ES8316_DAC_PDN_REG2F, 4, 1),
334 /* Headphone Output Side */
335 /* hpmux for hp mixer */
336 SND_SOC_DAPM_MUX("Left Hp mux", SND_SOC_NOPM, 0, 0,
337 &es8316_left_hpmux_controls),
338 SND_SOC_DAPM_MUX("Right Hp mux", SND_SOC_NOPM, 0, 0,
339 &es8316_right_hpmux_controls),
341 SND_SOC_DAPM_MIXER("Left Hp mixer", ES8316_HPMIX_PDN_REG15,
342 4, 1, &es8316_out_left_mix[0],
343 ARRAY_SIZE(es8316_out_left_mix)),
344 SND_SOC_DAPM_MIXER("Right Hp mixer", ES8316_HPMIX_PDN_REG15,
345 0, 1, &es8316_out_right_mix[0],
346 ARRAY_SIZE(es8316_out_right_mix)),
347 SND_SOC_DAPM_MIXER("Left Hp mixer", SND_SOC_NOPM,
348 4, 1, &es8316_out_left_mix[0],
349 ARRAY_SIZE(es8316_out_left_mix)),
350 SND_SOC_DAPM_MIXER("Right Hp mixer", SND_SOC_NOPM,
351 0, 1, &es8316_out_right_mix[0],
352 ARRAY_SIZE(es8316_out_right_mix)),
354 /* Output charge pump */
356 SND_SOC_DAPM_PGA("HPCP L", SND_SOC_NOPM,
358 SND_SOC_DAPM_PGA("HPCP R", SND_SOC_NOPM,
361 SND_SOC_DAPM_PGA("HPCP L", ES8316_CPHP_OUTEN_REG17,
363 SND_SOC_DAPM_PGA("HPCP R", ES8316_CPHP_OUTEN_REG17,
367 SND_SOC_DAPM_PGA("HPVOL L", SND_SOC_NOPM,
369 SND_SOC_DAPM_PGA("HPVOL R", SND_SOC_NOPM,
373 SND_SOC_DAPM_PGA("HPVOL L", ES8316_CPHP_OUTEN_REG17,
375 SND_SOC_DAPM_PGA("HPVOL R", ES8316_CPHP_OUTEN_REG17,
378 SND_SOC_DAPM_OUTPUT("HPOL"),
379 SND_SOC_DAPM_OUTPUT("HPOR"),
382 static const struct snd_soc_dapm_route es8316_dapm_routes[] = {
386 {"MIC1", NULL, "micbias"},
387 {"MIC2", NULL, "micbias"},
388 {"DMIC", NULL, "micbias"},
390 {"Differential Mux", "lin1-rin1", "MIC1"},
391 {"Differential Mux", "lin2-rin2", "MIC2"},
392 {"Line input PGA", NULL, "Differential Mux"},
394 {"Mono ADC", NULL, "Line input PGA"},
396 {"Digital Mic Mux", "dmic disable", "Mono ADC"},
397 {"Digital Mic Mux", "dmic data at high level", "DMIC"},
398 {"Digital Mic Mux", "dmic data at low level", "DMIC"},
400 {"I2S OUT", NULL, "Digital Mic Mux"},
404 {"DAC SRC Mux", "LDATA TO LDAC, RDATA TO RDAC", "I2S IN"},
405 {"DAC SRC Mux", "LDATA TO LDAC, LDATA TO RDAC", "I2S IN"},
406 {"DAC SRC Mux", "RDATA TO LDAC, RDATA TO RDAC", "I2S IN"},
407 {"DAC SRC Mux", "RDATA TO LDAC, LDATA TO RDAC", "I2S IN"},
409 {"Left DAC", NULL, "DAC SRC Mux"},
410 {"Right DAC", NULL, "DAC SRC Mux"},
412 {"Left Hp mux", "lin1-rin1", "MIC1"},
413 {"Left Hp mux", "lin2-rin2", "MIC2"},
414 {"Left Hp mux", "lin-rin with Boost", "Differential Mux"},
415 {"Left Hp mux", "lin-rin with Boost and PGA", "Line input PGA"},
417 {"Right Hp mux", "lin1-rin1", "MIC1"},
418 {"Right Hp mux", "lin2-rin2", "MIC2"},
419 {"Right Hp mux", "lin-rin with Boost", "Differential Mux"},
420 {"Right Hp mux", "lin-rin with Boost and PGA", "Line input PGA"},
422 {"Left Hp mixer", "LLIN Switch", "Left Hp mux"},
423 {"Left Hp mixer", "Left DAC Switch", "Left DAC"},
425 {"Right Hp mixer", "RLIN Switch", "Right Hp mux"},
426 {"Right Hp mixer", "Right DAC Switch", "Right DAC"},
428 {"HPCP L", NULL, "Left Hp mixer"},
429 {"HPCP R", NULL, "Right Hp mixer"},
431 {"HPVOL L", NULL, "HPCP L"},
432 {"HPVOL R", NULL, "HPCP R"},
434 {"HPOL", NULL, "HPVOL L"},
435 {"HPOR", NULL, "HPVOL R"},
439 u32 mclk; /*mclk frequency*/
440 u32 rate; /*sample rate*/
441 u8 div; /*adcclk and dacclk divider*/
442 u8 lrck_h; /*adclrck divider and daclrck divider*/
444 u8 sr; /*sclk divider*/
448 /* codec hifi mclk clock divider coefficients */
449 static const struct _coeff_div coeff_div[] = {
451 { 12288000, 8000, 6, 0x06, 0x00, 21, 32 },
452 { 11289600, 8000, 6, 0x05, 0x83, 20, 29 },
453 { 18432000, 8000, 9, 0x09, 0x00, 27, 32 },
454 { 16934400, 8000, 8, 0x08, 0x44, 25, 33 },
455 { 12000000, 8000, 7, 0x05, 0xdc, 21, 25 },
456 { 19200000, 8000, 12, 0x09, 0x60, 27, 25 },
459 { 11289600, 11025, 4, 0x04, 0x00, 16, 32 },
460 { 16934400, 11025, 6, 0x06, 0x00, 21, 32 },
461 { 12000000, 11025, 4, 0x04, 0x40, 17, 34 },
464 { 12288000, 16000, 3, 0x03, 0x00, 12, 32 },
465 { 18432000, 16000, 5, 0x04, 0x80, 18, 25 },
466 { 12000000, 16000, 3, 0x02, 0xee, 12, 31 },
467 { 19200000, 16000, 6, 0x04, 0xb0, 18, 25 },
470 { 11289600, 22050, 2, 0x02, 0x00, 8, 32 },
471 { 16934400, 22050, 3, 0x03, 0x00, 12, 32 },
472 { 12000000, 22050, 2, 0x02, 0x20, 8, 34 },
475 { 12288000, 32000, 1, 0x01, 0x80, 6, 48 },
476 { 18432000, 32000, 2, 0x02, 0x40, 9, 32 },
477 { 12000000, 32000, 1, 0x01, 0x77, 6, 31 },
478 { 19200000, 32000, 3, 0x02, 0x58, 10, 25 },
481 { 11289600, 44100, 1, 0x01, 0x00, 4, 32 },
482 { 16934400, 44100, 1, 0x01, 0x80, 6, 32 },
483 { 12000000, 44100, 1, 0x01, 0x10, 4, 34 },
486 { 12288000, 48000, 1, 0x01, 0x00, 4, 32 },
487 { 18432000, 48000, 1, 0x01, 0x80, 6, 32 },
488 { 12000000, 48000, 1, 0x00, 0xfa, 4, 31 },
489 { 19200000, 48000, 2, 0x01, 0x90, 6, 25 },
492 { 11289600, 88200, 1, 0x00, 0x80, 2, 32 },
493 { 16934400, 88200, 1, 0x00, 0xc0, 3, 48 },
494 { 12000000, 88200, 1, 0x00, 0x88, 2, 34 },
497 { 12288000, 96000, 1, 0x00, 0x80, 2, 32 },
498 { 18432000, 96000, 1, 0x00, 0xc0, 3, 48 },
499 { 12000000, 96000, 1, 0x00, 0x7d, 1, 31 },
500 { 19200000, 96000, 1, 0x00, 0xc8, 3, 25 },
503 static inline int get_coeff(int mclk, int rate)
507 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
508 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
515 /* The set of rates we can generate from the above for each SYSCLK */
517 static unsigned int rates_12288[] = {
518 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
521 static struct snd_pcm_hw_constraint_list constraints_12288 = {
522 .count = ARRAY_SIZE(rates_12288),
526 static unsigned int rates_112896[] = {
527 8000, 11025, 22050, 44100,
530 static struct snd_pcm_hw_constraint_list constraints_112896 = {
531 .count = ARRAY_SIZE(rates_112896),
532 .list = rates_112896,
535 static unsigned int rates_12[] = {
536 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
540 static struct snd_pcm_hw_constraint_list constraints_12 = {
541 .count = ARRAY_SIZE(rates_12),
546 * Note that this should be called from init rather than from hw_params.
548 static int es8316_set_dai_sysclk(struct snd_soc_dai *codec_dai,
549 int clk_id, unsigned int freq, int dir)
551 struct snd_soc_codec *codec = codec_dai->codec;
552 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
559 es8316->sysclk_constraints = &constraints_112896;
560 es8316->sysclk = freq;
567 es8316->sysclk_constraints = &constraints_12288;
568 es8316->sysclk = freq;
572 es8316->sysclk_constraints = &constraints_12;
573 es8316->sysclk = freq;
579 static int es8316_set_dai_fmt(struct snd_soc_dai *codec_dai,
582 struct snd_soc_codec *codec = codec_dai->codec;
587 iface = snd_soc_read(codec, ES8316_IFACE);
588 adciface = snd_soc_read(codec, ES8316_ADC_IFACE);
589 daciface = snd_soc_read(codec, ES8316_DAC_IFACE);
591 /* set master/slave audio interface */
592 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
593 case SND_SOC_DAIFMT_CBM_CFM:
596 case SND_SOC_DAIFMT_CBS_CFS:
603 /* interface format */
605 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
606 case SND_SOC_DAIFMT_I2S:
610 case SND_SOC_DAIFMT_RIGHT_J:
612 case SND_SOC_DAIFMT_LEFT_J:
618 case SND_SOC_DAIFMT_DSP_A:
624 case SND_SOC_DAIFMT_DSP_B:
634 /* clock inversion */
635 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
636 case SND_SOC_DAIFMT_NB_NF:
641 case SND_SOC_DAIFMT_IB_IF:
646 case SND_SOC_DAIFMT_IB_NF:
651 case SND_SOC_DAIFMT_NB_IF:
659 snd_soc_write(codec, ES8316_IFACE, iface);
660 snd_soc_write(codec, ES8316_ADC_IFACE, adciface);
661 snd_soc_write(codec, ES8316_DAC_IFACE, daciface);
665 static int es8316_pcm_startup(struct snd_pcm_substream *substream,
666 struct snd_soc_dai *dai)
668 struct snd_soc_codec *codec = dai->codec;
669 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
670 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
672 snd_soc_write(codec, ES8316_RESET_REG00, 0xC0);
673 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x00);
674 /* es8316: both playback and capture need dac mclk */
675 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01,
676 ES8316_CLKMGR_MCLK_DIV_MASK |
677 ES8316_CLKMGR_DAC_MCLK_MASK,
678 ES8316_CLKMGR_MCLK_DIV_NML |
679 ES8316_CLKMGR_DAC_MCLK_EN);
683 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0x3F);
684 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0x1F);
685 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x88);
686 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x00);
687 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0xBB);
688 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x10);
689 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x30);
690 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x02);
691 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x00);
692 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x66);
693 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01,
694 ES8316_CLKMGR_DAC_MCLK_MASK |
695 ES8316_CLKMGR_DAC_ANALOG_MASK,
696 ES8316_CLKMGR_DAC_MCLK_EN |
697 ES8316_CLKMGR_DAC_ANALOG_EN);
700 snd_soc_update_bits(codec,
701 ES8316_ADC_PDN_LINSEL_REG22, 0xC0, 0x20);
702 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01,
703 ES8316_CLKMGR_ADC_MCLK_MASK |
704 ES8316_CLKMGR_ADC_ANALOG_MASK,
705 ES8316_CLKMGR_ADC_MCLK_EN |
706 ES8316_CLKMGR_ADC_ANALOG_EN);
712 static void es8316_pcm_shutdown(struct snd_pcm_substream *substream,
713 struct snd_soc_dai *dai)
715 struct snd_soc_pcm_runtime *rtd = substream->private_data;
716 struct snd_soc_codec *codec = rtd->codec;
717 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
718 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
721 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x00);
722 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
723 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x03);
724 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x22);
725 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x06);
726 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x00);
727 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x33);
728 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0x00);
729 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x00);
730 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0xFF);
731 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0xFF);
732 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01,
733 ES8316_CLKMGR_DAC_ANALOG_MASK,
734 ES8316_CLKMGR_DAC_ANALOG_DIS);
736 snd_soc_write(codec, ES8316_ADC_PDN_LINSEL_REG22, 0xc0);
737 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01,
738 ES8316_CLKMGR_ADC_MCLK_MASK |
739 ES8316_CLKMGR_ADC_ANALOG_MASK,
740 ES8316_CLKMGR_ADC_MCLK_DIS |
741 ES8316_CLKMGR_ADC_ANALOG_DIS);
744 if (--es8316->pwr_count == 0) {
745 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x3F);
746 snd_soc_write(codec, ES8316_CLKMGR_CLKSW_REG01, 0xF3);
750 static int es8316_pcm_hw_params(struct snd_pcm_substream *substream,
751 struct snd_pcm_hw_params *params,
752 struct snd_soc_dai *dai)
754 struct snd_soc_codec *codec = dai->codec;
757 switch (params_format(params)) {
758 case SNDRV_PCM_FORMAT_S16_LE:
759 val = ES8316_DACWL_16;
761 case SNDRV_PCM_FORMAT_S20_3LE:
762 val = ES8316_DACWL_20;
764 case SNDRV_PCM_FORMAT_S24_LE:
765 val = ES8316_DACWL_24;
767 case SNDRV_PCM_FORMAT_S32_LE:
768 val = ES8316_DACWL_32;
772 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
773 snd_soc_update_bits(codec, ES8316_SDP_DACFMT_REG0B,
774 ES8316_DACWL_MASK, val);
776 snd_soc_update_bits(codec, ES8316_SDP_ADCFMT_REG0A,
777 ES8316_ADCWL_MASK, val);
782 static int es8316_mute(struct snd_soc_dai *dai, int mute)
784 struct snd_soc_codec *codec = dai->codec;
785 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
787 es8316->muted = mute;
789 es8316_enable_spk(es8316, false);
791 snd_soc_write(codec, ES8316_DAC_SET1_REG30, 0x20);
792 } else if (dai->playback_active) {
793 snd_soc_write(codec, ES8316_DAC_SET1_REG30, 0x00);
795 if (!es8316->hp_inserted)
796 es8316_enable_spk(es8316, true);
801 static int es8316_set_bias_level(struct snd_soc_codec *codec,
802 enum snd_soc_bias_level level)
804 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
808 case SND_SOC_BIAS_ON:
811 case SND_SOC_BIAS_PREPARE:
812 if (IS_ERR(es8316->mclk))
815 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
816 clk_disable_unprepare(es8316->mclk);
818 ret = clk_prepare_enable(es8316->mclk);
824 case SND_SOC_BIAS_STANDBY:
827 case SND_SOC_BIAS_OFF:
828 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x00);
829 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
830 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x03);
831 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x22);
832 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x06);
833 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x00);
834 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x33);
835 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0x00);
836 snd_soc_write(codec, ES8316_ADC_PDN_LINSEL_REG22, 0xC0);
837 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x3F);
838 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0x3F);
839 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0x1F);
840 snd_soc_write(codec, ES8316_RESET_REG00, 0x00);
847 #define es8316_RATES SNDRV_PCM_RATE_8000_96000
849 #define es8316_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
850 SNDRV_PCM_FMTBIT_S24_LE)
852 static struct snd_soc_dai_ops es8316_ops = {
853 .startup = es8316_pcm_startup,
854 .hw_params = es8316_pcm_hw_params,
855 .set_fmt = es8316_set_dai_fmt,
856 .set_sysclk = es8316_set_dai_sysclk,
857 .digital_mute = es8316_mute,
858 .shutdown = es8316_pcm_shutdown,
861 static struct snd_soc_dai_driver es8316_dai = {
862 .name = "ES8316 HiFi",
864 .stream_name = "Playback",
867 .rates = es8316_RATES,
868 .formats = es8316_FORMATS,
871 .stream_name = "Capture",
874 .rates = es8316_RATES,
875 .formats = es8316_FORMATS,
878 .symmetric_rates = 1,
881 static int es8316_init_regs(struct snd_soc_codec *codec)
883 snd_soc_write(codec, ES8316_RESET_REG00, 0x3f);
884 usleep_range(5000, 5500);
885 snd_soc_write(codec, ES8316_RESET_REG00, 0x00);
886 snd_soc_write(codec, ES8316_SYS_VMIDSEL_REG0C, 0xFF);
888 snd_soc_write(codec, ES8316_CLKMGR_CLKSEL_REG02, 0x08);
889 snd_soc_write(codec, ES8316_CLKMGR_ADCOSR_REG03, 0x20);
890 snd_soc_write(codec, ES8316_CLKMGR_ADCDIV1_REG04, 0x11);
891 snd_soc_write(codec, ES8316_CLKMGR_ADCDIV2_REG05, 0x00);
892 snd_soc_write(codec, ES8316_CLKMGR_DACDIV1_REG06, 0x11);
893 snd_soc_write(codec, ES8316_CLKMGR_DACDIV2_REG07, 0x00);
894 snd_soc_write(codec, ES8316_CLKMGR_CPDIV_REG08, 0x00);
895 snd_soc_write(codec, ES8316_SDP_MS_BCKDIV_REG09, 0x04);
896 snd_soc_write(codec, ES8316_CLKMGR_CLKSW_REG01, 0x7F);
897 snd_soc_write(codec, ES8316_CAL_TYPE_REG1C, 0x0F);
898 snd_soc_write(codec, ES8316_CAL_HPLIV_REG1E, 0x90);
899 snd_soc_write(codec, ES8316_CAL_HPRIV_REG1F, 0x90);
900 snd_soc_write(codec, ES8316_ADC_VOLUME_REG27, 0x00);
901 snd_soc_write(codec, ES8316_ADC_PDN_LINSEL_REG22, 0xc0);
902 snd_soc_write(codec, ES8316_ADC_D2SEPGA_REG24, 0x00);
903 snd_soc_write(codec, ES8316_ADC_DMIC_REG25, 0x08);
904 snd_soc_write(codec, ES8316_DAC_SET2_REG31, 0x20);
905 snd_soc_write(codec, ES8316_DAC_SET3_REG32, 0x00);
906 snd_soc_write(codec, ES8316_DAC_VOLL_REG33, 0x00);
907 snd_soc_write(codec, ES8316_DAC_VOLR_REG34, 0x00);
908 snd_soc_write(codec, ES8316_SDP_ADCFMT_REG0A, 0x00);
909 snd_soc_write(codec, ES8316_SDP_DACFMT_REG0B, 0x00);
910 snd_soc_write(codec, ES8316_SYS_VMIDLOW_REG10, 0x11);
911 snd_soc_write(codec, ES8316_SYS_VSEL_REG11, 0xFC);
912 snd_soc_write(codec, ES8316_SYS_REF_REG12, 0x28);
913 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0x04);
914 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0x0C);
915 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
916 snd_soc_write(codec, ES8316_HPMIX_SEL_REG13, 0x00);
917 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x88);
918 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x00);
919 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0xBB);
920 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x10);
921 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x30);
922 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x02);
923 snd_soc_write(codec, ES8316_CPHP_ICAL_VOL_REG18, 0x00);
924 snd_soc_write(codec, ES8316_GPIO_SEL_REG4D, 0x00);
925 snd_soc_write(codec, ES8316_GPIO_DEBUNCE_INT_REG4E, 0x02);
926 snd_soc_write(codec, ES8316_TESTMODE_REG50, 0xA0);
927 snd_soc_write(codec, ES8316_TEST1_REG51, 0x00);
928 snd_soc_write(codec, ES8316_TEST2_REG52, 0x00);
929 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x00);
930 snd_soc_write(codec, ES8316_RESET_REG00, 0xC0);
932 snd_soc_write(codec, ES8316_ADC_PGAGAIN_REG23, 0x60);
933 snd_soc_write(codec, ES8316_ADC_D2SEPGA_REG24, 0x01);
934 /* adc ds mode, HPF enable */
935 snd_soc_write(codec, ES8316_ADC_DMIC_REG25, 0x08);
936 snd_soc_write(codec, ES8316_ADC_ALC1_REG29, 0xcd);
937 snd_soc_write(codec, ES8316_ADC_ALC2_REG2A, 0x08);
938 snd_soc_write(codec, ES8316_ADC_ALC3_REG2B, 0xa0);
939 snd_soc_write(codec, ES8316_ADC_ALC4_REG2C, 0x05);
940 snd_soc_write(codec, ES8316_ADC_ALC5_REG2D, 0x06);
941 snd_soc_write(codec, ES8316_ADC_ALC6_REG2E, 0x61);
945 static int es8316_suspend(struct snd_soc_codec *codec)
950 static int es8316_resume(struct snd_soc_codec *codec)
954 es8316_reset(codec); /* UPDATED BY DAVID,15-3-5 */
955 ret = snd_soc_read(codec, ES8316_CLKMGR_ADCDIV2_REG05);
957 es8316_init_regs(codec);
958 snd_soc_write(codec, ES8316_GPIO_SEL_REG4D, 0x00);
959 /* max debance time, enable interrupt, low active */
960 snd_soc_write(codec, ES8316_GPIO_DEBUNCE_INT_REG4E, 0xf3);
961 /* es8316_set_bias_level(codec, SND_SOC_BIAS_OFF); */
962 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x00);
963 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
964 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x03);
965 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x22);
966 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x06);
967 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x00);
968 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x33);
969 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0x00);
970 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x3F);
971 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0xFF);
972 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0xFF);
973 snd_soc_write(codec, ES8316_CLKMGR_CLKSW_REG01, 0xF3);
974 snd_soc_write(codec, ES8316_ADC_PDN_LINSEL_REG22, 0xc0);
979 static irqreturn_t es8316_irq_handler(int irq, void *data)
981 struct es8316_priv *es8316 = data;
983 queue_delayed_work(system_power_efficient_wq, &es8316->work,
984 msecs_to_jiffies(es8316->debounce_time));
989 static void hp_work(struct work_struct *work)
991 struct es8316_priv *es8316;
994 es8316 = container_of(work, struct es8316_priv, work.work);
995 enable = gpio_get_value(es8316->hp_det_gpio);
996 if (es8316->hp_det_invert)
999 es8316->hp_inserted = enable ? true : false;
1000 if (!es8316->muted) {
1001 if (es8316->hp_inserted)
1002 es8316_enable_spk(es8316, false);
1004 es8316_enable_spk(es8316, true);
1008 static int es8316_probe(struct snd_soc_codec *codec)
1010 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
1013 es8316->mclk = devm_clk_get(codec->dev, "mclk");
1014 if (PTR_ERR(es8316->mclk) == -EPROBE_DEFER)
1015 return -EPROBE_DEFER;
1017 ret = clk_prepare_enable(es8316->mclk);
1020 ret = snd_soc_read(codec, ES8316_CLKMGR_ADCDIV2_REG05);
1022 es8316_reset(codec); /* UPDATED BY DAVID,15-3-5 */
1023 ret = snd_soc_read(codec, ES8316_CLKMGR_ADCDIV2_REG05);
1025 es8316_init_regs(codec);
1026 snd_soc_write(codec, ES8316_GPIO_SEL_REG4D, 0x00);
1027 /* max debance time, enable interrupt, low active */
1028 snd_soc_write(codec,
1029 ES8316_GPIO_DEBUNCE_INT_REG4E, 0xf3);
1031 /* es8316_set_bias_level(codec, SND_SOC_BIAS_OFF); */
1032 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x00);
1033 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
1034 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x03);
1035 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x22);
1036 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x06);
1037 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x00);
1038 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x33);
1039 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0x00);
1040 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x3F);
1041 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0xFF);
1042 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0xFF);
1043 snd_soc_write(codec, ES8316_CLKMGR_CLKSW_REG01, 0xF3);
1044 snd_soc_write(codec,
1045 ES8316_ADC_PDN_LINSEL_REG22, 0xc0);
1052 static int es8316_remove(struct snd_soc_codec *codec)
1054 es8316_set_bias_level(codec, SND_SOC_BIAS_OFF);
1058 const struct regmap_config es8316_regmap_config = {
1061 .max_register = ES8316_TEST3_REG53,
1062 .cache_type = REGCACHE_RBTREE,
1063 .reg_defaults = es8316_reg_defaults,
1064 .num_reg_defaults = ARRAY_SIZE(es8316_reg_defaults),
1067 static struct snd_soc_codec_driver soc_codec_dev_es8316 = {
1068 .probe = es8316_probe,
1069 .remove = es8316_remove,
1070 .suspend = es8316_suspend,
1071 .resume = es8316_resume,
1072 .set_bias_level = es8316_set_bias_level,
1074 .controls = es8316_snd_controls,
1075 .num_controls = ARRAY_SIZE(es8316_snd_controls),
1076 .dapm_widgets = es8316_dapm_widgets,
1077 .num_dapm_widgets = ARRAY_SIZE(es8316_dapm_widgets),
1078 .dapm_routes = es8316_dapm_routes,
1079 .num_dapm_routes = ARRAY_SIZE(es8316_dapm_routes),
1082 static int es8316_i2c_probe(struct i2c_client *i2c,
1083 const struct i2c_device_id *id)
1085 struct es8316_priv *es8316;
1088 enum of_gpio_flags flags;
1089 struct device_node *np = i2c->dev.of_node;
1091 es8316 = devm_kzalloc(&i2c->dev, sizeof(*es8316), GFP_KERNEL);
1095 es8316->debounce_time = 200;
1096 es8316->hp_det_invert = 0;
1097 es8316->pwr_count = 0;
1098 es8316->hp_inserted = false;
1099 es8316->muted = true;
1101 es8316->regmap = devm_regmap_init_i2c(i2c, &es8316_regmap_config);
1102 if (IS_ERR(es8316->regmap)) {
1103 ret = PTR_ERR(es8316->regmap);
1104 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
1108 i2c_set_clientdata(i2c, es8316);
1110 es8316->spk_ctl_gpio = of_get_named_gpio_flags(np,
1114 if (es8316->spk_ctl_gpio < 0) {
1115 dev_info(&i2c->dev, "Can not read property spk_ctl_gpio\n");
1116 es8316->spk_ctl_gpio = INVALID_GPIO;
1118 es8316->spk_active_level = !(flags & OF_GPIO_ACTIVE_LOW);
1119 ret = devm_gpio_request_one(&i2c->dev, es8316->spk_ctl_gpio,
1120 GPIOF_DIR_OUT, NULL);
1122 dev_err(&i2c->dev, "Failed to request spk_ctl_gpio\n");
1125 es8316_enable_spk(es8316, false);
1128 es8316->hp_det_gpio = of_get_named_gpio_flags(np,
1132 if (es8316->hp_det_gpio < 0) {
1133 dev_info(&i2c->dev, "Can not read property hp_det_gpio\n");
1134 es8316->hp_det_gpio = INVALID_GPIO;
1136 INIT_DELAYED_WORK(&es8316->work, hp_work);
1137 es8316->hp_det_invert = !!(flags & OF_GPIO_ACTIVE_LOW);
1138 ret = devm_gpio_request_one(&i2c->dev, es8316->hp_det_gpio,
1139 GPIOF_IN, "hp det");
1142 hp_irq = gpio_to_irq(es8316->hp_det_gpio);
1143 ret = devm_request_threaded_irq(&i2c->dev, hp_irq, NULL,
1145 IRQF_TRIGGER_FALLING |
1146 IRQF_TRIGGER_RISING |
1148 "es8316_interrupt", es8316);
1150 dev_err(&i2c->dev, "request_irq failed: %d\n", ret);
1154 schedule_delayed_work(&es8316->work,
1155 msecs_to_jiffies(es8316->debounce_time));
1158 ret = snd_soc_register_codec(&i2c->dev,
1159 &soc_codec_dev_es8316,
1165 static int es8316_i2c_remove(struct i2c_client *client)
1167 snd_soc_unregister_codec(&client->dev);
1171 static const struct i2c_device_id es8316_i2c_id[] = {
1177 MODULE_DEVICE_TABLE(i2c, es8316_i2c_id);
1179 static const struct of_device_id es8316_of_match[] = {
1180 { .compatible = "everest,es8316", },
1183 MODULE_DEVICE_TABLE(of, es8316_of_match);
1185 static struct i2c_driver es8316_i2c_driver = {
1188 .of_match_table = es8316_of_match,
1190 .probe = es8316_i2c_probe,
1191 .remove = es8316_i2c_remove,
1192 .id_table = es8316_i2c_id,
1195 module_i2c_driver(es8316_i2c_driver);
1197 MODULE_DESCRIPTION("ASoC es8316 driver");
1198 MODULE_AUTHOR("Will <will@everset-semi.com>");
1199 MODULE_LICENSE("GPL");