2 * es8316.c -- es8316 ALSA SoC audio driver
3 * Copyright Everest Semiconductor Co.,Ltd
5 * Author: David Yang <yangxiaohua@everest-semi.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/spi/spi.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/of_gpio.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/tlv.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30 #include <linux/proc_fs.h>
31 #include <linux/gpio.h>
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
34 #include <linux/regmap.h>
38 #define DBG(x...) printk(x)
40 #define DBG(x...) do { } while (0)
47 #define INVALID_GPIO -1
49 #define ES8316_CODEC_SET_SPK 1
50 #define ES8316_CODEC_SET_HP 2
55 int es8316_init_reg = 0;
59 #ifndef es8316_DEF_VOL
60 #define es8316_DEF_VOL 0x1e
63 struct snd_soc_codec *es8316_codec;
64 static int es8316_init_regs(struct snd_soc_codec *codec);
65 static int es8316_set_bias_level(struct snd_soc_codec *codec,
66 enum snd_soc_bias_level level);
68 static const struct reg_default es8316_reg_defaults[] = {
69 {0x00, 0x03}, {0x01, 0x03}, {0x02, 0x00}, {0x03, 0x20},
70 {0x04, 0x11}, {0x05, 0x00}, {0x06, 0x11}, {0x07, 0x00},
71 {0x08, 0x00}, {0x09, 0x01}, {0x0a, 0x00}, {0x0b, 0x00},
72 {0x0c, 0xf8}, {0x0d, 0x3f}, {0x0e, 0x00}, {0x0f, 0x00},
73 {0x10, 0x01}, {0x11, 0xfc}, {0x12, 0x28}, {0x13, 0x00},
74 {0x14, 0x00}, {0x15, 0x33}, {0x16, 0x00}, {0x17, 0x00},
75 {0x18, 0x88}, {0x19, 0x06}, {0x1a, 0x22}, {0x1b, 0x03},
76 {0x1c, 0x0f}, {0x1d, 0x00}, {0x1e, 0x80}, {0x1f, 0x80},
77 {0x20, 0x00}, {0x21, 0x00}, {0x22, 0xc0}, {0x23, 0x00},
78 {0x24, 0x01}, {0x25, 0x08}, {0x26, 0x10}, {0x27, 0xc0},
79 {0x28, 0x00}, {0x29, 0x1c}, {0x2a, 0x00}, {0x2b, 0xb0},
80 {0x2c, 0x32}, {0x2d, 0x03}, {0x2e, 0x00}, {0x2f, 0x11},
81 {0x30, 0x10}, {0x31, 0x00}, {0x32, 0x00}, {0x33, 0xc0},
82 {0x34, 0xc0}, {0x35, 0x1f}, {0x36, 0xf7}, {0x37, 0xfd},
83 {0x38, 0xff}, {0x39, 0x1f}, {0x3a, 0xf7}, {0x3b, 0xfd},
84 {0x3c, 0xff}, {0x3d, 0x1f}, {0x3e, 0xf7}, {0x3f, 0xfd},
85 {0x40, 0xff}, {0x41, 0x1f}, {0x42, 0xf7}, {0x43, 0xfd},
86 {0x44, 0xff}, {0x45, 0x1f}, {0x46, 0xf7}, {0x47, 0xfd},
87 {0x48, 0xff}, {0x49, 0x1f}, {0x4a, 0xf7}, {0x4b, 0xfd},
88 {0x4c, 0xff}, {0x4d, 0x00}, {0x4e, 0x00}, {0x4f, 0xff},
89 {0x50, 0x00}, {0x51, 0x00}, {0x52, 0x00}, {0x53, 0x00},
92 static int es8316_readable(struct snd_soc_codec *codec, unsigned int reg)
99 static int es8316_volatile(struct snd_soc_codec *codec, unsigned int reg)
106 /* codec private data */
108 struct regmap *regmap;
109 unsigned int dmic_amic;
111 struct snd_pcm_hw_constraint_list *sysclk_constraints;
124 struct es8316_priv *es8316_private;
128 * write value 0xff to reg0x00, the chip will be in reset mode
129 * then, writer 0x00 to reg0x00, unreset the chip
131 static int es8316_reset(struct snd_soc_codec *codec)
133 snd_soc_write(codec, ES8316_RESET_REG00, 0x3F);
134 usleep_range(5000, 5500);
135 return snd_soc_write(codec, ES8316_RESET_REG00, 0x03);
138 static int es8316_set_gpio(int gpio, bool level)
140 struct es8316_priv *es8316 = es8316_private;
143 DBG("%s : es8316_priv is NULL\n", __func__);
146 DBG("%s : set %s %s ctl gpio %s\n", __func__,
147 gpio & ES8316_CODEC_SET_SPK ? "spk" : "",
148 gpio & ES8316_CODEC_SET_HP ? "hp" : "",
149 level ? "HIGH" : "LOW");
150 if ((gpio & ES8316_CODEC_SET_SPK)
151 && es8316 && es8316->spk_ctl_gpio != INVALID_GPIO) {
152 DBG("%d,set_value%s\n", es8316->spk_ctl_gpio, level ?
154 gpio_set_value(es8316->spk_ctl_gpio, level);
159 static char mute_flag = 1;
160 static irqreturn_t hp_det_irq_handler(int irq, void *dev_id)
164 struct es8316_priv *es8316 = es8316_private;
166 disable_irq_nosync(irq);
168 type = gpio_get_value(es8316->hp_det_gpio) ?
169 IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
170 ret = irq_set_irq_type(irq, type);
172 DBG("%s: irq_set_irq_type(%d, %d) failed\n",
173 __func__, irq, type);
177 if (es8316->hp_det_level != gpio_get_value(es8316->hp_det_gpio))
181 if (mute_flag == 0) {
182 if (es8316->hp_det_level == gpio_get_value(es8316->hp_det_gpio))
183 es8316_set_gpio(ES8316_CODEC_SET_SPK,
184 !es8316->spk_gpio_level);
186 es8316_set_gpio(ES8316_CODEC_SET_SPK,
187 es8316->spk_gpio_level);
197 /*#define DECLARE_TLV_DB_SCALE(name, min, step, mute) */
198 /*static const DECLARE_TLV_DB_SCALE(hpout_vol_tlv, -4800, 1200, 0);*/
199 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9600, 50, 1);
200 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -9600, 50, 1);
201 static const DECLARE_TLV_DB_SCALE(hpmixer_gain_tlv, -1200, 150, 0);
202 static const DECLARE_TLV_DB_SCALE(mic_bst_tlv, 0, 1200, 0);
203 /*static const DECLARE_TLV_DB_SCALE(linin_pga_tlv, 0, 300, 0);*/
204 /* {0, +3, +6, +9, +12, +15, +18, +21, +24,+27,+30,+33} dB */
205 static unsigned int linin_pga_tlv[] = {
206 TLV_DB_RANGE_HEAD(12),
207 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
208 1, 1, TLV_DB_SCALE_ITEM(300, 0, 0),
209 2, 2, TLV_DB_SCALE_ITEM(600, 0, 0),
210 3, 3, TLV_DB_SCALE_ITEM(900, 0, 0),
211 4, 4, TLV_DB_SCALE_ITEM(1200, 0, 0),
212 5, 5, TLV_DB_SCALE_ITEM(1500, 0, 0),
213 6, 6, TLV_DB_SCALE_ITEM(1800, 0, 0),
214 7, 7, TLV_DB_SCALE_ITEM(2100, 0, 0),
215 8, 8, TLV_DB_SCALE_ITEM(2400, 0, 0),
217 static unsigned int hpout_vol_tlv[] = {
218 TLV_DB_RANGE_HEAD(1),
219 0, 3, TLV_DB_SCALE_ITEM(-4800, 1200, 0),
221 static const char *const alc_func_txt[] = {"Off", "On"};
222 static const struct soc_enum alc_func =
223 SOC_ENUM_SINGLE(ES8316_ADC_ALC1_REG29, 6, 2, alc_func_txt);
225 static const char *const ng_type_txt[] = {"Constant PGA Gain",
227 static const struct soc_enum ng_type =
228 SOC_ENUM_SINGLE(ES8316_ADC_ALC6_REG2E, 6, 2, ng_type_txt);
230 static const char *const adcpol_txt[] = {"Normal", "Invert"};
231 static const struct soc_enum adcpol =
232 SOC_ENUM_SINGLE(ES8316_ADC_MUTE_REG26, 1, 2, adcpol_txt);
233 static const char *const dacpol_txt[] = {"Normal", "R Invert", "L Invert",
235 static const struct soc_enum dacpol =
236 SOC_ENUM_SINGLE(ES8316_DAC_SET1_REG30, 0, 4, dacpol_txt);
238 static const struct snd_kcontrol_new es8316_snd_controls[] = {
240 SOC_DOUBLE_TLV("HP Playback Volume", ES8316_CPHP_ICAL_VOL_REG18,
241 4, 0, 0, 1, hpout_vol_tlv),
242 /* HPMIXER VOLUME Control */
243 SOC_DOUBLE_TLV("HPMixer Gain", ES8316_HPMIX_VOL_REG16,
244 0, 4, 7, 0, hpmixer_gain_tlv),
246 /* DAC Digital controls */
247 SOC_DOUBLE_R_TLV("DAC Playback Volume", ES8316_DAC_VOLL_REG33,
248 ES8316_DAC_VOLR_REG34, 0, 0xC0, 1, dac_vol_tlv),
250 SOC_SINGLE("Enable DAC Soft Ramp", ES8316_DAC_SET1_REG30, 4, 1, 1),
251 SOC_SINGLE("DAC Soft Ramp Rate", ES8316_DAC_SET1_REG30, 2, 4, 0),
253 SOC_ENUM("Playback Polarity", dacpol),
254 SOC_SINGLE("DAC Notch Filter", ES8316_DAC_SET2_REG31, 6, 1, 0),
255 SOC_SINGLE("DAC Double Fs Mode", ES8316_DAC_SET2_REG31, 7, 1, 0),
256 SOC_SINGLE("DAC Volume Control-LeR", ES8316_DAC_SET2_REG31, 2, 1, 0),
257 SOC_SINGLE("DAC Stereo Enhancement", ES8316_DAC_SET3_REG32, 0, 7, 0),
259 /* +20dB D2SE PGA Control */
260 SOC_SINGLE_TLV("MIC Boost", ES8316_ADC_D2SEPGA_REG24,
261 0, 1, 0, mic_bst_tlv),
262 /* 0-+24dB Lineinput PGA Control */
263 SOC_SINGLE_TLV("Input PGA", ES8316_ADC_PGAGAIN_REG23,
264 4, 8, 0, linin_pga_tlv),
266 /* ADC Digital Control */
267 SOC_SINGLE_TLV("ADC Capture Volume", ES8316_ADC_VOLUME_REG27,
268 0, 0xC0, 1, adc_vol_tlv),
269 SOC_SINGLE("ADC Soft Ramp", ES8316_ADC_MUTE_REG26, 4, 1, 0),
270 SOC_ENUM("Capture Polarity", adcpol),
271 SOC_SINGLE("ADC Double FS Mode", ES8316_ADC_DMIC_REG25, 4, 1, 0),
272 /* ADC ALC Control */
273 SOC_SINGLE("ALC Capture Target Volume",
274 ES8316_ADC_ALC3_REG2B, 4, 10, 0),
275 SOC_SINGLE("ALC Capture Max PGA", ES8316_ADC_ALC1_REG29, 0, 28, 0),
276 SOC_SINGLE("ALC Capture Min PGA", ES8316_ADC_ALC2_REG2A, 0, 28, 0),
277 SOC_ENUM("ALC Capture Function", alc_func),
278 SOC_SINGLE("ALC Capture Hold Time", ES8316_ADC_ALC3_REG2B, 0, 10, 0),
279 SOC_SINGLE("ALC Capture Decay Time", ES8316_ADC_ALC4_REG2C, 4, 10, 0),
280 SOC_SINGLE("ALC Capture Attack Time", ES8316_ADC_ALC4_REG2C, 0, 10, 0),
281 SOC_SINGLE("ALC Capture NG Threshold", ES8316_ADC_ALC6_REG2E, 0, 31, 0),
282 SOC_ENUM("ALC Capture NG Type", ng_type),
283 SOC_SINGLE("ALC Capture NG Switch", ES8316_ADC_ALC6_REG2E, 5, 1, 0),
286 /* Analog Input MUX */
287 static const char * const es8316_analog_in_txt[] = {
290 "lin1-rin1 with 20db Boost",
291 "lin2-rin2 with 20db Boost"
293 static const unsigned int es8316_analog_in_values[] = {
299 static const struct soc_enum es8316_analog_input_enum =
300 SOC_VALUE_ENUM_SINGLE(ES8316_ADC_PDN_LINSEL_REG22, 4, 3,
301 ARRAY_SIZE(es8316_analog_in_txt),
302 es8316_analog_in_txt,
303 es8316_analog_in_values);
304 static const struct snd_kcontrol_new es8316_analog_in_mux_controls =
305 SOC_DAPM_ENUM("Route", es8316_analog_input_enum);
308 static const char * const es8316_dmic_txt[] = {
310 "dmic data at high level",
311 "dmic data at low level",
313 static const unsigned int es8316_dmic_values[] = {
318 static const struct soc_enum es8316_dmic_src_enum =
319 SOC_VALUE_ENUM_SINGLE(ES8316_ADC_DMIC_REG25, 0, 3,
320 ARRAY_SIZE(es8316_dmic_txt),
323 static const struct snd_kcontrol_new es8316_dmic_src_controls =
324 SOC_DAPM_ENUM("Route", es8316_dmic_src_enum);
327 static const char *const es8316_hpmux_texts[] = {
330 "lin-rin with Boost",
331 "lin-rin with Boost and PGA"
334 static const unsigned int es8316_hpmux_values[] = {0, 1, 2, 3};
336 static const struct soc_enum es8316_left_hpmux_enum =
337 SOC_VALUE_ENUM_SINGLE(ES8316_HPMIX_SEL_REG13, 4, 7,
338 ARRAY_SIZE(es8316_hpmux_texts),
340 es8316_hpmux_values);
341 static const struct snd_kcontrol_new es8316_left_hpmux_controls =
342 SOC_DAPM_VALUE_ENUM("Route", es8316_left_hpmux_enum);
344 static const struct soc_enum es8316_right_hpmux_enum =
345 SOC_VALUE_ENUM_SINGLE(ES8316_HPMIX_SEL_REG13, 0, 7,
346 ARRAY_SIZE(es8316_hpmux_texts),
348 es8316_hpmux_values);
349 static const struct snd_kcontrol_new es8316_right_hpmux_controls =
350 SOC_DAPM_VALUE_ENUM("Route", es8316_right_hpmux_enum);
352 /* headphone Output Mixer */
353 static const struct snd_kcontrol_new es8316_out_left_mix[] = {
354 SOC_DAPM_SINGLE("LLIN Switch", ES8316_HPMIX_SWITCH_REG14,
356 SOC_DAPM_SINGLE("Left DAC Switch", ES8316_HPMIX_SWITCH_REG14,
359 static const struct snd_kcontrol_new es8316_out_right_mix[] = {
360 SOC_DAPM_SINGLE("RLIN Switch", ES8316_HPMIX_SWITCH_REG14,
362 SOC_DAPM_SINGLE("Right DAC Switch", ES8316_HPMIX_SWITCH_REG14,
366 /* DAC data source mux */
367 static const char * const es8316_dacsrc_texts[] = {
368 "LDATA TO LDAC, RDATA TO RDAC",
369 "LDATA TO LDAC, LDATA TO RDAC",
370 "RDATA TO LDAC, RDATA TO RDAC",
371 "RDATA TO LDAC, LDATA TO RDAC",
374 static const unsigned int es8316_dacsrc_values[] = {
377 static const struct soc_enum es8316_dacsrc_mux_enum =
378 SOC_VALUE_ENUM_SINGLE(ES8316_DAC_SET1_REG30, 6, 4,
379 ARRAY_SIZE(es8316_dacsrc_texts),
381 es8316_dacsrc_values);
382 static const struct snd_kcontrol_new es8316_dacsrc_mux_controls =
383 SOC_DAPM_VALUE_ENUM("Route", es8316_dacsrc_mux_enum);
386 static const struct snd_soc_dapm_widget es8316_dapm_widgets[] = {
388 SND_SOC_DAPM_INPUT("DMIC"),
389 SND_SOC_DAPM_INPUT("MIC1"),
390 SND_SOC_DAPM_INPUT("MIC2"),
392 SND_SOC_DAPM_MICBIAS("micbias", SND_SOC_NOPM,
395 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
396 &es8316_analog_in_mux_controls),
398 SND_SOC_DAPM_PGA("Line input PGA", ES8316_ADC_PDN_LINSEL_REG22,
402 SND_SOC_DAPM_ADC("Mono ADC", NULL, ES8316_ADC_PDN_LINSEL_REG22, 6, 1),
405 SND_SOC_DAPM_MUX("Digital Mic Mux", SND_SOC_NOPM, 0, 0,
406 &es8316_dmic_src_controls),
408 /* Digital Interface */
409 SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 1,
410 ES8316_SDP_ADCFMT_REG0A, 6, 0),
412 SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0,
415 /* DACs DATA SRC MUX */
416 SND_SOC_DAPM_MUX("DAC SRC Mux", SND_SOC_NOPM, 0, 0,
417 &es8316_dacsrc_mux_controls),
419 SND_SOC_DAPM_DAC("Right DAC", NULL, ES8316_DAC_PDN_REG2F, 0, 1),
420 SND_SOC_DAPM_DAC("Left DAC", NULL, ES8316_DAC_PDN_REG2F, 4, 1),
422 /* Headphone Output Side */
423 /* hpmux for hp mixer */
424 SND_SOC_DAPM_MUX("Left Hp mux", SND_SOC_NOPM, 0, 0,
425 &es8316_left_hpmux_controls),
426 SND_SOC_DAPM_MUX("Right Hp mux", SND_SOC_NOPM, 0, 0,
427 &es8316_right_hpmux_controls),
429 SND_SOC_DAPM_MIXER("Left Hp mixer", ES8316_HPMIX_PDN_REG15,
430 4, 1, &es8316_out_left_mix[0],
431 ARRAY_SIZE(es8316_out_left_mix)),
432 SND_SOC_DAPM_MIXER("Right Hp mixer", ES8316_HPMIX_PDN_REG15,
433 0, 1, &es8316_out_right_mix[0],
434 ARRAY_SIZE(es8316_out_right_mix)),
435 SND_SOC_DAPM_MIXER("Left Hp mixer", SND_SOC_NOPM,
436 4, 1, &es8316_out_left_mix[0],
437 ARRAY_SIZE(es8316_out_left_mix)),
438 SND_SOC_DAPM_MIXER("Right Hp mixer", SND_SOC_NOPM,
439 0, 1, &es8316_out_right_mix[0],
440 ARRAY_SIZE(es8316_out_right_mix)),
442 /* Ouput charge pump */
444 SND_SOC_DAPM_PGA("HPCP L", SND_SOC_NOPM,
446 SND_SOC_DAPM_PGA("HPCP R", SND_SOC_NOPM,
449 SND_SOC_DAPM_PGA("HPCP L", ES8316_CPHP_OUTEN_REG17,
451 SND_SOC_DAPM_PGA("HPCP R", ES8316_CPHP_OUTEN_REG17,
455 SND_SOC_DAPM_PGA("HPVOL L", SND_SOC_NOPM,
457 SND_SOC_DAPM_PGA("HPVOL R", SND_SOC_NOPM,
461 SND_SOC_DAPM_PGA("HPVOL L", ES8316_CPHP_OUTEN_REG17,
463 SND_SOC_DAPM_PGA("HPVOL R", ES8316_CPHP_OUTEN_REG17,
466 SND_SOC_DAPM_OUTPUT("HPOL"),
467 SND_SOC_DAPM_OUTPUT("HPOR"),
470 static const struct snd_soc_dapm_route es8316_dapm_routes[] = {
474 {"MIC1", NULL, "micbias"},
475 {"MIC2", NULL, "micbias"},
476 {"DMIC", NULL, "micbias"},
478 {"Differential Mux", "lin1-rin1", "MIC1"},
479 {"Differential Mux", "lin2-rin2", "MIC2"},
480 {"Line input PGA", NULL, "Differential Mux"},
482 {"Mono ADC", NULL, "Line input PGA"},
484 {"Digital Mic Mux", "dmic disable", "Mono ADC"},
485 {"Digital Mic Mux", "dmic data at high level", "DMIC"},
486 {"Digital Mic Mux", "dmic data at low level", "DMIC"},
488 {"I2S OUT", NULL, "Digital Mic Mux"},
492 {"DAC SRC Mux", "LDATA TO LDAC, RDATA TO RDAC", "I2S IN"},
493 {"DAC SRC Mux", "LDATA TO LDAC, LDATA TO RDAC", "I2S IN"},
494 {"DAC SRC Mux", "RDATA TO LDAC, RDATA TO RDAC", "I2S IN"},
495 {"DAC SRC Mux", "RDATA TO LDAC, LDATA TO RDAC", "I2S IN"},
497 {"Left DAC", NULL, "DAC SRC Mux"},
498 {"Right DAC", NULL, "DAC SRC Mux"},
500 {"Left Hp mux", "lin1-rin1", "MIC1"},
501 {"Left Hp mux", "lin2-rin2", "MIC2"},
502 {"Left Hp mux", "lin-rin with Boost", "Differential Mux"},
503 {"Left Hp mux", "lin-rin with Boost and PGA", "Line input PGA"},
505 {"Right Hp mux", "lin1-rin1", "MIC1"},
506 {"Right Hp mux", "lin2-rin2", "MIC2"},
507 {"Right Hp mux", "lin-rin with Boost", "Differential Mux"},
508 {"Right Hp mux", "lin-rin with Boost and PGA", "Line input PGA"},
510 {"Left Hp mixer", "LLIN Switch", "Left Hp mux"},
511 {"Left Hp mixer", "Left DAC Switch", "Left DAC"},
513 {"Right Hp mixer", "RLIN Switch", "Right Hp mux"},
514 {"Right Hp mixer", "Right DAC Switch", "Right DAC"},
516 {"HPCP L", NULL, "Left Hp mixer"},
517 {"HPCP R", NULL, "Right Hp mixer"},
519 {"HPVOL L", NULL, "HPCP L"},
520 {"HPVOL R", NULL, "HPCP R"},
522 {"HPOL", NULL, "HPVOL L"},
523 {"HPOR", NULL, "HPVOL R"},
527 u32 mclk; /*mclk frequency*/
528 u32 rate; /*sample rate*/
529 u8 div; /*adcclk and dacclk divider*/
530 u8 lrck_h; /*adclrck divider and daclrck divider*/
532 u8 sr; /*sclk divider*/
537 /* codec hifi mclk clock divider coefficients */
538 static const struct _coeff_div coeff_div[] = {
540 {12288000, 8000 , 6 , 0x06, 0x00, 21, 32},
541 {11289600, 8000 , 6 , 0x05, 0x83, 20, 29},
542 {18432000, 8000 , 9 , 0x09, 0x00, 27, 32},
543 {16934400, 8000 , 8 , 0x08, 0x44, 25, 33},
544 {12000000, 8000 , 7 , 0x05, 0xdc, 21, 25},
545 {19200000, 8000 , 12, 0x09, 0x60, 27, 25},
548 {11289600, 11025, 4 , 0x04, 0x00, 16, 32},
549 {16934400, 11025, 6 , 0x06, 0x00, 21, 32},
550 {12000000, 11025, 4 , 0x04, 0x40, 17, 34},
553 {12288000, 16000, 3 , 0x03, 0x00, 12, 32},
554 {18432000, 16000, 5 , 0x04, 0x80, 18, 25},
555 {12000000, 16000, 3 , 0x02, 0xee, 12, 31},
556 {19200000, 16000, 6 , 0x04, 0xb0, 18, 25},
559 {11289600, 22050, 2 , 0x02, 0x00, 8 , 32},
560 {16934400, 22050, 3 , 0x03, 0x00, 12, 32},
561 {12000000, 22050, 2 , 0x02, 0x20, 8 , 34},
564 {12288000, 32000, 1 , 0x01, 0x80, 6 , 48},
565 {18432000, 32000, 2 , 0x02, 0x40, 9 , 32},
566 {12000000, 32000, 1 , 0x01, 0x77, 6 , 31},
567 {19200000, 32000, 3 , 0x02, 0x58, 10, 25},
570 {11289600, 44100, 1 , 0x01, 0x00, 4 , 32},
571 {16934400, 44100, 1 , 0x01, 0x80, 6 , 32},
572 {12000000, 44100, 1 , 0x01, 0x10, 4 , 34},
575 {12288000, 48000, 1 , 0x01, 0x00, 4 , 32},
576 {18432000, 48000, 1 , 0x01, 0x80, 6 , 32},
577 {12000000, 48000, 1 , 0x00, 0xfa, 4 , 31},
578 {19200000, 48000, 2 , 0x01, 0x90, 6, 25},
581 {11289600, 88200, 1 , 0x00, 0x80, 2 , 32},
582 {16934400, 88200, 1 , 0x00, 0xc0, 3 , 48},
583 {12000000, 88200, 1 , 0x00, 0x88, 2 , 34},
586 {12288000, 96000, 1 , 0x00, 0x80, 2 , 32},
587 {18432000, 96000, 1 , 0x00, 0xc0, 3 , 48},
588 {12000000, 96000, 1 , 0x00, 0x7d, 1 , 31},
589 {19200000, 96000, 1 , 0x00, 0xc8, 3 , 25},
591 static inline int get_coeff(int mclk, int rate)
595 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
596 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
603 /* The set of rates we can generate from the above for each SYSCLK */
605 static unsigned int rates_12288[] = {
606 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
609 static struct snd_pcm_hw_constraint_list constraints_12288 = {
610 .count = ARRAY_SIZE(rates_12288),
614 static unsigned int rates_112896[] = {
615 8000, 11025, 22050, 44100,
618 static struct snd_pcm_hw_constraint_list constraints_112896 = {
619 .count = ARRAY_SIZE(rates_112896),
620 .list = rates_112896,
623 static unsigned int rates_12[] = {
624 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
628 static struct snd_pcm_hw_constraint_list constraints_12 = {
629 .count = ARRAY_SIZE(rates_12),
634 * Note that this should be called from init rather than from hw_params.
636 static int es8316_set_dai_sysclk(struct snd_soc_dai *codec_dai,
637 int clk_id, unsigned int freq, int dir)
639 struct snd_soc_codec *codec = codec_dai->codec;
640 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
647 es8316->sysclk_constraints = &constraints_112896;
648 es8316->sysclk = freq;
655 es8316->sysclk_constraints = &constraints_12288;
656 es8316->sysclk = freq;
660 es8316->sysclk_constraints = &constraints_12;
661 es8316->sysclk = freq;
667 static int es8316_set_dai_fmt(struct snd_soc_dai *codec_dai,
670 struct snd_soc_codec *codec = codec_dai->codec;
675 alsa_dbg("%s----%d, fmt[%02x]\n", __func__, __LINE__, fmt);
677 iface = snd_soc_read(codec, ES8316_IFACE);
678 adciface = snd_soc_read(codec, ES8316_ADC_IFACE);
679 daciface = snd_soc_read(codec, ES8316_DAC_IFACE);
681 /* set master/slave audio interface */
682 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
683 case SND_SOC_DAIFMT_CBM_CFM:
684 alsa_dbg("es8316 in master mode");
687 case SND_SOC_DAIFMT_CBS_CFS:
688 alsa_dbg("es8316 in slave mode");
696 /* interface format */
698 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
699 case SND_SOC_DAIFMT_I2S:
703 case SND_SOC_DAIFMT_RIGHT_J:
705 case SND_SOC_DAIFMT_LEFT_J:
711 case SND_SOC_DAIFMT_DSP_A:
717 case SND_SOC_DAIFMT_DSP_B:
728 /* clock inversion */
729 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
730 case SND_SOC_DAIFMT_NB_NF:
735 case SND_SOC_DAIFMT_IB_IF:
740 case SND_SOC_DAIFMT_IB_NF:
745 case SND_SOC_DAIFMT_NB_IF:
753 snd_soc_write(codec, ES8316_IFACE, iface);
754 snd_soc_write(codec, ES8316_ADC_IFACE, adciface);
755 snd_soc_write(codec, ES8316_DAC_IFACE, daciface);
759 static int es8316_pcm_startup(struct snd_pcm_substream *substream,
760 struct snd_soc_dai *dai)
762 struct snd_soc_codec *codec = dai->codec;
763 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
764 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
766 DBG("Enter::%s----%d es8316->sysclk=%d\n",
767 __func__, __LINE__, es8316->sysclk);
768 snd_soc_write(codec, ES8316_RESET_REG00, 0xC0);
769 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x00);
770 /* es8316: both playback and capture need dac mclk */
771 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01,
772 ES8316_CLKMGR_MCLK_DIV_MASK |
773 ES8316_CLKMGR_DAC_MCLK_MASK,
774 ES8316_CLKMGR_MCLK_DIV_NML |
775 ES8316_CLKMGR_DAC_MCLK_EN);
779 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0x3F);
780 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0x1F);
781 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x88);
782 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x00);
783 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0xBB);
784 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x10);
785 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x30);
786 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x02);
787 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x00);
788 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x66);
789 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01,
790 ES8316_CLKMGR_DAC_MCLK_MASK |
791 ES8316_CLKMGR_DAC_ANALOG_MASK,
792 ES8316_CLKMGR_DAC_MCLK_EN |
793 ES8316_CLKMGR_DAC_ANALOG_EN);
795 DBG("%s playback\n", __func__);
797 snd_soc_update_bits(codec,
798 ES8316_ADC_PDN_LINSEL_REG22, 0xC0, 0x20);
799 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01,
800 ES8316_CLKMGR_ADC_MCLK_MASK |
801 ES8316_CLKMGR_ADC_ANALOG_MASK,
802 ES8316_CLKMGR_ADC_MCLK_EN |
803 ES8316_CLKMGR_ADC_ANALOG_EN);
804 DBG("%s capture\n", __func__);
807 /* The set of sample rates that can be supported depends on the
808 * MCLK supplied to the CODEC - enforce this.
810 if (!es8316->sysclk) {
812 "No MCLK configured, call set_sysclk() on init\n");
816 snd_pcm_hw_constraint_list(substream->runtime, 0,
817 SNDRV_PCM_HW_PARAM_RATE,
818 es8316->sysclk_constraints);
823 static void es8316_pcm_shutdown(struct snd_pcm_substream *substream,
824 struct snd_soc_dai *dai)
826 struct snd_soc_pcm_runtime *rtd = substream->private_data;
827 struct snd_soc_codec *codec = rtd->codec;
828 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
829 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
832 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x00);
833 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
834 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x03);
835 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x22);
836 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x06);
837 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x00);
838 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x33);
839 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0x00);
840 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x00);
841 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0xFF);
842 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0xFF);
843 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01,
844 ES8316_CLKMGR_DAC_ANALOG_MASK,
845 ES8316_CLKMGR_DAC_ANALOG_DIS);
846 DBG("%s playback\n", __func__);
848 snd_soc_write(codec, ES8316_ADC_PDN_LINSEL_REG22, 0xc0);
849 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01,
850 ES8316_CLKMGR_ADC_MCLK_MASK |
851 ES8316_CLKMGR_ADC_ANALOG_MASK,
852 ES8316_CLKMGR_ADC_MCLK_DIS |
853 ES8316_CLKMGR_ADC_ANALOG_DIS);
854 DBG("%s capture\n", __func__);
857 if (--es8316->pwr_count) {
858 DBG("%s pwr count: %d\n", __func__, es8316->pwr_count);
860 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x3F);
861 snd_soc_write(codec, ES8316_CLKMGR_CLKSW_REG01, 0xF3);
862 DBG("%s pwr count close ES8316_SYS_PDN_REG0D\n", __func__);
866 static int es8316_pcm_hw_params(struct snd_pcm_substream *substream,
867 struct snd_pcm_hw_params *params,
868 struct snd_soc_dai *dai)
870 struct snd_soc_pcm_runtime *rtd = substream->private_data;
871 struct snd_soc_codec *codec = rtd->codec;
872 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
875 u16 osrate = snd_soc_read(codec,
876 ES8316_CLKMGR_ADCOSR_REG03) & 0xc0;
877 u16 mclkdiv = snd_soc_read(codec,
878 ES8316_CLKMGR_CLKSW_REG01) & 0x7f;
879 u16 srate = snd_soc_read(codec,
880 ES8316_SDP_MS_BCKDIV_REG09) & 0xE0;
881 u16 adciface = snd_soc_read(codec,
882 ES8316_SDP_ADCFMT_REG0A) & 0xE3;
883 u16 daciface = snd_soc_read(codec,
884 ES8316_SDP_DACFMT_REG0B) & 0xE3;
885 u16 adcdiv = snd_soc_read(codec,
886 ES8316_CLKMGR_ADCDIV1_REG04);
887 u16 adclrckdiv_l = snd_soc_read(codec,
888 ES8316_CLKMGR_ADCDIV2_REG05) & 0x00;
889 u16 dacdiv = snd_soc_read(codec, ES8316_CLKMGR_DACDIV1_REG06);
890 u16 daclrckdiv_l = snd_soc_read(codec,
891 ES8316_CLKMGR_DACDIV2_REG07) & 0x00;
893 u16 adclrckdiv_h = adcdiv & 0xf0;
894 u16 daclrckdiv_h = dacdiv & 0xf0;
900 coeff = get_coeff(es8316->sysclk, params_rate(params));
902 coeff = get_coeff(es8316->sysclk / 2, params_rate(params));
907 "Unable to configure sample rate %dHz with %dHz MCLK\n",
908 params_rate(params), es8316->sysclk);
913 switch (params_format(params)) {
914 case SNDRV_PCM_FORMAT_S16_LE:
918 case SNDRV_PCM_FORMAT_S20_3LE:
922 case SNDRV_PCM_FORMAT_S24_LE:
924 case SNDRV_PCM_FORMAT_S32_LE:
930 /* set iface & srate*/
931 snd_soc_update_bits(codec, ES8316_SDP_DACFMT_REG0B, 0xe3, daciface);
932 snd_soc_update_bits(codec, ES8316_SDP_ADCFMT_REG0A, 0xe3, adciface);
933 snd_soc_update_bits(codec, ES8316_CLKMGR_CLKSW_REG01, 0x80, mclkdiv);
935 osrate = coeff_div[coeff].osr;
938 srate |= coeff_div[coeff].sr;
941 adcdiv |= (coeff_div[coeff].div << 4);
942 adclrckdiv_h |= coeff_div[coeff].lrck_h;
944 adclrckdiv_h &= 0x0f;
945 adcdiv |= adclrckdiv_h;
946 adclrckdiv_l = coeff_div[coeff].lrck_l;
948 dacdiv |= (coeff_div[coeff].div << 4);
949 daclrckdiv_h |= coeff_div[coeff].lrck_h;
951 daclrckdiv_h &= 0x0f;
952 dacdiv |= daclrckdiv_h;
953 daclrckdiv_l = coeff_div[coeff].lrck_l;
956 retv = snd_soc_read(codec, ES8316_GPIO_FLAG);
960 static int es8316_mute(struct snd_soc_dai *dai, int mute)
962 struct snd_soc_codec *codec = dai->codec;
963 struct es8316_priv *es8316 = es8316_private;
967 es8316_set_gpio(ES8316_CODEC_SET_SPK, !es8316->spk_gpio_level);
969 snd_soc_write(codec, ES8316_DAC_SET1_REG30, 0x20);
970 } else if (dai->playback_active) {
971 snd_soc_write(codec, ES8316_DAC_SET1_REG30, 0x00);
973 if (hp_irq_flag == 0)
974 es8316_set_gpio(ES8316_CODEC_SET_SPK,
975 es8316->spk_gpio_level);
981 static int es8316_set_bias_level(struct snd_soc_codec *codec,
982 enum snd_soc_bias_level level)
985 case SND_SOC_BIAS_ON:
986 dev_dbg(codec->dev, "%s on\n", __func__);
988 case SND_SOC_BIAS_PREPARE:
989 dev_dbg(codec->dev, "%s prepare\n", __func__);
991 case SND_SOC_BIAS_STANDBY:
992 dev_dbg(codec->dev, "%s standby\n", __func__);
994 case SND_SOC_BIAS_OFF:
995 dev_dbg(codec->dev, "%s off\n", __func__);
996 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x00);
997 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
998 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x03);
999 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x22);
1000 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x06);
1001 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x00);
1002 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x33);
1003 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0x00);
1004 snd_soc_write(codec, ES8316_ADC_PDN_LINSEL_REG22, 0xC0);
1005 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x3F);
1006 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0x3F);
1007 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0x1F);
1008 snd_soc_write(codec, ES8316_RESET_REG00, 0x00);
1011 codec->dapm.bias_level = level;
1016 #define es8316_RATES SNDRV_PCM_RATE_8000_96000
1018 #define es8316_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1019 SNDRV_PCM_FMTBIT_S24_LE)
1021 static struct snd_soc_dai_ops es8316_ops = {
1022 .startup = es8316_pcm_startup,
1023 .hw_params = es8316_pcm_hw_params,
1024 .set_fmt = es8316_set_dai_fmt,
1025 .set_sysclk = es8316_set_dai_sysclk,
1026 .digital_mute = es8316_mute,
1027 .shutdown = es8316_pcm_shutdown,
1030 static struct snd_soc_dai_driver es8316_dai = {
1031 .name = "ES8316 HiFi",
1033 .stream_name = "Playback",
1036 .rates = es8316_RATES,
1037 .formats = es8316_FORMATS,
1040 .stream_name = "Capture",
1043 .rates = es8316_RATES,
1044 .formats = es8316_FORMATS,
1047 .symmetric_rates = 1,
1051 static int es8316_init_regs(struct snd_soc_codec *codec)
1053 dev_dbg(codec->dev, "%s\n", __func__);
1055 snd_soc_write(codec, ES8316_RESET_REG00, 0x3f);
1056 usleep_range(5000, 5500);
1057 snd_soc_write(codec, ES8316_RESET_REG00, 0x00);
1058 snd_soc_write(codec, ES8316_SYS_VMIDSEL_REG0C, 0xFF);
1060 snd_soc_write(codec, ES8316_CLKMGR_CLKSEL_REG02, 0x08);
1061 snd_soc_write(codec, ES8316_CLKMGR_ADCOSR_REG03, 0x20);
1062 snd_soc_write(codec, ES8316_CLKMGR_ADCDIV1_REG04, 0x11);
1063 snd_soc_write(codec, ES8316_CLKMGR_ADCDIV2_REG05, 0x00);
1064 snd_soc_write(codec, ES8316_CLKMGR_DACDIV1_REG06, 0x11);
1065 snd_soc_write(codec, ES8316_CLKMGR_DACDIV2_REG07, 0x00);
1066 snd_soc_write(codec, ES8316_CLKMGR_CPDIV_REG08, 0x00);
1067 snd_soc_write(codec, ES8316_SDP_MS_BCKDIV_REG09, 0x04);
1068 snd_soc_write(codec, ES8316_CLKMGR_CLKSW_REG01, 0x7F);
1069 snd_soc_write(codec, ES8316_CAL_TYPE_REG1C, 0x0F);
1070 snd_soc_write(codec, ES8316_CAL_HPLIV_REG1E, 0x90);
1071 snd_soc_write(codec, ES8316_CAL_HPRIV_REG1F, 0x90);
1072 snd_soc_write(codec, ES8316_ADC_VOLUME_REG27, 0x00);
1073 snd_soc_write(codec, ES8316_ADC_PDN_LINSEL_REG22, 0xc0);
1074 snd_soc_write(codec, ES8316_ADC_D2SEPGA_REG24, 0x00);
1075 snd_soc_write(codec, ES8316_ADC_DMIC_REG25, 0x08);
1076 snd_soc_write(codec, ES8316_DAC_SET2_REG31, 0x20);
1077 snd_soc_write(codec, ES8316_DAC_SET3_REG32, 0x00);
1078 snd_soc_write(codec, ES8316_DAC_VOLL_REG33, 0x00);
1079 snd_soc_write(codec, ES8316_DAC_VOLR_REG34, 0x00);
1080 snd_soc_write(codec, ES8316_SDP_ADCFMT_REG0A, 0x00);
1081 snd_soc_write(codec, ES8316_SDP_DACFMT_REG0B, 0x00);
1082 snd_soc_write(codec, ES8316_SYS_VMIDLOW_REG10, 0x11);
1083 snd_soc_write(codec, ES8316_SYS_VSEL_REG11, 0xFC);
1084 snd_soc_write(codec, ES8316_SYS_REF_REG12, 0x28);
1085 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0x04);
1086 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0x0C);
1087 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
1088 snd_soc_write(codec, ES8316_HPMIX_SEL_REG13, 0x00);
1089 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x88);
1090 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x00);
1091 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0xBB);
1092 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x10);
1093 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x30);
1094 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x02);
1095 snd_soc_write(codec, ES8316_CPHP_ICAL_VOL_REG18, 0x00);
1096 snd_soc_write(codec, ES8316_GPIO_SEL_REG4D, 0x00);
1097 snd_soc_write(codec, ES8316_GPIO_DEBUNCE_INT_REG4E, 0x02);
1098 snd_soc_write(codec, ES8316_TESTMODE_REG50, 0xA0);
1099 snd_soc_write(codec, ES8316_TEST1_REG51, 0x00);
1100 snd_soc_write(codec, ES8316_TEST2_REG52, 0x00);
1101 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x00);
1102 snd_soc_write(codec, ES8316_RESET_REG00, 0xC0);
1104 snd_soc_write(codec, ES8316_ADC_PGAGAIN_REG23, 0x60);
1105 snd_soc_write(codec, ES8316_ADC_D2SEPGA_REG24, 0x01);
1106 /* adc ds mode, HPF enable */
1107 snd_soc_write(codec, ES8316_ADC_DMIC_REG25, 0x08);
1108 snd_soc_write(codec, ES8316_ADC_ALC1_REG29, 0xcd);
1109 snd_soc_write(codec, ES8316_ADC_ALC2_REG2A, 0x08);
1110 snd_soc_write(codec, ES8316_ADC_ALC3_REG2B, 0xa0);
1111 snd_soc_write(codec, ES8316_ADC_ALC4_REG2C, 0x05);
1112 snd_soc_write(codec, ES8316_ADC_ALC5_REG2D, 0x06);
1113 snd_soc_write(codec, ES8316_ADC_ALC6_REG2E, 0x61);
1117 static int es8316_suspend(struct snd_soc_codec *codec)
1122 static int es8316_resume(struct snd_soc_codec *codec)
1124 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
1127 pr_info("%s: %d\n", __func__, __LINE__);
1128 retv = es8316_reset(codec); /* UPDATED BY DAVID,15-3-5 */
1129 retv = snd_soc_read(codec, ES8316_CLKMGR_ADCDIV2_REG05);
1131 es8316_init_regs(codec);
1132 if (es8316->dmic_amic == dmic_used) {
1133 /* set gpio2 to DMIC CLK */
1134 snd_soc_write(codec, ES8316_GPIO_SEL_REG4D, 0x02);
1136 /* set gpio2 to GM SHORT */
1137 snd_soc_write(codec, ES8316_GPIO_SEL_REG4D, 0x00);
1139 /* max debance time, enable interrupt, low active */
1140 snd_soc_write(codec, ES8316_GPIO_DEBUNCE_INT_REG4E, 0xf3);
1141 /* es8316_set_bias_level(codec, SND_SOC_BIAS_OFF); */
1142 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x00);
1143 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
1144 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x03);
1145 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x22);
1146 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x06);
1147 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x00);
1148 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x33);
1149 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0x00);
1150 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x3F);
1151 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0xFF);
1152 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0xFF);
1153 snd_soc_write(codec, ES8316_CLKMGR_CLKSW_REG01, 0xF3);
1154 snd_soc_write(codec, ES8316_ADC_PDN_LINSEL_REG22, 0xc0);
1155 es8316_init_reg = 1;
1160 static int es8316_probe(struct snd_soc_codec *codec)
1163 struct es8316_priv *es8316 = snd_soc_codec_get_drvdata(codec);
1165 DBG("---%s--start--\n", __func__);
1167 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
1170 dev_err(codec->dev, "fail to reset audio (%d)\n", ret);
1173 retv = snd_soc_read(codec, ES8316_CLKMGR_ADCDIV2_REG05);
1175 retv = es8316_reset(codec); /* UPDATED BY DAVID,15-3-5 */
1176 retv = snd_soc_read(codec, ES8316_CLKMGR_ADCDIV2_REG05);
1177 pr_err("%s: %d, retv=%x\n", __func__, __LINE__, retv);
1179 es8316_init_regs(codec);
1180 if (es8316->dmic_amic == dmic_used) {
1181 /* set gpio2 to DMIC CLK */
1182 snd_soc_write(codec,
1183 ES8316_GPIO_SEL_REG4D, 0x02);
1185 /* set gpio2 to GM SHORT */
1186 snd_soc_write(codec,
1187 ES8316_GPIO_SEL_REG4D, 0x00);
1189 /* max debance time, enable interrupt, low active */
1190 snd_soc_write(codec,
1191 ES8316_GPIO_DEBUNCE_INT_REG4E, 0xf3);
1193 /* es8316_set_bias_level(codec, SND_SOC_BIAS_OFF); */
1194 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x00);
1195 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
1196 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x03);
1197 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x22);
1198 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x06);
1199 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x00);
1200 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x33);
1201 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0x00);
1202 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x3F);
1203 snd_soc_write(codec, ES8316_SYS_LP1_REG0E, 0xFF);
1204 snd_soc_write(codec, ES8316_SYS_LP2_REG0F, 0xFF);
1205 snd_soc_write(codec, ES8316_CLKMGR_CLKSW_REG01, 0xF3);
1206 snd_soc_write(codec,
1207 ES8316_ADC_PDN_LINSEL_REG22, 0xc0);
1208 es8316_init_reg = 1;
1211 codec->dapm.idle_bias_off = 0;
1214 #elif defined(HS_TIMER)
1221 static int es8316_remove(struct snd_soc_codec *codec)
1223 es8316_set_bias_level(codec, SND_SOC_BIAS_OFF);
1227 static struct snd_soc_codec_driver soc_codec_dev_es8316 = {
1228 .probe = es8316_probe,
1229 .remove = es8316_remove,
1230 .suspend = es8316_suspend,
1231 .resume = es8316_resume,
1232 .set_bias_level = es8316_set_bias_level,
1233 .reg_cache_size = ARRAY_SIZE(es8316_reg_defaults),
1234 .reg_word_size = sizeof(u8),
1235 .reg_cache_default = es8316_reg_defaults,
1236 .volatile_register = es8316_volatile,
1237 .readable_register = es8316_readable,
1239 .controls = es8316_snd_controls,
1240 .num_controls = ARRAY_SIZE(es8316_snd_controls),
1241 .dapm_widgets = es8316_dapm_widgets,
1242 .num_dapm_widgets = ARRAY_SIZE(es8316_dapm_widgets),
1243 .dapm_routes = es8316_dapm_routes,
1244 .num_dapm_routes = ARRAY_SIZE(es8316_dapm_routes),
1247 #if defined(CONFIG_SPI_MASTER)
1248 static int es8316_spi_probe(struct spi_device *spi)
1250 struct es8316_priv *es8316;
1253 es8316 = kzalloc(sizeof(*es8316), GFP_KERNEL);
1257 spi_set_drvdata(spi, es8316);
1258 ret = snd_soc_register_codec(&spi->dev,
1259 &soc_codec_dev_es8316,
1266 static int es8316_spi_remove(struct spi_device *spi)
1268 snd_soc_unregister_codec(&spi->dev);
1269 kfree(spi_get_drvdata(spi));
1273 static struct spi_driver es8316_spi_driver = {
1276 .owner = THIS_MODULE,
1278 .probe = es8316_spi_probe,
1279 .remove = es8316_spi_remove,
1281 #endif /* CONFIG_SPI_MASTER */
1283 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1285 static void es8316_i2c_shutdown(struct i2c_client *i2c)
1287 struct snd_soc_codec *codec;
1288 struct es8316_priv *es8316 = es8316_private;
1293 es8316_set_gpio(ES8316_CODEC_SET_SPK, !es8316->spk_gpio_level);
1297 codec = es8316_codec;
1298 snd_soc_write(codec, ES8316_CPHP_ICAL_VOL_REG18, 0x33);
1299 snd_soc_write(codec, ES8316_CPHP_OUTEN_REG17, 0x00);
1300 snd_soc_write(codec, ES8316_CPHP_LDOCTL_REG1B, 0x03);
1301 snd_soc_write(codec, ES8316_CPHP_PDN2_REG1A, 0x22);
1302 snd_soc_write(codec, ES8316_CPHP_PDN1_REG19, 0x06);
1303 snd_soc_write(codec, ES8316_HPMIX_SWITCH_REG14, 0x00);
1304 snd_soc_write(codec, ES8316_HPMIX_PDN_REG15, 0x33);
1305 snd_soc_write(codec, ES8316_HPMIX_VOL_REG16, 0x00);
1306 snd_soc_write(codec, ES8316_ADC_PDN_LINSEL_REG22, 0xC0);
1307 snd_soc_write(codec, ES8316_DAC_PDN_REG2F, 0x11);
1308 snd_soc_write(codec, ES8316_SYS_PDN_REG0D, 0x3F);
1309 snd_soc_write(codec, ES8316_CLKMGR_CLKSW_REG01, 0x03);
1310 snd_soc_write(codec, ES8316_RESET_REG00, 0x7F);
1315 static int es8316_i2c_probe(struct i2c_client *i2c_client,
1316 const struct i2c_device_id *id)
1318 struct es8316_priv *es8316;
1320 unsigned long irq_flag = 0;
1323 enum of_gpio_flags flags;
1324 struct device_node *np = i2c_client->dev.of_node;
1326 DBG("---%s---probe start\n", __func__);
1328 es8316 = kzalloc(sizeof(*es8316), GFP_KERNEL);
1332 es8316_private = es8316;
1334 es8316->dmic_amic = amic_used; /*if internal mic is amic*/
1335 es8316->pwr_count = 0;
1336 i2c_set_clientdata(i2c_client, es8316);
1339 es8316->spk_ctl_gpio = of_get_named_gpio_flags(np,
1340 "spk-con-gpio", 0, &flags);
1341 if (es8316->spk_ctl_gpio < 0) {
1342 DBG("%s() Can not read property spk codec-en-gpio\n", __func__);
1343 es8316->spk_ctl_gpio = INVALID_GPIO;
1345 es8316->spk_gpio_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
1346 ret = gpio_request(es8316->spk_ctl_gpio, NULL);
1347 gpio_direction_output(es8316->spk_ctl_gpio,
1348 !es8316->spk_gpio_level);
1351 es8316->hp_ctl_gpio = of_get_named_gpio_flags(np,
1352 "hp-con-gpio", 0, &flags);
1353 if (es8316->hp_ctl_gpio < 0) {
1354 DBG("%s() Can not read property hp codec-en-gpio\n", __func__);
1355 es8316->hp_ctl_gpio = INVALID_GPIO;
1357 es8316->hp_gpio_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
1358 ret = gpio_request(es8316->hp_ctl_gpio, NULL);
1359 gpio_direction_output(es8316->hp_ctl_gpio, !es8316->hp_gpio_level);
1362 es8316->hp_det_gpio = of_get_named_gpio_flags(np,
1363 "hp-det-gpio", 0, &flags);
1364 if (es8316->hp_det_gpio < 0) {
1365 DBG("%s() Can not read property hp_det gpio\n", __func__);
1366 es8316->hp_det_gpio = INVALID_GPIO;
1368 es8316->hp_det_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
1369 ret = gpio_request(es8316->hp_det_gpio, NULL);
1371 DBG("%s request HP_DET error", __func__);
1374 gpio_direction_input(es8316->hp_det_gpio);
1376 irq_flag = IRQF_TRIGGER_LOW | IRQF_ONESHOT;
1377 hp_irq = gpio_to_irq(es8316->hp_det_gpio);
1379 val = gpio_get_value(es8316->hp_det_gpio);
1380 if (val == es8316->hp_det_level) {
1381 pr_info("hp inserted.\n");
1383 es8316_set_gpio(ES8316_CODEC_SET_SPK,
1384 !es8316->spk_gpio_level);
1388 ret = request_threaded_irq(hp_irq, NULL,
1389 hp_det_irq_handler, irq_flag, "ES8316", NULL);
1392 ret = snd_soc_register_codec(&i2c_client->dev,
1393 &soc_codec_dev_es8316,
1405 static int es8316_i2c_remove(struct i2c_client *client)
1407 snd_soc_unregister_codec(&client->dev);
1408 kfree(i2c_get_clientdata(client));
1412 static const unsigned short normal_i2c[] = {0x10, I2C_CLIENT_END};
1413 static const struct i2c_device_id es8316_i2c_id[] = {
1419 MODULE_DEVICE_TABLE(i2c, es8316_i2c_id);
1421 static struct i2c_driver es8316_i2c_driver = {
1424 .owner = THIS_MODULE,
1426 .shutdown = es8316_i2c_shutdown,
1427 .probe = es8316_i2c_probe,
1428 .remove = es8316_i2c_remove,
1429 .id_table = es8316_i2c_id,
1430 .class = I2C_CLASS_HWMON,
1431 .address_list = normal_i2c,
1435 static int __init es8316_init(void)
1437 DBG("--%s--start--\n", __func__);
1438 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1439 return i2c_add_driver(&es8316_i2c_driver);
1441 #if defined(CONFIG_SPI_MASTER)
1442 return spi_register_driver(&es8316_spi_driver);
1446 static void __exit es8316_exit(void)
1448 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1449 return i2c_del_driver(&es8316_i2c_driver);
1451 #if defined(CONFIG_SPI_MASTER)
1452 return spi_unregister_driver(&es8316_spi_driver);
1457 module_init(es8316_init);
1458 module_exit(es8316_exit);
1460 MODULE_DESCRIPTION("ASoC es8316 driver");
1461 MODULE_AUTHOR("Will <will@everset-semi.com>");
1462 MODULE_LICENSE("GPL");