2 * es8323.c -- es8323 ALSA SoC audio driver
4 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
6 * Author: Mark Brown <will@everset-semi.com>
7 * Author: Jianqun Xu <jay.xu@rock-chips.com>
8 * Author: Nickey Yang <nickey.yang@rock-chips.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
21 #include <linux/i2c.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/of_gpio.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/tlv.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <linux/proc_fs.h>
33 #include <linux/gpio.h>
34 #include <linux/interrupt.h>
35 #include <linux/irq.h>
38 #define INVALID_GPIO -1
40 #define ES8323_CODEC_SET_SPK 1
41 #define ES8323_CODEC_SET_HP 2
43 #define es8323_DEF_VOL 0x20
45 static int es8323_set_bias_level(struct snd_soc_codec *codec,
46 enum snd_soc_bias_level level);
49 * es8323 register cache
50 * We can't read the es8323 register space when we
51 * are using 2 wire for device control, so we cache them instead.
53 static u16 es8323_reg[] = {
54 0x06, 0x1C, 0xC3, 0xFC, /* 0 */
55 0xC0, 0x00, 0x00, 0x7C, /* 4 */
56 0x80, 0x00, 0x00, 0x06, /* 8 */
57 0x00, 0x06, 0x30, 0x30, /* 12 */
58 0xC0, 0xC0, 0x38, 0xB0, /* 16 */
59 0x32, 0x06, 0x00, 0x00, /* 20 */
60 0x06, 0x30, 0xC0, 0xC0, /* 24 */
61 0x08, 0x06, 0x1F, 0xF7, /* 28 */
62 0xFD, 0xFF, 0x1F, 0xF7, /* 32 */
63 0xFD, 0xFF, 0x00, 0x38, /* 36 */
64 0x38, 0x38, 0x38, 0x38, /* 40 */
65 0x38, 0x00, 0x00, 0x00, /* 44 */
66 0x00, 0x00, 0x00, 0x00, /* 48 */
67 0x00, 0x00, 0x00, 0x00, /* 52 */
70 /* codec private data */
74 struct snd_pcm_hw_constraint_list *sysclk_constraints;
85 static struct es8323_priv *es8323_private;
86 static int es8323_set_gpio(int gpio, bool level)
88 struct es8323_priv *es8323 = es8323_private;
94 if ((gpio & ES8323_CODEC_SET_SPK) && es8323
95 && es8323->spk_ctl_gpio != INVALID_GPIO) {
96 gpio_set_value(es8323->spk_ctl_gpio, level);
102 static irqreturn_t hp_det_irq_handler(int irq, void *dev_id)
104 struct es8323_priv *es8323 = es8323_private;
106 if (gpio_get_value(es8323->hp_det_gpio))
107 es8323->hp_inserted = 0;
109 es8323->hp_inserted = 1;
111 if (es8323->muted == 0) {
112 if (es8323->hp_det_level != es8323->hp_inserted)
113 es8323_set_gpio(ES8323_CODEC_SET_SPK, !es8323->spk_gpio_level);
115 es8323_set_gpio(ES8323_CODEC_SET_SPK, es8323->spk_gpio_level);
120 static unsigned int es8323_read_reg_cache(struct snd_soc_codec *codec,
123 if (reg >= ARRAY_SIZE(es8323_reg))
125 return es8323_reg[reg];
128 static int es8323_write(struct snd_soc_codec *codec, unsigned int reg,
135 data[1] = value & 0x00ff;
137 if (reg < ARRAY_SIZE(es8323_reg))
138 es8323_reg[reg] = value;
139 ret = codec->hw_write(codec->control_data, data, 2);
148 static int es8323_reset(struct snd_soc_codec *codec)
150 snd_soc_write(codec, ES8323_CONTROL1, 0x80);
151 return snd_soc_write(codec, ES8323_CONTROL1, 0x00);
154 static const char *es8323_line_texts[] = {
155 "Line 1", "Line 2", "PGA"
158 static const unsigned int es8323_line_values[] = {
161 static const char *es8323_pga_sel[] = { "Line 1", "Line 2", "Differential" };
162 static const char *stereo_3d_txt[] =
163 { "No 3D ", "Level 1", "Level 2", "Level 3", "Level 4", "Level 5",
164 "Level 6", "Level 7" };
165 static const char *alc_func_txt[] = { "Off", "Right", "Left", "Stereo" };
166 static const char *ng_type_txt[] = { "Constant PGA Gain", "Mute ADC Output" };
167 static const char *deemph_txt[] = { "None", "32Khz", "44.1Khz", "48Khz" };
168 static const char *adcpol_txt[] =
169 { "Normal", "L Invert", "R Invert", "L + R Invert" };
170 static const char *es8323_mono_mux[] =
171 { "Stereo", "Mono (Left)", "Mono (Right)" };
172 static const char *es8323_diff_sel[] = { "Line 1", "Line 2" };
174 static const struct soc_enum es8323_enum[] = {
175 SOC_VALUE_ENUM_SINGLE(ES8323_DACCONTROL16, 3, 7, ARRAY_SIZE(es8323_line_texts), es8323_line_texts, es8323_line_values), /* LLINE */
176 SOC_VALUE_ENUM_SINGLE(ES8323_DACCONTROL16, 0, 7, ARRAY_SIZE(es8323_line_texts), es8323_line_texts, es8323_line_values), /* RLINE */
177 SOC_VALUE_ENUM_SINGLE(ES8323_ADCCONTROL2, 6, 3, ARRAY_SIZE(es8323_pga_sel), es8323_line_texts, es8323_line_values), /* Left PGA Mux */
178 SOC_VALUE_ENUM_SINGLE(ES8323_ADCCONTROL2, 4, 3, ARRAY_SIZE(es8323_pga_sel), es8323_line_texts, es8323_line_values), /* Right PGA Mux */
179 SOC_ENUM_SINGLE(ES8323_DACCONTROL7, 2, 8, stereo_3d_txt), /* stereo-3d */
180 SOC_ENUM_SINGLE(ES8323_ADCCONTROL10, 6, 4, alc_func_txt), /* alc func */
181 SOC_ENUM_SINGLE(ES8323_ADCCONTROL14, 1, 2, ng_type_txt), /* noise gate type */
182 SOC_ENUM_SINGLE(ES8323_DACCONTROL6, 6, 4, deemph_txt), /* Playback De-emphasis */
183 SOC_ENUM_SINGLE(ES8323_ADCCONTROL6, 6, 4, adcpol_txt),
184 SOC_ENUM_SINGLE(ES8323_ADCCONTROL3, 3, 3, es8323_mono_mux),
185 SOC_ENUM_SINGLE(ES8323_ADCCONTROL3, 7, 2, es8323_diff_sel),
188 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
189 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 50, 1);
190 static const DECLARE_TLV_DB_SCALE(dac_tlv, -9600, 50, 1);
191 static const DECLARE_TLV_DB_SCALE(out_tlv, -4500, 150, 0);
192 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
194 static const struct snd_kcontrol_new es8323_snd_controls[] = {
195 SOC_ENUM("3D Mode", es8323_enum[4]),
196 SOC_SINGLE("ALC Capture Target Volume", ES8323_ADCCONTROL11, 4, 15, 0),
197 SOC_SINGLE("ALC Capture Max PGA", ES8323_ADCCONTROL10, 3, 7, 0),
198 SOC_SINGLE("ALC Capture Min PGA", ES8323_ADCCONTROL10, 0, 7, 0),
199 SOC_ENUM("ALC Capture Function", es8323_enum[5]),
200 SOC_SINGLE("ALC Capture ZC Switch", ES8323_ADCCONTROL13, 6, 1, 0),
201 SOC_SINGLE("ALC Capture Hold Time", ES8323_ADCCONTROL11, 0, 15, 0),
202 SOC_SINGLE("ALC Capture Decay Time", ES8323_ADCCONTROL12, 4, 15, 0),
203 SOC_SINGLE("ALC Capture Attack Time", ES8323_ADCCONTROL12, 0, 15, 0),
204 SOC_SINGLE("ALC Capture NG Threshold", ES8323_ADCCONTROL14, 3, 31, 0),
205 SOC_ENUM("ALC Capture NG Type", es8323_enum[6]),
206 SOC_SINGLE("ALC Capture NG Switch", ES8323_ADCCONTROL14, 0, 1, 0),
207 SOC_SINGLE("ZC Timeout Switch", ES8323_ADCCONTROL13, 6, 1, 0),
208 SOC_DOUBLE_R_TLV("Capture Digital Volume", ES8323_ADCCONTROL8,
209 ES8323_ADCCONTROL9, 0, 255, 1, adc_tlv),
210 SOC_SINGLE("Capture Mute", ES8323_ADCCONTROL7, 2, 1, 0),
211 SOC_SINGLE_TLV("Left Channel Capture Volume", ES8323_ADCCONTROL1, 4, 15,
213 SOC_SINGLE_TLV("Right Channel Capture Volume", ES8323_ADCCONTROL1, 0,
215 SOC_ENUM("Playback De-emphasis", es8323_enum[7]),
216 SOC_ENUM("Capture Polarity", es8323_enum[8]),
217 SOC_DOUBLE_R_TLV("PCM Volume", ES8323_DACCONTROL4, ES8323_DACCONTROL5,
219 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", ES8323_DACCONTROL17, 3,
221 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", ES8323_DACCONTROL20,
222 3, 7, 1, bypass_tlv),
223 SOC_DOUBLE_R_TLV("Output 1 Playback Volume", ES8323_DACCONTROL24,
224 ES8323_DACCONTROL25, 0, 64, 0, out_tlv),
225 SOC_DOUBLE_R_TLV("Output 2 Playback Volume", ES8323_DACCONTROL26,
226 ES8323_DACCONTROL27, 0, 64, 0, out_tlv),
229 static const struct snd_kcontrol_new es8323_left_line_controls =
230 SOC_DAPM_ENUM("Route", es8323_enum[0]);
232 static const struct snd_kcontrol_new es8323_right_line_controls =
233 SOC_DAPM_ENUM("Route", es8323_enum[1]);
236 static const struct snd_kcontrol_new es8323_left_pga_controls =
237 SOC_DAPM_ENUM("Route", es8323_enum[2]);
240 static const struct snd_kcontrol_new es8323_right_pga_controls =
241 SOC_DAPM_ENUM("Route", es8323_enum[3]);
244 static const struct snd_kcontrol_new es8323_left_mixer_controls[] = {
245 SOC_DAPM_SINGLE("Left Playback Switch", ES8323_DACCONTROL17, 7, 1, 0),
246 SOC_DAPM_SINGLE("Left Bypass Switch", ES8323_DACCONTROL17, 6, 1, 0),
250 static const struct snd_kcontrol_new es8323_right_mixer_controls[] = {
251 SOC_DAPM_SINGLE("Right Playback Switch", ES8323_DACCONTROL20, 7, 1, 0),
252 SOC_DAPM_SINGLE("Right Bypass Switch", ES8323_DACCONTROL20, 6, 1, 0),
255 /* Differential Mux */
256 static const struct snd_kcontrol_new es8323_diffmux_controls =
257 SOC_DAPM_ENUM("Route", es8323_enum[10]);
260 static const struct snd_kcontrol_new es8323_monomux_controls =
261 SOC_DAPM_ENUM("Route", es8323_enum[9]);
263 static const struct snd_soc_dapm_widget es8323_dapm_widgets[] = {
264 SND_SOC_DAPM_INPUT("LINPUT1"),
265 SND_SOC_DAPM_INPUT("LINPUT2"),
266 SND_SOC_DAPM_INPUT("RINPUT1"),
267 SND_SOC_DAPM_INPUT("RINPUT2"),
269 SND_SOC_DAPM_MICBIAS("Mic Bias", ES8323_ADCPOWER, 3, 1),
271 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
272 &es8323_diffmux_controls),
274 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
275 &es8323_monomux_controls),
276 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
277 &es8323_monomux_controls),
279 SND_SOC_DAPM_MUX("Left PGA Mux", ES8323_ADCPOWER, 7, 1,
280 &es8323_left_pga_controls),
281 SND_SOC_DAPM_MUX("Right PGA Mux", ES8323_ADCPOWER, 6, 1,
282 &es8323_right_pga_controls),
284 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
285 &es8323_left_line_controls),
286 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
287 &es8323_right_line_controls),
289 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8323_ADCPOWER, 4, 1),
290 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8323_ADCPOWER, 5, 1),
292 /* gModify.Cmmt Implement when suspend/startup */
293 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8323_DACPOWER, 7, 0),
294 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8323_DACPOWER, 8, 0),
296 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
297 &es8323_left_mixer_controls[0],
298 ARRAY_SIZE(es8323_left_mixer_controls)),
299 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
300 &es8323_right_mixer_controls[0],
301 ARRAY_SIZE(es8323_right_mixer_controls)),
303 SND_SOC_DAPM_PGA("Right Out 2", ES8323_DACPOWER, 2, 0, NULL, 0),
304 SND_SOC_DAPM_PGA("Left Out 2", ES8323_DACPOWER, 3, 0, NULL, 0),
305 SND_SOC_DAPM_PGA("Right Out 1", ES8323_DACPOWER, 4, 0, NULL, 0),
306 SND_SOC_DAPM_PGA("Left Out 1", ES8323_DACPOWER, 5, 0, NULL, 0),
307 SND_SOC_DAPM_PGA("LAMP", ES8323_ADCCONTROL1, 4, 0, NULL, 0),
308 SND_SOC_DAPM_PGA("RAMP", ES8323_ADCCONTROL1, 0, 0, NULL, 0),
310 SND_SOC_DAPM_OUTPUT("LOUT1"),
311 SND_SOC_DAPM_OUTPUT("ROUT1"),
312 SND_SOC_DAPM_OUTPUT("LOUT2"),
313 SND_SOC_DAPM_OUTPUT("ROUT2"),
314 SND_SOC_DAPM_OUTPUT("VREF"),
317 static const struct snd_soc_dapm_route audio_map[] = {
319 {"Left Line Mux", "NULL", "LINPUT1"},
320 {"Left Line Mux", "NULL", "LINPUT2"},
321 {"Left Line Mux", "NULL", "Left PGA Mux"},
323 {"Right Line Mux", "NULL", "RINPUT1"},
324 {"Right Line Mux", "NULL", "RINPUT2"},
325 {"Right Line Mux", "NULL", "Right PGA Mux"},
327 {"Left PGA Mux", "LAMP", "LINPUT1"},
328 {"Left PGA Mux", "LAMP", "LINPUT2"},
329 {"Left PGA Mux", "LAMP", "Differential Mux"},
331 {"Right PGA Mux", "RAMP", "RINPUT1"},
332 {"Right PGA Mux", "RAMP", "RINPUT2"},
333 {"Right PGA Mux", "RAMP", "Differential Mux"},
335 {"Differential Mux", "LAMP", "LINPUT1"},
336 {"Differential Mux", "RAMP", "RINPUT1"},
337 {"Differential Mux", "LAMP", "LINPUT2"},
338 {"Differential Mux", "RAMP", "RINPUT2"},
340 {"Left ADC Mux", "Stereo", "Left PGA Mux"},
341 {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
343 {"Right ADC Mux", "Stereo", "Right PGA Mux"},
344 {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
346 {"Left ADC", NULL, "Left ADC Mux"},
347 {"Right ADC", NULL, "Right ADC Mux"},
349 {"Left Line Mux", "LAMP", "LINPUT1"},
350 {"Left Line Mux", "LAMP", "LINPUT2"},
351 {"Left Line Mux", "LAMP", "Left PGA Mux"},
353 {"Right Line Mux", "RAMP", "RINPUT1"},
354 {"Right Line Mux", "RAMP", "RINPUT2"},
355 {"Right Line Mux", "RAMP", "Right PGA Mux"},
357 {"Left Mixer", "Left Playback Switch", "Left DAC"},
358 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
360 {"Right Mixer", "Right Playback Switch", "Right DAC"},
361 {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
363 {"Left Out 1", NULL, "Left Mixer"},
364 {"LOUT1", NULL, "Left Out 1"},
365 {"Right Out 1", NULL, "Right Mixer"},
366 {"ROUT1", NULL, "Right Out 1"},
368 {"Left Out 2", NULL, "Left Mixer"},
369 {"LOUT2", NULL, "Left Out 2"},
370 {"Right Out 2", NULL, "Right Mixer"},
371 {"ROUT2", NULL, "Right Out 2"},
382 /* codec hifi mclk clock divider coefficients */
383 static const struct _coeff_div coeff_div[] = {
385 {12288000, 8000, 1536, 0xa, 0x0},
386 {11289600, 8000, 1408, 0x9, 0x0},
387 {18432000, 8000, 2304, 0xc, 0x0},
388 {16934400, 8000, 2112, 0xb, 0x0},
389 {12000000, 8000, 1500, 0xb, 0x1},
392 {11289600, 11025, 1024, 0x7, 0x0},
393 {16934400, 11025, 1536, 0xa, 0x0},
394 {12000000, 11025, 1088, 0x9, 0x1},
397 {12288000, 16000, 768, 0x6, 0x0},
398 {18432000, 16000, 1152, 0x8, 0x0},
399 {12000000, 16000, 750, 0x7, 0x1},
402 {11289600, 22050, 512, 0x4, 0x0},
403 {16934400, 22050, 768, 0x6, 0x0},
404 {12000000, 22050, 544, 0x6, 0x1},
407 {12288000, 32000, 384, 0x3, 0x0},
408 {18432000, 32000, 576, 0x5, 0x0},
409 {12000000, 32000, 375, 0x4, 0x1},
412 {11289600, 44100, 256, 0x2, 0x0},
413 {16934400, 44100, 384, 0x3, 0x0},
414 {12000000, 44100, 272, 0x3, 0x1},
417 {12288000, 48000, 256, 0x2, 0x0},
418 {18432000, 48000, 384, 0x3, 0x0},
419 {12000000, 48000, 250, 0x2, 0x1},
422 {11289600, 88200, 128, 0x0, 0x0},
423 {16934400, 88200, 192, 0x1, 0x0},
424 {12000000, 88200, 136, 0x1, 0x1},
427 {12288000, 96000, 128, 0x0, 0x0},
428 {18432000, 96000, 192, 0x1, 0x0},
429 {12000000, 96000, 125, 0x0, 0x1},
432 static inline int get_coeff(int mclk, int rate)
436 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
437 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
444 /* The set of rates we can generate from the above for each SYSCLK */
445 static unsigned int rates_12288[] = {
446 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
449 static struct snd_pcm_hw_constraint_list constraints_12288 = {
450 .count = ARRAY_SIZE(rates_12288),
454 static unsigned int rates_112896[] = {
455 8000, 11025, 22050, 44100,
458 static struct snd_pcm_hw_constraint_list constraints_112896 = {
459 .count = ARRAY_SIZE(rates_112896),
460 .list = rates_112896,
463 static unsigned int rates_12[] = {
464 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
468 static struct snd_pcm_hw_constraint_list constraints_12 = {
469 .count = ARRAY_SIZE(rates_12),
474 * Note that this should be called from init rather than from hw_params.
476 static int es8323_set_dai_sysclk(struct snd_soc_dai *codec_dai,
477 int clk_id, unsigned int freq, int dir)
479 struct snd_soc_codec *codec = codec_dai->codec;
480 struct es8323_priv *es8323 = snd_soc_codec_get_drvdata(codec);
487 es8323->sysclk_constraints = &constraints_112896;
488 es8323->sysclk = freq;
495 es8323->sysclk_constraints = &constraints_12288;
496 es8323->sysclk = freq;
501 es8323->sysclk_constraints = &constraints_12;
502 es8323->sysclk = freq;
508 static int es8323_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
510 struct snd_soc_codec *codec = codec_dai->codec;
515 iface = snd_soc_read(codec, ES8323_IFACE);
516 adciface = snd_soc_read(codec, ES8323_ADC_IFACE);
517 daciface = snd_soc_read(codec, ES8323_DAC_IFACE);
519 /* set master/slave audio interface */
520 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
521 case SND_SOC_DAIFMT_CBM_CFM: /* MASTER MODE */
524 case SND_SOC_DAIFMT_CBS_CFS: /* SLAVE MODE */
531 /* interface format */
532 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
533 case SND_SOC_DAIFMT_I2S:
537 case SND_SOC_DAIFMT_RIGHT_J:
539 case SND_SOC_DAIFMT_LEFT_J:
541 case SND_SOC_DAIFMT_DSP_A:
543 case SND_SOC_DAIFMT_DSP_B:
549 /* clock inversion */
550 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
551 case SND_SOC_DAIFMT_NB_NF:
556 case SND_SOC_DAIFMT_IB_IF:
561 case SND_SOC_DAIFMT_IB_NF:
566 case SND_SOC_DAIFMT_NB_IF:
575 snd_soc_write(codec, ES8323_IFACE, iface);
576 snd_soc_write(codec, ES8323_ADC_IFACE, adciface);
577 snd_soc_write(codec, ES8323_DAC_IFACE, daciface);
582 static int es8323_pcm_startup(struct snd_pcm_substream *substream,
583 struct snd_soc_dai *dai)
585 struct snd_soc_codec *codec = dai->codec;
586 struct es8323_priv *es8323 = snd_soc_codec_get_drvdata(codec);
588 /* The set of sample rates that can be supported depends on the
589 * MCLK supplied to the CODEC - enforce this.
591 if (!es8323->sysclk) {
593 "No MCLK configured, call set_sysclk() on init\n");
597 snd_pcm_hw_constraint_list(substream->runtime, 0,
598 SNDRV_PCM_HW_PARAM_RATE,
599 es8323->sysclk_constraints);
604 static int es8323_pcm_hw_params(struct snd_pcm_substream *substream,
605 struct snd_pcm_hw_params *params,
606 struct snd_soc_dai *dai)
608 struct snd_soc_pcm_runtime *rtd = substream->private_data;
609 struct snd_soc_codec *codec = rtd->codec;
610 struct es8323_priv *es8323 = snd_soc_codec_get_drvdata(codec);
611 u16 srate = snd_soc_read(codec, ES8323_IFACE) & 0x80;
612 u16 adciface = snd_soc_read(codec, ES8323_ADC_IFACE) & 0xE3;
613 u16 daciface = snd_soc_read(codec, ES8323_DAC_IFACE) & 0xC7;
616 coeff = get_coeff(es8323->sysclk, params_rate(params));
618 coeff = get_coeff(es8323->sysclk / 2, params_rate(params));
623 "Unable to configure sample rate %dHz with %dHz MCLK\n",
624 params_rate(params), es8323->sysclk);
629 switch (params_format(params)) {
630 case SNDRV_PCM_FORMAT_S16_LE:
634 case SNDRV_PCM_FORMAT_S20_3LE:
638 case SNDRV_PCM_FORMAT_S24_LE:
640 case SNDRV_PCM_FORMAT_S32_LE:
646 /* set iface & srate */
647 snd_soc_write(codec, ES8323_DAC_IFACE, daciface);
648 snd_soc_write(codec, ES8323_ADC_IFACE, adciface);
651 snd_soc_write(codec, ES8323_IFACE, srate);
652 snd_soc_write(codec, ES8323_ADCCONTROL5,
653 coeff_div[coeff].sr | (coeff_div[coeff].
655 snd_soc_write(codec, ES8323_DACCONTROL2,
656 coeff_div[coeff].sr | (coeff_div[coeff].
663 static int es8323_mute(struct snd_soc_dai *dai, int mute)
665 struct snd_soc_codec *codec = dai->codec;
666 struct es8323_priv *es8323 = snd_soc_codec_get_drvdata(codec);
668 es8323->muted = mute;
670 es8323_set_gpio(ES8323_CODEC_SET_SPK, !es8323->spk_gpio_level);
671 usleep_range(18000, 20000);
672 snd_soc_write(codec, ES8323_DACCONTROL3, 0x06);
674 snd_soc_write(codec, ES8323_DACCONTROL3, 0x02);
675 snd_soc_write(codec, 0x30, es8323_DEF_VOL);
676 snd_soc_write(codec, 0x31, es8323_DEF_VOL);
678 if (!es8323->hp_inserted)
679 es8323_set_gpio(ES8323_CODEC_SET_SPK, es8323->spk_gpio_level);
680 usleep_range(18000, 20000);
685 static int es8323_set_bias_level(struct snd_soc_codec *codec,
686 enum snd_soc_bias_level level)
688 struct es8323_priv *es8323 = snd_soc_codec_get_drvdata(codec);
691 case SND_SOC_BIAS_ON:
692 dev_dbg(codec->dev, "%s on\n", __func__);
694 case SND_SOC_BIAS_PREPARE:
695 dev_dbg(codec->dev, "%s prepare\n", __func__);
696 if (IS_ERR(es8323->mclk))
698 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
699 clk_disable_unprepare(es8323->mclk);
701 ret = clk_prepare_enable(es8323->mclk);
705 snd_soc_write(codec, ES8323_ANAVOLMANAG, 0x7C);
706 snd_soc_write(codec, ES8323_CHIPLOPOW1, 0x00);
707 snd_soc_write(codec, ES8323_CHIPLOPOW2, 0x00);
708 snd_soc_write(codec, ES8323_CHIPPOWER, 0x00);
709 snd_soc_write(codec, ES8323_ADCPOWER, 0x59);
711 case SND_SOC_BIAS_STANDBY:
712 dev_dbg(codec->dev, "%s standby\n", __func__);
713 snd_soc_write(codec, ES8323_ANAVOLMANAG, 0x7C);
714 snd_soc_write(codec, ES8323_CHIPLOPOW1, 0x00);
715 snd_soc_write(codec, ES8323_CHIPLOPOW2, 0x00);
716 snd_soc_write(codec, ES8323_CHIPPOWER, 0x00);
717 snd_soc_write(codec, ES8323_ADCPOWER, 0x59);
719 case SND_SOC_BIAS_OFF:
721 clk_disable_unprepare(es8323->mclk);
722 dev_dbg(codec->dev, "%s off\n", __func__);
723 snd_soc_write(codec, ES8323_ADCPOWER, 0xFF);
724 snd_soc_write(codec, ES8323_DACPOWER, 0xC0);
725 snd_soc_write(codec, ES8323_CHIPLOPOW1, 0xFF);
726 snd_soc_write(codec, ES8323_CHIPLOPOW2, 0xFF);
727 snd_soc_write(codec, ES8323_CHIPPOWER, 0xFF);
728 snd_soc_write(codec, ES8323_ANAVOLMANAG, 0x7B);
734 #define es8323_RATES SNDRV_PCM_RATE_8000_96000
736 #define es8323_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
737 SNDRV_PCM_FMTBIT_S24_LE)
739 static struct snd_soc_dai_ops es8323_ops = {
740 .startup = es8323_pcm_startup,
741 .hw_params = es8323_pcm_hw_params,
742 .set_fmt = es8323_set_dai_fmt,
743 .set_sysclk = es8323_set_dai_sysclk,
744 .digital_mute = es8323_mute,
747 static struct snd_soc_dai_driver es8323_dai = {
748 .name = "ES8323 HiFi",
750 .stream_name = "Playback",
753 .rates = es8323_RATES,
754 .formats = es8323_FORMATS,
757 .stream_name = "Capture",
760 .rates = es8323_RATES,
761 .formats = es8323_FORMATS,
764 .symmetric_rates = 1,
767 static int es8323_suspend(struct snd_soc_codec *codec)
769 snd_soc_write(codec, 0x19, 0x06);
770 snd_soc_write(codec, 0x30, 0x00);
771 snd_soc_write(codec, 0x31, 0x00);
772 snd_soc_write(codec, ES8323_ADCPOWER, 0xFF);
773 snd_soc_write(codec, ES8323_DACPOWER, 0xc0);
774 snd_soc_write(codec, ES8323_CHIPPOWER, 0xF3);
775 snd_soc_write(codec, 0x00, 0x00);
776 snd_soc_write(codec, 0x01, 0x58);
777 snd_soc_write(codec, 0x2b, 0x9c);
778 usleep_range(18000, 20000);
782 static int es8323_resume(struct snd_soc_codec *codec)
784 snd_soc_write(codec, 0x2b, 0x80);
785 snd_soc_write(codec, 0x01, 0x50);
786 snd_soc_write(codec, 0x00, 0x32);
787 snd_soc_write(codec, ES8323_CHIPPOWER, 0x00);
788 snd_soc_write(codec, ES8323_DACPOWER, 0x0c);
789 snd_soc_write(codec, ES8323_ADCPOWER, 0x59);
790 snd_soc_write(codec, 0x31, es8323_DEF_VOL);
791 snd_soc_write(codec, 0x30, es8323_DEF_VOL);
792 snd_soc_write(codec, 0x19, 0x02);
796 static struct snd_soc_codec *es8323_codec;
797 static int es8323_probe(struct snd_soc_codec *codec)
799 struct es8323_priv *es8323 = snd_soc_codec_get_drvdata(codec);
803 dev_err(codec->dev, "Codec device not registered\n");
807 es8323->mclk = devm_clk_get(codec->dev, "mclk");
808 if (IS_ERR(es8323->mclk)) {
809 dev_err(codec->dev, "%s mclk is missing or invalid\n", __func__);
810 return PTR_ERR(es8323->mclk);
812 ret = clk_prepare_enable(es8323->mclk);
816 codec->hw_write = (hw_write_t) i2c_master_send;
817 codec->control_data = container_of(codec->dev, struct i2c_client, dev);
819 es8323_codec = codec;
820 ret = es8323_reset(codec);
822 dev_err(codec->dev, "Failed to issue reset\n");
825 usleep_range(18000, 20000);
826 snd_soc_write(codec, 0x02, 0xf3);
827 snd_soc_write(codec, 0x2B, 0x80);
828 snd_soc_write(codec, 0x08, 0x00); /* ES8388 salve */
829 snd_soc_write(codec, 0x00, 0x35);
830 snd_soc_write(codec, 0x01, 0x50); /* PLAYBACK & RECORD Mode,EnRefr=1 */
831 snd_soc_write(codec, 0x03, 0x59); /* pdn_ana=0,ibiasgen_pdn=0 */
832 snd_soc_write(codec, 0x05, 0x00); /* pdn_ana=0,ibiasgen_pdn=0 */
833 snd_soc_write(codec, 0x06, 0x00); /* pdn_ana=0,ibiasgen_pdn=0 */
834 snd_soc_write(codec, 0x07, 0x7c);
835 snd_soc_write(codec, 0x09, 0x88); /* ADC L/R PGA = +24dB */
836 snd_soc_write(codec, 0x0a, 0xf0); /* ADC INPUT=LIN2/RIN2 */
837 snd_soc_write(codec, 0x0b, 0x82); /* ADC INPUT=LIN2/RIN2 */
838 snd_soc_write(codec, 0x0C, 0x4c); /* I2S-24BIT */
839 snd_soc_write(codec, 0x0d, 0x02); /* MCLK/LRCK=256 */
840 snd_soc_write(codec, 0x10, 0x00); /* ADC Left Volume=0db */
841 snd_soc_write(codec, 0x11, 0x00); /* ADC Right Volume=0db */
842 snd_soc_write(codec, 0x12, 0xea); /* ALC stereo MAXGAIN: 35.5dB, MINGAIN: +6dB (Record Volume increased!) */
843 snd_soc_write(codec, 0x13, 0xc0);
844 snd_soc_write(codec, 0x14, 0x05);
845 snd_soc_write(codec, 0x15, 0x06);
846 snd_soc_write(codec, 0x16, 0x53);
847 snd_soc_write(codec, 0x17, 0x18); /* I2S-16BIT */
848 snd_soc_write(codec, 0x18, 0x02);
849 snd_soc_write(codec, 0x1A, 0x0A); /* DAC VOLUME=0DB */
850 snd_soc_write(codec, 0x1B, 0x0A);
851 snd_soc_write(codec, 0x26, 0x12); /* Left DAC TO Left IXER */
852 snd_soc_write(codec, 0x27, 0xb8); /* Left DAC TO Left MIXER */
853 snd_soc_write(codec, 0x28, 0x38);
854 snd_soc_write(codec, 0x29, 0x38);
855 snd_soc_write(codec, 0x2A, 0xb8);
856 snd_soc_write(codec, 0x02, 0x00); /* START DLL and state-machine,START DSM */
857 snd_soc_write(codec, 0x19, 0x02); /* SOFT RAMP RATE=32LRCKS/STEP,Enable ZERO-CROSS CHECK,DAC MUTE */
858 snd_soc_write(codec, 0x04, 0x0c); /* pdn_ana=0,ibiasgen_pdn=0 */
859 usleep_range(18000, 20000);
860 snd_soc_write(codec, 0x2e, 0x00);
861 snd_soc_write(codec, 0x2f, 0x00);
862 snd_soc_write(codec, 0x30, 0x08);
863 snd_soc_write(codec, 0x31, 0x08);
864 usleep_range(18000, 20000);
865 snd_soc_write(codec, 0x30, 0x0f);
866 snd_soc_write(codec, 0x31, 0x0f);
867 usleep_range(18000, 20000);
868 snd_soc_write(codec, 0x30, 0x18);
869 snd_soc_write(codec, 0x31, 0x18);
870 usleep_range(18000, 20000);
871 snd_soc_write(codec, 0x04, 0x2c); /* pdn_ana=0,ibiasgen_pdn=0 */
873 es8323_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
877 static int es8323_remove(struct snd_soc_codec *codec)
879 es8323_set_bias_level(codec, SND_SOC_BIAS_OFF);
883 static struct snd_soc_codec_driver soc_codec_dev_es8323 = {
884 .probe = es8323_probe,
885 .remove = es8323_remove,
886 .suspend = es8323_suspend,
887 .resume = es8323_resume,
888 .set_bias_level = es8323_set_bias_level,
889 .reg_cache_size = ARRAY_SIZE(es8323_reg),
890 .reg_word_size = sizeof(u16),
891 .reg_cache_default = es8323_reg,
893 .read = es8323_read_reg_cache,
894 .write = es8323_write,
898 static int es8323_i2c_probe(struct i2c_client *i2c,
899 const struct i2c_device_id *id)
901 struct es8323_priv *es8323;
904 enum of_gpio_flags flags;
905 struct i2c_adapter *adapter = to_i2c_adapter(i2c->dev.parent);
908 if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) {
909 dev_warn(&adapter->dev,
910 "I2C-Adapter doesn't support I2C_FUNC_I2C\n");
914 es8323 = devm_kzalloc(&i2c->dev, sizeof(struct es8323_priv), GFP_KERNEL);
918 i2c_set_clientdata(i2c, es8323);
920 reg = ES8323_DACCONTROL18;
921 ret = i2c_master_recv(i2c, ®, 1);
923 dev_err(&i2c->dev, "i2c recv Failed\n");
927 es8323_private = es8323;
928 es8323->spk_ctl_gpio = of_get_named_gpio_flags(i2c->dev.of_node, "spk-con-gpio", 0, &flags);
929 if (es8323->spk_ctl_gpio < 0) {
930 dev_info(&i2c->dev, "Can not read property spk_ctl_gpio\n");
931 es8323->spk_ctl_gpio = INVALID_GPIO;
933 es8323->spk_gpio_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
934 ret = devm_gpio_request_one(&i2c->dev, es8323->spk_ctl_gpio, GPIOF_DIR_OUT, NULL);
936 dev_err(&i2c->dev, "Failed to request spk_ctl_gpio\n");
939 es8323_set_gpio(ES8323_CODEC_SET_SPK, !es8323->spk_gpio_level);
942 es8323->hp_det_gpio = of_get_named_gpio_flags(i2c->dev.of_node, "hp-det-gpio", 0, &flags);
943 if (es8323->hp_det_gpio < 0) {
944 dev_info(&i2c->dev, "Can not read property hp_det_gpio\n");
945 es8323->hp_det_gpio = INVALID_GPIO;
947 es8323->hp_det_level = (flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
948 ret = devm_gpio_request_one(&i2c->dev, es8323->hp_det_gpio, GPIOF_IN, NULL);
950 dev_err(&i2c->dev, "Failed to request hp_det_gpio\n");
953 hp_irq = gpio_to_irq(es8323->hp_det_gpio);
956 ret = devm_request_threaded_irq(&i2c->dev, hp_irq, NULL, hp_det_irq_handler,
957 IRQ_TYPE_EDGE_BOTH | IRQF_ONESHOT,"ES8323", NULL);
959 dev_err(&i2c->dev, "request_irq failed: %d\n", ret);
964 ret = snd_soc_register_codec(&i2c->dev,
965 &soc_codec_dev_es8323,
970 static int es8323_i2c_remove(struct i2c_client *client)
972 snd_soc_unregister_codec(&client->dev);
976 static const struct i2c_device_id es8323_i2c_id[] = {
981 MODULE_DEVICE_TABLE(i2c, es8323_i2c_id);
983 void es8323_i2c_shutdown(struct i2c_client *client)
985 struct es8323_priv *es8323 = es8323_private;
987 es8323_set_gpio(ES8323_CODEC_SET_SPK, !es8323->spk_gpio_level);
989 snd_soc_write(es8323_codec, ES8323_CONTROL2, 0x58);
990 snd_soc_write(es8323_codec, ES8323_CONTROL1, 0x32);
991 snd_soc_write(es8323_codec, ES8323_CHIPPOWER, 0xf3);
992 snd_soc_write(es8323_codec, ES8323_DACPOWER, 0xc0);
994 snd_soc_write(es8323_codec, ES8323_DACCONTROL26, 0x00);
995 snd_soc_write(es8323_codec, ES8323_DACCONTROL27, 0x00);
997 snd_soc_write(es8323_codec, ES8323_CONTROL1, 0x30);
998 snd_soc_write(es8323_codec, ES8323_CONTROL1, 0x34);
1001 static const struct of_device_id es8323_of_match[] = {
1002 { .compatible = "everest,es8323", },
1005 MODULE_DEVICE_TABLE(of, es8323_of_match);
1007 static struct i2c_driver es8323_i2c_driver = {
1010 .of_match_table = of_match_ptr(es8323_of_match),
1012 .shutdown = es8323_i2c_shutdown,
1013 .probe = es8323_i2c_probe,
1014 .remove = es8323_i2c_remove,
1015 .id_table = es8323_i2c_id,
1017 module_i2c_driver(es8323_i2c_driver);
1019 MODULE_DESCRIPTION("ASoC es8323 driver");
1020 MODULE_AUTHOR("Mark Brown <will@everset-semi.com>");
1021 MODULE_LICENSE("GPL");