2 * es8323.c -- es8323 ALSA SoC audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
5 * Copyright 2005 Openedhand Ltd.
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/slab.h>
22 #include <linux/of_gpio.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/tlv.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30 #include <linux/proc_fs.h>
31 #include <linux/gpio.h>
32 #include <linux/interrupt.h>
33 #include <linux/irq.h>
37 #define DBG(x...) printk(x)
39 #define DBG(x...) do { } while (0)
43 #define INVALID_GPIO -1
45 #define ES8323_CODEC_SET_SPK 1
46 #define ES8323_CODEC_SET_HP 2
48 static bool hp_irq_flag = 0;
51 #ifndef es8323_DEF_VOL
52 #define es8323_DEF_VOL 0x1b
55 static int es8323_set_bias_level(struct snd_soc_codec *codec,enum snd_soc_bias_level level);
58 * es8323 register cache
59 * We can't read the es8323 register space when we
60 * are using 2 wire for device control, so we cache them instead.
62 static u16 es8323_reg[] = {
63 0x06, 0x1C, 0xC3, 0xFC, /* 0 *////0x0100 0x0180
64 0xC0, 0x00, 0x00, 0x7C, /* 4 */
65 0x80, 0x00, 0x00, 0x06, /* 8 */
66 0x00, 0x06, 0x30, 0x30, /* 12 */
67 0xC0, 0xC0, 0x38, 0xB0, /* 16 */
68 0x32, 0x06, 0x00, 0x00, /* 20 */
69 0x06, 0x30, 0xC0, 0xC0, /* 24 */
70 0x08, 0x06, 0x1F, 0xF7, /* 28 */
71 0xFD, 0xFF, 0x1F, 0xF7, /* 32 */
72 0xFD, 0xFF, 0x00, 0x38, /* 36 */
73 0x38, 0x38, 0x38, 0x38, /* 40 */
74 0x38, 0x00, 0x00, 0x00, /* 44 */
75 0x00, 0x00, 0x00, 0x00, /* 48 */
76 0x00, 0x00, 0x00, 0x00, /* 52 */
79 /* codec private data */
82 enum snd_soc_control_type control_type;
83 struct snd_pcm_hw_constraint_list *sysclk_constraints;
94 struct es8323_priv *es8323_private;
95 static int es8323_set_gpio(int gpio, bool level)
97 struct es8323_priv *es8323 = es8323_private;
100 printk("%s : es8323_priv is NULL\n", __func__);
104 DBG("%s : set %s %s ctl gpio %s\n", __func__,
105 gpio & ES8323_CODEC_SET_SPK ? "spk" : "",
106 gpio & ES8323_CODEC_SET_HP ? "hp" : "",
107 level ? "HIGH" : "LOW");
109 if ((gpio & ES8323_CODEC_SET_SPK) && es8323 && es8323->spk_ctl_gpio != INVALID_GPIO) {
110 gpio_set_value(es8323->spk_ctl_gpio, level);
113 if ((gpio & ES8323_CODEC_SET_HP) && es8323 && es8323->hp_ctl_gpio != INVALID_GPIO) {
114 gpio_set_value(es8323->hp_ctl_gpio, level);
120 static char mute_flag = 1;
121 static irqreturn_t hp_det_irq_handler(int irq, void *dev_id)
125 struct es8323_priv *es8323 = es8323_private;
127 disable_irq_nosync(irq);
129 type = gpio_get_value(es8323->hp_det_gpio) ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
130 ret = irq_set_irq_type(irq, type);
132 pr_err("%s: irq_set_irq_type(%d, %d) failed\n", __func__, irq, type);
136 if (type == IRQ_TYPE_EDGE_FALLING)
143 if(es8323->hp_det_level == gpio_get_value(es8323->hp_det_gpio)){
144 DBG("hp_det_level = 0,insert hp\n");
145 es8323_set_gpio(ES8323_CODEC_SET_SPK,!es8323->spk_gpio_level);
146 es8323_set_gpio(ES8323_CODEC_SET_HP,es8323->hp_gpio_level);
148 DBG("hp_det_level = 1,deinsert hp\n");
149 es8323_set_gpio(ES8323_CODEC_SET_SPK,es8323->spk_gpio_level);
150 es8323_set_gpio(ES8323_CODEC_SET_HP,!es8323->hp_gpio_level);
158 static unsigned int es8323_read_reg_cache(struct snd_soc_codec *codec,
161 //u16 *cache = codec->reg_cache;
162 if (reg >= ARRAY_SIZE(es8323_reg))
164 return es8323_reg[reg];
167 static int es8323_write(struct snd_soc_codec *codec, unsigned int reg,
170 //u16 *cache = codec->reg_cache;
174 BUG_ON(codec->volatile_register);
176 data[1] = value & 0x00ff;
178 if (reg < ARRAY_SIZE(es8323_reg))
179 es8323_reg[reg] = value;
180 ret = codec->hw_write(codec->control_data, data, 2);
189 //#define es8323_reset(c) snd_soc_write(c, es8323_RESET, 0)
190 static int es8323_reset(struct snd_soc_codec *codec)
192 snd_soc_write(codec, ES8323_CONTROL1, 0x80);
193 return snd_soc_write(codec, ES8323_CONTROL1, 0x00);
196 static const char *es8323_line_texts[] = {
197 "Line 1", "Line 2", "PGA"};
199 static const unsigned int es8323_line_values[] = {
201 static const char *es8323_pga_sel[] = {"Line 1", "Line 2", "Differential"};
202 static const char *stereo_3d_txt[] = {"No 3D ", "Level 1","Level 2","Level 3","Level 4","Level 5","Level 6","Level 7"};
203 static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
204 static const char *ng_type_txt[] = {"Constant PGA Gain","Mute ADC Output"};
205 static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
206 static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert","L + R Invert"};
207 static const char *es8323_mono_mux[] = {"Stereo", "Mono (Left)","Mono (Right)"};
208 static const char *es8323_diff_sel[] = {"Line 1", "Line 2"};
210 static const struct soc_enum es8323_enum[]={
211 SOC_VALUE_ENUM_SINGLE(ES8323_DACCONTROL16, 3, 7, ARRAY_SIZE(es8323_line_texts), es8323_line_texts, es8323_line_values),/* LLINE */
212 SOC_VALUE_ENUM_SINGLE(ES8323_DACCONTROL16, 0, 7, ARRAY_SIZE(es8323_line_texts), es8323_line_texts, es8323_line_values),/* rline */
213 SOC_VALUE_ENUM_SINGLE(ES8323_ADCCONTROL2, 6, 3, ARRAY_SIZE(es8323_pga_sel), es8323_line_texts, es8323_line_values),/* Left PGA Mux */
214 SOC_VALUE_ENUM_SINGLE(ES8323_ADCCONTROL2, 4, 3, ARRAY_SIZE(es8323_pga_sel), es8323_line_texts, es8323_line_values),/* Right PGA Mux */
215 SOC_ENUM_SINGLE(ES8323_DACCONTROL7, 2, 8, stereo_3d_txt),/* stereo-3d */
216 SOC_ENUM_SINGLE(ES8323_ADCCONTROL10, 6, 4, alc_func_txt),/*alc func*/
217 SOC_ENUM_SINGLE(ES8323_ADCCONTROL14, 1, 2, ng_type_txt),/*noise gate type*/
218 SOC_ENUM_SINGLE(ES8323_DACCONTROL6, 6, 4, deemph_txt),/*Playback De-emphasis*/
219 SOC_ENUM_SINGLE(ES8323_ADCCONTROL6, 6, 4, adcpol_txt),
220 SOC_ENUM_SINGLE(ES8323_ADCCONTROL3, 3, 3, es8323_mono_mux),
221 SOC_ENUM_SINGLE(ES8323_ADCCONTROL3, 7, 2, es8323_diff_sel),
225 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
226 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 50, 1);
227 static const DECLARE_TLV_DB_SCALE(dac_tlv, -9600, 50, 1);
228 static const DECLARE_TLV_DB_SCALE(out_tlv, -4500, 150, 0);
229 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
231 static const struct snd_kcontrol_new es8323_snd_controls[] = {
232 SOC_ENUM("3D Mode", es8323_enum[4]),
233 SOC_SINGLE("ALC Capture Target Volume", ES8323_ADCCONTROL11, 4, 15, 0),
234 SOC_SINGLE("ALC Capture Max PGA", ES8323_ADCCONTROL10, 3, 7, 0),
235 SOC_SINGLE("ALC Capture Min PGA", ES8323_ADCCONTROL10, 0, 7, 0),
236 SOC_ENUM("ALC Capture Function", es8323_enum[5]),
237 SOC_SINGLE("ALC Capture ZC Switch", ES8323_ADCCONTROL13, 6, 1, 0),
238 SOC_SINGLE("ALC Capture Hold Time", ES8323_ADCCONTROL11, 0, 15, 0),
239 SOC_SINGLE("ALC Capture Decay Time", ES8323_ADCCONTROL12, 4, 15, 0),
240 SOC_SINGLE("ALC Capture Attack Time", ES8323_ADCCONTROL12, 0, 15, 0),
241 SOC_SINGLE("ALC Capture NG Threshold", ES8323_ADCCONTROL14, 3, 31, 0),
242 SOC_ENUM("ALC Capture NG Type",es8323_enum[6]),
243 SOC_SINGLE("ALC Capture NG Switch", ES8323_ADCCONTROL14, 0, 1, 0),
244 SOC_SINGLE("ZC Timeout Switch", ES8323_ADCCONTROL13, 6, 1, 0),
245 SOC_DOUBLE_R_TLV("Capture Digital Volume", ES8323_ADCCONTROL8, ES8323_ADCCONTROL9,0, 255, 1, adc_tlv),
246 SOC_SINGLE("Capture Mute", ES8323_ADCCONTROL7, 2, 1, 0),
247 SOC_SINGLE_TLV("Left Channel Capture Volume", ES8323_ADCCONTROL1, 4, 15, 0, bypass_tlv),
248 SOC_SINGLE_TLV("Right Channel Capture Volume", ES8323_ADCCONTROL1, 0, 15, 0, bypass_tlv),
249 SOC_ENUM("Playback De-emphasis", es8323_enum[7]),
250 SOC_ENUM("Capture Polarity", es8323_enum[8]),
251 SOC_DOUBLE_R_TLV("PCM Volume", ES8323_DACCONTROL4, ES8323_DACCONTROL5, 0, 255, 1, dac_tlv),
252 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", ES8323_DACCONTROL17, 3, 7, 1, bypass_tlv),
253 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", ES8323_DACCONTROL20, 3, 7, 1, bypass_tlv),
254 SOC_DOUBLE_R_TLV("Output 1 Playback Volume", ES8323_DACCONTROL24, ES8323_DACCONTROL25, 0, 64, 0, out_tlv),
255 SOC_DOUBLE_R_TLV("Output 2 Playback Volume", ES8323_DACCONTROL26, ES8323_DACCONTROL27, 0, 64, 0, out_tlv),
259 static const struct snd_kcontrol_new es8323_left_line_controls =
260 SOC_DAPM_VALUE_ENUM("Route", es8323_enum[0]);
262 static const struct snd_kcontrol_new es8323_right_line_controls =
263 SOC_DAPM_VALUE_ENUM("Route", es8323_enum[1]);
266 static const struct snd_kcontrol_new es8323_left_pga_controls =
267 SOC_DAPM_VALUE_ENUM("Route", es8323_enum[2]);
269 static const struct snd_kcontrol_new es8323_right_pga_controls =
270 SOC_DAPM_VALUE_ENUM("Route", es8323_enum[3]);
273 static const struct snd_kcontrol_new es8323_left_mixer_controls[] = {
274 SOC_DAPM_SINGLE("Left Playback Switch", ES8323_DACCONTROL17, 7, 1, 0),
275 SOC_DAPM_SINGLE("Left Bypass Switch", ES8323_DACCONTROL17, 6, 1, 0),
279 static const struct snd_kcontrol_new es8323_right_mixer_controls[] = {
280 SOC_DAPM_SINGLE("Right Playback Switch", ES8323_DACCONTROL20, 7, 1, 0),
281 SOC_DAPM_SINGLE("Right Bypass Switch", ES8323_DACCONTROL20, 6, 1, 0),
284 /* Differential Mux */
285 //static const char *es8323_diff_sel[] = {"Line 1", "Line 2"};
286 static const struct snd_kcontrol_new es8323_diffmux_controls =
287 SOC_DAPM_ENUM("Route", es8323_enum[10]);
290 static const struct snd_kcontrol_new es8323_monomux_controls =
291 SOC_DAPM_ENUM("Route", es8323_enum[9]);
293 static const struct snd_soc_dapm_widget es8323_dapm_widgets[] = {
294 SND_SOC_DAPM_INPUT("LINPUT1"),
295 SND_SOC_DAPM_INPUT("LINPUT2"),
296 SND_SOC_DAPM_INPUT("RINPUT1"),
297 SND_SOC_DAPM_INPUT("RINPUT2"),
299 SND_SOC_DAPM_MICBIAS("Mic Bias", ES8323_ADCPOWER, 3, 1),
301 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
302 &es8323_diffmux_controls),
304 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
305 &es8323_monomux_controls),
306 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
307 &es8323_monomux_controls),
309 SND_SOC_DAPM_MUX("Left PGA Mux", ES8323_ADCPOWER, 7, 1,
310 &es8323_left_pga_controls),
311 SND_SOC_DAPM_MUX("Right PGA Mux", ES8323_ADCPOWER, 6, 1,
312 &es8323_right_pga_controls),
314 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
315 &es8323_left_line_controls),
316 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
317 &es8323_right_line_controls),
319 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8323_ADCPOWER, 4, 1),
320 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8323_ADCPOWER, 5, 1),
322 /* gModify.Cmmt Implement when suspend/startup */
323 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8323_DACPOWER, 7, 0),
324 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8323_DACPOWER, 8, 0),
326 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
327 &es8323_left_mixer_controls[0],
328 ARRAY_SIZE(es8323_left_mixer_controls)),
329 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
330 &es8323_right_mixer_controls[0],
331 ARRAY_SIZE(es8323_right_mixer_controls)),
333 SND_SOC_DAPM_PGA("Right Out 2", ES8323_DACPOWER, 2, 0, NULL, 0),
334 SND_SOC_DAPM_PGA("Left Out 2", ES8323_DACPOWER, 3, 0, NULL, 0),
335 SND_SOC_DAPM_PGA("Right Out 1", ES8323_DACPOWER, 4, 0, NULL, 0),
336 SND_SOC_DAPM_PGA("Left Out 1", ES8323_DACPOWER, 5, 0, NULL, 0),
337 SND_SOC_DAPM_PGA("LAMP", ES8323_ADCCONTROL1, 4, 0, NULL, 0),
338 SND_SOC_DAPM_PGA("RAMP", ES8323_ADCCONTROL1, 0, 0, NULL, 0),
340 SND_SOC_DAPM_OUTPUT("LOUT1"),
341 SND_SOC_DAPM_OUTPUT("ROUT1"),
342 SND_SOC_DAPM_OUTPUT("LOUT2"),
343 SND_SOC_DAPM_OUTPUT("ROUT2"),
344 SND_SOC_DAPM_OUTPUT("VREF"),
347 static const struct snd_soc_dapm_route audio_map[] = {
349 { "Left Line Mux", "NULL", "LINPUT1" },
350 { "Left Line Mux", "NULL", "LINPUT2" },
351 { "Left Line Mux", "NULL", "Left PGA Mux" },
353 { "Right Line Mux", "NULL", "RINPUT1" },
354 { "Right Line Mux", "NULL", "RINPUT2" },
355 { "Right Line Mux", "NULL", "Right PGA Mux" },
357 { "Left PGA Mux", "LAMP", "LINPUT1" },
358 { "Left PGA Mux", "LAMP", "LINPUT2" },
359 { "Left PGA Mux", "LAMP", "Differential Mux" },
361 { "Right PGA Mux", "RAMP", "RINPUT1" },
362 { "Right PGA Mux", "RAMP", "RINPUT2" },
363 { "Right PGA Mux", "RAMP", "Differential Mux" },
365 { "Differential Mux", "LAMP", "LINPUT1" },
366 { "Differential Mux", "RAMP", "RINPUT1" },
367 { "Differential Mux", "LAMP", "LINPUT2" },
368 { "Differential Mux", "RAMP", "RINPUT2" },
370 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
371 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
372 //{ "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
374 { "Right ADC Mux", "Stereo", "Right PGA Mux" },
375 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
376 //{ "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
378 { "Left ADC", NULL, "Left ADC Mux" },
379 { "Right ADC", NULL, "Right ADC Mux" },
381 { "Left Line Mux", "LAMP", "LINPUT1" },
382 { "Left Line Mux", "LAMP", "LINPUT2" },
383 { "Left Line Mux", "LAMP", "Left PGA Mux" },
385 { "Right Line Mux", "RAMP", "RINPUT1" },
386 { "Right Line Mux", "RAMP", "RINPUT2" },
387 { "Right Line Mux", "RAMP", "Right PGA Mux" },
389 { "Left Mixer", "Left Playback Switch", "Left DAC" },
390 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
392 { "Right Mixer", "Right Playback Switch", "Right DAC" },
393 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
395 { "Left Out 1", NULL, "Left Mixer" },
396 { "LOUT1", NULL, "Left Out 1" },
397 { "Right Out 1", NULL, "Right Mixer" },
398 { "ROUT1", NULL, "Right Out 1" },
400 { "Left Out 2", NULL, "Left Mixer" },
401 { "LOUT2", NULL, "Left Out 2" },
402 { "Right Out 2", NULL, "Right Mixer" },
403 { "ROUT2", NULL, "Right Out 2" },
415 /* codec hifi mclk clock divider coefficients */
416 static const struct _coeff_div coeff_div[] = {
418 {12288000, 8000, 1536, 0xa, 0x0},
419 {11289600, 8000, 1408, 0x9, 0x0},
420 {18432000, 8000, 2304, 0xc, 0x0},
421 {16934400, 8000, 2112, 0xb, 0x0},
422 {12000000, 8000, 1500, 0xb, 0x1},
425 {11289600, 11025, 1024, 0x7, 0x0},
426 {16934400, 11025, 1536, 0xa, 0x0},
427 {12000000, 11025, 1088, 0x9, 0x1},
430 {12288000, 16000, 768, 0x6, 0x0},
431 {18432000, 16000, 1152, 0x8, 0x0},
432 {12000000, 16000, 750, 0x7, 0x1},
435 {11289600, 22050, 512, 0x4, 0x0},
436 {16934400, 22050, 768, 0x6, 0x0},
437 {12000000, 22050, 544, 0x6, 0x1},
440 {12288000, 32000, 384, 0x3, 0x0},
441 {18432000, 32000, 576, 0x5, 0x0},
442 {12000000, 32000, 375, 0x4, 0x1},
445 {11289600, 44100, 256, 0x2, 0x0},
446 {16934400, 44100, 384, 0x3, 0x0},
447 {12000000, 44100, 272, 0x3, 0x1},
450 {12288000, 48000, 256, 0x2, 0x0},
451 {18432000, 48000, 384, 0x3, 0x0},
452 {12000000, 48000, 250, 0x2, 0x1},
455 {11289600, 88200, 128, 0x0, 0x0},
456 {16934400, 88200, 192, 0x1, 0x0},
457 {12000000, 88200, 136, 0x1, 0x1},
460 {12288000, 96000, 128, 0x0, 0x0},
461 {18432000, 96000, 192, 0x1, 0x0},
462 {12000000, 96000, 125, 0x0, 0x1},
465 static inline int get_coeff(int mclk, int rate)
469 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
470 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
477 /* The set of rates we can generate from the above for each SYSCLK */
479 static unsigned int rates_12288[] = {
480 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
483 static struct snd_pcm_hw_constraint_list constraints_12288 = {
484 .count = ARRAY_SIZE(rates_12288),
488 static unsigned int rates_112896[] = {
489 8000, 11025, 22050, 44100,
492 static struct snd_pcm_hw_constraint_list constraints_112896 = {
493 .count = ARRAY_SIZE(rates_112896),
494 .list = rates_112896,
497 static unsigned int rates_12[] = {
498 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000,
502 static struct snd_pcm_hw_constraint_list constraints_12 = {
503 .count = ARRAY_SIZE(rates_12),
508 * Note that this should be called from init rather than from hw_params.
510 static int es8323_set_dai_sysclk(struct snd_soc_dai *codec_dai,
511 int clk_id, unsigned int freq, int dir)
513 struct snd_soc_codec *codec = codec_dai->codec;
514 struct es8323_priv *es8323 = snd_soc_codec_get_drvdata(codec);
516 DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
523 es8323->sysclk_constraints = &constraints_112896;
524 es8323->sysclk = freq;
531 es8323->sysclk_constraints = &constraints_12288;
532 es8323->sysclk = freq;
537 es8323->sysclk_constraints = &constraints_12;
538 es8323->sysclk = freq;
544 static int es8323_set_dai_fmt(struct snd_soc_dai *codec_dai,
547 struct snd_soc_codec *codec = codec_dai->codec;
551 alsa_dbg("%s----%d, fmt[%02x]\n",__FUNCTION__,__LINE__,fmt);
553 iface = snd_soc_read(codec, ES8323_IFACE);
554 adciface = snd_soc_read(codec, ES8323_ADC_IFACE);
555 daciface = snd_soc_read(codec, ES8323_DAC_IFACE);
557 /* set master/slave audio interface */
558 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
559 case SND_SOC_DAIFMT_CBM_CFM: // MASTER MODE
560 alsa_dbg("es8323 in master mode");
563 case SND_SOC_DAIFMT_CBS_CFS: // SLAVE MODE
564 alsa_dbg("es8323 in slave mode");
572 /* interface format */
573 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
574 case SND_SOC_DAIFMT_I2S:
576 //daciface &= 0xF9; //updated by david-everest,5-25
579 case SND_SOC_DAIFMT_RIGHT_J:
581 case SND_SOC_DAIFMT_LEFT_J:
583 case SND_SOC_DAIFMT_DSP_A:
585 case SND_SOC_DAIFMT_DSP_B:
591 /* clock inversion */
592 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
593 case SND_SOC_DAIFMT_NB_NF:
596 //daciface &= 0xDF; //UPDATED BY david-everest,5-25
599 case SND_SOC_DAIFMT_IB_IF:
601 //adciface &= 0xDF; //UPDATED BY david-everest,5-25
603 //daciface &= 0xDF; //UPDATED BY david-everest,5-25
606 case SND_SOC_DAIFMT_IB_NF:
608 // adciface |= 0x40; //UPDATED BY david-everest,5-25
610 //daciface |= 0x40; //UPDATED BY david-everest,5-25
613 case SND_SOC_DAIFMT_NB_IF:
616 //daciface |= 0x20; //UPDATED BY david-everest,5-25
623 snd_soc_write(codec, ES8323_IFACE, iface);
624 snd_soc_write(codec, ES8323_ADC_IFACE, adciface);
625 snd_soc_write(codec, ES8323_DAC_IFACE, daciface);
630 static int es8323_pcm_startup(struct snd_pcm_substream *substream,
631 struct snd_soc_dai *dai)
633 struct snd_soc_codec *codec = dai->codec;
634 struct es8323_priv *es8323 = snd_soc_codec_get_drvdata(codec);
636 DBG("Enter::%s----%d es8323->sysclk=%d\n",__FUNCTION__,__LINE__,es8323->sysclk);
638 /* The set of sample rates that can be supported depends on the
639 * MCLK supplied to the CODEC - enforce this.
641 if (!es8323->sysclk) {
643 "No MCLK configured, call set_sysclk() on init\n");
647 snd_pcm_hw_constraint_list(substream->runtime, 0,
648 SNDRV_PCM_HW_PARAM_RATE,
649 es8323->sysclk_constraints);
654 static int es8323_pcm_hw_params(struct snd_pcm_substream *substream,
655 struct snd_pcm_hw_params *params,
656 struct snd_soc_dai *dai)
658 struct snd_soc_pcm_runtime *rtd = substream->private_data;
659 struct snd_soc_codec *codec = rtd->codec;
660 struct es8323_priv *es8323 = snd_soc_codec_get_drvdata(codec);
661 u16 srate = snd_soc_read(codec, ES8323_IFACE) & 0x80;
662 u16 adciface = snd_soc_read(codec, ES8323_ADC_IFACE) & 0xE3;
663 u16 daciface = snd_soc_read(codec, ES8323_DAC_IFACE) & 0xC7;
666 coeff = get_coeff(es8323->sysclk, params_rate(params));
668 coeff = get_coeff(es8323->sysclk / 2, params_rate(params));
673 "Unable to configure sample rate %dHz with %dHz MCLK\n",
674 params_rate(params), es8323->sysclk);
679 switch (params_format(params)) {
680 case SNDRV_PCM_FORMAT_S16_LE:
684 case SNDRV_PCM_FORMAT_S20_3LE:
688 case SNDRV_PCM_FORMAT_S24_LE:
690 case SNDRV_PCM_FORMAT_S32_LE:
696 /* set iface & srate*/
697 snd_soc_write(codec, ES8323_DAC_IFACE, daciface);
698 snd_soc_write(codec, ES8323_ADC_IFACE, adciface);
701 snd_soc_write(codec, ES8323_IFACE, srate);
702 snd_soc_write(codec, ES8323_ADCCONTROL5, coeff_div[coeff].sr | (coeff_div[coeff].usb) << 4);
703 snd_soc_write(codec, ES8323_DACCONTROL2, coeff_div[coeff].sr | (coeff_div[coeff].usb) << 4);
709 static int es8323_mute(struct snd_soc_dai *dai, int mute)
711 struct snd_soc_codec *codec = dai->codec;
712 struct es8323_priv *es8323 = es8323_private;
713 // u16 mute_reg = snd_soc_read(codec, ES8323_DACCONTROL3) & 0xfb;
715 DBG("Enter::%s----%d--hp_irq_flag=%d mute=%d\n",__FUNCTION__,__LINE__,hp_irq_flag,mute);
721 es8323_set_gpio(ES8323_CODEC_SET_SPK,!es8323->spk_gpio_level);
722 es8323_set_gpio(ES8323_CODEC_SET_HP,!es8323->hp_gpio_level);
724 snd_soc_write(codec, ES8323_DACCONTROL3, 0x06);
728 snd_soc_write(codec, ES8323_DACCONTROL3, 0x02);
729 snd_soc_write(codec, 0x30,es8323_DEF_VOL);
730 snd_soc_write(codec, 0x31,es8323_DEF_VOL);
735 es8323_set_gpio(ES8323_CODEC_SET_SPK,es8323->spk_gpio_level);
737 es8323_set_gpio(ES8323_CODEC_SET_HP,es8323->hp_gpio_level);
744 static int es8323_set_bias_level(struct snd_soc_codec *codec,
745 enum snd_soc_bias_level level)
748 case SND_SOC_BIAS_ON:
749 dev_dbg(codec->dev, "%s on\n", __func__);
751 case SND_SOC_BIAS_PREPARE:
752 dev_dbg(codec->dev, "%s prepare\n", __func__);
753 snd_soc_write(codec, ES8323_ANAVOLMANAG, 0x7C);
754 snd_soc_write(codec, ES8323_CHIPLOPOW1, 0x00);
755 snd_soc_write(codec, ES8323_CHIPLOPOW2, 0x00);
756 snd_soc_write(codec, ES8323_CHIPPOWER, 0x00);
757 snd_soc_write(codec, ES8323_ADCPOWER, 0x59);
759 case SND_SOC_BIAS_STANDBY:
760 dev_dbg(codec->dev, "%s standby\n", __func__);
761 snd_soc_write(codec, ES8323_ANAVOLMANAG, 0x7C);
762 snd_soc_write(codec, ES8323_CHIPLOPOW1, 0x00);
763 snd_soc_write(codec, ES8323_CHIPLOPOW2, 0x00);
764 snd_soc_write(codec, ES8323_CHIPPOWER, 0x00);
765 snd_soc_write(codec, ES8323_ADCPOWER, 0x59);
767 case SND_SOC_BIAS_OFF:
768 dev_dbg(codec->dev, "%s off\n", __func__);
769 snd_soc_write(codec, ES8323_ADCPOWER, 0xFF);
770 snd_soc_write(codec, ES8323_DACPOWER, 0xC0);
771 snd_soc_write(codec, ES8323_CHIPLOPOW1, 0xFF);
772 snd_soc_write(codec, ES8323_CHIPLOPOW2, 0xFF);
773 snd_soc_write(codec, ES8323_CHIPPOWER, 0xFF);
774 snd_soc_write(codec, ES8323_ANAVOLMANAG, 0x7B);
777 codec->dapm.bias_level = level;
783 #define es8323_RATES SNDRV_PCM_RATE_8000_96000
785 #define es8323_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
786 SNDRV_PCM_FMTBIT_S24_LE)
788 static struct snd_soc_dai_ops es8323_ops = {
789 .startup = es8323_pcm_startup,
790 .hw_params = es8323_pcm_hw_params,
791 .set_fmt = es8323_set_dai_fmt,
792 .set_sysclk = es8323_set_dai_sysclk,
793 .digital_mute = es8323_mute,
796 static struct snd_soc_dai_driver es8323_dai = {
797 .name = "ES8323 HiFi",
799 .stream_name = "Playback",
802 .rates = es8323_RATES,
803 .formats = es8323_FORMATS,
806 .stream_name = "Capture",
809 .rates = es8323_RATES,
810 .formats = es8323_FORMATS,
813 .symmetric_rates = 1,
816 static int es8323_suspend(struct snd_soc_codec *codec)
819 DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
820 snd_soc_write(codec, 0x19, 0x06);
821 snd_soc_write(codec, 0x30, 0x00);
822 snd_soc_write(codec, 0x31, 0x00);
823 snd_soc_write(codec, ES8323_ADCPOWER, 0xFF);
824 snd_soc_write(codec, ES8323_DACPOWER, 0xc0);
825 snd_soc_write(codec, ES8323_CHIPPOWER, 0xF3);
826 snd_soc_write(codec, 0x00, 0x00);
827 snd_soc_write(codec, 0x01, 0x58);
828 snd_soc_write(codec, 0x2b, 0x9c);
834 static int es8323_resume(struct snd_soc_codec *codec)
836 snd_soc_write(codec, 0x2b, 0x80);
837 snd_soc_write(codec, 0x01, 0x50);
838 snd_soc_write(codec, 0x00, 0x32);
839 snd_soc_write(codec, ES8323_CHIPPOWER, 0x00);
840 snd_soc_write(codec, ES8323_DACPOWER, 0x0c);
841 snd_soc_write(codec, ES8323_ADCPOWER, 0x59);
842 snd_soc_write(codec, 0x31, es8323_DEF_VOL);
843 snd_soc_write(codec, 0x30, es8323_DEF_VOL);
844 snd_soc_write(codec, 0x19, 0x02);
848 static struct snd_soc_codec *es8323_codec;
849 static int es8323_probe(struct snd_soc_codec *codec)
851 // struct es8323_priv *es8323 = snd_soc_codec_get_drvdata(codec);
854 printk("%s\n", __func__);
857 dev_err(codec->dev, "Codec device not registered\n");
861 codec->read = es8323_read_reg_cache;
862 codec->write = es8323_write;
863 codec->hw_write = (hw_write_t)i2c_master_send;
865 codec->control_data = container_of(codec->dev, struct i2c_client, dev);
867 es8323_codec = codec;
868 ret = es8323_reset(codec);
870 dev_err(codec->dev, "Failed to issue reset\n");
875 //snd_soc_write(codec, 0x35 , 0xa0);
876 //snd_soc_write(codec, 0x36 , 0x08); //for 1.8V VDD
877 //snd_soc_write(codec, 0x08,0x80); //ES8388 salve
879 snd_soc_write(codec, 0x02,0xf3);
880 snd_soc_write(codec, 0x2B,0x80);
881 snd_soc_write(codec, 0x08,0x00); //ES8388 salve
882 snd_soc_write(codec, 0x00,0x35); //
883 snd_soc_write(codec, 0x01,0x50); //PLAYBACK & RECORD Mode,EnRefr=1
884 snd_soc_write(codec, 0x03,0x59); //pdn_ana=0,ibiasgen_pdn=0
885 snd_soc_write(codec, 0x05,0x00); //pdn_ana=0,ibiasgen_pdn=0
886 snd_soc_write(codec, 0x06,0x00); //pdn_ana=0,ibiasgen_pdn=0
887 snd_soc_write(codec, 0x07,0x7c);
888 snd_soc_write(codec, 0x09,0x88); //ADC L/R PGA = +24dB
889 snd_soc_write(codec, 0x0a,0xf0); //ADC INPUT=LIN2/RIN2
890 snd_soc_write(codec, 0x0b,0x82); //ADC INPUT=LIN2/RIN2 //82
891 snd_soc_write(codec, 0x0C,0x4c); //I2S-24BIT
892 snd_soc_write(codec, 0x0d,0x02); //MCLK/LRCK=256
893 snd_soc_write(codec, 0x10,0x00); //ADC Left Volume=0db
894 snd_soc_write(codec, 0x11,0x00); //ADC Right Volume=0db
895 snd_soc_write(codec, 0x12,0xea); // ALC stereo MAXGAIN: 35.5dB, MINGAIN: +6dB (Record Volume increased!)
896 snd_soc_write(codec, 0x13,0xc0);
897 snd_soc_write(codec, 0x14,0x05);
898 snd_soc_write(codec, 0x15,0x06);
899 snd_soc_write(codec, 0x16,0x53);
900 snd_soc_write(codec, 0x17,0x18); //I2S-16BIT
901 snd_soc_write(codec, 0x18,0x02);
902 snd_soc_write(codec, 0x1A,0x0A); //DAC VOLUME=0DB
903 snd_soc_write(codec, 0x1B,0x0A);
905 snd_soc_write(codec, 0x1E,0x01); //for 47uF capacitors ,15db Bass@90Hz,Fs=44100
906 snd_soc_write(codec, 0x1F,0x84);
907 snd_soc_write(codec, 0x20,0xED);
908 snd_soc_write(codec, 0x21,0xAF);
909 snd_soc_write(codec, 0x22,0x20);
910 snd_soc_write(codec, 0x23,0x6C);
911 snd_soc_write(codec, 0x24,0xE9);
912 snd_soc_write(codec, 0x25,0xBE);
914 snd_soc_write(codec, 0x26,0x12); //Left DAC TO Left IXER
915 snd_soc_write(codec, 0x27,0xb8); //Left DAC TO Left MIXER
916 snd_soc_write(codec, 0x28,0x38);
917 snd_soc_write(codec, 0x29,0x38);
918 snd_soc_write(codec, 0x2A,0xb8);
919 snd_soc_write(codec, 0x02,0x00); //aa //START DLL and state-machine,START DSM
920 snd_soc_write(codec, 0x19,0x02); //SOFT RAMP RATE=32LRCKS/STEP,Enable ZERO-CROSS CHECK,DAC MUTE
921 snd_soc_write(codec, 0x04,0x0c); //pdn_ana=0,ibiasgen_pdn=0
923 snd_soc_write(codec, 0x2e,0x00);
924 snd_soc_write(codec, 0x2f,0x00);
925 snd_soc_write(codec, 0x30,0x08);
926 snd_soc_write(codec, 0x31,0x08);
928 snd_soc_write(codec, 0x30,0x0f);
929 snd_soc_write(codec, 0x31,0x0f);
931 snd_soc_write(codec, 0x30,0x18);
932 snd_soc_write(codec, 0x31,0x18);
934 snd_soc_write(codec, 0x04,0x2c); //pdn_ana=0,ibiasgen_pdn=0
936 snd_soc_write(codec, ES8323_DACCONTROL3, 0x06);
939 es8323_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
943 static int es8323_remove(struct snd_soc_codec *codec)
945 es8323_set_bias_level(codec, SND_SOC_BIAS_OFF);
949 static struct snd_soc_codec_driver soc_codec_dev_es8323 = {
950 .probe = es8323_probe,
951 .remove = es8323_remove,
952 .suspend = es8323_suspend,
953 .resume = es8323_resume,
954 .set_bias_level = es8323_set_bias_level,
955 .reg_cache_size = ARRAY_SIZE(es8323_reg),
956 .reg_word_size = sizeof(u16),
957 .reg_cache_default = es8323_reg,
958 //------------------------------------------
959 //.volatile_register = es8323_volatile_register,
960 //.readable_register = es8323_readable_register,
963 .controls = es8323_snd_controls,
964 .num_controls = ARRAY_SIZE(es8323_snd_controls),
965 .dapm_routes = audio_map,
966 .num_dapm_routes = ARRAY_SIZE(audio_map),
967 .dapm_widgets = es8323_dapm_widgets,
968 .num_dapm_widgets = ARRAY_SIZE(es8323_dapm_widgets),
970 //--------------------------------------------------
971 .read = es8323_read_reg_cache,
972 .write = es8323_write,
979 compatible = "es8323";
981 spk-con-gpio = <&gpio2 GPIO_D7 GPIO_ACTIVE_HIGH>;
982 hp-con-gpio = <&gpio2 GPIO_D7 GPIO_ACTIVE_HIGH>;
983 hp-det-gpio = <&gpio0 GPIO_B5 GPIO_ACTIVE_HIGH>;
987 static int es8323_i2c_probe(struct i2c_client *i2c,
988 const struct i2c_device_id *id)
990 struct es8323_priv *es8323;
992 unsigned long irq_flag=0;
994 enum of_gpio_flags flags;
995 struct i2c_adapter *adapter = to_i2c_adapter(i2c->dev.parent);
998 if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) {
999 dev_warn(&adapter->dev,
1000 "I2C-Adapter doesn't support I2C_FUNC_I2C\n");
1004 es8323 = devm_kzalloc(&i2c->dev,sizeof(struct es8323_priv), GFP_KERNEL);
1008 i2c_set_clientdata(i2c, es8323);
1009 es8323->control_type = SND_SOC_I2C;
1011 reg = ES8323_DACCONTROL18;
1012 ret = i2c_master_recv(i2c, ®, 1);
1014 printk("es8323 probe error\n");
1018 es8323_private = es8323;
1019 es8323->spk_ctl_gpio = of_get_named_gpio_flags(i2c->dev.of_node, "spk-con-gpio", 0, &flags);
1020 if (es8323->spk_ctl_gpio < 0) {
1021 DBG("%s() Can not read property spk codec-en-gpio\n", __FUNCTION__);
1022 es8323->spk_ctl_gpio = INVALID_GPIO;
1026 es8323->spk_gpio_level = (flags & OF_GPIO_ACTIVE_LOW)? 0:1;
1027 ret = gpio_request(es8323->spk_ctl_gpio, NULL);
1029 printk("%s request SPK_CON error", __func__);
1032 gpio_direction_output(es8323->spk_ctl_gpio,!es8323->spk_gpio_level);
1035 es8323->hp_ctl_gpio = of_get_named_gpio_flags(i2c->dev.of_node, "hp-con-gpio", 0, &flags);
1036 if (es8323->hp_ctl_gpio < 0) {
1037 DBG("%s() Can not read property hp codec-en-gpio\n", __FUNCTION__);
1038 es8323->hp_ctl_gpio = INVALID_GPIO;
1042 es8323->hp_gpio_level = (flags & OF_GPIO_ACTIVE_LOW)? 0:1;
1043 ret = gpio_request(es8323->hp_ctl_gpio, NULL);
1045 printk("%s request hp_ctl error", __func__);
1048 gpio_direction_output(es8323->hp_ctl_gpio,!es8323->hp_gpio_level);
1051 es8323->hp_det_gpio = of_get_named_gpio_flags(i2c->dev.of_node, "hp-det-gpio", 0, &flags);
1052 if (es8323->hp_det_gpio < 0) {
1053 DBG("%s() Can not read property hp_det gpio\n", __FUNCTION__);
1054 es8323->hp_det_gpio = INVALID_GPIO;
1058 es8323->hp_det_level = (flags & OF_GPIO_ACTIVE_LOW)? 0:1;
1059 ret = gpio_request(es8323->hp_det_gpio, NULL);
1061 printk("%s request HP_DET error", __func__);
1064 gpio_direction_input(es8323->hp_det_gpio);
1066 irq_flag = IRQF_TRIGGER_LOW |IRQF_ONESHOT;
1067 hp_irq = gpio_to_irq(es8323->hp_det_gpio);
1070 ret = request_threaded_irq(hp_irq, NULL, hp_det_irq_handler, irq_flag, "ES8323", NULL);
1072 printk("%s:register ISR (irq=%d)\n", __FUNCTION__,hp_irq);
1075 printk("request_irq hp_irq failed\n");
1079 ret = snd_soc_register_codec(&i2c->dev,
1080 &soc_codec_dev_es8323, &es8323_dai, 1);
1085 printk("es8323 probe i2c recv ok\n");
1087 #ifdef CONFIG_MACH_RK_FAC
1093 static int es8323_i2c_remove(struct i2c_client *client)
1095 snd_soc_unregister_codec(&client->dev);
1096 kfree(i2c_get_clientdata(client));
1100 static const struct i2c_device_id es8323_i2c_id[] = {
1104 MODULE_DEVICE_TABLE(i2c, es8323_i2c_id);
1106 void es8323_i2c_shutdown(struct i2c_client *client)
1108 struct es8323_priv *es8323 = es8323_private;
1110 es8323_set_gpio(ES8323_CODEC_SET_SPK,!es8323->spk_gpio_level);
1111 es8323_set_gpio(ES8323_CODEC_SET_HP,!es8323->hp_gpio_level);
1113 snd_soc_write(es8323_codec, ES8323_CONTROL2, 0x58);
1114 snd_soc_write(es8323_codec, ES8323_CONTROL1, 0x32);
1115 snd_soc_write(es8323_codec, ES8323_CHIPPOWER, 0xf3);
1116 snd_soc_write(es8323_codec, ES8323_DACPOWER, 0xc0);
1118 snd_soc_write(es8323_codec, ES8323_DACCONTROL26, 0x00);
1119 snd_soc_write(es8323_codec, ES8323_DACCONTROL27, 0x00);
1121 snd_soc_write(es8323_codec, ES8323_CONTROL1, 0x30);
1122 snd_soc_write(es8323_codec, ES8323_CONTROL1, 0x34);
1128 static struct i2c_driver es8323_i2c_driver = {
1131 .owner = THIS_MODULE,
1133 .shutdown = es8323_i2c_shutdown,
1134 .probe = es8323_i2c_probe,
1135 .remove = es8323_i2c_remove,
1136 .id_table = es8323_i2c_id,
1139 static int __init es8323_init(void)
1141 return i2c_add_driver(&es8323_i2c_driver);
1144 static void __exit es8323_exit(void)
1146 i2c_del_driver(&es8323_i2c_driver);
1149 module_init(es8323_init);
1150 module_exit(es8323_exit);
1153 MODULE_DESCRIPTION("ASoC es8323 driver");
1154 MODULE_AUTHOR("Mark Brown <will@everset-semi.com>");
1155 MODULE_LICENSE("GPL");