2 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
3 * Copyright 2009 Sascha Hauer, s.hauer@pengutronix.de
4 * Copyright 2012 Philippe Retornaz, philippe.retornaz@epfl.ch
6 * Initial development of this code was funded by
7 * Phytec Messtechnik GmbH, http://www.phytec.de
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #include <linux/module.h>
24 #include <linux/device.h>
25 #include <linux/mfd/mc13xxx.h>
26 #include <linux/slab.h>
27 #include <sound/core.h>
28 #include <sound/control.h>
29 #include <sound/pcm.h>
30 #include <sound/soc.h>
31 #include <sound/initval.h>
32 #include <sound/soc-dapm.h>
36 #define MC13783_AUDIO_RX0 36
37 #define MC13783_AUDIO_RX1 37
38 #define MC13783_AUDIO_TX 38
39 #define MC13783_SSI_NETWORK 39
40 #define MC13783_AUDIO_CODEC 40
41 #define MC13783_AUDIO_DAC 41
43 #define AUDIO_RX0_ALSPEN (1 << 5)
44 #define AUDIO_RX0_ALSPSEL (1 << 7)
45 #define AUDIO_RX0_ADDCDC (1 << 21)
46 #define AUDIO_RX0_ADDSTDC (1 << 22)
47 #define AUDIO_RX0_ADDRXIN (1 << 23)
49 #define AUDIO_RX1_PGARXEN (1 << 0);
50 #define AUDIO_RX1_PGASTEN (1 << 5)
51 #define AUDIO_RX1_ARXINEN (1 << 10)
53 #define AUDIO_TX_AMC1REN (1 << 5)
54 #define AUDIO_TX_AMC1LEN (1 << 7)
55 #define AUDIO_TX_AMC2EN (1 << 9)
56 #define AUDIO_TX_ATXINEN (1 << 11)
57 #define AUDIO_TX_RXINREC (1 << 13)
59 #define SSI_NETWORK_CDCTXRXSLOT(x) (((x) & 0x3) << 2)
60 #define SSI_NETWORK_CDCTXSECSLOT(x) (((x) & 0x3) << 4)
61 #define SSI_NETWORK_CDCRXSECSLOT(x) (((x) & 0x3) << 6)
62 #define SSI_NETWORK_CDCRXSECGAIN(x) (((x) & 0x3) << 8)
63 #define SSI_NETWORK_CDCSUMGAIN(x) (1 << 10)
64 #define SSI_NETWORK_CDCFSDLY(x) (1 << 11)
65 #define SSI_NETWORK_DAC_SLOTS_8 (1 << 12)
66 #define SSI_NETWORK_DAC_SLOTS_4 (2 << 12)
67 #define SSI_NETWORK_DAC_SLOTS_2 (3 << 12)
68 #define SSI_NETWORK_DAC_SLOT_MASK (3 << 12)
69 #define SSI_NETWORK_DAC_RXSLOT_0_1 (0 << 14)
70 #define SSI_NETWORK_DAC_RXSLOT_2_3 (1 << 14)
71 #define SSI_NETWORK_DAC_RXSLOT_4_5 (2 << 14)
72 #define SSI_NETWORK_DAC_RXSLOT_6_7 (3 << 14)
73 #define SSI_NETWORK_DAC_RXSLOT_MASK (3 << 14)
74 #define SSI_NETWORK_STDCRXSECSLOT(x) (((x) & 0x3) << 16)
75 #define SSI_NETWORK_STDCRXSECGAIN(x) (((x) & 0x3) << 18)
76 #define SSI_NETWORK_STDCSUMGAIN (1 << 20)
79 * MC13783_AUDIO_CODEC and MC13783_AUDIO_DAC mostly share the same
82 #define AUDIO_SSI_SEL (1 << 0)
83 #define AUDIO_CLK_SEL (1 << 1)
84 #define AUDIO_CSM (1 << 2)
85 #define AUDIO_BCL_INV (1 << 3)
86 #define AUDIO_CFS_INV (1 << 4)
87 #define AUDIO_CFS(x) (((x) & 0x3) << 5)
88 #define AUDIO_CLK(x) (((x) & 0x7) << 7)
89 #define AUDIO_C_EN (1 << 11)
90 #define AUDIO_C_CLK_EN (1 << 12)
91 #define AUDIO_C_RESET (1 << 15)
93 #define AUDIO_CODEC_CDCFS8K16K (1 << 10)
94 #define AUDIO_DAC_CFS_DLY_B (1 << 10)
97 struct mc13xxx *mc13xxx;
99 enum mc13783_ssi_port adc_ssi_port;
100 enum mc13783_ssi_port dac_ssi_port;
103 static unsigned int mc13783_read(struct snd_soc_codec *codec,
106 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
107 unsigned int value = 0;
109 mc13xxx_lock(priv->mc13xxx);
111 mc13xxx_reg_read(priv->mc13xxx, reg, &value);
113 mc13xxx_unlock(priv->mc13xxx);
118 static int mc13783_write(struct snd_soc_codec *codec,
119 unsigned int reg, unsigned int value)
121 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
124 mc13xxx_lock(priv->mc13xxx);
126 ret = mc13xxx_reg_write(priv->mc13xxx, reg, value);
128 mc13xxx_unlock(priv->mc13xxx);
133 /* Mapping between sample rates and register value */
134 static unsigned int mc13783_rates[] = {
135 8000, 11025, 12000, 16000,
136 22050, 24000, 32000, 44100,
140 static int mc13783_pcm_hw_params_dac(struct snd_pcm_substream *substream,
141 struct snd_pcm_hw_params *params,
142 struct snd_soc_dai *dai)
144 struct snd_soc_pcm_runtime *rtd = substream->private_data;
145 struct snd_soc_codec *codec = rtd->codec;
146 unsigned int rate = params_rate(params);
149 for (i = 0; i < ARRAY_SIZE(mc13783_rates); i++) {
150 if (rate == mc13783_rates[i]) {
151 snd_soc_update_bits(codec, MC13783_AUDIO_DAC,
160 static int mc13783_pcm_hw_params_codec(struct snd_pcm_substream *substream,
161 struct snd_pcm_hw_params *params,
162 struct snd_soc_dai *dai)
164 struct snd_soc_pcm_runtime *rtd = substream->private_data;
165 struct snd_soc_codec *codec = rtd->codec;
166 unsigned int rate = params_rate(params);
174 val = AUDIO_CODEC_CDCFS8K16K;
180 snd_soc_update_bits(codec, MC13783_AUDIO_CODEC, AUDIO_CODEC_CDCFS8K16K,
186 static int mc13783_pcm_hw_params_sync(struct snd_pcm_substream *substream,
187 struct snd_pcm_hw_params *params,
188 struct snd_soc_dai *dai)
190 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
191 return mc13783_pcm_hw_params_dac(substream, params, dai);
193 return mc13783_pcm_hw_params_codec(substream, params, dai);
196 static int mc13783_set_fmt(struct snd_soc_dai *dai, unsigned int fmt,
199 struct snd_soc_codec *codec = dai->codec;
200 unsigned int val = 0;
201 unsigned int mask = AUDIO_CFS(3) | AUDIO_BCL_INV | AUDIO_CFS_INV |
202 AUDIO_CSM | AUDIO_C_CLK_EN | AUDIO_C_RESET;
206 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
207 case SND_SOC_DAIFMT_I2S:
210 case SND_SOC_DAIFMT_DSP_A:
217 /* DAI clock inversion */
218 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
219 case SND_SOC_DAIFMT_NB_NF:
220 val |= AUDIO_BCL_INV;
222 case SND_SOC_DAIFMT_NB_IF:
223 val |= AUDIO_BCL_INV | AUDIO_CFS_INV;
225 case SND_SOC_DAIFMT_IB_NF:
227 case SND_SOC_DAIFMT_IB_IF:
228 val |= AUDIO_CFS_INV;
232 /* DAI clock master masks */
233 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
234 case SND_SOC_DAIFMT_CBM_CFM:
235 val |= AUDIO_C_CLK_EN;
237 case SND_SOC_DAIFMT_CBS_CFS:
240 case SND_SOC_DAIFMT_CBM_CFS:
241 case SND_SOC_DAIFMT_CBS_CFM:
245 val |= AUDIO_C_RESET;
247 snd_soc_update_bits(codec, reg, mask, val);
252 static int mc13783_set_fmt_async(struct snd_soc_dai *dai, unsigned int fmt)
254 if (dai->id == MC13783_ID_STEREO_DAC)
255 return mc13783_set_fmt(dai, fmt, MC13783_AUDIO_DAC);
257 return mc13783_set_fmt(dai, fmt, MC13783_AUDIO_CODEC);
260 static int mc13783_set_fmt_sync(struct snd_soc_dai *dai, unsigned int fmt)
264 ret = mc13783_set_fmt(dai, fmt, MC13783_AUDIO_DAC);
269 * In synchronous mode force the voice codec into slave mode
270 * so that the clock / framesync from the stereo DAC is used
272 fmt &= ~SND_SOC_DAIFMT_MASTER_MASK;
273 fmt |= SND_SOC_DAIFMT_CBS_CFS;
274 ret = mc13783_set_fmt(dai, fmt, MC13783_AUDIO_CODEC);
279 static int mc13783_sysclk[] = {
285 -1, /* 12000000, invalid for voice codec */
286 -1, /* 3686400, invalid for voice codec */
290 static int mc13783_set_sysclk(struct snd_soc_dai *dai,
291 int clk_id, unsigned int freq, int dir,
294 struct snd_soc_codec *codec = dai->codec;
296 unsigned int val = 0;
297 unsigned int mask = AUDIO_CLK(0x7) | AUDIO_CLK_SEL;
299 for (clk = 0; clk < ARRAY_SIZE(mc13783_sysclk); clk++) {
300 if (mc13783_sysclk[clk] < 0)
302 if (mc13783_sysclk[clk] == freq)
306 if (clk == ARRAY_SIZE(mc13783_sysclk))
309 if (clk_id == MC13783_CLK_CLIB)
310 val |= AUDIO_CLK_SEL;
312 val |= AUDIO_CLK(clk);
314 snd_soc_update_bits(codec, reg, mask, val);
319 static int mc13783_set_sysclk_dac(struct snd_soc_dai *dai,
320 int clk_id, unsigned int freq, int dir)
322 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC);
325 static int mc13783_set_sysclk_codec(struct snd_soc_dai *dai,
326 int clk_id, unsigned int freq, int dir)
328 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC);
331 static int mc13783_set_sysclk_sync(struct snd_soc_dai *dai,
332 int clk_id, unsigned int freq, int dir)
336 ret = mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_DAC);
340 return mc13783_set_sysclk(dai, clk_id, freq, dir, MC13783_AUDIO_CODEC);
343 static int mc13783_set_tdm_slot_dac(struct snd_soc_dai *dai,
344 unsigned int tx_mask, unsigned int rx_mask, int slots,
347 struct snd_soc_codec *codec = dai->codec;
348 unsigned int val = 0;
349 unsigned int mask = SSI_NETWORK_DAC_SLOT_MASK |
350 SSI_NETWORK_DAC_RXSLOT_MASK;
354 val |= SSI_NETWORK_DAC_SLOTS_2;
357 val |= SSI_NETWORK_DAC_SLOTS_4;
360 val |= SSI_NETWORK_DAC_SLOTS_8;
368 val |= SSI_NETWORK_DAC_RXSLOT_0_1;
371 val |= SSI_NETWORK_DAC_RXSLOT_2_3;
374 val |= SSI_NETWORK_DAC_RXSLOT_4_5;
377 val |= SSI_NETWORK_DAC_RXSLOT_6_7;
383 snd_soc_update_bits(codec, MC13783_SSI_NETWORK, mask, val);
388 static int mc13783_set_tdm_slot_codec(struct snd_soc_dai *dai,
389 unsigned int tx_mask, unsigned int rx_mask, int slots,
392 struct snd_soc_codec *codec = dai->codec;
393 unsigned int val = 0;
394 unsigned int mask = 0x3f;
399 if (tx_mask != 0xfffffffc)
402 val |= (0x00 << 2); /* primary timeslot RX/TX(?) is 0 */
403 val |= (0x01 << 4); /* secondary timeslot TX is 1 */
405 snd_soc_update_bits(codec, MC13783_SSI_NETWORK, mask, val);
410 static int mc13783_set_tdm_slot_sync(struct snd_soc_dai *dai,
411 unsigned int tx_mask, unsigned int rx_mask, int slots,
416 ret = mc13783_set_tdm_slot_dac(dai, tx_mask, rx_mask, slots,
421 ret = mc13783_set_tdm_slot_codec(dai, tx_mask, rx_mask, slots,
427 static const struct snd_kcontrol_new mc1l_amp_ctl =
428 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_TX, 7, 1, 0);
430 static const struct snd_kcontrol_new mc1r_amp_ctl =
431 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_TX, 5, 1, 0);
433 static const struct snd_kcontrol_new mc2_amp_ctl =
434 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_TX, 9, 1, 0);
436 static const struct snd_kcontrol_new atx_amp_ctl =
437 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_TX, 11, 1, 0);
440 /* Virtual mux. The chip does the input selection automatically
441 * as soon as we enable one input. */
442 static const char * const adcl_enum_text[] = {
446 static const struct soc_enum adcl_enum =
447 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(adcl_enum_text), adcl_enum_text);
449 static const struct snd_kcontrol_new left_input_mux =
450 SOC_DAPM_ENUM_VIRT("Route", adcl_enum);
452 static const char * const adcr_enum_text[] = {
453 "MC1R", "MC2", "RXINR", "TXIN",
456 static const struct soc_enum adcr_enum =
457 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(adcr_enum_text), adcr_enum_text);
459 static const struct snd_kcontrol_new right_input_mux =
460 SOC_DAPM_ENUM_VIRT("Route", adcr_enum);
462 static const struct snd_kcontrol_new samp_ctl =
463 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 3, 1, 0);
465 static const struct snd_kcontrol_new lamp_ctl =
466 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 5, 1, 0);
468 static const struct snd_kcontrol_new hlamp_ctl =
469 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 10, 1, 0);
471 static const struct snd_kcontrol_new hramp_ctl =
472 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 9, 1, 0);
474 static const struct snd_kcontrol_new llamp_ctl =
475 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 16, 1, 0);
477 static const struct snd_kcontrol_new lramp_ctl =
478 SOC_DAPM_SINGLE("Switch", MC13783_AUDIO_RX0, 15, 1, 0);
480 static const struct snd_soc_dapm_widget mc13783_dapm_widgets[] = {
482 SND_SOC_DAPM_INPUT("MC1LIN"),
483 SND_SOC_DAPM_INPUT("MC1RIN"),
484 SND_SOC_DAPM_INPUT("MC2IN"),
485 SND_SOC_DAPM_INPUT("RXINR"),
486 SND_SOC_DAPM_INPUT("RXINL"),
487 SND_SOC_DAPM_INPUT("TXIN"),
489 SND_SOC_DAPM_SUPPLY("MC1 Bias", MC13783_AUDIO_TX, 0, 0, NULL, 0),
490 SND_SOC_DAPM_SUPPLY("MC2 Bias", MC13783_AUDIO_TX, 1, 0, NULL, 0),
492 SND_SOC_DAPM_SWITCH("MC1L Amp", MC13783_AUDIO_TX, 7, 0, &mc1l_amp_ctl),
493 SND_SOC_DAPM_SWITCH("MC1R Amp", MC13783_AUDIO_TX, 5, 0, &mc1r_amp_ctl),
494 SND_SOC_DAPM_SWITCH("MC2 Amp", MC13783_AUDIO_TX, 9, 0, &mc2_amp_ctl),
495 SND_SOC_DAPM_SWITCH("TXIN Amp", MC13783_AUDIO_TX, 11, 0, &atx_amp_ctl),
497 SND_SOC_DAPM_VIRT_MUX("PGA Left Input Mux", SND_SOC_NOPM, 0, 0,
499 SND_SOC_DAPM_VIRT_MUX("PGA Right Input Mux", SND_SOC_NOPM, 0, 0,
502 SND_SOC_DAPM_PGA("PGA Left Input", SND_SOC_NOPM, 0, 0, NULL, 0),
503 SND_SOC_DAPM_PGA("PGA Right Input", SND_SOC_NOPM, 0, 0, NULL, 0),
505 SND_SOC_DAPM_ADC("ADC", "Capture", MC13783_AUDIO_CODEC, 11, 0),
506 SND_SOC_DAPM_SUPPLY("ADC_Reset", MC13783_AUDIO_CODEC, 15, 0, NULL, 0),
509 SND_SOC_DAPM_SUPPLY("DAC_E", MC13783_AUDIO_DAC, 11, 0, NULL, 0),
510 SND_SOC_DAPM_SUPPLY("DAC_Reset", MC13783_AUDIO_DAC, 15, 0, NULL, 0),
511 SND_SOC_DAPM_OUTPUT("RXOUTL"),
512 SND_SOC_DAPM_OUTPUT("RXOUTR"),
513 SND_SOC_DAPM_OUTPUT("HSL"),
514 SND_SOC_DAPM_OUTPUT("HSR"),
515 SND_SOC_DAPM_OUTPUT("LSP"),
516 SND_SOC_DAPM_OUTPUT("SP"),
518 SND_SOC_DAPM_SWITCH("Speaker Amp", MC13783_AUDIO_RX0, 3, 0, &samp_ctl),
519 SND_SOC_DAPM_SWITCH("Loudspeaker Amp", SND_SOC_NOPM, 0, 0, &lamp_ctl),
520 SND_SOC_DAPM_SWITCH("Headset Amp Left", MC13783_AUDIO_RX0, 10, 0,
522 SND_SOC_DAPM_SWITCH("Headset Amp Right", MC13783_AUDIO_RX0, 9, 0,
524 SND_SOC_DAPM_SWITCH("Line out Amp Left", MC13783_AUDIO_RX0, 16, 0,
526 SND_SOC_DAPM_SWITCH("Line out Amp Right", MC13783_AUDIO_RX0, 15, 0,
528 SND_SOC_DAPM_DAC("DAC", "Playback", MC13783_AUDIO_RX0, 22, 0),
529 SND_SOC_DAPM_PGA("DAC PGA", MC13783_AUDIO_RX1, 5, 0, NULL, 0),
532 static struct snd_soc_dapm_route mc13783_routes[] = {
534 { "MC1L Amp", NULL, "MC1LIN"},
535 { "MC1R Amp", NULL, "MC1RIN" },
536 { "MC2 Amp", NULL, "MC2IN" },
537 { "TXIN Amp", NULL, "TXIN"},
539 { "PGA Left Input Mux", "MC1L", "MC1L Amp" },
540 { "PGA Left Input Mux", "RXINL", "RXINL"},
541 { "PGA Right Input Mux", "MC1R", "MC1R Amp" },
542 { "PGA Right Input Mux", "MC2", "MC2 Amp"},
543 { "PGA Right Input Mux", "TXIN", "TXIN Amp"},
544 { "PGA Right Input Mux", "RXINR", "RXINR"},
546 { "PGA Left Input", NULL, "PGA Left Input Mux"},
547 { "PGA Right Input", NULL, "PGA Right Input Mux"},
549 { "ADC", NULL, "PGA Left Input"},
550 { "ADC", NULL, "PGA Right Input"},
551 { "ADC", NULL, "ADC_Reset"},
554 { "HSL", NULL, "Headset Amp Left" },
555 { "HSR", NULL, "Headset Amp Right"},
556 { "RXOUTL", NULL, "Line out Amp Left"},
557 { "RXOUTR", NULL, "Line out Amp Right"},
558 { "SP", NULL, "Speaker Amp"},
559 { "Speaker Amp", NULL, "DAC PGA"},
560 { "LSP", NULL, "DAC PGA"},
561 { "Headset Amp Left", NULL, "DAC PGA"},
562 { "Headset Amp Right", NULL, "DAC PGA"},
563 { "Line out Amp Left", NULL, "DAC PGA"},
564 { "Line out Amp Right", NULL, "DAC PGA"},
565 { "DAC PGA", NULL, "DAC"},
566 { "DAC", NULL, "DAC_E"},
569 static const char * const mc13783_3d_mixer[] = {"Stereo", "Phase Mix",
572 static const struct soc_enum mc13783_enum_3d_mixer =
573 SOC_ENUM_SINGLE(MC13783_AUDIO_RX1, 16, ARRAY_SIZE(mc13783_3d_mixer),
576 static struct snd_kcontrol_new mc13783_control_list[] = {
577 SOC_SINGLE("Loudspeaker enable", MC13783_AUDIO_RX0, 5, 1, 0),
578 SOC_SINGLE("PCM Playback Volume", MC13783_AUDIO_RX1, 6, 15, 0),
579 SOC_DOUBLE("PCM Capture Volume", MC13783_AUDIO_TX, 19, 14, 31, 0),
580 SOC_ENUM("3D Control", mc13783_enum_3d_mixer),
583 static int mc13783_probe(struct snd_soc_codec *codec)
585 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
587 mc13xxx_lock(priv->mc13xxx);
589 /* these are the reset values */
590 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);
591 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A);
592 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_TX, 0x420000);
593 mc13xxx_reg_write(priv->mc13xxx, MC13783_SSI_NETWORK, 0x013060);
594 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_CODEC, 0x180027);
595 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_DAC, 0x0e0004);
597 if (priv->adc_ssi_port == MC13783_SSI1_PORT)
598 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_CODEC,
601 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_CODEC,
604 if (priv->dac_ssi_port == MC13783_SSI1_PORT)
605 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_DAC,
608 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_DAC,
611 mc13xxx_unlock(priv->mc13xxx);
616 static int mc13783_remove(struct snd_soc_codec *codec)
618 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
620 mc13xxx_lock(priv->mc13xxx);
622 /* Make sure VAUDIOON is off */
623 mc13xxx_reg_rmw(priv->mc13xxx, MC13783_AUDIO_RX0, 0x3, 0);
625 mc13xxx_unlock(priv->mc13xxx);
630 #define MC13783_RATES_RECORD (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000)
632 #define MC13783_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
633 SNDRV_PCM_FMTBIT_S24_LE)
635 static struct snd_soc_dai_ops mc13783_ops_dac = {
636 .hw_params = mc13783_pcm_hw_params_dac,
637 .set_fmt = mc13783_set_fmt_async,
638 .set_sysclk = mc13783_set_sysclk_dac,
639 .set_tdm_slot = mc13783_set_tdm_slot_dac,
642 static struct snd_soc_dai_ops mc13783_ops_codec = {
643 .hw_params = mc13783_pcm_hw_params_codec,
644 .set_fmt = mc13783_set_fmt_async,
645 .set_sysclk = mc13783_set_sysclk_codec,
646 .set_tdm_slot = mc13783_set_tdm_slot_codec,
650 * The mc13783 has two SSI ports, both of them can be routed either
651 * to the voice codec or the stereo DAC. When two different SSI ports
652 * are used for the voice codec and the stereo DAC we can do different
653 * formats and sysclock settings for playback and capture
654 * (mc13783-hifi-playback and mc13783-hifi-capture). Using the same port
655 * forces us to use symmetric rates (mc13783-hifi).
657 static struct snd_soc_dai_driver mc13783_dai_async[] = {
659 .name = "mc13783-hifi-playback",
660 .id = MC13783_ID_STEREO_DAC,
662 .stream_name = "Playback",
665 .rates = SNDRV_PCM_RATE_8000_96000,
666 .formats = MC13783_FORMATS,
668 .ops = &mc13783_ops_dac,
670 .name = "mc13783-hifi-capture",
671 .id = MC13783_ID_STEREO_CODEC,
673 .stream_name = "Capture",
676 .rates = MC13783_RATES_RECORD,
677 .formats = MC13783_FORMATS,
679 .ops = &mc13783_ops_codec,
683 static struct snd_soc_dai_ops mc13783_ops_sync = {
684 .hw_params = mc13783_pcm_hw_params_sync,
685 .set_fmt = mc13783_set_fmt_sync,
686 .set_sysclk = mc13783_set_sysclk_sync,
687 .set_tdm_slot = mc13783_set_tdm_slot_sync,
690 static struct snd_soc_dai_driver mc13783_dai_sync[] = {
692 .name = "mc13783-hifi",
693 .id = MC13783_ID_SYNC,
695 .stream_name = "Playback",
698 .rates = SNDRV_PCM_RATE_8000_96000,
699 .formats = MC13783_FORMATS,
702 .stream_name = "Capture",
705 .rates = MC13783_RATES_RECORD,
706 .formats = MC13783_FORMATS,
708 .ops = &mc13783_ops_sync,
709 .symmetric_rates = 1,
713 static struct snd_soc_codec_driver soc_codec_dev_mc13783 = {
714 .probe = mc13783_probe,
715 .remove = mc13783_remove,
716 .read = mc13783_read,
717 .write = mc13783_write,
718 .controls = mc13783_control_list,
719 .num_controls = ARRAY_SIZE(mc13783_control_list),
720 .dapm_widgets = mc13783_dapm_widgets,
721 .num_dapm_widgets = ARRAY_SIZE(mc13783_dapm_widgets),
722 .dapm_routes = mc13783_routes,
723 .num_dapm_routes = ARRAY_SIZE(mc13783_routes),
726 static int mc13783_codec_probe(struct platform_device *pdev)
728 struct mc13xxx *mc13xxx;
729 struct mc13783_priv *priv;
730 struct mc13xxx_codec_platform_data *pdata = pdev->dev.platform_data;
733 mc13xxx = dev_get_drvdata(pdev->dev.parent);
736 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
740 dev_set_drvdata(&pdev->dev, priv);
741 priv->mc13xxx = mc13xxx;
743 priv->adc_ssi_port = pdata->adc_ssi_port;
744 priv->dac_ssi_port = pdata->dac_ssi_port;
746 priv->adc_ssi_port = MC13783_SSI1_PORT;
747 priv->dac_ssi_port = MC13783_SSI2_PORT;
750 if (priv->adc_ssi_port == priv->dac_ssi_port)
751 ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_mc13783,
752 mc13783_dai_sync, ARRAY_SIZE(mc13783_dai_sync));
754 ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_mc13783,
755 mc13783_dai_async, ARRAY_SIZE(mc13783_dai_async));
758 goto err_register_codec;
763 dev_err(&pdev->dev, "register codec failed with %d\n", ret);
768 static int mc13783_codec_remove(struct platform_device *pdev)
770 snd_soc_unregister_codec(&pdev->dev);
775 static struct platform_driver mc13783_codec_driver = {
777 .name = "mc13783-codec",
778 .owner = THIS_MODULE,
780 .probe = mc13783_codec_probe,
781 .remove = mc13783_codec_remove,
784 module_platform_driver(mc13783_codec_driver);
786 MODULE_DESCRIPTION("ASoC MC13783 driver");
787 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
788 MODULE_AUTHOR("Philippe Retornaz <philippe.retornaz@epfl.ch>");
789 MODULE_LICENSE("GPL");