sound/soc/codecs/rk1000_codec.c

   1 /*
   2  * rk1000.c -- RK1000 ALSA SoC audio driver
   3  *
   4  * Copyright (C) 2009 rockchip lhh
   5  *
   6  *
   7  * Based on RK1000.c
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32 #include <mach/gpio.h>
  33 #include <mach/iomux.h>
  34
  35 #include "rk1000_codec.h"
  36 #define RK1000_CODEC_PROC
  37 #ifdef RK1000_CODEC_PROC
  38 #include <linux/proc_fs.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/vmalloc.h>
  41 char debug_write_read = 0;
  42 #endif
  43 /*
  44  * Debug
  45  */
  46 #if 1
  47 #define DBG(x...)       printk(KERN_INFO x)
  48 #else
  49 #define DBG(x...)
  50 #endif
  51
  52 #define err(format, arg...) \
  53         printk(KERN_ERR AUDIO_NAME ": " format "\n" , ## arg)
  54 #define info(format, arg...) \
  55         printk(KERN_INFO AUDIO_NAME ": " format "\n" , ## arg)
  56
  57 #define OUT_CAPLESS  (0)   //ÊÇ·ñÎªÎÞµçÈÝÊä³ö£¬1:ÎÞµçÈÝÊä³ö£¬0:ÓÐµçÈÝÊä³ö
  58
  59 static struct snd_soc_codec *rk1000_codec_codec;
  60
  61 //static u32 gVolReg = 0x0f;  ///0x0f; //ÓÃÓÚ¼ÇÂ¼ÒôÁ¿¼Ä´æÆ÷
  62 //static u32 gCodecVol = 0x0f;
  63 static u8 gR0AReg = 0;  //ÓÃÓÚ¼ÇÂ¼R0A¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚ¸Ä±ä²ÉÑùÂÊÇ°Í¨¹ýR0AÍ£Ö¹clk
  64 static u8 gR0BReg = 0;  //ÓÃÓÚ¼ÇÂ¼R0B¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚ¸Ä±ä²ÉÑùÂÊÇ°Í¨¹ýR0BÍ£Ö¹interplateºÍdecimation
  65 static u8 gR1314Reg = 0;  //ÓÃÓÚ¼ÇÂ¼R13,R14¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚFMÒôÁ¿Îª0Ê±
  66
  67 /*
  68  * rk1000 register cache
  69  * We can't read the RK1000 register space when we
  70  * are using 2 wire for device control, so we cache them instead.
  71  */
  72 static const u16 rk1000_codec_reg[] = {
  73         0x0005, 0x0004, 0x00fd, 0x00f3,  /*  0 */
  74         0x0003, 0x0000, 0x0000, 0x0000,  /*  4 */
  75         0x0000, 0x0005, 0x0000, 0x0000,  /*  8 */
  76         0x0097, 0x0097, 0x0097, 0x0097,  /* 0x0a */
  77         0x0097, 0x0097, 0x00cc, 0x0000,  /* 0x10 */
  78         0x0000, 0x00f1, 0x0090, 0x00ff,  /* 0x14 */
  79         0x00ff, 0x00ff, 0x009c, 0x0000,  /* 0x18 */
  80         0x0000, 0x00ff, 0x00ff, 0x00ff,  /* 0x1a */
  81 };
  82
  83 /* codec private data */
  84 struct rk1000_codec_priv {
  85         enum snd_soc_control_type control_type;
  86         void *control_data;
  87
  88         unsigned int sysclk;
  89         struct snd_soc_codec codec;
  90         struct snd_pcm_hw_constraint_list *sysclk_constraints;
  91         u16 reg_cache[RK1000_CODEC_NUM_REG];
  92 };
  93
  94 /*
  95  * read rk1000 register cache
  96  */
  97 static inline unsigned int rk1000_codec_read_reg_cache(struct snd_soc_codec *codec,
  98         unsigned int reg)
  99 {
 100         u16 *cache = codec->reg_cache;
 101         if (reg > RK1000_CACHE_REGNUM)
 102                 return -1;
 103         return cache[reg];
 104 }
 105
 106 static unsigned int rk1000_codec_read(struct snd_soc_codec *codec, unsigned int r)
 107 {
 108         struct i2c_msg xfer[1];
 109         u8 reg = r;
 110         int ret;
 111         struct i2c_client *client = codec->control_data;
 112
 113         /* Read register */
 114         xfer[0].addr = (client->addr& 0x60)|(reg);
 115         xfer[0].flags = I2C_M_RD;
 116         xfer[0].len = 1;
 117         xfer[0].buf = &reg;
 118         xfer[0].scl_rate = 100*1000;
 119         ret = i2c_transfer(client->adapter, xfer, 1);
 120         if (ret != 1) {
 121                 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
 122                 return 0;
 123         }
 124
 125         return reg;
 126 }
 127
 128 /*
 129  * write rk1000 register cache
 130  */
 131 static inline void rk1000_codec_write_reg_cache(struct snd_soc_codec *codec,
 132         unsigned int reg, unsigned int value)
 133 {
 134         u16 *cache = codec->reg_cache;
 135         if (reg > RK1000_CACHE_REGNUM)
 136                 return;
 137         cache[reg] = value;
 138 }
 139
 140 static int rk1000_codec_write(struct snd_soc_codec *codec, unsigned int reg,
 141         unsigned int value)
 142 {
 143         u8 data[2];
 144         struct i2c_client *i2c;
 145         DBG("Enter-%s::reg=0x%02X, value=0x%02X\n",__FUNCTION__, reg, value);
 146         data[0] = value & 0x00ff;
 147         rk1000_codec_write_reg_cache (codec, reg, value);
 148         i2c = (struct i2c_client *)codec->control_data;
 149         i2c->addr = (i2c->addr & 0x60)|reg;
 150         if (codec->hw_write(codec->control_data, data, 1) == 1){
 151 //                DBG("================%s Run OK====%d============\n",__FUNCTION__,__LINE__);
 152                 return 0;
 153         }else{
 154                 DBG("================%s Run EIO=======%d=========\n",__FUNCTION__,__LINE__);
 155                 return -EIO;
 156         }
 157 }
 158
 159 static const struct snd_kcontrol_new rk1000_codec_snd_controls[] = {
 160
 161 SOC_DOUBLE_R("Capture Volume", ACCELCODEC_R0C, ACCELCODEC_R0D, 0, 15, 0),
 162 SOC_DOUBLE_R("Capture Switch", ACCELCODEC_R0C, ACCELCODEC_R0D, 7, 1, 1),
 163
 164 SOC_DOUBLE_R("PCM Volume", ACCELCODEC_R0D, ACCELCODEC_R0E, 0, 7, 0),
 165
 166 //SOC_SINGLE("Left ADC Capture Volume", ACCELCODEC_R17, 0, 63, 0),
 167 //SOC_SINGLE("Right ADC Capture Volume", ACCELCODEC_R18, 0, 63, 0),
 168
 169
 170 };
 171
 172
 173 /* Left Mixer */
 174 static const struct snd_kcontrol_new rk1000_codec_left_mixer_controls[] = {
 175 SOC_DAPM_SINGLE("Playback Switch", ACCELCODEC_R15, 6, 1, 0),
 176 SOC_DAPM_SINGLE("Left Bypass Switch", ACCELCODEC_R15, 2, 1, 0),
 177
 178 };
 179
 180 /* Right Mixer */
 181 static const struct snd_kcontrol_new rk1000_codec_right_mixer_controls[] = {
 182 SOC_DAPM_SINGLE("Playback Switch", ACCELCODEC_R15, 7, 1, 0),
 183 SOC_DAPM_SINGLE("Left Bypass Switch", ACCELCODEC_R15, 3, 1, 0),
 184
 185 };
 186
 187
 188 static const struct snd_soc_dapm_widget rk1000_codec_dapm_widgets[] = {
 189         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
 190                 &rk1000_codec_left_mixer_controls[0],
 191                 ARRAY_SIZE(rk1000_codec_left_mixer_controls)),
 192         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
 193                 &rk1000_codec_right_mixer_controls[0],
 194                 ARRAY_SIZE(rk1000_codec_right_mixer_controls)),
 195
 196         //SND_SOC_DAPM_PGA("Right Out 1", ACCELCODEC_R1E, 0, 0, NULL, 0),
 197         //SND_SOC_DAPM_PGA("Left Out 1", ACCELCODEC_R1E, 1, 0, NULL, 0),
 198         //SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ACCELCODEC_R1F, 1, 0),
 199         //SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ACCELCODEC_R1F, 2, 0),
 200
 201         SND_SOC_DAPM_ADC("ADC", "Capture", ACCELCODEC_R1D, 6, 1),
 202         SND_SOC_DAPM_ADC("ADC BUFF", "Capture BUFF", ACCELCODEC_R1D, 2, 0),
 203
 204
 205         SND_SOC_DAPM_OUTPUT("LOUT1"),
 206         SND_SOC_DAPM_OUTPUT("ROUT1"),
 207
 208         SND_SOC_DAPM_INPUT("LINPUT1"),
 209         SND_SOC_DAPM_INPUT("RINPUT1"),
 210 };
 211
 212 static const struct snd_soc_dapm_route audio_map[] = {
 213         /* left mixer */
 214         {"Left Mixer", "Playback Switch", "Left DAC"},
 215         {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
 216         {"Right Mixer", "Playback Switch", "Right DAC"},
 217         {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
 218
 219         /* left out 1 */
 220         {"Left Out 1", NULL, "Left Mixer"},
 221         {"LOUT1", NULL, "Left Out 1"},
 222
 223
 224         /* right out 1 */
 225         {"Right Out 1", NULL, "Right Mixer"},
 226         {"ROUT1", NULL, "Right Out 1"},
 227
 228         /* Left Line Mux */
 229         {"Left Line Mux", "Line 1", "LINPUT1"},
 230         {"Left Line Mux", "PGA", "Left PGA Mux"},
 231         {"Left Line Mux", "Differential", "Differential Mux"},
 232
 233         /* Right Line Mux */
 234         {"Right Line Mux", "Line 1", "RINPUT1"},
 235         {"Right Line Mux", "PGA", "Right PGA Mux"},
 236         {"Right Line Mux", "Differential", "Differential Mux"},
 237
 238         /* Left PGA Mux */
 239         {"Left PGA Mux", "Line 1", "LINPUT1"},
 240         {"Left PGA Mux", "Line 2", "LINPUT2"},
 241         {"Left PGA Mux", "Line 3", "LINPUT3"},
 242         {"Left PGA Mux", "Differential", "Differential Mux"},
 243
 244         /* Right PGA Mux */
 245         {"Right PGA Mux", "Line 1", "RINPUT1"},
 246         {"Right PGA Mux", "Differential", "Differential Mux"},
 247
 248         /* Differential Mux */
 249         {"Differential Mux", "Line 1", "LINPUT1"},
 250         {"Differential Mux", "Line 1", "RINPUT1"},
 251
 252         /* Left ADC Mux */
 253         {"Left ADC Mux", "Stereo", "Left PGA Mux"},
 254         {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
 255         {"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
 256
 257         /* Right ADC Mux */
 258         {"Right ADC Mux", "Stereo", "Right PGA Mux"},
 259         {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
 260         {"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
 261
 262         /* ADC */
 263         {"Left ADC", NULL, "Left ADC Mux"},
 264         {"Right ADC", NULL, "Right ADC Mux"},
 265
 266         /* terminator */
 267         {NULL, NULL, NULL},
 268 };
 269
 270 struct _coeff_div {
 271         u32 mclk;
 272         u32 rate;
 273         u16 fs;
 274         u8 sr:5;
 275         u8 usb:1;
 276         u8 bclk;
 277 };
 278
 279 /* codec hifi mclk clock divider coefficients */
 280 static const struct _coeff_div coeff_div[] = {
 281         /* 8k */
 282         {12288000, 8000, 1536, 0x6, 0x0,ASC_BCLKDIV_16},
 283         {11289600, 8000, 1408, 0x16, 0x0,ASC_BCLKDIV_16},
 284         {18432000, 8000, 2304, 0x7, 0x0,ASC_BCLKDIV_16},
 285         {16934400, 8000, 2112, 0x17, 0x0,ASC_BCLKDIV_16},
 286         {8192000, 8000, 1024, 0x0, 0x0,ASC_BCLKDIV_16},
 287         {12000000, 8000, 1500, 0x6, 0x1,ASC_BCLKDIV_16},
 288
 289         /* 11.025k */
 290         {11289600, 11025, 1024, 0x18, 0x0,ASC_BCLKDIV_16},
 291         {16934400, 11025, 1536, 0x19, 0x0,ASC_BCLKDIV_16},
 292         {12000000, 11025, 1088, 0x19, 0x1,ASC_BCLKDIV_16},
 293
 294     /* 12k */
 295         {12288000, 12000, 1024, 0x8, 0x0,ASC_BCLKDIV_16},
 296         {18432000, 12000, 1536, 0x9, 0x0,ASC_BCLKDIV_16},
 297         {12000000, 12000, 1000, 0x8, 0x1,ASC_BCLKDIV_16},
 298
 299         /* 16k */
 300         {12288000, 16000, 768, 0xa, 0x0,ASC_BCLKDIV_8},
 301         {18432000, 16000, 1152, 0xb, 0x0,ASC_BCLKDIV_8},
 302         {12000000, 16000, 750, 0xa, 0x1,ASC_BCLKDIV_8},
 303
 304         /* 22.05k */
 305         {11289600, 22050, 512, 0x1a, 0x0,ASC_BCLKDIV_8},
 306         {16934400, 22050, 768, 0x1b, 0x0,ASC_BCLKDIV_8},
 307         {12000000, 22050, 544, 0x1b, 0x1,ASC_BCLKDIV_8},
 308
 309     /* 24k */
 310         {12288000, 24000, 512, 0x1c, 0x0,ASC_BCLKDIV_8},
 311         {18432000, 24000, 768, 0x1d, 0x0,ASC_BCLKDIV_8},
 312         {12000000, 24000, 500, 0x1c, 0x1,ASC_BCLKDIV_8},
 313
 314         /* 32k */
 315         {12288000, 32000, 384, 0xc, 0x0,ASC_BCLKDIV_8},
 316         {18432000, 32000, 576, 0xd, 0x0,ASC_BCLKDIV_8},
 317         {12000000, 32000, 375, 0xa, 0x1,ASC_BCLKDIV_8},
 318
 319         /* 44.1k */
 320         {11289600, 44100, 256, 0x10, 0x0,ASC_BCLKDIV_8},
 321         {16934400, 44100, 384, 0x11, 0x0,ASC_BCLKDIV_8},
 322         {12000000, 44100, 272, 0x11, 0x1,ASC_BCLKDIV_8},
 323
 324         /* 48k */
 325         {12288000, 48000, 256, 0x0, 0x0,ASC_BCLKDIV_4},
 326         {18432000, 48000, 384, 0x1, 0x0,ASC_BCLKDIV_4},
 327         {12000000, 48000, 250, 0x0, 0x1,ASC_BCLKDIV_4},
 328
 329         /* 88.2k */
 330         {11289600, 88200, 128, 0x1e, 0x0,ASC_BCLKDIV_4},
 331         {16934400, 88200, 192, 0x1f, 0x0,ASC_BCLKDIV_4},
 332         {12000000, 88200, 136, 0x1f, 0x1,ASC_BCLKDIV_4},
 333
 334         /* 96k */
 335         {12288000, 96000, 128, 0xe, 0x0,ASC_BCLKDIV_4},
 336         {18432000, 96000, 192, 0xf, 0x0,ASC_BCLKDIV_4},
 337         {12000000, 96000, 125, 0xe, 0x1,ASC_BCLKDIV_4},
 338 };
 339
 340 static inline int get_coeff(int mclk, int rate)
 341 {
 342         int i;
 343
 344         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
 345                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
 346                         return i;
 347         }
 348
 349         return -EINVAL;
 350 }
 351
 352 /* The set of rates we can generate from the above for each SYSCLK */
 353
 354 static unsigned int rates_12288[] = {
 355         8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
 356 };
 357
 358 static struct snd_pcm_hw_constraint_list constraints_12288 = {
 359         .count  = ARRAY_SIZE(rates_12288),
 360         .list   = rates_12288,
 361 };
 362
 363 static unsigned int rates_112896[] = {
 364         8000, 11025, 22050, 44100,
 365 };
 366
 367 static struct snd_pcm_hw_constraint_list constraints_112896 = {
 368         .count  = ARRAY_SIZE(rates_112896),
 369         .list   = rates_112896,
 370 };
 371
 372 static unsigned int rates_12[] = {
 373         8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
 374         48000, 88235, 96000,
 375 };
 376
 377 static struct snd_pcm_hw_constraint_list constraints_12 = {
 378         .count  = ARRAY_SIZE(rates_12),
 379         .list   = rates_12,
 380 };
 381
 382 /*
 383  * Note that this should be called from init rather than from hw_params.
 384  */
 385 static int rk1000_codec_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 386                 int clk_id, unsigned int freq, int dir)
 387 {
 388         struct snd_soc_codec *codec = codec_dai->codec;
 389         struct rk1000_codec_priv *rk1000_codec = snd_soc_codec_get_drvdata(codec);
 390
 391         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 392         freq = 12000000;
 393         switch (freq) {
 394         case 11289600:
 395         case 18432000:
 396         case 22579200:
 397         case 36864000:
 398                 rk1000_codec->sysclk_constraints = &constraints_112896;
 399                 rk1000_codec->sysclk = freq;
 400                 return 0;
 401
 402         case 12288000:
 403         case 16934400:
 404         case 24576000:
 405         case 33868800:
 406                 rk1000_codec->sysclk_constraints = &constraints_12288;
 407                 rk1000_codec->sysclk = freq;
 408                 return 0;
 409
 410         case 12000000:
 411         case 24000000:
 412                 rk1000_codec->sysclk_constraints = &constraints_12;
 413                 rk1000_codec->sysclk = freq;
 414                 return 0;
 415         }
 416         return -EINVAL;
 417 }
 418
 419 static int rk1000_codec_set_dai_fmt(struct snd_soc_dai *codec_dai,
 420                 unsigned int fmt)
 421 {
 422         struct snd_soc_codec *codec = codec_dai->codec;
 423         u16 iface = 0;
 424
 425         /* set master/slave audio interface */
 426         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 427         case SND_SOC_DAIFMT_CBM_CFM:
 428                 iface = 0x0040;
 429                 break;
 430         case SND_SOC_DAIFMT_CBS_CFS:
 431                 iface = 0x0020;
 432                 break;
 433         default:
 434                 return -EINVAL;
 435         }
 436
 437         /* interface format */
 438         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 439         case SND_SOC_DAIFMT_I2S:
 440                 iface |= 0x0002;
 441                 break;
 442         case SND_SOC_DAIFMT_RIGHT_J:
 443                 break;
 444         case SND_SOC_DAIFMT_LEFT_J:
 445                 iface |= 0x0001;
 446                 break;
 447         case SND_SOC_DAIFMT_DSP_A:
 448                 iface |= 0x0003;
 449                 break;
 450         case SND_SOC_DAIFMT_DSP_B:
 451                 iface |= 0x0013;
 452                 break;
 453         default:
 454                 return -EINVAL;
 455         }
 456
 457         /* clock inversion */
 458         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 459         case SND_SOC_DAIFMT_NB_NF:
 460                 break;
 461         case SND_SOC_DAIFMT_IB_IF:
 462                 iface |= 0x0090;
 463                 break;
 464         case SND_SOC_DAIFMT_IB_NF:
 465                 iface |= 0x0080;
 466                 break;
 467         case SND_SOC_DAIFMT_NB_IF:
 468                 iface |= 0x0010;
 469                 break;
 470         default:
 471                 return -EINVAL;
 472         }
 473
 474         DBG("Enter::%s----%d  iface=%x\n",__FUNCTION__,__LINE__,iface);
 475         rk1000_codec_write(codec, ACCELCODEC_R09, iface);
 476         return 0;
 477 }
 478
 479 static int rk1000_codec_pcm_startup(struct snd_pcm_substream *substream,
 480                               struct snd_soc_dai *dai)
 481 {
 482         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 483         struct snd_soc_codec *codec = rtd->codec;
 484         struct rk1000_codec_priv *rk1000_codec = snd_soc_codec_get_drvdata(codec);
 485
 486         /* The set of sample rates that can be supported depends on the
 487          * MCLK supplied to the CODEC - enforce this.
 488          */
 489         DBG("Enter::%s----%d  rk1000_codec->sysclk=%d\n",__FUNCTION__,__LINE__,rk1000_codec->sysclk);
 490 //      if (!rk1000_codec->sysclk) {
 491 //              dev_err(codec->dev,
 492 //                      "No MCLK configured, call set_sysclk() on init\n");
 493 //              return -EINVAL;
 494 //      }
 495
 496 #if 0
 497     snd_pcm_hw_constraint_list(substream->runtime, 0,
 498                                    SNDRV_PCM_HW_PARAM_RATE,
 499                                    rk1000_codec->sysclk_constraints);
 500 #endif
 501         return 0;
 502 }
 503
 504 static int rk1000_codec_pcm_hw_params(struct snd_pcm_substream *substream,
 505                                 struct snd_pcm_hw_params *params,
 506                                 struct snd_soc_dai *dai)
 507 {
 508         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 509         struct snd_soc_codec *codec = rtd->codec;
 510         struct rk1000_codec_priv *rk1000_codec = snd_soc_codec_get_drvdata(codec);
 511
 512         u16 iface = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R09) & 0x1f3;
 513         u16 srate = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R00) & 0x180;
 514         int coeff;
 515
 516         rk1000_codec->sysclk = 12000000;
 517         /*by Vincent Hsiung for EQ Vol Change*/
 518         #define HW_PARAMS_FLAG_EQVOL_ON 0x21
 519         #define HW_PARAMS_FLAG_EQVOL_OFF 0x22
 520         if (params->flags == HW_PARAMS_FLAG_EQVOL_ON)
 521         {
 522                 u16 r17 = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R17);
 523                 u16 r18 = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R18);
 524
 525                 r17 &= (~0x3f); //6db
 526                 r18 &= (~0x3f); //6db
 527
 528                 rk1000_codec_write(codec, ACCELCODEC_R17, r17);
 529                 rk1000_codec_write(codec, ACCELCODEC_R18, r18);
 530
 531                 return 0;
 532         }
 533         else if (params->flags == HW_PARAMS_FLAG_EQVOL_OFF)
 534         {
 535                 u16 r17 = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R17);
 536                 u16 r18 = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R18);
 537
 538                 r17 &= (~0x3f);
 539                 r17 |= 0x0f; //0db
 540
 541                 r18 &= (~0x3f);
 542                 r18 |= 0x0f; //0db
 543
 544                 rk1000_codec_write(codec, ACCELCODEC_R17, r17);
 545                 rk1000_codec_write(codec, ACCELCODEC_R18, r18);
 546                 return 0;
 547         }
 548
 549         coeff = get_coeff(rk1000_codec->sysclk, params_rate(params));
 550
 551         /* bit size */
 552         switch (params_format(params)) {
 553         case SNDRV_PCM_FORMAT_S16_LE:
 554                 break;
 555         case SNDRV_PCM_FORMAT_S20_3LE:
 556                 iface |= 0x0004;
 557                 break;
 558         case SNDRV_PCM_FORMAT_S24_LE:
 559                 iface |= 0x0008;
 560                 break;
 561         case SNDRV_PCM_FORMAT_S32_LE:
 562                 iface |= 0x000c;
 563                 break;
 564         }
 565         DBG("Enter::%s----%d  iface=%x srate =%x rate=%d\n",__FUNCTION__,__LINE__,iface,srate,params_rate(params));
 566
 567         rk1000_codec_write(codec,ACCELCODEC_R0C, 0x17);
 568         rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);   //soft mute
 569         //±ØÐëÏÈ½«clkºÍEN_INT¶¼disableµô£¬·ñÔòÇÐ»»bclk·ÖÆµÖµ¿ÉÄÜµ¼ÖÂcodecÄÚ²¿Ê±Ðò»ìÂÒµô£¬
 570         //±íÏÖ³öÀ´µÄÏÖÏóÊÇ£¬ÒÔºóµÄÒôÀÖ¶¼±ä³ÉÁËÔëÒô£¬¶øÇÒ¾ÍËã°ÑÊäÈëcodecµÄI2S_DATAOUT¶Ï¿ªÒ²Ò»Ñù³öÔëÒô
 571         rk1000_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_DISABLE|ASC_INT_DISABLE);  //0x00
 572
 573         /* set iface & srate */
 574         rk1000_codec_write(codec, ACCELCODEC_R09, iface);
 575         if (coeff >= 0)
 576         {
 577         //      rk1000_codec_write(codec, ACCELCODEC_R0A, (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb|ASC_CLKNODIV|ASC_CLK_ENABLE);
 578                 rk1000_codec_write(codec, ACCELCODEC_R0A, 0xa0);
 579         //      rk1000_codec_write(codec, ACCELCODEC_R00, srate|coeff_div[coeff].bclk);
 580         }
 581         rk1000_codec_write(codec,ACCELCODEC_R0B, gR0BReg);
 582
 583         return 0;
 584 }
 585
 586 void PhaseOut(struct snd_soc_codec *codec,u32 nStep, u32 us)
 587 {
 588         DBG("%s[%d]\n",__FUNCTION__,__LINE__);
 589         rk1000_codec_write(codec,ACCELCODEC_R17, 0x00|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOL
 590         rk1000_codec_write(codec,ACCELCODEC_R18, 0x00|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOR
 591         udelay(us);
 592 }
 593
 594 void PhaseIn(struct snd_soc_codec *codec,u32 nStep, u32 us)
 595 {
 596         DBG("%s[%d]\n",__FUNCTION__,__LINE__);
 597         rk1000_codec_write(codec,ACCELCODEC_R17, 0x00|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOL gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOL
 598         rk1000_codec_write(codec,ACCELCODEC_R18, 0x00|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOR
 599         udelay(us);
 600 }
 601
 602 static int rk1000_codec_mute(struct snd_soc_dai *dai, int mute)
 603 {
 604         struct snd_soc_codec *codec = dai->codec;
 605
 606         DBG("Enter::%s----%d--mute=%d\n",__FUNCTION__,__LINE__,mute);
 607
 608         if (mute)
 609         {
 610                 PhaseOut(codec,1, 5000);
 611                 rk1000_codec_write(codec,ACCELCODEC_R19, 0xFF);  //AOM
 612                 rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);  //soft mute
 613         }
 614         else
 615         {
 616                 rk1000_codec_write(codec,ACCELCODEC_R1D, 0x2a);  //setup Vmid and Vref, other module power down
 617                 rk1000_codec_write(codec,ACCELCODEC_R1E, 0x40);  ///|ASC_PDASDML_ENABLE);
 618                 rk1000_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE);  ///|ASC_PDMICB_ENABLE|ASC_PDMIXM_ENABLE);
 619                 PhaseIn(codec,1, 5000);
 620         //      if(gCodecVol != 0)
 621                 {
 622                         rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_ACTIVE_L|ASC_INT_ACTIVE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);
 623         }
 624                 rk1000_codec_write(codec,ACCELCODEC_R19, 0x7F);  //AOM
 625                 #if 0
 626                 /*disable speaker */
 627                 rockchip_mux_api_set(SPK_IOMUX_PIN_NAME, SPK_IOMUX_PIN_DIR);
 628                 GPIOSetPinDirection(SPK_CTRL_PIN,GPIO_OUT);
 629                 GPIOSetPinLevel(SPK_CTRL_PIN,GPIO_HIGH);
 630                 #endif
 631         }
 632         return 0;
 633 }
 634
 635 static int rk1000_codec_set_bias_level(struct snd_soc_codec *codec,
 636                                  enum snd_soc_bias_level level)
 637 {
 638         u16 pwr_reg = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R1D) & ~0x1c1;
 639         DBG("Enter::%s----%d level =%d\n",__FUNCTION__,__LINE__,level);
 640         switch (level) {
 641         case SND_SOC_BIAS_ON:
 642                 break;
 643
 644         case SND_SOC_BIAS_PREPARE:
 645                 /* VREF, VMID=2x50k, digital enabled */
 646                 rk1000_codec_write(codec, ACCELCODEC_R1D, pwr_reg | 0x0080);
 647                 break;
 648
 649         case SND_SOC_BIAS_STANDBY:
 650                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 651                         /* VREF, VMID=2x5k */
 652                         rk1000_codec_write(codec, ACCELCODEC_R1D, pwr_reg | 0x0080);
 653
 654                         /* Charge caps */
 655                         msleep(100);
 656                 }
 657
 658                 /* VREF, VMID=2*500k, digital stopped */
 659                 rk1000_codec_write(codec, ACCELCODEC_R1D, pwr_reg | 0x0080);
 660                 break;
 661
 662         case SND_SOC_BIAS_OFF:
 663                 rk1000_codec_write(codec, ACCELCODEC_R1D, 0x0000);
 664                 break;
 665         }
 666         codec->dapm.bias_level = level;
 667         return 0;
 668 }
 669
 670 #define RK1000_CODEC_RATES SNDRV_PCM_RATE_8000_96000
 671
 672 #define RK1000_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 673         SNDRV_PCM_FMTBIT_S24_LE)
 674
 675 static struct snd_soc_dai_ops rk1000_codec_ops = {
 676         .startup = rk1000_codec_pcm_startup,
 677         .hw_params = rk1000_codec_pcm_hw_params,
 678         .set_fmt = rk1000_codec_set_dai_fmt,
 679         .set_sysclk = rk1000_codec_set_dai_sysclk,
 680         .digital_mute = rk1000_codec_mute,
 681 };
 682
 683 static struct snd_soc_dai_driver rk1000_codec_dai[] = {
 684         {
 685                 .name = "rk1000_codec",
 686                 .playback = {
 687                         .stream_name = "Playback",
 688                         .channels_min = 1,
 689                         .channels_max = 2,
 690                         .rates = RK1000_CODEC_RATES,
 691                         .formats = RK1000_CODEC_FORMATS,
 692                 },
 693                 .capture = {
 694                         .stream_name = "Capture",
 695                         .channels_min = 1,
 696                         .channels_max = 2,
 697                         .rates = RK1000_CODEC_RATES,
 698                         .formats = RK1000_CODEC_FORMATS,
 699                  },
 700                 .ops = &rk1000_codec_ops,
 701                 .symmetric_rates = 1,
 702         }
 703 };
 704
 705 static int rk1000_codec_suspend(struct snd_soc_codec *codec, pm_message_t state)
 706 {
 707         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 708         rk1000_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
 709         return 0;
 710 }
 711
 712 static int rk1000_codec_resume(struct snd_soc_codec *codec)
 713 {
 714         int i;
 715         u8 data[2];
 716         struct i2c_client *i2c;
 717         u16 *cache = codec->reg_cache;
 718
 719         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 720         /* Sync reg_cache with the hardware */
 721         for (i = 0; i < RK1000_CODEC_NUM_REG; i++) {
 722                 data[0] = cache[i] & 0x00ff;
 723                 i2c = (struct i2c_client *)codec->control_data;
 724                 i2c->addr = (i2c->addr & 0x60)|i;
 725                 codec->hw_write(codec->control_data, data, 1);
 726         }
 727
 728         rk1000_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 729
 730         return 0;
 731 }
 732
 733 static void rk1000_reg_init(struct snd_soc_codec *codec)
 734 {
 735         rk1000_codec_write(codec,ACCELCODEC_R1D, 0x00);
 736     rk1000_codec_write(codec,ACCELCODEC_R17, 0xFF);  //AOL
 737     rk1000_codec_write(codec,ACCELCODEC_R18, 0xFF);  //AOR
 738     rk1000_codec_write(codec,ACCELCODEC_R19, 0xFF);  //AOM
 739
 740     rk1000_codec_write(codec,ACCELCODEC_R1F, 0xDF);
 741     mdelay(10);
 742     rk1000_codec_write(codec,ACCELCODEC_R1F, 0x5F);
 743     rk1000_codec_write(codec,ACCELCODEC_R19, 0x7F);  //AOM
 744     rk1000_codec_write(codec,ACCELCODEC_R15, 0xC1);//rk1000_codec_write(codec,ACCELCODEC_R15, 0xCD);//by Vincent Hsiung
 745     rk1000_codec_write(codec,ACCELCODEC_R1A, 0x1C);
 746     mdelay(100);
 747     rk1000_codec_write(codec,ACCELCODEC_R1F, 0x09);
 748     rk1000_codec_write(codec,ACCELCODEC_R1E, 0x00);
 749     mdelay(10);
 750     rk1000_codec_write(codec,ACCELCODEC_R1A, 0x14);
 751     rk1000_codec_write(codec,ACCELCODEC_R1D, 0xFE);
 752     rk1000_codec_write(codec,ACCELCODEC_R17, 0xBF);  //AOL
 753     rk1000_codec_write(codec,ACCELCODEC_R18, 0xBF);  //AOR
 754     rk1000_codec_write(codec,ACCELCODEC_R19, 0x7F);  //AOM
 755     rk1000_codec_write(codec,ACCELCODEC_R1F, 0xDF);
 756
 757     //2soft mute
 758     rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);   //soft mute
 759
 760     //2set default SR and clk
 761     rk1000_codec_write(codec,ACCELCODEC_R0A, ASC_USB_MODE|FREQ48kHz|ASC_CLKNODIV|ASC_CLK_DISABLE);
 762     gR0AReg = ASC_USB_MODE|FREQ48kHz|ASC_CLKNODIV|ASC_CLK_DISABLE;
 763     //2Config audio  interface
 764     rk1000_codec_write(codec,ACCELCODEC_R09, ASC_I2S_MODE|ASC_16BIT_MODE|ASC_NORMAL_LRCLK|ASC_LRSWAP_DISABLE|ASC_MASTER_MODE|ASC_NORMAL_BCLK);
 765     rk1000_codec_write(codec,ACCELCODEC_R00, ASC_HPF_ENABLE|ASC_DSM_MODE_DISABLE|ASC_SCRAMBLE_ENABLE|ASC_DITHER_ENABLE|ASC_BCLKDIV_8);  //BCLK div 8
 766     //2volume,input,outpu
 767     rk1000_codec_write(codec,ACCELCODEC_R05, 0x0e);
 768     rk1000_codec_write(codec,ACCELCODEC_R06, 0x42);
 769     rk1000_codec_write(codec,ACCELCODEC_R07, 0x0e);
 770     rk1000_codec_write(codec,ACCELCODEC_R08, 0x42);
 771
 772     rk1000_codec_write(codec,ACCELCODEC_R0C, 0x10|ASC_INPUT_VOL_0DB|ASC_INPUT_MUTE);   //LIL
 773     rk1000_codec_write(codec,ACCELCODEC_R0D, 0x10|ASC_INPUT_VOL_0DB);   //LIR
 774     rk1000_codec_write(codec,ACCELCODEC_R0E, 0x10|ASC_INPUT_VOL_0DB);   //MIC
 775     rk1000_codec_write(codec,ACCELCODEC_R12, 0x4c|ASC_MIC_INPUT|ASC_MIC_BOOST_20DB);  //mic input and boost 20dB
 776     rk1000_codec_write(codec,ACCELCODEC_R13, ASC_LPGAMX_DISABLE|ASC_ALMX_DISABLE|((LINE_2_MIXER_GAIN & 0x7) << 4)|0x0);
 777     rk1000_codec_write(codec,ACCELCODEC_R14, ASC_RPGAMX_DISABLE|ASC_ARMX_DISABLE|((LINE_2_MIXER_GAIN & 0x7) << 4)|0x0);
 778     gR1314Reg = ASC_RPGAMX_DISABLE|ASC_ARMX_DISABLE|((LINE_2_MIXER_GAIN & 0x7) << 4)|0x0;
 779
 780     //2other
 781     rk1000_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_DISABLE|ASC_INT_DISABLE);  //0x00
 782     gR0BReg = ASC_DEC_DISABLE|ASC_INT_DISABLE;
 783     rk1000_codec_write(codec,ACCELCODEC_R15, \
 784                     0x01|ASC_RLPFMX_DISABLE|ASC_LLPFMX_DISABLE|ASC_LDAMX_DISABLE|ASC_RDAMX_DISABLE|ASC_LSCF_ACTIVE|ASC_RSCF_ACTIVE);  //0x3c
 785     rk1000_codec_write(codec,ACCELCODEC_R1B, 0x32);
 786     rk1000_codec_write(codec,ACCELCODEC_R1C, ASC_DEM_ENABLE);  ///0x00);  //use default value
 787
 788     //dac mode
 789     rk1000_codec_write(codec,ACCELCODEC_R17, 0xBF);  //AOL  ÒôÁ¿×îµÍ
 790     rk1000_codec_write(codec,ACCELCODEC_R18, 0xBF);  //AOR
 791
 792     //2power down useless module
 793     rk1000_codec_write(codec,ACCELCODEC_R1D, 0x2a|ASC_PDSDL_ENABLE|ASC_PDBSTL_ENABLE|ASC_PDPGAL_ENABLE);  //setup Vmid and Vref, other module power down
 794     rk1000_codec_write(codec,ACCELCODEC_R1E, 0x40|ASC_PDASDML_ENABLE);
 795     #if OUT_CAPLESS
 796     rk1000_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMICB_ENABLE|ASC_PDMIXM_ENABLE);
 797     #else
 798     rk1000_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMICB_ENABLE|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE);
 799     #endif
 800
 801     //2other
 802     rk1000_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_DISABLE|ASC_INT_ENABLE);
 803     gR0BReg = ASC_DEC_ENABLE|ASC_INT_ENABLE;  //ASC_DEC_DISABLE|ASC_INT_ENABLE;
 804     rk1000_codec_write(codec,ACCELCODEC_R15, 0xC1);//rk1000_codec_write(codec,ACCELCODEC_R15, 0xCD);//by Vincent Hsiung
 805     rk1000_codec_write(codec,ACCELCODEC_R0C, 0x10|ASC_INPUT_VOL_0DB|ASC_INPUT_MUTE);   //LIL
 806     rk1000_codec_write(codec,ACCELCODEC_R0D, 0x10|ASC_INPUT_VOL_0DB);   //LIR
 807     rk1000_codec_write(codec,ACCELCODEC_R0E, 0x10|ASC_INPUT_VOL_0DB);   //MIC
 808     rk1000_codec_write(codec,ACCELCODEC_R12, 0x4c|ASC_MIC_INPUT|ASC_MIC_BOOST_20DB);  //mic input and boost 20dB
 809     rk1000_codec_write(codec,ACCELCODEC_R13, 0x00);
 810     rk1000_codec_write(codec,ACCELCODEC_R14, 0x00);
 811     gR1314Reg = 0x00;
 812     rk1000_codec_write(codec,ACCELCODEC_R1C, ASC_DEM_ENABLE);  //0x00);  //use default value
 813 }
 814
 815 static int rk1000_codec_probe(struct snd_soc_codec *codec)
 816 {
 817         struct rk1000_codec_priv *rk1000_codec_priv = snd_soc_codec_get_drvdata(codec);
 818
 819         int ret = 0;
 820         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 821
 822         rk1000_codec_codec = codec;
 823
 824         codec->control_data = rk1000_codec_priv->control_data;
 825
 826         ret = snd_soc_codec_set_cache_io(codec, 8, 8, rk1000_codec_priv->control_type);
 827         if (ret != 0) {
 828                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 829                 return ret;
 830         }
 831
 832         codec->reg_cache = kmemdup(rk1000_codec_reg, sizeof(rk1000_codec_reg), GFP_KERNEL);
 833         if (codec->reg_cache == NULL)
 834                 return -ENOMEM;
 835
 836         rk1000_reg_init(codec);
 837 //      snd_soc_add_controls(codec, rk1000_codec_snd_controls,
 838 //                              ARRAY_SIZE(rk1000_codec_snd_controls));
 839 //      snd_soc_dapm_new_controls(codec, rk1000_codec_dapm_widgets,
 840 //                                ARRAY_SIZE(rk1000_codec_dapm_widgets));
 841 //      snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 842
 843
 844         return ret;
 845 }
 846
 847 static int rk1000_codec_remove(struct snd_soc_codec *codec)
 848 {
 849         struct rk1000_codec_priv *rk1000_codec_priv = snd_soc_codec_get_drvdata(codec);
 850
 851         rk1000_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
 852         kfree(rk1000_codec_priv);
 853         return 0;
 854 }
 855
 856 static struct snd_soc_codec_driver soc_codec_dev_rk1000_codec = {
 857         .probe =        rk1000_codec_probe,
 858         .remove =       rk1000_codec_remove,
 859         .suspend =      rk1000_codec_suspend,
 860         .resume =       rk1000_codec_resume,
 861         .set_bias_level = rk1000_codec_set_bias_level,
 862         .read =         rk1000_codec_read,
 863         .write =        rk1000_codec_write,
 864 //      .readable_register = rk1000_codec_read_reg_cache,
 865 //      .writable_register = rk1000_codec_write_reg_cache,
 866 //      .volatile_register = wm8994_volatile,
 867         .reg_cache_size = ARRAY_SIZE(rk1000_codec_reg),
 868         .reg_word_size = sizeof(u8),
 869         .reg_cache_default = rk1000_codec_reg,
 870 };
 871
 872 #ifdef RK1000_CODEC_PROC
 873 static int rk1000_codec_proc_init(void);
 874 #endif
 875
 876 static __devinit int rk1000_codec_i2c_probe(struct i2c_client *i2c,
 877                             const struct i2c_device_id *id)
 878 {
 879         struct rk1000_codec_priv *rk1000_codec;
 880         int ret;
 881         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 882         rk1000_codec = kzalloc(sizeof(struct rk1000_codec_priv), GFP_KERNEL);
 883         if (rk1000_codec == NULL)
 884                 return -ENOMEM;
 885
 886         i2c_set_clientdata(i2c, rk1000_codec);
 887         rk1000_codec->control_type = SND_SOC_I2C;
 888         rk1000_codec->control_data = i2c;
 889
 890         ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rk1000_codec,
 891                         rk1000_codec_dai, ARRAY_SIZE(rk1000_codec_dai));
 892         if (ret < 0)
 893                 kfree(rk1000_codec);
 894
 895 #ifdef RK1000_CODEC_PROC
 896   rk1000_codec_proc_init();
 897 #endif
 898
 899         return ret;
 900 }
 901
 902 static __devexit int rk1000_codec_i2c_remove(struct i2c_client *client)
 903 {
 904         snd_soc_unregister_codec(&client->dev);
 905         kfree(i2c_get_clientdata(client));
 906         return 0;
 907 }
 908
 909 static const struct i2c_device_id rk1000_codec_i2c_id[] = {
 910         { "rk1000_i2c_codec", 0 },
 911         { }
 912 };
 913 MODULE_DEVICE_TABLE(i2c, rk1000_codec_i2c_id);
 914
 915 /* corgi i2c codec control layer */
 916 static struct i2c_driver rk1000_codec_i2c_driver = {
 917         .driver = {
 918                 .name = "RK1000_CODEC",
 919                 .owner = THIS_MODULE,
 920         },
 921         .probe = rk1000_codec_i2c_probe,
 922         .remove = __devexit_p(rk1000_codec_i2c_remove),
 923         .id_table = rk1000_codec_i2c_id,
 924 };
 925
 926
 927 static int __init rk1000_codec_modinit(void)
 928 {
 929         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 930         return i2c_add_driver(&rk1000_codec_i2c_driver);
 931 }
 932 module_init(rk1000_codec_modinit);
 933
 934 static void __exit rk1000_codec_exit(void)
 935 {
 936         i2c_del_driver(&rk1000_codec_i2c_driver);
 937 }
 938 module_exit(rk1000_codec_exit);
 939
 940 #ifdef RK1000_CODEC_PROC
 941 void rk1000_codec_reg_read(void)
 942 {
 943     struct snd_soc_codec *codec = rk1000_codec_codec;
 944     int i;
 945     unsigned int data;
 946
 947     for (i=0; i<=0x1f; i++){
 948         data = rk1000_codec_read(codec, i);
 949         printk("reg[0x%x]=0x%x\n",i,data);
 950     }
 951 }
 952
 953 static ssize_t rk1000_codec_proc_write(struct file *file, const char __user *buffer,
 954                            unsigned long len, void *data)
 955 {
 956         char *cookie_pot;
 957         char *p;
 958         int reg;
 959         int value;
 960
 961         cookie_pot = (char *)vmalloc( len );
 962         if (!cookie_pot)
 963         {
 964                 return -ENOMEM;
 965         }
 966         else
 967         {
 968                 if (copy_from_user( cookie_pot, buffer, len ))
 969                         return -EFAULT;
 970         }
 971
 972         switch(cookie_pot[0])
 973         {
 974         case 'd':
 975         case 'D':
 976                 debug_write_read ++;
 977                 debug_write_read %= 2;
 978                 if(debug_write_read != 0)
 979                         printk("Debug read and write reg on\n");
 980                 else
 981                         printk("Debug read and write reg off\n");
 982                 break;
 983         case 'r':
 984         case 'R':
 985                 printk("Read reg debug\n");
 986                 if(cookie_pot[1] ==':')
 987                 {
 988                         debug_write_read = 1;
 989                         strsep(&cookie_pot,":");
 990                         while((p=strsep(&cookie_pot,",")))
 991                         {
 992                                 reg = simple_strtol(p,NULL,16);
 993                                 value = rk1000_codec_read(rk1000_codec_codec,reg);
 994                                 printk("rk1000_codec_read:0x%04x = 0x%04x",reg,value);
 995                         }
 996                         debug_write_read = 0;
 997                         printk("\n");
 998                 }
 999                 else
1000                 {
1001                         printk("Error Read reg debug.\n");
1002                         printk("For example: echo 'r:22,23,24,25'>wm8994_ts\n");
1003                 }
1004                 break;
1005         case 'w':
1006         case 'W':
1007                 printk("Write reg debug\n");
1008                 if(cookie_pot[1] ==':')
1009                 {
1010                         debug_write_read = 1;
1011                         strsep(&cookie_pot,":");
1012                         while((p=strsep(&cookie_pot,"=")))
1013                         {
1014                                 reg = simple_strtol(p,NULL,16);
1015                                 p=strsep(&cookie_pot,",");
1016                                 value = simple_strtol(p,NULL,16);
1017                                 rk1000_codec_write(rk1000_codec_codec,reg,value);
1018                                 printk("rk1000_codec_write:0x%04x = 0x%04x\n",reg,value);
1019                         }
1020                         debug_write_read = 0;
1021                         printk("\n");
1022                 }
1023                 else
1024                 {
1025                         printk("Error Write reg debug.\n");
1026                         printk("For example: w:22=0,23=0,24=0,25=0\n");
1027                 }
1028                 break;
1029         case 'p'://enable pa
1030                 rk1000_codec_reg_read();
1031                 break;
1032         default:
1033                 printk("Help for rk1000_codec_ts .\n-->The Cmd list: \n");
1034                 printk("-->'d&&D' Open or Off the debug\n");
1035                 printk("-->'r&&R' Read reg debug,Example: echo 'r:22,23,24,25'>rk1000_codec_ts\n");
1036                 printk("-->'w&&W' Write reg debug,Example: echo 'w:22=0,23=0,24=0,25=0'>rk1000_codec_ts\n");
1037                 break;
1038         }
1039
1040         return len;
1041 }
1042 static const struct file_operations rk1000_codec_proc_fops = {
1043         .owner          = THIS_MODULE,
1044         //.open         = snd_mem_proc_open,
1045         //.read         = seq_read,
1046 //#ifdef CONFIG_PCI
1047 //      .write          = rk1000_codec_proc_write,
1048 //#endif
1049         //.llseek       = seq_lseek,
1050         //.release      = single_release,
1051 };
1052
1053 static int rk1000_codec_proc_init(void)
1054 {
1055         struct proc_dir_entry *rk1000_codec_proc_entry;
1056         rk1000_codec_proc_entry = create_proc_entry("driver/rk1000_codec", 0777, NULL);
1057         if(rk1000_codec_proc_entry != NULL)
1058         {
1059                 rk1000_codec_proc_entry->write_proc = rk1000_codec_proc_write;
1060                 return -1;
1061         }
1062         else
1063         {
1064                 printk("create rk1000_codec proc error !\n");
1065         }
1066         return 0;
1067 }
1068
1069 #endif
1070
1071 #if 1
1072 int reg_send_data(struct i2c_client *client, const char start_reg,
1073                                 const char *buf, int count, unsigned int scl_rate)
1074 {
1075         int ret;
1076         struct i2c_adapter *adap = client->adapter;
1077         struct i2c_msg msg;
1078         char tx_buf[count + 1];
1079
1080         tx_buf[0] = start_reg;
1081         memcpy(tx_buf+1, buf, count);
1082
1083         msg.addr = client->addr;
1084         msg.buf = tx_buf;
1085         msg.len = count +1;
1086         msg.flags = client->flags;
1087         msg.scl_rate = scl_rate;
1088
1089         ret = i2c_transfer(adap, &msg, 1);
1090
1091         return ret;
1092 }
1093
1094 static int rk1000_control_probe(struct i2c_client *client,
1095                         const struct i2c_device_id *id)
1096 {
1097         int ret;
1098         char data[4] = {0x88, 0x0d, 0x22, 0x00};
1099 //      reg[0x00] = 0x88, --> ADC_CON
1100 //      reg[0x01] = 0x0d, --> CODEC_CON
1101 //      reg[0x02] = 0x22, --> I2C_CON
1102 //      reg[0x03] = 0x00, --> TVE_CON
1103         #ifdef CONFIG_SND_SOC_RK1000
1104     data[1] = 0x00;
1105     #endif
1106
1107         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1108         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
1109         {
1110                 dev_err(&client->dev, "i2c bus does not support the rk1000_control\n");
1111                 return -EIO;
1112         }
1113
1114         msleep(50);
1115         ret = reg_send_data(client, 0x00, data, 4, 100 * 1000);
1116 #if 1
1117     printk("i2c write ret = 0x%x\n",ret);
1118         memset(data,0,sizeof(data));
1119     ret = i2c_master_reg8_recv(client, 0, data, (int)4, 20*1000);
1120     printk("i2c read reg    %x,   %x,   %x,  %x   ret=x%x\n",data[0],data[1],data[2],data[3],ret);
1121 #endif
1122
1123         if (ret > 0)
1124                 ret = 0;
1125
1126         return ret;
1127 }
1128
1129 static int rk1000_control_remove(struct i2c_client *client)
1130 {
1131         return 0;
1132 }
1133
1134 static const struct i2c_device_id rk1000_control_id[] = {
1135         { "rk1000_control", 0 },
1136         { }
1137 };
1138 MODULE_DEVICE_TABLE(i2c, rk1000_control_id);
1139
1140 static struct i2c_driver rk1000_control_driver = {
1141         .driver = {
1142                 .name = "rk1000_control",
1143         },
1144         .probe = rk1000_control_probe,
1145         .remove = rk1000_control_remove,
1146         .id_table = rk1000_control_id,
1147 };
1148
1149 static int __init rk1000_control_init(void)
1150 {
1151         return i2c_add_driver(&rk1000_control_driver);
1152 }
1153
1154 static void __exit rk1000_control_exit(void)
1155 {
1156         i2c_del_driver(&rk1000_control_driver);
1157 }
1158
1159 module_init(rk1000_control_init);
1160 module_exit(rk1000_control_exit);
1161
1162 MODULE_DESCRIPTION("ASoC RK1000 CODEC driver");
1163 MODULE_AUTHOR("lhh lhh@rock-chips.com");
1164 MODULE_LICENSE("GPL");
1165 #endif