sound/soc/codecs/rk1000_codec.c

   1 /*
   2  * rk1000.c -- RK1000 ALSA SoC audio driver
   3  *
   4  * Copyright (C) 2009 rockchip lhh
   5  *
   6  *
   7  * Based on RK1000.c
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <sound/core.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/soc.h>
  25 #include <sound/soc-dapm.h>
  26 #include <sound/initval.h>
  27 #include <mach/gpio.h>
  28 #include <mach/iomux.h>
  29
  30 #include "rk1000_codec.h"
  31
  32 /*
  33  * Debug
  34  */
  35 #if 0
  36 #define DBG(x...)       printk(KERN_INFO x)
  37 #else
  38 #define DBG(x...)
  39 #endif
  40
  41 #define err(format, arg...) \
  42         printk(KERN_ERR AUDIO_NAME ": " format "\n" , ## arg)
  43 #define info(format, arg...) \
  44         printk(KERN_INFO AUDIO_NAME ": " format "\n" , ## arg)
  45
  46 #define OUT_CAPLESS  (0)   //ÊÇ·ñÎªÎÞµçÈÝÊä³ö£¬1:ÎÞµçÈÝÊä³ö£¬0:ÓÐµçÈÝÊä³ö
  47
  48 ///static u32 gVolReg = 0x0f;  ///0x0f; //ÓÃÓÚ¼ÇÂ¼ÒôÁ¿¼Ä´æÆ÷
  49 //static u32 gCodecVol = 0x0f;
  50 static u8 gR0AReg = 0;  //ÓÃÓÚ¼ÇÂ¼R0A¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚ¸Ä±ä²ÉÑùÂÊÇ°Í¨¹ýR0AÍ£Ö¹clk
  51 static u8 gR0BReg = 0;  //ÓÃÓÚ¼ÇÂ¼R0B¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚ¸Ä±ä²ÉÑùÂÊÇ°Í¨¹ýR0BÍ£Ö¹interplateºÍdecimation
  52 static u8 gR1314Reg = 0;  //ÓÃÓÚ¼ÇÂ¼R13,R14¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚFMÒôÁ¿Îª0Ê±
  53
  54 /*
  55  * rk1000 register cache
  56  * We can't read the RK1000 register space when we
  57  * are using 2 wire for device control, so we cache them instead.
  58  */
  59 static const u16 rk1000_codec_reg[] = {
  60         0x0005, 0x0004, 0x00fd, 0x00f3,  /*  0 */
  61         0x0003, 0x0000, 0x0000, 0x0000,  /*  4 */
  62         0x0000, 0x0005, 0x0000, 0x0000,  /*  8 */
  63         0x0097, 0x0097, 0x0097, 0x0097,  /* 12 */
  64         0x0097, 0x0097, 0x00cc, 0x0000,  /* 16 */
  65         0x0000, 0x00f1, 0x0090, 0x00ff,  /* 20 */
  66         0x00ff, 0x00ff, 0x009c, 0x0000,  /* 24 */
  67         0x0000, 0x00ff, 0x00ff, 0x00ff,  /* 28 */
  68 };
  69
  70
  71 /* codec private data */
  72 struct rk1000_codec_priv {
  73         unsigned int sysclk;
  74         struct snd_soc_codec codec;
  75         struct snd_pcm_hw_constraint_list *sysclk_constraints;
  76         u16 reg_cache[RK1000_CODEC_NUM_REG];
  77 };
  78
  79 /*
  80  * read rk1000 register cache
  81  */
  82 static inline unsigned int rk1000_codec_read_reg_cache(struct snd_soc_codec *codec,
  83         unsigned int reg)
  84 {
  85         u16 *cache = codec->reg_cache;
  86         if (reg > RK1000_CACHE_REGNUM)
  87                 return -1;
  88         return cache[reg];
  89 }
  90
  91 static unsigned int rk1000_codec_read(struct snd_soc_codec *codec, unsigned int r)
  92 {
  93         struct i2c_msg xfer[1];
  94         u8 reg = r;
  95         int ret;
  96         struct i2c_client *client = codec->control_data;
  97
  98         /* Read register */
  99         xfer[0].addr = (client->addr& 0x60)|(reg);
 100         xfer[0].flags = I2C_M_RD;
 101         xfer[0].len = 1;
 102         xfer[0].buf = &reg;
 103
 104         ret = i2c_transfer(client->adapter, xfer, 1);
 105         if (ret != 1) {
 106                 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
 107                 return 0;
 108         }
 109
 110         return reg;
 111 }
 112 /*
 113  * write rk1000 register cache
 114  */
 115 static inline void rk1000_codec_write_reg_cache(struct snd_soc_codec *codec,
 116         unsigned int reg, unsigned int value)
 117 {
 118         u16 *cache = codec->reg_cache;
 119         if (reg > RK1000_CACHE_REGNUM)
 120                 return;
 121         cache[reg] = value;
 122 }
 123
 124 static int rk1000_codec_write(struct snd_soc_codec *codec, unsigned int reg,
 125         unsigned int value)
 126 {
 127         u8 data[2];
 128         struct i2c_client *i2c;
 129         DBG("Enter::%s, %d, reg=0x%02X, value=0x%02X\n",__FUNCTION__,__LINE__, reg, value);
 130         data[0] = value & 0x00ff;
 131         rk1000_codec_write_reg_cache (codec, reg, value);
 132         i2c = (struct i2c_client *)codec->control_data;
 133         i2c->addr = (i2c->addr & 0x60)|reg;
 134         if (codec->hw_write(codec->control_data, data, 1) == 1){
 135                 DBG("================%s Run OK================\n",__FUNCTION__,__LINE__);
 136                 return 0;
 137         }else{
 138                 DBG("================%s Run EIO================\n",__FUNCTION__,__LINE__);
 139                 return -EIO;
 140         }
 141 }
 142
 143 static const struct snd_kcontrol_new rk1000_codec_snd_controls[] = {
 144
 145 SOC_DOUBLE_R("Capture Volume", ACCELCODEC_R0C, ACCELCODEC_R0D, 0, 15, 0),
 146 SOC_DOUBLE_R("Capture Switch", ACCELCODEC_R0C, ACCELCODEC_R0D, 7, 1, 1),
 147
 148 SOC_DOUBLE_R("PCM Volume", ACCELCODEC_R0D, ACCELCODEC_R0E, 0, 7, 0),
 149
 150 //SOC_SINGLE("Left ADC Capture Volume", ACCELCODEC_R17, 0, 63, 0),
 151 //SOC_SINGLE("Right ADC Capture Volume", ACCELCODEC_R18, 0, 63, 0),
 152
 153
 154 };
 155
 156
 157 /* Left Mixer */
 158 static const struct snd_kcontrol_new rk1000_codec_left_mixer_controls[] = {
 159 SOC_DAPM_SINGLE("Playback Switch", ACCELCODEC_R15, 6, 1, 0),
 160 SOC_DAPM_SINGLE("Left Bypass Switch", ACCELCODEC_R15, 2, 1, 0),
 161
 162 };
 163
 164 /* Right Mixer */
 165 static const struct snd_kcontrol_new rk1000_codec_right_mixer_controls[] = {
 166 SOC_DAPM_SINGLE("Playback Switch", ACCELCODEC_R15, 7, 1, 0),
 167 SOC_DAPM_SINGLE("Left Bypass Switch", ACCELCODEC_R15, 3, 1, 0),
 168
 169 };
 170
 171
 172 static const struct snd_soc_dapm_widget rk1000_codec_dapm_widgets[] = {
 173         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
 174                 &rk1000_codec_left_mixer_controls[0],
 175                 ARRAY_SIZE(rk1000_codec_left_mixer_controls)),
 176         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
 177                 &rk1000_codec_right_mixer_controls[0],
 178                 ARRAY_SIZE(rk1000_codec_right_mixer_controls)),
 179
 180         //SND_SOC_DAPM_PGA("Right Out 1", ACCELCODEC_R1E, 0, 0, NULL, 0),
 181         //SND_SOC_DAPM_PGA("Left Out 1", ACCELCODEC_R1E, 1, 0, NULL, 0),
 182         //SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ACCELCODEC_R1F, 1, 0),
 183         //SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ACCELCODEC_R1F, 2, 0),
 184
 185         SND_SOC_DAPM_ADC("ADC", "Capture", ACCELCODEC_R1D, 6, 1),
 186         SND_SOC_DAPM_ADC("ADC BUFF", "Capture BUFF", ACCELCODEC_R1D, 2, 0),
 187
 188
 189         SND_SOC_DAPM_OUTPUT("LOUT1"),
 190         SND_SOC_DAPM_OUTPUT("ROUT1"),
 191
 192         SND_SOC_DAPM_INPUT("LINPUT1"),
 193         SND_SOC_DAPM_INPUT("RINPUT1"),
 194 };
 195
 196 static const struct snd_soc_dapm_route audio_map[] = {
 197         /* left mixer */
 198         {"Left Mixer", "Playback Switch", "Left DAC"},
 199         {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
 200         {"Right Mixer", "Playback Switch", "Right DAC"},
 201         {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
 202
 203         /* left out 1 */
 204         {"Left Out 1", NULL, "Left Mixer"},
 205         {"LOUT1", NULL, "Left Out 1"},
 206
 207
 208         /* right out 1 */
 209         {"Right Out 1", NULL, "Right Mixer"},
 210         {"ROUT1", NULL, "Right Out 1"},
 211
 212         /* Left Line Mux */
 213         {"Left Line Mux", "Line 1", "LINPUT1"},
 214         {"Left Line Mux", "PGA", "Left PGA Mux"},
 215         {"Left Line Mux", "Differential", "Differential Mux"},
 216
 217         /* Right Line Mux */
 218         {"Right Line Mux", "Line 1", "RINPUT1"},
 219         {"Right Line Mux", "PGA", "Right PGA Mux"},
 220         {"Right Line Mux", "Differential", "Differential Mux"},
 221
 222         /* Left PGA Mux */
 223         {"Left PGA Mux", "Line 1", "LINPUT1"},
 224         {"Left PGA Mux", "Line 2", "LINPUT2"},
 225         {"Left PGA Mux", "Line 3", "LINPUT3"},
 226         {"Left PGA Mux", "Differential", "Differential Mux"},
 227
 228         /* Right PGA Mux */
 229         {"Right PGA Mux", "Line 1", "RINPUT1"},
 230         {"Right PGA Mux", "Differential", "Differential Mux"},
 231
 232         /* Differential Mux */
 233         {"Differential Mux", "Line 1", "LINPUT1"},
 234         {"Differential Mux", "Line 1", "RINPUT1"},
 235
 236         /* Left ADC Mux */
 237         {"Left ADC Mux", "Stereo", "Left PGA Mux"},
 238         {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
 239         {"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
 240
 241         /* Right ADC Mux */
 242         {"Right ADC Mux", "Stereo", "Right PGA Mux"},
 243         {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
 244         {"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
 245
 246         /* ADC */
 247         {"Left ADC", NULL, "Left ADC Mux"},
 248         {"Right ADC", NULL, "Right ADC Mux"},
 249
 250         /* terminator */
 251         {NULL, NULL, NULL},
 252 };
 253
 254 struct _coeff_div {
 255         u32 mclk;
 256         u32 rate;
 257         u16 fs;
 258         u8 sr:5;
 259         u8 usb:1;
 260         u8 bclk;
 261 };
 262
 263 /* codec hifi mclk clock divider coefficients */
 264 static const struct _coeff_div coeff_div[] = {
 265         /* 8k */
 266         {12288000, 8000, 1536, 0x6, 0x0,ASC_BCLKDIV_16},
 267         {11289600, 8000, 1408, 0x16, 0x0,ASC_BCLKDIV_16},
 268         {18432000, 8000, 2304, 0x7, 0x0,ASC_BCLKDIV_16},
 269         {16934400, 8000, 2112, 0x17, 0x0,ASC_BCLKDIV_16},
 270         {8192000, 8000, 1024, 0x0, 0x0,ASC_BCLKDIV_16},
 271         {12000000, 8000, 1500, 0x6, 0x1,ASC_BCLKDIV_16},
 272
 273         /* 11.025k */
 274         {11289600, 11025, 1024, 0x18, 0x0,ASC_BCLKDIV_16},
 275         {16934400, 11025, 1536, 0x19, 0x0,ASC_BCLKDIV_16},
 276         {12000000, 11025, 1088, 0x19, 0x1,ASC_BCLKDIV_16},
 277
 278     /* 12k */
 279         {12288000, 12000, 1024, 0x8, 0x0,ASC_BCLKDIV_16},
 280         {18432000, 12000, 1536, 0x9, 0x0,ASC_BCLKDIV_16},
 281         {12000000, 12000, 1000, 0x8, 0x1,ASC_BCLKDIV_16},
 282
 283         /* 16k */
 284         {12288000, 16000, 768, 0xa, 0x0,ASC_BCLKDIV_8},
 285         {18432000, 16000, 1152, 0xb, 0x0,ASC_BCLKDIV_8},
 286         {12000000, 16000, 750, 0xa, 0x1,ASC_BCLKDIV_8},
 287
 288         /* 22.05k */
 289         {11289600, 22050, 512, 0x1a, 0x0,ASC_BCLKDIV_8},
 290         {16934400, 22050, 768, 0x1b, 0x0,ASC_BCLKDIV_8},
 291         {12000000, 22050, 544, 0x1b, 0x1,ASC_BCLKDIV_8},
 292
 293     /* 24k */
 294         {12288000, 24000, 512, 0x1c, 0x0,ASC_BCLKDIV_8},
 295         {18432000, 24000, 768, 0x1d, 0x0,ASC_BCLKDIV_8},
 296         {12000000, 24000, 500, 0x1c, 0x1,ASC_BCLKDIV_8},
 297
 298         /* 32k */
 299         {12288000, 32000, 384, 0xc, 0x0,ASC_BCLKDIV_8},
 300         {18432000, 32000, 576, 0xd, 0x0,ASC_BCLKDIV_8},
 301         {12000000, 32000, 375, 0xa, 0x1,ASC_BCLKDIV_8},
 302
 303         /* 44.1k */
 304         {11289600, 44100, 256, 0x10, 0x0,ASC_BCLKDIV_8},
 305         {16934400, 44100, 384, 0x11, 0x0,ASC_BCLKDIV_8},
 306         {12000000, 44100, 272, 0x11, 0x1,ASC_BCLKDIV_8},
 307
 308         /* 48k */
 309         {12288000, 48000, 256, 0x0, 0x0,ASC_BCLKDIV_4},
 310         {18432000, 48000, 384, 0x1, 0x0,ASC_BCLKDIV_4},
 311         {12000000, 48000, 250, 0x0, 0x1,ASC_BCLKDIV_4},
 312
 313         /* 88.2k */
 314         {11289600, 88200, 128, 0x1e, 0x0,ASC_BCLKDIV_4},
 315         {16934400, 88200, 192, 0x1f, 0x0,ASC_BCLKDIV_4},
 316         {12000000, 88200, 136, 0x1f, 0x1,ASC_BCLKDIV_4},
 317
 318         /* 96k */
 319         {12288000, 96000, 128, 0xe, 0x0,ASC_BCLKDIV_4},
 320         {18432000, 96000, 192, 0xf, 0x0,ASC_BCLKDIV_4},
 321         {12000000, 96000, 125, 0xe, 0x1,ASC_BCLKDIV_4},
 322 };
 323
 324 static inline int get_coeff(int mclk, int rate)
 325 {
 326         int i;
 327
 328         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
 329                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
 330                         return i;
 331         }
 332
 333         return -EINVAL;
 334 }
 335
 336 /* The set of rates we can generate from the above for each SYSCLK */
 337
 338 static unsigned int rates_12288[] = {
 339         8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
 340 };
 341
 342 static struct snd_pcm_hw_constraint_list constraints_12288 = {
 343         .count  = ARRAY_SIZE(rates_12288),
 344         .list   = rates_12288,
 345 };
 346
 347 static unsigned int rates_112896[] = {
 348         8000, 11025, 22050, 44100,
 349 };
 350
 351 static struct snd_pcm_hw_constraint_list constraints_112896 = {
 352         .count  = ARRAY_SIZE(rates_112896),
 353         .list   = rates_112896,
 354 };
 355
 356 static unsigned int rates_12[] = {
 357         8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
 358         48000, 88235, 96000,
 359 };
 360
 361 static struct snd_pcm_hw_constraint_list constraints_12 = {
 362         .count  = ARRAY_SIZE(rates_12),
 363         .list   = rates_12,
 364 };
 365
 366 /*
 367  * Note that this should be called from init rather than from hw_params.
 368  */
 369 static int rk1000_codec_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 370                 int clk_id, unsigned int freq, int dir)
 371 {
 372         struct snd_soc_codec *codec = codec_dai->codec;
 373         struct rk1000_codec_priv *rk1000_codec = codec->private_data;
 374
 375         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 376
 377         switch (freq) {
 378         case 11289600:
 379         case 18432000:
 380         case 22579200:
 381         case 36864000:
 382                 rk1000_codec->sysclk_constraints = &constraints_112896;
 383                 rk1000_codec->sysclk = freq;
 384                 return 0;
 385
 386         case 12288000:
 387         case 16934400:
 388         case 24576000:
 389         case 33868800:
 390                 rk1000_codec->sysclk_constraints = &constraints_12288;
 391                 rk1000_codec->sysclk = freq;
 392                 return 0;
 393
 394         case 12000000:
 395         case 24000000:
 396                 rk1000_codec->sysclk_constraints = &constraints_12;
 397                 rk1000_codec->sysclk = freq;
 398                 return 0;
 399         }
 400         return -EINVAL;
 401 }
 402
 403 static int rk1000_codec_set_dai_fmt(struct snd_soc_dai *codec_dai,
 404                 unsigned int fmt)
 405 {
 406         struct snd_soc_codec *codec = codec_dai->codec;
 407         u16 iface = 0;
 408
 409         /* set master/slave audio interface */
 410         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 411         case SND_SOC_DAIFMT_CBM_CFM:
 412                 iface = 0x0040;
 413                 break;
 414         case SND_SOC_DAIFMT_CBS_CFS:
 415                 iface = 0x0020;
 416                 break;
 417         default:
 418                 return -EINVAL;
 419         }
 420
 421         /* interface format */
 422         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 423         case SND_SOC_DAIFMT_I2S:
 424                 iface |= 0x0002;
 425                 break;
 426         case SND_SOC_DAIFMT_RIGHT_J:
 427                 break;
 428         case SND_SOC_DAIFMT_LEFT_J:
 429                 iface |= 0x0001;
 430                 break;
 431         case SND_SOC_DAIFMT_DSP_A:
 432                 iface |= 0x0003;
 433                 break;
 434         case SND_SOC_DAIFMT_DSP_B:
 435                 iface |= 0x0013;
 436                 break;
 437         default:
 438                 return -EINVAL;
 439         }
 440
 441         /* clock inversion */
 442         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 443         case SND_SOC_DAIFMT_NB_NF:
 444                 break;
 445         case SND_SOC_DAIFMT_IB_IF:
 446                 iface |= 0x0090;
 447                 break;
 448         case SND_SOC_DAIFMT_IB_NF:
 449                 iface |= 0x0080;
 450                 break;
 451         case SND_SOC_DAIFMT_NB_IF:
 452                 iface |= 0x0010;
 453                 break;
 454         default:
 455                 return -EINVAL;
 456         }
 457
 458         DBG("Enter::%s----%d  iface=%x\n",__FUNCTION__,__LINE__,iface);
 459         rk1000_codec_write(codec, ACCELCODEC_R09, iface);
 460         return 0;
 461 }
 462
 463 static int rk1000_codec_pcm_startup(struct snd_pcm_substream *substream,
 464                               struct snd_soc_dai *dai)
 465 {
 466         struct snd_soc_codec *codec = dai->codec;
 467         struct rk1000_codec_priv *rk1000_codec = codec->private_data;
 468
 469         /* The set of sample rates that can be supported depends on the
 470          * MCLK supplied to the CODEC - enforce this.
 471          */
 472         DBG("Enter::%s----%d  rk1000_codec->sysclk=%d\n",__FUNCTION__,__LINE__,rk1000_codec->sysclk);
 473         if (!rk1000_codec->sysclk) {
 474                 dev_err(codec->dev,
 475                         "No MCLK configured, call set_sysclk() on init\n");
 476                 return -EINVAL;
 477         }
 478
 479         snd_pcm_hw_constraint_list(substream->runtime, 0,
 480                                    SNDRV_PCM_HW_PARAM_RATE,
 481                                    rk1000_codec->sysclk_constraints);
 482
 483         return 0;
 484 }
 485
 486 static int rk1000_codec_pcm_hw_params(struct snd_pcm_substream *substream,
 487                                 struct snd_pcm_hw_params *params,
 488                                 struct snd_soc_dai *dai)
 489 {
 490         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 491         struct snd_soc_device *socdev = rtd->socdev;
 492         struct snd_soc_codec *codec = socdev->card->codec;
 493         struct rk1000_codec_priv *rk1000_codec = codec->private_data;
 494         u16 iface = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R09) & 0x1f3;
 495         u16 srate = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R00) & 0x180;
 496         int coeff;
 497
 498         /*by Vincent Hsiung for EQ Vol Change*/
 499         #define HW_PARAMS_FLAG_EQVOL_ON 0x21
 500         #define HW_PARAMS_FLAG_EQVOL_OFF 0x22
 501         if (params->flags == HW_PARAMS_FLAG_EQVOL_ON)
 502         {
 503                 u16 r17 = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R17);
 504                 u16 r18 = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R18);
 505
 506                 r17 &= (~0x3f); //6db
 507                 r18 &= (~0x3f); //6db
 508
 509                 rk1000_codec_write(codec, ACCELCODEC_R17, r17);
 510                 rk1000_codec_write(codec, ACCELCODEC_R18, r18);
 511
 512                 return 0;
 513         }
 514         else if (params->flags == HW_PARAMS_FLAG_EQVOL_OFF)
 515         {
 516                 u16 r17 = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R17);
 517                 u16 r18 = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R18);
 518
 519                 r17 &= (~0x3f);
 520                 r17 |= 0x0f; //0db
 521
 522                 r18 &= (~0x3f);
 523                 r18 |= 0x0f; //0db
 524
 525                 rk1000_codec_write(codec, ACCELCODEC_R17, r17);
 526                 rk1000_codec_write(codec, ACCELCODEC_R18, r18);
 527                 return 0;
 528         }
 529
 530         coeff = get_coeff(rk1000_codec->sysclk, params_rate(params));
 531
 532         /* bit size */
 533         switch (params_format(params)) {
 534         case SNDRV_PCM_FORMAT_S16_LE:
 535                 break;
 536         case SNDRV_PCM_FORMAT_S20_3LE:
 537                 iface |= 0x0004;
 538                 break;
 539         case SNDRV_PCM_FORMAT_S24_LE:
 540                 iface |= 0x0008;
 541                 break;
 542         case SNDRV_PCM_FORMAT_S32_LE:
 543                 iface |= 0x000c;
 544                 break;
 545         }
 546         DBG("Enter::%s----%d  iface=%x srate =%x rate=%d\n",__FUNCTION__,__LINE__,iface,srate,params_rate(params));
 547
 548         rk1000_codec_write(codec,ACCELCODEC_R0C, 0x17);
 549         rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);   //soft mute
 550         //±ØÐëÏÈ½«clkºÍEN_INT¶¼disableµô£¬·ñÔòÇÐ»»bclk·ÖÆµÖµ¿ÉÄÜµ¼ÖÂcodecÄÚ²¿Ê±Ðò»ìÂÒµô£¬
 551         //±íÏÖ³öÀ´µÄÏÖÏóÊÇ£¬ÒÔºóµÄÒôÀÖ¶¼±ä³ÉÁËÔëÒô£¬¶øÇÒ¾ÍËã°ÑÊäÈëcodecµÄI2S_DATAOUT¶Ï¿ªÒ²Ò»Ñù³öÔëÒô
 552         rk1000_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_DISABLE|ASC_INT_DISABLE);  //0x00
 553
 554         /* set iface & srate */
 555         rk1000_codec_write(codec, ACCELCODEC_R09, iface);
 556         if (coeff >= 0){
 557                 rk1000_codec_write(codec, ACCELCODEC_R0A, (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb|ASC_CLKNODIV|ASC_CLK_ENABLE);
 558                 rk1000_codec_write(codec, ACCELCODEC_R00, srate|coeff_div[coeff].bclk);
 559         }
 560         rk1000_codec_write(codec,ACCELCODEC_R0B, gR0BReg);
 561         return 0;
 562 }
 563
 564 void PhaseOut(struct snd_soc_codec *codec,u32 nStep, u32 us)
 565 {
 566         DBG("%s[%d]\n",__FUNCTION__,__LINE__);
 567         rk1000_codec_write(codec,ACCELCODEC_R17, 0x0F|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOL
 568         rk1000_codec_write(codec,ACCELCODEC_R18, 0x0F|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOR
 569         udelay(us);
 570 }
 571
 572 void PhaseIn(struct snd_soc_codec *codec,u32 nStep, u32 us)
 573 {
 574         DBG("%s[%d]\n",__FUNCTION__,__LINE__);
 575         rk1000_codec_write(codec,ACCELCODEC_R17, 0x0f|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOL gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOL
 576         rk1000_codec_write(codec,ACCELCODEC_R18, 0x0f|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOR
 577         udelay(us);
 578 }
 579
 580 static int rk1000_codec_mute(struct snd_soc_dai *dai, int mute)
 581 {
 582         struct snd_soc_codec *codec = dai->codec;
 583
 584         DBG("Enter::%s----%d--mute=%d\n",__FUNCTION__,__LINE__,mute);
 585
 586         if (mute){
 587                 PhaseOut(codec,1, 5000);
 588                 rk1000_codec_write(codec,ACCELCODEC_R19, 0xFF);  //AOM
 589                 rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);  //soft mute
 590         }else{
 591                 rk1000_codec_write(codec,ACCELCODEC_R1D, 0x2a);  //setup Vmid and Vref, other module power down
 592                 rk1000_codec_write(codec,ACCELCODEC_R1E, 0x40);  ///|ASC_PDASDML_ENABLE);
 593                 rk1000_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE);  ///|ASC_PDMICB_ENABLE|ASC_PDMIXM_ENABLE);
 594                 PhaseIn(codec,1, 5000);
 595                 ///if(gCodecVol != 0){
 596                 rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_ACTIVE_L|ASC_INT_ACTIVE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);
 597                 //}
 598                 rk1000_codec_write(codec,ACCELCODEC_R19, 0x7F);  //AOM
 599                 #if 0
 600                 /*disable speaker */
 601                 rockchip_mux_api_set(SPK_IOMUX_PIN_NAME, SPK_IOMUX_PIN_DIR);
 602                 GPIOSetPinDirection(SPK_CTRL_PIN,GPIO_OUT);
 603                 GPIOSetPinLevel(SPK_CTRL_PIN,GPIO_HIGH);
 604                 #endif
 605         }
 606         return 0;
 607 }
 608
 609 static int rk1000_codec_set_bias_level(struct snd_soc_codec *codec,
 610                                  enum snd_soc_bias_level level)
 611 {
 612         u16 pwr_reg = rk1000_codec_read_reg_cache(codec, ACCELCODEC_R1D) & ~0x1c1;
 613         DBG("Enter::%s----%d level =%d\n",__FUNCTION__,__LINE__,level);
 614         switch (level) {
 615         case SND_SOC_BIAS_ON:
 616                 break;
 617
 618         case SND_SOC_BIAS_PREPARE:
 619                 /* VREF, VMID=2x50k, digital enabled */
 620                 rk1000_codec_write(codec, ACCELCODEC_R1D, pwr_reg | 0x0080);
 621                 break;
 622
 623         case SND_SOC_BIAS_STANDBY:
 624                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 625                         /* VREF, VMID=2x5k */
 626                         rk1000_codec_write(codec, ACCELCODEC_R1D, pwr_reg | 0x0080);
 627
 628                         /* Charge caps */
 629                         msleep(100);
 630                 }
 631
 632                 /* VREF, VMID=2*500k, digital stopped */
 633                 rk1000_codec_write(codec, ACCELCODEC_R1D, pwr_reg | 0x0080);
 634                 break;
 635
 636         case SND_SOC_BIAS_OFF:
 637                 rk1000_codec_write(codec, ACCELCODEC_R1D, 0x0000);
 638                 break;
 639         }
 640         codec->bias_level = level;
 641         return 0;
 642 }
 643
 644 #define RK1000_CODEC_RATES SNDRV_PCM_RATE_8000_96000
 645
 646 #define RK1000_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 647         SNDRV_PCM_FMTBIT_S24_LE)
 648
 649 static struct snd_soc_dai_ops rk1000_codec_ops = {
 650         .startup = rk1000_codec_pcm_startup,
 651         .hw_params = rk1000_codec_pcm_hw_params,
 652         .set_fmt = rk1000_codec_set_dai_fmt,
 653         .set_sysclk = rk1000_codec_set_dai_sysclk,
 654         .digital_mute = rk1000_codec_mute,
 655 };
 656
 657 struct snd_soc_dai rk1000_codec_dai = {
 658         .name = "rk1000_codec",
 659         .playback = {
 660                 .stream_name = "Playback",
 661                 .channels_min = 1,
 662                 .channels_max = 2,
 663                 .rates = RK1000_CODEC_RATES,
 664                 .formats = RK1000_CODEC_FORMATS,
 665         },
 666         .capture = {
 667                 .stream_name = "Capture",
 668                 .channels_min = 1,
 669                 .channels_max = 2,
 670                 .rates = RK1000_CODEC_RATES,
 671                 .formats = RK1000_CODEC_FORMATS,
 672          },
 673         .ops = &rk1000_codec_ops,
 674         .symmetric_rates = 1,
 675 };
 676 EXPORT_SYMBOL_GPL(rk1000_codec_dai);
 677
 678 static int rk1000_codec_suspend(struct platform_device *pdev, pm_message_t state)
 679 {
 680         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 681         struct snd_soc_codec *codec = socdev->card->codec;
 682         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 683         rk1000_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
 684         return 0;
 685 }
 686
 687 static int rk1000_codec_resume(struct platform_device *pdev)
 688 {
 689         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 690         struct snd_soc_codec *codec = socdev->card->codec;
 691         int i;
 692         u8 data[2];
 693         struct i2c_client *i2c;
 694         u16 *cache = codec->reg_cache;
 695
 696         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 697         /* Sync reg_cache with the hardware */
 698         for (i = 0; i < RK1000_CODEC_NUM_REG; i++) {
 699                 data[0] = cache[i] & 0x00ff;
 700                 i2c = (struct i2c_client *)codec->control_data;
 701                 i2c->addr = (i2c->addr & 0x60)|i;
 702                 codec->hw_write(codec->control_data, data, 1);
 703         }
 704
 705         rk1000_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 706
 707         return 0;
 708 }
 709
 710 static struct snd_soc_codec *rk1000_codec_codec;
 711
 712 static int rk1000_codec_probe(struct platform_device *pdev)
 713 {
 714         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 715         struct snd_soc_codec *codec;
 716         int ret = 0;
 717
 718         if (rk1000_codec_codec == NULL) {
 719                 dev_err(&pdev->dev, "Codec device not registered\n");
 720                 return -ENODEV;
 721         }
 722
 723         socdev->card->codec = rk1000_codec_codec;
 724         codec = rk1000_codec_codec;
 725
 726         /* register pcms */
 727         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
 728         if (ret < 0) {
 729                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
 730                 goto pcm_err;
 731         }
 732
 733         snd_soc_add_controls(codec, rk1000_codec_snd_controls,
 734                                 ARRAY_SIZE(rk1000_codec_snd_controls));
 735         snd_soc_dapm_new_controls(codec, rk1000_codec_dapm_widgets,
 736                                   ARRAY_SIZE(rk1000_codec_dapm_widgets));
 737         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 738         snd_soc_dapm_new_widgets(codec);
 739
 740         ret = snd_soc_init_card(socdev);
 741         if (ret < 0) {
 742                 dev_err(codec->dev, "failed to register card: %d\n", ret);
 743                 goto card_err;
 744         }
 745
 746         return ret;
 747
 748 card_err:
 749         snd_soc_free_pcms(socdev);
 750         snd_soc_dapm_free(socdev);
 751 pcm_err:
 752         return ret;
 753 }
 754
 755 static int rk1000_codec_remove(struct platform_device *pdev)
 756 {
 757         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 758         snd_soc_free_pcms(socdev);
 759         snd_soc_dapm_free(socdev);
 760         return 0;
 761 }
 762
 763 struct snd_soc_codec_device soc_codec_dev_rk1000_codec = {
 764         .probe =        rk1000_codec_probe,
 765         .remove =       rk1000_codec_remove,
 766         .suspend =      rk1000_codec_suspend,
 767         .resume =       rk1000_codec_resume,
 768 };
 769 EXPORT_SYMBOL_GPL(soc_codec_dev_rk1000_codec);
 770
 771 static int rk1000_codec_register(struct rk1000_codec_priv *rk1000_codec,
 772                            enum snd_soc_control_type control)
 773 {
 774         struct snd_soc_codec *codec = &rk1000_codec->codec;
 775         int ret;
 776
 777         if (rk1000_codec_codec) {
 778                 dev_err(codec->dev, "Another rk1000 codec is registered\n");
 779                 ret = -EINVAL;
 780                 goto err;
 781         }
 782         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 783         mutex_init(&codec->mutex);
 784         INIT_LIST_HEAD(&codec->dapm_widgets);
 785         INIT_LIST_HEAD(&codec->dapm_paths);
 786
 787         codec->private_data = rk1000_codec;
 788         codec->name = "RK1000_CODEC";
 789         codec->owner = THIS_MODULE;
 790         codec->dai = &rk1000_codec_dai;
 791         codec->num_dai = 1;
 792         codec->reg_cache_size = ARRAY_SIZE(rk1000_codec->reg_cache);
 793         codec->reg_cache = &rk1000_codec->reg_cache;
 794         codec->bias_level = SND_SOC_BIAS_OFF;
 795         codec->set_bias_level = rk1000_codec_set_bias_level;
 796
 797         memcpy(codec->reg_cache, rk1000_codec_reg,
 798                sizeof(rk1000_codec_reg));
 799
 800         codec->write = rk1000_codec_write;
 801         codec->read = rk1000_codec_read;
 802         codec->hw_write = (hw_write_t)i2c_master_send;
 803
 804         //ret = snd_soc_codec_set_cache_io(codec, 0, 8, control);
 805         //if (ret < 0) {
 806                 //dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 807                 //goto err;
 808         //}
 809
 810 #if 0   //fzf rk2818 is SPK_CTL
 811         gpio_request(RK2818_PIN_PF7, "rk1000_codec");
 812         rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_GPIO1_A3B7);
 813         gpio_direction_output(RK2818_PIN_PF7,GPIO_HIGH);
 814
 815 #endif
 816 #if 1
 817         rk1000_codec_write(codec,ACCELCODEC_R1D, 0x00);
 818     rk1000_codec_write(codec,ACCELCODEC_R17, 0xFF);  //AOL
 819     rk1000_codec_write(codec,ACCELCODEC_R18, 0xFF);  //AOR
 820     rk1000_codec_write(codec,ACCELCODEC_R19, 0xFF);  //AOM
 821
 822     rk1000_codec_write(codec,ACCELCODEC_R1F, 0xDF);
 823     mdelay(10);
 824     rk1000_codec_write(codec,ACCELCODEC_R1F, 0x5F);
 825     rk1000_codec_write(codec,ACCELCODEC_R19, 0x7F);  //AOM
 826     rk1000_codec_write(codec,ACCELCODEC_R15, 0xC1);//rk1000_codec_write(codec,ACCELCODEC_R15, 0xCD);//by Vincent Hsiung
 827     rk1000_codec_write(codec,ACCELCODEC_R1A, 0x1C);
 828     mdelay(100);
 829     rk1000_codec_write(codec,ACCELCODEC_R1F, 0x09);
 830     rk1000_codec_write(codec,ACCELCODEC_R1E, 0x00);
 831     mdelay(10);
 832     rk1000_codec_write(codec,ACCELCODEC_R1A, 0x14);
 833     rk1000_codec_write(codec,ACCELCODEC_R1D, 0xFE);
 834     rk1000_codec_write(codec,ACCELCODEC_R17, 0xBF);  //AOL
 835     rk1000_codec_write(codec,ACCELCODEC_R18, 0xBF);  //AOR
 836     rk1000_codec_write(codec,ACCELCODEC_R19, 0x7F);  //AOM
 837     rk1000_codec_write(codec,ACCELCODEC_R1F, 0xDF);
 838
 839     //2soft mute
 840     rk1000_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);   //soft mute
 841
 842     //2set default SR and clk
 843     rk1000_codec_write(codec,ACCELCODEC_R0A, ASC_USB_MODE|FREQ48kHz|ASC_CLKNODIV|ASC_CLK_DISABLE);
 844     gR0AReg = ASC_USB_MODE|FREQ48kHz|ASC_CLKNODIV|ASC_CLK_DISABLE;
 845     //2Config audio  interface
 846     rk1000_codec_write(codec,ACCELCODEC_R09, ASC_I2S_MODE|ASC_16BIT_MODE|ASC_NORMAL_LRCLK|ASC_LRSWAP_DISABLE|ASC_MASTER_MODE|ASC_NORMAL_BCLK);
 847     rk1000_codec_write(codec,ACCELCODEC_R00, ASC_HPF_ENABLE|ASC_DSM_MODE_DISABLE|ASC_SCRAMBLE_ENABLE|ASC_DITHER_ENABLE|ASC_BCLKDIV_8);  //BCLK div 8
 848     //2volume,input,outpu
 849     rk1000_codec_write(codec,ACCELCODEC_R05, 0x0e);
 850     rk1000_codec_write(codec,ACCELCODEC_R06, 0x42);
 851     rk1000_codec_write(codec,ACCELCODEC_R07, 0x0e);
 852     rk1000_codec_write(codec,ACCELCODEC_R08, 0x42);
 853
 854     rk1000_codec_write(codec,ACCELCODEC_R0C, 0x10|ASC_INPUT_VOL_0DB|ASC_INPUT_MUTE);   //LIL
 855     rk1000_codec_write(codec,ACCELCODEC_R0D, 0x10|ASC_INPUT_VOL_0DB);   //LIR
 856     rk1000_codec_write(codec,ACCELCODEC_R0E, 0x10|ASC_INPUT_VOL_0DB);   //MIC
 857     rk1000_codec_write(codec,ACCELCODEC_R12, 0x4c|ASC_MIC_INPUT|ASC_MIC_BOOST_20DB);  //mic input and boost 20dB
 858     rk1000_codec_write(codec,ACCELCODEC_R13, ASC_LPGAMX_DISABLE|ASC_ALMX_DISABLE|((LINE_2_MIXER_GAIN & 0x7) << 4)|0x0);
 859     rk1000_codec_write(codec,ACCELCODEC_R14, ASC_RPGAMX_DISABLE|ASC_ARMX_DISABLE|((LINE_2_MIXER_GAIN & 0x7) << 4)|0x0);
 860     gR1314Reg = ASC_RPGAMX_DISABLE|ASC_ARMX_DISABLE|((LINE_2_MIXER_GAIN & 0x7) << 4)|0x0;
 861
 862     //2other
 863     rk1000_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_DISABLE|ASC_INT_DISABLE);  //0x00
 864     gR0BReg = ASC_DEC_DISABLE|ASC_INT_DISABLE;
 865     rk1000_codec_write(codec,ACCELCODEC_R15, \
 866                     0x01|ASC_RLPFMX_DISABLE|ASC_LLPFMX_DISABLE|ASC_LDAMX_DISABLE|ASC_RDAMX_DISABLE|ASC_LSCF_ACTIVE|ASC_RSCF_ACTIVE);  //0x3c
 867     rk1000_codec_write(codec,ACCELCODEC_R1B, 0x32);
 868     rk1000_codec_write(codec,ACCELCODEC_R1C, ASC_DEM_ENABLE);  ///0x00);  //use default value
 869
 870     ///dac mode
 871     rk1000_codec_write(codec,ACCELCODEC_R17, 0xBF);  //AOL  ÒôÁ¿×îµÍ
 872     rk1000_codec_write(codec,ACCELCODEC_R18, 0xBF);  //AOR
 873
 874     //2power down useless module
 875     rk1000_codec_write(codec,ACCELCODEC_R1D, 0x2a|ASC_PDSDL_ENABLE|ASC_PDBSTL_ENABLE|ASC_PDPGAL_ENABLE);  //setup Vmid and Vref, other module power down
 876     rk1000_codec_write(codec,ACCELCODEC_R1E, 0x40|ASC_PDASDML_ENABLE);
 877     #if OUT_CAPLESS
 878     rk1000_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMICB_ENABLE|ASC_PDMIXM_ENABLE);
 879     #else
 880     rk1000_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMICB_ENABLE|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE);
 881     #endif
 882
 883     //2other
 884     rk1000_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_DISABLE|ASC_INT_ENABLE);
 885     gR0BReg = ASC_DEC_ENABLE|ASC_INT_ENABLE;  //ASC_DEC_DISABLE|ASC_INT_ENABLE;
 886     rk1000_codec_write(codec,ACCELCODEC_R15, 0xC1);//rk1000_codec_write(codec,ACCELCODEC_R15, 0xCD);//by Vincent Hsiung
 887     rk1000_codec_write(codec,ACCELCODEC_R0C, 0x10|ASC_INPUT_VOL_0DB|ASC_INPUT_MUTE);   //LIL
 888     rk1000_codec_write(codec,ACCELCODEC_R0D, 0x10|ASC_INPUT_VOL_0DB);   //LIR
 889     rk1000_codec_write(codec,ACCELCODEC_R0E, 0x10|ASC_INPUT_VOL_0DB);   //MIC
 890     rk1000_codec_write(codec,ACCELCODEC_R12, 0x4c|ASC_MIC_INPUT|ASC_MIC_BOOST_20DB);  //mic input and boost 20dB
 891     rk1000_codec_write(codec,ACCELCODEC_R13, 0x00);
 892     rk1000_codec_write(codec,ACCELCODEC_R14, 0x00);
 893     gR1314Reg = 0x00;
 894     rk1000_codec_write(codec,ACCELCODEC_R1C, ASC_DEM_ENABLE);  //0x00);  //use default value
 895 #endif
 896
 897         rk1000_codec_set_bias_level(&rk1000_codec->codec, SND_SOC_BIAS_STANDBY);
 898
 899         rk1000_codec_dai.dev = codec->dev;
 900
 901         rk1000_codec_codec = codec;
 902
 903         ret = snd_soc_register_codec(codec);
 904         if (ret != 0) {
 905                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
 906                 goto err;
 907         }
 908
 909         ret = snd_soc_register_dai(&rk1000_codec_dai);
 910         if (ret != 0) {
 911                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
 912                 snd_soc_unregister_codec(codec);
 913                 goto err_codec;
 914         }
 915
 916         return 0;
 917
 918 err_codec:
 919         snd_soc_unregister_codec(codec);
 920 err:
 921         kfree(rk1000_codec);
 922         return ret;
 923 }
 924
 925 static void rk1000_codec_unregister(struct rk1000_codec_priv *rk1000_codec)
 926 {
 927         rk1000_codec_set_bias_level(&rk1000_codec->codec, SND_SOC_BIAS_OFF);
 928         snd_soc_unregister_dai(&rk1000_codec_dai);
 929         snd_soc_unregister_codec(&rk1000_codec->codec);
 930         kfree(rk1000_codec);
 931         rk1000_codec_codec = NULL;
 932 }
 933
 934 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 935 static int rk1000_codec_i2c_probe(struct i2c_client *i2c,
 936                             const struct i2c_device_id *id)
 937 {
 938         struct rk1000_codec_priv *rk1000_codec;
 939         struct snd_soc_codec *codec;
 940
 941         rk1000_codec = kzalloc(sizeof(struct rk1000_codec_priv), GFP_KERNEL);
 942         if (rk1000_codec == NULL)
 943                 return -ENOMEM;
 944
 945         codec = &rk1000_codec->codec;
 946
 947         i2c_set_clientdata(i2c, rk1000_codec);
 948         codec->control_data = i2c;
 949
 950         codec->dev = &i2c->dev;
 951
 952         return rk1000_codec_register(rk1000_codec, SND_SOC_I2C);
 953 }
 954
 955 static int rk1000_codec_i2c_remove(struct i2c_client *client)
 956 {
 957         struct rk1000_codec_priv *rk1000_codec = i2c_get_clientdata(client);
 958         rk1000_codec_unregister(rk1000_codec);
 959         return 0;
 960 }
 961
 962 #ifdef CONFIG_PM
 963 static int rk1000_codec_i2c_suspend(struct i2c_client *client, pm_message_t msg)
 964 {
 965         return snd_soc_suspend_device(&client->dev);
 966 }
 967
 968 static int rk1000_codec_i2c_resume(struct i2c_client *client)
 969 {
 970         return snd_soc_resume_device(&client->dev);
 971 }
 972 #else
 973 #define rk1000_codec_i2c_suspend NULL
 974 #define rk1000_codec_i2c_resume NULL
 975 #endif
 976
 977 static const struct i2c_device_id rk1000_codec_i2c_id[] = {
 978         { "rk1000_i2c_codec", 0 },
 979         { }
 980 };
 981 MODULE_DEVICE_TABLE(i2c, rk1000_codec_i2c_id);
 982
 983 /* corgi i2c codec control layer */
 984 static struct i2c_driver rk1000_codec_i2c_driver = {
 985         .driver = {
 986                 .name = "RK1000_CODEC",
 987                 .owner = THIS_MODULE,
 988         },
 989         .probe = rk1000_codec_i2c_probe,
 990         .remove = rk1000_codec_i2c_remove,
 991         .suspend = rk1000_codec_i2c_suspend,
 992         .resume = rk1000_codec_i2c_resume,
 993         .id_table = rk1000_codec_i2c_id,
 994 };
 995 #endif
 996
 997 static int __init rk1000_codec_modinit(void)
 998 {
 999         int ret;
1000
1001         ret = i2c_add_driver(&rk1000_codec_i2c_driver);
1002         if (ret != 0)
1003                 pr_err("rk1000 codec: Unable to register I2C driver: %d\n", ret);
1004         return ret;
1005 }
1006 module_init(rk1000_codec_modinit);
1007
1008 static void __exit rk1000_codec_exit(void)
1009 {
1010         i2c_del_driver(&rk1000_codec_i2c_driver);
1011 }
1012 module_exit(rk1000_codec_exit);
1013
1014 MODULE_DESCRIPTION("ASoC RK1000 CODEC driver");
1015 MODULE_AUTHOR("lhh lhh@rock-chips.com");
1016 MODULE_LICENSE("GPL");