3 * Copyright (C) 2014 rockchip
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #ifndef _RK3036_CODEC_H
13 #define _RK3036_CODEC_H
16 #define RK3036_CODEC_RESET (0x00 << 2)
17 #define RK3036_CODEC_REG03 (0x03 << 2)
18 #define RK3036_CODEC_REG04 (0x04 << 2)
19 #define RK3036_CODEC_REG05 (0x05 << 2)
21 #define RK3036_CODEC_REG22 (0x22 << 2)
22 #define RK3036_CODEC_REG23 (0x23 << 2)
23 #define RK3036_CODEC_REG24 (0x24 << 2)
24 #define RK3036_CODEC_REG25 (0x25 << 2)
25 #define RK3036_CODEC_REG26 (0x26 << 2)
26 #define RK3036_CODEC_REG27 (0x27 << 2)
27 #define RK3036_CODEC_REG28 (0x28 << 2)
29 /* RK3036_CODEC_RESET */
30 #define RK3036_CR00_DIGITAL_RESET (0 << 1)
31 #define RK3036_CR00_DIGITAL_WORK (1 << 1)
32 #define RK3036_CR00_SYSTEM_RESET (0 << 0)
33 #define RK3036_CR00_SYSTEM_WORK (1 << 0)
35 /*RK3036_CODEC_REG03*/
36 #define RK3036_CR03_DIRECTION_MASK (1 << 5)
37 #define RK3036_CR03_DIRECTION_IN (0 << 5)
38 #define RK3036_CR03_DIRECTION_IOUT (1 << 5)
39 #define RK3036_CR03_I2SMODE_MASK (1 << 4)
40 #define RK3036_CR03_I2SMODE_SLAVE (0 << 4)
41 #define RK3036_CR03_I2SMODE_MASTER (1 << 4)
43 /*RK3036_CODEC_REG04*/
44 #define RK3036_CR04_I2SLRC_MASK (1 << 7)
45 #define RK3036_CR04_I2SLRC_NORMAL (0 << 7)
46 #define RK3036_CR04_I2SLRC_REVERSAL (1 << 7)
47 #define RK3036_CR04_HFVALID_MASK (3 << 5)
48 #define RK3036_CR04_HFVALID_16BITS (0 << 5)
49 #define RK3036_CR04_HFVALID_20BITS (1 << 5)
50 #define RK3036_CR04_HFVALID_24BITS (2 << 5)
51 #define RK3036_CR04_HFVALID_32BITS (3 << 5)
52 #define RK3036_CR04_MODE_MASK (3 << 3)
53 #define RK3036_CR04_MODE_RIGHT (0 << 3)
54 #define RK3036_CR04_MODE_LEFT (1 << 3)
55 #define RK3036_CR04_MODE_I2S (2 << 3)
56 #define RK3036_CR04_MODE_PCM (3 << 3)
57 #define RK3036_CR04_LR_SWAP_MASK (1 << 2)
58 #define RK3036_CR04_LR_SWAP_DIS (0 << 2)
59 #define RK3036_CR04_LR_SWAP_EN (1 << 2)
61 /*RK3036_CODEC_REG05*/
62 #define RK3036_CR05_FRAMEH_MASK (3 << 2)
63 #define RK3036_CR05_FRAMEH_16BITS (0 << 2)
64 #define RK3036_CR05_FRAMEH_20BITS (1 << 2)
65 #define RK3036_CR05_FRAMEH_24BITS (2 << 2)
66 #define RK3036_CR05_FRAMEH_32BITS (3 << 2)
67 #define RK3036_CR05_DAC_RESET_MASK (1 << 1)
68 #define RK3036_CR05_DAC_RESET_EN (0 << 1)
69 #define RK3036_CR05_DAC_RESET_DIS (1 << 1)
70 #define RK3036_CR05_BCLKPOL_MASK (1 << 0)
71 #define RK3036_CR05_BCLKPOL_NORMAL (0 << 0)
72 #define RK3036_CR05_BCLKPOL_REVERSAL (1 << 0)
74 /*RK3036_CODEC_REG22*/
75 #define RK3036_CR22_DACL_PATH_REFV_MASK (1 << 5)
76 #define RK3036_CR22_DACL_PATH_REFV_STOP (0 << 5)
77 #define RK3036_CR22_DACL_PATH_REFV_WORK (1 << 5)
78 #define RK3036_CR22_DACR_PATH_REFV_MASK (1 << 4)
79 #define RK3036_CR22_DACR_PATH_REFV_STOP (0 << 4)
80 #define RK3036_CR22_DACR_PATH_REFV_WORK (1 << 4)
81 #define RK3036_CR22_DACL_CLK_STOP (0 << 3)
82 #define RK3036_CR22_DACL_CLK_WORK (1 << 3)
83 #define RK3036_CR22_DACR_CLK_STOP (0 << 2)
84 #define RK3036_CR22_DACR_CLK_WORK (1 << 2)
85 #define RK3036_CR22_DACL_STOP (0 << 1)
86 #define RK3036_CR22_DACL_WORK (1 << 1)
87 #define RK3036_CR22_DACR_STOP (0 << 0)
88 #define RK3036_CR22_DACR_WORK (1 << 0)
90 /*RK3036_CODEC_REG23*/
91 #define RK3036_CR23_HPOUTL_INIT (0 << 3)
92 #define RK3036_CR23_HPOUTL_WORK (1 << 3)
93 #define RK3036_CR23_HPOUTR_INIT (0 << 2)
94 #define RK3036_CR23_HPOUTR_WORK (1 << 2)
95 #define RK3036_CR23_HPOUTL_EN_STOP (0 << 1)
96 #define RK3036_CR23_HPOUTL_EN_WORK (1 << 1)
97 #define RK3036_CR23_HPOUTR_EN_STOP (0 << 0)
98 #define RK3036_CR23_HPOUTR_EN_WORK (1 << 0)
100 /*RK3036_CODEC_REG24*/
101 #define RK3036_CR24_DAC_SOURCE_STOP (0 << 5)
102 #define RK3036_CR24_DAC_SOURCE_WORK (1 << 5)
103 #define RK3036_CR24_DAC_PRECHARGE (0 << 4)
104 #define RK3036_CR24_DAC_DISCHARGE (1 << 4)
105 #define RK3036_CR24_DACL_REFV_STOP (0 << 3)
106 #define RK3036_CR24_DACL_REFV_WORK (1 << 3)
107 #define RK3036_CR24_DACR_REFV_STOP (0 << 2)
108 #define RK3036_CR24_DACR_REFV_WORK (1 << 2)
109 #define RK3036_CR24_VOUTL_ZEROD_STOP (0 << 1)
110 #define RK3036_CR24_VOUTL_ZEROD_WORK (1 << 1)
111 #define RK3036_CR24_VOUTR_ZEROD_STOP (0 << 0)
112 #define RK3036_CR24_VOUTR_ZEROD_WORK (1 << 0)
114 /*RK3036_CODEC_REG27*/
115 #define RK3036_CR27_DACL_INIT (0 << 7)
116 #define RK3036_CR27_DACL_WORK (1 << 7)
117 #define RK3036_CR27_DACR_INIT (0 << 6)
118 #define RK3036_CR27_DACR_WORK (1 << 6)
119 #define RK3036_CR27_HPOUTL_G_MUTE (0 << 5)
120 #define RK3036_CR27_HPOUTL_G_WORK (1 << 5)
121 #define RK3036_CR27_HPOUTR_G_MUTE (0 << 4)
122 #define RK3036_CR27_HPOUTR_G_WORK (1 << 4)
123 #define RK3036_CR27_HPOUTL_POP_PRECHARGE (1 << 2)
124 #define RK3036_CR27_HPOUTL_POP_WORK (2 << 2)
125 #define RK3036_CR27_HPOUTR_POP_PRECHARGE (1 << 0)
126 #define RK3036_CR27_HPOUTR_POP_WORK (2 << 0)
128 /*RK3036_CODEC_REG28*/
129 #define RK3036_CR28_YES_027I (0 << 5)
130 #define RK3036_CR28_NON_027I (1 << 5)
131 #define RK3036_CR28_YES_050I (0 << 4)
132 #define RK3036_CR28_NON_050I (1 << 4)
133 #define RK3036_CR28_YES_100I (0 << 3)
134 #define RK3036_CR28_NON_100I (1 << 3)
135 #define RK3036_CR28_YES_130I (0 << 2)
136 #define RK3036_CR28_NON_130I (1 << 2)
137 #define RK3036_CR28_YES_260I (0 << 1)
138 #define RK3036_CR28_NON_260I (1 << 1)
139 #define RK3036_CR28_YES_400I (0 << 0)
140 #define RK3036_CR28_NON_400I (1 << 0)
147 struct rk3036_reg_val_typ {
152 struct rk3036_init_bit_typ {
154 unsigned int power_bit;
155 unsigned int init2_bit;
156 unsigned int init1_bit;
157 unsigned int init0_bit;