sound/soc/codecs/rk610_codec.c

   1 /*
   2  * rk610.c -- RK610 ALSA SoC audio driver
   3  *
   4  * Copyright (C) 2009 rockchip lhh
   5  *
   6  *
   7  * Based on RK610.c
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <mach/gpio.h>
  29 #include <mach/iomux.h>
  30 #include <linux/workqueue.h>
  31 #include "rk610_codec.h"
  32 #include <mach/board.h>
  33
  34 #define RK610_PROC
  35 #ifdef RK610_PROC
  36 #include <linux/proc_fs.h>
  37 #include <linux/seq_file.h>
  38 #include <linux/vmalloc.h>
  39 #endif
  40
  41 //if you find resume rk610 cannot work,you can try RESUME_PROBLEM 1.
  42 //if rk610 Normal working on RESUME_PROBLEM 1, you must detect Machine other driver queue.
  43 //you can look soc-core.c the resume source.s
  44 #define RESUME_PROBLEM 0
  45
  46 //old control method,please filling rk610_codec_platform_data into Board-xx-xx.c
  47 //qjb 2013-01-14
  48 #if 0
  49 #if defined(CONFIG_MACH_RK3168_DS1006H)|| defined(CONFIG_MACH_RK3168_LR097)
  50 #define RK610_SPK_CTRL_PIN  RK30_PIN2_PD7
  51 #elif defined(CONFIG_ARCH_RK3066B)
  52 #define RK610_SPK_CTRL_PIN  RK30_PIN2_PA0
  53 #elif defined(CONFIG_ARCH_RK30)
  54 #define RK610_SPK_CTRL_PIN  RK30_PIN4_PC6
  55 #else
  56 #define RK610_SPK_CTRL_PIN  RK29_PIN6_PB6
  57 #endif
  58 #endif
  59
  60 //1:set pll from rk610
  61 #define RK610_CTL_PLL 0
  62
  63 /*
  64  * Debug
  65  */
  66 #if 0
  67 #define DBG(x...)       printk(KERN_INFO x)
  68 #else
  69 #define DBG(x...)
  70 #endif
  71
  72 //it can change rk610 output volume
  73 //0x0000 ~ 0xFFFF
  74 #define Volume_Output 0xF42
  75 //it can change rk610 input volume
  76 //0x00 ~ 0x0E
  77 #define Volume_Input 0x07
  78
  79 #define OUT_CAPLESS  (1)   //ÊÇ·ñÎªÎÞµçÈÝÊä³ö£¬1:ÎÞµçÈÝÊä³ö£¬0:ÓÐµçÈÝÊä³ö
  80
  81 static u32 gVolReg = 0x00;  ///0x0f; //ÓÃÓÚ¼ÇÂ¼ÒôÁ¿¼Ä´æÆ÷
  82 //static u32 gCodecVol = 0x0f;
  83 static u8 gR0AReg = 0;  //ÓÃÓÚ¼ÇÂ¼R0A¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚ¸Ä±ä²ÉÑùÂÊÇ°Í¨¹ýR0AÍ£Ö¹clk
  84 static u8 gR0BReg = 0;  //ÓÃÓÚ¼ÇÂ¼R0B¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚ¸Ä±ä²ÉÑùÂÊÇ°Í¨¹ýR0BÍ£Ö¹interplateºÍdecimation
  85 //static u8 gR1314Reg = 0;  //ÓÃÓÚ¼ÇÂ¼R13,R14¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚFMÒôÁ¿Îª0Ê±
  86
  87 /*
  88  * rk610 register cache
  89  * We can't read the RK610 register space when we
  90  * are using 2 wire for device control, so we cache them instead.
  91  */
  92 static const u16 rk610_codec_reg[] = {
  93         0x0005, 0x0004, 0x00fd, 0x00f3,  /*  0 */
  94         0x0003, 0x0000, 0x0000, 0x0000,  /*  4 */
  95         0x0000, 0x0005, 0x0000, 0x0000,  /*  8 */
  96         0x0097, 0x0097, 0x0097, 0x0097,  /* 12 */
  97         0x0097, 0x0097, 0x00cc, 0x0000,  /* 16 */
  98         0x0000, 0x00f1, 0x0090, 0x00ff,  /* 20 */
  99         0x00ff, 0x00ff, 0x009c, 0x0000,  /* 24 */
 100         0x0000, 0x00ff, 0x00ff, 0x00ff,  /* 28 */
 101 };
 102
 103 static struct snd_soc_codec *rk610_codec_codec=NULL;
 104 /* codec private data */
 105 struct rk610_codec_priv {
 106         enum snd_soc_control_type control_type;
 107         unsigned int sysclk;
 108         struct snd_soc_codec codec;
 109         struct snd_pcm_hw_constraint_list *sysclk_constraints;
 110         u16 reg_cache[RK610_CODEC_NUM_REG];
 111
 112         struct delayed_work rk610_delayed_work;
 113         unsigned int spk_ctrl_io;
 114         bool hdmi_ndet;
 115 #if RESUME_PROBLEM
 116         int rk610_workstatus;
 117 #endif
 118         struct rk610_codec_platform_data *pdata;
 119 };
 120
 121 void codec_set_spk(bool on)
 122 {
 123         struct rk610_codec_priv *rk610_codec;
 124         if(!rk610_codec_codec)
 125                 return;
 126
 127         rk610_codec=snd_soc_codec_get_drvdata(rk610_codec_codec);
 128         if(!rk610_codec)
 129                 return;
 130
 131         rk610_codec->hdmi_ndet = on;
 132         if(on)
 133                 gpio_set_value(rk610_codec->spk_ctrl_io, GPIO_HIGH);
 134         else
 135                 gpio_set_value(rk610_codec->spk_ctrl_io, GPIO_LOW);
 136 }
 137 EXPORT_SYMBOL(codec_set_spk);
 138
 139 /*
 140  * read rk610 register cache
 141  */
 142 static inline unsigned int rk610_codec_read_reg_cache(struct snd_soc_codec *codec,
 143         unsigned int reg)
 144 {
 145         u16 *cache = codec->reg_cache;
 146         if (reg > RK610_CACHE_REGNUM)
 147                 return -1;
 148         return cache[reg];
 149 }
 150
 151 static unsigned int rk610_codec_read(struct snd_soc_codec *codec, unsigned int r)
 152 {
 153         struct i2c_msg xfer[1];
 154         u8 reg = r;
 155         int ret;
 156         struct i2c_client *client = codec->control_data;
 157
 158         /* Read register */
 159         xfer[0].addr = (client->addr& 0x60)|(reg);
 160         xfer[0].flags = I2C_M_RD;
 161         xfer[0].len = 1;
 162         xfer[0].buf = &reg;
 163         xfer[0].scl_rate = 100000;
 164         ret = i2c_transfer(client->adapter, xfer, 1);
 165         if (ret != 1) {
 166                 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
 167                 return 0;
 168         }
 169
 170         return reg;
 171 }
 172
 173 /*
 174  * write rk610 register cache
 175  */
 176 static inline void rk610_codec_write_reg_cache(struct snd_soc_codec *codec,
 177         unsigned int reg, unsigned int value)
 178 {
 179         u16 *cache = codec->reg_cache;
 180         if (reg > RK610_CACHE_REGNUM)
 181                 return;
 182         cache[reg] = value;
 183 }
 184
 185 static int rk610_codec_write(struct snd_soc_codec *codec, unsigned int reg,
 186         unsigned int value)
 187 {
 188         u8 data[2];
 189         struct i2c_client *i2c;
 190         DBG("Enter::%s, %d, reg=0x%02X, value=0x%02X\n",__FUNCTION__,__LINE__, reg, value);
 191         data[0] = value & 0x00ff;
 192         rk610_codec_write_reg_cache (codec, reg, value);
 193         i2c = (struct i2c_client *)codec->control_data;
 194         i2c->addr = (i2c->addr & 0x60)|reg;
 195
 196         if (codec->hw_write(codec->control_data, data, 1) == 1){
 197 //              DBG("================%s %d Run OK================\n",__FUNCTION__,__LINE__);
 198                 return 0;
 199         }else{
 200                 DBG("================%s %d Run EIO================\n",__FUNCTION__,__LINE__);
 201                 return -EIO;
 202         }
 203 }
 204
 205 void rk610_codec_reg_read(void)
 206 {
 207     struct snd_soc_codec *codec = rk610_codec_codec;
 208     int i;
 209     unsigned int data;
 210
 211     for (i=0; i<=0x1f; i++){
 212         data = rk610_codec_read(codec, i);
 213         printk("reg[0x%x]=0x%x\n",i,data);
 214     }
 215 }
 216
 217 static void spk_ctrl_fun(int status)
 218 {
 219         struct rk610_codec_priv *rk610_codec = NULL;
 220         if(rk610_codec_codec == NULL)
 221                 return;
 222         rk610_codec = snd_soc_codec_get_drvdata(rk610_codec_codec);
 223         if(rk610_codec == NULL)
 224                 return;
 225
 226         if(rk610_codec->spk_ctrl_io)
 227         {
 228                 DBG("--------%s----------status = %d\n",__FUNCTION__,status);
 229                 gpio_set_value(rk610_codec->spk_ctrl_io, status);
 230         }
 231 }
 232
 233 struct _coeff_div {
 234         u32 mclk;
 235         u32 rate;
 236         u16 fs;
 237         u8 sr:5;
 238         u8 usb:1;
 239         u8 bclk;
 240 };
 241
 242 /* codec hifi mclk clock divider coefficients */
 243 static const struct _coeff_div coeff_div[] = {
 244         /* 8k */
 245         {12288000, 8000, 1536, 0x6, 0x0,ASC_BCLKDIV_16},
 246         {11289600, 8000, 1408, 0x16, 0x0,ASC_BCLKDIV_16},
 247         {18432000, 8000, 2304, 0x7, 0x0,ASC_BCLKDIV_16},
 248         {16934400, 8000, 2112, 0x17, 0x0,ASC_BCLKDIV_16},
 249         {8192000, 8000, 1024, 0x0, 0x0,ASC_BCLKDIV_16},
 250         {12000000, 8000, 1500, 0x6, 0x1,ASC_BCLKDIV_16},
 251
 252         /* 11.025k */
 253         {11289600, 11025, 1024, 0x18, 0x0,ASC_BCLKDIV_16},
 254         {16934400, 11025, 1536, 0x19, 0x0,ASC_BCLKDIV_16},
 255         {12000000, 11025, 1088, 0x19, 0x1,ASC_BCLKDIV_16},
 256
 257     /* 12k */
 258         {12288000, 12000, 1024, 0x8, 0x0,ASC_BCLKDIV_16},
 259         {18432000, 12000, 1536, 0x9, 0x0,ASC_BCLKDIV_16},
 260         {12000000, 12000, 1000, 0x8, 0x1,ASC_BCLKDIV_16},
 261
 262         /* 16k */
 263         {12288000, 16000, 768, 0xa, 0x0,ASC_BCLKDIV_8},
 264         {18432000, 16000, 1152, 0xb, 0x0,ASC_BCLKDIV_8},
 265         {12000000, 16000, 750, 0xa, 0x1,ASC_BCLKDIV_8},
 266
 267         /* 22.05k */
 268         {11289600, 22050, 512, 0x1a, 0x0,ASC_BCLKDIV_8},
 269         {16934400, 22050, 768, 0x1b, 0x0,ASC_BCLKDIV_8},
 270         {12000000, 22050, 544, 0x1b, 0x1,ASC_BCLKDIV_8},
 271
 272     /* 24k */
 273         {12288000, 24000, 512, 0x1c, 0x0,ASC_BCLKDIV_8},
 274         {18432000, 24000, 768, 0x1d, 0x0,ASC_BCLKDIV_8},
 275         {12000000, 24000, 500, 0x1c, 0x1,ASC_BCLKDIV_8},
 276
 277         /* 32k */
 278         {12288000, 32000, 384, 0xc, 0x0,ASC_BCLKDIV_8},
 279         {18432000, 32000, 576, 0xd, 0x0,ASC_BCLKDIV_8},
 280         {12000000, 32000, 375, 0xa, 0x1,ASC_BCLKDIV_8},
 281
 282         /* 44.1k */
 283         {11289600, 44100, 256, 0x10, 0x0,ASC_BCLKDIV_4},
 284         {16934400, 44100, 384, 0x11, 0x0,ASC_BCLKDIV_8},
 285         {12000000, 44100, 272, 0x11, 0x1,ASC_BCLKDIV_8},
 286
 287         /* 48k */
 288         {12288000, 48000, 256, 0x0, 0x0,ASC_BCLKDIV_4},
 289         {18432000, 48000, 384, 0x1, 0x0,ASC_BCLKDIV_4},
 290         {12000000, 48000, 250, 0x0, 0x1,ASC_BCLKDIV_4},
 291
 292         /* 88.2k */
 293         {11289600, 88200, 128, 0x1e, 0x0,ASC_BCLKDIV_4},
 294         {16934400, 88200, 192, 0x1f, 0x0,ASC_BCLKDIV_4},
 295         {12000000, 88200, 136, 0x1f, 0x1,ASC_BCLKDIV_4},
 296
 297         /* 96k */
 298         {12288000, 96000, 128, 0xe, 0x0,ASC_BCLKDIV_4},
 299         {18432000, 96000, 192, 0xf, 0x0,ASC_BCLKDIV_4},
 300         {12000000, 96000, 125, 0xe, 0x1,ASC_BCLKDIV_4},
 301 };
 302
 303 static inline int get_coeff(int mclk, int rate)
 304 {
 305         int i;
 306
 307         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
 308                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
 309                         return i;
 310         }
 311
 312         return -EINVAL;
 313 }
 314
 315 /* The set of rates we can generate from the above for each SYSCLK */
 316
 317 static unsigned int rates_12288[] = {
 318         8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
 319 };
 320
 321 static struct snd_pcm_hw_constraint_list constraints_12288 = {
 322         .count  = ARRAY_SIZE(rates_12288),
 323         .list   = rates_12288,
 324 };
 325
 326 static unsigned int rates_112896[] = {
 327         8000, 11025, 22050, 44100,
 328 };
 329
 330 static struct snd_pcm_hw_constraint_list constraints_112896 = {
 331         .count  = ARRAY_SIZE(rates_112896),
 332         .list   = rates_112896,
 333 };
 334
 335 static unsigned int rates_12[] = {
 336         8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
 337         48000, 88235, 96000,
 338 };
 339
 340 static struct snd_pcm_hw_constraint_list constraints_12 = {
 341         .count  = ARRAY_SIZE(rates_12),
 342         .list   = rates_12,
 343 };
 344
 345 static int rk610_codec_set_bias_level(struct snd_soc_codec *codec,
 346                                  enum snd_soc_bias_level level)
 347 {
 348         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 349         DBG("Enter::%s----%d now_level =%d  old_level = %d\n",__FUNCTION__,__LINE__,level,codec->dapm.bias_level);
 350         switch (level) {
 351         case SND_SOC_BIAS_ON:
 352                 break;
 353         case SND_SOC_BIAS_PREPARE:
 354                 /* VREF, VMID=2x50k, digital enabled */
 355         //      rk610_codec_write(codec, ACCELCODEC_R1D, pwr_reg | 0x0080);
 356                 break;
 357
 358         case SND_SOC_BIAS_STANDBY:
 359 #if RESUME_PROBLEM
 360                 if(rk610_codec->rk610_workstatus == SND_SOC_DAPM_STREAM_RESUME)
 361                 {
 362                         DBG("rk610 is resume,have not into standby\n");
 363                         rk610_codec->rk610_workstatus = SND_SOC_DAPM_STREAM_NOP;
 364                         break;
 365                 }
 366 #endif
 367                 printk("rk610 standby\n");
 368                 spk_ctrl_fun(GPIO_LOW);
 369                 rk610_codec_write(codec, ACCELCODEC_R1D, 0xFE);
 370                 rk610_codec_write(codec, ACCELCODEC_R1E, 0xFF);
 371                 rk610_codec_write(codec, ACCELCODEC_R1F, 0xFF);
 372                 break;
 373
 374         case SND_SOC_BIAS_OFF:
 375                 printk("rk610 power off\n");
 376                 spk_ctrl_fun(GPIO_LOW);
 377                 rk610_codec_write(codec, ACCELCODEC_R1D, 0xFF);
 378                 rk610_codec_write(codec, ACCELCODEC_R1E, 0xFF);
 379                 rk610_codec_write(codec, ACCELCODEC_R1F, 0xFF);
 380                 break;
 381         }
 382
 383         codec->dapm.bias_level = level;
 384
 385         return 0;
 386 }
 387
 388 /*
 389  * Note that this should be called from init rather than from hw_params.
 390  */
 391 static int rk610_codec_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 392                 int clk_id, unsigned int freq, int dir)
 393 {
 394         struct snd_soc_codec *codec = codec_dai->codec;
 395
 396         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 397
 398         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 399
 400 #ifdef RK610_CTL_PLL
 401         if(rk610_codec_pll_set(freq))
 402                 return -EINVAL;
 403 #endif
 404         switch (freq) {
 405         case 11289600:
 406         case 18432000:
 407         case 22579200:
 408         case 36864000:
 409                 rk610_codec->sysclk_constraints = &constraints_112896;
 410                 rk610_codec->sysclk = freq;
 411                 break;
 412
 413         case 12288000:
 414         case 16934400:
 415         case 24576000:
 416         case 33868800:
 417                 rk610_codec->sysclk_constraints = &constraints_12288;
 418                 rk610_codec->sysclk = freq;
 419                 break;
 420
 421         case 12000000:
 422         case 24000000:
 423                 rk610_codec->sysclk_constraints = &constraints_12;
 424                 rk610_codec->sysclk = freq;
 425                 break;
 426         default:
 427                 return -EINVAL;
 428         }
 429         return 0;
 430 }
 431
 432 static int rk610_codec_set_dai_fmt(struct snd_soc_dai *codec_dai,
 433                 unsigned int fmt)
 434 {
 435         struct snd_soc_codec *codec = codec_dai->codec;
 436         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 437         u16 iface = 0;
 438
 439         spk_ctrl_fun(GPIO_LOW);
 440         rk610_codec_write(codec,ACCELCODEC_R1D, 0x2a);  //setup Vmid and Vref, other module power down
 441         rk610_codec_write(codec,ACCELCODEC_R1E, 0x40);  ///|ASC_PDASDML_ENABLE);
 442
 443         /* set master/slave audio interface */
 444         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 445         case SND_SOC_DAIFMT_CBM_CFM:
 446                 iface = 0x0040;
 447                 break;
 448         case SND_SOC_DAIFMT_CBS_CFS:
 449                 iface = 0x0000;
 450                 break;
 451         default:
 452                 return -EINVAL;
 453         }
 454
 455         /* interface format */
 456         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 457         case SND_SOC_DAIFMT_I2S:
 458                 iface |= 0x0002;
 459                 break;
 460         case SND_SOC_DAIFMT_RIGHT_J:
 461                 break;
 462         case SND_SOC_DAIFMT_LEFT_J:
 463                 iface |= 0x0001;
 464                 break;
 465         case SND_SOC_DAIFMT_DSP_A:
 466                 iface |= 0x0003;
 467                 break;
 468         case SND_SOC_DAIFMT_DSP_B:
 469                 iface |= 0x0013;
 470                 break;
 471         default:
 472                 return -EINVAL;
 473         }
 474
 475         /* clock inversion */
 476         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 477         case SND_SOC_DAIFMT_NB_NF:
 478                 break;
 479         case SND_SOC_DAIFMT_IB_IF:
 480                 iface |= 0x0090;
 481                 break;
 482         case SND_SOC_DAIFMT_IB_NF:
 483                 iface |= 0x0080;
 484                 break;
 485         case SND_SOC_DAIFMT_NB_IF:
 486                 iface |= 0x0010;
 487                 break;
 488         default:
 489                 return -EINVAL;
 490         }
 491
 492         DBG("Enter::%s----%d  iface=%x\n",__FUNCTION__,__LINE__,iface);
 493         rk610_codec_write(codec, ACCELCODEC_R09, iface);
 494         return 0;
 495 }
 496
 497 static int rk610_codec_pcm_hw_params(struct snd_pcm_substream *substream,
 498                                 struct snd_pcm_hw_params *params,
 499                                 struct snd_soc_dai *dai)
 500 {
 501         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 502         struct snd_soc_codec *codec = rtd->codec;
 503         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 504
 505         u16 iface = rk610_codec_read_reg_cache(codec, ACCELCODEC_R09) & 0x1f3;
 506         u16 srate = rk610_codec_read_reg_cache(codec, ACCELCODEC_R00) & 0x180;
 507         int coeff;
 508
 509         coeff = get_coeff(rk610_codec->sysclk, params_rate(params));
 510         DBG("Enter::%s----%d  rk610_codec->sysclk=%d coeff = %d\n",__FUNCTION__,__LINE__,rk610_codec->sysclk, coeff);
 511         /* bit size */
 512         switch (params_format(params)) {
 513         case SNDRV_PCM_FORMAT_S16_LE:
 514                 break;
 515         case SNDRV_PCM_FORMAT_S20_3LE:
 516                 iface |= 0x0004;
 517                 break;
 518         case SNDRV_PCM_FORMAT_S24_LE:
 519                 iface |= 0x0008;
 520                 break;
 521         case SNDRV_PCM_FORMAT_S32_LE:
 522                 iface |= 0x000c;
 523                 break;
 524         }
 525         DBG("Enter::%s----%d  iface=%x srate =%x rate=%d\n",__FUNCTION__,__LINE__,iface,srate,params_rate(params));
 526
 527 //      rk610_codec_write(codec,ACCELCODEC_R0C, 0x17);
 528         rk610_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);   //soft mute
 529         //±ØÐëÏÈ½«clkºÍEN_INT¶¼disableµô£¬·ñÔòÇÐ»»bclk·ÖÆµÖµ¿ÉÄÜµ¼ÖÂcodecÄÚ²¿Ê±Ðò»ìÂÒµô£¬
 530         //±íÏÖ³öÀ´µÄÏÖÏóÊÇ£¬ÒÔºóµÄÒôÀÖ¶¼±ä³ÉÁËÔëÒô£¬¶øÇÒ¾ÍËã°ÑÊäÈëcodecµÄI2S_DATAOUT¶Ï¿ªÒ²Ò»Ñù³öÔëÒô
 531         rk610_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_DISABLE|ASC_INT_DISABLE);  //0x00
 532
 533         /* set iface & srate */
 534         #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 535         iface |= ASC_INVERT_BCLK;//·×ªBCLK  master×´Ì¬ËÍ³öµÄÉÙÁË°ë¸öÊ±ÖÓ£¬µ¼ÖÂÎ´µ½×î´óÒôÁ¿µÄÊ±ºòÆÆÒô¡¢
 536         #endif
 537         rk610_codec_write(codec, ACCELCODEC_R09, iface);
 538         if (coeff >= 0){
 539         //    rk610_codec_write(codec, ACCELCODEC_R00, srate|coeff_div[coeff].bclk);
 540                 rk610_codec_write(codec, ACCELCODEC_R0A, (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb|ASC_CLKNODIV|ASC_CLK_ENABLE);
 541         }
 542         rk610_codec_write(codec,ACCELCODEC_R0B, gR0BReg);
 543
 544         return 0;
 545 }
 546
 547 static int rk610_codec_mute(struct snd_soc_dai *dai, int mute)
 548 {
 549     struct snd_soc_codec *codec = dai->codec;
 550         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 551     DBG("Enter::%s----%d--mute=%d\n",__FUNCTION__,__LINE__,mute);
 552
 553     if (mute)
 554         {
 555                 rk610_codec_write(codec,ACCELCODEC_R17, 0xFF);  //AOL
 556                 rk610_codec_write(codec,ACCELCODEC_R18, 0xFF);  //AOR
 557         rk610_codec_write(codec,ACCELCODEC_R19, 0xFF);  //AOM
 558         rk610_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);  //soft mute
 559         //add for standby
 560         //      if(!dai->capture_active)
 561         //      {
 562         //              rk610_codec_write(codec, ACCELCODEC_R1D, 0xFE);
 563         //              rk610_codec_write(codec, ACCELCODEC_R1E, 0xFF);
 564         //              rk610_codec_write(codec, ACCELCODEC_R1F, 0xFF);
 565         //      }
 566     }
 567         else
 568         {
 569         //      rk610_codec_write(codec,ACCELCODEC_R1D, 0x2a);  //setup Vmid and Vref, other module power down
 570         //      rk610_codec_write(codec,ACCELCODEC_R1E, 0x40);  ///|ASC_PDASDML_ENABLE);
 571                 rk610_codec_write(codec,ACCELCODEC_R17, gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOL gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOL
 572                 rk610_codec_write(codec,ACCELCODEC_R18, gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOR
 573         rk610_codec_write(codec,ACCELCODEC_R04, ASC_INT_ACTIVE_L|ASC_INT_ACTIVE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);
 574                 rk610_codec_write(codec,ACCELCODEC_R19, 0x7F);  //AOM
 575                 msleep(300);
 576                 #if OUT_CAPLESS
 577         rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE);
 578         #else
 579         rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE);
 580                 #endif
 581         //      schedule_delayed_work(&rk610_codec->rk610_delayed_work, 0);
 582         //      rk610_codec_reg_read();
 583                 if(rk610_codec->hdmi_ndet)
 584                         spk_ctrl_fun(GPIO_HIGH);
 585     }
 586
 587     return 0;
 588 }
 589
 590 static void rk610_delayedwork_fun(struct work_struct *work)
 591 {
 592     struct snd_soc_codec *codec = rk610_codec_codec;
 593         DBG("--------%s----------\n",__FUNCTION__);
 594
 595         #if OUT_CAPLESS
 596         rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE);
 597         #else
 598         rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE);
 599         #endif
 600         spk_ctrl_fun(GPIO_HIGH);
 601 }
 602
 603 static struct snd_soc_dai_ops rk610_codec_ops = {
 604         .hw_params = rk610_codec_pcm_hw_params,
 605         .set_fmt = rk610_codec_set_dai_fmt,
 606         .set_sysclk = rk610_codec_set_dai_sysclk,
 607         .digital_mute = rk610_codec_mute,
 608 };
 609
 610 #define RK610_CODEC_RATES SNDRV_PCM_RATE_8000_96000
 611 #define RK610_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 612                                                         SNDRV_PCM_FMTBIT_S24_LE)
 613
 614 static struct snd_soc_dai_driver rk610_codec_dai = {
 615         .name = "rk610_codec",
 616         .playback = {
 617                 .stream_name = "Playback",
 618                 .channels_min = 1,
 619                 .channels_max = 2,
 620                 .rates = RK610_CODEC_RATES,
 621                 .formats = RK610_CODEC_FORMATS,
 622         },
 623         .capture = {
 624                 .stream_name = "Capture",
 625                 .channels_min = 1,
 626                 .channels_max = 2,
 627                 .rates = RK610_CODEC_RATES,
 628                 .formats = RK610_CODEC_FORMATS,
 629          },
 630         .ops = &rk610_codec_ops,
 631         .symmetric_rates = 1,
 632 };
 633
 634 static int rk610_codec_suspend(struct snd_soc_codec *codec, pm_message_t state)
 635 {
 636         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 637         rk610_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
 638 //      rk610_codec_reg_read();
 639         return 0;
 640 }
 641
 642 static int rk610_codec_resume(struct snd_soc_codec *codec)
 643 {
 644         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 645
 646         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 647         /* Sync reg_cache with the hardware */
 648
 649 //      rk610_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 650 #if RESUME_PROBLEM
 651         rk610_codec->rk610_workstatus = SND_SOC_DAPM_STREAM_RESUME;
 652 #endif
 653         return 0;
 654 }
 655
 656 #define USE_MIC_IN
 657 #define USE_LPF
 658 void rk610_codec_reg_set(void)
 659 {
 660     struct snd_soc_codec *codec = rk610_codec_codec;
 661     unsigned int digital_gain;
 662         unsigned int mic_vol = Volume_Input;
 663         rk610_codec_write(codec,ACCELCODEC_R1D, 0x30);
 664         rk610_codec_write(codec,ACCELCODEC_R1E, 0x40);
 665
 666 #ifdef USE_LPF
 667         // Route R-LPF->R-Mixer, L-LPF->L-Mixer
 668         rk610_codec_write(codec,ACCELCODEC_R15, 0xC1);
 669 #else
 670         // Route RDAC->R-Mixer, LDAC->L->Mixer
 671         rk610_codec_write(codec,ACCELCODEC_R15, 0x0C);
 672 #endif
 673         // With Cap Output, VMID ramp up slow
 674         rk610_codec_write(codec,ACCELCODEC_R1A, 0x14);
 675     mdelay(10);
 676
 677         rk610_codec_write(codec,ACCELCODEC_R0C, 0x10|ASC_INPUT_VOL_0DB);   //LIL
 678     rk610_codec_write(codec,ACCELCODEC_R0D, 0x10|ASC_INPUT_VOL_0DB);   //LIR
 679
 680 #ifdef USE_MIC_IN
 681         if(mic_vol > 0x07)
 682         {
 683                 rk610_codec_write(codec,ACCELCODEC_R12, 0x4c|ASC_MIC_INPUT|ASC_MIC_BOOST_20DB);   //Select MIC input
 684                 mic_vol -= 0x07;
 685         }
 686         else
 687                 rk610_codec_write(codec,ACCELCODEC_R12, 0x4c|ASC_MIC_INPUT);   //Select MIC input
 688     rk610_codec_write(codec,ACCELCODEC_R1C, ASC_DEM_ENABLE);  //0x00);  //use default value
 689 #else
 690     rk610_codec_write(codec,ACCELCODEC_R12, 0x4c);   //Select Line input
 691 #endif
 692
 693     rk610_codec_write(codec,ACCELCODEC_R0E, 0x10|mic_vol);   //MIC
 694
 695         // Diable route PGA->R/L Mixer, PGA gain 0db.
 696     rk610_codec_write(codec,ACCELCODEC_R13, 0x05 | 0 << 3);
 697     rk610_codec_write(codec,ACCELCODEC_R14, 0x05 | 0 << 3);
 698
 699     //2soft mute
 700     rk610_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);   //soft mute
 701
 702     //2set default SR and clk
 703     rk610_codec_write(codec,ACCELCODEC_R0A, ASC_NORMAL_MODE|(0x10 << 1)|ASC_CLKNODIV|ASC_CLK_DISABLE);
 704     gR0AReg = ASC_NORMAL_MODE|(0x10 << 1)|ASC_CLKNODIV|ASC_CLK_DISABLE;
 705     //2Config audio  interface
 706     rk610_codec_write(codec,ACCELCODEC_R09, ASC_I2S_MODE|ASC_16BIT_MODE|ASC_NORMAL_LRCLK|ASC_LRSWAP_DISABLE|ASC_MASTER_MODE|ASC_NORMAL_BCLK);
 707     rk610_codec_write(codec,ACCELCODEC_R00, ASC_HPF_ENABLE|ASC_DSM_MODE_ENABLE|ASC_SCRAMBLE_ENABLE|ASC_DITHER_ENABLE|ASC_BCLKDIV_4);
 708     //2volume,input,output
 709     digital_gain = Volume_Output;
 710     rk610_codec_write(codec,ACCELCODEC_R05, (digital_gain >> 8) & 0xFF);
 711     rk610_codec_write(codec,ACCELCODEC_R06, digital_gain & 0xFF);
 712     rk610_codec_write(codec,ACCELCODEC_R07, (digital_gain >> 8) & 0xFF);
 713     rk610_codec_write(codec,ACCELCODEC_R08, digital_gain & 0xFF);
 714
 715     rk610_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_ENABLE|ASC_INT_ENABLE);
 716     gR0BReg = ASC_DEC_ENABLE|ASC_INT_ENABLE;  //ASC_DEC_DISABLE|ASC_INT_ENABLE;
 717
 718
 719 //      #if OUT_CAPLESS
 720 //      rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE);
 721 //      #else
 722 //      rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE);
 723 //      #endif
 724 }
 725
 726 #ifdef RK610_PROC
 727 static int RK610_PROC_init(void);
 728 #endif
 729
 730 static int rk610_codec_probe(struct snd_soc_codec *codec)
 731 {
 732         struct rk610_codec_priv *rk610_codec = snd_soc_codec_get_drvdata(codec);
 733         int ret;
 734
 735 #ifdef RK610_PROC
 736         RK610_PROC_init();
 737 #endif
 738         rk610_codec_codec = codec;
 739         DBG("[%s] start\n", __FUNCTION__);
 740         ret = snd_soc_codec_set_cache_io(codec, 8, 16, rk610_codec->control_type);
 741         if (ret != 0) {
 742                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 743                 return ret;
 744         }
 745         //For RK610, i2c write&read method is special, do not use system default method.
 746         codec->write = rk610_codec_write;
 747         codec->read = rk610_codec_read;
 748         codec->hw_write = (hw_write_t)i2c_master_send;
 749
 750         if (rk610_codec_codec == NULL) {
 751                 dev_err(codec->dev, "Codec device not registered\n");
 752                 return -ENODEV;
 753         }
 754
 755         INIT_DELAYED_WORK(&rk610_codec->rk610_delayed_work, rk610_delayedwork_fun);
 756
 757 //old control method,please filling rk610_codec_platform_data into Board-xx-xx.c
 758 //qjb 2013-01-14
 759 #if 0
 760 #ifdef RK610_SPK_CTRL_PIN
 761         rk610_codec->spk_ctrl_io = RK610_SPK_CTRL_PIN;
 762         ret = gpio_request(rk610_codec->spk_ctrl_io, "rk610 spk_ctrl");
 763     if (ret){
 764         printk("rk610_control request gpio fail!\n");
 765                 return ret;
 766     }
 767     gpio_direction_output(rk610_codec->spk_ctrl_io, GPIO_LOW);
 768     gpio_set_value(rk610_codec->spk_ctrl_io, GPIO_LOW);
 769 #else
 770         rk610_codec->spk_ctrl_io = 0;
 771 #endif
 772 #endif
 773         if(rk610_codec->spk_ctrl_io)
 774         {
 775                 ret = gpio_request(rk610_codec->spk_ctrl_io, "rk610 spk_ctrl");
 776             if (ret){
 777                 printk("rk610_control request gpio fail!\n");
 778                         return ret;
 779             }
 780             gpio_direction_output(rk610_codec->spk_ctrl_io, GPIO_LOW);
 781             gpio_set_value(rk610_codec->spk_ctrl_io, GPIO_LOW);
 782         }
 783
 784         rk610_codec->hdmi_ndet = true;
 785 #if RESUME_PROBLEM
 786         rk610_codec->rk610_workstatus = SND_SOC_DAPM_STREAM_NOP;
 787 #endif
 788
 789     rk610_control_init_codec();
 790     rk610_codec_reg_set();
 791 //      rk610_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 792         schedule_delayed_work(&rk610_codec->rk610_delayed_work, msecs_to_jiffies(1000));
 793
 794         codec->dapm.bias_level = SND_SOC_BIAS_PREPARE;
 795         return ret;
 796 }
 797
 798 /* power down chip */
 799 static int rk610_codec_remove(struct snd_soc_codec *codec)
 800 {
 801         rk610_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
 802         return 0;
 803 }
 804
 805 static struct snd_soc_codec_driver soc_codec_dev_rk610_codec = {
 806         .probe =        rk610_codec_probe,
 807         .remove =       rk610_codec_remove,
 808         .suspend =      rk610_codec_suspend,
 809         .resume =       rk610_codec_resume,
 810         .set_bias_level = rk610_codec_set_bias_level,
 811 //      .volatile_register = wm8900_volatile_register,
 812         .reg_cache_size = ARRAY_SIZE(rk610_codec_reg),
 813         .reg_word_size = sizeof(u16),
 814         .reg_cache_default = rk610_codec_reg,
 815 //      .dapm_widgets = rk610_codec_dapm_widgets,
 816 //      .num_dapm_widgets = ARRAY_SIZE(rk610_codec_dapm_widgets),
 817 //      .dapm_routes = audio_map,
 818 //      .num_dapm_routes = ARRAY_SIZE(audio_map),
 819 };
 820
 821 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 822 static int rk610_codec_i2c_probe(struct i2c_client *i2c,
 823                             const struct i2c_device_id *id)
 824 {
 825         struct rk610_codec_priv *rk610_codec;
 826         struct rk610_codec_platform_data *pdata = i2c->dev.platform_data;
 827         int ret;
 828         DBG("%s start\n", __FUNCTION__);
 829         rk610_codec = kzalloc(sizeof(struct rk610_codec_priv), GFP_KERNEL);
 830         if (rk610_codec == NULL)
 831                 return -ENOMEM;
 832 //qjb 2013-01-14
 833         rk610_codec->pdata = pdata;
 834         rk610_codec->spk_ctrl_io = pdata->spk_ctl_io;
 835         if(pdata->io_init){
 836                 ret =  pdata->io_init();
 837                 if (ret < 0) {
 838                         dev_err(&i2c->dev, "Failed to register codec pdata io_init error: %d\n", ret);
 839                         kfree(rk610_codec);
 840                         return ret;
 841                 }
 842         }
 843
 844         i2c_set_clientdata(i2c, rk610_codec);
 845         rk610_codec->control_type = SND_SOC_I2C;
 846
 847         ret =  snd_soc_register_codec(&i2c->dev,
 848                         &soc_codec_dev_rk610_codec, &rk610_codec_dai, 1);
 849         if (ret < 0) {
 850                 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
 851                 kfree(rk610_codec);
 852         }
 853         return ret;
 854 }
 855
 856 static int rk610_codec_i2c_remove(struct i2c_client *client)
 857 {
 858         snd_soc_unregister_codec(&client->dev);
 859         kfree(i2c_get_clientdata(client));
 860         return 0;
 861 }
 862
 863 static const struct i2c_device_id rk610_codec_i2c_id[] = {
 864         { "rk610_i2c_codec", 0 },
 865         { }
 866 };
 867 MODULE_DEVICE_TABLE(i2c, rk610_codec_i2c_id);
 868
 869 /* corgi i2c codec control layer */
 870 static struct i2c_driver rk610_codec_i2c_driver = {
 871         .driver = {
 872                 .name = "RK610_CODEC",
 873                 .owner = THIS_MODULE,
 874         },
 875         .probe = rk610_codec_i2c_probe,
 876         .remove = rk610_codec_i2c_remove,
 877         .id_table = rk610_codec_i2c_id,
 878 };
 879 #endif
 880
 881 static int __init rk610_codec_modinit(void)
 882 {
 883         int ret;
 884         DBG("[%s] start\n", __FUNCTION__);
 885         ret = i2c_add_driver(&rk610_codec_i2c_driver);
 886         if (ret != 0)
 887                 pr_err("rk610 codec: Unable to register I2C driver: %d\n", ret);
 888         return ret;
 889 }
 890 module_init(rk610_codec_modinit);
 891
 892 static void __exit rk610_codec_exit(void)
 893 {
 894         i2c_del_driver(&rk610_codec_i2c_driver);
 895 }
 896 module_exit(rk610_codec_exit);
 897
 898 MODULE_DESCRIPTION("ASoC RK610 CODEC driver");
 899 MODULE_AUTHOR("rk@rock-chips.com");
 900 MODULE_LICENSE("GPL");
 901
 902 //=====================================================================
 903 //Proc
 904 #ifdef RK610_PROC
 905 static ssize_t RK610_PROC_write(struct file *file, const char __user *buffer,
 906                            unsigned long len, void *data)
 907 {
 908         char *cookie_pot;
 909         char *p;
 910         int reg;
 911         int value;
 912
 913         cookie_pot = (char *)vmalloc( len );
 914         if (!cookie_pot)
 915         {
 916                 return -ENOMEM;
 917         }
 918         else
 919         {
 920                 if (copy_from_user( cookie_pot, buffer, len ))
 921                         return -EFAULT;
 922         }
 923
 924         switch(cookie_pot[0])
 925         {
 926         case 'p':
 927                 spk_ctrl_fun(GPIO_HIGH);
 928                 break;
 929         case 'o':
 930                 spk_ctrl_fun(GPIO_LOW);
 931                 break;
 932         case 'r':
 933         case 'R':
 934                 printk("Read reg debug\n");
 935                 if(cookie_pot[1] ==':')
 936                 {
 937                         strsep(&cookie_pot,":");
 938                         while((p=strsep(&cookie_pot,",")))
 939                         {
 940                                 reg = simple_strtol(p,NULL,16);
 941                                 value = rk610_codec_read(rk610_codec_codec,reg);
 942                                 printk("wm8994_read:0x%04x = 0x%04x\n",reg,value);
 943                         }
 944                         printk("\n");
 945                 }
 946                 else
 947                 {
 948                         printk("Error Read reg debug.\n");
 949                         printk("For example: echo 'r:22,23,24,25'>wm8994_ts\n");
 950                 }
 951                 break;
 952         case 'w':
 953         case 'W':
 954                 printk("Write reg debug\n");
 955                 if(cookie_pot[1] ==':')
 956                 {
 957                         strsep(&cookie_pot,":");
 958                         while((p=strsep(&cookie_pot,"=")))
 959                         {
 960                                 reg = simple_strtol(p,NULL,16);
 961                                 p=strsep(&cookie_pot,",");
 962                                 value = simple_strtol(p,NULL,16);
 963                                 rk610_codec_write(rk610_codec_codec,reg,value);
 964                                 printk("wm8994_write:0x%04x = 0x%04x\n",reg,value);
 965                         }
 966                         printk("\n");
 967                 }
 968                 else
 969                 {
 970                         printk("Error Write reg debug.\n");
 971                         printk("For example: w:22=0,23=0,24=0,25=0\n");
 972                 }
 973                 break;
 974         case 'D' :
 975                 printk("Dump reg\n");
 976                 rk610_codec_reg_read();
 977                 break;
 978         }
 979
 980         return len;
 981 }
 982
 983 static int RK610_PROC_init(void)
 984 {
 985         struct proc_dir_entry *RK610_PROC_entry;
 986         RK610_PROC_entry = create_proc_entry("driver/rk610_ts", 0777, NULL);
 987         if(RK610_PROC_entry != NULL)
 988         {
 989                 RK610_PROC_entry->write_proc = RK610_PROC_write;
 990                 return -1;
 991         }
 992         else
 993         {
 994                 printk("create proc error !\n");
 995         }
 996         return 0;
 997 }
 998
 999 #endif