sound/soc/codecs/rk610_codec.c

   1 /*
   2  * rk610.c -- RK610 ALSA SoC audio driver
   3  *
   4  * Copyright (C) 2009 rockchip lhh
   5  *
   6  *
   7  * Based on RK610.c
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <mach/gpio.h>
  29 #include <mach/iomux.h>
  30 #include <linux/workqueue.h>
  31 #include "rk610_codec.h"
  32
  33 #define RK610_PROC
  34 #ifdef RK610_PROC
  35 #include <linux/proc_fs.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/vmalloc.h>
  38 #endif
  39
  40 //if you find resume rk610 cannot work,you can try RESUME_PROBLEM 1.
  41 //if rk610 Normal working on RESUME_PROBLEM 1, you must detect Machine other driver queue.
  42 //you can look soc-core.c the resume source.s
  43 #define RESUME_PROBLEM 0
  44
  45 #if defined(CONFIG_ARCH_RK3066B)
  46 #define RK610_SPK_CTRL_PIN  RK30_PIN2_PA0
  47 #elif defined(CONFIG_ARCH_RK30)
  48 #define RK610_SPK_CTRL_PIN  RK30_PIN4_PC6
  49 #else
  50 #define RK610_SPK_CTRL_PIN  RK29_PIN6_PB6
  51 #endif
  52 //1:set pll from rk610
  53 #define RK610_CTL_PLL 0
  54
  55 /*
  56  * Debug
  57  */
  58 #if 0
  59 #define DBG(x...)       printk(KERN_INFO x)
  60 #else
  61 #define DBG(x...)
  62 #endif
  63
  64 //it can change rk610 output volume
  65 //0x0000 ~ 0xFFFF
  66 #define Volume_Output 0xF42
  67 //it can change rk610 input volume
  68 //0x00 ~ 0x0E
  69 #define Volume_Input 0x07
  70
  71 #define OUT_CAPLESS  (1)   //ÊÇ·ñÎªÎÞµçÈÝÊä³ö£¬1:ÎÞµçÈÝÊä³ö£¬0:ÓÐµçÈÝÊä³ö
  72
  73 static u32 gVolReg = 0x00;  ///0x0f; //ÓÃÓÚ¼ÇÂ¼ÒôÁ¿¼Ä´æÆ÷
  74 //static u32 gCodecVol = 0x0f;
  75 static u8 gR0AReg = 0;  //ÓÃÓÚ¼ÇÂ¼R0A¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚ¸Ä±ä²ÉÑùÂÊÇ°Í¨¹ýR0AÍ£Ö¹clk
  76 static u8 gR0BReg = 0;  //ÓÃÓÚ¼ÇÂ¼R0B¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚ¸Ä±ä²ÉÑùÂÊÇ°Í¨¹ýR0BÍ£Ö¹interplateºÍdecimation
  77 //static u8 gR1314Reg = 0;  //ÓÃÓÚ¼ÇÂ¼R13,R14¼Ä´æÆ÷µÄÖµ£¬ÓÃÓÚFMÒôÁ¿Îª0Ê±
  78
  79 /*
  80  * rk610 register cache
  81  * We can't read the RK610 register space when we
  82  * are using 2 wire for device control, so we cache them instead.
  83  */
  84 static const u16 rk610_codec_reg[] = {
  85         0x0005, 0x0004, 0x00fd, 0x00f3,  /*  0 */
  86         0x0003, 0x0000, 0x0000, 0x0000,  /*  4 */
  87         0x0000, 0x0005, 0x0000, 0x0000,  /*  8 */
  88         0x0097, 0x0097, 0x0097, 0x0097,  /* 12 */
  89         0x0097, 0x0097, 0x00cc, 0x0000,  /* 16 */
  90         0x0000, 0x00f1, 0x0090, 0x00ff,  /* 20 */
  91         0x00ff, 0x00ff, 0x009c, 0x0000,  /* 24 */
  92         0x0000, 0x00ff, 0x00ff, 0x00ff,  /* 28 */
  93 };
  94
  95 static struct snd_soc_codec *rk610_codec_codec=NULL;
  96 /* codec private data */
  97 struct rk610_codec_priv {
  98         enum snd_soc_control_type control_type;
  99         unsigned int sysclk;
 100         struct snd_soc_codec codec;
 101         struct snd_pcm_hw_constraint_list *sysclk_constraints;
 102         u16 reg_cache[RK610_CODEC_NUM_REG];
 103
 104         struct delayed_work rk610_delayed_work;
 105         unsigned int spk_ctrl_io;
 106         bool hdmi_ndet;
 107 #if RESUME_PROBLEM
 108         int rk610_workstatus;
 109 #endif
 110 };
 111
 112 void codec_set_spk(bool on)
 113 {
 114         struct rk610_codec_priv *rk610_codec;
 115         if(!rk610_codec_codec)
 116                 return;
 117
 118         rk610_codec=snd_soc_codec_get_drvdata(rk610_codec_codec);
 119         if(!rk610_codec)
 120                 return;
 121
 122         rk610_codec->hdmi_ndet = on;
 123         if(on)
 124                 gpio_set_value(RK610_SPK_CTRL_PIN, GPIO_HIGH);
 125         else
 126                 gpio_set_value(RK610_SPK_CTRL_PIN, GPIO_LOW);
 127 }
 128 EXPORT_SYMBOL(codec_set_spk);
 129
 130 /*
 131  * read rk610 register cache
 132  */
 133 static inline unsigned int rk610_codec_read_reg_cache(struct snd_soc_codec *codec,
 134         unsigned int reg)
 135 {
 136         u16 *cache = codec->reg_cache;
 137         if (reg > RK610_CACHE_REGNUM)
 138                 return -1;
 139         return cache[reg];
 140 }
 141
 142 static unsigned int rk610_codec_read(struct snd_soc_codec *codec, unsigned int r)
 143 {
 144         struct i2c_msg xfer[1];
 145         u8 reg = r;
 146         int ret;
 147         struct i2c_client *client = codec->control_data;
 148
 149         /* Read register */
 150         xfer[0].addr = (client->addr& 0x60)|(reg);
 151         xfer[0].flags = I2C_M_RD;
 152         xfer[0].len = 1;
 153         xfer[0].buf = &reg;
 154         xfer[0].scl_rate = 100000;
 155         ret = i2c_transfer(client->adapter, xfer, 1);
 156         if (ret != 1) {
 157                 dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
 158                 return 0;
 159         }
 160
 161         return reg;
 162 }
 163
 164 /*
 165  * write rk610 register cache
 166  */
 167 static inline void rk610_codec_write_reg_cache(struct snd_soc_codec *codec,
 168         unsigned int reg, unsigned int value)
 169 {
 170         u16 *cache = codec->reg_cache;
 171         if (reg > RK610_CACHE_REGNUM)
 172                 return;
 173         cache[reg] = value;
 174 }
 175
 176 static int rk610_codec_write(struct snd_soc_codec *codec, unsigned int reg,
 177         unsigned int value)
 178 {
 179         u8 data[2];
 180         struct i2c_client *i2c;
 181         DBG("Enter::%s, %d, reg=0x%02X, value=0x%02X\n",__FUNCTION__,__LINE__, reg, value);
 182         data[0] = value & 0x00ff;
 183         rk610_codec_write_reg_cache (codec, reg, value);
 184         i2c = (struct i2c_client *)codec->control_data;
 185         i2c->addr = (i2c->addr & 0x60)|reg;
 186
 187         if (codec->hw_write(codec->control_data, data, 1) == 1){
 188 //              DBG("================%s %d Run OK================\n",__FUNCTION__,__LINE__);
 189                 return 0;
 190         }else{
 191                 DBG("================%s %d Run EIO================\n",__FUNCTION__,__LINE__);
 192                 return -EIO;
 193         }
 194 }
 195
 196 void rk610_codec_reg_read(void)
 197 {
 198     struct snd_soc_codec *codec = rk610_codec_codec;
 199     int i;
 200     unsigned int data;
 201
 202     for (i=0; i<=0x1f; i++){
 203         data = rk610_codec_read(codec, i);
 204         printk("reg[0x%x]=0x%x\n",i,data);
 205     }
 206 }
 207
 208 static void spk_ctrl_fun(int status)
 209 {
 210         struct rk610_codec_priv *rk610_codec = NULL;
 211         if(rk610_codec_codec == NULL)
 212                 return;
 213         rk610_codec = snd_soc_codec_get_drvdata(rk610_codec_codec);
 214         if(rk610_codec == NULL)
 215                 return;
 216
 217         if(rk610_codec->spk_ctrl_io)
 218         {
 219                 DBG("--------%s----------status = %d\n",__FUNCTION__,status);
 220                 gpio_set_value(rk610_codec->spk_ctrl_io, status);
 221         }
 222 }
 223
 224 struct _coeff_div {
 225         u32 mclk;
 226         u32 rate;
 227         u16 fs;
 228         u8 sr:5;
 229         u8 usb:1;
 230         u8 bclk;
 231 };
 232
 233 /* codec hifi mclk clock divider coefficients */
 234 static const struct _coeff_div coeff_div[] = {
 235         /* 8k */
 236         {12288000, 8000, 1536, 0x6, 0x0,ASC_BCLKDIV_16},
 237         {11289600, 8000, 1408, 0x16, 0x0,ASC_BCLKDIV_16},
 238         {18432000, 8000, 2304, 0x7, 0x0,ASC_BCLKDIV_16},
 239         {16934400, 8000, 2112, 0x17, 0x0,ASC_BCLKDIV_16},
 240         {8192000, 8000, 1024, 0x0, 0x0,ASC_BCLKDIV_16},
 241         {12000000, 8000, 1500, 0x6, 0x1,ASC_BCLKDIV_16},
 242
 243         /* 11.025k */
 244         {11289600, 11025, 1024, 0x18, 0x0,ASC_BCLKDIV_16},
 245         {16934400, 11025, 1536, 0x19, 0x0,ASC_BCLKDIV_16},
 246         {12000000, 11025, 1088, 0x19, 0x1,ASC_BCLKDIV_16},
 247
 248     /* 12k */
 249         {12288000, 12000, 1024, 0x8, 0x0,ASC_BCLKDIV_16},
 250         {18432000, 12000, 1536, 0x9, 0x0,ASC_BCLKDIV_16},
 251         {12000000, 12000, 1000, 0x8, 0x1,ASC_BCLKDIV_16},
 252
 253         /* 16k */
 254         {12288000, 16000, 768, 0xa, 0x0,ASC_BCLKDIV_8},
 255         {18432000, 16000, 1152, 0xb, 0x0,ASC_BCLKDIV_8},
 256         {12000000, 16000, 750, 0xa, 0x1,ASC_BCLKDIV_8},
 257
 258         /* 22.05k */
 259         {11289600, 22050, 512, 0x1a, 0x0,ASC_BCLKDIV_8},
 260         {16934400, 22050, 768, 0x1b, 0x0,ASC_BCLKDIV_8},
 261         {12000000, 22050, 544, 0x1b, 0x1,ASC_BCLKDIV_8},
 262
 263     /* 24k */
 264         {12288000, 24000, 512, 0x1c, 0x0,ASC_BCLKDIV_8},
 265         {18432000, 24000, 768, 0x1d, 0x0,ASC_BCLKDIV_8},
 266         {12000000, 24000, 500, 0x1c, 0x1,ASC_BCLKDIV_8},
 267
 268         /* 32k */
 269         {12288000, 32000, 384, 0xc, 0x0,ASC_BCLKDIV_8},
 270         {18432000, 32000, 576, 0xd, 0x0,ASC_BCLKDIV_8},
 271         {12000000, 32000, 375, 0xa, 0x1,ASC_BCLKDIV_8},
 272
 273         /* 44.1k */
 274         {11289600, 44100, 256, 0x10, 0x0,ASC_BCLKDIV_4},
 275         {16934400, 44100, 384, 0x11, 0x0,ASC_BCLKDIV_8},
 276         {12000000, 44100, 272, 0x11, 0x1,ASC_BCLKDIV_8},
 277
 278         /* 48k */
 279         {12288000, 48000, 256, 0x0, 0x0,ASC_BCLKDIV_4},
 280         {18432000, 48000, 384, 0x1, 0x0,ASC_BCLKDIV_4},
 281         {12000000, 48000, 250, 0x0, 0x1,ASC_BCLKDIV_4},
 282
 283         /* 88.2k */
 284         {11289600, 88200, 128, 0x1e, 0x0,ASC_BCLKDIV_4},
 285         {16934400, 88200, 192, 0x1f, 0x0,ASC_BCLKDIV_4},
 286         {12000000, 88200, 136, 0x1f, 0x1,ASC_BCLKDIV_4},
 287
 288         /* 96k */
 289         {12288000, 96000, 128, 0xe, 0x0,ASC_BCLKDIV_4},
 290         {18432000, 96000, 192, 0xf, 0x0,ASC_BCLKDIV_4},
 291         {12000000, 96000, 125, 0xe, 0x1,ASC_BCLKDIV_4},
 292 };
 293
 294 static inline int get_coeff(int mclk, int rate)
 295 {
 296         int i;
 297
 298         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
 299                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
 300                         return i;
 301         }
 302
 303         return -EINVAL;
 304 }
 305
 306 /* The set of rates we can generate from the above for each SYSCLK */
 307
 308 static unsigned int rates_12288[] = {
 309         8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
 310 };
 311
 312 static struct snd_pcm_hw_constraint_list constraints_12288 = {
 313         .count  = ARRAY_SIZE(rates_12288),
 314         .list   = rates_12288,
 315 };
 316
 317 static unsigned int rates_112896[] = {
 318         8000, 11025, 22050, 44100,
 319 };
 320
 321 static struct snd_pcm_hw_constraint_list constraints_112896 = {
 322         .count  = ARRAY_SIZE(rates_112896),
 323         .list   = rates_112896,
 324 };
 325
 326 static unsigned int rates_12[] = {
 327         8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
 328         48000, 88235, 96000,
 329 };
 330
 331 static struct snd_pcm_hw_constraint_list constraints_12 = {
 332         .count  = ARRAY_SIZE(rates_12),
 333         .list   = rates_12,
 334 };
 335
 336 static int rk610_codec_set_bias_level(struct snd_soc_codec *codec,
 337                                  enum snd_soc_bias_level level)
 338 {
 339         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 340         DBG("Enter::%s----%d now_level =%d  old_level = %d\n",__FUNCTION__,__LINE__,level,codec->dapm.bias_level);
 341         switch (level) {
 342         case SND_SOC_BIAS_ON:
 343                 break;
 344         case SND_SOC_BIAS_PREPARE:
 345                 /* VREF, VMID=2x50k, digital enabled */
 346         //      rk610_codec_write(codec, ACCELCODEC_R1D, pwr_reg | 0x0080);
 347                 break;
 348
 349         case SND_SOC_BIAS_STANDBY:
 350 #if RESUME_PROBLEM
 351                 if(rk610_codec->rk610_workstatus == SND_SOC_DAPM_STREAM_RESUME)
 352                 {
 353                         DBG("rk610 is resume,have not into standby\n");
 354                         rk610_codec->rk610_workstatus = SND_SOC_DAPM_STREAM_NOP;
 355                         break;
 356                 }
 357 #endif
 358                 printk("rk610 standby\n");
 359                 spk_ctrl_fun(GPIO_LOW);
 360                 rk610_codec_write(codec, ACCELCODEC_R1D, 0xFE);
 361                 rk610_codec_write(codec, ACCELCODEC_R1E, 0xFF);
 362                 rk610_codec_write(codec, ACCELCODEC_R1F, 0xFF);
 363                 break;
 364
 365         case SND_SOC_BIAS_OFF:
 366                 printk("rk610 power off\n");
 367                 spk_ctrl_fun(GPIO_LOW);
 368                 rk610_codec_write(codec, ACCELCODEC_R1D, 0xFF);
 369                 rk610_codec_write(codec, ACCELCODEC_R1E, 0xFF);
 370                 rk610_codec_write(codec, ACCELCODEC_R1F, 0xFF);
 371                 break;
 372         }
 373
 374         codec->dapm.bias_level = level;
 375
 376         return 0;
 377 }
 378
 379 /*
 380  * Note that this should be called from init rather than from hw_params.
 381  */
 382 static int rk610_codec_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 383                 int clk_id, unsigned int freq, int dir)
 384 {
 385         struct snd_soc_codec *codec = codec_dai->codec;
 386
 387         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 388
 389         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 390
 391 #ifdef RK610_CTL_PLL
 392         if(rk610_codec_pll_set(freq))
 393                 return -EINVAL;
 394 #endif
 395         switch (freq) {
 396         case 11289600:
 397         case 18432000:
 398         case 22579200:
 399         case 36864000:
 400                 rk610_codec->sysclk_constraints = &constraints_112896;
 401                 rk610_codec->sysclk = freq;
 402                 break;
 403
 404         case 12288000:
 405         case 16934400:
 406         case 24576000:
 407         case 33868800:
 408                 rk610_codec->sysclk_constraints = &constraints_12288;
 409                 rk610_codec->sysclk = freq;
 410                 break;
 411
 412         case 12000000:
 413         case 24000000:
 414                 rk610_codec->sysclk_constraints = &constraints_12;
 415                 rk610_codec->sysclk = freq;
 416                 break;
 417         default:
 418                 return -EINVAL;
 419         }
 420         return 0;
 421 }
 422
 423 static int rk610_codec_set_dai_fmt(struct snd_soc_dai *codec_dai,
 424                 unsigned int fmt)
 425 {
 426         struct snd_soc_codec *codec = codec_dai->codec;
 427         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 428         u16 iface = 0;
 429
 430         spk_ctrl_fun(GPIO_LOW);
 431         rk610_codec_write(codec,ACCELCODEC_R1D, 0x2a);  //setup Vmid and Vref, other module power down
 432         rk610_codec_write(codec,ACCELCODEC_R1E, 0x40);  ///|ASC_PDASDML_ENABLE);
 433
 434         /* set master/slave audio interface */
 435         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 436         case SND_SOC_DAIFMT_CBM_CFM:
 437                 iface = 0x0040;
 438                 break;
 439         case SND_SOC_DAIFMT_CBS_CFS:
 440                 iface = 0x0000;
 441                 break;
 442         default:
 443                 return -EINVAL;
 444         }
 445
 446         /* interface format */
 447         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 448         case SND_SOC_DAIFMT_I2S:
 449                 iface |= 0x0002;
 450                 break;
 451         case SND_SOC_DAIFMT_RIGHT_J:
 452                 break;
 453         case SND_SOC_DAIFMT_LEFT_J:
 454                 iface |= 0x0001;
 455                 break;
 456         case SND_SOC_DAIFMT_DSP_A:
 457                 iface |= 0x0003;
 458                 break;
 459         case SND_SOC_DAIFMT_DSP_B:
 460                 iface |= 0x0013;
 461                 break;
 462         default:
 463                 return -EINVAL;
 464         }
 465
 466         /* clock inversion */
 467         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 468         case SND_SOC_DAIFMT_NB_NF:
 469                 break;
 470         case SND_SOC_DAIFMT_IB_IF:
 471                 iface |= 0x0090;
 472                 break;
 473         case SND_SOC_DAIFMT_IB_NF:
 474                 iface |= 0x0080;
 475                 break;
 476         case SND_SOC_DAIFMT_NB_IF:
 477                 iface |= 0x0010;
 478                 break;
 479         default:
 480                 return -EINVAL;
 481         }
 482
 483         DBG("Enter::%s----%d  iface=%x\n",__FUNCTION__,__LINE__,iface);
 484         rk610_codec_write(codec, ACCELCODEC_R09, iface);
 485         return 0;
 486 }
 487
 488 static int rk610_codec_pcm_hw_params(struct snd_pcm_substream *substream,
 489                                 struct snd_pcm_hw_params *params,
 490                                 struct snd_soc_dai *dai)
 491 {
 492         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 493         struct snd_soc_codec *codec = rtd->codec;
 494         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 495
 496         u16 iface = rk610_codec_read_reg_cache(codec, ACCELCODEC_R09) & 0x1f3;
 497         u16 srate = rk610_codec_read_reg_cache(codec, ACCELCODEC_R00) & 0x180;
 498         int coeff;
 499
 500         coeff = get_coeff(rk610_codec->sysclk, params_rate(params));
 501         DBG("Enter::%s----%d  rk610_codec->sysclk=%d coeff = %d\n",__FUNCTION__,__LINE__,rk610_codec->sysclk, coeff);
 502         /* bit size */
 503         switch (params_format(params)) {
 504         case SNDRV_PCM_FORMAT_S16_LE:
 505                 break;
 506         case SNDRV_PCM_FORMAT_S20_3LE:
 507                 iface |= 0x0004;
 508                 break;
 509         case SNDRV_PCM_FORMAT_S24_LE:
 510                 iface |= 0x0008;
 511                 break;
 512         case SNDRV_PCM_FORMAT_S32_LE:
 513                 iface |= 0x000c;
 514                 break;
 515         }
 516         DBG("Enter::%s----%d  iface=%x srate =%x rate=%d\n",__FUNCTION__,__LINE__,iface,srate,params_rate(params));
 517
 518 //      rk610_codec_write(codec,ACCELCODEC_R0C, 0x17);
 519         rk610_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);   //soft mute
 520         //±ØÐëÏÈ½«clkºÍEN_INT¶¼disableµô£¬·ñÔòÇÐ»»bclk·ÖÆµÖµ¿ÉÄÜµ¼ÖÂcodecÄÚ²¿Ê±Ðò»ìÂÒµô£¬
 521         //±íÏÖ³öÀ´µÄÏÖÏóÊÇ£¬ÒÔºóµÄÒôÀÖ¶¼±ä³ÉÁËÔëÒô£¬¶øÇÒ¾ÍËã°ÑÊäÈëcodecµÄI2S_DATAOUT¶Ï¿ªÒ²Ò»Ñù³öÔëÒô
 522         rk610_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_DISABLE|ASC_INT_DISABLE);  //0x00
 523
 524         /* set iface & srate */
 525         #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 526         iface |= ASC_INVERT_BCLK;//·×ªBCLK  master×´Ì¬ËÍ³öµÄÉÙÁË°ë¸öÊ±ÖÓ£¬µ¼ÖÂÎ´µ½×î´óÒôÁ¿µÄÊ±ºòÆÆÒô¡¢
 527         #endif
 528         rk610_codec_write(codec, ACCELCODEC_R09, iface);
 529         if (coeff >= 0){
 530         //    rk610_codec_write(codec, ACCELCODEC_R00, srate|coeff_div[coeff].bclk);
 531                 rk610_codec_write(codec, ACCELCODEC_R0A, (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb|ASC_CLKNODIV|ASC_CLK_ENABLE);
 532         }
 533         rk610_codec_write(codec,ACCELCODEC_R0B, gR0BReg);
 534
 535         return 0;
 536 }
 537
 538 static int rk610_codec_mute(struct snd_soc_dai *dai, int mute)
 539 {
 540     struct snd_soc_codec *codec = dai->codec;
 541         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 542     DBG("Enter::%s----%d--mute=%d\n",__FUNCTION__,__LINE__,mute);
 543
 544     if (mute)
 545         {
 546                 rk610_codec_write(codec,ACCELCODEC_R17, 0xFF);  //AOL
 547                 rk610_codec_write(codec,ACCELCODEC_R18, 0xFF);  //AOR
 548         rk610_codec_write(codec,ACCELCODEC_R19, 0xFF);  //AOM
 549         rk610_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);  //soft mute
 550         //add for standby
 551         //      if(!dai->capture_active)
 552         //      {
 553         //              rk610_codec_write(codec, ACCELCODEC_R1D, 0xFE);
 554         //              rk610_codec_write(codec, ACCELCODEC_R1E, 0xFF);
 555         //              rk610_codec_write(codec, ACCELCODEC_R1F, 0xFF);
 556         //      }
 557     }
 558         else
 559         {
 560         //      rk610_codec_write(codec,ACCELCODEC_R1D, 0x2a);  //setup Vmid and Vref, other module power down
 561         //      rk610_codec_write(codec,ACCELCODEC_R1E, 0x40);  ///|ASC_PDASDML_ENABLE);
 562                 rk610_codec_write(codec,ACCELCODEC_R17, gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOL gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOL
 563                 rk610_codec_write(codec,ACCELCODEC_R18, gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //gVolReg|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN);  //AOR
 564         rk610_codec_write(codec,ACCELCODEC_R04, ASC_INT_ACTIVE_L|ASC_INT_ACTIVE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);
 565                 rk610_codec_write(codec,ACCELCODEC_R19, 0x7F);  //AOM
 566                 msleep(300);
 567                 #if OUT_CAPLESS
 568         rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE);
 569         #else
 570         rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE);
 571                 #endif
 572         //      schedule_delayed_work(&rk610_codec->rk610_delayed_work, 0);
 573         //      rk610_codec_reg_read();
 574                 if(rk610_codec->hdmi_ndet)
 575                         spk_ctrl_fun(GPIO_HIGH);
 576     }
 577
 578     return 0;
 579 }
 580
 581 static void rk610_delayedwork_fun(struct work_struct *work)
 582 {
 583     struct snd_soc_codec *codec = rk610_codec_codec;
 584         DBG("--------%s----------\n",__FUNCTION__);
 585
 586         #if OUT_CAPLESS
 587         rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE);
 588         #else
 589         rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE);
 590         #endif
 591         spk_ctrl_fun(GPIO_HIGH);
 592 }
 593
 594 static struct snd_soc_dai_ops rk610_codec_ops = {
 595         .hw_params = rk610_codec_pcm_hw_params,
 596         .set_fmt = rk610_codec_set_dai_fmt,
 597         .set_sysclk = rk610_codec_set_dai_sysclk,
 598         .digital_mute = rk610_codec_mute,
 599 };
 600
 601 #define RK610_CODEC_RATES SNDRV_PCM_RATE_8000_96000
 602 #define RK610_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 603                                                         SNDRV_PCM_FMTBIT_S24_LE)
 604
 605 static struct snd_soc_dai_driver rk610_codec_dai = {
 606         .name = "rk610_codec",
 607         .playback = {
 608                 .stream_name = "Playback",
 609                 .channels_min = 1,
 610                 .channels_max = 2,
 611                 .rates = RK610_CODEC_RATES,
 612                 .formats = RK610_CODEC_FORMATS,
 613         },
 614         .capture = {
 615                 .stream_name = "Capture",
 616                 .channels_min = 1,
 617                 .channels_max = 2,
 618                 .rates = RK610_CODEC_RATES,
 619                 .formats = RK610_CODEC_FORMATS,
 620          },
 621         .ops = &rk610_codec_ops,
 622         .symmetric_rates = 1,
 623 };
 624
 625 static int rk610_codec_suspend(struct snd_soc_codec *codec, pm_message_t state)
 626 {
 627         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 628         rk610_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
 629 //      rk610_codec_reg_read();
 630         return 0;
 631 }
 632
 633 static int rk610_codec_resume(struct snd_soc_codec *codec)
 634 {
 635         struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec);
 636
 637         DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
 638         /* Sync reg_cache with the hardware */
 639
 640 //      rk610_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 641 #if RESUME_PROBLEM
 642         rk610_codec->rk610_workstatus = SND_SOC_DAPM_STREAM_RESUME;
 643 #endif
 644         return 0;
 645 }
 646
 647 #define USE_MIC_IN
 648 #define USE_LPF
 649 void rk610_codec_reg_set(void)
 650 {
 651     struct snd_soc_codec *codec = rk610_codec_codec;
 652     unsigned int digital_gain;
 653         unsigned int mic_vol = Volume_Input;
 654         rk610_codec_write(codec,ACCELCODEC_R1D, 0x30);
 655         rk610_codec_write(codec,ACCELCODEC_R1E, 0x40);
 656
 657 #ifdef USE_LPF
 658         // Route R-LPF->R-Mixer, L-LPF->L-Mixer
 659         rk610_codec_write(codec,ACCELCODEC_R15, 0xC1);
 660 #else
 661         // Route RDAC->R-Mixer, LDAC->L->Mixer
 662         rk610_codec_write(codec,ACCELCODEC_R15, 0x0C);
 663 #endif
 664         // With Cap Output, VMID ramp up slow
 665         rk610_codec_write(codec,ACCELCODEC_R1A, 0x14);
 666     mdelay(10);
 667
 668         rk610_codec_write(codec,ACCELCODEC_R0C, 0x10|ASC_INPUT_VOL_0DB);   //LIL
 669     rk610_codec_write(codec,ACCELCODEC_R0D, 0x10|ASC_INPUT_VOL_0DB);   //LIR
 670
 671 #ifdef USE_MIC_IN
 672         if(mic_vol > 0x07)
 673         {
 674                 rk610_codec_write(codec,ACCELCODEC_R12, 0x4c|ASC_MIC_INPUT|ASC_MIC_BOOST_20DB);   //Select MIC input
 675                 mic_vol -= 0x07;
 676         }
 677         else
 678                 rk610_codec_write(codec,ACCELCODEC_R12, 0x4c|ASC_MIC_INPUT);   //Select MIC input
 679     rk610_codec_write(codec,ACCELCODEC_R1C, ASC_DEM_ENABLE);  //0x00);  //use default value
 680 #else
 681     rk610_codec_write(codec,ACCELCODEC_R12, 0x4c);   //Select Line input
 682 #endif
 683
 684     rk610_codec_write(codec,ACCELCODEC_R0E, 0x10|mic_vol);   //MIC
 685
 686         // Diable route PGA->R/L Mixer, PGA gain 0db.
 687     rk610_codec_write(codec,ACCELCODEC_R13, 0x05 | 0 << 3);
 688     rk610_codec_write(codec,ACCELCODEC_R14, 0x05 | 0 << 3);
 689
 690     //2soft mute
 691     rk610_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF);   //soft mute
 692
 693     //2set default SR and clk
 694     rk610_codec_write(codec,ACCELCODEC_R0A, ASC_NORMAL_MODE|(0x10 << 1)|ASC_CLKNODIV|ASC_CLK_DISABLE);
 695     gR0AReg = ASC_NORMAL_MODE|(0x10 << 1)|ASC_CLKNODIV|ASC_CLK_DISABLE;
 696     //2Config audio  interface
 697     rk610_codec_write(codec,ACCELCODEC_R09, ASC_I2S_MODE|ASC_16BIT_MODE|ASC_NORMAL_LRCLK|ASC_LRSWAP_DISABLE|ASC_MASTER_MODE|ASC_NORMAL_BCLK);
 698     rk610_codec_write(codec,ACCELCODEC_R00, ASC_HPF_ENABLE|ASC_DSM_MODE_ENABLE|ASC_SCRAMBLE_ENABLE|ASC_DITHER_ENABLE|ASC_BCLKDIV_4);
 699     //2volume,input,output
 700     digital_gain = Volume_Output;
 701     rk610_codec_write(codec,ACCELCODEC_R05, (digital_gain >> 8) & 0xFF);
 702     rk610_codec_write(codec,ACCELCODEC_R06, digital_gain & 0xFF);
 703     rk610_codec_write(codec,ACCELCODEC_R07, (digital_gain >> 8) & 0xFF);
 704     rk610_codec_write(codec,ACCELCODEC_R08, digital_gain & 0xFF);
 705
 706     rk610_codec_write(codec,ACCELCODEC_R0B, ASC_DEC_ENABLE|ASC_INT_ENABLE);
 707     gR0BReg = ASC_DEC_ENABLE|ASC_INT_ENABLE;  //ASC_DEC_DISABLE|ASC_INT_ENABLE;
 708
 709
 710 //      #if OUT_CAPLESS
 711 //      rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE);
 712 //      #else
 713 //      rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE);
 714 //      #endif
 715 }
 716
 717 #ifdef RK610_PROC
 718 static int RK610_PROC_init(void);
 719 #endif
 720
 721 static int rk610_codec_probe(struct snd_soc_codec *codec)
 722 {
 723         struct rk610_codec_priv *rk610_codec = snd_soc_codec_get_drvdata(codec);
 724         int ret;
 725
 726 #ifdef RK610_PROC
 727         RK610_PROC_init();
 728 #endif
 729         rk610_codec_codec = codec;
 730         DBG("[%s] start\n", __FUNCTION__);
 731         ret = snd_soc_codec_set_cache_io(codec, 8, 16, rk610_codec->control_type);
 732         if (ret != 0) {
 733                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 734                 return ret;
 735         }
 736         //For RK610, i2c write&read method is special, do not use system default method.
 737         codec->write = rk610_codec_write;
 738         codec->read = rk610_codec_read;
 739         codec->hw_write = (hw_write_t)i2c_master_send;
 740
 741         if (rk610_codec_codec == NULL) {
 742                 dev_err(codec->dev, "Codec device not registered\n");
 743                 return -ENODEV;
 744         }
 745
 746         INIT_DELAYED_WORK(&rk610_codec->rk610_delayed_work, rk610_delayedwork_fun);
 747
 748 #ifdef RK610_SPK_CTRL_PIN
 749         rk610_codec->spk_ctrl_io = RK610_SPK_CTRL_PIN;
 750         ret = gpio_request(rk610_codec->spk_ctrl_io, "rk610 spk_ctrl");
 751     if (ret){
 752         printk("rk610_control request gpio fail!\n");
 753                 return ret;
 754     }
 755     gpio_direction_output(rk610_codec->spk_ctrl_io, GPIO_LOW);
 756     gpio_set_value(rk610_codec->spk_ctrl_io, GPIO_LOW);
 757 #else
 758         rk610_codec->spk_ctrl_io = 0;
 759 #endif
 760         rk610_codec->hdmi_ndet = true;
 761 #if RESUME_PROBLEM
 762         rk610_codec->rk610_workstatus = SND_SOC_DAPM_STREAM_NOP;
 763 #endif
 764
 765     rk610_control_init_codec();
 766     rk610_codec_reg_set();
 767 //      rk610_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 768         schedule_delayed_work(&rk610_codec->rk610_delayed_work, msecs_to_jiffies(1000));
 769
 770         codec->dapm.bias_level = SND_SOC_BIAS_PREPARE;
 771         return ret;
 772 }
 773
 774 /* power down chip */
 775 static int rk610_codec_remove(struct snd_soc_codec *codec)
 776 {
 777         rk610_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
 778         return 0;
 779 }
 780
 781 static struct snd_soc_codec_driver soc_codec_dev_rk610_codec = {
 782         .probe =        rk610_codec_probe,
 783         .remove =       rk610_codec_remove,
 784         .suspend =      rk610_codec_suspend,
 785         .resume =       rk610_codec_resume,
 786         .set_bias_level = rk610_codec_set_bias_level,
 787 //      .volatile_register = wm8900_volatile_register,
 788         .reg_cache_size = ARRAY_SIZE(rk610_codec_reg),
 789         .reg_word_size = sizeof(u16),
 790         .reg_cache_default = rk610_codec_reg,
 791 //      .dapm_widgets = rk610_codec_dapm_widgets,
 792 //      .num_dapm_widgets = ARRAY_SIZE(rk610_codec_dapm_widgets),
 793 //      .dapm_routes = audio_map,
 794 //      .num_dapm_routes = ARRAY_SIZE(audio_map),
 795 };
 796
 797 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 798 static int rk610_codec_i2c_probe(struct i2c_client *i2c,
 799                             const struct i2c_device_id *id)
 800 {
 801         struct rk610_codec_priv *rk610_codec;
 802         int ret;
 803         DBG("%s start\n", __FUNCTION__);
 804         rk610_codec = kzalloc(sizeof(struct rk610_codec_priv), GFP_KERNEL);
 805         if (rk610_codec == NULL)
 806                 return -ENOMEM;
 807
 808         i2c_set_clientdata(i2c, rk610_codec);
 809         rk610_codec->control_type = SND_SOC_I2C;
 810
 811         ret =  snd_soc_register_codec(&i2c->dev,
 812                         &soc_codec_dev_rk610_codec, &rk610_codec_dai, 1);
 813         if (ret < 0) {
 814                 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
 815                 kfree(rk610_codec);
 816         }
 817         return ret;
 818 }
 819
 820 static int rk610_codec_i2c_remove(struct i2c_client *client)
 821 {
 822         snd_soc_unregister_codec(&client->dev);
 823         kfree(i2c_get_clientdata(client));
 824         return 0;
 825 }
 826
 827 static const struct i2c_device_id rk610_codec_i2c_id[] = {
 828         { "rk610_i2c_codec", 0 },
 829         { }
 830 };
 831 MODULE_DEVICE_TABLE(i2c, rk610_codec_i2c_id);
 832
 833 /* corgi i2c codec control layer */
 834 static struct i2c_driver rk610_codec_i2c_driver = {
 835         .driver = {
 836                 .name = "RK610_CODEC",
 837                 .owner = THIS_MODULE,
 838         },
 839         .probe = rk610_codec_i2c_probe,
 840         .remove = rk610_codec_i2c_remove,
 841         .id_table = rk610_codec_i2c_id,
 842 };
 843 #endif
 844
 845 static int __init rk610_codec_modinit(void)
 846 {
 847         int ret;
 848         DBG("[%s] start\n", __FUNCTION__);
 849         ret = i2c_add_driver(&rk610_codec_i2c_driver);
 850         if (ret != 0)
 851                 pr_err("rk610 codec: Unable to register I2C driver: %d\n", ret);
 852         return ret;
 853 }
 854 module_init(rk610_codec_modinit);
 855
 856 static void __exit rk610_codec_exit(void)
 857 {
 858         i2c_del_driver(&rk610_codec_i2c_driver);
 859 }
 860 module_exit(rk610_codec_exit);
 861
 862 MODULE_DESCRIPTION("ASoC RK610 CODEC driver");
 863 MODULE_AUTHOR("rk@rock-chips.com");
 864 MODULE_LICENSE("GPL");
 865
 866 //=====================================================================
 867 //Proc
 868 #ifdef RK610_PROC
 869 static ssize_t RK610_PROC_write(struct file *file, const char __user *buffer,
 870                            unsigned long len, void *data)
 871 {
 872         char *cookie_pot;
 873         char *p;
 874         int reg;
 875         int value;
 876
 877         cookie_pot = (char *)vmalloc( len );
 878         if (!cookie_pot)
 879         {
 880                 return -ENOMEM;
 881         }
 882         else
 883         {
 884                 if (copy_from_user( cookie_pot, buffer, len ))
 885                         return -EFAULT;
 886         }
 887
 888         switch(cookie_pot[0])
 889         {
 890         case 'p':
 891                 spk_ctrl_fun(GPIO_HIGH);
 892                 break;
 893         case 'o':
 894                 spk_ctrl_fun(GPIO_LOW);
 895                 break;
 896         case 'r':
 897         case 'R':
 898                 printk("Read reg debug\n");
 899                 if(cookie_pot[1] ==':')
 900                 {
 901                         strsep(&cookie_pot,":");
 902                         while((p=strsep(&cookie_pot,",")))
 903                         {
 904                                 reg = simple_strtol(p,NULL,16);
 905                                 value = rk610_codec_read(rk610_codec_codec,reg);
 906                                 printk("wm8994_read:0x%04x = 0x%04x\n",reg,value);
 907                         }
 908                         printk("\n");
 909                 }
 910                 else
 911                 {
 912                         printk("Error Read reg debug.\n");
 913                         printk("For example: echo 'r:22,23,24,25'>wm8994_ts\n");
 914                 }
 915                 break;
 916         case 'w':
 917         case 'W':
 918                 printk("Write reg debug\n");
 919                 if(cookie_pot[1] ==':')
 920                 {
 921                         strsep(&cookie_pot,":");
 922                         while((p=strsep(&cookie_pot,"=")))
 923                         {
 924                                 reg = simple_strtol(p,NULL,16);
 925                                 p=strsep(&cookie_pot,",");
 926                                 value = simple_strtol(p,NULL,16);
 927                                 rk610_codec_write(rk610_codec_codec,reg,value);
 928                                 printk("wm8994_write:0x%04x = 0x%04x\n",reg,value);
 929                         }
 930                         printk("\n");
 931                 }
 932                 else
 933                 {
 934                         printk("Error Write reg debug.\n");
 935                         printk("For example: w:22=0,23=0,24=0,25=0\n");
 936                 }
 937                 break;
 938         case 'D' :
 939                 printk("Dump reg\n");
 940                 rk610_codec_reg_read();
 941                 break;
 942         }
 943
 944         return len;
 945 }
 946
 947 static int RK610_PROC_init(void)
 948 {
 949         struct proc_dir_entry *RK610_PROC_entry;
 950         RK610_PROC_entry = create_proc_entry("driver/rk610_ts", 0777, NULL);
 951         if(RK610_PROC_entry != NULL)
 952         {
 953                 RK610_PROC_entry->write_proc = RK610_PROC_write;
 954                 return -1;
 955         }
 956         else
 957         {
 958                 printk("create proc error !\n");
 959         }
 960         return 0;
 961 }
 962
 963 #endif