2 * rk616.h -- RK616 CODEC ALSA SoC audio driver
4 * Copyright 2013 Rockship
5 * Author: chenjq <chenjq@rock-chips.com>
9 #ifndef __RK616_CODEC_H__
10 #define __RK616_CODEC_H__
12 //#define CRU_PCM2IS2_CON2 0x0098
13 #define APS_SEL (1 << 2)
14 #define APS_CLR (1 << 1)
15 #define I2S_CHANNEL_SEL (1 << 0)
17 //#define CRU_CFGMISC_CON 0x009C
18 #define MICDET1_PIN_F_CODEC (1 << 18)
19 #define MICDET2_PIN_F_CODEC (1 << 17)
20 #define AD_DA_LOOP (1 << 0)
22 #define RK616_CODEC_BASE 0x0800
24 #define RK616_RESET (RK616_CODEC_BASE + 0x00)
25 #define RK616_ADC_INT_CTL1 (RK616_CODEC_BASE + 0x08)
26 #define RK616_ADC_INT_CTL2 (RK616_CODEC_BASE + 0x0c)
27 #define RK616_DAC_INT_CTL1 (RK616_CODEC_BASE + 0x10)
28 #define RK616_DAC_INT_CTL2 (RK616_CODEC_BASE + 0x14)
29 #define RK616_PGA_AGC_CTL (RK616_CODEC_BASE + 0x28)
30 #define RK616_PWR_ADD1 (RK616_CODEC_BASE + 0x3c)
31 #define RK616_BST_CTL (RK616_CODEC_BASE + 0x40)
32 #define RK616_DIFFIN_CTL (RK616_CODEC_BASE + 0x44)
33 #define RK616_MIXINL_CTL (RK616_CODEC_BASE + 0x48)
34 #define RK616_MIXINL_VOL1 (RK616_CODEC_BASE + 0x4c)
35 #define RK616_MIXINL_VOL2 (RK616_CODEC_BASE + 0x50)
36 #define RK616_MIXINR_CTL (RK616_CODEC_BASE + 0x54)
37 #define RK616_MIXINR_VOL1 (RK616_CODEC_BASE + 0x58)
38 #define RK616_MIXINR_VOL2 (RK616_CODEC_BASE + 0x5c)
39 #define RK616_PGAL_CTL (RK616_CODEC_BASE + 0x60)
40 #define RK616_PGAR_CTL (RK616_CODEC_BASE + 0x64)
41 #define RK616_PWR_ADD2 (RK616_CODEC_BASE + 0x68)
42 #define RK616_DAC_CTL (RK616_CODEC_BASE + 0x6c)
43 #define RK616_LINEMIX_CTL (RK616_CODEC_BASE + 0x70)
44 #define RK616_MUXHP_HPMIX_CTL (RK616_CODEC_BASE + 0x74)
45 #define RK616_HPMIX_CTL (RK616_CODEC_BASE + 0x78)
46 #define RK616_HPMIX_VOL1 (RK616_CODEC_BASE + 0x7c)
47 #define RK616_HPMIX_VOL2 (RK616_CODEC_BASE + 0x80)
48 #define RK616_LINEOUT1_CTL (RK616_CODEC_BASE + 0x84)
49 #define RK616_LINEOUT2_CTL (RK616_CODEC_BASE + 0x88)
50 #define RK616_SPKL_CTL (RK616_CODEC_BASE + 0x8c)
51 #define RK616_SPKR_CTL (RK616_CODEC_BASE + 0x90)
52 #define RK616_HPL_CTL (RK616_CODEC_BASE + 0x94)
53 #define RK616_HPR_CTL (RK616_CODEC_BASE + 0x98)
54 #define RK616_MICBIAS_CTL (RK616_CODEC_BASE + 0x9c)
55 #define RK616_MICKEY_DET_CTL (RK616_CODEC_BASE + 0xa0)
56 #define RK616_PWR_ADD3 (RK616_CODEC_BASE + 0xa4)
57 #define RK616_ADC_CTL (RK616_CODEC_BASE + 0xa8)
58 #define RK616_PGAL_AGC_CTL1 (RK616_CODEC_BASE + 0xc0)
59 #define RK616_PGAL_AGC_CTL2 (RK616_CODEC_BASE + 0xc4)
60 #define RK616_PGAL_AGC_CTL3 (RK616_CODEC_BASE + 0xc8)
61 #define RK616_PGAL_AGC_CTL4 (RK616_CODEC_BASE + 0xcc)
62 #define RK616_PGAL_ASR_CTL (RK616_CODEC_BASE + 0xd0)
63 #define RK616_PGAL_AGC_MAX_H (RK616_CODEC_BASE + 0xd4)
64 #define RK616_PGAL_AGC_MAX_L (RK616_CODEC_BASE + 0xd8)
65 #define RK616_PGAL_AGC_MIN_H (RK616_CODEC_BASE + 0xdc)
66 #define RK616_PGAL_AGC_MIN_L (RK616_CODEC_BASE + 0xe0)
67 #define RK616_PGAL_AGC_CTL5 (RK616_CODEC_BASE + 0xe4)
68 #define RK616_PGAR_AGC_CTL1 (RK616_CODEC_BASE + 0x100)
69 #define RK616_PGAR_AGC_CTL2 (RK616_CODEC_BASE + 0x104)
70 #define RK616_PGAR_AGC_CTL3 (RK616_CODEC_BASE + 0x108)
71 #define RK616_PGAR_AGC_CTL4 (RK616_CODEC_BASE + 0x10c)
72 #define RK616_PGAR_ASR_CTL (RK616_CODEC_BASE + 0x110)
73 #define RK616_PGAR_AGC_MAX_H (RK616_CODEC_BASE + 0x114)
74 #define RK616_PGAR_AGC_MAX_L (RK616_CODEC_BASE + 0x118)
75 #define RK616_PGAR_AGC_MIN_H (RK616_CODEC_BASE + 0x11c)
76 #define RK616_PGAR_AGC_MIN_L (RK616_CODEC_BASE + 0x120)
77 #define RK616_PGAR_AGC_CTL5 (RK616_CODEC_BASE + 0x124)
79 /* global definition (0x8c 0x90 0x94 0x98) */
80 #define RK616_PWRD (0x1 << 7)
81 #define RK616_PWRD_SFT 7
83 #define RK616_INIT_MASK (0x1 << 6)
84 #define RK616_INIT_SFT 6
85 #define RK616_INIT_RN (0x1 << 6)
86 #define RK616_INIT_AFT (0x0 << 6)
88 #define RK616_MUTE (0x1 << 5)
89 #define RK616_MUTE_SFT 5
91 #define RK616_VOL_MASK 0x1f
92 #define RK616_VOL_SFT 0
94 /* ADC Interface Control 1 (0x08) */
95 #define RK616_ALRCK_POL_MASK (0x1 << 7)
96 #define RK616_ALRCK_POL_SFT 7
97 #define RK616_ALRCK_POL_EN (0x1 << 7)
98 #define RK616_ALRCK_POL_DIS (0x0 << 7)
100 #define RK616_ADC_VWL_MASK (0x3 << 5)
101 #define RK616_ADC_VWL_SFT 5
102 #define RK616_ADC_VWL_32 (0x3 << 5)
103 #define RK616_ADC_VWL_24 (0x2 << 5)
104 #define RK616_ADC_VWL_20 (0x1 << 5)
105 #define RK616_ADC_VWL_16 (0x0 << 5)
107 #define RK616_ADC_DF_MASK (0x3 << 3)
108 #define RK616_ADC_DF_SFT 3
109 #define RK616_ADC_DF_PCM (0x3 << 3)
110 #define RK616_ADC_DF_I2S (0x2 << 3)
111 #define RK616_ADC_DF_LJ (0x1 << 3)
112 #define RK616_ADC_DF_RJ (0x0 << 3)
114 #define RK616_ADC_SWAP_MASK (0x1 << 1)
115 #define RK616_ADC_SWAP_SFT 1
116 #define RK616_ADC_SWAP_EN (0x1 << 1)
117 #define RK616_ADC_SWAP_DIS (0x0 << 1)
119 #define RK616_I2S_TYPE_MASK 0x1
120 #define RK616_I2S_TYPE_SFT 0
121 #define RK616_I2S_TYPE_STEREO 0x1
122 #define RK616_I2S_TYPE_MONO 0x0
124 /* ADC Interface Control 2 (0x0c) */
125 #define RK616_I2S_MODE_MASK (0x1 << 4)
126 #define RK616_I2S_MODE_SFT 4
127 #define RK616_I2S_MODE_MST (0x1 << 4)
128 #define RK616_I2S_MODE_SLV (0x0 << 4)
130 #define RK616_ADC_WL_MASK (0x3 << 2)
131 #define RK616_ADC_WL_SFT 2
132 #define RK616_ADC_WL_32 (0x3 << 2)
133 #define RK616_ADC_WL_24 (0x2 << 2)
134 #define RK616_ADC_WL_20 (0x1 << 2)
135 #define RK616_ADC_WL_16 (0x0 << 2)
137 #define RK616_ADC_RST_MASK (0x1 << 1)
138 #define RK616_ADC_RST_SFT 1
139 #define RK616_ADC_RST_DIS (0x1 << 1)
140 #define RK616_ADC_RST_EN (0x0 << 1)
142 #define RK616_ABCLK_POL_MASK 0x1
143 #define RK616_ABCLK_POL_SFT 0
144 #define RK616_ABCLK_POL_EN 0x1
145 #define RK616_ABCLK_POL_DIS 0x0
147 /* DAC Interface Control 1 (0x10) */
148 #define RK616_DLRCK_POL_MASK (0x1 << 7)
149 #define RK616_DLRCK_POL_SFT 7
150 #define RK616_DLRCK_POL_EN (0x1 << 7)
151 #define RK616_DLRCK_POL_DIS (0x0 << 7)
153 #define RK616_DAC_VWL_MASK (0x3 << 5)
154 #define RK616_DAC_VWL_SFT 5
155 #define RK616_DAC_VWL_32 (0x3 << 5)
156 #define RK616_DAC_VWL_24 (0x2 << 5)
157 #define RK616_DAC_VWL_20 (0x1 << 5)
158 #define RK616_DAC_VWL_16 (0x0 << 5)
160 #define RK616_DAC_DF_MASK (0x3 << 3)
161 #define RK616_DAC_DF_SFT 3
162 #define RK616_DAC_DF_PCM (0x3 << 3)
163 #define RK616_DAC_DF_I2S (0x2 << 3)
164 #define RK616_DAC_DF_LJ (0x1 << 3)
165 #define RK616_DAC_DF_RJ (0x0 << 3)
167 #define RK616_DAC_SWAP_MASK (0x1 << 2)
168 #define RK616_DAC_SWAP_SFT 2
169 #define RK616_DAC_SWAP_EN (0x1 << 2)
170 #define RK616_DAC_SWAP_DIS (0x0 << 2)
172 /* DAC Interface Control 2 (0x14) */
173 #define RK616_DAC_WL_MASK (0x3 << 2)
174 #define RK616_DAC_WL_SFT 2
175 #define RK616_DAC_WL_32 (0x3 << 2)
176 #define RK616_DAC_WL_24 (0x2 << 2)
177 #define RK616_DAC_WL_20 (0x1 << 2)
178 #define RK616_DAC_WL_16 (0x0 << 2)
180 #define RK616_DAC_RST_MASK (0x1 << 1)
181 #define RK616_DAC_RST_SFT 1
182 #define RK616_DAC_RST_DIS (0x1 << 1)
183 #define RK616_DAC_RST_EN (0x0 << 1)
185 #define RK616_DBCLK_POL_MASK 0x1
186 #define RK616_DBCLK_POL_SFT 0
187 #define RK616_DBCLK_POL_EN 0x1
188 #define RK616_DBCLK_POL_DIS 0x0
190 /* PGA AGC Enable (0x28) */
191 #define RK616_PGAL_AGC_EN_MASK (0x1 << 5)
192 #define RK616_PGAL_AGC_EN_SFT 5
193 #define RK616_PGAL_AGC_EN (0x1 << 5)
194 #define RK616_PGAL_AGC_DIS (0x0 << 5)
196 #define RK616_PGAR_AGC_EN_MASK (0x1 << 4)
197 #define RK616_PGAR_AGC_EN_SFT 4
198 #define RK616_PGAR_AGC_EN (0x1 << 4)
199 #define RK616_PGAR_AGC_DIS (0x0 << 4)
201 /* Power Management Addition 1 (0x3c) */
202 #define RK616_ADC_PWRD (0x1 << 6)
203 #define RK616_ADC_PWRD_SFT 6
205 #define RK616_DIFFIN_MIR_PGAR_RLPWRD (0x1 << 5)
206 #define RK616_DIFFIN_MIR_PGAR_RLPWRD_SFT 5
208 #define RK616_MIC1_MIC2_MIL_PGAL_RLPWRD (0x1 << 4)
209 #define RK616_MIC1_MIC2_MIL_PGAL_RLPWRD_SFT 4
211 #define RK616_ADCL_RLPWRD (0x1 << 3)
212 #define RK616_ADCL_RLPWRD_SFT 3
214 #define RK616_ADCR_RLPWRD (0x1 << 2)
215 #define RK616_ADCR_RLPWRD_SFT 2
217 /* BST Control (0x40) */
218 #define RK616_BSTL_PWRD (0x1 << 7)
219 #define RK616_BSTL_PWRD_SFT 7
221 #define RK616_BSTL_MODE_MASK (0x1 << 6)
222 #define RK616_BSTL_MODE_SFT 6
223 #define RK616_BSTL_MODE_SE (0x1 << 6)
224 #define RK616_BSTL_MODE_DIFF (0x0 << 6)
226 #define RK616_BSTL_GAIN_MASK (0x1 << 5)
227 #define RK616_BSTL_GAIN_SFT 5
228 #define RK616_BSTL_GAIN_20DB (0x1 << 5)
229 #define RK616_BSTL_GAIN_0DB (0x0 << 5)
231 #define RK616_BSTL_MUTE (0x1 << 4)
232 #define RK616_BSTL_MUTE_SFT 4
234 #define RK616_BSTR_PWRD (0x1 << 3)
235 #define RK616_BSTR_PWRD_SFT 3
237 #define RK616_BSTR_MODE_MASK (0x1 << 2)
238 #define RK616_BSTR_MODE_SFT 2
239 #define RK616_BSTR_MODE_SE (0x1 << 2)
240 #define RK616_BSTR_MODE_DIFF (0x0 << 2)
242 #define RK616_BSTR_GAIN_MASK (0x1 << 1)
243 #define RK616_BSTR_GAIN_SFT 1
244 #define RK616_BSTR_GAIN_20DB (0x1 << 1)
245 #define RK616_BSTR_GAIN_0DB (0x0 << 1)
247 #define RK616_BSTR_MUTE 0x1
248 #define RK616_BSTR_MUTE_SFT 0
250 /* DIFFIN Control (0x44) */
251 #define RK616_DIFFIN_PWRD (0x1 << 5)
252 #define RK616_DIFFIN_PWRD_SFT 5
254 #define RK616_DIFFIN_MODE_MASK (0x1 << 4)
255 #define RK616_DIFFIN_MODE_SFT 4
256 #define RK616_DIFFIN_MODE_SE (0x1 << 4)
257 #define RK616_DIFFIN_MODE_DIFF (0x0 << 4)
259 #define RK616_DIFFIN_GAIN_MASK (0x1 << 3)
260 #define RK616_DIFFIN_GAIN_SFT 3
261 #define RK616_DIFFIN_GAIN_20DB (0x1 << 3)
262 #define RK616_DIFFIN_GAIN_0DB (0x0 << 3)
264 #define RK616_DIFFIN_MUTE (0x1 << 2)
265 #define RK616_DIFFIN_MUTE_SFT 2
267 #define RK616_MIRM_F_MASK (0x1 << 1)
268 #define RK616_MIRM_F_SFT 1
269 #define RK616_MIRM_F_IN1N (0x1 << 1)
270 #define RK616_MIRM_F_DIFFIN (0x0 << 1)
272 #define RK616_HMM_F_MASK 0x1
273 #define RK616_HMM_F_SFT 0
274 #define RK616_HMM_F_IN1N 0x1
275 #define RK616_HMM_F_DIFFIN 0x0
278 /* BSTR MUXMIC MIXINL Control (0x48) */
279 #define RK616_SE_BSTR_F_MASK (0x1 << 6)
280 #define RK616_SE_BSTR_F_SFT 6
281 #define RK616_SE_BSTR_F_MIN2P (0x1 << 6)
282 #define RK616_SE_BSTR_F_MIN2N (0x0 << 6)
284 #define RK616_MM_F_MASK (0x1 << 5)
285 #define RK616_MM_F_SFT 5
286 #define RK616_MM_F_BSTR (0x1 << 5)
287 #define RK616_MM_F_BSTL (0x0 << 5)
289 #define RK616_MIL_PWRD (0x1 << 4)
290 #define RK616_MIL_PWRD_SFT 4
292 #define RK616_MIL_MUTE (0x1 << 3)
293 #define RK616_MIL_MUTE_SFT 3
295 #define RK616_MIL_F_IN3L (0x1 << 2)
296 #define RK616_MIL_F_IN3L_SFT 2
298 #define RK616_MIL_F_IN1P (0x1 << 1)
299 #define RK616_MIL_F_IN1P_SFT 1
301 #define RK616_MIL_F_MUX (0x1 << 0)
302 #define RK616_MIL_F_MUX_SFT 0
304 /* MIXINL volume 1 (0x4c) */
305 #define RK616_MIL_F_MUX_VOL_MASK (0x7 << 3)
306 #define RK616_MIL_F_MUX_VOL_SFT 3
308 #define RK616_MIL_F_IN1P_VOL_MASK 0x7
309 #define RK616_MIL_F_IN1P_VOL_SFT 0
311 /* MIXINL volume 2 (0x50) */
312 #define RK616_MIL_F_IN3L_VOL_MASK 0x7
313 #define RK616_MIL_F_IN3L_VOL_SFT 0
315 /* MIXINR Control (0x54) */
316 #define RK616_MIR_PWRD (0x1 << 5)
317 #define RK616_MIR_PWRD_SFT 5
319 #define RK616_MIR_MUTE (0x1 << 4)
320 #define RK616_MIR_MUTE_SFT 4
322 #define RK616_MIR_F_MIC2N (0x1 << 3)
323 #define RK616_MIR_F_MIC2N_SFT 3
325 #define RK616_MIR_F_IN1P (0x1 << 2)
326 #define RK616_MIR_F_IN1P_SFT 2
328 #define RK616_MIR_F_IN3R (0x1 << 1)
329 #define RK616_MIR_F_IN3R_SFT 1
331 #define RK616_MIR_F_MIRM 0x1
332 #define RK616_MIR_F_MIRM_SFT 0
334 /* MIXINR volume 1 (0x58) */
335 #define RK616_MIR_F_MIRM_VOL_MASK (0x7 << 3)
336 #define RK616_MIR_F_MIRM_VOL_SFT 3
338 #define RK616_MIR_F_IN3R_VOL_MASK 0x7
339 #define RK616_MIR_F_IN3R_VOL_SFT 0
341 /* MIXINR volume 2 (0x5c) */
342 #define RK616_MIR_F_MIC2N_VOL_MASK (0x7 << 3)
343 #define RK616_MIR_F_MIC2N_VOL_SFT 3
345 #define RK616_MIR_F_IN1P_VOL_MASK 0x7
346 #define RK616_MIR_F_IN1P_VOL_SFT 0
348 /* PGA Control (0x60 0x64) */
349 #define RK616_PGA_PWRD (0x1 << 7)
350 #define RK616_PGA_PWRD_SFT 7
352 #define RK616_PGA_MUTE (0x1 << 6)
353 #define RK616_PGA_MUTE_SFT 6
355 #define RK616_PGA_VOL_MASK (0x1f << 0)
356 #define RK616_PGA_VOL_SFT 0
359 /* Power Management Addition 2 (0x68) */
360 #define RK616_HPL_HPR_PWRD (0x1 << 7)
361 #define RK616_HPL_HPR_PWRD_SFT 7
363 #define RK616_DAC_PWRD (0x1 << 6)
364 #define RK616_DAC_PWRD_SFT 6
366 #define RK616_DACL_RLPWRD (0x1 << 5)
367 #define RK616_DACL_RLPWRD_SFT 5
369 #define RK616_DACL_SPKL_RLPWRD (0x1 << 4)
370 #define RK616_DACL_SPKL_RLPWRD_SFT 4
372 #define RK616_DACR_RLPWRD (0x1 << 3)
373 #define RK616_DACR_RLPWRD_SFT 3
375 #define RK616_DACR_SPKR_RLPWRD (0x1 << 2)//? BIT 3 BIT 6 BIT 2
376 #define RK616_DACR_SPKR_RLPWRD_SFT 2
378 #define RK616_LM_LO_RLPWRD (0x1 << 1)
379 #define RK616_LM_LO_RLPWRD_SFT 1
381 #define RK616_HM_RLPWRD 0x1
382 #define RK616_HM_RLPWRD_SFT 0
384 /* DAC Control (0x6c) */
385 #define RK616_DACL_INIT_MASK (0x1 << 5)
386 #define RK616_DACL_INIT_SFT 5
387 #define RK616_DACL_INIT_RN (0x1 << 5)
388 #define RK616_DACL_INIT_AFT (0x0 << 5)
390 #define RK616_DACR_INIT_MASK (0x1 << 4)
391 #define RK616_DACR_INIT_SFT 4
392 #define RK616_DACR_INIT_RN (0x1 << 4)
393 #define RK616_DACR_INIT_AFT (0x0 << 4)
395 #define RK616_DACL_PWRD (0x1 << 3)
396 #define RK616_DACL_PWRD_SFT 3
398 #define RK616_DACR_PWRD (0x1 << 2)
399 #define RK616_DACR_PWRD_SFT 2
401 #define RK616_DACR_CLK_PWRD (0x1 << 1)
402 #define RK616_DACR_CLK_PWRD_SFT 1
404 #define RK616_DACL_CLK_PWRD 0x1
405 #define RK616_DACL_CLK_PWRD_SFT 0
407 /* Linemix Control (0x70) */
408 #define RK616_LM_PWRD (0x1 << 4)
409 #define RK616_LM_PWRD_SFT 4
411 #define RK616_LM_F_PGAR (0x1 << 3)
412 #define RK616_LM_F_PGAR_SFT 3
414 #define RK616_LM_F_PGAL (0x1 << 2)
415 #define RK616_LM_F_PGAL_SFT 2
417 #define RK616_LM_F_DACR (0x1 << 1)
418 #define RK616_LM_F_DACR_SFT 1
420 #define RK616_LM_F_DACL 0x1
421 #define RK616_LM_F_DACL_SFT 0
423 /* MUXHP HPMIX Control (0x74) */
424 #define RK616_HML_PWRD (0x1 << 5)
425 #define RK616_HML_PWRD_SFT 5
427 #define RK616_HML_INIT_MASK (0x1 << 4)
428 #define RK616_HML_INIT_SFT 4
429 #define RK616_HML_INIT_RN (0x1 << 4)
430 #define RK616_HML_INIT_AFT (0x0 << 4)
432 #define RK616_HMR_PWRD (0x1 << 3)
433 #define RK616_HMR_PWRD_SFT 3
435 #define RK616_HMR_INIT_MASK (0x1 << 2)
436 #define RK616_HMR_INIT_SFT 2
437 #define RK616_HMR_INIT_RN (0x1 << 2)
438 #define RK616_HMR_INIT_AFT (0x0 << 2)
440 #define RK616_MHL_F_MASK (0x1 << 1)
441 #define RK616_MHL_F_SFT 1
442 #define RK616_MHL_F_DACL (0x1 << 1)
443 #define RK616_MHL_F_HPMIXL (0x0 << 1)
445 #define RK616_MHR_F_MASK 0x1
446 #define RK616_MHR_F_SFT 0
447 #define RK616_MHR_F_DACR 0x1
448 #define RK616_MHR_F_HPMIXR 0x0
450 /* HPMIX Control (0x78) */
451 #define RK616_HML_F_HMM (0x1 << 7)
452 #define RK616_HML_F_HMM_SFT 7
454 #define RK616_HML_F_IN1P (0x1 << 6)
455 #define RK616_HML_F_IN1P_SFT 6
457 #define RK616_HML_F_PGAL (0x1 << 5)
458 #define RK616_HML_F_PGAL_SFT 5
460 #define RK616_HML_F_DACL (0x1 << 4)
461 #define RK616_HML_F_DACL_SFT 4
463 #define RK616_HMR_F_HMM (0x1 << 3)
464 #define RK616_HMR_F_HMM_SFT 3
466 #define RK616_HMR_F_PGAR (0x1 << 2)
467 #define RK616_HMR_F_PGAR_SFT 2
469 #define RK616_HMR_F_PGAL (0x1 << 1)
470 #define RK616_HMR_F_PGAL_SFT 1
472 #define RK616_HMR_F_DACR 0x1
473 #define RK616_HMR_F_DACR_SFT 0
475 /* HPMIX Volume Control 1 (0x7c) */
476 #define RK616_HML_F_IN1P_VOL_MASK 0x7
477 #define RK616_HML_F_IN1P_VOL_SFT 0
479 /* HPMIX Volume Control 2 (0x80) */
480 #define RK616_HML_F_HMM_VOL_MASK (0x7 << 3)
481 #define RK616_HML_F_HMM_VOL_SFT 3
483 #define RK616_HMR_F_HMM_VOL_MASK 0x7
484 #define RK616_HMR_F_HMM_VOL_SFT 0
486 /* Lineout1 Control (0x84 0x88) */
487 #define RK616_LINEOUT_PWRD (0x1 << 6)
488 #define RK616_LINEOUT_PWRD_SFT 6
490 #define RK616_LINEOUT_MUTE (0x1 << 5)
491 #define RK616_LINEOUT_MUTE_SFT 5
493 #define RK616_LINEOUT_VOL_MASK 0x1f
494 #define RK616_LINEOUT_VOL_SFT 0
496 /* Micbias Control 1 (0x9c) */
497 #define RK616_MICBIAS1_PWRD (0x1 << 7)
498 #define RK616_MICBIAS1_PWRD_SFT 7
500 #define RK616_MICBIAS2_PWRD (0x1 << 6)
501 #define RK616_MICBIAS2_PWRD_SFT 6
503 #define RK616_MICBIAS1_V_MASK (0x7 << 3)
504 #define RK616_MICBIAS1_V_SFT 3
505 #define RK616_MICBIAS1_V_1_7 (0x7 << 3)
506 #define RK616_MICBIAS1_V_1_6 (0x6 << 3)
507 #define RK616_MICBIAS1_V_1_5 (0x5 << 3)
508 #define RK616_MICBIAS1_V_1_4 (0x4 << 3)
509 #define RK616_MICBIAS1_V_1_3 (0x3 << 3)
510 #define RK616_MICBIAS1_V_1_2 (0x2 << 3)
511 #define RK616_MICBIAS1_V_1_1 (0x1 << 3)
512 #define RK616_MICBIAS1_V_1_0 (0x0 << 3)
514 #define RK616_MICBIAS2_V_MASK 0x7
515 #define RK616_MICBIAS2_V_SFT 0
516 #define RK616_MICBIAS2_V_1_7 0x7
517 #define RK616_MICBIAS2_V_1_6 0x6
518 #define RK616_MICBIAS2_V_1_5 0x5
519 #define RK616_MICBIAS2_V_1_4 0x4
520 #define RK616_MICBIAS2_V_1_3 0x3
521 #define RK616_MICBIAS2_V_1_2 0x2
522 #define RK616_MICBIAS2_V_1_1 0x1
523 #define RK616_MICBIAS2_V_1_0 0x0
525 /* MIC Key Detection Control (0xa0) */
526 #define RK616_MK1_DET_MASK (0x1 << 7)
527 #define RK616_MK1_DET_SFT 7
528 #define RK616_MK1_EN (0x1 << 7)
529 #define RK616_MK1_DIS (0x0 << 7)
531 #define RK616_MK2_DET_MASK (0x1 << 6)
532 #define RK616_MK2_DET_SFT 6
533 #define RK616_MK2_EN (0x1 << 6)
534 #define RK616_MK2_DIS (0x0 << 6)
536 #define RK616_MK1_DET_I_MASK (0x7 << 3)
537 #define RK616_MK1_DET_I_SFT 3
538 #define RK616_MK1_DET_I_1500 (0x7 << 3)
539 #define RK616_MK1_DET_I_1300 (0x6 << 3)
540 #define RK616_MK1_DET_I_1100 (0x5 << 3)
541 #define RK616_MK1_DET_I_900 (0x4 << 3)
542 #define RK616_MK1_DET_I_700 (0x3 << 3)
543 #define RK616_MK1_DET_I_500 (0x2 << 3)
544 #define RK616_MK1_DET_I_300 (0x1 << 3)
545 #define RK616_MK1_DET_I_100 (0x0 << 3)
547 #define RK616_MK2_DET_I_MASK 0x7
548 #define RK616_MK2_DET_I_SFT 0
549 #define RK616_MK2_DET_I_1500 0x7
550 #define RK616_MK2_DET_I_1300 0x6
551 #define RK616_MK2_DET_I_1100 0x5
552 #define RK616_MK2_DET_I_900 0x4
553 #define RK616_MK2_DET_I_700 0x3
554 #define RK616_MK2_DET_I_500 0x2
555 #define RK616_MK2_DET_I_300 0x1
556 #define RK616_MK2_DET_I_100 0x0
558 /* Power Management Addition 3 (0xa4) */
559 #define RK616_ADCL_ZO_PWRD (0x1 << 3)
560 #define RK616_ADCL_ZO_PWRD_SFT 3
562 #define RK616_ADCR_ZO_PWRD (0x1 << 2)
563 #define RK616_ADCR_ZO_PWRD_SFT 2
565 #define RK616_DACL_ZO_PWRD (0x1 << 1)
566 #define RK616_DACL_ZO_PWRD_SFT 1
568 #define RK616_DACR_ZO_PWRD 0x1
569 #define RK616_DACR_ZO_PWRD_SFT 0
571 /* ADC control (0xa8) */
572 #define RK616_ADCL_CLK_PWRD (0x1 << 5)
573 #define RK616_ADCL_CLK_PWRD_SFT 5
575 #define RK616_ADCL_PWRD (0x1 << 4)
576 #define RK616_ADCL_PWRD_SFT 4
578 #define RK616_ADCL_CLEAR_MASK (0x1 << 3)//clear buf
579 #define RK616_ADCL_CLEAR_SFT 3
580 #define RK616_ADCL_CLEAR_EN (0x1 << 3)
581 #define RK616_ADCL_CLEAR_DIS (0x0 << 3)
583 #define RK616_ADCR_CLK_PWRD (0x1 << 2)
584 #define RK616_ADCR_CLK_PWRD_SFT 2
586 #define RK616_ADCR_PWRD (0x1 << 1)
587 #define RK616_ADCR_PWRD_SFT 1
589 #define RK616_ADCR_CLEAR_MASK 0x1//clear buf
590 #define RK616_ADCR_CLEAR_SFT 0
591 #define RK616_ADCR_CLEAR_EN 0x1
592 #define RK616_ADCR_CLEAR_DIS 0x0
594 /* PGA AGC control 1 (0xc0 0x110) */
595 #define RK616_PGA_AGC_WAY_MASK (0x1 << 4)
596 #define RK616_PGA_AGC_WAY_SFT 4
597 #define RK616_PGA_AGC_WAY_JACK (0x1 << 4)
598 #define RK616_PGA_AGC_WAY_NOR (0x0 << 4)
600 #define RK616_PGA_AGC_HOLD_T_MASK 0xf
601 #define RK616_PGA_AGC_HOLD_T_SFT 0
602 #define RK616_PGA_AGC_HOLD_T_1024 0xa
603 #define RK616_PGA_AGC_HOLD_T_512 0x9
604 #define RK616_PGA_AGC_HOLD_T_256 0x8
605 #define RK616_PGA_AGC_HOLD_T_128 0x7
606 #define RK616_PGA_AGC_HOLD_T_64 0x6
607 #define RK616_PGA_AGC_HOLD_T_32 0x5
608 #define RK616_PGA_AGC_HOLD_T_16 0x4
609 #define RK616_PGA_AGC_HOLD_T_8 0x3
610 #define RK616_PGA_AGC_HOLD_T_4 0x2
611 #define RK616_PGA_AGC_HOLD_T_2 0x1
612 #define RK616_PGA_AGC_HOLD_T_0 0x0
614 /* PGA AGC control 2 (0xc4 0x104) */
615 #define RK616_PGA_AGC_GRU_T_MASK (0xf << 4)
616 #define RK616_PGA_AGC_GRU_T_SFT 4
617 #define RK616_PGA_AGC_GRU_T_512 (0xa << 4)
618 #define RK616_PGA_AGC_GRU_T_256 (0x9 << 4)
619 #define RK616_PGA_AGC_GRU_T_128 (0x8 << 4)
620 #define RK616_PGA_AGC_GRU_T_64 (0x7 << 4)
621 #define RK616_PGA_AGC_GRU_T_32 (0x6 << 4)
622 #define RK616_PGA_AGC_GRU_T_16 (0x5 << 4)
623 #define RK616_PGA_AGC_GRU_T_8 (0x4 << 4)
624 #define RK616_PGA_AGC_GRU_T_4 (0x3 << 4)
625 #define RK616_PGA_AGC_GRU_T_2 (0x2 << 4)
626 #define RK616_PGA_AGC_GRU_T_1 (0x1 << 4)
627 #define RK616_PGA_AGC_GRU_T_0_5 (0x0 << 4)
629 #define RK616_PGA_AGC_GRD_T_MASK 0xf
630 #define RK616_PGA_AGC_GRD_T_SFT 0
631 #define RK616_PGA_AGC_GRD_T_128_32 0xa
632 #define RK616_PGA_AGC_GRD_T_64_16 0x9
633 #define RK616_PGA_AGC_GRD_T_32_8 0x8
634 #define RK616_PGA_AGC_GRD_T_16_4 0x7
635 #define RK616_PGA_AGC_GRD_T_8_2 0x6
636 #define RK616_PGA_AGC_GRD_T_4_1 0x5
637 #define RK616_PGA_AGC_GRD_T_2_0_512 0x4
638 #define RK616_PGA_AGC_GRD_T_1_0_256 0x3
639 #define RK616_PGA_AGC_GRD_T_0_500_128 0x2
640 #define RK616_PGA_AGC_GRD_T_0_250_64 0x1
641 #define RK616_PGA_AGC_GRD_T_0_125_32 0x0
643 /* PGA AGC control 3 (0xc8 0x108) */
644 #define RK616_PGA_AGC_MODE_MASK (0x1 << 7)
645 #define RK616_PGA_AGC_MODE_SFT 7
646 #define RK616_PGA_AGC_MODE_LIMIT (0x1 << 7)
647 #define RK616_PGA_AGC_MODE_NOR (0x0 << 7)
649 #define RK616_PGA_AGC_ZO_MASK (0x1 << 6)
650 #define RK616_PGA_AGC_ZO_SFT 6
651 #define RK616_PGA_AGC_ZO_EN (0x1 << 6)
652 #define RK616_PGA_AGC_ZO_DIS (0x0 << 6)
654 #define RK616_PGA_AGC_REC_MODE_MASK (0x1 << 5)
655 #define RK616_PGA_AGC_REC_MODE_SFT 5
656 #define RK616_PGA_AGC_REC_MODE_AC (0x1 << 5)
657 #define RK616_PGA_AGC_REC_MODE_RN (0x0 << 5)
659 #define RK616_PGA_AGC_FAST_D_MASK (0x1 << 4)
660 #define RK616_PGA_AGC_FAST_D_SFT 4
661 #define RK616_PGA_AGC_FAST_D_EN (0x1 << 4)
662 #define RK616_PGA_AGC_FAST_D_DIS (0x0 << 4)
664 #define RK616_PGA_AGC_NG_MASK (0x1 << 3)
665 #define RK616_PGA_AGC_NG_SFT 3
666 #define RK616_PGA_AGC_NG_EN (0x1 << 3)
667 #define RK616_PGA_AGC_NG_DIS (0x0 << 3)
669 #define RK616_PGA_AGC_NG_THR_MASK 0x7
670 #define RK616_PGA_AGC_NG_THR_SFT 0
671 #define RK616_PGA_AGC_NG_THR_N81DB 0x7
672 #define RK616_PGA_AGC_NG_THR_N75DB 0x6
673 #define RK616_PGA_AGC_NG_THR_N69DB 0x5
674 #define RK616_PGA_AGC_NG_THR_N63DB 0x4
675 #define RK616_PGA_AGC_NG_THR_N57DB 0x3
676 #define RK616_PGA_AGC_NG_THR_N51DB 0x2
677 #define RK616_PGA_AGC_NG_THR_N45DB 0x1
678 #define RK616_PGA_AGC_NG_THR_N39DB 0x0
680 /* PGA AGC Control 4 (0xcc 0x10c) */
681 #define RK616_PGA_AGC_ZO_MODE_MASK (0x1 << 5)
682 #define RK616_PGA_AGC_ZO_MODE_SFT 5
683 #define RK616_PGA_AGC_ZO_MODE_UWRC (0x1 << 5)
684 #define RK616_PGA_AGC_ZO_MODE_UARC (0x0 << 5)
686 #define RK616_PGA_AGC_VOL_MASK 0x1f
687 #define RK616_PGA_AGC_VOL_SFT 0
689 /* PGA ASR Control (0xd0 0x110) */
690 #define RK616_PGA_SLOW_CLK_MASK (0x1 << 3)
691 #define RK616_PGA_SLOW_CLK_SFT 3
692 #define RK616_PGA_SLOW_CLK_EN (0x1 << 3)
693 #define RK616_PGA_SLOW_CLK_DIS (0x0 << 3)
695 #define RK616_PGA_ASR_MASK 0x7
696 #define RK616_PGA_ASR_SFT 0
697 #define RK616_PGA_ASR_8KHz 0x5
698 #define RK616_PGA_ASR_12KHz 0x4
699 #define RK616_PGA_ASR_16KHz 0x3
700 #define RK616_PGA_ASR_24KHz 0x2
701 #define RK616_PGA_ASR_32KHz 0x1
702 #define RK616_PGA_ASR_48KHz 0x0
704 /* PGA AGC Control 5 (0xe4 0x124) */
705 #define RK616_PGA_AGC_MASK (0x1 << 6)
706 #define RK616_PGA_AGC_SFT 6
707 #define RK616_PGA_AGC_EN (0x1 << 6)
708 #define RK616_PGA_AGC_DIS (0x0 << 6)
710 #define RK616_PGA_AGC_MAX_G_MASK (0x7 << 3)
711 #define RK616_PGA_AGC_MAX_G_SFT 3
712 #define RK616_PGA_AGC_MAX_G_28_5DB (0x7 << 3)
713 #define RK616_PGA_AGC_MAX_G_22_5DB (0x6 << 3)
714 #define RK616_PGA_AGC_MAX_G_16_5DB (0x5 << 3)
715 #define RK616_PGA_AGC_MAX_G_10_5DB (0x4 << 3)
716 #define RK616_PGA_AGC_MAX_G_4_5DB (0x3 << 3)
717 #define RK616_PGA_AGC_MAX_G_N1_5DB (0x2 << 3)
718 #define RK616_PGA_AGC_MAX_G_N7_5DB (0x1 << 3)
719 #define RK616_PGA_AGC_MAX_G_N13_5DB (0x0 << 3)
721 #define RK616_PGA_AGC_MIN_G_MASK 0x7
722 #define RK616_PGA_AGC_MIN_G_SFT 0
723 #define RK616_PGA_AGC_MIN_G_24DB 0x7
724 #define RK616_PGA_AGC_MIN_G_18DB 0x6
725 #define RK616_PGA_AGC_MIN_G_12DB 0x5
726 #define RK616_PGA_AGC_MIN_G_6DB 0x4
727 #define RK616_PGA_AGC_MIN_G_0DB 0x3
728 #define RK616_PGA_AGC_MIN_G_N6DB 0x2
729 #define RK616_PGA_AGC_MIN_G_N12DB 0x1
730 #define RK616_PGA_AGC_MIN_G_N18DB 0x0
742 struct rk616_reg_val_typ {
747 struct rk616_init_bit_typ {
749 unsigned int power_bit;
750 unsigned int init_bit;
753 #endif //__RK616_CODEC_H__