2 * rt3261.c -- RT3261 ALSA SoC audio codec driver
4 * Copyright 2011 Realtek Semiconductor Corp.
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/of_gpio.h>
21 #include <linux/clk.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
31 #define DIFFERENTIAL 1
37 SPK_AMPLIFY_ZERO_POINT_FIVE_WATT=1,
38 SPK_AMPLIFY_ZERO_POINT_SIX_WATT,
39 SPK_AMPLIFY_ZERO_POINT_EIGHT_WATT,
50 static struct snd_soc_codec *rt3261_codec;
53 #define DBG(x...) printk(KERN_DEBUG x)
60 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
61 #include "rt_codec_ioctl.h"
62 #include "rt3261_ioctl.h"
67 #if defined (CONFIG_SND_SOC_RT3261)
68 #include "rt3261-dsp.h"
71 #define RT3261_REG_RW 1 /* for debug */
72 #define RT3261_DET_EXT_MIC 0
74 #define VERSION "RT3261_V1.3.0"
76 #if defined (CONFIG_SND_SOC_RT5623)
77 extern void rt5623_on(void);
78 extern void rt5623_off(void);
81 struct rt3261_init_reg {
86 static struct rt3261_init_reg init_list[] = {
87 {RT3261_GEN_CTRL1 , 0x3701},//fa[12:13] = 1'b; fa[8~10]=1; fa[0]=1
88 {RT3261_ADDA_CLK1 , 0x1114},//73[2] = 1'b
89 {RT3261_MICBIAS , 0x3030},//93[5:4] = 11'b
90 {RT3261_CLS_D_OUT , 0xa000},//8d[11] = 0'b
91 {RT3261_CLS_D_OVCD , 0x0334},//8c[8] = 1'b
92 {RT3261_PRIV_INDEX , 0x001d},//PR1d[8] = 1'b;
93 {RT3261_PRIV_DATA , 0x0347},
94 {RT3261_PRIV_INDEX , 0x003d},//PR3d[12] = 0'b; PR3d[9] = 1'b
95 {RT3261_PRIV_DATA , 0x3600},
96 {RT3261_PRIV_INDEX , 0x0012},//PR12 = 0aa8'h
97 {RT3261_PRIV_DATA , 0x0aa8},
98 {RT3261_PRIV_INDEX , 0x0014},//PR14 = 8aaa'h
99 {RT3261_PRIV_DATA , 0x8aaa},
100 {RT3261_PRIV_INDEX , 0x0020},//PR20 = 6115'h
101 {RT3261_PRIV_DATA , 0x6115},
102 {RT3261_PRIV_INDEX , 0x0023},//PR23 = 0804'h
103 {RT3261_PRIV_DATA , 0x0804},
104 {RT3261_SPK_VOL , 0x8888},//SPKMIX -> SPKVOL
105 {RT3261_HP_VOL , 0x8888},
106 {RT3261_OUTPUT , 0x8888},//unmute OUTVOLL/R
107 {RT3261_SPO_CLSD_RATIO , 0x0001},
108 {RT3261_I2S1_SDP , 0xd000},
109 {RT3261_GLB_CLK , 0x4000},//0424
110 //{0x90 , 0x636},//0424
111 {RT3261_CHARGE_PUMP , 0xe00},//0424
112 {RT3261_DEPOP_M3 , 0x636},//0424
113 {RT3261_DEPOP_M1 , 0x84},//0424
114 {RT3261_PWR_DIG1 , 0x8000},//0424
115 {RT3261_PWR_ANLG2 , 0x0800},
116 // huangcun 20130816 s
119 {RT3261_DSP_PATH2 , 0x0000},
120 {RT3261_PRIV_INDEX , 0x003f},//PR3d[14] = 0'b;
121 {RT3261_PRIV_DATA , 0x0000},
122 {RT3261_DAC2_CTRL , 0x0000},
123 {RT3261_MONO_DAC_MIXER, 0x4444},
124 {RT3261_SPK_L_MIXER, 0x003a},
125 {RT3261_SPK_R_MIXER, 0x003a},
126 {RT3261_SPO_L_MIXER, 0xc800},
128 {RT3261_OUT_L3_MIXER, 0x01fd},
129 {RT3261_OUT_R3_MIXER, 0x01fd},
130 {RT3261_HPO_MIXER, 0xc000},
134 {RT3261_IN1_IN2, 0x2080},//boost1 = 24db
135 {RT3261_REC_R2_MIXER, 0x007d},
136 {RT3261_MONO_ADC_MIXER,0x7030},
137 //{RT3261_GEN_CTRL1 , 0x2701},//regfa[13]=0
138 {RT3261_DSP_PATH2 , 0x0400},
139 {RT3261_DIG_INF_DATA, 0x0300},//right copy to left
143 {RT3261_DSP_PATH2 , 0x0000},
144 {RT3261_PRIV_INDEX , 0x003f},//PR3d[14] = 0'b;
145 {RT3261_PRIV_DATA , 0x0000},
146 {RT3261_DAC2_CTRL , 0x0000},
147 {RT3261_MONO_DAC_MIXER, 0x4444},
148 {RT3261_OUT_L3_MIXER, 0x01fd},
149 {RT3261_OUT_R3_MIXER, 0x01fd},
150 {RT3261_LOUT_MIXER, 0xc000},
152 // huangcun 20130816 e
154 #define RT3261_INIT_REG_LEN ARRAY_SIZE(init_list)
156 static int rt3261_reg_init(struct snd_soc_codec *codec)
160 for (i = 0; i < RT3261_INIT_REG_LEN; i++)
161 snd_soc_write(codec, init_list[i].reg, init_list[i].val);
166 static int rt3261_customer_redefine(struct snd_soc_codec *codec, struct rt3261_priv *rt3261)
168 if(rt3261->spk_num==TWO_SPK)
170 snd_soc_update_bits(codec, RT3261_SPO_L_MIXER,
171 RT3261_M_SV_R_SPM_L | RT3261_M_SV_L_SPM_L,
172 1 << RT3261_M_SV_R_SPM_L_SFT | 0 << RT3261_M_SV_L_SPM_L_SFT);
173 snd_soc_update_bits(codec, RT3261_SPO_R_MIXER,
174 RT3261_M_SV_R_SPM_R, 0 << RT3261_M_SV_R_SPM_R_SFT);
178 snd_soc_update_bits(codec, RT3261_SPO_L_MIXER,
179 RT3261_M_SV_R_SPM_L | RT3261_M_SV_L_SPM_L,
180 0 << RT3261_M_SV_R_SPM_L_SFT | 0 << RT3261_M_SV_L_SPM_L_SFT);
181 snd_soc_update_bits(codec, RT3261_SPO_R_MIXER,
182 RT3261_M_SV_R_SPM_R, 1 << RT3261_M_SV_R_SPM_R_SFT);
186 snd_soc_update_bits(codec, RT3261_IN3_IN4,
187 RT3261_IN_DF2, rt3261->modem_input_mode << RT3261_IN_SFT2);
188 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
189 RT3261_LOUT_DF_MASK, rt3261->lout_to_modem_mode << RT3261_LOUT_DF);
190 snd_soc_update_bits(codec, RT3261_SPO_CLSD_RATIO,
191 RT3261_SPO_CLSD_RATIO_MASK, rt3261->spk_amplify);
192 snd_soc_update_bits(codec, RT3261_DIG_INF_DATA,
193 RT3261_IF1_DAC_SEL_MASK | RT3261_IF2_DAC_SEL_MASK,
194 (rt3261->playback_if1_data_control<<RT3261_IF1_DAC_SEL_SFT) | (rt3261->playback_if2_data_control<<RT3261_IF2_DAC_SEL_SFT));
200 static int rt3261_index_sync(struct snd_soc_codec *codec)
204 for (i = 0; i < RT3261_INIT_REG_LEN; i++)
205 if (RT3261_PRIV_INDEX == init_list[i].reg ||
206 RT3261_PRIV_DATA == init_list[i].reg)
207 snd_soc_write(codec, init_list[i].reg,
212 static const u16 rt3261_reg[RT3261_VENDOR_ID2 + 1] = {
213 [RT3261_RESET] = 0x000c,
214 [RT3261_SPK_VOL] = 0xc8c8,
215 [RT3261_HP_VOL] = 0xc8c8,
216 [RT3261_OUTPUT] = 0xc8c8,
217 [RT3261_MONO_OUT] = 0x8000,
218 [RT3261_INL_INR_VOL] = 0x0808,
219 [RT3261_DAC1_DIG_VOL] = 0xafaf,
220 [RT3261_DAC2_DIG_VOL] = 0xafaf,
221 [RT3261_ADC_DIG_VOL] = 0x2f2f,
222 [RT3261_ADC_DATA] = 0x2f2f,
223 [RT3261_STO_ADC_MIXER] = 0x7060,
224 [RT3261_MONO_ADC_MIXER] = 0x7070,
225 [RT3261_AD_DA_MIXER] = 0x8080,
226 [RT3261_STO_DAC_MIXER] = 0x5454,
227 [RT3261_MONO_DAC_MIXER] = 0x5454,
228 [RT3261_DIG_MIXER] = 0xaa00,
229 [RT3261_DSP_PATH2] = 0xa000,
230 [RT3261_REC_L2_MIXER] = 0x007f,
231 [RT3261_REC_R2_MIXER] = 0x007f,
232 [RT3261_HPO_MIXER] = 0xe000,
233 [RT3261_SPK_L_MIXER] = 0x003e,
234 [RT3261_SPK_R_MIXER] = 0x003e,
235 [RT3261_SPO_L_MIXER] = 0xf800,
236 [RT3261_SPO_R_MIXER] = 0x3800,
237 [RT3261_SPO_CLSD_RATIO] = 0x0004,
238 [RT3261_MONO_MIXER] = 0xfc00,
239 [RT3261_OUT_L3_MIXER] = 0x01ff,
240 [RT3261_OUT_R3_MIXER] = 0x01ff,
241 [RT3261_LOUT_MIXER] = 0xf000,
242 [RT3261_PWR_ANLG1] = 0x00c0,
243 [RT3261_I2S1_SDP] = 0x8000,
244 [RT3261_I2S2_SDP] = 0x8000,
245 [RT3261_I2S3_SDP] = 0x8000,
246 [RT3261_ADDA_CLK1] = 0x1110,
247 [RT3261_ADDA_CLK2] = 0x0c00,
248 [RT3261_DMIC] = 0x1d00,
249 [RT3261_ASRC_3] = 0x0008,
250 [RT3261_HP_OVCD] = 0x0600,
251 [RT3261_CLS_D_OVCD] = 0x0228,
252 [RT3261_CLS_D_OUT] = 0xa800,
253 [RT3261_DEPOP_M1] = 0x0004,
254 [RT3261_DEPOP_M2] = 0x1100,
255 [RT3261_DEPOP_M3] = 0x0646,
256 [RT3261_CHARGE_PUMP] = 0x0c00,
257 [RT3261_MICBIAS] = 0x3000,
258 [RT3261_EQ_CTRL1] = 0x2080,
259 [RT3261_DRC_AGC_1] = 0x2206,
260 [RT3261_DRC_AGC_2] = 0x1f00,
261 [RT3261_ANC_CTRL1] = 0x034b,
262 [RT3261_ANC_CTRL2] = 0x0066,
263 [RT3261_ANC_CTRL3] = 0x000b,
264 [RT3261_GPIO_CTRL1] = 0x0400,
265 [RT3261_DSP_CTRL3] = 0x2000,
266 [RT3261_BASE_BACK] = 0x0013,
267 [RT3261_MP3_PLUS1] = 0x0680,
268 [RT3261_MP3_PLUS2] = 0x1c17,
269 [RT3261_3D_HP] = 0x8c00,
270 [RT3261_ADJ_HPF] = 0x2a20,
271 [RT3261_HP_CALIB_AMP_DET] = 0x0400,
272 [RT3261_SV_ZCD1] = 0x0809,
273 [RT3261_VENDOR_ID1] = 0x10ec,
274 [RT3261_VENDOR_ID2] = 0x6231,
277 static int rt3261_reset(struct snd_soc_codec *codec)
279 return snd_soc_write(codec, RT3261_RESET, 0);
282 static unsigned int rt3261_read(struct snd_soc_codec *codec,
287 val = codec->hw_read(codec, reg);
291 static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
292 unsigned int value, const void *data, int len)
294 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
297 if (!snd_soc_codec_volatile_register(codec, reg) &&
298 reg < codec->driver->reg_cache_size &&
299 !codec->cache_bypass) {
300 ret = snd_soc_cache_write(codec, reg, value);
305 if (codec->cache_only) {
306 codec->cache_sync = 1;
310 if (i2c_master_send(rt3261->i2c, data, len) == len)
316 static int rt3261_write(struct snd_soc_codec *codec, unsigned int reg,
322 data[1] = (value >> 8) & 0xff;
323 data[2] = value & 0xff;
325 DBG("rt3261_write 0x%x = 0x%x\n",reg,value);
327 return do_hw_write(codec, reg, value, data, 3);
331 * rt3261_index_write - Write private register.
332 * @codec: SoC audio codec device.
333 * @reg: Private register index.
334 * @value: Private register Data.
336 * Modify private register for advanced setting. It can be written through
337 * private index (0x6a) and data (0x6c) register.
339 * Returns 0 for success or negative error code.
341 static int rt3261_index_write(struct snd_soc_codec *codec,
342 unsigned int reg, unsigned int value)
346 ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
348 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
351 ret = snd_soc_write(codec, RT3261_PRIV_DATA, value);
353 dev_err(codec->dev, "Failed to set private value: %d\n", ret);
363 * rt3261_index_read - Read private register.
364 * @codec: SoC audio codec device.
365 * @reg: Private register index.
367 * Read advanced setting from private register. It can be read through
368 * private index (0x6a) and data (0x6c) register.
370 * Returns private register value or negative error code.
372 static unsigned int rt3261_index_read(
373 struct snd_soc_codec *codec, unsigned int reg)
377 ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
379 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
382 return snd_soc_read(codec, RT3261_PRIV_DATA);
386 * rt3261_index_update_bits - update private register bits
387 * @codec: audio codec
388 * @reg: Private register index.
389 * @mask: register mask
392 * Writes new register value.
394 * Returns 1 for change, 0 for no change, or negative error code.
396 static int rt3261_index_update_bits(struct snd_soc_codec *codec,
397 unsigned int reg, unsigned int mask, unsigned int value)
399 unsigned int old, new;
402 ret = rt3261_index_read(codec, reg);
404 dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
409 new = (old & ~mask) | (value & mask);
412 ret = rt3261_index_write(codec, reg, new);
415 "Failed to write private reg: %d\n", ret);
425 static int rt3261_volatile_register(
426 struct snd_soc_codec *codec, unsigned int reg)
430 case RT3261_PRIV_DATA:
432 case RT3261_EQ_CTRL1:
433 case RT3261_DRC_AGC_1:
434 case RT3261_ANC_CTRL1:
435 case RT3261_IRQ_CTRL2:
436 case RT3261_INT_IRQ_ST:
437 case RT3261_DSP_CTRL2:
438 case RT3261_DSP_CTRL3:
439 case RT3261_PGM_REG_ARR1:
440 case RT3261_PGM_REG_ARR3:
441 case RT3261_VENDOR_ID:
442 case RT3261_VENDOR_ID1:
443 case RT3261_VENDOR_ID2:
450 static int rt3261_readable_register(
451 struct snd_soc_codec *codec, unsigned int reg)
458 case RT3261_MONO_OUT:
461 case RT3261_INL_INR_VOL:
462 case RT3261_DAC1_DIG_VOL:
463 case RT3261_DAC2_DIG_VOL:
464 case RT3261_DAC2_CTRL:
465 case RT3261_ADC_DIG_VOL:
466 case RT3261_ADC_DATA:
467 case RT3261_ADC_BST_VOL:
468 case RT3261_STO_ADC_MIXER:
469 case RT3261_MONO_ADC_MIXER:
470 case RT3261_AD_DA_MIXER:
471 case RT3261_STO_DAC_MIXER:
472 case RT3261_MONO_DAC_MIXER:
473 case RT3261_DIG_MIXER:
474 case RT3261_DSP_PATH1:
475 case RT3261_DSP_PATH2:
476 case RT3261_DIG_INF_DATA:
477 case RT3261_REC_L1_MIXER:
478 case RT3261_REC_L2_MIXER:
479 case RT3261_REC_R1_MIXER:
480 case RT3261_REC_R2_MIXER:
481 case RT3261_HPO_MIXER:
482 case RT3261_SPK_L_MIXER:
483 case RT3261_SPK_R_MIXER:
484 case RT3261_SPO_L_MIXER:
485 case RT3261_SPO_R_MIXER:
486 case RT3261_SPO_CLSD_RATIO:
487 case RT3261_MONO_MIXER:
488 case RT3261_OUT_L1_MIXER:
489 case RT3261_OUT_L2_MIXER:
490 case RT3261_OUT_L3_MIXER:
491 case RT3261_OUT_R1_MIXER:
492 case RT3261_OUT_R2_MIXER:
493 case RT3261_OUT_R3_MIXER:
494 case RT3261_LOUT_MIXER:
495 case RT3261_PWR_DIG1:
496 case RT3261_PWR_DIG2:
497 case RT3261_PWR_ANLG1:
498 case RT3261_PWR_ANLG2:
499 case RT3261_PWR_MIXER:
501 case RT3261_PRIV_INDEX:
502 case RT3261_PRIV_DATA:
503 case RT3261_I2S1_SDP:
504 case RT3261_I2S2_SDP:
505 case RT3261_I2S3_SDP:
506 case RT3261_ADDA_CLK1:
507 case RT3261_ADDA_CLK2:
510 case RT3261_PLL_CTRL1:
511 case RT3261_PLL_CTRL2:
518 case RT3261_CLS_D_OVCD:
519 case RT3261_CLS_D_OUT:
520 case RT3261_DEPOP_M1:
521 case RT3261_DEPOP_M2:
522 case RT3261_DEPOP_M3:
523 case RT3261_CHARGE_PUMP:
524 case RT3261_PV_DET_SPK_G:
526 case RT3261_EQ_CTRL1:
527 case RT3261_EQ_CTRL2:
528 case RT3261_WIND_FILTER:
529 case RT3261_DRC_AGC_1:
530 case RT3261_DRC_AGC_2:
531 case RT3261_DRC_AGC_3:
533 case RT3261_ANC_CTRL1:
534 case RT3261_ANC_CTRL2:
535 case RT3261_ANC_CTRL3:
538 case RT3261_IRQ_CTRL1:
539 case RT3261_IRQ_CTRL2:
540 case RT3261_INT_IRQ_ST:
541 case RT3261_GPIO_CTRL1:
542 case RT3261_GPIO_CTRL2:
543 case RT3261_GPIO_CTRL3:
544 case RT3261_DSP_CTRL1:
545 case RT3261_DSP_CTRL2:
546 case RT3261_DSP_CTRL3:
547 case RT3261_DSP_CTRL4:
548 case RT3261_PGM_REG_ARR1:
549 case RT3261_PGM_REG_ARR2:
550 case RT3261_PGM_REG_ARR3:
551 case RT3261_PGM_REG_ARR4:
552 case RT3261_PGM_REG_ARR5:
553 case RT3261_SCB_FUNC:
554 case RT3261_SCB_CTRL:
555 case RT3261_BASE_BACK:
556 case RT3261_MP3_PLUS1:
557 case RT3261_MP3_PLUS2:
560 case RT3261_HP_CALIB_AMP_DET:
561 case RT3261_HP_CALIB2:
564 case RT3261_GEN_CTRL1:
565 case RT3261_GEN_CTRL2:
566 case RT3261_GEN_CTRL3:
567 case RT3261_VENDOR_ID:
568 case RT3261_VENDOR_ID1:
569 case RT3261_VENDOR_ID2:
577 * rt3261_headset_mic_detect - Detect headset.
578 * @codec: SoC audio codec device.
579 * @jack_insert: Jack insert or not.
581 * Detect whether is headset or not when jack inserted.
583 * Returns detect status.
585 int rt3261_headset_mic_detect(int jack_insert)
592 if(rt3261_codec == NULL){
597 if (SND_SOC_BIAS_OFF == rt3261_codec->dapm.bias_level) {
598 snd_soc_write(rt3261_codec, RT3261_PWR_ANLG1, 0x2004);
599 snd_soc_write(rt3261_codec, RT3261_MICBIAS, 0x3830);
600 snd_soc_write(rt3261_codec, RT3261_GEN_CTRL1 , 0x3701);
603 sclk_src = snd_soc_read(rt3261_codec, RT3261_GLB_CLK) &
604 RT3261_SCLK_SRC_MASK;
605 snd_soc_update_bits(rt3261_codec, RT3261_GLB_CLK,
606 RT3261_SCLK_SRC_MASK, 0x3 << RT3261_SCLK_SRC_SFT);
608 snd_soc_update_bits(rt3261_codec, RT3261_PWR_ANLG1,
609 RT3261_PWR_LDO2, RT3261_PWR_LDO2);
610 snd_soc_update_bits(rt3261_codec, RT3261_PWR_ANLG2,
611 RT3261_PWR_MB1, RT3261_PWR_MB1);
613 snd_soc_update_bits(rt3261_codec, RT3261_MICBIAS,
614 RT3261_MIC1_OVCD_MASK | RT3261_MIC1_OVTH_MASK |
615 RT3261_PWR_CLK25M_MASK | RT3261_PWR_MB_MASK,
616 RT3261_MIC1_OVCD_EN | RT3261_MIC1_OVTH_600UA |
617 RT3261_PWR_MB_PU | RT3261_PWR_CLK25M_PU);
618 snd_soc_update_bits(rt3261_codec, RT3261_GEN_CTRL1,
621 if (snd_soc_read(rt3261_codec, RT3261_IRQ_CTRL2) & 0x8)
622 jack_type = RT3261_HEADPHO_DET;
624 jack_type = RT3261_HEADSET_DET;
625 snd_soc_update_bits(rt3261_codec, RT3261_IRQ_CTRL2,
626 RT3261_MB1_OC_CLR, 0);
628 snd_soc_update_bits(rt3261_codec, RT3261_GLB_CLK,
629 RT3261_SCLK_SRC_MASK, sclk_src);
632 snd_soc_update_bits(rt3261_codec, RT3261_MICBIAS,
633 RT3261_MIC1_OVCD_MASK,
634 RT3261_MIC1_OVCD_DIS);
636 jack_type = RT3261_NO_JACK;
641 EXPORT_SYMBOL(rt3261_headset_mic_detect);
643 static const char *rt3261_dacr2_src[] = { "TxDC_R", "TxDP_R" };
645 static const SOC_ENUM_SINGLE_DECL(rt3261_dacr2_enum,RT3261_DUMMY_PR3F,
646 14, rt3261_dacr2_src);
647 static const struct snd_kcontrol_new rt3261_dacr2_mux =
648 SOC_DAPM_ENUM("Mono dacr source", rt3261_dacr2_enum);
650 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
651 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
652 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
653 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
654 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
656 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
657 static unsigned int bst_tlv[] = {
658 TLV_DB_RANGE_HEAD(7),
659 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
660 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
661 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
662 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
663 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
664 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
665 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
668 static int rt3261_dmic_get(struct snd_kcontrol *kcontrol,
669 struct snd_ctl_elem_value *ucontrol)
671 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
672 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
674 ucontrol->value.integer.value[0] = rt3261->dmic_en;
679 static int rt3261_dmic_put(struct snd_kcontrol *kcontrol,
680 struct snd_ctl_elem_value *ucontrol)
682 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
683 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
685 if (rt3261->dmic_en == ucontrol->value.integer.value[0])
688 rt3261->dmic_en = ucontrol->value.integer.value[0];
689 switch (rt3261->dmic_en) {
690 case RT3261_DMIC_DIS:
691 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
692 RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK |
694 RT3261_GP2_PIN_GPIO2 | RT3261_GP3_PIN_GPIO3 |
695 RT3261_GP4_PIN_GPIO4);
696 snd_soc_update_bits(codec, RT3261_DMIC,
697 RT3261_DMIC_1_DP_MASK | RT3261_DMIC_2_DP_MASK,
698 RT3261_DMIC_1_DP_GPIO3 | RT3261_DMIC_2_DP_GPIO4);
699 snd_soc_update_bits(codec, RT3261_DMIC,
700 RT3261_DMIC_1_EN_MASK | RT3261_DMIC_2_EN_MASK,
701 RT3261_DMIC_1_DIS | RT3261_DMIC_2_DIS);
705 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
706 RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK,
707 RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP3_PIN_DMIC1_SDA);
708 snd_soc_update_bits(codec, RT3261_DMIC,
709 RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK |
710 RT3261_DMIC_1_DP_MASK,
711 RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING |
712 RT3261_DMIC_1_DP_IN1P);
713 snd_soc_update_bits(codec, RT3261_DMIC,
714 RT3261_DMIC_1_EN_MASK, RT3261_DMIC_1_EN);
718 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
719 RT3261_GP2_PIN_MASK | RT3261_GP4_PIN_MASK,
720 RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP4_PIN_DMIC2_SDA);
721 snd_soc_update_bits(codec, RT3261_DMIC,
722 RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK |
723 RT3261_DMIC_2_DP_MASK,
724 RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING |
725 RT3261_DMIC_2_DP_IN1N);
726 snd_soc_update_bits(codec, RT3261_DMIC,
727 RT3261_DMIC_2_EN_MASK, RT3261_DMIC_2_EN);
737 static int rt3261_asrc_get(struct snd_kcontrol *kcontrol,
738 struct snd_ctl_elem_value *ucontrol)
740 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
741 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
743 DBG("%s\n", __FUNCTION__);
744 ucontrol->value.integer.value[0] = rt3261->asrc_en;
749 static int rt3261_asrc_put(struct snd_kcontrol *kcontrol,
750 struct snd_ctl_elem_value *ucontrol)
752 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
753 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
755 DBG("%s\n", __FUNCTION__);
756 if (rt3261->asrc_en == ucontrol->value.integer.value[0])
759 rt3261->asrc_en = ucontrol->value.integer.value[0];
760 switch (rt3261->asrc_en) {
761 case RT3261_ASRC_DIS://disable ASRC
762 DBG("%s disable\n", __FUNCTION__);
763 snd_soc_write(codec, RT3261_ASRC_1, 0x0);
764 snd_soc_write(codec, RT3261_ASRC_2, 0x0);
765 snd_soc_update_bits(codec, RT3261_GEN_CTRL1, 0x70, 0x0); //bard 8-29
766 mutex_lock(&codec->mutex);
767 snd_soc_dapm_disable_pin(&codec->dapm, "DAC L2 Power"); //bard 9-4
768 snd_soc_dapm_disable_pin(&codec->dapm, "stereo filter"); //bard 9-4
769 snd_soc_dapm_sync(&codec->dapm); //bard 9-4
770 mutex_unlock(&codec->mutex);
773 case RT3261_ASRC_EN://enable ASRC
774 DBG("%s enable\n", __FUNCTION__);
775 snd_soc_write(codec, RT3261_ASRC_1, 0x9800);
776 snd_soc_write(codec, RT3261_ASRC_2, 0xF800);
777 snd_soc_update_bits(codec, RT3261_GEN_CTRL1, 0x70, 0x70); //bard 8-29
778 snd_soc_write(codec, RT3261_JD_CTRL, 0x03); //bard 8-29
779 //snd_soc_update_bits(codec, RT3261_PWR_DIG1, 0x0080, 0x0080);
780 //snd_soc_update_bits(codec, RT3261_PWR_DIG2, 0x8000, 0x8000);
781 mutex_lock(&codec->mutex);
782 snd_soc_dapm_force_enable_pin(&codec->dapm, "DAC L2 Power"); //bard 9-4
783 snd_soc_dapm_force_enable_pin(&codec->dapm, "stereo filter"); //bard 9-4
784 snd_soc_dapm_sync(&codec->dapm); //bard 9-4
785 mutex_unlock(&codec->mutex);
786 snd_soc_write(codec, RT3261_ADDA_CLK1, 0x1114);
797 static int rt3261_mic1_get(struct snd_kcontrol *kcontrol,
798 struct snd_ctl_elem_value *ucontrol)
800 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
802 ucontrol->value.integer.value[0] =
803 (snd_soc_read(codec, RT3261_REC_L2_MIXER) & RT3261_M_BST1_RM_L) >> RT3261_M_BST1_RM_L_SFT;
808 static int rt3261_mic1_put(struct snd_kcontrol *kcontrol,
809 struct snd_ctl_elem_value *ucontrol)
811 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
813 if(ucontrol->value.integer.value[0]==0) {
814 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
815 RT3261_M_BST1_RM_L, 0);
816 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
817 RT3261_M_BST1_RM_R, 0);
819 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
820 RT3261_M_BST1_RM_L, RT3261_M_BST1_RM_L);
821 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
822 RT3261_M_BST1_RM_R, RT3261_M_BST1_RM_R);
828 static int rt3261_mic2_get(struct snd_kcontrol *kcontrol,
829 struct snd_ctl_elem_value *ucontrol)
831 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
833 ucontrol->value.integer.value[0] =
834 (snd_soc_read(codec, RT3261_REC_L2_MIXER) & RT3261_M_BST1_RM_L) >> RT3261_M_BST1_RM_L_SFT;
839 static int rt3261_mic2_put(struct snd_kcontrol *kcontrol,
840 struct snd_ctl_elem_value *ucontrol)
842 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
844 if(ucontrol->value.integer.value[0]==0) {
845 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
846 RT3261_M_BST4_RM_L, 0);
847 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
848 RT3261_M_BST4_RM_R, 0);
850 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
851 RT3261_M_BST4_RM_L, RT3261_M_BST4_RM_L);
852 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
853 RT3261_M_BST4_RM_R, RT3261_M_BST4_RM_R);
860 void rt3261_hp_amp_power(struct snd_soc_codec *codec, int on)
862 static int hp_amp_power_count;
863 DBG("rt3261_hp_amp_power on=%d hp_amp_power_count=%d\n",on,hp_amp_power_count);
866 if(hp_amp_power_count <= 0) {
867 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
868 RT3261_PWR_I2S1, RT3261_PWR_I2S1);
869 /* depop parameters */
870 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0200); //bard 12-6
871 snd_soc_write(codec, RT3261_DEPOP_M2, 0x3100); //bard 4-22
872 snd_soc_write(codec, RT3261_DEPOP_M1, 0x0009); //bard 4-22
875 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
876 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
877 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
878 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
879 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
881 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
882 /* headphone amp power on */
883 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
884 RT3261_PWR_FV1 | RT3261_PWR_FV2 , 0);
885 snd_soc_update_bits(codec, RT3261_PWR_VOL,
886 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
887 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
888 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
889 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA , //bard 10-18
890 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA); //bard 10-18
891 msleep(30); //bard 4-22
892 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
893 RT3261_PWR_FV1 | RT3261_PWR_FV2,
894 RT3261_PWR_FV1 | RT3261_PWR_FV2);
896 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
897 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
898 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
899 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
900 RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
901 RT3261_HP_CO_EN | RT3261_HP_SG_EN);
902 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0400); //bard 12-6
904 hp_amp_power_count++;
906 hp_amp_power_count--;
907 if(hp_amp_power_count <= 0) {
908 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
909 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
910 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
911 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
912 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
913 /* headphone amp power down */
914 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
915 RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
916 RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
917 RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
918 RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
919 RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
920 RT3261_HP_SG_EN | RT3261_HP_CB_PD);
921 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
922 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA , //bard 10-18
928 static int rt3261_hp_mute_get(struct snd_kcontrol *kcontrol,
929 struct snd_ctl_elem_value *ucontrol)
931 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
933 ucontrol->value.integer.value[0] =
934 !((snd_soc_read(codec, RT3261_HP_VOL) & RT3261_L_MUTE) >> RT3261_L_MUTE_SFT);
939 static int rt3261_hp_mute_put(struct snd_kcontrol *kcontrol,
940 struct snd_ctl_elem_value *ucontrol)
942 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
944 if(ucontrol->value.integer.value[0]) {
945 /* headphone unmute sequence */
947 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
948 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
949 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
950 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
951 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
952 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
953 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
954 RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
955 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
956 RT3261_RSTN_MASK, RT3261_RSTN_EN);
957 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
958 RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
959 RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
960 //snd_soc_update_bits(codec, RT3261_HP_VOL,
961 // RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
962 msleep(60); //bard 4-22
963 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
964 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
965 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
966 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
969 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
970 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
973 /* headphone mute sequence */
974 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
975 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
976 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
977 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
978 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
979 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
980 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
981 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
982 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
983 RT3261_RSTP_MASK, RT3261_RSTP_EN);
984 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
985 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
986 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
987 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
989 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
990 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
993 snd_soc_update_bits(codec, RT3261_HP_VOL,
994 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
997 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
998 RT3261_HP_R_SMT_MASK | RT3261_HP_L_SMT_MASK,
999 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
1005 #if defined (CONFIG_SND_SOC_RT5623)
1006 static int rt3261_modem_input_switch_get(struct snd_kcontrol *kcontrol,
1007 struct snd_ctl_elem_value *ucontrol)
1009 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1010 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
1012 ucontrol->value.integer.value[0] = rt3261->modem_is_open;
1016 static int rt3261_modem_input_switch_put(struct snd_kcontrol *kcontrol,
1017 struct snd_ctl_elem_value *ucontrol)
1019 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1020 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
1022 if(ucontrol->value.integer.value[0]) {
1024 rt3261->modem_is_open = 1;
1027 rt3261->modem_is_open = 0;
1033 static int rt3261_modem_input_switch_get(struct snd_kcontrol *kcontrol,
1034 struct snd_ctl_elem_value *ucontrol)
1039 static int rt3261_modem_input_switch_put(struct snd_kcontrol *kcontrol,
1040 struct snd_ctl_elem_value *ucontrol)
1046 static int rt3261_dacr_sel_get(struct snd_kcontrol *kcontrol,
1047 struct snd_ctl_elem_value *ucontrol)
1049 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1051 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x4000) >> 14;
1056 static int rt3261_dacr_sel_put(struct snd_kcontrol *kcontrol,
1057 struct snd_ctl_elem_value *ucontrol)
1059 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1061 if(ucontrol->value.integer.value[0])
1062 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x4000, 0x4000);
1064 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x4000, 0x0);
1070 static int rt3261_rxdp_sel_get(struct snd_kcontrol *kcontrol,
1071 struct snd_ctl_elem_value *ucontrol)
1073 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1075 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x0400) >> 10;
1080 static int rt3261_rxdp_sel_put(struct snd_kcontrol *kcontrol,
1081 struct snd_ctl_elem_value *ucontrol)
1083 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1085 if(ucontrol->value.integer.value[0])
1086 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0400, 0x0400);
1088 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0400, 0x0);
1094 static int rt3261_rxdp1_sel_get(struct snd_kcontrol *kcontrol,
1095 struct snd_ctl_elem_value *ucontrol)
1097 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1099 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x0200) >> 9;
1104 static int rt3261_rxdp1_sel_put(struct snd_kcontrol *kcontrol,
1105 struct snd_ctl_elem_value *ucontrol)
1107 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1109 if(ucontrol->value.integer.value[0])
1110 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0200, 0x0200);
1112 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0200, 0x0);
1118 /* IN1/IN2 Input Type */
1119 static const char *rt3261_input_mode[] = {
1120 "Single ended", "Differential"};
1122 static const SOC_ENUM_SINGLE_DECL(
1123 rt3261_in1_mode_enum, RT3261_IN1_IN2,
1124 RT3261_IN_SFT1, rt3261_input_mode);
1126 static const SOC_ENUM_SINGLE_DECL(
1127 rt3261_in2_mode_enum, RT3261_IN3_IN4,
1128 RT3261_IN_SFT2, rt3261_input_mode);
1130 static const SOC_ENUM_SINGLE_DECL(
1131 rt3261_in3_mode_enum, RT3261_IN1_IN2,
1132 RT3261_IN_SFT2, rt3261_input_mode);
1135 static const char *rt3261_output_mode[] = {
1136 "Single ended", "Differential"};
1138 static const SOC_ENUM_SINGLE_DECL(
1139 rt3261_lout_mode_enum, RT3261_GEN_CTRL1,
1140 RT3261_LOUT_DF, rt3261_output_mode);
1143 /* Interface data select */
1144 static const char *rt3261_data_select[] = {
1145 "Normal", "Swap", "left copy to right", "right copy to left"};
1147 static const SOC_ENUM_SINGLE_DECL(rt3261_if1_dac_enum, RT3261_DIG_INF_DATA,
1148 RT3261_IF1_DAC_SEL_SFT, rt3261_data_select);
1150 static const SOC_ENUM_SINGLE_DECL(rt3261_if1_adc_enum, RT3261_DIG_INF_DATA,
1151 RT3261_IF1_ADC_SEL_SFT, rt3261_data_select);
1153 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_dac_enum, RT3261_DIG_INF_DATA,
1154 RT3261_IF2_DAC_SEL_SFT, rt3261_data_select);
1156 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_enum, RT3261_DIG_INF_DATA,
1157 RT3261_IF2_ADC_SEL_SFT, rt3261_data_select);
1159 static const SOC_ENUM_SINGLE_DECL(rt3261_if3_dac_enum, RT3261_DIG_INF_DATA,
1160 RT3261_IF3_DAC_SEL_SFT, rt3261_data_select);
1162 static const SOC_ENUM_SINGLE_DECL(rt3261_if3_adc_enum, RT3261_DIG_INF_DATA,
1163 RT3261_IF3_ADC_SEL_SFT, rt3261_data_select);
1165 /* Class D speaker gain ratio */
1166 static const char *rt3261_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
1167 "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
1169 static const SOC_ENUM_SINGLE_DECL(
1170 rt3261_clsd_spk_ratio_enum, RT3261_CLS_D_OUT,
1171 RT3261_CLSD_RATIO_SFT, rt3261_clsd_spk_ratio);
1174 static const char *rt3261_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
1176 static const SOC_ENUM_SINGLE_DECL(rt3261_dmic_enum, 0, 0, rt3261_dmic_mode);
1178 static const char *rt3261_asrc_mode[] = {"Disable", "Enable"};
1180 static const SOC_ENUM_SINGLE_DECL(rt3261_asrc_enum, 0, 0, rt3261_asrc_mode);
1183 static const char *rt3261_dacr_sel_mode[] = {"IF2_DAC", "IF2_ADC"};
1185 static const SOC_ENUM_SINGLE_DECL(rt3261_dacr_sel_enum, 0, 0, rt3261_dacr_sel_mode);
1187 static const char *rt3261_rxdp_sel_mode[] = {"RxDP2", "RxDP1"};
1189 static const SOC_ENUM_SINGLE_DECL(rt3261_rxdp_sel_enum, 0, 0, rt3261_rxdp_sel_mode);
1191 static const char *rt3261_rxdp1_sel_mode[] = {"DAC1", "IF1_DAC"};
1193 static const SOC_ENUM_SINGLE_DECL(rt3261_rxdp1_sel_enum, 0, 0, rt3261_rxdp1_sel_mode);
1197 static const char *rt3261_mic_mode[] = {"off", "on",};
1198 static const SOC_ENUM_SINGLE_DECL(rt3261_mic_enum, 0, 0, rt3261_mic_mode);
1201 static const char *rt3261_hp_mute_mode[] = {"off", "on",};
1203 static const SOC_ENUM_SINGLE_DECL(rt3261_hp_mute_enum, 0, 0, rt3261_hp_mute_mode);
1205 static const char *rt3261_modem_input_switch_mode[] = {"off", "on",};
1207 static const SOC_ENUM_SINGLE_DECL(rt3261_modem_input_switch_enum, 0, 0, rt3261_modem_input_switch_mode);
1209 #ifdef RT3261_REG_RW
1210 #define REGVAL_MAX 0xffff
1211 static unsigned int regctl_addr;
1212 static int rt3261_regctl_info(struct snd_kcontrol *kcontrol,
1213 struct snd_ctl_elem_info *uinfo)
1215 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1217 uinfo->value.integer.min = 0;
1218 uinfo->value.integer.max = REGVAL_MAX;
1222 static int rt3261_regctl_get(struct snd_kcontrol *kcontrol,
1223 struct snd_ctl_elem_value *ucontrol)
1225 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1226 ucontrol->value.integer.value[0] = regctl_addr;
1227 ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
1231 static int rt3261_regctl_put(struct snd_kcontrol *kcontrol,
1232 struct snd_ctl_elem_value *ucontrol)
1234 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1235 regctl_addr = ucontrol->value.integer.value[0];
1236 if(ucontrol->value.integer.value[1] <= REGVAL_MAX)
1237 snd_soc_write(codec, regctl_addr, ucontrol->value.integer.value[1]);
1243 static int rt3261_vol_rescale_get(struct snd_kcontrol *kcontrol,
1244 struct snd_ctl_elem_value *ucontrol)
1246 struct soc_mixer_control *mc =
1247 (struct soc_mixer_control *)kcontrol->private_value;
1248 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1249 unsigned int val = snd_soc_read(codec, mc->reg);
1251 ucontrol->value.integer.value[0] = RT3261_VOL_RSCL_MAX -
1252 ((val & RT3261_L_VOL_MASK) >> mc->shift);
1253 ucontrol->value.integer.value[1] = RT3261_VOL_RSCL_MAX -
1254 (val & RT3261_R_VOL_MASK);
1259 static int rt3261_vol_rescale_put(struct snd_kcontrol *kcontrol,
1260 struct snd_ctl_elem_value *ucontrol)
1262 struct soc_mixer_control *mc =
1263 (struct soc_mixer_control *)kcontrol->private_value;
1264 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1265 unsigned int val, val2;
1267 val = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[0];
1268 val2 = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[1];
1269 return snd_soc_update_bits_locked(codec, mc->reg, RT3261_L_VOL_MASK |
1270 RT3261_R_VOL_MASK, val << mc->shift | val2);
1274 static const struct snd_kcontrol_new rt3261_snd_controls[] = {
1275 /* Speaker Output Volume */
1276 SOC_DOUBLE("Speaker Playback Switch", RT3261_SPK_VOL,
1277 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1278 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT3261_SPK_VOL,
1279 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1280 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1281 SOC_DOUBLE_EXT_TLV("Earpiece Playback Volume", RT3261_SPK_VOL,
1282 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1283 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1284 /* Headphone Output Volume */
1286 SOC_DOUBLE("HP Playback Switch", RT3261_HP_VOL,
1287 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1289 SOC_DOUBLE_EXT_TLV("Headphone Playback Volume", RT3261_HP_VOL,
1290 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1291 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1292 /* OUTPUT Control */
1293 SOC_DOUBLE("OUT Playback Switch", RT3261_OUTPUT,
1294 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1295 SOC_DOUBLE("OUT Channel Switch", RT3261_OUTPUT,
1296 RT3261_VOL_L_SFT, RT3261_VOL_R_SFT, 1, 1),
1297 SOC_DOUBLE_TLV("OUT Playback Volume", RT3261_OUTPUT,
1298 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, 39, 1, out_vol_tlv),
1299 /* MONO Output Control */
1300 SOC_SINGLE("Mono Playback Switch", RT3261_MONO_OUT,
1301 RT3261_L_MUTE_SFT, 1, 1),
1302 /* DAC Digital Volume */
1303 SOC_DOUBLE("DAC2 Playback Switch", RT3261_DAC2_CTRL,
1304 RT3261_M_DAC_L2_VOL_SFT, RT3261_M_DAC_R2_VOL_SFT, 1, 1),
1305 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT3261_DAC1_DIG_VOL,
1306 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1307 175, 0, dac_vol_tlv),
1308 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT3261_DAC2_DIG_VOL,
1309 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1310 175, 0, dac_vol_tlv),
1311 /* IN1/IN2 Control */
1312 SOC_ENUM("IN1 Mode Control", rt3261_in1_mode_enum),
1313 SOC_SINGLE_TLV("IN1 Boost", RT3261_IN1_IN2,
1314 RT3261_BST_SFT1, 8, 0, bst_tlv),
1315 SOC_ENUM("IN2 Mode Control", rt3261_in2_mode_enum),
1316 SOC_SINGLE_TLV("IN2 Boost", RT3261_IN3_IN4,
1317 RT3261_BST_SFT2, 8, 0, bst_tlv),
1318 SOC_ENUM("IN3 Mode Control", rt3261_in3_mode_enum),
1319 SOC_SINGLE_TLV("IN3 Boost", RT3261_IN1_IN2,
1320 RT3261_BST_SFT2, 8, 0, bst_tlv),
1322 SOC_ENUM("LOUT Mode Control", rt3261_lout_mode_enum),
1323 /* INL/INR Volume Control */
1324 SOC_DOUBLE_TLV("IN Capture Volume", RT3261_INL_INR_VOL,
1325 RT3261_INL_VOL_SFT, RT3261_INR_VOL_SFT,
1327 /* ADC Digital Volume Control */
1328 SOC_DOUBLE("ADC Capture Switch", RT3261_ADC_DIG_VOL,
1329 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1330 SOC_DOUBLE_TLV("ADC Capture Volume", RT3261_ADC_DIG_VOL,
1331 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1332 127, 0, adc_vol_tlv),
1333 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT3261_ADC_DATA,
1334 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1335 127, 0, adc_vol_tlv),
1336 /* ADC Boost Volume Control */
1337 SOC_DOUBLE_TLV("ADC Boost Gain", RT3261_ADC_BST_VOL,
1338 RT3261_ADC_L_BST_SFT, RT3261_ADC_R_BST_SFT,
1340 /* Class D speaker gain ratio */
1341 SOC_ENUM("Class D SPK Ratio Control", rt3261_clsd_spk_ratio_enum),
1343 SOC_ENUM_EXT("DMIC Switch", rt3261_dmic_enum,
1344 rt3261_dmic_get, rt3261_dmic_put),
1346 SOC_ENUM_EXT("ASRC Switch", rt3261_asrc_enum,
1347 rt3261_asrc_get, rt3261_asrc_put),
1349 SOC_ENUM_EXT("DACR Select", rt3261_dacr_sel_enum,
1350 rt3261_dacr_sel_get, rt3261_dacr_sel_put),
1351 SOC_ENUM_EXT("RxDP Select", rt3261_rxdp_sel_enum,
1352 rt3261_rxdp_sel_get, rt3261_rxdp_sel_put),
1353 SOC_ENUM_EXT("RxDP1 Select", rt3261_rxdp1_sel_enum,
1354 rt3261_rxdp1_sel_get, rt3261_rxdp1_sel_put),
1355 #ifdef RT3261_REG_RW
1357 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1358 .name = "Register Control",
1359 .info = rt3261_regctl_info,
1360 .get = rt3261_regctl_get,
1361 .put = rt3261_regctl_put,
1365 SOC_SINGLE_TLV("Main Mic Capture Volume", RT3261_IN1_IN2,
1366 RT3261_BST_SFT1, 8, 0, bst_tlv),
1367 SOC_SINGLE_TLV("Headset Mic Capture Volume", RT3261_IN3_IN4,
1368 RT3261_BST_SFT2, 8, 0, bst_tlv),
1369 SOC_ENUM_EXT("Main Mic Capture Switch", rt3261_mic_enum,
1370 rt3261_mic1_get, rt3261_mic1_put),
1371 SOC_ENUM_EXT("Headset Mic Capture Switch", rt3261_mic_enum,
1372 rt3261_mic2_get, rt3261_mic2_put),
1375 SOC_ENUM_EXT("HP mute Switch", rt3261_hp_mute_enum,
1376 rt3261_hp_mute_get, rt3261_hp_mute_put),
1378 SOC_ENUM_EXT("Modem Input Switch", rt3261_modem_input_switch_enum,
1379 rt3261_modem_input_switch_get, rt3261_modem_input_switch_put),
1381 SOC_ENUM("ADC IF1 Data Switch", rt3261_if1_adc_enum),
1382 SOC_ENUM("DAC IF1 Data Switch", rt3261_if1_dac_enum),
1383 SOC_ENUM("ADC IF2 Data Switch", rt3261_if2_adc_enum),
1384 SOC_ENUM("DAC IF2 Data Switch", rt3261_if2_dac_enum),
1388 * set_dmic_clk - Set parameter of dmic.
1391 * @kcontrol: The kcontrol of this widget.
1394 * Choose dmic clock between 1MHz and 3MHz.
1395 * It is better for clock to approximate 3MHz.
1397 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1398 struct snd_kcontrol *kcontrol, int event)
1400 struct snd_soc_codec *codec = w->codec;
1401 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
1402 int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
1404 rate = rt3261->lrck[rt3261->aif_pu] << 8;
1406 for (i = 0; i < ARRAY_SIZE(div); i++) {
1407 bound = div[i] * 3000000;
1410 temp = bound - rate;
1417 dev_err(codec->dev, "Failed to set DMIC clock\n");
1419 snd_soc_update_bits(codec, RT3261_DMIC, RT3261_DMIC_CLK_MASK,
1420 idx << RT3261_DMIC_CLK_SFT);
1424 static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
1425 struct snd_soc_dapm_widget *sink)
1429 val = snd_soc_read(source->codec, RT3261_GLB_CLK);
1430 val &= RT3261_SCLK_SRC_MASK;
1431 if (val == RT3261_SCLK_SRC_PLL1)
1438 static const struct snd_kcontrol_new rt3261_sto_adc_l_mix[] = {
1439 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
1440 RT3261_M_ADC_L1_SFT, 1, 1),
1441 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
1442 RT3261_M_ADC_L2_SFT, 1, 1),
1445 static const struct snd_kcontrol_new rt3261_sto_adc_r_mix[] = {
1446 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
1447 RT3261_M_ADC_R1_SFT, 1, 1),
1448 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
1449 RT3261_M_ADC_R2_SFT, 1, 1),
1452 static const struct snd_kcontrol_new rt3261_mono_adc_l_mix[] = {
1453 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
1454 RT3261_M_MONO_ADC_L1_SFT, 1, 1),
1455 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
1456 RT3261_M_MONO_ADC_L2_SFT, 1, 1),
1459 static const struct snd_kcontrol_new rt3261_mono_adc_r_mix[] = {
1460 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
1461 RT3261_M_MONO_ADC_R1_SFT, 1, 1),
1462 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
1463 RT3261_M_MONO_ADC_R2_SFT, 1, 1),
1466 static const struct snd_kcontrol_new rt3261_dac_l_mix[] = {
1467 SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
1468 RT3261_M_ADCMIX_L_SFT, 1, 1),
1469 SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
1470 RT3261_M_IF1_DAC_L_SFT, 1, 1),
1473 static const struct snd_kcontrol_new rt3261_dac_r_mix[] = {
1474 SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
1475 RT3261_M_ADCMIX_R_SFT, 1, 1),
1476 SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
1477 RT3261_M_IF1_DAC_R_SFT, 1, 1),
1480 static const struct snd_kcontrol_new rt3261_sto_dac_l_mix[] = {
1481 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_STO_DAC_MIXER,
1482 RT3261_M_DAC_L1_SFT, 1, 1),
1483 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_STO_DAC_MIXER,
1484 RT3261_M_DAC_L2_SFT, 1, 1),
1485 SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
1486 RT3261_M_ANC_DAC_L_SFT, 1, 1),
1489 static const struct snd_kcontrol_new rt3261_sto_dac_r_mix[] = {
1490 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_STO_DAC_MIXER,
1491 RT3261_M_DAC_R1_SFT, 1, 1),
1492 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_STO_DAC_MIXER,
1493 RT3261_M_DAC_R2_SFT, 1, 1),
1494 SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
1495 RT3261_M_ANC_DAC_R_SFT, 1, 1),
1498 static const struct snd_kcontrol_new rt3261_mono_dac_l_mix[] = {
1499 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_MONO_DAC_MIXER,
1500 RT3261_M_DAC_L1_MONO_L_SFT, 1, 1),
1501 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
1502 RT3261_M_DAC_L2_MONO_L_SFT, 1, 1),
1503 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
1504 RT3261_M_DAC_R2_MONO_L_SFT, 1, 1),
1507 static const struct snd_kcontrol_new rt3261_mono_dac_r_mix[] = {
1508 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_MONO_DAC_MIXER,
1509 RT3261_M_DAC_R1_MONO_R_SFT, 1, 1),
1510 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
1511 RT3261_M_DAC_R2_MONO_R_SFT, 1, 1),
1512 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
1513 RT3261_M_DAC_L2_MONO_R_SFT, 1, 1),
1516 static const struct snd_kcontrol_new rt3261_dig_l_mix[] = {
1517 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_DIG_MIXER,
1518 RT3261_M_STO_L_DAC_L_SFT, 1, 1),
1519 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_DIG_MIXER,
1520 RT3261_M_DAC_L2_DAC_L_SFT, 1, 1),
1523 static const struct snd_kcontrol_new rt3261_dig_r_mix[] = {
1524 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_DIG_MIXER,
1525 RT3261_M_STO_R_DAC_R_SFT, 1, 1),
1526 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_DIG_MIXER,
1527 RT3261_M_DAC_R2_DAC_R_SFT, 1, 1),
1530 /* Analog Input Mixer */
1531 static const struct snd_kcontrol_new rt3261_rec_l_mix[] = {
1532 SOC_DAPM_SINGLE("HPOL Switch", RT3261_REC_L2_MIXER,
1533 RT3261_M_HP_L_RM_L_SFT, 1, 1),
1534 SOC_DAPM_SINGLE("INL Switch", RT3261_REC_L2_MIXER,
1535 RT3261_M_IN_L_RM_L_SFT, 1, 1),
1536 SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_L2_MIXER,
1537 RT3261_M_BST2_RM_L, 1, 1),
1538 SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_L2_MIXER,
1539 RT3261_M_BST4_RM_L_SFT, 1, 1),
1540 SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_L2_MIXER,
1541 RT3261_M_BST1_RM_L_SFT, 1, 1),
1542 SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_REC_L2_MIXER,
1543 RT3261_M_OM_L_RM_L_SFT, 1, 1),
1546 static const struct snd_kcontrol_new rt3261_rec_r_mix[] = {
1547 SOC_DAPM_SINGLE("HPOR Switch", RT3261_REC_R2_MIXER,
1548 RT3261_M_HP_R_RM_R_SFT, 1, 1),
1549 SOC_DAPM_SINGLE("INR Switch", RT3261_REC_R2_MIXER,
1550 RT3261_M_IN_R_RM_R_SFT, 1, 1),
1551 SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_R2_MIXER,
1552 RT3261_M_BST2_RM_R_SFT, 1, 1),
1553 SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_R2_MIXER,
1554 RT3261_M_BST4_RM_R_SFT, 1, 1),
1555 SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_R2_MIXER,
1556 RT3261_M_BST1_RM_R_SFT, 1, 1),
1557 SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_REC_R2_MIXER,
1558 RT3261_M_OM_R_RM_R_SFT, 1, 1),
1561 /* Analog Output Mixer */
1562 static const struct snd_kcontrol_new rt3261_spk_l_mix[] = {
1563 SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_SPK_L_MIXER,
1564 RT3261_M_RM_L_SM_L_SFT, 1, 1),
1565 SOC_DAPM_SINGLE("INL Switch", RT3261_SPK_L_MIXER,
1566 RT3261_M_IN_L_SM_L_SFT, 1, 1),
1567 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPK_L_MIXER,
1568 RT3261_M_DAC_L1_SM_L_SFT, 1, 1),
1569 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_SPK_L_MIXER,
1570 RT3261_M_DAC_L2_SM_L_SFT, 1, 1),
1571 SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_SPK_L_MIXER,
1572 RT3261_M_OM_L_SM_L_SFT, 1, 1),
1575 static const struct snd_kcontrol_new rt3261_spk_r_mix[] = {
1576 SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_SPK_R_MIXER,
1577 RT3261_M_RM_R_SM_R_SFT, 1, 1),
1578 SOC_DAPM_SINGLE("INR Switch", RT3261_SPK_R_MIXER,
1579 RT3261_M_IN_R_SM_R_SFT, 1, 1),
1580 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPK_R_MIXER,
1581 RT3261_M_DAC_R1_SM_R_SFT, 1, 1),
1582 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_SPK_R_MIXER,
1583 RT3261_M_DAC_R2_SM_R_SFT, 1, 1),
1584 SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_SPK_R_MIXER,
1585 RT3261_M_OM_R_SM_R_SFT, 1, 1),
1588 static const struct snd_kcontrol_new rt3261_out_l_mix[] = {
1589 SOC_DAPM_SINGLE("SPK MIXL Switch", RT3261_OUT_L3_MIXER,
1590 RT3261_M_SM_L_OM_L_SFT, 1, 1),
1591 SOC_DAPM_SINGLE("BST3 Switch", RT3261_OUT_L3_MIXER,
1592 RT3261_M_BST2_OM_L_SFT, 1, 1),
1593 SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_L3_MIXER,
1594 RT3261_M_BST1_OM_L_SFT, 1, 1),
1595 SOC_DAPM_SINGLE("INL Switch", RT3261_OUT_L3_MIXER,
1596 RT3261_M_IN_L_OM_L_SFT, 1, 1),
1597 SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_OUT_L3_MIXER,
1598 RT3261_M_RM_L_OM_L_SFT, 1, 1),
1599 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_L3_MIXER,
1600 RT3261_M_DAC_R2_OM_L_SFT, 1, 1),
1601 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_L3_MIXER,
1602 RT3261_M_DAC_L2_OM_L_SFT, 1, 1),
1603 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_OUT_L3_MIXER,
1604 RT3261_M_DAC_L1_OM_L_SFT, 1, 1),
1607 static const struct snd_kcontrol_new rt3261_out_r_mix[] = {
1608 SOC_DAPM_SINGLE("SPK MIXR Switch", RT3261_OUT_R3_MIXER,
1609 RT3261_M_SM_L_OM_R_SFT, 1, 1),
1610 SOC_DAPM_SINGLE("BST3 Switch", RT3261_OUT_R3_MIXER,
1611 RT3261_M_BST2_OM_R_SFT, 1, 1),
1612 SOC_DAPM_SINGLE("BST2 Switch", RT3261_OUT_R3_MIXER,
1613 RT3261_M_BST4_OM_R_SFT, 1, 1),
1614 SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_R3_MIXER,
1615 RT3261_M_BST1_OM_R_SFT, 1, 1),
1616 SOC_DAPM_SINGLE("INR Switch", RT3261_OUT_R3_MIXER,
1617 RT3261_M_IN_R_OM_R_SFT, 1, 1),
1618 SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_OUT_R3_MIXER,
1619 RT3261_M_RM_R_OM_R_SFT, 1, 1),
1620 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_R3_MIXER,
1621 RT3261_M_DAC_L2_OM_R_SFT, 1, 1),
1622 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_R3_MIXER,
1623 RT3261_M_DAC_R2_OM_R_SFT, 1, 1),
1624 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_OUT_R3_MIXER,
1625 RT3261_M_DAC_R1_OM_R_SFT, 1, 1),
1628 static const struct snd_kcontrol_new rt3261_spo_l_mix[] = {
1630 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
1631 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1632 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
1633 RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
1635 SOC_DAPM_SINGLE("DAC Switch", RT3261_DUMMY_SPKMIXER,
1636 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1638 SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_L_MIXER,
1639 RT3261_M_SV_R_SPM_L_SFT, 1, 1),
1640 SOC_DAPM_SINGLE("SPKVOL L Switch", RT3261_SPO_L_MIXER,
1641 RT3261_M_SV_L_SPM_L_SFT, 1, 1),
1642 SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_L_MIXER,
1643 RT3261_M_BST1_SPM_L_SFT, 1, 1),
1646 static const struct snd_kcontrol_new rt3261_spo_dac_mix[] = {
1647 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
1648 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1649 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
1650 RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
1654 static const struct snd_kcontrol_new rt3261_spo_r_mix[] = {
1655 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_R_MIXER,
1656 RT3261_M_DAC_R1_SPM_R_SFT, 1, 1),
1657 SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_R_MIXER,
1658 RT3261_M_SV_R_SPM_R_SFT, 1, 1),
1659 SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_R_MIXER,
1660 RT3261_M_BST1_SPM_R_SFT, 1, 1),
1663 static const struct snd_kcontrol_new rt3261_hpo_mix[] = {
1664 SOC_DAPM_SINGLE("DAC2 Switch", RT3261_HPO_MIXER,
1665 RT3261_M_DAC2_HM_SFT, 1, 1),
1666 SOC_DAPM_SINGLE("DAC1 Switch", RT3261_HPO_MIXER,
1667 RT3261_M_DAC1_HM_SFT, 1, 1),
1668 SOC_DAPM_SINGLE("HPVOL Switch", RT3261_HPO_MIXER,
1669 RT3261_M_HPVOL_HM_SFT, 1, 1),
1672 static const struct snd_kcontrol_new rt3261_lout_mix[] = {
1673 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_LOUT_MIXER,
1674 RT3261_M_DAC_L1_LM_SFT, 1, 1),
1675 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_LOUT_MIXER,
1676 RT3261_M_DAC_R1_LM_SFT, 1, 1),
1677 SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_LOUT_MIXER,
1678 RT3261_M_OV_L_LM_SFT, 1, 1),
1679 SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_LOUT_MIXER,
1680 RT3261_M_OV_R_LM_SFT, 1, 1),
1683 static const struct snd_kcontrol_new rt3261_mono_mix[] = {
1684 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_MIXER,
1685 RT3261_M_DAC_R2_MM_SFT, 1, 1),
1686 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_MIXER,
1687 RT3261_M_DAC_L2_MM_SFT, 1, 1),
1688 SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_MONO_MIXER,
1689 RT3261_M_OV_R_MM_SFT, 1, 1),
1690 SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_MONO_MIXER,
1691 RT3261_M_OV_L_MM_SFT, 1, 1),
1692 SOC_DAPM_SINGLE("BST1 Switch", RT3261_MONO_MIXER,
1693 RT3261_M_BST1_MM_SFT, 1, 1),
1697 static const char *rt3261_inl_src[] = {"IN2P", "MonoP"};
1699 static const SOC_ENUM_SINGLE_DECL(
1700 rt3261_inl_enum, RT3261_INL_INR_VOL,
1701 RT3261_INL_SEL_SFT, rt3261_inl_src);
1703 static const struct snd_kcontrol_new rt3261_inl_mux =
1704 SOC_DAPM_ENUM("INL source", rt3261_inl_enum);
1706 static const char *rt3261_inr_src[] = {"IN2N", "MonoN"};
1708 static const SOC_ENUM_SINGLE_DECL(
1709 rt3261_inr_enum, RT3261_INL_INR_VOL,
1710 RT3261_INR_SEL_SFT, rt3261_inr_src);
1712 static const struct snd_kcontrol_new rt3261_inr_mux =
1713 SOC_DAPM_ENUM("INR source", rt3261_inr_enum);
1715 /* Stereo ADC source */
1716 static const char *rt3261_stereo_adc1_src[] = {"DIG MIX", "ADC"};
1718 static const SOC_ENUM_SINGLE_DECL(
1719 rt3261_stereo_adc1_enum, RT3261_STO_ADC_MIXER,
1720 RT3261_ADC_1_SRC_SFT, rt3261_stereo_adc1_src);
1722 static const struct snd_kcontrol_new rt3261_sto_adc_l1_mux =
1723 SOC_DAPM_ENUM("Stereo ADC L1 source", rt3261_stereo_adc1_enum);
1725 static const struct snd_kcontrol_new rt3261_sto_adc_r1_mux =
1726 SOC_DAPM_ENUM("Stereo ADC R1 source", rt3261_stereo_adc1_enum);
1728 static const char *rt3261_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
1730 static const SOC_ENUM_SINGLE_DECL(
1731 rt3261_stereo_adc2_enum, RT3261_STO_ADC_MIXER,
1732 RT3261_ADC_2_SRC_SFT, rt3261_stereo_adc2_src);
1734 static const struct snd_kcontrol_new rt3261_sto_adc_l2_mux =
1735 SOC_DAPM_ENUM("Stereo ADC L2 source", rt3261_stereo_adc2_enum);
1737 static const struct snd_kcontrol_new rt3261_sto_adc_r2_mux =
1738 SOC_DAPM_ENUM("Stereo ADC R2 source", rt3261_stereo_adc2_enum);
1740 /* Mono ADC source */
1741 static const char *rt3261_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
1743 static const SOC_ENUM_SINGLE_DECL(
1744 rt3261_mono_adc_l1_enum, RT3261_MONO_ADC_MIXER,
1745 RT3261_MONO_ADC_L1_SRC_SFT, rt3261_mono_adc_l1_src);
1747 static const struct snd_kcontrol_new rt3261_mono_adc_l1_mux =
1748 SOC_DAPM_ENUM("Mono ADC1 left source", rt3261_mono_adc_l1_enum);
1750 static const char *rt3261_mono_adc_l2_src[] =
1751 {"DMIC L1", "DMIC L2", "Mono DAC MIXL"};
1753 static const SOC_ENUM_SINGLE_DECL(
1754 rt3261_mono_adc_l2_enum, RT3261_MONO_ADC_MIXER,
1755 RT3261_MONO_ADC_L2_SRC_SFT, rt3261_mono_adc_l2_src);
1757 static const struct snd_kcontrol_new rt3261_mono_adc_l2_mux =
1758 SOC_DAPM_ENUM("Mono ADC2 left source", rt3261_mono_adc_l2_enum);
1760 static const char *rt3261_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
1762 static const SOC_ENUM_SINGLE_DECL(
1763 rt3261_mono_adc_r1_enum, RT3261_MONO_ADC_MIXER,
1764 RT3261_MONO_ADC_R1_SRC_SFT, rt3261_mono_adc_r1_src);
1766 static const struct snd_kcontrol_new rt3261_mono_adc_r1_mux =
1767 SOC_DAPM_ENUM("Mono ADC1 right source", rt3261_mono_adc_r1_enum);
1769 static const char *rt3261_mono_adc_r2_src[] =
1770 {"DMIC R1", "DMIC R2", "Mono DAC MIXR"};
1772 static const SOC_ENUM_SINGLE_DECL(
1773 rt3261_mono_adc_r2_enum, RT3261_MONO_ADC_MIXER,
1774 RT3261_MONO_ADC_R2_SRC_SFT, rt3261_mono_adc_r2_src);
1776 static const struct snd_kcontrol_new rt3261_mono_adc_r2_mux =
1777 SOC_DAPM_ENUM("Mono ADC2 right source", rt3261_mono_adc_r2_enum);
1779 /* DAC2 channel source */
1780 static const char *rt3261_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
1782 static const SOC_ENUM_SINGLE_DECL(rt3261_dac_l2_enum, RT3261_DSP_PATH2,
1783 RT3261_DAC_L2_SEL_SFT, rt3261_dac_l2_src);
1785 static const struct snd_kcontrol_new rt3261_dac_l2_mux =
1786 SOC_DAPM_ENUM("DAC2 left channel source", rt3261_dac_l2_enum);
1788 static const char *rt3261_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
1790 static const SOC_ENUM_SINGLE_DECL(
1791 rt3261_dac_r2_enum, RT3261_DSP_PATH2,
1792 RT3261_DAC_R2_SEL_SFT, rt3261_dac_r2_src);
1794 static const struct snd_kcontrol_new rt3261_dac_r2_mux =
1795 SOC_DAPM_ENUM("DAC2 right channel source", rt3261_dac_r2_enum);
1797 /* Interface 2 ADC channel source */
1798 static const char *rt3261_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
1800 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_l_enum, RT3261_DSP_PATH2,
1801 RT3261_IF2_ADC_L_SEL_SFT, rt3261_if2_adc_l_src);
1803 static const struct snd_kcontrol_new rt3261_if2_adc_l_mux =
1804 SOC_DAPM_ENUM("IF2 ADC left channel source", rt3261_if2_adc_l_enum);
1806 static const char *rt3261_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
1808 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_r_enum, RT3261_DSP_PATH2,
1809 RT3261_IF2_ADC_R_SEL_SFT, rt3261_if2_adc_r_src);
1811 static const struct snd_kcontrol_new rt3261_if2_adc_r_mux =
1812 SOC_DAPM_ENUM("IF2 ADC right channel source", rt3261_if2_adc_r_enum);
1814 /* digital interface and iis interface map */
1815 static const char *rt3261_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
1816 "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
1817 "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
1819 static const SOC_ENUM_SINGLE_DECL(
1820 rt3261_dai_iis_map_enum, RT3261_I2S1_SDP,
1821 RT3261_I2S_IF_SFT, rt3261_dai_iis_map);
1823 static const struct snd_kcontrol_new rt3261_dai_mux =
1824 SOC_DAPM_ENUM("DAI select", rt3261_dai_iis_map_enum);
1827 static const char *rt3261_sdi_sel[] = {"IF1", "IF2"};
1829 static const SOC_ENUM_SINGLE_DECL(
1830 rt3261_sdi_sel_enum, RT3261_I2S2_SDP,
1831 RT3261_I2S2_SDI_SFT, rt3261_sdi_sel);
1833 static const struct snd_kcontrol_new rt3261_sdi_mux =
1834 SOC_DAPM_ENUM("SDI select", rt3261_sdi_sel_enum);
1836 static int rt3261_adc_event(struct snd_soc_dapm_widget *w,
1837 struct snd_kcontrol *kcontrol, int event)
1839 //struct snd_soc_codec *codec = w->codec;
1840 //unsigned int val, mask;
1843 case SND_SOC_DAPM_POST_PMU:
1844 //rt3261_index_update_bits(codec,
1845 // RT3261_CHOP_DAC_ADC, 0x1000, 0x1000);
1847 val = snd_soc_read(codec, RT3261_MONO_ADC_MIXER);
1848 mask = RT3261_M_MONO_ADC_L1 | RT3261_M_MONO_ADC_L2 |
1849 RT3261_M_MONO_ADC_R1 | RT3261_M_MONO_ADC_R2;
1850 if ((val & mask) ^ mask)
1851 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1852 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R, 0);
1856 case SND_SOC_DAPM_POST_PMD:
1858 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1859 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R,
1860 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R);
1862 //rt3261_index_update_bits(codec,
1863 // RT3261_CHOP_DAC_ADC, 0x1000, 0x0000);
1874 static int rt3261_mono_adcl_event(struct snd_soc_dapm_widget *w,
1875 struct snd_kcontrol *kcontrol, int event)
1877 struct snd_soc_codec *codec = w->codec;
1878 //unsigned int val, mask;
1881 case SND_SOC_DAPM_POST_PMU:
1882 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1883 RT3261_M_MAMIX_L, 0);
1885 case SND_SOC_DAPM_PRE_PMD:
1886 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1898 static int rt3261_mono_adcr_event(struct snd_soc_dapm_widget *w,
1899 struct snd_kcontrol *kcontrol, int event)
1901 struct snd_soc_codec *codec = w->codec;
1902 //unsigned int val, mask;
1905 case SND_SOC_DAPM_POST_PMU:
1906 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1907 RT3261_M_MAMIX_R, 0);
1909 case SND_SOC_DAPM_PRE_PMD:
1910 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1922 static int rt3261_spk_event(struct snd_soc_dapm_widget *w,
1923 struct snd_kcontrol *kcontrol, int event)
1925 struct snd_soc_codec *codec = w->codec;
1929 case SND_SOC_DAPM_POST_PMU:
1931 val = snd_soc_read(codec, RT3261_PWR_DIG1);
1932 if(val & (RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1)) {
1933 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1934 RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1,
1935 RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1);
1938 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1939 RT3261_PWR_CLS_D, RT3261_PWR_CLS_D);
1940 rt3261_index_update_bits(codec,
1941 RT3261_CLSD_INT_REG1, 0xf000, 0xf000);
1942 snd_soc_update_bits(codec, RT3261_SPK_VOL,
1943 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1946 case SND_SOC_DAPM_PRE_PMD:
1947 snd_soc_update_bits(codec, RT3261_SPK_VOL,
1948 RT3261_L_MUTE | RT3261_R_MUTE,
1949 RT3261_L_MUTE | RT3261_R_MUTE);
1950 rt3261_index_update_bits(codec,
1951 RT3261_CLSD_INT_REG1, 0xf000, 0x0000);
1952 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1953 RT3261_PWR_CLS_D, 0);
1964 static void rt3261_pmu_depop(struct snd_soc_codec *codec)
1967 /* depop parameters */
1968 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0200); //bard 12-6
1969 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
1970 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
1971 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1972 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1973 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
1974 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
1975 /* headphone amp power on */
1976 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1977 RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
1978 snd_soc_update_bits(codec, RT3261_PWR_VOL,
1979 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
1980 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
1981 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1982 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1983 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
1985 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1986 RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
1987 RT3261_PWR_HP_R | RT3261_PWR_HA,
1988 RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
1989 RT3261_PWR_HP_R | RT3261_PWR_HA);
1990 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
1991 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
1992 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
1993 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1994 RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
1995 RT3261_HP_CO_EN | RT3261_HP_SG_EN);
1996 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0400); //bard 12-6
1998 rt3261_hp_amp_power(codec, 1);
2000 /* headphone unmute sequence */
2001 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
2002 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
2003 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
2004 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
2005 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
2006 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
2007 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2008 RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
2009 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2010 RT3261_RSTN_MASK, RT3261_RSTN_EN);
2011 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2012 RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
2013 RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
2015 snd_soc_update_bits(codec, RT3261_HP_VOL,
2016 RT3261_L_MUTE | RT3261_R_MUTE, 0);
2017 msleep(30); //bard 4-22
2018 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2019 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
2020 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
2021 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
2024 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2025 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
2029 static void rt3261_pmd_depop(struct snd_soc_codec *codec)
2031 /* headphone mute sequence */
2032 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
2033 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
2034 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
2035 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
2036 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
2037 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
2038 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2039 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
2040 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2041 RT3261_RSTP_MASK, RT3261_RSTP_EN);
2042 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2043 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
2044 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
2045 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
2047 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2048 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);*/
2050 snd_soc_update_bits(codec, RT3261_HP_VOL,
2051 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
2054 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
2055 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2056 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
2057 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
2058 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
2059 /* headphone amp power down */
2060 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2061 RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
2062 RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
2063 RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
2064 RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
2065 RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
2066 RT3261_HP_SG_EN | RT3261_HP_CB_PD);
2067 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2068 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
2071 rt3261_hp_amp_power(codec, 0);
2075 static void rt3261_pmu_depop(struct snd_soc_codec *codec)
2077 /* depop parameters */
2078 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0200); //bard 12-6
2079 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
2080 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
2081 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2082 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
2083 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
2084 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
2085 /* headphone amp power on */
2086 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2087 RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
2088 snd_soc_update_bits(codec, RT3261_PWR_VOL,
2089 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
2090 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
2091 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2092 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
2093 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
2095 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2096 RT3261_PWR_FV1 | RT3261_PWR_FV2 ,
2097 RT3261_PWR_FV1 | RT3261_PWR_FV2 );
2098 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
2099 /* headphone unmute sequence */
2100 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
2101 RT3261_DEPOP_MASK | RT3261_DIG_DP_MASK,
2102 RT3261_DEPOP_AUTO | RT3261_DIG_DP_EN);
2103 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
2104 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
2105 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
2106 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
2107 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
2108 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
2109 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
2110 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2111 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK,
2112 RT3261_HP_CP_PD | RT3261_HP_SG_EN);
2113 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0400); //bard 12-6
2115 snd_soc_update_bits(codec, RT3261_HP_VOL,
2116 RT3261_L_MUTE | RT3261_R_MUTE, 0);
2117 msleep(70); //bard 10-18
2119 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2120 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
2124 static void rt3261_pmd_depop(struct snd_soc_codec *codec)
2127 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2128 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
2130 snd_soc_update_bits(codec, RT3261_HP_VOL,
2131 RT3261_L_MUTE | RT3261_R_MUTE,
2132 RT3261_L_MUTE | RT3261_R_MUTE);
2133 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2134 RT3261_HP_CB_MASK, RT3261_HP_CB_PD);
2135 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
2136 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2137 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
2142 static int rt3261_hp_event(struct snd_soc_dapm_widget *w,
2143 struct snd_kcontrol *kcontrol, int event)
2145 struct snd_soc_codec *codec = w->codec;
2147 case SND_SOC_DAPM_POST_PMU:
2148 rt3261_pmu_depop(codec);
2151 case SND_SOC_DAPM_PRE_PMD:
2152 rt3261_pmd_depop(codec);
2162 static int rt3261_mono_event(struct snd_soc_dapm_widget *w,
2163 struct snd_kcontrol *kcontrol, int event)
2165 struct snd_soc_codec *codec = w->codec;
2168 case SND_SOC_DAPM_POST_PMU:
2169 snd_soc_update_bits(codec, RT3261_MONO_OUT,
2173 case SND_SOC_DAPM_PRE_PMD:
2174 snd_soc_update_bits(codec, RT3261_MONO_OUT,
2175 RT3261_L_MUTE, RT3261_L_MUTE);
2185 static int rt3261_lout_event(struct snd_soc_dapm_widget *w,
2186 struct snd_kcontrol *kcontrol, int event)
2188 struct snd_soc_codec *codec = w->codec;
2191 case SND_SOC_DAPM_POST_PMU:
2192 rt3261_hp_amp_power(codec,1);
2193 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2194 RT3261_PWR_LM, RT3261_PWR_LM); //bard 10-18
2195 snd_soc_update_bits(codec, RT3261_OUTPUT,
2196 RT3261_L_MUTE | RT3261_R_MUTE, 0);
2199 case SND_SOC_DAPM_PRE_PMD:
2200 snd_soc_update_bits(codec, RT3261_OUTPUT,
2201 RT3261_L_MUTE | RT3261_R_MUTE,
2202 RT3261_L_MUTE | RT3261_R_MUTE);
2203 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2204 RT3261_PWR_LM, 0); //bard 10-18
2205 rt3261_hp_amp_power(codec,0);
2215 static int rt3261_dac_event(struct snd_soc_dapm_widget *w,
2216 struct snd_kcontrol *kcontrol, int event)
2218 struct snd_soc_codec *codec = w->codec;
2219 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2222 case SND_SOC_DAPM_POST_PMU:
2223 if( rt3261->asrc_en == RT3261_ASRC_EN)
2224 rt3261_update_eqmode(codec, 2);//BT_VOIP
2227 case SND_SOC_DAPM_PRE_PMD:
2228 rt3261_update_eqmode(codec, 0);//NORMAL
2238 static const struct snd_soc_dapm_widget rt3261_dapm_widgets[] = {
2239 SND_SOC_DAPM_SUPPLY("PLL1", RT3261_PWR_ANLG2,
2240 RT3261_PWR_PLL_BIT, 0, NULL, 0),
2243 SND_SOC_DAPM_SUPPLY("LDO2", RT3261_PWR_ANLG1,
2244 RT3261_PWR_LDO2_BIT, 0, NULL, 0),
2246 SND_SOC_DAPM_MICBIAS("micbias1", RT3261_PWR_ANLG2,
2247 RT3261_PWR_MB1_BIT, 0),
2249 SND_SOC_DAPM_MICBIAS("micbias1", SND_SOC_NOPM,
2252 SND_SOC_DAPM_MICBIAS("micbias2", RT3261_PWR_ANLG2,
2253 RT3261_PWR_MB2_BIT, 0),
2255 SND_SOC_DAPM_INPUT("MIC1"),
2256 SND_SOC_DAPM_INPUT("MIC2"),
2257 SND_SOC_DAPM_INPUT("MIC3"),
2258 SND_SOC_DAPM_INPUT("DMIC1"),
2259 SND_SOC_DAPM_INPUT("DMIC2"),
2261 SND_SOC_DAPM_INPUT("IN1P"),
2262 SND_SOC_DAPM_INPUT("IN1N"),
2263 SND_SOC_DAPM_INPUT("IN2P"),
2264 SND_SOC_DAPM_INPUT("IN2N"),
2265 SND_SOC_DAPM_INPUT("IN3P"),
2266 SND_SOC_DAPM_INPUT("IN3N"),
2267 SND_SOC_DAPM_INPUT("DMIC L1"),
2268 SND_SOC_DAPM_INPUT("DMIC R1"),
2269 SND_SOC_DAPM_INPUT("DMIC L2"),
2270 SND_SOC_DAPM_INPUT("DMIC R2"),
2271 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2272 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2274 SND_SOC_DAPM_PGA("BST1", RT3261_PWR_ANLG2,
2275 RT3261_PWR_BST1_BIT, 0, NULL, 0),
2276 SND_SOC_DAPM_PGA("BST2", RT3261_PWR_ANLG2,
2277 RT3261_PWR_BST4_BIT, 0, NULL, 0),
2278 SND_SOC_DAPM_PGA("BST3", RT3261_PWR_ANLG2,
2279 RT3261_PWR_BST2_BIT, 0, NULL, 0),
2281 SND_SOC_DAPM_PGA("INL VOL", RT3261_PWR_VOL,
2282 RT3261_PWR_IN_L_BIT, 0, NULL, 0),
2283 SND_SOC_DAPM_PGA("INR VOL", RT3261_PWR_VOL,
2284 RT3261_PWR_IN_R_BIT, 0, NULL, 0),
2287 SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt3261_inl_mux),
2288 SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt3261_inr_mux),
2291 SND_SOC_DAPM_MIXER("RECMIXL", RT3261_PWR_MIXER, RT3261_PWR_RM_L_BIT, 0,
2292 rt3261_rec_l_mix, ARRAY_SIZE(rt3261_rec_l_mix)),
2293 SND_SOC_DAPM_MIXER("RECMIXR", RT3261_PWR_MIXER, RT3261_PWR_RM_R_BIT, 0,
2294 rt3261_rec_r_mix, ARRAY_SIZE(rt3261_rec_r_mix)),
2296 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM,
2298 SND_SOC_DAPM_ADC_E("ADC R", NULL, SND_SOC_NOPM,
2299 0, 0, rt3261_adc_event,
2300 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
2302 SND_SOC_DAPM_SUPPLY("ADC L power",RT3261_PWR_DIG1,
2303 RT3261_PWR_ADC_L_BIT, 0, NULL, 0),
2304 SND_SOC_DAPM_SUPPLY("ADC R power",RT3261_PWR_DIG1,
2305 RT3261_PWR_ADC_R_BIT, 0, NULL, 0),
2307 SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2308 &rt3261_sto_adc_l2_mux),
2309 SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2310 &rt3261_sto_adc_r2_mux),
2311 SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2312 &rt3261_sto_adc_l1_mux),
2313 SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2314 &rt3261_sto_adc_r1_mux),
2315 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2316 &rt3261_mono_adc_l2_mux),
2317 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2318 &rt3261_mono_adc_l1_mux),
2319 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2320 &rt3261_mono_adc_r1_mux),
2321 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2322 &rt3261_mono_adc_r2_mux),
2324 SND_SOC_DAPM_SUPPLY("stereo filter", RT3261_PWR_DIG2,
2325 RT3261_PWR_ADC_SF_BIT, 0, NULL, 0),
2326 SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
2327 rt3261_sto_adc_l_mix, ARRAY_SIZE(rt3261_sto_adc_l_mix)),
2328 SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
2329 rt3261_sto_adc_r_mix, ARRAY_SIZE(rt3261_sto_adc_r_mix)),
2330 SND_SOC_DAPM_SUPPLY("mono left filter", RT3261_PWR_DIG2,
2331 RT3261_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2332 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2333 rt3261_mono_adc_l_mix, ARRAY_SIZE(rt3261_mono_adc_l_mix),
2334 rt3261_mono_adcl_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), //bard 3-26
2335 SND_SOC_DAPM_SUPPLY("mono right filter", RT3261_PWR_DIG2,
2336 RT3261_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2337 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2338 rt3261_mono_adc_r_mix, ARRAY_SIZE(rt3261_mono_adc_r_mix),
2339 rt3261_mono_adcr_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), //bard 3-26
2342 SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2343 &rt3261_if2_adc_l_mux),
2344 SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2345 &rt3261_if2_adc_r_mux),
2347 /* Digital Interface */
2348 SND_SOC_DAPM_SUPPLY("I2S1", SND_SOC_NOPM,
2350 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2351 SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2352 SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2353 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2354 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2355 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2356 SND_SOC_DAPM_SUPPLY("I2S2", RT3261_PWR_DIG1,
2357 RT3261_PWR_I2S2_BIT, 0, NULL, 0),
2358 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2359 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2360 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2361 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2362 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2363 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2364 SND_SOC_DAPM_SUPPLY("I2S3", RT3261_PWR_DIG1,
2365 RT3261_PWR_I2S3_BIT, 0, NULL, 0),
2366 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2367 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2368 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2369 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2370 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2371 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2373 /* Digital Interface Select */
2374 SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2375 SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2376 SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2377 SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2378 SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
2380 SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2381 SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2382 SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2383 SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2384 SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
2386 SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2387 SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2389 /* Audio Interface */
2390 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2391 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2392 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2393 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2394 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2395 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2398 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2401 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
2404 /* DAC mixer before sound effect */
2406 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2407 rt3261_dac_l_mix, ARRAY_SIZE(rt3261_dac_l_mix)),
2408 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2409 rt3261_dac_r_mix, ARRAY_SIZE(rt3261_dac_r_mix)),
2411 SND_SOC_DAPM_MIXER_E("DAC MIXL", SND_SOC_NOPM, 0, 0,
2412 rt3261_dac_l_mix, ARRAY_SIZE(rt3261_dac_l_mix),
2413 rt3261_dac_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2414 SND_SOC_DAPM_MIXER_E("DAC MIXR", SND_SOC_NOPM, 0, 0,
2415 rt3261_dac_r_mix, ARRAY_SIZE(rt3261_dac_r_mix),
2416 rt3261_dac_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2419 /* DAC2 channel Mux */
2420 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
2421 &rt3261_dac_l2_mux),
2422 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
2423 &rt3261_dac_r2_mux),
2425 SND_SOC_DAPM_PGA("DAC L2 Volume", RT3261_PWR_DIG1,
2426 RT3261_PWR_DAC_L2_BIT, 0, NULL, 0),
2427 SND_SOC_DAPM_PGA("DAC R2 Volume", RT3261_PWR_DIG1,
2428 RT3261_PWR_DAC_R2_BIT, 0, NULL, 0),
2430 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM,
2432 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM,
2434 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT3261_PWR_DIG1,
2435 RT3261_PWR_DAC_L1_BIT, 0, NULL, 0),
2436 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT3261_PWR_DIG1,
2437 RT3261_PWR_DAC_R1_BIT, 0, NULL, 0),
2438 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT3261_PWR_DIG1,
2439 RT3261_PWR_DAC_L2_BIT, 0, NULL, 0),
2440 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT3261_PWR_DIG1,
2441 RT3261_PWR_DAC_R2_BIT, 0, NULL, 0),
2445 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2446 rt3261_sto_dac_l_mix, ARRAY_SIZE(rt3261_sto_dac_l_mix)),
2447 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2448 rt3261_sto_dac_r_mix, ARRAY_SIZE(rt3261_sto_dac_r_mix)),
2449 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2450 rt3261_mono_dac_l_mix, ARRAY_SIZE(rt3261_mono_dac_l_mix)),
2451 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2452 rt3261_mono_dac_r_mix, ARRAY_SIZE(rt3261_mono_dac_r_mix)),
2453 SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
2454 rt3261_dig_l_mix, ARRAY_SIZE(rt3261_dig_l_mix)),
2455 SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
2456 rt3261_dig_r_mix, ARRAY_SIZE(rt3261_dig_r_mix)),
2457 SND_SOC_DAPM_MUX("Mono dacr Mux", SND_SOC_NOPM, 0, 0,
2462 SND_SOC_DAPM_DAC("DAC L1", NULL, RT3261_PWR_DIG1,
2463 RT3261_PWR_DAC_L1_BIT, 0),
2464 SND_SOC_DAPM_DAC("DAC L2", NULL, RT3261_PWR_DIG1,
2465 RT3261_PWR_DAC_L2_BIT, 0),
2466 SND_SOC_DAPM_DAC("DAC R1", NULL, RT3261_PWR_DIG1,
2467 RT3261_PWR_DAC_R1_BIT, 0),
2468 SND_SOC_DAPM_DAC("DAC R2", NULL, RT3261_PWR_DIG1,
2469 RT3261_PWR_DAC_R2_BIT, 0),
2471 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
2472 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
2473 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
2474 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
2476 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
2478 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM,
2481 SND_SOC_DAPM_MIXER("SPK MIXL", RT3261_PWR_MIXER, RT3261_PWR_SM_L_BIT,
2482 0, rt3261_spk_l_mix, ARRAY_SIZE(rt3261_spk_l_mix)),
2483 SND_SOC_DAPM_MIXER("SPK MIXR", RT3261_PWR_MIXER, RT3261_PWR_SM_R_BIT,
2484 0, rt3261_spk_r_mix, ARRAY_SIZE(rt3261_spk_r_mix)),
2485 SND_SOC_DAPM_MIXER("OUT MIXL", RT3261_PWR_MIXER, RT3261_PWR_OM_L_BIT,
2486 0, rt3261_out_l_mix, ARRAY_SIZE(rt3261_out_l_mix)),
2487 SND_SOC_DAPM_MIXER("OUT MIXR", RT3261_PWR_MIXER, RT3261_PWR_OM_R_BIT,
2488 0, rt3261_out_r_mix, ARRAY_SIZE(rt3261_out_r_mix)),
2490 SND_SOC_DAPM_PGA("SPKVOL L", RT3261_PWR_VOL,
2491 RT3261_PWR_SV_L_BIT, 0, NULL, 0),
2492 SND_SOC_DAPM_PGA("SPKVOL R", RT3261_PWR_VOL,
2493 RT3261_PWR_SV_R_BIT, 0, NULL, 0),
2494 SND_SOC_DAPM_PGA("OUTVOL L", RT3261_PWR_VOL,
2495 RT3261_PWR_OV_L_BIT, 0, NULL, 0),
2496 SND_SOC_DAPM_PGA("OUTVOL R", RT3261_PWR_VOL,
2497 RT3261_PWR_OV_R_BIT, 0, NULL, 0),
2498 SND_SOC_DAPM_PGA("HPOVOL L", RT3261_PWR_VOL,
2499 RT3261_PWR_HV_L_BIT, 0, NULL, 0),
2500 SND_SOC_DAPM_PGA("HPOVOL R", RT3261_PWR_VOL,
2501 RT3261_PWR_HV_R_BIT, 0, NULL, 0),
2502 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM,
2504 /* SPO/HPO/LOUT/Mono Mixer */
2505 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
2506 0, rt3261_spo_l_mix, ARRAY_SIZE(rt3261_spo_l_mix)),
2507 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
2508 0, rt3261_spo_r_mix, ARRAY_SIZE(rt3261_spo_r_mix)),
2509 SND_SOC_DAPM_MIXER("DAC SPK", SND_SOC_NOPM, 0,
2510 0, rt3261_spo_dac_mix, ARRAY_SIZE(rt3261_spo_dac_mix)), //bard 8-27
2511 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
2512 rt3261_hpo_mix, ARRAY_SIZE(rt3261_hpo_mix)),
2513 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
2514 rt3261_lout_mix, ARRAY_SIZE(rt3261_lout_mix)),
2515 SND_SOC_DAPM_MIXER("Mono MIX", RT3261_PWR_ANLG1, RT3261_PWR_MM_BIT, 0,
2516 rt3261_mono_mix, ARRAY_SIZE(rt3261_mono_mix)),
2518 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0,
2519 rt3261_hp_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2520 SND_SOC_DAPM_PGA_S("SPK amp", 1, SND_SOC_NOPM, 0, 0,
2521 rt3261_spk_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2522 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
2523 rt3261_lout_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2524 SND_SOC_DAPM_PGA_S("Mono amp", 1, RT3261_PWR_ANLG1,
2525 RT3261_PWR_MA_BIT, 0, rt3261_mono_event,
2526 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2529 SND_SOC_DAPM_OUTPUT("SPOLP"),
2530 SND_SOC_DAPM_OUTPUT("SPOLN"),
2531 SND_SOC_DAPM_OUTPUT("SPORP"),
2532 SND_SOC_DAPM_OUTPUT("SPORN"),
2533 SND_SOC_DAPM_OUTPUT("HPOL"),
2534 SND_SOC_DAPM_OUTPUT("HPOR"),
2535 SND_SOC_DAPM_OUTPUT("LOUTL"),
2536 SND_SOC_DAPM_OUTPUT("LOUTR"),
2537 SND_SOC_DAPM_OUTPUT("MonoP"),
2538 SND_SOC_DAPM_OUTPUT("MonoN"),
2541 static const struct snd_soc_dapm_route rt3261_dapm_routes[] = {
2542 {"IN1P", NULL, "LDO2"},
2543 {"IN2P", NULL, "LDO2"},
2544 {"IN3P", NULL, "LDO2"},
2546 {"IN1P", NULL, "MIC1"},
2547 {"IN1N", NULL, "MIC1"},
2548 {"IN2P", NULL, "MIC2"},
2549 {"IN2N", NULL, "MIC2"},
2550 {"IN3P", NULL, "MIC3"},
2551 {"IN3N", NULL, "MIC3"},
2553 {"DMIC L1", NULL, "DMIC1"},
2554 {"DMIC R1", NULL, "DMIC1"},
2555 {"DMIC L2", NULL, "DMIC2"},
2556 {"DMIC R2", NULL, "DMIC2"},
2558 {"BST1", NULL, "IN1P"},
2559 {"BST1", NULL, "IN1N"},
2560 {"BST2", NULL, "IN2P"},
2561 {"BST2", NULL, "IN2N"},
2562 {"BST3", NULL, "IN3P"},
2563 {"BST3", NULL, "IN3N"},
2565 {"INL VOL", NULL, "IN2P"},
2566 {"INR VOL", NULL, "IN2N"},
2568 {"RECMIXL", "HPOL Switch", "HPOL"},
2569 {"RECMIXL", "INL Switch", "INL VOL"},
2570 {"RECMIXL", "BST3 Switch", "BST3"},
2571 {"RECMIXL", "BST2 Switch", "BST2"},
2572 {"RECMIXL", "BST1 Switch", "BST1"},
2573 {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
2575 {"RECMIXR", "HPOR Switch", "HPOR"},
2576 {"RECMIXR", "INR Switch", "INR VOL"},
2577 {"RECMIXR", "BST3 Switch", "BST3"},
2578 {"RECMIXR", "BST2 Switch", "BST2"},
2579 {"RECMIXR", "BST1 Switch", "BST1"},
2580 {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
2582 {"ADC L", NULL, "RECMIXL"},
2583 {"ADC L", NULL, "ADC L power"},
2584 {"ADC R", NULL, "RECMIXR"},
2585 {"ADC R", NULL, "ADC R power"},
2587 {"DMIC L1", NULL, "DMIC CLK"},
2588 {"DMIC L2", NULL, "DMIC CLK"},
2590 {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
2591 {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
2592 {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
2593 {"Stereo ADC L1 Mux", "ADC", "ADC L"},
2594 {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
2596 {"Stereo ADC R1 Mux", "ADC", "ADC R"},
2597 {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
2598 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
2599 {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
2600 {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
2602 {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
2603 {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
2604 {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
2605 {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
2606 {"Mono ADC L1 Mux", "ADCL", "ADC L"},
2608 {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
2609 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
2610 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
2611 {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
2612 {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
2614 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
2615 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
2616 {"Stereo ADC MIXL", NULL, "stereo filter"},
2617 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
2619 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
2620 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
2621 {"Stereo ADC MIXR", NULL, "stereo filter"},
2622 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
2624 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
2625 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
2626 {"Mono ADC MIXL", NULL, "mono left filter"},
2627 {"mono left filter", NULL, "PLL1", check_sysclk1_source},
2629 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
2630 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
2631 {"Mono ADC MIXR", NULL, "mono right filter"},
2632 {"mono right filter", NULL, "PLL1", check_sysclk1_source},
2634 {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
2635 {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
2637 {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
2638 {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
2639 {"IF3 ADC L", NULL, "Mono ADC MIXL"},
2640 {"IF3 ADC R", NULL, "Mono ADC MIXR"},
2641 {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
2642 {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
2644 {"IF1 ADC", NULL, "I2S1"},
2645 {"IF1 ADC", NULL, "IF1 ADC L"},
2646 {"IF1 ADC", NULL, "IF1 ADC R"},
2647 {"IF2 ADC", NULL, "I2S2"},
2648 {"IF2 ADC", NULL, "IF2 ADC L"},
2649 {"IF2 ADC", NULL, "IF2 ADC R"},
2650 {"IF3 ADC", NULL, "I2S3"},
2651 {"IF3 ADC", NULL, "IF3 ADC L"},
2652 {"IF3 ADC", NULL, "IF3 ADC R"},
2654 {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
2655 {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
2656 {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
2657 {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
2658 {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
2659 {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
2660 {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
2661 {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
2662 {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
2663 {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
2665 {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
2666 {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
2667 {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
2668 {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
2669 {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
2670 {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
2671 {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
2672 {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
2673 {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
2674 {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
2676 {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
2677 {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
2678 {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
2679 {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
2680 {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
2681 {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
2682 {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
2683 {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
2685 {"AIF1TX", NULL, "DAI1 TX Mux"},
2686 {"AIF1TX", NULL, "SDI1 TX Mux"},
2687 {"AIF2TX", NULL, "DAI2 TX Mux"},
2688 {"AIF2TX", NULL, "SDI2 TX Mux"},
2689 {"AIF3TX", NULL, "DAI3 TX Mux"},
2691 {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
2692 {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
2693 {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
2694 {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
2695 {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
2696 {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
2697 {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
2698 {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
2700 {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
2701 {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
2702 {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
2703 {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
2704 {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
2705 {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
2706 {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
2707 {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
2709 {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
2710 {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
2711 {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
2712 {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
2713 {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
2714 {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
2715 {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
2716 {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
2718 {"IF1 DAC", NULL, "I2S1"},
2719 {"IF1 DAC", NULL, "DAI1 RX Mux"},
2720 {"IF2 DAC", NULL, "I2S2"},
2721 {"IF2 DAC", NULL, "DAI2 RX Mux"},
2722 {"IF3 DAC", NULL, "I2S3"},
2723 {"IF3 DAC", NULL, "DAI3 RX Mux"},
2725 {"IF1 DAC L", NULL, "IF1 DAC"},
2726 {"IF1 DAC R", NULL, "IF1 DAC"},
2727 {"IF2 DAC L", NULL, "IF2 DAC"},
2728 {"IF2 DAC R", NULL, "IF2 DAC"},
2729 {"IF3 DAC L", NULL, "IF3 DAC"},
2730 {"IF3 DAC R", NULL, "IF3 DAC"},
2732 {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
2733 {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
2734 {"DAC MIXL", NULL, "DAC L1 Power"}, //bard 9-26
2735 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
2736 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
2737 {"DAC MIXR", NULL, "DAC R1 Power"}, //bard 9-26
2739 {"ANC", NULL, "Stereo ADC MIXL"},
2740 {"ANC", NULL, "Stereo ADC MIXR"},
2742 {"Audio DSP", NULL, "DAC MIXL"},
2743 {"Audio DSP", NULL, "DAC MIXR"},
2745 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
2746 {"DAC L2 Mux", "IF3", "IF3 DAC L"},
2747 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
2748 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
2749 {"DAC L2 Volume", NULL, "DAC L2 Power"}, //bard 9-26
2751 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
2752 {"DAC R2 Mux", "IF3", "IF3 DAC R"},
2753 {"DAC R2 Volume", NULL, "Mono dacr Mux"},
2754 {"Mono dacr Mux", "TxDC_R", "DAC R2 Mux"},
2755 {"Mono dacr Mux", "TxDP_R", "IF2 ADC R Mux"},
2756 {"DAC R2 Volume", NULL, "DAC R2 Power"}, //bsrd 9-26
2758 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
2759 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2760 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
2761 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
2762 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2763 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
2765 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
2766 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2767 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume"},
2768 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
2769 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2770 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume"},
2772 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
2773 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2774 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
2775 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2777 {"DAC L1", NULL, "Stereo DAC MIXL"},
2778 {"DAC L1", NULL, "PLL1", check_sysclk1_source},
2779 {"DAC L1", NULL, "DAC L1 Power"}, //bard 9-26
2780 {"DAC R1", NULL, "Stereo DAC MIXR"},
2781 {"DAC R1", NULL, "PLL1", check_sysclk1_source},
2782 {"DAC R1", NULL, "DAC R1 Power"}, //bard 9-26
2783 {"DAC L2", NULL, "Mono DAC MIXL"},
2784 {"DAC L2", NULL, "PLL1", check_sysclk1_source},
2785 {"DAC L2", NULL, "DAC L2 Power"}, //bard 9-26
2786 {"DAC R2", NULL, "Mono DAC MIXR"},
2787 {"DAC R2", NULL, "PLL1", check_sysclk1_source},
2788 {"DAC R2", NULL, "DAC R2 Power"}, //bard 9-26
2790 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
2791 {"SPK MIXL", "INL Switch", "INL VOL"},
2792 {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
2793 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
2794 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
2795 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
2796 {"SPK MIXR", "INR Switch", "INR VOL"},
2797 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
2798 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
2799 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
2801 {"OUT MIXL", "BST3 Switch", "BST3"},
2802 {"OUT MIXL", "BST1 Switch", "BST1"},
2803 {"OUT MIXL", "INL Switch", "INL VOL"},
2804 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
2805 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
2806 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
2807 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
2809 {"OUT MIXR", "BST3 Switch", "BST3"},
2810 {"OUT MIXR", "BST2 Switch", "BST2"},
2811 {"OUT MIXR", "BST1 Switch", "BST1"},
2812 {"OUT MIXR", "INR Switch", "INR VOL"},
2813 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
2814 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
2815 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
2816 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
2818 {"SPKVOL L", NULL, "SPK MIXL"},
2819 {"SPKVOL R", NULL, "SPK MIXR"},
2820 {"HPOVOL L", NULL, "OUT MIXL"},
2821 {"HPOVOL R", NULL, "OUT MIXR"},
2822 {"OUTVOL L", NULL, "OUT MIXL"},
2823 {"OUTVOL R", NULL, "OUT MIXR"},
2825 {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
2826 {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
2828 {"SPOL MIX", "DAC Switch", "DAC SPK"},
2829 {"DAC SPK", "DAC L1 Switch", "DAC L1"},
2830 {"DAC SPK", "DAC R1 Switch", "DAC R1"},
2832 {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
2833 {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
2834 {"SPOL MIX", "BST1 Switch", "BST1"},
2835 {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
2836 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
2837 {"SPOR MIX", "BST1 Switch", "BST1"},
2839 {"DAC 2", NULL, "DAC L2"},
2840 {"DAC 2", NULL, "DAC R2"},
2841 {"DAC 1", NULL, "DAC L1"},
2842 {"DAC 1", NULL, "DAC R1"},
2843 {"HPOVOL", NULL, "HPOVOL L"},
2844 {"HPOVOL", NULL, "HPOVOL R"},
2845 {"HPO MIX", "DAC2 Switch", "DAC 2"},
2846 {"HPO MIX", "DAC1 Switch", "DAC 1"},
2847 {"HPO MIX", "HPVOL Switch", "HPOVOL"},
2849 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
2850 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
2851 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
2852 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
2854 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
2855 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
2856 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
2857 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
2858 {"Mono MIX", "BST1 Switch", "BST1"},
2860 {"SPK amp", NULL, "SPOL MIX"},
2861 {"SPK amp", NULL, "SPOR MIX"},
2862 {"SPOLP", NULL, "SPK amp"},
2863 {"SPOLN", NULL, "SPK amp"},
2864 {"SPORP", NULL, "SPK amp"},
2865 {"SPORN", NULL, "SPK amp"},
2867 {"HP amp", NULL, "HPO MIX"},
2868 {"HPOL", NULL, "HP amp"},
2869 {"HPOR", NULL, "HP amp"},
2871 {"LOUT amp", NULL, "LOUT MIX"},
2872 {"LOUTL", NULL, "LOUT amp"},
2873 {"LOUTR", NULL, "LOUT amp"},
2875 {"Mono amp", NULL, "Mono MIX"},
2876 {"MonoP", NULL, "Mono amp"},
2877 {"MonoN", NULL, "Mono amp"},
2880 static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
2887 val = snd_soc_read(codec, RT3261_I2S1_SDP);
2888 val = (val & RT3261_I2S_IF_MASK) >> RT3261_I2S_IF_SFT;
2891 if (val == RT3261_IF_123 || val == RT3261_IF_132 ||
2892 val == RT3261_IF_113)
2893 ret |= RT3261_U_IF1;
2894 if (val == RT3261_IF_312 || val == RT3261_IF_213 ||
2895 val == RT3261_IF_113)
2896 ret |= RT3261_U_IF2;
2897 if (val == RT3261_IF_321 || val == RT3261_IF_231)
2898 ret |= RT3261_U_IF3;
2902 if (val == RT3261_IF_231 || val == RT3261_IF_213 ||
2903 val == RT3261_IF_223)
2904 ret |= RT3261_U_IF1;
2905 if (val == RT3261_IF_123 || val == RT3261_IF_321 ||
2906 val == RT3261_IF_223)
2907 ret |= RT3261_U_IF2;
2908 if (val == RT3261_IF_132 || val == RT3261_IF_312)
2909 ret |= RT3261_U_IF3;
2920 static int get_clk_info(int sclk, int rate)
2922 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
2923 struct snd_soc_codec *codec = rt3261_codec;
2924 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2926 if (sclk <= 0 || rate <= 0)
2929 if (rt3261->asrc_en)
2933 for (i = 0; i < ARRAY_SIZE(pd); i++)
2934 if (sclk == rate * pd[i])
2940 static int rt3261_hw_params(struct snd_pcm_substream *substream,
2941 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2943 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2944 struct snd_soc_codec *codec = rtd->codec;
2945 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2946 unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
2947 int pre_div, bclk_ms, frame_size;
2949 rt3261->lrck[dai->id] = params_rate(params);
2951 rt3261->lrck[dai->id] = 8000;
2952 pre_div = get_clk_info(rt3261->sysclk, rt3261->lrck[dai->id]);
2954 dev_err(codec->dev, "Unsupported clock setting\n");
2957 frame_size = snd_soc_params_to_frame_size(params);
2958 if (frame_size < 0) {
2959 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2962 bclk_ms = frame_size > 32 ? 1 : 0;
2963 rt3261->bclk[dai->id] = rt3261->lrck[dai->id] * (32 << bclk_ms);
2965 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2966 rt3261->bclk[dai->id], rt3261->lrck[dai->id]);
2967 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2968 bclk_ms, pre_div, dai->id);
2970 switch (params_format(params)) {
2971 case SNDRV_PCM_FORMAT_S16_LE:
2973 case SNDRV_PCM_FORMAT_S20_3LE:
2974 val_len |= RT3261_I2S_DL_20;
2976 case SNDRV_PCM_FORMAT_S24_LE:
2977 val_len |= RT3261_I2S_DL_24;
2979 case SNDRV_PCM_FORMAT_S8:
2980 val_len |= RT3261_I2S_DL_8;
2986 dai_sel = get_sdp_info(codec, dai->id);
2987 dai_sel |= (RT3261_U_IF1 | RT3261_U_IF2);
2989 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
2992 if (dai_sel & RT3261_U_IF1) {
2993 mask_clk = RT3261_I2S_BCLK_MS1_MASK | RT3261_I2S_PD1_MASK;
2994 val_clk = bclk_ms << RT3261_I2S_BCLK_MS1_SFT |
2995 pre_div << RT3261_I2S_PD1_SFT;
2996 snd_soc_update_bits(codec, RT3261_I2S1_SDP,
2997 RT3261_I2S_DL_MASK, val_len);
2998 //snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
3000 if (dai_sel & RT3261_U_IF2) {
3001 mask_clk |= RT3261_I2S_BCLK_MS2_MASK | RT3261_I2S_PD2_MASK;
3002 val_clk |= bclk_ms << RT3261_I2S_BCLK_MS2_SFT |
3003 pre_div << RT3261_I2S_PD2_SFT;
3004 snd_soc_update_bits(codec, RT3261_I2S2_SDP,
3005 RT3261_I2S_DL_MASK, val_len);
3006 //snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
3008 if (rt3261->asrc_en)
3009 snd_soc_write(codec, RT3261_ADDA_CLK1, 0x1114);
3011 snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
3016 static int rt3261_prepare(struct snd_pcm_substream *substream,
3017 struct snd_soc_dai *dai)
3019 struct snd_soc_pcm_runtime *rtd = substream->private_data;
3020 struct snd_soc_codec *codec = rtd->codec;
3021 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3023 rt3261->aif_pu = dai->id;
3027 static int rt3261_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3029 struct snd_soc_codec *codec = dai->codec;
3030 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3031 unsigned int reg_val = 0, dai_sel;
3033 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3034 case SND_SOC_DAIFMT_CBM_CFM:
3035 rt3261->master[dai->id] = 1;
3037 case SND_SOC_DAIFMT_CBS_CFS:
3038 reg_val |= RT3261_I2S_MS_S;
3039 rt3261->master[dai->id] = 0;
3045 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3046 case SND_SOC_DAIFMT_NB_NF:
3048 case SND_SOC_DAIFMT_IB_NF:
3049 reg_val |= RT3261_I2S_BP_INV;
3055 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3056 case SND_SOC_DAIFMT_I2S:
3058 case SND_SOC_DAIFMT_LEFT_J:
3059 reg_val |= RT3261_I2S_DF_LEFT;
3061 case SND_SOC_DAIFMT_DSP_A:
3062 reg_val |= RT3261_I2S_DF_PCM_A;
3064 case SND_SOC_DAIFMT_DSP_B:
3065 reg_val |= RT3261_I2S_DF_PCM_B;
3071 dai_sel = get_sdp_info(codec, dai->id);
3073 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
3076 if (dai_sel & RT3261_U_IF1) {
3077 snd_soc_update_bits(codec, RT3261_I2S1_SDP,
3078 RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
3079 RT3261_I2S_DF_MASK, reg_val);
3081 if (dai_sel & RT3261_U_IF2) {
3082 snd_soc_update_bits(codec, RT3261_I2S2_SDP,
3083 RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
3084 RT3261_I2S_DF_MASK, reg_val);
3090 static int rt3261_set_dai_sysclk(struct snd_soc_dai *dai,
3091 int clk_id, unsigned int freq, int dir)
3093 struct snd_soc_codec *codec = dai->codec;
3094 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3095 unsigned int reg_val = 0;
3097 if (freq == rt3261->sysclk && clk_id == rt3261->sysclk_src)
3099 snd_soc_update_bits(codec, RT3261_PWR_ANLG2, RT3261_PWR_PLL, RT3261_PWR_PLL);
3102 case RT3261_SCLK_S_MCLK:
3103 reg_val |= RT3261_SCLK_SRC_MCLK;
3105 case RT3261_SCLK_S_PLL1:
3106 reg_val |= RT3261_SCLK_SRC_PLL1;
3108 case RT3261_SCLK_S_RCCLK:
3109 reg_val |= RT3261_SCLK_SRC_RCCLK;
3112 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3115 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3116 RT3261_SCLK_SRC_MASK, reg_val);
3117 rt3261->sysclk = freq;
3118 rt3261->sysclk_src = clk_id;
3120 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3126 * rt3261_pll_calc - Calcualte PLL M/N/K code.
3127 * @freq_in: external clock provided to codec.
3128 * @freq_out: target clock which codec works on.
3129 * @pll_code: Pointer to structure with M, N, K and bypass flag.
3131 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
3132 * which make calculation more efficiently.
3134 * Returns 0 for success or negative error code.
3136 static int rt3261_pll_calc(const unsigned int freq_in,
3137 const unsigned int freq_out, struct rt3261_pll_code *pll_code)
3139 int max_n = RT3261_PLL_N_MAX, max_m = RT3261_PLL_M_MAX;
3140 int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
3141 bool bypass = false;
3143 if (RT3261_PLL_INP_MAX < freq_in || RT3261_PLL_INP_MIN > freq_in)
3146 for (n_t = 0; n_t <= max_n; n_t++) {
3147 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
3150 if (in_t == freq_out) {
3155 for (m_t = 0; m_t <= max_m; m_t++) {
3156 out_t = in_t / (m_t + 2);
3157 red = abs(out_t - freq_out);
3167 pr_debug("Only get approximation about PLL\n");
3171 pll_code->m_bp = bypass;
3172 pll_code->m_code = m;
3173 pll_code->n_code = n;
3174 pll_code->k_code = 2;
3178 static int rt3261_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3179 unsigned int freq_in, unsigned int freq_out)
3181 struct snd_soc_codec *codec = dai->codec;
3182 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3183 struct rt3261_pll_code pll_code;
3186 if (source == rt3261->pll_src && freq_in == rt3261->pll_in &&
3187 freq_out == rt3261->pll_out)
3190 if (!freq_in || !freq_out) {
3191 dev_dbg(codec->dev, "PLL disabled\n");
3194 rt3261->pll_out = 0;
3195 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3196 RT3261_SCLK_SRC_MASK, RT3261_SCLK_SRC_MCLK);
3201 case RT3261_PLL1_S_MCLK:
3202 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3203 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_MCLK);
3205 case RT3261_PLL1_S_BCLK1:
3206 case RT3261_PLL1_S_BCLK2:
3207 dai_sel = get_sdp_info(codec, dai->id);
3210 "Failed to get sdp info: %d\n", dai_sel);
3213 if (dai_sel & RT3261_U_IF1) {
3214 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3215 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK1);
3217 if (dai_sel & RT3261_U_IF2) {
3218 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3219 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK2);
3221 if (dai_sel & RT3261_U_IF3) {
3222 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3223 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK3);
3227 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3231 ret = rt3261_pll_calc(freq_in, freq_out, &pll_code);
3233 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3237 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
3238 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
3240 snd_soc_write(codec, RT3261_PLL_CTRL1,
3241 pll_code.n_code << RT3261_PLL_N_SFT | pll_code.k_code);
3242 snd_soc_write(codec, RT3261_PLL_CTRL2,
3243 (pll_code.m_bp ? 0 : pll_code.m_code) << RT3261_PLL_M_SFT |
3244 pll_code.m_bp << RT3261_PLL_M_BP_SFT);
3246 rt3261->pll_in = freq_in;
3247 rt3261->pll_out = freq_out;
3248 rt3261->pll_src = source;
3254 * rt3261_index_show - Dump private registers.
3255 * @dev: codec device.
3256 * @attr: device attribute.
3257 * @buf: buffer for display.
3259 * To show non-zero values of all private registers.
3261 * Returns buffer length.
3263 static ssize_t rt3261_index_show(struct device *dev,
3264 struct device_attribute *attr, char *buf)
3266 struct i2c_client *client = to_i2c_client(dev);
3267 struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
3268 struct snd_soc_codec *codec = rt3261->codec;
3272 cnt += sprintf(buf, "RT3261 index register\n");
3273 for (i = 0; i < 0xb4; i++) {
3274 if (cnt + RT3261_REG_DISP_LEN >= PAGE_SIZE)
3276 val = rt3261_index_read(codec, i);
3279 cnt += snprintf(buf + cnt, RT3261_REG_DISP_LEN,
3280 "%02x: %04x\n", i, val);
3283 if (cnt >= PAGE_SIZE)
3284 cnt = PAGE_SIZE - 1;
3288 static DEVICE_ATTR(index_reg, 0444, rt3261_index_show, NULL);
3290 static int rt3261_set_bias_level(struct snd_soc_codec *codec,
3291 enum snd_soc_bias_level level)
3294 case SND_SOC_BIAS_ON:
3297 case SND_SOC_BIAS_PREPARE:
3298 //snd_soc_update_bits(codec, RT3261_HP_VOL,
3299 // RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE); //bard 12-7
3300 snd_soc_update_bits(codec, RT3261_SPK_VOL,
3301 RT3261_L_MUTE | RT3261_R_MUTE,
3302 RT3261_L_MUTE | RT3261_R_MUTE);
3303 snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
3304 RT3261_PWR_MB1 | RT3261_PWR_MB2,
3305 RT3261_PWR_MB1 | RT3261_PWR_MB2);
3308 case SND_SOC_BIAS_STANDBY:
3309 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
3310 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3311 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3312 RT3261_PWR_BG | RT3261_PWR_VREF2,
3313 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3314 RT3261_PWR_BG | RT3261_PWR_VREF2);
3316 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3317 RT3261_PWR_FV1 | RT3261_PWR_FV2,
3318 RT3261_PWR_FV1 | RT3261_PWR_FV2);
3319 snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3701);
3320 snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
3321 RT3261_PWR_MB1 | RT3261_PWR_MB2,
3322 RT3261_PWR_MB1 | RT3261_PWR_MB2);
3323 codec->cache_only = false;
3324 codec->cache_sync = 1;
3325 snd_soc_cache_sync(codec);
3326 rt3261_index_sync(codec);
3330 case SND_SOC_BIAS_OFF:
3331 //snd_soc_write(codec, RT3261_DEPOP_M1, 0x0004);//bard 4-22 r
3332 //snd_soc_write(codec, RT3261_DEPOP_M2, 0x1100);//bard 4-22 r
3333 snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3700);
3334 snd_soc_write(codec, RT3261_PWR_DIG1, 0x0000);
3335 snd_soc_write(codec, RT3261_PWR_DIG2, 0x0000);
3336 snd_soc_write(codec, RT3261_PWR_VOL, 0x0000);
3337 snd_soc_write(codec, RT3261_PWR_MIXER, 0x0000);
3338 snd_soc_write(codec, RT3261_PWR_ANLG1, 0x0000);
3339 snd_soc_write(codec, RT3261_PWR_ANLG2, 0x0000);
3345 codec->dapm.bias_level = level;
3350 static int rt3261_probe(struct snd_soc_codec *codec)
3352 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3355 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
3356 struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
3359 #if defined (CONFIG_SND_SOC_RT3224)
3360 pr_info("Codec driver version %s, in fact you choose rt3224, no dsp!\n", VERSION);
3362 pr_info("Codec driver version %s, in fact you choose rt3261 with a dsp!\n", VERSION);
3365 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
3367 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
3370 codec->write = rt3261_write;
3372 #if 0//defined (CONFIG_SND_SOC_RT5623)
3373 struct clk *iis_clk;
3374 //for rt5623 MCLK use
3375 iis_clk = clk_get_sys("rk_i2s.2", "i2s");
3376 if (IS_ERR(iis_clk)) {
3377 DBG("failed to get i2s clk\n");
3378 ret = PTR_ERR(iis_clk);
3380 DBG("I2S2 got i2s clk ok!\n");
3381 clk_enable(iis_clk);
3382 clk_set_rate(iis_clk, 11289600);
3383 rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME, GPIO0D_I2S2_2CH_CLK);
3388 ret=rt3261_reset(codec);
3393 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3394 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3395 RT3261_PWR_BG | RT3261_PWR_VREF2,
3396 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3397 RT3261_PWR_BG | RT3261_PWR_VREF2);
3399 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3400 RT3261_PWR_FV1 | RT3261_PWR_FV2,
3401 RT3261_PWR_FV1 | RT3261_PWR_FV2);
3403 if (rt3261->dmic_en == RT3261_DMIC1) {
3404 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
3405 RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
3406 snd_soc_update_bits(codec, RT3261_DMIC,
3407 RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK,
3408 RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING);
3409 } else if (rt3261->dmic_en == RT3261_DMIC2) {
3410 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
3411 RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
3412 snd_soc_update_bits(codec, RT3261_DMIC,
3413 RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK,
3414 RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING);
3416 snd_soc_write(codec, RT3261_GEN_CTRL2, 0x4040);
3417 ret = snd_soc_read(codec, RT3261_VENDOR_ID);
3418 printk("read codec chip id is 0x%x\n",ret);
3420 snd_soc_update_bits(codec, RT3261_JD_CTRL,
3421 RT3261_JD1_IN4P_MASK | RT3261_JD2_IN4N_MASK,
3422 RT3261_JD1_IN4P_EN | RT3261_JD2_IN4N_EN);
3426 printk("you use an old chip, please use a new one\n");
3428 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3429 RT3261_PWR_HP_L | RT3261_PWR_HP_R,
3431 rt3261_reg_init(codec);
3432 rt3261_customer_redefine(codec, rt3261);
3434 codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
3435 rt3261->codec = codec;
3437 snd_soc_add_codec_controls(codec, rt3261_snd_controls,
3438 ARRAY_SIZE(rt3261_snd_controls));
3439 snd_soc_dapm_new_controls(&codec->dapm, rt3261_dapm_widgets,
3440 ARRAY_SIZE(rt3261_dapm_widgets));
3441 snd_soc_dapm_add_routes(&codec->dapm, rt3261_dapm_routes,
3442 ARRAY_SIZE(rt3261_dapm_routes));
3445 #if defined (CONFIG_SND_SOC_RT3261)
3446 rt3261->dsp_sw = RT3261_DSP_AEC_NS_FENS;
3447 rt3261_dsp_probe(codec);
3451 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
3452 ioctl_ops->index_write = rt3261_index_write;
3453 ioctl_ops->index_read = rt3261_index_read;
3454 ioctl_ops->index_update_bits = rt3261_index_update_bits;
3455 ioctl_ops->ioctl_common = rt3261_ioctl_common;
3456 realtek_ce_init_hwdep(codec);
3461 ret = device_create_file(codec->dev, &dev_attr_index_reg);
3464 "Failed to create index_reg sysfs files: %d\n", ret);
3467 rt3261_codec = codec;
3472 static int rt3261_remove(struct snd_soc_codec *codec)
3474 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3479 static int rt3261_suspend(struct snd_soc_codec *codec)
3481 #if defined (CONFIG_SND_SOC_RT3261)
3482 /* After opening LDO of DSP, then close LDO of codec.
3483 * (1) DSP LDO power on
3484 * (2) DSP core power off
3485 * (3) DSP IIS interface power off
3486 * (4) Toggle pin of codec LDO1 to power off
3488 rt3261_dsp_suspend(codec);
3490 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3494 static int rt3261_resume(struct snd_soc_codec *codec)
3496 rt3261_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3497 #if defined (CONFIG_SND_SOC_RT3261)
3498 /* After opening LDO of codec, then close LDO of DSP. */
3499 rt3261_dsp_resume(codec);
3504 #define rt3261_suspend NULL
3505 #define rt3261_resume NULL
3508 #define RT3261_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3509 #define RT3261_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3510 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3512 struct snd_soc_dai_ops rt3261_aif_dai_ops = {
3513 .hw_params = rt3261_hw_params,
3514 .prepare = rt3261_prepare,
3515 .set_fmt = rt3261_set_dai_fmt,
3516 .set_sysclk = rt3261_set_dai_sysclk,
3517 .set_pll = rt3261_set_dai_pll,
3520 struct snd_soc_dai_driver rt3261_dai[] = {
3522 .name = "rt3261-aif1",
3525 .stream_name = "AIF1 Playback",
3528 .rates = RT3261_STEREO_RATES,
3529 .formats = RT3261_FORMATS,
3532 .stream_name = "AIF1 Capture",
3535 .rates = RT3261_STEREO_RATES,
3536 .formats = RT3261_FORMATS,
3538 .ops = &rt3261_aif_dai_ops,
3541 .name = "rt3261-aif2",
3544 .stream_name = "AIF2 Playback",
3547 .rates = RT3261_STEREO_RATES,
3548 .formats = RT3261_FORMATS,
3551 .stream_name = "AIF2 Capture",
3554 .rates = RT3261_STEREO_RATES,
3555 .formats = RT3261_FORMATS,
3557 .ops = &rt3261_aif_dai_ops,
3561 static struct snd_soc_codec_driver soc_codec_dev_rt3261 = {
3562 .probe = rt3261_probe,
3563 .remove = rt3261_remove,
3564 .suspend = rt3261_suspend,
3565 .resume = rt3261_resume,
3566 .write = rt3261_write,
3567 .set_bias_level = rt3261_set_bias_level,
3568 .reg_cache_size = RT3261_VENDOR_ID2 + 1,
3569 .reg_word_size = sizeof(u16),
3570 .reg_cache_default = rt3261_reg,
3571 .volatile_register = rt3261_volatile_register,
3572 .readable_register = rt3261_readable_register,
3573 .reg_cache_step = 1,
3576 static const struct i2c_device_id rt3261_i2c_id[] = {
3580 MODULE_DEVICE_TABLE(i2c, rt3261_i2c_id);
3586 compatible = "rt3261";
3588 codec-en-gpio = <&gpio3 GPIO_D7 GPIO_ACTIVE_HIGH>;
3590 modem-input-mode = <1>;
3591 lout-to-modem_mode = <1>;
3593 playback-if1-data_control = <0>;
3594 playback-if2-data_control = <0>;
3598 static int rt3261_parse_dt_property(struct device *dev,
3599 struct rt3261_priv *rt3261)
3601 struct device_node *node = dev->of_node;
3603 enum of_gpio_flags flags;
3605 DBG("%s()\n", __FUNCTION__);
3610 rt3261->codec_en_gpio = of_get_named_gpio_flags(node, "codec-en-gpio", 0, &flags);
3611 if (rt3261->codec_en_gpio <= 0) {
3612 DBG("%s() Can not read property codec-en-gpio\n", __FUNCTION__);
3614 ret = devm_gpio_request(dev, rt3261->codec_en_gpio, "codec_en_gpio");
3616 printk("%s() codec_en_gpio request ERROR", __FUNCTION__);
3619 ret = gpio_direction_output(rt3261->codec_en_gpio , !flags);
3621 printk("%s() codec_en_gpio set ERROR", __FUNCTION__);
3626 ret = of_property_read_u32(node, "spk-num", &rt3261->spk_num);
3628 DBG("%s() Can not read property spk-num\n", __FUNCTION__);
3629 rt3261->spk_num = TWO_SPK;
3632 ret = of_property_read_u32(node, "modem-input-mode", &rt3261->modem_input_mode);
3634 DBG("%s() Can not read property modem-input-mode\n", __FUNCTION__);
3635 rt3261->modem_input_mode = DIFFERENTIAL;
3638 ret = of_property_read_u32(node, "lout-to-modem-mode", &rt3261->lout_to_modem_mode);
3640 DBG("%s() Can not read property lout-to-modem-mode\n", __FUNCTION__);
3641 rt3261->lout_to_modem_mode = DIFFERENTIAL;
3644 ret = of_property_read_u32(node, "spk-amplify", &rt3261->spk_amplify);
3646 DBG("%s() Can not read property spk-amplify\n", __FUNCTION__);
3647 rt3261->spk_amplify = SPK_AMPLIFY_ZERO_POINT_SIX_WATT;
3650 ret = of_property_read_u32(node, "playback-if1-data-control", &rt3261->playback_if1_data_control);
3652 DBG("%s() Can not read property playback-if1-data-control\n", __FUNCTION__);
3653 rt3261->playback_if1_data_control = LR_NORMAL;
3656 ret = of_property_read_u32(node, "playback-if2-data-control", &rt3261->playback_if2_data_control);
3658 DBG("%s() Can not read property playback-if2-data-control\n", __FUNCTION__);
3659 rt3261->playback_if1_data_control = LR_NORMAL;
3664 static int rt3261_parse_dt_property(struct device *dev,
3665 struct rt3261_priv *rt3261)
3669 #endif //#ifdef CONFIG_OF
3671 static int rt3261_i2c_probe(struct i2c_client *i2c,
3672 const struct i2c_device_id *id)
3674 struct rt3261_priv *rt3261;
3678 reg = RT3261_VENDOR_ID;
3679 ret = i2c_master_recv(i2c, ®, 1);
3681 printk("rt3261 && rt3224 probe error\n");
3685 rt3261 = devm_kzalloc(&i2c->dev,sizeof(struct rt3261_priv), GFP_KERNEL);
3690 ret = rt3261_parse_dt_property(&i2c->dev, rt3261);
3692 printk("%s() parse device tree property error %d\n", __FUNCTION__, ret);
3696 #if defined (CONFIG_SND_SOC_RT5623)
3697 rt3261->modem_is_open = 0;
3700 i2c_set_clientdata(i2c, rt3261);
3701 DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
3702 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt3261,
3703 rt3261_dai, ARRAY_SIZE(rt3261_dai));
3708 static int rt3261_i2c_remove(struct i2c_client *i2c)
3710 snd_soc_unregister_codec(&i2c->dev);
3711 kfree(i2c_get_clientdata(i2c));
3715 static void rt3261_i2c_shutdown(struct i2c_client *client)
3717 struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
3718 struct snd_soc_codec *codec = rt3261->codec;
3721 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3724 struct i2c_driver rt3261_i2c_driver = {
3727 .owner = THIS_MODULE,
3729 .probe = rt3261_i2c_probe,
3730 .remove = rt3261_i2c_remove,
3731 .shutdown = rt3261_i2c_shutdown,
3732 .id_table = rt3261_i2c_id,
3735 static int __init rt3261_modinit(void)
3737 return i2c_add_driver(&rt3261_i2c_driver);
3739 module_init(rt3261_modinit);
3741 static void __exit rt3261_modexit(void)
3743 i2c_del_driver(&rt3261_i2c_driver);
3745 module_exit(rt3261_modexit);
3747 MODULE_DESCRIPTION("ASoC RT3261 driver");
3748 MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
3749 MODULE_LICENSE("GPL");