2 * rt3261.c -- RT3261 ALSA SoC audio codec driver
4 * Copyright 2011 Realtek Semiconductor Corp.
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/of_gpio.h>
21 #include <linux/clk.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
31 #define DIFFERENTIAL 1
37 SPK_AMPLIFY_ZERO_POINT_FIVE_WATT=1,
38 SPK_AMPLIFY_ZERO_POINT_SIX_WATT,
39 SPK_AMPLIFY_ZERO_POINT_EIGHT_WATT,
50 static struct snd_soc_codec *rt3261_codec;
53 #define DBG(x...) printk(KERN_DEBUG x)
60 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
61 #include "rt_codec_ioctl.h"
62 #include "rt3261_ioctl.h"
67 #if defined (CONFIG_SND_SOC_RT3261)
68 #include "rt3261-dsp.h"
71 #define RT3261_REG_RW 1 /* for debug */
72 #define RT3261_DET_EXT_MIC 0
74 #define VERSION "RT3261_V1.3.0"
76 #if defined (CONFIG_SND_SOC_RT5623)
77 extern void rt5623_on(void);
78 extern void rt5623_off(void);
81 struct rt3261_init_reg {
86 static struct rt3261_init_reg init_list[] = {
87 {RT3261_GEN_CTRL1 , 0x3701},//fa[12:13] = 1'b; fa[8~10]=1; fa[0]=1
88 {RT3261_ADDA_CLK1 , 0x1114},//73[2] = 1'b
89 {RT3261_MICBIAS , 0x3030},//93[5:4] = 11'b
90 {RT3261_CLS_D_OUT , 0xa000},//8d[11] = 0'b
91 {RT3261_CLS_D_OVCD , 0x0334},//8c[8] = 1'b
92 {RT3261_PRIV_INDEX , 0x001d},//PR1d[8] = 1'b;
93 {RT3261_PRIV_DATA , 0x0347},
94 {RT3261_PRIV_INDEX , 0x003d},//PR3d[12] = 0'b; PR3d[9] = 1'b
95 {RT3261_PRIV_DATA , 0x3600},
96 {RT3261_PRIV_INDEX , 0x0012},//PR12 = 0aa8'h
97 {RT3261_PRIV_DATA , 0x0aa8},
98 {RT3261_PRIV_INDEX , 0x0014},//PR14 = 8aaa'h
99 {RT3261_PRIV_DATA , 0x8aaa},
100 {RT3261_PRIV_INDEX , 0x0020},//PR20 = 6115'h
101 {RT3261_PRIV_DATA , 0x6115},
102 {RT3261_PRIV_INDEX , 0x0023},//PR23 = 0804'h
103 {RT3261_PRIV_DATA , 0x0804},
104 {RT3261_SPK_VOL , 0x8888},//SPKMIX -> SPKVOL
105 {RT3261_HP_VOL , 0x8888},
106 {RT3261_OUTPUT , 0x8888},//unmute OUTVOLL/R
107 {RT3261_SPO_CLSD_RATIO , 0x0001},
108 {RT3261_I2S1_SDP , 0xd000},
109 // huangcun 20130816 s
112 {RT3261_DSP_PATH2 , 0x0000},
113 {RT3261_PRIV_INDEX , 0x003f},//PR3d[14] = 0'b;
114 {RT3261_PRIV_DATA , 0x0000},
115 {RT3261_DAC2_CTRL , 0x0000},
116 {RT3261_MONO_DAC_MIXER, 0x4444},
117 {RT3261_SPK_L_MIXER, 0x003a},
118 {RT3261_SPK_R_MIXER, 0x003a},
119 {RT3261_SPO_L_MIXER, 0xc800},
121 {RT3261_OUT_L3_MIXER, 0x01fd},
122 {RT3261_OUT_R3_MIXER, 0x01fd},
123 {RT3261_HPO_MIXER, 0xc000},
127 {RT3261_IN1_IN2, 0x2080},//boost1 = 24db
128 {RT3261_REC_R2_MIXER, 0x007d},
129 {RT3261_MONO_ADC_MIXER,0x7030},
130 //{RT3261_GEN_CTRL1 , 0x2701},//regfa[13]=0
131 {RT3261_DSP_PATH2 , 0x0400},
132 {RT3261_DIG_INF_DATA, 0x0300},//right copy to left
136 {RT3261_DSP_PATH2 , 0x0000},
137 {RT3261_PRIV_INDEX , 0x003f},//PR3d[14] = 0'b;
138 {RT3261_PRIV_DATA , 0x0000},
139 {RT3261_DAC2_CTRL , 0x0000},
140 {RT3261_MONO_DAC_MIXER, 0x4444},
141 {RT3261_OUT_L3_MIXER, 0x01fd},
142 {RT3261_OUT_R3_MIXER, 0x01fd},
143 {RT3261_LOUT_MIXER, 0xc000},
145 // huangcun 20130816 e
147 #define RT3261_INIT_REG_LEN ARRAY_SIZE(init_list)
149 static int rt3261_reg_init(struct snd_soc_codec *codec)
153 for (i = 0; i < RT3261_INIT_REG_LEN; i++)
154 snd_soc_write(codec, init_list[i].reg, init_list[i].val);
159 static int rt3261_customer_redefine(struct snd_soc_codec *codec, struct rt3261_priv *rt3261)
161 if(rt3261->spk_num==TWO_SPK)
163 snd_soc_update_bits(codec, RT3261_SPO_L_MIXER,
164 RT3261_M_SV_R_SPM_L | RT3261_M_SV_L_SPM_L,
165 1 << RT3261_M_SV_R_SPM_L_SFT | 0 << RT3261_M_SV_L_SPM_L_SFT);
166 snd_soc_update_bits(codec, RT3261_SPO_R_MIXER,
167 RT3261_M_SV_R_SPM_R, 0 << RT3261_M_SV_R_SPM_R_SFT);
171 snd_soc_update_bits(codec, RT3261_SPO_L_MIXER,
172 RT3261_M_SV_R_SPM_L | RT3261_M_SV_L_SPM_L,
173 0 << RT3261_M_SV_R_SPM_L_SFT | 0 << RT3261_M_SV_L_SPM_L_SFT);
174 snd_soc_update_bits(codec, RT3261_SPO_R_MIXER,
175 RT3261_M_SV_R_SPM_R, 1 << RT3261_M_SV_R_SPM_R_SFT);
179 snd_soc_update_bits(codec, RT3261_IN3_IN4,
180 RT3261_IN_DF2, rt3261->modem_input_mode << RT3261_IN_SFT2);
181 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
182 RT3261_LOUT_DF_MASK, rt3261->lout_to_modem_mode << RT3261_LOUT_DF);
183 snd_soc_update_bits(codec, RT3261_SPO_CLSD_RATIO,
184 RT3261_SPO_CLSD_RATIO_MASK, rt3261->spk_amplify);
185 snd_soc_update_bits(codec, RT3261_DIG_INF_DATA,
186 RT3261_IF1_DAC_SEL_MASK | RT3261_IF2_DAC_SEL_MASK,
187 (rt3261->playback_if1_data_control<<RT3261_IF1_DAC_SEL_SFT) | (rt3261->playback_if2_data_control<<RT3261_IF2_DAC_SEL_SFT));
193 static int rt3261_index_sync(struct snd_soc_codec *codec)
197 for (i = 0; i < RT3261_INIT_REG_LEN; i++)
198 if (RT3261_PRIV_INDEX == init_list[i].reg ||
199 RT3261_PRIV_DATA == init_list[i].reg)
200 snd_soc_write(codec, init_list[i].reg,
205 static const u16 rt3261_reg[RT3261_VENDOR_ID2 + 1] = {
206 [RT3261_RESET] = 0x000c,
207 [RT3261_SPK_VOL] = 0xc8c8,
208 [RT3261_HP_VOL] = 0xc8c8,
209 [RT3261_OUTPUT] = 0xc8c8,
210 [RT3261_MONO_OUT] = 0x8000,
211 [RT3261_INL_INR_VOL] = 0x0808,
212 [RT3261_DAC1_DIG_VOL] = 0xafaf,
213 [RT3261_DAC2_DIG_VOL] = 0xafaf,
214 [RT3261_ADC_DIG_VOL] = 0x2f2f,
215 [RT3261_ADC_DATA] = 0x2f2f,
216 [RT3261_STO_ADC_MIXER] = 0x7060,
217 [RT3261_MONO_ADC_MIXER] = 0x7070,
218 [RT3261_AD_DA_MIXER] = 0x8080,
219 [RT3261_STO_DAC_MIXER] = 0x5454,
220 [RT3261_MONO_DAC_MIXER] = 0x5454,
221 [RT3261_DIG_MIXER] = 0xaa00,
222 [RT3261_DSP_PATH2] = 0xa000,
223 [RT3261_REC_L2_MIXER] = 0x007f,
224 [RT3261_REC_R2_MIXER] = 0x007f,
225 [RT3261_HPO_MIXER] = 0xe000,
226 [RT3261_SPK_L_MIXER] = 0x003e,
227 [RT3261_SPK_R_MIXER] = 0x003e,
228 [RT3261_SPO_L_MIXER] = 0xf800,
229 [RT3261_SPO_R_MIXER] = 0x3800,
230 [RT3261_SPO_CLSD_RATIO] = 0x0004,
231 [RT3261_MONO_MIXER] = 0xfc00,
232 [RT3261_OUT_L3_MIXER] = 0x01ff,
233 [RT3261_OUT_R3_MIXER] = 0x01ff,
234 [RT3261_LOUT_MIXER] = 0xf000,
235 [RT3261_PWR_ANLG1] = 0x00c0,
236 [RT3261_I2S1_SDP] = 0x8000,
237 [RT3261_I2S2_SDP] = 0x8000,
238 [RT3261_I2S3_SDP] = 0x8000,
239 [RT3261_ADDA_CLK1] = 0x1110,
240 [RT3261_ADDA_CLK2] = 0x0c00,
241 [RT3261_DMIC] = 0x1d00,
242 [RT3261_ASRC_3] = 0x0008,
243 [RT3261_HP_OVCD] = 0x0600,
244 [RT3261_CLS_D_OVCD] = 0x0228,
245 [RT3261_CLS_D_OUT] = 0xa800,
246 [RT3261_DEPOP_M1] = 0x0004,
247 [RT3261_DEPOP_M2] = 0x1100,
248 [RT3261_DEPOP_M3] = 0x0646,
249 [RT3261_CHARGE_PUMP] = 0x0c00,
250 [RT3261_MICBIAS] = 0x3000,
251 [RT3261_EQ_CTRL1] = 0x2080,
252 [RT3261_DRC_AGC_1] = 0x2206,
253 [RT3261_DRC_AGC_2] = 0x1f00,
254 [RT3261_ANC_CTRL1] = 0x034b,
255 [RT3261_ANC_CTRL2] = 0x0066,
256 [RT3261_ANC_CTRL3] = 0x000b,
257 [RT3261_GPIO_CTRL1] = 0x0400,
258 [RT3261_DSP_CTRL3] = 0x2000,
259 [RT3261_BASE_BACK] = 0x0013,
260 [RT3261_MP3_PLUS1] = 0x0680,
261 [RT3261_MP3_PLUS2] = 0x1c17,
262 [RT3261_3D_HP] = 0x8c00,
263 [RT3261_ADJ_HPF] = 0x2a20,
264 [RT3261_HP_CALIB_AMP_DET] = 0x0400,
265 [RT3261_SV_ZCD1] = 0x0809,
266 [RT3261_VENDOR_ID1] = 0x10ec,
267 [RT3261_VENDOR_ID2] = 0x6231,
270 static int rt3261_reset(struct snd_soc_codec *codec)
272 return snd_soc_write(codec, RT3261_RESET, 0);
275 static unsigned int rt3261_read(struct snd_soc_codec *codec,
280 val = codec->hw_read(codec, reg);
284 static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
285 unsigned int value, const void *data, int len)
287 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
290 if (!snd_soc_codec_volatile_register(codec, reg) &&
291 reg < codec->driver->reg_cache_size &&
292 !codec->cache_bypass) {
293 ret = snd_soc_cache_write(codec, reg, value);
298 if (codec->cache_only) {
299 codec->cache_sync = 1;
303 if (i2c_master_send(rt3261->i2c, data, len) == len)
309 static int rt3261_write(struct snd_soc_codec *codec, unsigned int reg,
315 data[1] = (value >> 8) & 0xff;
316 data[2] = value & 0xff;
318 DBG("rt3261_write 0x%x = 0x%x\n",reg,value);
319 return do_hw_write(codec, reg, value, data, 3);
323 * rt3261_index_write - Write private register.
324 * @codec: SoC audio codec device.
325 * @reg: Private register index.
326 * @value: Private register Data.
328 * Modify private register for advanced setting. It can be written through
329 * private index (0x6a) and data (0x6c) register.
331 * Returns 0 for success or negative error code.
333 static int rt3261_index_write(struct snd_soc_codec *codec,
334 unsigned int reg, unsigned int value)
338 ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
340 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
343 ret = snd_soc_write(codec, RT3261_PRIV_DATA, value);
345 dev_err(codec->dev, "Failed to set private value: %d\n", ret);
355 * rt3261_index_read - Read private register.
356 * @codec: SoC audio codec device.
357 * @reg: Private register index.
359 * Read advanced setting from private register. It can be read through
360 * private index (0x6a) and data (0x6c) register.
362 * Returns private register value or negative error code.
364 static unsigned int rt3261_index_read(
365 struct snd_soc_codec *codec, unsigned int reg)
369 ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
371 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
374 return snd_soc_read(codec, RT3261_PRIV_DATA);
378 * rt3261_index_update_bits - update private register bits
379 * @codec: audio codec
380 * @reg: Private register index.
381 * @mask: register mask
384 * Writes new register value.
386 * Returns 1 for change, 0 for no change, or negative error code.
388 static int rt3261_index_update_bits(struct snd_soc_codec *codec,
389 unsigned int reg, unsigned int mask, unsigned int value)
391 unsigned int old, new;
394 ret = rt3261_index_read(codec, reg);
396 dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
401 new = (old & ~mask) | (value & mask);
404 ret = rt3261_index_write(codec, reg, new);
407 "Failed to write private reg: %d\n", ret);
417 static int rt3261_volatile_register(
418 struct snd_soc_codec *codec, unsigned int reg)
422 case RT3261_PRIV_DATA:
424 case RT3261_EQ_CTRL1:
425 case RT3261_DRC_AGC_1:
426 case RT3261_ANC_CTRL1:
427 case RT3261_IRQ_CTRL2:
428 case RT3261_INT_IRQ_ST:
429 case RT3261_DSP_CTRL2:
430 case RT3261_DSP_CTRL3:
431 case RT3261_PGM_REG_ARR1:
432 case RT3261_PGM_REG_ARR3:
433 case RT3261_VENDOR_ID:
434 case RT3261_VENDOR_ID1:
435 case RT3261_VENDOR_ID2:
442 static int rt3261_readable_register(
443 struct snd_soc_codec *codec, unsigned int reg)
450 case RT3261_MONO_OUT:
453 case RT3261_INL_INR_VOL:
454 case RT3261_DAC1_DIG_VOL:
455 case RT3261_DAC2_DIG_VOL:
456 case RT3261_DAC2_CTRL:
457 case RT3261_ADC_DIG_VOL:
458 case RT3261_ADC_DATA:
459 case RT3261_ADC_BST_VOL:
460 case RT3261_STO_ADC_MIXER:
461 case RT3261_MONO_ADC_MIXER:
462 case RT3261_AD_DA_MIXER:
463 case RT3261_STO_DAC_MIXER:
464 case RT3261_MONO_DAC_MIXER:
465 case RT3261_DIG_MIXER:
466 case RT3261_DSP_PATH1:
467 case RT3261_DSP_PATH2:
468 case RT3261_DIG_INF_DATA:
469 case RT3261_REC_L1_MIXER:
470 case RT3261_REC_L2_MIXER:
471 case RT3261_REC_R1_MIXER:
472 case RT3261_REC_R2_MIXER:
473 case RT3261_HPO_MIXER:
474 case RT3261_SPK_L_MIXER:
475 case RT3261_SPK_R_MIXER:
476 case RT3261_SPO_L_MIXER:
477 case RT3261_SPO_R_MIXER:
478 case RT3261_SPO_CLSD_RATIO:
479 case RT3261_MONO_MIXER:
480 case RT3261_OUT_L1_MIXER:
481 case RT3261_OUT_L2_MIXER:
482 case RT3261_OUT_L3_MIXER:
483 case RT3261_OUT_R1_MIXER:
484 case RT3261_OUT_R2_MIXER:
485 case RT3261_OUT_R3_MIXER:
486 case RT3261_LOUT_MIXER:
487 case RT3261_PWR_DIG1:
488 case RT3261_PWR_DIG2:
489 case RT3261_PWR_ANLG1:
490 case RT3261_PWR_ANLG2:
491 case RT3261_PWR_MIXER:
493 case RT3261_PRIV_INDEX:
494 case RT3261_PRIV_DATA:
495 case RT3261_I2S1_SDP:
496 case RT3261_I2S2_SDP:
497 case RT3261_I2S3_SDP:
498 case RT3261_ADDA_CLK1:
499 case RT3261_ADDA_CLK2:
502 case RT3261_PLL_CTRL1:
503 case RT3261_PLL_CTRL2:
510 case RT3261_CLS_D_OVCD:
511 case RT3261_CLS_D_OUT:
512 case RT3261_DEPOP_M1:
513 case RT3261_DEPOP_M2:
514 case RT3261_DEPOP_M3:
515 case RT3261_CHARGE_PUMP:
516 case RT3261_PV_DET_SPK_G:
518 case RT3261_EQ_CTRL1:
519 case RT3261_EQ_CTRL2:
520 case RT3261_WIND_FILTER:
521 case RT3261_DRC_AGC_1:
522 case RT3261_DRC_AGC_2:
523 case RT3261_DRC_AGC_3:
525 case RT3261_ANC_CTRL1:
526 case RT3261_ANC_CTRL2:
527 case RT3261_ANC_CTRL3:
530 case RT3261_IRQ_CTRL1:
531 case RT3261_IRQ_CTRL2:
532 case RT3261_INT_IRQ_ST:
533 case RT3261_GPIO_CTRL1:
534 case RT3261_GPIO_CTRL2:
535 case RT3261_GPIO_CTRL3:
536 case RT3261_DSP_CTRL1:
537 case RT3261_DSP_CTRL2:
538 case RT3261_DSP_CTRL3:
539 case RT3261_DSP_CTRL4:
540 case RT3261_PGM_REG_ARR1:
541 case RT3261_PGM_REG_ARR2:
542 case RT3261_PGM_REG_ARR3:
543 case RT3261_PGM_REG_ARR4:
544 case RT3261_PGM_REG_ARR5:
545 case RT3261_SCB_FUNC:
546 case RT3261_SCB_CTRL:
547 case RT3261_BASE_BACK:
548 case RT3261_MP3_PLUS1:
549 case RT3261_MP3_PLUS2:
552 case RT3261_HP_CALIB_AMP_DET:
553 case RT3261_HP_CALIB2:
556 case RT3261_GEN_CTRL1:
557 case RT3261_GEN_CTRL2:
558 case RT3261_GEN_CTRL3:
559 case RT3261_VENDOR_ID:
560 case RT3261_VENDOR_ID1:
561 case RT3261_VENDOR_ID2:
569 * rt3261_headset_mic_detect - Detect headset.
570 * @codec: SoC audio codec device.
571 * @jack_insert: Jack insert or not.
573 * Detect whether is headset or not when jack inserted.
575 * Returns detect status.
577 int rt3261_headset_mic_detect(int jack_insert)
584 if(rt3261_codec == NULL){
589 if (SND_SOC_BIAS_OFF == rt3261_codec->dapm.bias_level) {
590 snd_soc_write(rt3261_codec, RT3261_PWR_ANLG1, 0x2004);
591 snd_soc_write(rt3261_codec, RT3261_MICBIAS, 0x3830);
592 snd_soc_write(rt3261_codec, RT3261_GEN_CTRL1 , 0x3701);
595 sclk_src = snd_soc_read(rt3261_codec, RT3261_GLB_CLK) &
596 RT3261_SCLK_SRC_MASK;
597 snd_soc_update_bits(rt3261_codec, RT3261_GLB_CLK,
598 RT3261_SCLK_SRC_MASK, 0x3 << RT3261_SCLK_SRC_SFT);
600 snd_soc_update_bits(rt3261_codec, RT3261_PWR_ANLG1,
601 RT3261_PWR_LDO2, RT3261_PWR_LDO2);
602 snd_soc_update_bits(rt3261_codec, RT3261_PWR_ANLG2,
603 RT3261_PWR_MB1, RT3261_PWR_MB1);
605 snd_soc_update_bits(rt3261_codec, RT3261_MICBIAS,
606 RT3261_MIC1_OVCD_MASK | RT3261_MIC1_OVTH_MASK |
607 RT3261_PWR_CLK25M_MASK | RT3261_PWR_MB_MASK,
608 RT3261_MIC1_OVCD_EN | RT3261_MIC1_OVTH_600UA |
609 RT3261_PWR_MB_PU | RT3261_PWR_CLK25M_PU);
610 snd_soc_update_bits(rt3261_codec, RT3261_GEN_CTRL1,
613 if (snd_soc_read(rt3261_codec, RT3261_IRQ_CTRL2) & 0x8)
614 jack_type = RT3261_HEADPHO_DET;
616 jack_type = RT3261_HEADSET_DET;
617 snd_soc_update_bits(rt3261_codec, RT3261_IRQ_CTRL2,
618 RT3261_MB1_OC_CLR, 0);
620 snd_soc_update_bits(rt3261_codec, RT3261_GLB_CLK,
621 RT3261_SCLK_SRC_MASK, sclk_src);
624 snd_soc_update_bits(rt3261_codec, RT3261_MICBIAS,
625 RT3261_MIC1_OVCD_MASK,
626 RT3261_MIC1_OVCD_DIS);
628 jack_type = RT3261_NO_JACK;
633 EXPORT_SYMBOL(rt3261_headset_mic_detect);
635 static const char *rt3261_dacr2_src[] = { "TxDC_R", "TxDP_R" };
637 static const SOC_ENUM_SINGLE_DECL(rt3261_dacr2_enum,RT3261_DUMMY_PR3F,
638 14, rt3261_dacr2_src);
639 static const struct snd_kcontrol_new rt3261_dacr2_mux =
640 SOC_DAPM_ENUM("Mono dacr source", rt3261_dacr2_enum);
642 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
643 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
644 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
645 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
646 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
648 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
649 static unsigned int bst_tlv[] = {
650 TLV_DB_RANGE_HEAD(7),
651 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
652 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
653 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
654 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
655 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
656 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
657 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
660 static int rt3261_dmic_get(struct snd_kcontrol *kcontrol,
661 struct snd_ctl_elem_value *ucontrol)
663 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
664 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
666 ucontrol->value.integer.value[0] = rt3261->dmic_en;
671 static int rt3261_dmic_put(struct snd_kcontrol *kcontrol,
672 struct snd_ctl_elem_value *ucontrol)
674 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
675 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
677 if (rt3261->dmic_en == ucontrol->value.integer.value[0])
680 rt3261->dmic_en = ucontrol->value.integer.value[0];
681 switch (rt3261->dmic_en) {
682 case RT3261_DMIC_DIS:
683 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
684 RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK |
686 RT3261_GP2_PIN_GPIO2 | RT3261_GP3_PIN_GPIO3 |
687 RT3261_GP4_PIN_GPIO4);
688 snd_soc_update_bits(codec, RT3261_DMIC,
689 RT3261_DMIC_1_DP_MASK | RT3261_DMIC_2_DP_MASK,
690 RT3261_DMIC_1_DP_GPIO3 | RT3261_DMIC_2_DP_GPIO4);
691 snd_soc_update_bits(codec, RT3261_DMIC,
692 RT3261_DMIC_1_EN_MASK | RT3261_DMIC_2_EN_MASK,
693 RT3261_DMIC_1_DIS | RT3261_DMIC_2_DIS);
697 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
698 RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK,
699 RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP3_PIN_DMIC1_SDA);
700 snd_soc_update_bits(codec, RT3261_DMIC,
701 RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK |
702 RT3261_DMIC_1_DP_MASK,
703 RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING |
704 RT3261_DMIC_1_DP_IN1P);
705 snd_soc_update_bits(codec, RT3261_DMIC,
706 RT3261_DMIC_1_EN_MASK, RT3261_DMIC_1_EN);
710 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
711 RT3261_GP2_PIN_MASK | RT3261_GP4_PIN_MASK,
712 RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP4_PIN_DMIC2_SDA);
713 snd_soc_update_bits(codec, RT3261_DMIC,
714 RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK |
715 RT3261_DMIC_2_DP_MASK,
716 RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING |
717 RT3261_DMIC_2_DP_IN1N);
718 snd_soc_update_bits(codec, RT3261_DMIC,
719 RT3261_DMIC_2_EN_MASK, RT3261_DMIC_2_EN);
729 static int rt3261_asrc_get(struct snd_kcontrol *kcontrol,
730 struct snd_ctl_elem_value *ucontrol)
732 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
733 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
735 DBG("%s\n", __FUNCTION__);
736 ucontrol->value.integer.value[0] = rt3261->asrc_en;
741 static int rt3261_asrc_put(struct snd_kcontrol *kcontrol,
742 struct snd_ctl_elem_value *ucontrol)
744 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
745 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
747 DBG("%s\n", __FUNCTION__);
748 if (rt3261->asrc_en == ucontrol->value.integer.value[0])
751 rt3261->asrc_en = ucontrol->value.integer.value[0];
752 switch (rt3261->asrc_en) {
753 case RT3261_ASRC_DIS://disable ASRC
754 DBG("%s disable\n", __FUNCTION__);
755 snd_soc_write(codec, RT3261_ASRC_1, 0x0);
756 snd_soc_write(codec, RT3261_ASRC_2, 0x0);
757 snd_soc_update_bits(codec, RT3261_GEN_CTRL1, 0x70, 0x0); //bard 8-29
758 mutex_lock(&codec->mutex);
759 snd_soc_dapm_disable_pin(&codec->dapm, "DAC L2 Power"); //bard 9-4
760 snd_soc_dapm_disable_pin(&codec->dapm, "stereo filter"); //bard 9-4
761 snd_soc_dapm_sync(&codec->dapm); //bard 9-4
762 mutex_unlock(&codec->mutex);
765 case RT3261_ASRC_EN://enable ASRC
766 DBG("%s enable\n", __FUNCTION__);
767 snd_soc_write(codec, RT3261_ASRC_1, 0x9800);
768 snd_soc_write(codec, RT3261_ASRC_2, 0xF800);
769 snd_soc_update_bits(codec, RT3261_GEN_CTRL1, 0x70, 0x70); //bard 8-29
770 snd_soc_write(codec, RT3261_JD_CTRL, 0x03); //bard 8-29
771 //snd_soc_update_bits(codec, RT3261_PWR_DIG1, 0x0080, 0x0080);
772 //snd_soc_update_bits(codec, RT3261_PWR_DIG2, 0x8000, 0x8000);
773 mutex_lock(&codec->mutex);
774 snd_soc_dapm_force_enable_pin(&codec->dapm, "DAC L2 Power"); //bard 9-4
775 snd_soc_dapm_force_enable_pin(&codec->dapm, "stereo filter"); //bard 9-4
776 snd_soc_dapm_sync(&codec->dapm); //bard 9-4
777 mutex_unlock(&codec->mutex);
778 snd_soc_write(codec, RT3261_ADDA_CLK1, 0x1114);
789 static int rt3261_mic1_get(struct snd_kcontrol *kcontrol,
790 struct snd_ctl_elem_value *ucontrol)
792 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
794 ucontrol->value.integer.value[0] =
795 (snd_soc_read(codec, RT3261_REC_L2_MIXER) & RT3261_M_BST1_RM_L) >> RT3261_M_BST1_RM_L_SFT;
800 static int rt3261_mic1_put(struct snd_kcontrol *kcontrol,
801 struct snd_ctl_elem_value *ucontrol)
803 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
805 if(ucontrol->value.integer.value[0]==0) {
806 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
807 RT3261_M_BST1_RM_L, 0);
808 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
809 RT3261_M_BST1_RM_R, 0);
811 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
812 RT3261_M_BST1_RM_L, RT3261_M_BST1_RM_L);
813 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
814 RT3261_M_BST1_RM_R, RT3261_M_BST1_RM_R);
820 static int rt3261_mic2_get(struct snd_kcontrol *kcontrol,
821 struct snd_ctl_elem_value *ucontrol)
823 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
825 ucontrol->value.integer.value[0] =
826 (snd_soc_read(codec, RT3261_REC_L2_MIXER) & RT3261_M_BST1_RM_L) >> RT3261_M_BST1_RM_L_SFT;
831 static int rt3261_mic2_put(struct snd_kcontrol *kcontrol,
832 struct snd_ctl_elem_value *ucontrol)
834 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
836 if(ucontrol->value.integer.value[0]==0) {
837 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
838 RT3261_M_BST4_RM_L, 0);
839 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
840 RT3261_M_BST4_RM_R, 0);
842 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
843 RT3261_M_BST4_RM_L, RT3261_M_BST4_RM_L);
844 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
845 RT3261_M_BST4_RM_R, RT3261_M_BST4_RM_R);
852 void rt3261_hp_amp_power(struct snd_soc_codec *codec, int on)
854 static int hp_amp_power_count;
855 DBG("rt3261_hp_amp_power on=%d hp_amp_power_count=%d\n",on,hp_amp_power_count);
858 if(hp_amp_power_count <= 0) {
859 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
860 RT3261_PWR_I2S1, RT3261_PWR_I2S1);
861 /* depop parameters */
862 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0200); //bard 12-6
863 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
864 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
865 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
866 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
867 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
868 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
869 /* headphone amp power on */
870 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
871 RT3261_PWR_FV1 | RT3261_PWR_FV2 , 0);
872 snd_soc_update_bits(codec, RT3261_PWR_VOL,
873 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
874 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
875 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
876 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA , //bard 10-18
877 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA); //bard 10-18
879 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
880 RT3261_PWR_FV1 | RT3261_PWR_FV2,
881 RT3261_PWR_FV1 | RT3261_PWR_FV2);
883 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
884 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
885 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
886 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
887 RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
888 RT3261_HP_CO_EN | RT3261_HP_SG_EN);
889 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0400); //bard 12-6
891 hp_amp_power_count++;
893 hp_amp_power_count--;
894 if(hp_amp_power_count <= 0) {
895 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
896 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
897 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
898 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
899 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
900 /* headphone amp power down */
901 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
902 RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
903 RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
904 RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
905 RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
906 RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
907 RT3261_HP_SG_EN | RT3261_HP_CB_PD);
908 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
909 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA , //bard 10-18
915 static int rt3261_hp_mute_get(struct snd_kcontrol *kcontrol,
916 struct snd_ctl_elem_value *ucontrol)
918 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
920 ucontrol->value.integer.value[0] =
921 !((snd_soc_read(codec, RT3261_HP_VOL) & RT3261_L_MUTE) >> RT3261_L_MUTE_SFT);
926 static int rt3261_hp_mute_put(struct snd_kcontrol *kcontrol,
927 struct snd_ctl_elem_value *ucontrol)
929 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
931 if(ucontrol->value.integer.value[0]) {
932 /* headphone unmute sequence */
933 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
934 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
935 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
936 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
937 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
938 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
939 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
940 RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
941 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
942 RT3261_RSTN_MASK, RT3261_RSTN_EN);
943 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
944 RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
945 RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
946 snd_soc_update_bits(codec, RT3261_HP_VOL,
947 RT3261_L_MUTE | RT3261_R_MUTE, 0);
949 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
950 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
951 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
952 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
955 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
956 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
959 /* headphone mute sequence */
960 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
961 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
962 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
963 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
964 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
965 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
966 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
967 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
968 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
969 RT3261_RSTP_MASK, RT3261_RSTP_EN);
970 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
971 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
972 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
973 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
975 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
976 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
979 snd_soc_update_bits(codec, RT3261_HP_VOL,
980 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
982 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
983 RT3261_HP_R_SMT_MASK | RT3261_HP_L_SMT_MASK,
984 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
989 #if defined (CONFIG_SND_SOC_RT5623)
990 static int rt3261_modem_input_switch_get(struct snd_kcontrol *kcontrol,
991 struct snd_ctl_elem_value *ucontrol)
993 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
994 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
996 ucontrol->value.integer.value[0] = rt3261->modem_is_open;
1000 static int rt3261_modem_input_switch_put(struct snd_kcontrol *kcontrol,
1001 struct snd_ctl_elem_value *ucontrol)
1003 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1004 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
1006 if(ucontrol->value.integer.value[0]) {
1008 rt3261->modem_is_open = 1;
1011 rt3261->modem_is_open = 0;
1017 static int rt3261_modem_input_switch_get(struct snd_kcontrol *kcontrol,
1018 struct snd_ctl_elem_value *ucontrol)
1023 static int rt3261_modem_input_switch_put(struct snd_kcontrol *kcontrol,
1024 struct snd_ctl_elem_value *ucontrol)
1030 static int rt3261_dacr_sel_get(struct snd_kcontrol *kcontrol,
1031 struct snd_ctl_elem_value *ucontrol)
1033 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1035 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x4000) >> 14;
1040 static int rt3261_dacr_sel_put(struct snd_kcontrol *kcontrol,
1041 struct snd_ctl_elem_value *ucontrol)
1043 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1045 if(ucontrol->value.integer.value[0])
1046 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x4000, 0x4000);
1048 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x4000, 0x0);
1054 static int rt3261_rxdp_sel_get(struct snd_kcontrol *kcontrol,
1055 struct snd_ctl_elem_value *ucontrol)
1057 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1059 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x0400) >> 10;
1064 static int rt3261_rxdp_sel_put(struct snd_kcontrol *kcontrol,
1065 struct snd_ctl_elem_value *ucontrol)
1067 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1069 if(ucontrol->value.integer.value[0])
1070 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0400, 0x0400);
1072 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0400, 0x0);
1078 static int rt3261_rxdp1_sel_get(struct snd_kcontrol *kcontrol,
1079 struct snd_ctl_elem_value *ucontrol)
1081 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1083 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x0200) >> 9;
1088 static int rt3261_rxdp1_sel_put(struct snd_kcontrol *kcontrol,
1089 struct snd_ctl_elem_value *ucontrol)
1091 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1093 if(ucontrol->value.integer.value[0])
1094 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0200, 0x0200);
1096 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0200, 0x0);
1102 /* IN1/IN2 Input Type */
1103 static const char *rt3261_input_mode[] = {
1104 "Single ended", "Differential"};
1106 static const SOC_ENUM_SINGLE_DECL(
1107 rt3261_in1_mode_enum, RT3261_IN1_IN2,
1108 RT3261_IN_SFT1, rt3261_input_mode);
1110 static const SOC_ENUM_SINGLE_DECL(
1111 rt3261_in2_mode_enum, RT3261_IN3_IN4,
1112 RT3261_IN_SFT2, rt3261_input_mode);
1114 static const SOC_ENUM_SINGLE_DECL(
1115 rt3261_in3_mode_enum, RT3261_IN1_IN2,
1116 RT3261_IN_SFT2, rt3261_input_mode);
1119 static const char *rt3261_output_mode[] = {
1120 "Single ended", "Differential"};
1122 static const SOC_ENUM_SINGLE_DECL(
1123 rt3261_lout_mode_enum, RT3261_GEN_CTRL1,
1124 RT3261_LOUT_DF, rt3261_output_mode);
1127 /* Interface data select */
1128 static const char *rt3261_data_select[] = {
1129 "Normal", "Swap", "left copy to right", "right copy to left"};
1131 static const SOC_ENUM_SINGLE_DECL(rt3261_if1_dac_enum, RT3261_DIG_INF_DATA,
1132 RT3261_IF1_DAC_SEL_SFT, rt3261_data_select);
1134 static const SOC_ENUM_SINGLE_DECL(rt3261_if1_adc_enum, RT3261_DIG_INF_DATA,
1135 RT3261_IF1_ADC_SEL_SFT, rt3261_data_select);
1137 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_dac_enum, RT3261_DIG_INF_DATA,
1138 RT3261_IF2_DAC_SEL_SFT, rt3261_data_select);
1140 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_enum, RT3261_DIG_INF_DATA,
1141 RT3261_IF2_ADC_SEL_SFT, rt3261_data_select);
1143 static const SOC_ENUM_SINGLE_DECL(rt3261_if3_dac_enum, RT3261_DIG_INF_DATA,
1144 RT3261_IF3_DAC_SEL_SFT, rt3261_data_select);
1146 static const SOC_ENUM_SINGLE_DECL(rt3261_if3_adc_enum, RT3261_DIG_INF_DATA,
1147 RT3261_IF3_ADC_SEL_SFT, rt3261_data_select);
1149 /* Class D speaker gain ratio */
1150 static const char *rt3261_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
1151 "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
1153 static const SOC_ENUM_SINGLE_DECL(
1154 rt3261_clsd_spk_ratio_enum, RT3261_CLS_D_OUT,
1155 RT3261_CLSD_RATIO_SFT, rt3261_clsd_spk_ratio);
1158 static const char *rt3261_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
1160 static const SOC_ENUM_SINGLE_DECL(rt3261_dmic_enum, 0, 0, rt3261_dmic_mode);
1162 static const char *rt3261_asrc_mode[] = {"Disable", "Enable"};
1164 static const SOC_ENUM_SINGLE_DECL(rt3261_asrc_enum, 0, 0, rt3261_asrc_mode);
1167 static const char *rt3261_dacr_sel_mode[] = {"IF2_DAC", "IF2_ADC"};
1169 static const SOC_ENUM_SINGLE_DECL(rt3261_dacr_sel_enum, 0, 0, rt3261_dacr_sel_mode);
1171 static const char *rt3261_rxdp_sel_mode[] = {"RxDP2", "RxDP1"};
1173 static const SOC_ENUM_SINGLE_DECL(rt3261_rxdp_sel_enum, 0, 0, rt3261_rxdp_sel_mode);
1175 static const char *rt3261_rxdp1_sel_mode[] = {"DAC1", "IF1_DAC"};
1177 static const SOC_ENUM_SINGLE_DECL(rt3261_rxdp1_sel_enum, 0, 0, rt3261_rxdp1_sel_mode);
1181 static const char *rt3261_mic_mode[] = {"off", "on",};
1182 static const SOC_ENUM_SINGLE_DECL(rt3261_mic_enum, 0, 0, rt3261_mic_mode);
1185 static const char *rt3261_hp_mute_mode[] = {"off", "on",};
1187 static const SOC_ENUM_SINGLE_DECL(rt3261_hp_mute_enum, 0, 0, rt3261_hp_mute_mode);
1189 static const char *rt3261_modem_input_switch_mode[] = {"off", "on",};
1191 static const SOC_ENUM_SINGLE_DECL(rt3261_modem_input_switch_enum, 0, 0, rt3261_modem_input_switch_mode);
1193 #ifdef RT3261_REG_RW
1194 #define REGVAL_MAX 0xffff
1195 static unsigned int regctl_addr;
1196 static int rt3261_regctl_info(struct snd_kcontrol *kcontrol,
1197 struct snd_ctl_elem_info *uinfo)
1199 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1201 uinfo->value.integer.min = 0;
1202 uinfo->value.integer.max = REGVAL_MAX;
1206 static int rt3261_regctl_get(struct snd_kcontrol *kcontrol,
1207 struct snd_ctl_elem_value *ucontrol)
1209 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1210 ucontrol->value.integer.value[0] = regctl_addr;
1211 ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
1215 static int rt3261_regctl_put(struct snd_kcontrol *kcontrol,
1216 struct snd_ctl_elem_value *ucontrol)
1218 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1219 regctl_addr = ucontrol->value.integer.value[0];
1220 if(ucontrol->value.integer.value[1] <= REGVAL_MAX)
1221 snd_soc_write(codec, regctl_addr, ucontrol->value.integer.value[1]);
1227 static int rt3261_vol_rescale_get(struct snd_kcontrol *kcontrol,
1228 struct snd_ctl_elem_value *ucontrol)
1230 struct soc_mixer_control *mc =
1231 (struct soc_mixer_control *)kcontrol->private_value;
1232 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1233 unsigned int val = snd_soc_read(codec, mc->reg);
1235 ucontrol->value.integer.value[0] = RT3261_VOL_RSCL_MAX -
1236 ((val & RT3261_L_VOL_MASK) >> mc->shift);
1237 ucontrol->value.integer.value[1] = RT3261_VOL_RSCL_MAX -
1238 (val & RT3261_R_VOL_MASK);
1243 static int rt3261_vol_rescale_put(struct snd_kcontrol *kcontrol,
1244 struct snd_ctl_elem_value *ucontrol)
1246 struct soc_mixer_control *mc =
1247 (struct soc_mixer_control *)kcontrol->private_value;
1248 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1249 unsigned int val, val2;
1251 val = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[0];
1252 val2 = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[1];
1253 return snd_soc_update_bits_locked(codec, mc->reg, RT3261_L_VOL_MASK |
1254 RT3261_R_VOL_MASK, val << mc->shift | val2);
1258 static const struct snd_kcontrol_new rt3261_snd_controls[] = {
1259 /* Speaker Output Volume */
1260 SOC_DOUBLE("Speaker Playback Switch", RT3261_SPK_VOL,
1261 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1262 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT3261_SPK_VOL,
1263 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1264 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1265 SOC_DOUBLE_EXT_TLV("Earpiece Playback Volume", RT3261_SPK_VOL,
1266 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1267 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1268 /* Headphone Output Volume */
1269 SOC_DOUBLE("HP Playback Switch", RT3261_HP_VOL,
1270 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1271 SOC_DOUBLE_EXT_TLV("Headphone Playback Volume", RT3261_HP_VOL,
1272 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1273 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1274 /* OUTPUT Control */
1275 SOC_DOUBLE("OUT Playback Switch", RT3261_OUTPUT,
1276 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1277 SOC_DOUBLE("OUT Channel Switch", RT3261_OUTPUT,
1278 RT3261_VOL_L_SFT, RT3261_VOL_R_SFT, 1, 1),
1279 SOC_DOUBLE_TLV("OUT Playback Volume", RT3261_OUTPUT,
1280 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, 39, 1, out_vol_tlv),
1281 /* MONO Output Control */
1282 SOC_SINGLE("Mono Playback Switch", RT3261_MONO_OUT,
1283 RT3261_L_MUTE_SFT, 1, 1),
1284 /* DAC Digital Volume */
1285 SOC_DOUBLE("DAC2 Playback Switch", RT3261_DAC2_CTRL,
1286 RT3261_M_DAC_L2_VOL_SFT, RT3261_M_DAC_R2_VOL_SFT, 1, 1),
1287 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT3261_DAC1_DIG_VOL,
1288 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1289 175, 0, dac_vol_tlv),
1290 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT3261_DAC2_DIG_VOL,
1291 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1292 175, 0, dac_vol_tlv),
1293 /* IN1/IN2 Control */
1294 SOC_ENUM("IN1 Mode Control", rt3261_in1_mode_enum),
1295 SOC_SINGLE_TLV("IN1 Boost", RT3261_IN1_IN2,
1296 RT3261_BST_SFT1, 8, 0, bst_tlv),
1297 SOC_ENUM("IN2 Mode Control", rt3261_in2_mode_enum),
1298 SOC_SINGLE_TLV("IN2 Boost", RT3261_IN3_IN4,
1299 RT3261_BST_SFT2, 8, 0, bst_tlv),
1300 SOC_ENUM("IN3 Mode Control", rt3261_in3_mode_enum),
1301 SOC_SINGLE_TLV("IN3 Boost", RT3261_IN1_IN2,
1302 RT3261_BST_SFT2, 8, 0, bst_tlv),
1304 SOC_ENUM("LOUT Mode Control", rt3261_lout_mode_enum),
1305 /* INL/INR Volume Control */
1306 SOC_DOUBLE_TLV("IN Capture Volume", RT3261_INL_INR_VOL,
1307 RT3261_INL_VOL_SFT, RT3261_INR_VOL_SFT,
1309 /* ADC Digital Volume Control */
1310 SOC_DOUBLE("ADC Capture Switch", RT3261_ADC_DIG_VOL,
1311 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1312 SOC_DOUBLE_TLV("ADC Capture Volume", RT3261_ADC_DIG_VOL,
1313 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1314 127, 0, adc_vol_tlv),
1315 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT3261_ADC_DATA,
1316 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1317 127, 0, adc_vol_tlv),
1318 /* ADC Boost Volume Control */
1319 SOC_DOUBLE_TLV("ADC Boost Gain", RT3261_ADC_BST_VOL,
1320 RT3261_ADC_L_BST_SFT, RT3261_ADC_R_BST_SFT,
1322 /* Class D speaker gain ratio */
1323 SOC_ENUM("Class D SPK Ratio Control", rt3261_clsd_spk_ratio_enum),
1325 SOC_ENUM_EXT("DMIC Switch", rt3261_dmic_enum,
1326 rt3261_dmic_get, rt3261_dmic_put),
1328 SOC_ENUM_EXT("ASRC Switch", rt3261_asrc_enum,
1329 rt3261_asrc_get, rt3261_asrc_put),
1331 SOC_ENUM_EXT("DACR Select", rt3261_dacr_sel_enum,
1332 rt3261_dacr_sel_get, rt3261_dacr_sel_put),
1333 SOC_ENUM_EXT("RxDP Select", rt3261_rxdp_sel_enum,
1334 rt3261_rxdp_sel_get, rt3261_rxdp_sel_put),
1335 SOC_ENUM_EXT("RxDP1 Select", rt3261_rxdp1_sel_enum,
1336 rt3261_rxdp1_sel_get, rt3261_rxdp1_sel_put),
1337 #ifdef RT3261_REG_RW
1339 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1340 .name = "Register Control",
1341 .info = rt3261_regctl_info,
1342 .get = rt3261_regctl_get,
1343 .put = rt3261_regctl_put,
1347 SOC_SINGLE_TLV("Main Mic Capture Volume", RT3261_IN1_IN2,
1348 RT3261_BST_SFT1, 8, 0, bst_tlv),
1349 SOC_SINGLE_TLV("Headset Mic Capture Volume", RT3261_IN3_IN4,
1350 RT3261_BST_SFT2, 8, 0, bst_tlv),
1351 SOC_ENUM_EXT("Main Mic Capture Switch", rt3261_mic_enum,
1352 rt3261_mic1_get, rt3261_mic1_put),
1353 SOC_ENUM_EXT("Headset Mic Capture Switch", rt3261_mic_enum,
1354 rt3261_mic2_get, rt3261_mic2_put),
1357 SOC_ENUM_EXT("HP mute Switch", rt3261_hp_mute_enum,
1358 rt3261_hp_mute_get, rt3261_hp_mute_put),
1360 SOC_ENUM_EXT("Modem Input Switch", rt3261_modem_input_switch_enum,
1361 rt3261_modem_input_switch_get, rt3261_modem_input_switch_put),
1363 SOC_ENUM("ADC IF1 Data Switch", rt3261_if1_adc_enum),
1364 SOC_ENUM("DAC IF1 Data Switch", rt3261_if1_dac_enum),
1365 SOC_ENUM("ADC IF2 Data Switch", rt3261_if2_adc_enum),
1366 SOC_ENUM("DAC IF2 Data Switch", rt3261_if2_dac_enum),
1370 * set_dmic_clk - Set parameter of dmic.
1373 * @kcontrol: The kcontrol of this widget.
1376 * Choose dmic clock between 1MHz and 3MHz.
1377 * It is better for clock to approximate 3MHz.
1379 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1380 struct snd_kcontrol *kcontrol, int event)
1382 struct snd_soc_codec *codec = w->codec;
1383 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
1384 int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
1386 rate = rt3261->lrck[rt3261->aif_pu] << 8;
1388 for (i = 0; i < ARRAY_SIZE(div); i++) {
1389 bound = div[i] * 3000000;
1392 temp = bound - rate;
1399 dev_err(codec->dev, "Failed to set DMIC clock\n");
1401 snd_soc_update_bits(codec, RT3261_DMIC, RT3261_DMIC_CLK_MASK,
1402 idx << RT3261_DMIC_CLK_SFT);
1406 static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
1407 struct snd_soc_dapm_widget *sink)
1411 val = snd_soc_read(source->codec, RT3261_GLB_CLK);
1412 val &= RT3261_SCLK_SRC_MASK;
1413 if (val == RT3261_SCLK_SRC_PLL1)
1420 static const struct snd_kcontrol_new rt3261_sto_adc_l_mix[] = {
1421 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
1422 RT3261_M_ADC_L1_SFT, 1, 1),
1423 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
1424 RT3261_M_ADC_L2_SFT, 1, 1),
1427 static const struct snd_kcontrol_new rt3261_sto_adc_r_mix[] = {
1428 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
1429 RT3261_M_ADC_R1_SFT, 1, 1),
1430 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
1431 RT3261_M_ADC_R2_SFT, 1, 1),
1434 static const struct snd_kcontrol_new rt3261_mono_adc_l_mix[] = {
1435 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
1436 RT3261_M_MONO_ADC_L1_SFT, 1, 1),
1437 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
1438 RT3261_M_MONO_ADC_L2_SFT, 1, 1),
1441 static const struct snd_kcontrol_new rt3261_mono_adc_r_mix[] = {
1442 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
1443 RT3261_M_MONO_ADC_R1_SFT, 1, 1),
1444 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
1445 RT3261_M_MONO_ADC_R2_SFT, 1, 1),
1448 static const struct snd_kcontrol_new rt3261_dac_l_mix[] = {
1449 SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
1450 RT3261_M_ADCMIX_L_SFT, 1, 1),
1451 SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
1452 RT3261_M_IF1_DAC_L_SFT, 1, 1),
1455 static const struct snd_kcontrol_new rt3261_dac_r_mix[] = {
1456 SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
1457 RT3261_M_ADCMIX_R_SFT, 1, 1),
1458 SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
1459 RT3261_M_IF1_DAC_R_SFT, 1, 1),
1462 static const struct snd_kcontrol_new rt3261_sto_dac_l_mix[] = {
1463 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_STO_DAC_MIXER,
1464 RT3261_M_DAC_L1_SFT, 1, 1),
1465 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_STO_DAC_MIXER,
1466 RT3261_M_DAC_L2_SFT, 1, 1),
1467 SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
1468 RT3261_M_ANC_DAC_L_SFT, 1, 1),
1471 static const struct snd_kcontrol_new rt3261_sto_dac_r_mix[] = {
1472 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_STO_DAC_MIXER,
1473 RT3261_M_DAC_R1_SFT, 1, 1),
1474 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_STO_DAC_MIXER,
1475 RT3261_M_DAC_R2_SFT, 1, 1),
1476 SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
1477 RT3261_M_ANC_DAC_R_SFT, 1, 1),
1480 static const struct snd_kcontrol_new rt3261_mono_dac_l_mix[] = {
1481 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_MONO_DAC_MIXER,
1482 RT3261_M_DAC_L1_MONO_L_SFT, 1, 1),
1483 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
1484 RT3261_M_DAC_L2_MONO_L_SFT, 1, 1),
1485 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
1486 RT3261_M_DAC_R2_MONO_L_SFT, 1, 1),
1489 static const struct snd_kcontrol_new rt3261_mono_dac_r_mix[] = {
1490 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_MONO_DAC_MIXER,
1491 RT3261_M_DAC_R1_MONO_R_SFT, 1, 1),
1492 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
1493 RT3261_M_DAC_R2_MONO_R_SFT, 1, 1),
1494 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
1495 RT3261_M_DAC_L2_MONO_R_SFT, 1, 1),
1498 static const struct snd_kcontrol_new rt3261_dig_l_mix[] = {
1499 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_DIG_MIXER,
1500 RT3261_M_STO_L_DAC_L_SFT, 1, 1),
1501 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_DIG_MIXER,
1502 RT3261_M_DAC_L2_DAC_L_SFT, 1, 1),
1505 static const struct snd_kcontrol_new rt3261_dig_r_mix[] = {
1506 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_DIG_MIXER,
1507 RT3261_M_STO_R_DAC_R_SFT, 1, 1),
1508 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_DIG_MIXER,
1509 RT3261_M_DAC_R2_DAC_R_SFT, 1, 1),
1512 /* Analog Input Mixer */
1513 static const struct snd_kcontrol_new rt3261_rec_l_mix[] = {
1514 SOC_DAPM_SINGLE("HPOL Switch", RT3261_REC_L2_MIXER,
1515 RT3261_M_HP_L_RM_L_SFT, 1, 1),
1516 SOC_DAPM_SINGLE("INL Switch", RT3261_REC_L2_MIXER,
1517 RT3261_M_IN_L_RM_L_SFT, 1, 1),
1518 SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_L2_MIXER,
1519 RT3261_M_BST2_RM_L, 1, 1),
1520 SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_L2_MIXER,
1521 RT3261_M_BST4_RM_L_SFT, 1, 1),
1522 SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_L2_MIXER,
1523 RT3261_M_BST1_RM_L_SFT, 1, 1),
1524 SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_REC_L2_MIXER,
1525 RT3261_M_OM_L_RM_L_SFT, 1, 1),
1528 static const struct snd_kcontrol_new rt3261_rec_r_mix[] = {
1529 SOC_DAPM_SINGLE("HPOR Switch", RT3261_REC_R2_MIXER,
1530 RT3261_M_HP_R_RM_R_SFT, 1, 1),
1531 SOC_DAPM_SINGLE("INR Switch", RT3261_REC_R2_MIXER,
1532 RT3261_M_IN_R_RM_R_SFT, 1, 1),
1533 SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_R2_MIXER,
1534 RT3261_M_BST2_RM_R_SFT, 1, 1),
1535 SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_R2_MIXER,
1536 RT3261_M_BST4_RM_R_SFT, 1, 1),
1537 SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_R2_MIXER,
1538 RT3261_M_BST1_RM_R_SFT, 1, 1),
1539 SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_REC_R2_MIXER,
1540 RT3261_M_OM_R_RM_R_SFT, 1, 1),
1543 /* Analog Output Mixer */
1544 static const struct snd_kcontrol_new rt3261_spk_l_mix[] = {
1545 SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_SPK_L_MIXER,
1546 RT3261_M_RM_L_SM_L_SFT, 1, 1),
1547 SOC_DAPM_SINGLE("INL Switch", RT3261_SPK_L_MIXER,
1548 RT3261_M_IN_L_SM_L_SFT, 1, 1),
1549 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPK_L_MIXER,
1550 RT3261_M_DAC_L1_SM_L_SFT, 1, 1),
1551 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_SPK_L_MIXER,
1552 RT3261_M_DAC_L2_SM_L_SFT, 1, 1),
1553 SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_SPK_L_MIXER,
1554 RT3261_M_OM_L_SM_L_SFT, 1, 1),
1557 static const struct snd_kcontrol_new rt3261_spk_r_mix[] = {
1558 SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_SPK_R_MIXER,
1559 RT3261_M_RM_R_SM_R_SFT, 1, 1),
1560 SOC_DAPM_SINGLE("INR Switch", RT3261_SPK_R_MIXER,
1561 RT3261_M_IN_R_SM_R_SFT, 1, 1),
1562 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPK_R_MIXER,
1563 RT3261_M_DAC_R1_SM_R_SFT, 1, 1),
1564 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_SPK_R_MIXER,
1565 RT3261_M_DAC_R2_SM_R_SFT, 1, 1),
1566 SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_SPK_R_MIXER,
1567 RT3261_M_OM_R_SM_R_SFT, 1, 1),
1570 static const struct snd_kcontrol_new rt3261_out_l_mix[] = {
1571 SOC_DAPM_SINGLE("SPK MIXL Switch", RT3261_OUT_L3_MIXER,
1572 RT3261_M_SM_L_OM_L_SFT, 1, 1),
1573 SOC_DAPM_SINGLE("BST3 Switch", RT3261_OUT_L3_MIXER,
1574 RT3261_M_BST2_OM_L_SFT, 1, 1),
1575 SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_L3_MIXER,
1576 RT3261_M_BST1_OM_L_SFT, 1, 1),
1577 SOC_DAPM_SINGLE("INL Switch", RT3261_OUT_L3_MIXER,
1578 RT3261_M_IN_L_OM_L_SFT, 1, 1),
1579 SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_OUT_L3_MIXER,
1580 RT3261_M_RM_L_OM_L_SFT, 1, 1),
1581 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_L3_MIXER,
1582 RT3261_M_DAC_R2_OM_L_SFT, 1, 1),
1583 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_L3_MIXER,
1584 RT3261_M_DAC_L2_OM_L_SFT, 1, 1),
1585 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_OUT_L3_MIXER,
1586 RT3261_M_DAC_L1_OM_L_SFT, 1, 1),
1589 static const struct snd_kcontrol_new rt3261_out_r_mix[] = {
1590 SOC_DAPM_SINGLE("SPK MIXR Switch", RT3261_OUT_R3_MIXER,
1591 RT3261_M_SM_L_OM_R_SFT, 1, 1),
1592 SOC_DAPM_SINGLE("BST3 Switch", RT3261_OUT_R3_MIXER,
1593 RT3261_M_BST2_OM_R_SFT, 1, 1),
1594 SOC_DAPM_SINGLE("BST2 Switch", RT3261_OUT_R3_MIXER,
1595 RT3261_M_BST4_OM_R_SFT, 1, 1),
1596 SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_R3_MIXER,
1597 RT3261_M_BST1_OM_R_SFT, 1, 1),
1598 SOC_DAPM_SINGLE("INR Switch", RT3261_OUT_R3_MIXER,
1599 RT3261_M_IN_R_OM_R_SFT, 1, 1),
1600 SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_OUT_R3_MIXER,
1601 RT3261_M_RM_R_OM_R_SFT, 1, 1),
1602 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_R3_MIXER,
1603 RT3261_M_DAC_L2_OM_R_SFT, 1, 1),
1604 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_R3_MIXER,
1605 RT3261_M_DAC_R2_OM_R_SFT, 1, 1),
1606 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_OUT_R3_MIXER,
1607 RT3261_M_DAC_R1_OM_R_SFT, 1, 1),
1610 static const struct snd_kcontrol_new rt3261_spo_l_mix[] = {
1612 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
1613 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1614 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
1615 RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
1617 SOC_DAPM_SINGLE("DAC Switch", RT3261_DUMMY_SPKMIXER,
1618 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1620 SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_L_MIXER,
1621 RT3261_M_SV_R_SPM_L_SFT, 1, 1),
1622 SOC_DAPM_SINGLE("SPKVOL L Switch", RT3261_SPO_L_MIXER,
1623 RT3261_M_SV_L_SPM_L_SFT, 1, 1),
1624 SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_L_MIXER,
1625 RT3261_M_BST1_SPM_L_SFT, 1, 1),
1628 static const struct snd_kcontrol_new rt3261_spo_dac_mix[] = {
1629 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
1630 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1631 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
1632 RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
1636 static const struct snd_kcontrol_new rt3261_spo_r_mix[] = {
1637 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_R_MIXER,
1638 RT3261_M_DAC_R1_SPM_R_SFT, 1, 1),
1639 SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_R_MIXER,
1640 RT3261_M_SV_R_SPM_R_SFT, 1, 1),
1641 SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_R_MIXER,
1642 RT3261_M_BST1_SPM_R_SFT, 1, 1),
1645 static const struct snd_kcontrol_new rt3261_hpo_mix[] = {
1646 SOC_DAPM_SINGLE("DAC2 Switch", RT3261_HPO_MIXER,
1647 RT3261_M_DAC2_HM_SFT, 1, 1),
1648 SOC_DAPM_SINGLE("DAC1 Switch", RT3261_HPO_MIXER,
1649 RT3261_M_DAC1_HM_SFT, 1, 1),
1650 SOC_DAPM_SINGLE("HPVOL Switch", RT3261_HPO_MIXER,
1651 RT3261_M_HPVOL_HM_SFT, 1, 1),
1654 static const struct snd_kcontrol_new rt3261_lout_mix[] = {
1655 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_LOUT_MIXER,
1656 RT3261_M_DAC_L1_LM_SFT, 1, 1),
1657 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_LOUT_MIXER,
1658 RT3261_M_DAC_R1_LM_SFT, 1, 1),
1659 SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_LOUT_MIXER,
1660 RT3261_M_OV_L_LM_SFT, 1, 1),
1661 SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_LOUT_MIXER,
1662 RT3261_M_OV_R_LM_SFT, 1, 1),
1665 static const struct snd_kcontrol_new rt3261_mono_mix[] = {
1666 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_MIXER,
1667 RT3261_M_DAC_R2_MM_SFT, 1, 1),
1668 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_MIXER,
1669 RT3261_M_DAC_L2_MM_SFT, 1, 1),
1670 SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_MONO_MIXER,
1671 RT3261_M_OV_R_MM_SFT, 1, 1),
1672 SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_MONO_MIXER,
1673 RT3261_M_OV_L_MM_SFT, 1, 1),
1674 SOC_DAPM_SINGLE("BST1 Switch", RT3261_MONO_MIXER,
1675 RT3261_M_BST1_MM_SFT, 1, 1),
1679 static const char *rt3261_inl_src[] = {"IN2P", "MonoP"};
1681 static const SOC_ENUM_SINGLE_DECL(
1682 rt3261_inl_enum, RT3261_INL_INR_VOL,
1683 RT3261_INL_SEL_SFT, rt3261_inl_src);
1685 static const struct snd_kcontrol_new rt3261_inl_mux =
1686 SOC_DAPM_ENUM("INL source", rt3261_inl_enum);
1688 static const char *rt3261_inr_src[] = {"IN2N", "MonoN"};
1690 static const SOC_ENUM_SINGLE_DECL(
1691 rt3261_inr_enum, RT3261_INL_INR_VOL,
1692 RT3261_INR_SEL_SFT, rt3261_inr_src);
1694 static const struct snd_kcontrol_new rt3261_inr_mux =
1695 SOC_DAPM_ENUM("INR source", rt3261_inr_enum);
1697 /* Stereo ADC source */
1698 static const char *rt3261_stereo_adc1_src[] = {"DIG MIX", "ADC"};
1700 static const SOC_ENUM_SINGLE_DECL(
1701 rt3261_stereo_adc1_enum, RT3261_STO_ADC_MIXER,
1702 RT3261_ADC_1_SRC_SFT, rt3261_stereo_adc1_src);
1704 static const struct snd_kcontrol_new rt3261_sto_adc_l1_mux =
1705 SOC_DAPM_ENUM("Stereo ADC L1 source", rt3261_stereo_adc1_enum);
1707 static const struct snd_kcontrol_new rt3261_sto_adc_r1_mux =
1708 SOC_DAPM_ENUM("Stereo ADC R1 source", rt3261_stereo_adc1_enum);
1710 static const char *rt3261_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
1712 static const SOC_ENUM_SINGLE_DECL(
1713 rt3261_stereo_adc2_enum, RT3261_STO_ADC_MIXER,
1714 RT3261_ADC_2_SRC_SFT, rt3261_stereo_adc2_src);
1716 static const struct snd_kcontrol_new rt3261_sto_adc_l2_mux =
1717 SOC_DAPM_ENUM("Stereo ADC L2 source", rt3261_stereo_adc2_enum);
1719 static const struct snd_kcontrol_new rt3261_sto_adc_r2_mux =
1720 SOC_DAPM_ENUM("Stereo ADC R2 source", rt3261_stereo_adc2_enum);
1722 /* Mono ADC source */
1723 static const char *rt3261_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
1725 static const SOC_ENUM_SINGLE_DECL(
1726 rt3261_mono_adc_l1_enum, RT3261_MONO_ADC_MIXER,
1727 RT3261_MONO_ADC_L1_SRC_SFT, rt3261_mono_adc_l1_src);
1729 static const struct snd_kcontrol_new rt3261_mono_adc_l1_mux =
1730 SOC_DAPM_ENUM("Mono ADC1 left source", rt3261_mono_adc_l1_enum);
1732 static const char *rt3261_mono_adc_l2_src[] =
1733 {"DMIC L1", "DMIC L2", "Mono DAC MIXL"};
1735 static const SOC_ENUM_SINGLE_DECL(
1736 rt3261_mono_adc_l2_enum, RT3261_MONO_ADC_MIXER,
1737 RT3261_MONO_ADC_L2_SRC_SFT, rt3261_mono_adc_l2_src);
1739 static const struct snd_kcontrol_new rt3261_mono_adc_l2_mux =
1740 SOC_DAPM_ENUM("Mono ADC2 left source", rt3261_mono_adc_l2_enum);
1742 static const char *rt3261_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
1744 static const SOC_ENUM_SINGLE_DECL(
1745 rt3261_mono_adc_r1_enum, RT3261_MONO_ADC_MIXER,
1746 RT3261_MONO_ADC_R1_SRC_SFT, rt3261_mono_adc_r1_src);
1748 static const struct snd_kcontrol_new rt3261_mono_adc_r1_mux =
1749 SOC_DAPM_ENUM("Mono ADC1 right source", rt3261_mono_adc_r1_enum);
1751 static const char *rt3261_mono_adc_r2_src[] =
1752 {"DMIC R1", "DMIC R2", "Mono DAC MIXR"};
1754 static const SOC_ENUM_SINGLE_DECL(
1755 rt3261_mono_adc_r2_enum, RT3261_MONO_ADC_MIXER,
1756 RT3261_MONO_ADC_R2_SRC_SFT, rt3261_mono_adc_r2_src);
1758 static const struct snd_kcontrol_new rt3261_mono_adc_r2_mux =
1759 SOC_DAPM_ENUM("Mono ADC2 right source", rt3261_mono_adc_r2_enum);
1761 /* DAC2 channel source */
1762 static const char *rt3261_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
1764 static const SOC_ENUM_SINGLE_DECL(rt3261_dac_l2_enum, RT3261_DSP_PATH2,
1765 RT3261_DAC_L2_SEL_SFT, rt3261_dac_l2_src);
1767 static const struct snd_kcontrol_new rt3261_dac_l2_mux =
1768 SOC_DAPM_ENUM("DAC2 left channel source", rt3261_dac_l2_enum);
1770 static const char *rt3261_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
1772 static const SOC_ENUM_SINGLE_DECL(
1773 rt3261_dac_r2_enum, RT3261_DSP_PATH2,
1774 RT3261_DAC_R2_SEL_SFT, rt3261_dac_r2_src);
1776 static const struct snd_kcontrol_new rt3261_dac_r2_mux =
1777 SOC_DAPM_ENUM("DAC2 right channel source", rt3261_dac_r2_enum);
1779 /* Interface 2 ADC channel source */
1780 static const char *rt3261_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
1782 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_l_enum, RT3261_DSP_PATH2,
1783 RT3261_IF2_ADC_L_SEL_SFT, rt3261_if2_adc_l_src);
1785 static const struct snd_kcontrol_new rt3261_if2_adc_l_mux =
1786 SOC_DAPM_ENUM("IF2 ADC left channel source", rt3261_if2_adc_l_enum);
1788 static const char *rt3261_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
1790 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_r_enum, RT3261_DSP_PATH2,
1791 RT3261_IF2_ADC_R_SEL_SFT, rt3261_if2_adc_r_src);
1793 static const struct snd_kcontrol_new rt3261_if2_adc_r_mux =
1794 SOC_DAPM_ENUM("IF2 ADC right channel source", rt3261_if2_adc_r_enum);
1796 /* digital interface and iis interface map */
1797 static const char *rt3261_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
1798 "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
1799 "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
1801 static const SOC_ENUM_SINGLE_DECL(
1802 rt3261_dai_iis_map_enum, RT3261_I2S1_SDP,
1803 RT3261_I2S_IF_SFT, rt3261_dai_iis_map);
1805 static const struct snd_kcontrol_new rt3261_dai_mux =
1806 SOC_DAPM_ENUM("DAI select", rt3261_dai_iis_map_enum);
1809 static const char *rt3261_sdi_sel[] = {"IF1", "IF2"};
1811 static const SOC_ENUM_SINGLE_DECL(
1812 rt3261_sdi_sel_enum, RT3261_I2S2_SDP,
1813 RT3261_I2S2_SDI_SFT, rt3261_sdi_sel);
1815 static const struct snd_kcontrol_new rt3261_sdi_mux =
1816 SOC_DAPM_ENUM("SDI select", rt3261_sdi_sel_enum);
1818 static int rt3261_adc_event(struct snd_soc_dapm_widget *w,
1819 struct snd_kcontrol *kcontrol, int event)
1821 //struct snd_soc_codec *codec = w->codec;
1822 //unsigned int val, mask;
1825 case SND_SOC_DAPM_POST_PMU:
1826 //rt3261_index_update_bits(codec,
1827 // RT3261_CHOP_DAC_ADC, 0x1000, 0x1000);
1829 val = snd_soc_read(codec, RT3261_MONO_ADC_MIXER);
1830 mask = RT3261_M_MONO_ADC_L1 | RT3261_M_MONO_ADC_L2 |
1831 RT3261_M_MONO_ADC_R1 | RT3261_M_MONO_ADC_R2;
1832 if ((val & mask) ^ mask)
1833 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1834 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R, 0);
1838 case SND_SOC_DAPM_POST_PMD:
1840 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1841 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R,
1842 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R);
1844 //rt3261_index_update_bits(codec,
1845 // RT3261_CHOP_DAC_ADC, 0x1000, 0x0000);
1856 static int rt3261_mono_adcl_event(struct snd_soc_dapm_widget *w,
1857 struct snd_kcontrol *kcontrol, int event)
1859 struct snd_soc_codec *codec = w->codec;
1860 //unsigned int val, mask;
1863 case SND_SOC_DAPM_POST_PMU:
1864 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1865 RT3261_M_MAMIX_L, 0);
1867 case SND_SOC_DAPM_PRE_PMD:
1868 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1880 static int rt3261_mono_adcr_event(struct snd_soc_dapm_widget *w,
1881 struct snd_kcontrol *kcontrol, int event)
1883 struct snd_soc_codec *codec = w->codec;
1884 //unsigned int val, mask;
1887 case SND_SOC_DAPM_POST_PMU:
1888 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1889 RT3261_M_MAMIX_R, 0);
1891 case SND_SOC_DAPM_PRE_PMD:
1892 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1904 static int rt3261_spk_event(struct snd_soc_dapm_widget *w,
1905 struct snd_kcontrol *kcontrol, int event)
1907 struct snd_soc_codec *codec = w->codec;
1911 case SND_SOC_DAPM_POST_PMU:
1913 val = snd_soc_read(codec, RT3261_PWR_DIG1);
1914 if(val & (RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1)) {
1915 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1916 RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1,
1917 RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1);
1920 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1921 RT3261_PWR_CLS_D, RT3261_PWR_CLS_D);
1922 rt3261_index_update_bits(codec,
1923 RT3261_CLSD_INT_REG1, 0xf000, 0xf000);
1924 snd_soc_update_bits(codec, RT3261_SPK_VOL,
1925 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1928 case SND_SOC_DAPM_PRE_PMD:
1929 snd_soc_update_bits(codec, RT3261_SPK_VOL,
1930 RT3261_L_MUTE | RT3261_R_MUTE,
1931 RT3261_L_MUTE | RT3261_R_MUTE);
1932 rt3261_index_update_bits(codec,
1933 RT3261_CLSD_INT_REG1, 0xf000, 0x0000);
1934 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1935 RT3261_PWR_CLS_D, 0);
1946 static void rt3261_pmu_depop(struct snd_soc_codec *codec)
1949 /* depop parameters */
1950 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0200); //bard 12-6
1951 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
1952 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
1953 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1954 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1955 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
1956 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
1957 /* headphone amp power on */
1958 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1959 RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
1960 snd_soc_update_bits(codec, RT3261_PWR_VOL,
1961 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
1962 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
1963 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1964 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1965 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
1967 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1968 RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
1969 RT3261_PWR_HP_R | RT3261_PWR_HA,
1970 RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
1971 RT3261_PWR_HP_R | RT3261_PWR_HA);
1972 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
1973 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
1974 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
1975 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1976 RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
1977 RT3261_HP_CO_EN | RT3261_HP_SG_EN);
1978 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0400); //bard 12-6
1980 rt3261_hp_amp_power(codec, 1);
1982 /* headphone unmute sequence */
1983 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
1984 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
1985 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
1986 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
1987 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
1988 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
1989 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1990 RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
1991 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1992 RT3261_RSTN_MASK, RT3261_RSTN_EN);
1993 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1994 RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
1995 RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
1996 snd_soc_update_bits(codec, RT3261_HP_VOL,
1997 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1999 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2000 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
2001 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
2002 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
2005 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2006 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
2010 static void rt3261_pmd_depop(struct snd_soc_codec *codec)
2012 /* headphone mute sequence */
2013 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
2014 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
2015 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
2016 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
2017 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
2018 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
2019 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2020 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
2021 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2022 RT3261_RSTP_MASK, RT3261_RSTP_EN);
2023 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2024 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
2025 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
2026 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
2028 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2029 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
2032 snd_soc_update_bits(codec, RT3261_HP_VOL,
2033 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
2036 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
2037 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2038 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
2039 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
2040 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
2041 /* headphone amp power down */
2042 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2043 RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
2044 RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
2045 RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
2046 RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
2047 RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
2048 RT3261_HP_SG_EN | RT3261_HP_CB_PD);
2049 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2050 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
2053 rt3261_hp_amp_power(codec, 0);
2057 static void rt3261_pmu_depop(struct snd_soc_codec *codec)
2059 /* depop parameters */
2060 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0200); //bard 12-6
2061 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
2062 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
2063 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2064 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
2065 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
2066 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
2067 /* headphone amp power on */
2068 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2069 RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
2070 snd_soc_update_bits(codec, RT3261_PWR_VOL,
2071 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
2072 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
2073 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2074 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
2075 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
2077 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2078 RT3261_PWR_FV1 | RT3261_PWR_FV2 ,
2079 RT3261_PWR_FV1 | RT3261_PWR_FV2 );
2080 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
2081 /* headphone unmute sequence */
2082 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
2083 RT3261_DEPOP_MASK | RT3261_DIG_DP_MASK,
2084 RT3261_DEPOP_AUTO | RT3261_DIG_DP_EN);
2085 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
2086 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
2087 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
2088 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
2089 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
2090 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
2091 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
2092 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2093 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK,
2094 RT3261_HP_CP_PD | RT3261_HP_SG_EN);
2095 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0400); //bard 12-6
2097 snd_soc_update_bits(codec, RT3261_HP_VOL,
2098 RT3261_L_MUTE | RT3261_R_MUTE, 0);
2099 msleep(70); //bard 10-18
2101 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2102 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
2106 static void rt3261_pmd_depop(struct snd_soc_codec *codec)
2109 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2110 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
2112 snd_soc_update_bits(codec, RT3261_HP_VOL,
2113 RT3261_L_MUTE | RT3261_R_MUTE,
2114 RT3261_L_MUTE | RT3261_R_MUTE);
2116 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2117 RT3261_HP_CB_MASK, RT3261_HP_CB_PD);
2119 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
2120 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2121 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
2126 static int rt3261_hp_event(struct snd_soc_dapm_widget *w,
2127 struct snd_kcontrol *kcontrol, int event)
2129 struct snd_soc_codec *codec = w->codec;
2132 case SND_SOC_DAPM_POST_PMU:
2133 rt3261_pmu_depop(codec);
2136 case SND_SOC_DAPM_PRE_PMD:
2137 rt3261_pmd_depop(codec);
2147 static int rt3261_mono_event(struct snd_soc_dapm_widget *w,
2148 struct snd_kcontrol *kcontrol, int event)
2150 struct snd_soc_codec *codec = w->codec;
2153 case SND_SOC_DAPM_POST_PMU:
2154 snd_soc_update_bits(codec, RT3261_MONO_OUT,
2158 case SND_SOC_DAPM_PRE_PMD:
2159 snd_soc_update_bits(codec, RT3261_MONO_OUT,
2160 RT3261_L_MUTE, RT3261_L_MUTE);
2170 static int rt3261_lout_event(struct snd_soc_dapm_widget *w,
2171 struct snd_kcontrol *kcontrol, int event)
2173 struct snd_soc_codec *codec = w->codec;
2176 case SND_SOC_DAPM_POST_PMU:
2177 rt3261_hp_amp_power(codec,1);
2178 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2179 RT3261_PWR_LM, RT3261_PWR_LM); //bard 10-18
2180 snd_soc_update_bits(codec, RT3261_OUTPUT,
2181 RT3261_L_MUTE | RT3261_R_MUTE, 0);
2184 case SND_SOC_DAPM_PRE_PMD:
2185 snd_soc_update_bits(codec, RT3261_OUTPUT,
2186 RT3261_L_MUTE | RT3261_R_MUTE,
2187 RT3261_L_MUTE | RT3261_R_MUTE);
2188 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2189 RT3261_PWR_LM, 0); //bard 10-18
2190 rt3261_hp_amp_power(codec,0);
2200 static int rt3261_dac_event(struct snd_soc_dapm_widget *w,
2201 struct snd_kcontrol *kcontrol, int event)
2203 struct snd_soc_codec *codec = w->codec;
2204 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2207 case SND_SOC_DAPM_POST_PMU:
2208 if( rt3261->asrc_en == RT3261_ASRC_EN)
2209 rt3261_update_eqmode(codec, 2);//BT_VOIP
2212 case SND_SOC_DAPM_PRE_PMD:
2213 rt3261_update_eqmode(codec, 0);//NORMAL
2223 static const struct snd_soc_dapm_widget rt3261_dapm_widgets[] = {
2224 SND_SOC_DAPM_SUPPLY("PLL1", RT3261_PWR_ANLG2,
2225 RT3261_PWR_PLL_BIT, 0, NULL, 0),
2228 SND_SOC_DAPM_SUPPLY("LDO2", RT3261_PWR_ANLG1,
2229 RT3261_PWR_LDO2_BIT, 0, NULL, 0),
2231 SND_SOC_DAPM_MICBIAS("micbias1", RT3261_PWR_ANLG2,
2232 RT3261_PWR_MB1_BIT, 0),
2234 SND_SOC_DAPM_MICBIAS("micbias1", SND_SOC_NOPM,
2237 SND_SOC_DAPM_MICBIAS("micbias2", RT3261_PWR_ANLG2,
2238 RT3261_PWR_MB2_BIT, 0),
2240 SND_SOC_DAPM_INPUT("MIC1"),
2241 SND_SOC_DAPM_INPUT("MIC2"),
2242 SND_SOC_DAPM_INPUT("MIC3"),
2243 SND_SOC_DAPM_INPUT("DMIC1"),
2244 SND_SOC_DAPM_INPUT("DMIC2"),
2246 SND_SOC_DAPM_INPUT("IN1P"),
2247 SND_SOC_DAPM_INPUT("IN1N"),
2248 SND_SOC_DAPM_INPUT("IN2P"),
2249 SND_SOC_DAPM_INPUT("IN2N"),
2250 SND_SOC_DAPM_INPUT("IN3P"),
2251 SND_SOC_DAPM_INPUT("IN3N"),
2252 SND_SOC_DAPM_INPUT("DMIC L1"),
2253 SND_SOC_DAPM_INPUT("DMIC R1"),
2254 SND_SOC_DAPM_INPUT("DMIC L2"),
2255 SND_SOC_DAPM_INPUT("DMIC R2"),
2256 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2257 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2259 SND_SOC_DAPM_PGA("BST1", RT3261_PWR_ANLG2,
2260 RT3261_PWR_BST1_BIT, 0, NULL, 0),
2261 SND_SOC_DAPM_PGA("BST2", RT3261_PWR_ANLG2,
2262 RT3261_PWR_BST4_BIT, 0, NULL, 0),
2263 SND_SOC_DAPM_PGA("BST3", RT3261_PWR_ANLG2,
2264 RT3261_PWR_BST2_BIT, 0, NULL, 0),
2266 SND_SOC_DAPM_PGA("INL VOL", RT3261_PWR_VOL,
2267 RT3261_PWR_IN_L_BIT, 0, NULL, 0),
2268 SND_SOC_DAPM_PGA("INR VOL", RT3261_PWR_VOL,
2269 RT3261_PWR_IN_R_BIT, 0, NULL, 0),
2271 SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt3261_inl_mux),
2272 SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt3261_inr_mux),
2274 SND_SOC_DAPM_MIXER("RECMIXL", RT3261_PWR_MIXER, RT3261_PWR_RM_L_BIT, 0,
2275 rt3261_rec_l_mix, ARRAY_SIZE(rt3261_rec_l_mix)),
2276 SND_SOC_DAPM_MIXER("RECMIXR", RT3261_PWR_MIXER, RT3261_PWR_RM_R_BIT, 0,
2277 rt3261_rec_r_mix, ARRAY_SIZE(rt3261_rec_r_mix)),
2279 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM,
2281 SND_SOC_DAPM_ADC_E("ADC R", NULL, SND_SOC_NOPM,
2282 0, 0, rt3261_adc_event,
2283 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
2285 SND_SOC_DAPM_SUPPLY("ADC L power",RT3261_PWR_DIG1,
2286 RT3261_PWR_ADC_L_BIT, 0, NULL, 0),
2287 SND_SOC_DAPM_SUPPLY("ADC R power",RT3261_PWR_DIG1,
2288 RT3261_PWR_ADC_R_BIT, 0, NULL, 0),
2290 SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2291 &rt3261_sto_adc_l2_mux),
2292 SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2293 &rt3261_sto_adc_r2_mux),
2294 SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2295 &rt3261_sto_adc_l1_mux),
2296 SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2297 &rt3261_sto_adc_r1_mux),
2298 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2299 &rt3261_mono_adc_l2_mux),
2300 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2301 &rt3261_mono_adc_l1_mux),
2302 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2303 &rt3261_mono_adc_r1_mux),
2304 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2305 &rt3261_mono_adc_r2_mux),
2307 SND_SOC_DAPM_SUPPLY("stereo filter", RT3261_PWR_DIG2,
2308 RT3261_PWR_ADC_SF_BIT, 0, NULL, 0),
2309 SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
2310 rt3261_sto_adc_l_mix, ARRAY_SIZE(rt3261_sto_adc_l_mix)),
2311 SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
2312 rt3261_sto_adc_r_mix, ARRAY_SIZE(rt3261_sto_adc_r_mix)),
2313 SND_SOC_DAPM_SUPPLY("mono left filter", RT3261_PWR_DIG2,
2314 RT3261_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2315 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2316 rt3261_mono_adc_l_mix, ARRAY_SIZE(rt3261_mono_adc_l_mix),
2317 rt3261_mono_adcl_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), //bard 3-26
2318 SND_SOC_DAPM_SUPPLY("mono right filter", RT3261_PWR_DIG2,
2319 RT3261_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2320 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2321 rt3261_mono_adc_r_mix, ARRAY_SIZE(rt3261_mono_adc_r_mix),
2322 rt3261_mono_adcr_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), //bard 3-26
2325 SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2326 &rt3261_if2_adc_l_mux),
2327 SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2328 &rt3261_if2_adc_r_mux),
2330 /* Digital Interface */
2331 SND_SOC_DAPM_SUPPLY("I2S1", RT3261_PWR_DIG1,
2332 RT3261_PWR_I2S1_BIT, 0, NULL, 0),
2333 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2334 SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2335 SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2336 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2337 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2338 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2339 SND_SOC_DAPM_SUPPLY("I2S2", RT3261_PWR_DIG1,
2340 RT3261_PWR_I2S2_BIT, 0, NULL, 0),
2341 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2342 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2343 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2344 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2345 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2346 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2347 SND_SOC_DAPM_SUPPLY("I2S3", RT3261_PWR_DIG1,
2348 RT3261_PWR_I2S3_BIT, 0, NULL, 0),
2349 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2350 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2351 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2352 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2353 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2354 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2356 /* Digital Interface Select */
2357 SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2358 SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2359 SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2360 SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2361 SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
2363 SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2364 SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2365 SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2366 SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2367 SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
2369 SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2370 SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2372 /* Audio Interface */
2373 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2374 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2375 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2376 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2377 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2378 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2381 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2384 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
2387 /* DAC mixer before sound effect */
2389 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2390 rt3261_dac_l_mix, ARRAY_SIZE(rt3261_dac_l_mix)),
2391 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2392 rt3261_dac_r_mix, ARRAY_SIZE(rt3261_dac_r_mix)),
2394 SND_SOC_DAPM_MIXER_E("DAC MIXL", SND_SOC_NOPM, 0, 0,
2395 rt3261_dac_l_mix, ARRAY_SIZE(rt3261_dac_l_mix),
2396 rt3261_dac_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2397 SND_SOC_DAPM_MIXER_E("DAC MIXR", SND_SOC_NOPM, 0, 0,
2398 rt3261_dac_r_mix, ARRAY_SIZE(rt3261_dac_r_mix),
2399 rt3261_dac_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2402 /* DAC2 channel Mux */
2403 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
2404 &rt3261_dac_l2_mux),
2405 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
2406 &rt3261_dac_r2_mux),
2408 SND_SOC_DAPM_PGA("DAC L2 Volume", RT3261_PWR_DIG1,
2409 RT3261_PWR_DAC_L2_BIT, 0, NULL, 0),
2410 SND_SOC_DAPM_PGA("DAC R2 Volume", RT3261_PWR_DIG1,
2411 RT3261_PWR_DAC_R2_BIT, 0, NULL, 0),
2413 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM,
2415 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM,
2417 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT3261_PWR_DIG1,
2418 RT3261_PWR_DAC_L1_BIT, 0, NULL, 0),
2419 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT3261_PWR_DIG1,
2420 RT3261_PWR_DAC_R1_BIT, 0, NULL, 0),
2421 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT3261_PWR_DIG1,
2422 RT3261_PWR_DAC_L2_BIT, 0, NULL, 0),
2423 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT3261_PWR_DIG1,
2424 RT3261_PWR_DAC_R2_BIT, 0, NULL, 0),
2428 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2429 rt3261_sto_dac_l_mix, ARRAY_SIZE(rt3261_sto_dac_l_mix)),
2430 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2431 rt3261_sto_dac_r_mix, ARRAY_SIZE(rt3261_sto_dac_r_mix)),
2432 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2433 rt3261_mono_dac_l_mix, ARRAY_SIZE(rt3261_mono_dac_l_mix)),
2434 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2435 rt3261_mono_dac_r_mix, ARRAY_SIZE(rt3261_mono_dac_r_mix)),
2436 SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
2437 rt3261_dig_l_mix, ARRAY_SIZE(rt3261_dig_l_mix)),
2438 SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
2439 rt3261_dig_r_mix, ARRAY_SIZE(rt3261_dig_r_mix)),
2440 SND_SOC_DAPM_MUX("Mono dacr Mux", SND_SOC_NOPM, 0, 0,
2445 SND_SOC_DAPM_DAC("DAC L1", NULL, RT3261_PWR_DIG1,
2446 RT3261_PWR_DAC_L1_BIT, 0),
2447 SND_SOC_DAPM_DAC("DAC L2", NULL, RT3261_PWR_DIG1,
2448 RT3261_PWR_DAC_L2_BIT, 0),
2449 SND_SOC_DAPM_DAC("DAC R1", NULL, RT3261_PWR_DIG1,
2450 RT3261_PWR_DAC_R1_BIT, 0),
2451 SND_SOC_DAPM_DAC("DAC R2", NULL, RT3261_PWR_DIG1,
2452 RT3261_PWR_DAC_R2_BIT, 0),
2454 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
2455 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
2456 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
2457 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
2459 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
2461 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM,
2464 SND_SOC_DAPM_MIXER("SPK MIXL", RT3261_PWR_MIXER, RT3261_PWR_SM_L_BIT,
2465 0, rt3261_spk_l_mix, ARRAY_SIZE(rt3261_spk_l_mix)),
2466 SND_SOC_DAPM_MIXER("SPK MIXR", RT3261_PWR_MIXER, RT3261_PWR_SM_R_BIT,
2467 0, rt3261_spk_r_mix, ARRAY_SIZE(rt3261_spk_r_mix)),
2468 SND_SOC_DAPM_MIXER("OUT MIXL", RT3261_PWR_MIXER, RT3261_PWR_OM_L_BIT,
2469 0, rt3261_out_l_mix, ARRAY_SIZE(rt3261_out_l_mix)),
2470 SND_SOC_DAPM_MIXER("OUT MIXR", RT3261_PWR_MIXER, RT3261_PWR_OM_R_BIT,
2471 0, rt3261_out_r_mix, ARRAY_SIZE(rt3261_out_r_mix)),
2473 SND_SOC_DAPM_PGA("SPKVOL L", RT3261_PWR_VOL,
2474 RT3261_PWR_SV_L_BIT, 0, NULL, 0),
2475 SND_SOC_DAPM_PGA("SPKVOL R", RT3261_PWR_VOL,
2476 RT3261_PWR_SV_R_BIT, 0, NULL, 0),
2477 SND_SOC_DAPM_PGA("OUTVOL L", RT3261_PWR_VOL,
2478 RT3261_PWR_OV_L_BIT, 0, NULL, 0),
2479 SND_SOC_DAPM_PGA("OUTVOL R", RT3261_PWR_VOL,
2480 RT3261_PWR_OV_R_BIT, 0, NULL, 0),
2481 SND_SOC_DAPM_PGA("HPOVOL L", RT3261_PWR_VOL,
2482 RT3261_PWR_HV_L_BIT, 0, NULL, 0),
2483 SND_SOC_DAPM_PGA("HPOVOL R", RT3261_PWR_VOL,
2484 RT3261_PWR_HV_R_BIT, 0, NULL, 0),
2485 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM,
2487 /* SPO/HPO/LOUT/Mono Mixer */
2488 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
2489 0, rt3261_spo_l_mix, ARRAY_SIZE(rt3261_spo_l_mix)),
2490 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
2491 0, rt3261_spo_r_mix, ARRAY_SIZE(rt3261_spo_r_mix)),
2492 SND_SOC_DAPM_MIXER("DAC SPK", SND_SOC_NOPM, 0,
2493 0, rt3261_spo_dac_mix, ARRAY_SIZE(rt3261_spo_dac_mix)), //bard 8-27
2494 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
2495 rt3261_hpo_mix, ARRAY_SIZE(rt3261_hpo_mix)),
2496 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
2497 rt3261_lout_mix, ARRAY_SIZE(rt3261_lout_mix)),
2498 SND_SOC_DAPM_MIXER("Mono MIX", RT3261_PWR_ANLG1, RT3261_PWR_MM_BIT, 0,
2499 rt3261_mono_mix, ARRAY_SIZE(rt3261_mono_mix)),
2501 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0,
2502 rt3261_hp_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2503 SND_SOC_DAPM_PGA_S("SPK amp", 1, SND_SOC_NOPM, 0, 0,
2504 rt3261_spk_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2505 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
2506 rt3261_lout_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2507 SND_SOC_DAPM_PGA_S("Mono amp", 1, RT3261_PWR_ANLG1,
2508 RT3261_PWR_MA_BIT, 0, rt3261_mono_event,
2509 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2512 SND_SOC_DAPM_OUTPUT("SPOLP"),
2513 SND_SOC_DAPM_OUTPUT("SPOLN"),
2514 SND_SOC_DAPM_OUTPUT("SPORP"),
2515 SND_SOC_DAPM_OUTPUT("SPORN"),
2516 SND_SOC_DAPM_OUTPUT("HPOL"),
2517 SND_SOC_DAPM_OUTPUT("HPOR"),
2518 SND_SOC_DAPM_OUTPUT("LOUTL"),
2519 SND_SOC_DAPM_OUTPUT("LOUTR"),
2520 SND_SOC_DAPM_OUTPUT("MonoP"),
2521 SND_SOC_DAPM_OUTPUT("MonoN"),
2524 static const struct snd_soc_dapm_route rt3261_dapm_routes[] = {
2525 {"IN1P", NULL, "LDO2"},
2526 {"IN2P", NULL, "LDO2"},
2527 {"IN3P", NULL, "LDO2"},
2529 {"IN1P", NULL, "MIC1"},
2530 {"IN1N", NULL, "MIC1"},
2531 {"IN2P", NULL, "MIC2"},
2532 {"IN2N", NULL, "MIC2"},
2533 {"IN3P", NULL, "MIC3"},
2534 {"IN3N", NULL, "MIC3"},
2536 {"DMIC L1", NULL, "DMIC1"},
2537 {"DMIC R1", NULL, "DMIC1"},
2538 {"DMIC L2", NULL, "DMIC2"},
2539 {"DMIC R2", NULL, "DMIC2"},
2541 {"BST1", NULL, "IN1P"},
2542 {"BST1", NULL, "IN1N"},
2543 {"BST2", NULL, "IN2P"},
2544 {"BST2", NULL, "IN2N"},
2545 {"BST3", NULL, "IN3P"},
2546 {"BST3", NULL, "IN3N"},
2548 {"INL VOL", NULL, "IN2P"},
2549 {"INR VOL", NULL, "IN2N"},
2551 {"RECMIXL", "HPOL Switch", "HPOL"},
2552 {"RECMIXL", "INL Switch", "INL VOL"},
2553 {"RECMIXL", "BST3 Switch", "BST3"},
2554 {"RECMIXL", "BST2 Switch", "BST2"},
2555 {"RECMIXL", "BST1 Switch", "BST1"},
2556 {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
2558 {"RECMIXR", "HPOR Switch", "HPOR"},
2559 {"RECMIXR", "INR Switch", "INR VOL"},
2560 {"RECMIXR", "BST3 Switch", "BST3"},
2561 {"RECMIXR", "BST2 Switch", "BST2"},
2562 {"RECMIXR", "BST1 Switch", "BST1"},
2563 {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
2565 {"ADC L", NULL, "RECMIXL"},
2566 {"ADC L", NULL, "ADC L power"},
2567 {"ADC R", NULL, "RECMIXR"},
2568 {"ADC R", NULL, "ADC R power"},
2570 {"DMIC L1", NULL, "DMIC CLK"},
2571 {"DMIC L2", NULL, "DMIC CLK"},
2573 {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
2574 {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
2575 {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
2576 {"Stereo ADC L1 Mux", "ADC", "ADC L"},
2577 {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
2579 {"Stereo ADC R1 Mux", "ADC", "ADC R"},
2580 {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
2581 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
2582 {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
2583 {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
2585 {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
2586 {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
2587 {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
2588 {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
2589 {"Mono ADC L1 Mux", "ADCL", "ADC L"},
2591 {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
2592 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
2593 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
2594 {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
2595 {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
2597 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
2598 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
2599 {"Stereo ADC MIXL", NULL, "stereo filter"},
2600 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
2602 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
2603 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
2604 {"Stereo ADC MIXR", NULL, "stereo filter"},
2605 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
2607 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
2608 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
2609 {"Mono ADC MIXL", NULL, "mono left filter"},
2610 {"mono left filter", NULL, "PLL1", check_sysclk1_source},
2612 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
2613 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
2614 {"Mono ADC MIXR", NULL, "mono right filter"},
2615 {"mono right filter", NULL, "PLL1", check_sysclk1_source},
2617 {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
2618 {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
2620 {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
2621 {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
2622 {"IF3 ADC L", NULL, "Mono ADC MIXL"},
2623 {"IF3 ADC R", NULL, "Mono ADC MIXR"},
2624 {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
2625 {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
2627 {"IF1 ADC", NULL, "I2S1"},
2628 {"IF1 ADC", NULL, "IF1 ADC L"},
2629 {"IF1 ADC", NULL, "IF1 ADC R"},
2630 {"IF2 ADC", NULL, "I2S2"},
2631 {"IF2 ADC", NULL, "IF2 ADC L"},
2632 {"IF2 ADC", NULL, "IF2 ADC R"},
2633 {"IF3 ADC", NULL, "I2S3"},
2634 {"IF3 ADC", NULL, "IF3 ADC L"},
2635 {"IF3 ADC", NULL, "IF3 ADC R"},
2637 {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
2638 {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
2639 {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
2640 {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
2641 {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
2642 {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
2643 {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
2644 {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
2645 {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
2646 {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
2648 {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
2649 {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
2650 {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
2651 {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
2652 {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
2653 {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
2654 {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
2655 {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
2656 {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
2657 {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
2659 {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
2660 {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
2661 {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
2662 {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
2663 {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
2664 {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
2665 {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
2666 {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
2668 {"AIF1TX", NULL, "DAI1 TX Mux"},
2669 {"AIF1TX", NULL, "SDI1 TX Mux"},
2670 {"AIF2TX", NULL, "DAI2 TX Mux"},
2671 {"AIF2TX", NULL, "SDI2 TX Mux"},
2672 {"AIF3TX", NULL, "DAI3 TX Mux"},
2674 {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
2675 {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
2676 {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
2677 {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
2678 {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
2679 {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
2680 {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
2681 {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
2683 {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
2684 {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
2685 {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
2686 {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
2687 {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
2688 {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
2689 {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
2690 {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
2692 {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
2693 {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
2694 {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
2695 {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
2696 {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
2697 {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
2698 {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
2699 {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
2701 {"IF1 DAC", NULL, "I2S1"},
2702 {"IF1 DAC", NULL, "DAI1 RX Mux"},
2703 {"IF2 DAC", NULL, "I2S2"},
2704 {"IF2 DAC", NULL, "DAI2 RX Mux"},
2705 {"IF3 DAC", NULL, "I2S3"},
2706 {"IF3 DAC", NULL, "DAI3 RX Mux"},
2708 {"IF1 DAC L", NULL, "IF1 DAC"},
2709 {"IF1 DAC R", NULL, "IF1 DAC"},
2710 {"IF2 DAC L", NULL, "IF2 DAC"},
2711 {"IF2 DAC R", NULL, "IF2 DAC"},
2712 {"IF3 DAC L", NULL, "IF3 DAC"},
2713 {"IF3 DAC R", NULL, "IF3 DAC"},
2715 {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
2716 {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
2717 {"DAC MIXL", NULL, "DAC L1 Power"}, //bard 9-26
2718 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
2719 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
2720 {"DAC MIXR", NULL, "DAC R1 Power"}, //bard 9-26
2722 {"ANC", NULL, "Stereo ADC MIXL"},
2723 {"ANC", NULL, "Stereo ADC MIXR"},
2725 {"Audio DSP", NULL, "DAC MIXL"},
2726 {"Audio DSP", NULL, "DAC MIXR"},
2728 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
2729 {"DAC L2 Mux", "IF3", "IF3 DAC L"},
2730 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
2731 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
2732 {"DAC L2 Volume", NULL, "DAC L2 Power"}, //bard 9-26
2734 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
2735 {"DAC R2 Mux", "IF3", "IF3 DAC R"},
2736 {"DAC R2 Volume", NULL, "Mono dacr Mux"},
2737 {"Mono dacr Mux", "TxDC_R", "DAC R2 Mux"},
2738 {"Mono dacr Mux", "TxDP_R", "IF2 ADC R Mux"},
2739 {"DAC R2 Volume", NULL, "DAC R2 Power"}, //bsrd 9-26
2741 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
2742 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2743 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
2744 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
2745 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2746 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
2748 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
2749 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2750 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume"},
2751 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
2752 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2753 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume"},
2755 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
2756 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2757 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
2758 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2760 {"DAC L1", NULL, "Stereo DAC MIXL"},
2761 {"DAC L1", NULL, "PLL1", check_sysclk1_source},
2762 {"DAC L1", NULL, "DAC L1 Power"}, //bard 9-26
2763 {"DAC R1", NULL, "Stereo DAC MIXR"},
2764 {"DAC R1", NULL, "PLL1", check_sysclk1_source},
2765 {"DAC R1", NULL, "DAC R1 Power"}, //bard 9-26
2766 {"DAC L2", NULL, "Mono DAC MIXL"},
2767 {"DAC L2", NULL, "PLL1", check_sysclk1_source},
2768 {"DAC L2", NULL, "DAC L2 Power"}, //bard 9-26
2769 {"DAC R2", NULL, "Mono DAC MIXR"},
2770 {"DAC R2", NULL, "PLL1", check_sysclk1_source},
2771 {"DAC R2", NULL, "DAC R2 Power"}, //bard 9-26
2773 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
2774 {"SPK MIXL", "INL Switch", "INL VOL"},
2775 {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
2776 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
2777 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
2778 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
2779 {"SPK MIXR", "INR Switch", "INR VOL"},
2780 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
2781 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
2782 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
2784 {"OUT MIXL", "BST3 Switch", "BST3"},
2785 {"OUT MIXL", "BST1 Switch", "BST1"},
2786 {"OUT MIXL", "INL Switch", "INL VOL"},
2787 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
2788 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
2789 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
2790 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
2792 {"OUT MIXR", "BST3 Switch", "BST3"},
2793 {"OUT MIXR", "BST2 Switch", "BST2"},
2794 {"OUT MIXR", "BST1 Switch", "BST1"},
2795 {"OUT MIXR", "INR Switch", "INR VOL"},
2796 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
2797 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
2798 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
2799 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
2801 {"SPKVOL L", NULL, "SPK MIXL"},
2802 {"SPKVOL R", NULL, "SPK MIXR"},
2803 {"HPOVOL L", NULL, "OUT MIXL"},
2804 {"HPOVOL R", NULL, "OUT MIXR"},
2805 {"OUTVOL L", NULL, "OUT MIXL"},
2806 {"OUTVOL R", NULL, "OUT MIXR"},
2808 {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
2809 {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
2811 {"SPOL MIX", "DAC Switch", "DAC SPK"},
2812 {"DAC SPK", "DAC L1 Switch", "DAC L1"},
2813 {"DAC SPK", "DAC R1 Switch", "DAC R1"},
2815 {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
2816 {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
2817 {"SPOL MIX", "BST1 Switch", "BST1"},
2818 {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
2819 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
2820 {"SPOR MIX", "BST1 Switch", "BST1"},
2822 {"DAC 2", NULL, "DAC L2"},
2823 {"DAC 2", NULL, "DAC R2"},
2824 {"DAC 1", NULL, "DAC L1"},
2825 {"DAC 1", NULL, "DAC R1"},
2826 {"HPOVOL", NULL, "HPOVOL L"},
2827 {"HPOVOL", NULL, "HPOVOL R"},
2828 {"HPO MIX", "DAC2 Switch", "DAC 2"},
2829 {"HPO MIX", "DAC1 Switch", "DAC 1"},
2830 {"HPO MIX", "HPVOL Switch", "HPOVOL"},
2832 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
2833 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
2834 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
2835 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
2837 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
2838 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
2839 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
2840 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
2841 {"Mono MIX", "BST1 Switch", "BST1"},
2843 {"SPK amp", NULL, "SPOL MIX"},
2844 {"SPK amp", NULL, "SPOR MIX"},
2845 {"SPOLP", NULL, "SPK amp"},
2846 {"SPOLN", NULL, "SPK amp"},
2847 {"SPORP", NULL, "SPK amp"},
2848 {"SPORN", NULL, "SPK amp"},
2850 {"HP amp", NULL, "HPO MIX"},
2851 {"HPOL", NULL, "HP amp"},
2852 {"HPOR", NULL, "HP amp"},
2854 {"LOUT amp", NULL, "LOUT MIX"},
2855 {"LOUTL", NULL, "LOUT amp"},
2856 {"LOUTR", NULL, "LOUT amp"},
2858 {"Mono amp", NULL, "Mono MIX"},
2859 {"MonoP", NULL, "Mono amp"},
2860 {"MonoN", NULL, "Mono amp"},
2863 static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
2870 val = snd_soc_read(codec, RT3261_I2S1_SDP);
2871 val = (val & RT3261_I2S_IF_MASK) >> RT3261_I2S_IF_SFT;
2874 if (val == RT3261_IF_123 || val == RT3261_IF_132 ||
2875 val == RT3261_IF_113)
2876 ret |= RT3261_U_IF1;
2877 if (val == RT3261_IF_312 || val == RT3261_IF_213 ||
2878 val == RT3261_IF_113)
2879 ret |= RT3261_U_IF2;
2880 if (val == RT3261_IF_321 || val == RT3261_IF_231)
2881 ret |= RT3261_U_IF3;
2885 if (val == RT3261_IF_231 || val == RT3261_IF_213 ||
2886 val == RT3261_IF_223)
2887 ret |= RT3261_U_IF1;
2888 if (val == RT3261_IF_123 || val == RT3261_IF_321 ||
2889 val == RT3261_IF_223)
2890 ret |= RT3261_U_IF2;
2891 if (val == RT3261_IF_132 || val == RT3261_IF_312)
2892 ret |= RT3261_U_IF3;
2903 static int get_clk_info(int sclk, int rate)
2905 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
2906 struct snd_soc_codec *codec = rt3261_codec;
2907 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2909 if (sclk <= 0 || rate <= 0)
2912 if (rt3261->asrc_en)
2916 for (i = 0; i < ARRAY_SIZE(pd); i++)
2917 if (sclk == rate * pd[i])
2923 static int rt3261_hw_params(struct snd_pcm_substream *substream,
2924 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2926 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2927 struct snd_soc_codec *codec = rtd->codec;
2928 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2929 unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
2930 int pre_div, bclk_ms, frame_size;
2932 rt3261->lrck[dai->id] = params_rate(params);
2934 rt3261->lrck[dai->id] = 8000;
2935 pre_div = get_clk_info(rt3261->sysclk, rt3261->lrck[dai->id]);
2937 dev_err(codec->dev, "Unsupported clock setting\n");
2940 frame_size = snd_soc_params_to_frame_size(params);
2941 if (frame_size < 0) {
2942 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2945 bclk_ms = frame_size > 32 ? 1 : 0;
2946 rt3261->bclk[dai->id] = rt3261->lrck[dai->id] * (32 << bclk_ms);
2948 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2949 rt3261->bclk[dai->id], rt3261->lrck[dai->id]);
2950 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2951 bclk_ms, pre_div, dai->id);
2953 switch (params_format(params)) {
2954 case SNDRV_PCM_FORMAT_S16_LE:
2956 case SNDRV_PCM_FORMAT_S20_3LE:
2957 val_len |= RT3261_I2S_DL_20;
2959 case SNDRV_PCM_FORMAT_S24_LE:
2960 val_len |= RT3261_I2S_DL_24;
2962 case SNDRV_PCM_FORMAT_S8:
2963 val_len |= RT3261_I2S_DL_8;
2969 dai_sel = get_sdp_info(codec, dai->id);
2970 dai_sel |= (RT3261_U_IF1 | RT3261_U_IF2);
2972 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
2975 if (dai_sel & RT3261_U_IF1) {
2976 mask_clk = RT3261_I2S_BCLK_MS1_MASK | RT3261_I2S_PD1_MASK;
2977 val_clk = bclk_ms << RT3261_I2S_BCLK_MS1_SFT |
2978 pre_div << RT3261_I2S_PD1_SFT;
2979 snd_soc_update_bits(codec, RT3261_I2S1_SDP,
2980 RT3261_I2S_DL_MASK, val_len);
2981 //snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
2983 if (dai_sel & RT3261_U_IF2) {
2984 mask_clk |= RT3261_I2S_BCLK_MS2_MASK | RT3261_I2S_PD2_MASK;
2985 val_clk |= bclk_ms << RT3261_I2S_BCLK_MS2_SFT |
2986 pre_div << RT3261_I2S_PD2_SFT;
2987 snd_soc_update_bits(codec, RT3261_I2S2_SDP,
2988 RT3261_I2S_DL_MASK, val_len);
2989 //snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
2991 if (rt3261->asrc_en)
2992 snd_soc_write(codec, RT3261_ADDA_CLK1, 0x1114);
2994 snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
2999 static int rt3261_prepare(struct snd_pcm_substream *substream,
3000 struct snd_soc_dai *dai)
3002 struct snd_soc_pcm_runtime *rtd = substream->private_data;
3003 struct snd_soc_codec *codec = rtd->codec;
3004 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3006 rt3261->aif_pu = dai->id;
3010 static int rt3261_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3012 struct snd_soc_codec *codec = dai->codec;
3013 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3014 unsigned int reg_val = 0, dai_sel;
3016 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3017 case SND_SOC_DAIFMT_CBM_CFM:
3018 rt3261->master[dai->id] = 1;
3020 case SND_SOC_DAIFMT_CBS_CFS:
3021 reg_val |= RT3261_I2S_MS_S;
3022 rt3261->master[dai->id] = 0;
3028 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3029 case SND_SOC_DAIFMT_NB_NF:
3031 case SND_SOC_DAIFMT_IB_NF:
3032 reg_val |= RT3261_I2S_BP_INV;
3038 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3039 case SND_SOC_DAIFMT_I2S:
3041 case SND_SOC_DAIFMT_LEFT_J:
3042 reg_val |= RT3261_I2S_DF_LEFT;
3044 case SND_SOC_DAIFMT_DSP_A:
3045 reg_val |= RT3261_I2S_DF_PCM_A;
3047 case SND_SOC_DAIFMT_DSP_B:
3048 reg_val |= RT3261_I2S_DF_PCM_B;
3054 dai_sel = get_sdp_info(codec, dai->id);
3056 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
3059 if (dai_sel & RT3261_U_IF1) {
3060 snd_soc_update_bits(codec, RT3261_I2S1_SDP,
3061 RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
3062 RT3261_I2S_DF_MASK, reg_val);
3064 if (dai_sel & RT3261_U_IF2) {
3065 snd_soc_update_bits(codec, RT3261_I2S2_SDP,
3066 RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
3067 RT3261_I2S_DF_MASK, reg_val);
3073 static int rt3261_set_dai_sysclk(struct snd_soc_dai *dai,
3074 int clk_id, unsigned int freq, int dir)
3076 struct snd_soc_codec *codec = dai->codec;
3077 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3078 unsigned int reg_val = 0;
3080 if (freq == rt3261->sysclk && clk_id == rt3261->sysclk_src)
3084 case RT3261_SCLK_S_MCLK:
3085 reg_val |= RT3261_SCLK_SRC_MCLK;
3087 case RT3261_SCLK_S_PLL1:
3088 reg_val |= RT3261_SCLK_SRC_PLL1;
3090 case RT3261_SCLK_S_RCCLK:
3091 reg_val |= RT3261_SCLK_SRC_RCCLK;
3094 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3097 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3098 RT3261_SCLK_SRC_MASK, reg_val);
3099 rt3261->sysclk = freq;
3100 rt3261->sysclk_src = clk_id;
3102 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3108 * rt3261_pll_calc - Calcualte PLL M/N/K code.
3109 * @freq_in: external clock provided to codec.
3110 * @freq_out: target clock which codec works on.
3111 * @pll_code: Pointer to structure with M, N, K and bypass flag.
3113 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
3114 * which make calculation more efficiently.
3116 * Returns 0 for success or negative error code.
3118 static int rt3261_pll_calc(const unsigned int freq_in,
3119 const unsigned int freq_out, struct rt3261_pll_code *pll_code)
3121 int max_n = RT3261_PLL_N_MAX, max_m = RT3261_PLL_M_MAX;
3122 int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
3123 bool bypass = false;
3125 if (RT3261_PLL_INP_MAX < freq_in || RT3261_PLL_INP_MIN > freq_in)
3128 for (n_t = 0; n_t <= max_n; n_t++) {
3129 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
3132 if (in_t == freq_out) {
3137 for (m_t = 0; m_t <= max_m; m_t++) {
3138 out_t = in_t / (m_t + 2);
3139 red = abs(out_t - freq_out);
3149 pr_debug("Only get approximation about PLL\n");
3153 pll_code->m_bp = bypass;
3154 pll_code->m_code = m;
3155 pll_code->n_code = n;
3156 pll_code->k_code = 2;
3160 static int rt3261_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3161 unsigned int freq_in, unsigned int freq_out)
3163 struct snd_soc_codec *codec = dai->codec;
3164 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3165 struct rt3261_pll_code pll_code;
3168 if (source == rt3261->pll_src && freq_in == rt3261->pll_in &&
3169 freq_out == rt3261->pll_out)
3172 if (!freq_in || !freq_out) {
3173 dev_dbg(codec->dev, "PLL disabled\n");
3176 rt3261->pll_out = 0;
3177 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3178 RT3261_SCLK_SRC_MASK, RT3261_SCLK_SRC_MCLK);
3183 case RT3261_PLL1_S_MCLK:
3184 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3185 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_MCLK);
3187 case RT3261_PLL1_S_BCLK1:
3188 case RT3261_PLL1_S_BCLK2:
3189 dai_sel = get_sdp_info(codec, dai->id);
3192 "Failed to get sdp info: %d\n", dai_sel);
3195 if (dai_sel & RT3261_U_IF1) {
3196 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3197 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK1);
3199 if (dai_sel & RT3261_U_IF2) {
3200 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3201 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK2);
3203 if (dai_sel & RT3261_U_IF3) {
3204 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3205 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK3);
3209 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3213 ret = rt3261_pll_calc(freq_in, freq_out, &pll_code);
3215 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3219 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
3220 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
3222 snd_soc_write(codec, RT3261_PLL_CTRL1,
3223 pll_code.n_code << RT3261_PLL_N_SFT | pll_code.k_code);
3224 snd_soc_write(codec, RT3261_PLL_CTRL2,
3225 (pll_code.m_bp ? 0 : pll_code.m_code) << RT3261_PLL_M_SFT |
3226 pll_code.m_bp << RT3261_PLL_M_BP_SFT);
3228 rt3261->pll_in = freq_in;
3229 rt3261->pll_out = freq_out;
3230 rt3261->pll_src = source;
3236 * rt3261_index_show - Dump private registers.
3237 * @dev: codec device.
3238 * @attr: device attribute.
3239 * @buf: buffer for display.
3241 * To show non-zero values of all private registers.
3243 * Returns buffer length.
3245 static ssize_t rt3261_index_show(struct device *dev,
3246 struct device_attribute *attr, char *buf)
3248 struct i2c_client *client = to_i2c_client(dev);
3249 struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
3250 struct snd_soc_codec *codec = rt3261->codec;
3254 cnt += sprintf(buf, "RT3261 index register\n");
3255 for (i = 0; i < 0xb4; i++) {
3256 if (cnt + RT3261_REG_DISP_LEN >= PAGE_SIZE)
3258 val = rt3261_index_read(codec, i);
3261 cnt += snprintf(buf + cnt, RT3261_REG_DISP_LEN,
3262 "%02x: %04x\n", i, val);
3265 if (cnt >= PAGE_SIZE)
3266 cnt = PAGE_SIZE - 1;
3270 static DEVICE_ATTR(index_reg, 0444, rt3261_index_show, NULL);
3272 static int rt3261_set_bias_level(struct snd_soc_codec *codec,
3273 enum snd_soc_bias_level level)
3276 case SND_SOC_BIAS_ON:
3279 case SND_SOC_BIAS_PREPARE:
3280 snd_soc_update_bits(codec, RT3261_HP_VOL,
3281 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE); //bard 12-7
3282 snd_soc_update_bits(codec, RT3261_SPK_VOL,
3283 RT3261_L_MUTE | RT3261_R_MUTE,
3284 RT3261_L_MUTE | RT3261_R_MUTE);
3285 snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
3286 RT3261_PWR_MB1 | RT3261_PWR_MB2,
3287 RT3261_PWR_MB1 | RT3261_PWR_MB2);
3290 case SND_SOC_BIAS_STANDBY:
3291 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
3292 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3293 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3294 RT3261_PWR_BG | RT3261_PWR_VREF2,
3295 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3296 RT3261_PWR_BG | RT3261_PWR_VREF2);
3298 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3299 RT3261_PWR_FV1 | RT3261_PWR_FV2,
3300 RT3261_PWR_FV1 | RT3261_PWR_FV2);
3301 snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3701);
3302 snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
3303 RT3261_PWR_MB1 | RT3261_PWR_MB2,
3304 RT3261_PWR_MB1 | RT3261_PWR_MB2);
3305 codec->cache_only = false;
3306 codec->cache_sync = 1;
3307 snd_soc_cache_sync(codec);
3308 rt3261_index_sync(codec);
3312 case SND_SOC_BIAS_OFF:
3313 snd_soc_write(codec, RT3261_DEPOP_M1, 0x0004);
3314 snd_soc_write(codec, RT3261_DEPOP_M2, 0x1100);
3315 snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3700);
3316 snd_soc_write(codec, RT3261_PWR_DIG1, 0x0000);
3317 snd_soc_write(codec, RT3261_PWR_DIG2, 0x0000);
3318 snd_soc_write(codec, RT3261_PWR_VOL, 0x0000);
3319 snd_soc_write(codec, RT3261_PWR_MIXER, 0x0000);
3320 snd_soc_write(codec, RT3261_PWR_ANLG1, 0x0000);
3321 snd_soc_write(codec, RT3261_PWR_ANLG2, 0x0000);
3327 codec->dapm.bias_level = level;
3332 static int rt3261_probe(struct snd_soc_codec *codec)
3334 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3337 #if defined (CONFIG_SND_SOC_RT3224)
3338 pr_info("Codec driver version %s, in fact you choose rt3224, no dsp!\n", VERSION);
3340 pr_info("Codec driver version %s, in fact you choose rt3261 with a dsp!\n", VERSION);
3343 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
3345 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
3348 codec->write = rt3261_write;
3350 #if 0//defined (CONFIG_SND_SOC_RT5623)
3351 struct clk *iis_clk;
3352 //for rt5623 MCLK use
3353 iis_clk = clk_get_sys("rk_i2s.2", "i2s");
3354 if (IS_ERR(iis_clk)) {
3355 DBG("failed to get i2s clk\n");
3356 ret = PTR_ERR(iis_clk);
3358 DBG("I2S2 got i2s clk ok!\n");
3359 clk_enable(iis_clk);
3360 clk_set_rate(iis_clk, 11289600);
3361 rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME, GPIO0D_I2S2_2CH_CLK);
3366 ret=rt3261_reset(codec);
3371 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3372 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3373 RT3261_PWR_BG | RT3261_PWR_VREF2,
3374 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3375 RT3261_PWR_BG | RT3261_PWR_VREF2);
3377 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3378 RT3261_PWR_FV1 | RT3261_PWR_FV2,
3379 RT3261_PWR_FV1 | RT3261_PWR_FV2);
3381 if (rt3261->dmic_en == RT3261_DMIC1) {
3382 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
3383 RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
3384 snd_soc_update_bits(codec, RT3261_DMIC,
3385 RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK,
3386 RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING);
3387 } else if (rt3261->dmic_en == RT3261_DMIC2) {
3388 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
3389 RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
3390 snd_soc_update_bits(codec, RT3261_DMIC,
3391 RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK,
3392 RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING);
3394 snd_soc_write(codec, RT3261_GEN_CTRL2, 0x4040);
3395 ret = snd_soc_read(codec, RT3261_VENDOR_ID);
3396 printk("read codec chip id is 0x%x\n",ret);
3398 snd_soc_update_bits(codec, RT3261_JD_CTRL,
3399 RT3261_JD1_IN4P_MASK | RT3261_JD2_IN4N_MASK,
3400 RT3261_JD1_IN4P_EN | RT3261_JD2_IN4N_EN);
3404 printk("you use an old chip, please use a new one\n");
3406 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3407 RT3261_PWR_HP_L | RT3261_PWR_HP_R,
3409 rt3261_reg_init(codec);
3410 rt3261_customer_redefine(codec, rt3261);
3412 codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
3413 rt3261->codec = codec;
3415 snd_soc_add_codec_controls(codec, rt3261_snd_controls,
3416 ARRAY_SIZE(rt3261_snd_controls));
3417 snd_soc_dapm_new_controls(&codec->dapm, rt3261_dapm_widgets,
3418 ARRAY_SIZE(rt3261_dapm_widgets));
3419 snd_soc_dapm_add_routes(&codec->dapm, rt3261_dapm_routes,
3420 ARRAY_SIZE(rt3261_dapm_routes));
3423 #if defined (CONFIG_SND_SOC_RT3261)
3424 rt3261->dsp_sw = RT3261_DSP_AEC_NS_FENS;
3425 rt3261_dsp_probe(codec);
3429 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
3430 struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
3431 ioctl_ops->index_write = rt3261_index_write;
3432 ioctl_ops->index_read = rt3261_index_read;
3433 ioctl_ops->index_update_bits = rt3261_index_update_bits;
3434 ioctl_ops->ioctl_common = rt3261_ioctl_common;
3435 realtek_ce_init_hwdep(codec);
3440 ret = device_create_file(codec->dev, &dev_attr_index_reg);
3443 "Failed to create index_reg sysfs files: %d\n", ret);
3446 rt3261_codec = codec;
3450 static int rt3261_remove(struct snd_soc_codec *codec)
3452 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3457 static int rt3261_suspend(struct snd_soc_codec *codec)
3459 #if defined (CONFIG_SND_SOC_RT3261)
3460 /* After opening LDO of DSP, then close LDO of codec.
3461 * (1) DSP LDO power on
3462 * (2) DSP core power off
3463 * (3) DSP IIS interface power off
3464 * (4) Toggle pin of codec LDO1 to power off
3466 rt3261_dsp_suspend(codec);
3468 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3472 static int rt3261_resume(struct snd_soc_codec *codec)
3474 rt3261_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3475 #if defined (CONFIG_SND_SOC_RT3261)
3476 /* After opening LDO of codec, then close LDO of DSP. */
3477 rt3261_dsp_resume(codec);
3482 #define rt3261_suspend NULL
3483 #define rt3261_resume NULL
3486 #define RT3261_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3487 #define RT3261_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3488 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3490 struct snd_soc_dai_ops rt3261_aif_dai_ops = {
3491 .hw_params = rt3261_hw_params,
3492 .prepare = rt3261_prepare,
3493 .set_fmt = rt3261_set_dai_fmt,
3494 .set_sysclk = rt3261_set_dai_sysclk,
3495 .set_pll = rt3261_set_dai_pll,
3498 struct snd_soc_dai_driver rt3261_dai[] = {
3500 .name = "rt3261-aif1",
3503 .stream_name = "AIF1 Playback",
3506 .rates = RT3261_STEREO_RATES,
3507 .formats = RT3261_FORMATS,
3510 .stream_name = "AIF1 Capture",
3513 .rates = RT3261_STEREO_RATES,
3514 .formats = RT3261_FORMATS,
3516 .ops = &rt3261_aif_dai_ops,
3519 .name = "rt3261-aif2",
3522 .stream_name = "AIF2 Playback",
3525 .rates = RT3261_STEREO_RATES,
3526 .formats = RT3261_FORMATS,
3529 .stream_name = "AIF2 Capture",
3532 .rates = RT3261_STEREO_RATES,
3533 .formats = RT3261_FORMATS,
3535 .ops = &rt3261_aif_dai_ops,
3539 static struct snd_soc_codec_driver soc_codec_dev_rt3261 = {
3540 .probe = rt3261_probe,
3541 .remove = rt3261_remove,
3542 .suspend = rt3261_suspend,
3543 .resume = rt3261_resume,
3544 .write = rt3261_write,
3545 .set_bias_level = rt3261_set_bias_level,
3546 .reg_cache_size = RT3261_VENDOR_ID2 + 1,
3547 .reg_word_size = sizeof(u16),
3548 .reg_cache_default = rt3261_reg,
3549 .volatile_register = rt3261_volatile_register,
3550 .readable_register = rt3261_readable_register,
3551 .reg_cache_step = 1,
3554 static const struct i2c_device_id rt3261_i2c_id[] = {
3558 MODULE_DEVICE_TABLE(i2c, rt3261_i2c_id);
3564 compatible = "rt3261";
3566 codec-en-gpio = <&gpio3 GPIO_D7 GPIO_ACTIVE_HIGH>;
3568 modem-input-mode = <1>;
3569 lout-to-modem_mode = <1>;
3571 playback-if1-data_control = <0>;
3572 playback-if2-data_control = <0>;
3576 static int rt3261_parse_dt_property(struct device *dev,
3577 struct rt3261_priv *rt3261)
3579 struct device_node *node = dev->of_node;
3581 enum of_gpio_flags flags;
3583 DBG("%s()\n", __FUNCTION__);
3588 rt3261->codec_en_gpio = of_get_named_gpio_flags(node, "codec-en-gpio", 0, &flags);
3589 if (rt3261->codec_en_gpio <= 0) {
3590 DBG("%s() Can not read property codec-en-gpio\n", __FUNCTION__);
3592 ret = devm_gpio_request(dev, rt3261->codec_en_gpio, "codec_en_gpio");
3594 printk("%s() codec_en_gpio request ERROR", __FUNCTION__);
3597 ret = gpio_direction_output(rt3261->codec_en_gpio , !flags);
3599 printk("%s() codec_en_gpio set ERROR", __FUNCTION__);
3604 ret = of_property_read_u32(node, "spk-num", &rt3261->spk_num);
3606 DBG("%s() Can not read property spk-num\n", __FUNCTION__);
3607 rt3261->spk_num = TWO_SPK;
3610 ret = of_property_read_u32(node, "modem-input-mode", &rt3261->modem_input_mode);
3612 DBG("%s() Can not read property modem-input-mode\n", __FUNCTION__);
3613 rt3261->modem_input_mode = DIFFERENTIAL;
3616 ret = of_property_read_u32(node, "lout-to-modem-mode", &rt3261->lout_to_modem_mode);
3618 DBG("%s() Can not read property lout-to-modem-mode\n", __FUNCTION__);
3619 rt3261->lout_to_modem_mode = DIFFERENTIAL;
3622 ret = of_property_read_u32(node, "spk-amplify", &rt3261->spk_amplify);
3624 DBG("%s() Can not read property spk-amplify\n", __FUNCTION__);
3625 rt3261->spk_amplify = SPK_AMPLIFY_ZERO_POINT_SIX_WATT;
3628 ret = of_property_read_u32(node, "playback-if1-data-control", &rt3261->playback_if1_data_control);
3630 DBG("%s() Can not read property playback-if1-data-control\n", __FUNCTION__);
3631 rt3261->playback_if1_data_control = LR_NORMAL;
3634 ret = of_property_read_u32(node, "playback-if2-data-control", &rt3261->playback_if2_data_control);
3636 DBG("%s() Can not read property playback-if2-data-control\n", __FUNCTION__);
3637 rt3261->playback_if1_data_control = LR_NORMAL;
3642 static int rt3261_parse_dt_property(struct device *dev,
3643 struct rt3261_priv *rt3261)
3647 #endif //#ifdef CONFIG_OF
3649 static int rt3261_i2c_probe(struct i2c_client *i2c,
3650 const struct i2c_device_id *id)
3652 struct rt3261_priv *rt3261;
3656 reg = RT3261_VENDOR_ID;
3657 ret = i2c_master_recv(i2c, ®, 1);
3659 printk("rt3261 && rt3224 probe error\n");
3663 rt3261 = devm_kzalloc(&i2c->dev,sizeof(struct rt3261_priv), GFP_KERNEL);
3668 ret = rt3261_parse_dt_property(&i2c->dev, rt3261);
3670 printk("%s() parse device tree property error %d\n", __FUNCTION__, ret);
3674 #if defined (CONFIG_SND_SOC_RT5623)
3675 rt3261->modem_is_open = 0;
3678 i2c_set_clientdata(i2c, rt3261);
3679 DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
3680 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt3261,
3681 rt3261_dai, ARRAY_SIZE(rt3261_dai));
3686 static int rt3261_i2c_remove(struct i2c_client *i2c)
3688 snd_soc_unregister_codec(&i2c->dev);
3689 kfree(i2c_get_clientdata(i2c));
3693 static void rt3261_i2c_shutdown(struct i2c_client *client)
3695 struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
3696 struct snd_soc_codec *codec = rt3261->codec;
3699 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3702 struct i2c_driver rt3261_i2c_driver = {
3705 .owner = THIS_MODULE,
3707 .probe = rt3261_i2c_probe,
3708 .remove = rt3261_i2c_remove,
3709 .shutdown = rt3261_i2c_shutdown,
3710 .id_table = rt3261_i2c_id,
3713 static int __init rt3261_modinit(void)
3715 return i2c_add_driver(&rt3261_i2c_driver);
3717 module_init(rt3261_modinit);
3719 static void __exit rt3261_modexit(void)
3721 i2c_del_driver(&rt3261_i2c_driver);
3723 module_exit(rt3261_modexit);
3725 MODULE_DESCRIPTION("ASoC RT3261 driver");
3726 MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
3727 MODULE_LICENSE("GPL");