2 * rt3261.c -- RT3261 ALSA SoC audio codec driver
4 * Copyright 2011 Realtek Semiconductor Corp.
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/soc-dapm.h>
25 #include <sound/initval.h>
26 #include <sound/tlv.h>
27 #include <mach/board.h>
28 #include <linux/clk.h>
29 #include <mach/iomux.h>
33 #include <linux/proc_fs.h>
34 #include <linux/seq_file.h>
35 #include <linux/vmalloc.h>
39 #define DIFFERENTIAL 1
44 static struct snd_soc_codec *rt3261_codec;
47 #define DBG(x...) printk(KERN_DEBUG x)
54 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
55 #include "rt_codec_ioctl.h"
56 #include "rt3261_ioctl.h"
61 #if defined (CONFIG_SND_SOC_RT3261)
62 #include "rt3261-dsp.h"
65 #define RT3261_REG_RW 1 /* for debug */
66 #define RT3261_DET_EXT_MIC 0
68 #define VERSION "RT3261_V1.3.0"
70 #if defined (CONFIG_SND_SOC_RT5623)
71 extern void rt5623_on(void);
72 extern void rt5623_off(void);
75 struct rt3261_init_reg {
80 static struct rt3261_init_reg init_list[] = {
81 {RT3261_GEN_CTRL1 , 0x3701},//fa[12:13] = 1'b; fa[8~10]=1; fa[0]=1
82 {RT3261_ADDA_CLK1 , 0x1114},//73[2] = 1'b
83 {RT3261_MICBIAS , 0x3030},//93[5:4] = 11'b
84 {RT3261_CLS_D_OUT , 0xa000},//8d[11] = 0'b
85 {RT3261_CLS_D_OVCD , 0x0334},//8c[8] = 1'b
86 {RT3261_PRIV_INDEX , 0x001d},//PR1d[8] = 1'b;
87 {RT3261_PRIV_DATA , 0x0347},
88 {RT3261_PRIV_INDEX , 0x003d},//PR3d[12] = 0'b; PR3d[9] = 1'b
89 {RT3261_PRIV_DATA , 0x3600},
90 {RT3261_PRIV_INDEX , 0x0012},//PR12 = 0aa8'h
91 {RT3261_PRIV_DATA , 0x0aa8},
92 {RT3261_PRIV_INDEX , 0x0014},//PR14 = 8aaa'h
93 {RT3261_PRIV_DATA , 0x8aaa},
94 {RT3261_PRIV_INDEX , 0x0020},//PR20 = 6115'h
95 {RT3261_PRIV_DATA , 0x6115},
96 {RT3261_PRIV_INDEX , 0x0023},//PR23 = 0804'h
97 {RT3261_PRIV_DATA , 0x0804},
98 {RT3261_SPK_VOL , 0x8888},//SPKMIX -> SPKVOL
99 {RT3261_HP_VOL , 0x8888},
100 {RT3261_OUTPUT , 0x8888},//unmute OUTVOLL/R
101 {RT3261_SPO_CLSD_RATIO , 0x0001},
102 {RT3261_I2S1_SDP , 0xd000},
103 // huangcun 20130816 s
106 {RT3261_DSP_PATH2 , 0x0000},
107 {RT3261_PRIV_INDEX , 0x003f},//PR3d[14] = 0'b;
108 {RT3261_PRIV_DATA , 0x0000},
109 {RT3261_DAC2_CTRL , 0x0000},
110 {RT3261_MONO_DAC_MIXER, 0x4444},
111 {RT3261_SPK_L_MIXER, 0x003a},
112 {RT3261_SPK_R_MIXER, 0x003a},
113 {RT3261_SPO_L_MIXER, 0xc800},
115 {RT3261_OUT_L3_MIXER, 0x01fd},
116 {RT3261_OUT_R3_MIXER, 0x01fd},
117 {RT3261_HPO_MIXER, 0xc000},
121 {RT3261_IN1_IN2, 0x2080},//boost1 = 24db
122 {RT3261_REC_R2_MIXER, 0x007d},
123 {RT3261_MONO_ADC_MIXER,0x7030},
124 //{RT3261_GEN_CTRL1 , 0x2701},//regfa[13]=0
125 {RT3261_DSP_PATH2 , 0x0400},
126 {RT3261_DIG_INF_DATA, 0x0300},//right copy to left
130 {RT3261_DSP_PATH2 , 0x0000},
131 {RT3261_PRIV_INDEX , 0x003f},//PR3d[14] = 0'b;
132 {RT3261_PRIV_DATA , 0x0000},
133 {RT3261_DAC2_CTRL , 0x0000},
134 {RT3261_MONO_DAC_MIXER, 0x4444},
135 {RT3261_OUT_L3_MIXER, 0x01fd},
136 {RT3261_OUT_R3_MIXER, 0x01fd},
137 {RT3261_LOUT_MIXER, 0xc000},
139 // huangcun 20130816 e
141 #define RT3261_INIT_REG_LEN ARRAY_SIZE(init_list)
143 static int rt3261_reg_init(struct snd_soc_codec *codec)
147 for (i = 0; i < RT3261_INIT_REG_LEN; i++)
148 snd_soc_write(codec, init_list[i].reg, init_list[i].val);
153 static int rt3261_customer_redefine(struct snd_soc_codec *codec, struct rt3261_priv *rt3261)
155 if(rt3261->spk_num==TWO_SPK)
157 snd_soc_update_bits(codec, RT3261_SPO_L_MIXER,
158 RT3261_M_SV_R_SPM_L | RT3261_M_SV_L_SPM_L,
159 1 << RT3261_M_SV_R_SPM_L_SFT | 0 << RT3261_M_SV_L_SPM_L_SFT);
160 snd_soc_update_bits(codec, RT3261_SPO_R_MIXER,
161 RT3261_M_SV_R_SPM_R, 0 << RT3261_M_SV_R_SPM_R_SFT);
165 snd_soc_update_bits(codec, RT3261_SPO_L_MIXER,
166 RT3261_M_SV_R_SPM_L | RT3261_M_SV_L_SPM_L,
167 0 << RT3261_M_SV_R_SPM_L_SFT | 0 << RT3261_M_SV_L_SPM_L_SFT);
168 snd_soc_update_bits(codec, RT3261_SPO_R_MIXER,
169 RT3261_M_SV_R_SPM_R, 1 << RT3261_M_SV_R_SPM_R_SFT);
173 snd_soc_update_bits(codec, RT3261_IN3_IN4,
174 RT3261_IN_DF2, rt3261->modem_input_mode << RT3261_IN_SFT2);
175 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
176 RT3261_LOUT_DF_MASK, rt3261->lout_to_modem_mode << RT3261_LOUT_DF);
177 snd_soc_update_bits(codec, RT3261_SPO_CLSD_RATIO,
178 RT3261_SPO_CLSD_RATIO_MASK, rt3261->spk_amplify);
179 snd_soc_update_bits(codec, RT3261_DIG_INF_DATA,
180 RT3261_IF1_DAC_SEL_MASK | RT3261_IF2_DAC_SEL_MASK,
181 (rt3261->playback_if1_data_control<<RT3261_IF1_DAC_SEL_SFT) | (rt3261->playback_if2_data_control<<RT3261_IF2_DAC_SEL_SFT));
187 static int rt3261_index_sync(struct snd_soc_codec *codec)
191 for (i = 0; i < RT3261_INIT_REG_LEN; i++)
192 if (RT3261_PRIV_INDEX == init_list[i].reg ||
193 RT3261_PRIV_DATA == init_list[i].reg)
194 snd_soc_write(codec, init_list[i].reg,
199 static const u16 rt3261_reg[RT3261_VENDOR_ID2 + 1] = {
200 [RT3261_RESET] = 0x000c,
201 [RT3261_SPK_VOL] = 0xc8c8,
202 [RT3261_HP_VOL] = 0xc8c8,
203 [RT3261_OUTPUT] = 0xc8c8,
204 [RT3261_MONO_OUT] = 0x8000,
205 [RT3261_INL_INR_VOL] = 0x0808,
206 [RT3261_DAC1_DIG_VOL] = 0xafaf,
207 [RT3261_DAC2_DIG_VOL] = 0xafaf,
208 [RT3261_ADC_DIG_VOL] = 0x2f2f,
209 [RT3261_ADC_DATA] = 0x2f2f,
210 [RT3261_STO_ADC_MIXER] = 0x7060,
211 [RT3261_MONO_ADC_MIXER] = 0x7070,
212 [RT3261_AD_DA_MIXER] = 0x8080,
213 [RT3261_STO_DAC_MIXER] = 0x5454,
214 [RT3261_MONO_DAC_MIXER] = 0x5454,
215 [RT3261_DIG_MIXER] = 0xaa00,
216 [RT3261_DSP_PATH2] = 0xa000,
217 [RT3261_REC_L2_MIXER] = 0x007f,
218 [RT3261_REC_R2_MIXER] = 0x007f,
219 [RT3261_HPO_MIXER] = 0xe000,
220 [RT3261_SPK_L_MIXER] = 0x003e,
221 [RT3261_SPK_R_MIXER] = 0x003e,
222 [RT3261_SPO_L_MIXER] = 0xf800,
223 [RT3261_SPO_R_MIXER] = 0x3800,
224 [RT3261_SPO_CLSD_RATIO] = 0x0004,
225 [RT3261_MONO_MIXER] = 0xfc00,
226 [RT3261_OUT_L3_MIXER] = 0x01ff,
227 [RT3261_OUT_R3_MIXER] = 0x01ff,
228 [RT3261_LOUT_MIXER] = 0xf000,
229 [RT3261_PWR_ANLG1] = 0x00c0,
230 [RT3261_I2S1_SDP] = 0x8000,
231 [RT3261_I2S2_SDP] = 0x8000,
232 [RT3261_I2S3_SDP] = 0x8000,
233 [RT3261_ADDA_CLK1] = 0x1110,
234 [RT3261_ADDA_CLK2] = 0x0c00,
235 [RT3261_DMIC] = 0x1d00,
236 [RT3261_ASRC_3] = 0x0008,
237 [RT3261_HP_OVCD] = 0x0600,
238 [RT3261_CLS_D_OVCD] = 0x0228,
239 [RT3261_CLS_D_OUT] = 0xa800,
240 [RT3261_DEPOP_M1] = 0x0004,
241 [RT3261_DEPOP_M2] = 0x1100,
242 [RT3261_DEPOP_M3] = 0x0646,
243 [RT3261_CHARGE_PUMP] = 0x0c00,
244 [RT3261_MICBIAS] = 0x3000,
245 [RT3261_EQ_CTRL1] = 0x2080,
246 [RT3261_DRC_AGC_1] = 0x2206,
247 [RT3261_DRC_AGC_2] = 0x1f00,
248 [RT3261_ANC_CTRL1] = 0x034b,
249 [RT3261_ANC_CTRL2] = 0x0066,
250 [RT3261_ANC_CTRL3] = 0x000b,
251 [RT3261_GPIO_CTRL1] = 0x0400,
252 [RT3261_DSP_CTRL3] = 0x2000,
253 [RT3261_BASE_BACK] = 0x0013,
254 [RT3261_MP3_PLUS1] = 0x0680,
255 [RT3261_MP3_PLUS2] = 0x1c17,
256 [RT3261_3D_HP] = 0x8c00,
257 [RT3261_ADJ_HPF] = 0x2a20,
258 [RT3261_HP_CALIB_AMP_DET] = 0x0400,
259 [RT3261_SV_ZCD1] = 0x0809,
260 [RT3261_VENDOR_ID1] = 0x10ec,
261 [RT3261_VENDOR_ID2] = 0x6231,
264 static int rt3261_reset(struct snd_soc_codec *codec)
266 return snd_soc_write(codec, RT3261_RESET, 0);
269 static unsigned int rt3261_read(struct snd_soc_codec *codec,
274 val = codec->hw_read(codec, reg);
278 static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
279 unsigned int value, const void *data, int len)
283 if (!snd_soc_codec_volatile_register(codec, reg) &&
284 reg < codec->driver->reg_cache_size &&
285 !codec->cache_bypass) {
286 ret = snd_soc_cache_write(codec, reg, value);
291 if (codec->cache_only) {
292 codec->cache_sync = 1;
296 ret = i2c_master_normal_send(codec->control_data, data, len,400*1000);
305 static int rt3261_write(struct snd_soc_codec *codec, unsigned int reg,
311 data[1] = (value >> 8) & 0xff;
312 data[2] = value & 0xff;
314 DBG("rt3261_write 0x%x = 0x%x\n",reg,value);
315 return do_hw_write(codec, reg, value, data, 3);
319 * rt3261_index_write - Write private register.
320 * @codec: SoC audio codec device.
321 * @reg: Private register index.
322 * @value: Private register Data.
324 * Modify private register for advanced setting. It can be written through
325 * private index (0x6a) and data (0x6c) register.
327 * Returns 0 for success or negative error code.
329 static int rt3261_index_write(struct snd_soc_codec *codec,
330 unsigned int reg, unsigned int value)
334 ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
336 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
339 ret = snd_soc_write(codec, RT3261_PRIV_DATA, value);
341 dev_err(codec->dev, "Failed to set private value: %d\n", ret);
351 * rt3261_index_read - Read private register.
352 * @codec: SoC audio codec device.
353 * @reg: Private register index.
355 * Read advanced setting from private register. It can be read through
356 * private index (0x6a) and data (0x6c) register.
358 * Returns private register value or negative error code.
360 static unsigned int rt3261_index_read(
361 struct snd_soc_codec *codec, unsigned int reg)
365 ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
367 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
370 return snd_soc_read(codec, RT3261_PRIV_DATA);
374 * rt3261_index_update_bits - update private register bits
375 * @codec: audio codec
376 * @reg: Private register index.
377 * @mask: register mask
380 * Writes new register value.
382 * Returns 1 for change, 0 for no change, or negative error code.
384 static int rt3261_index_update_bits(struct snd_soc_codec *codec,
385 unsigned int reg, unsigned int mask, unsigned int value)
387 unsigned int old, new;
390 ret = rt3261_index_read(codec, reg);
392 dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
397 new = (old & ~mask) | (value & mask);
400 ret = rt3261_index_write(codec, reg, new);
403 "Failed to write private reg: %d\n", ret);
413 static int rt3261_volatile_register(
414 struct snd_soc_codec *codec, unsigned int reg)
418 case RT3261_PRIV_DATA:
420 case RT3261_EQ_CTRL1:
421 case RT3261_DRC_AGC_1:
422 case RT3261_ANC_CTRL1:
423 case RT3261_IRQ_CTRL2:
424 case RT3261_INT_IRQ_ST:
425 case RT3261_DSP_CTRL2:
426 case RT3261_DSP_CTRL3:
427 case RT3261_PGM_REG_ARR1:
428 case RT3261_PGM_REG_ARR3:
429 case RT3261_VENDOR_ID:
430 case RT3261_VENDOR_ID1:
431 case RT3261_VENDOR_ID2:
438 static int rt3261_readable_register(
439 struct snd_soc_codec *codec, unsigned int reg)
446 case RT3261_MONO_OUT:
449 case RT3261_INL_INR_VOL:
450 case RT3261_DAC1_DIG_VOL:
451 case RT3261_DAC2_DIG_VOL:
452 case RT3261_DAC2_CTRL:
453 case RT3261_ADC_DIG_VOL:
454 case RT3261_ADC_DATA:
455 case RT3261_ADC_BST_VOL:
456 case RT3261_STO_ADC_MIXER:
457 case RT3261_MONO_ADC_MIXER:
458 case RT3261_AD_DA_MIXER:
459 case RT3261_STO_DAC_MIXER:
460 case RT3261_MONO_DAC_MIXER:
461 case RT3261_DIG_MIXER:
462 case RT3261_DSP_PATH1:
463 case RT3261_DSP_PATH2:
464 case RT3261_DIG_INF_DATA:
465 case RT3261_REC_L1_MIXER:
466 case RT3261_REC_L2_MIXER:
467 case RT3261_REC_R1_MIXER:
468 case RT3261_REC_R2_MIXER:
469 case RT3261_HPO_MIXER:
470 case RT3261_SPK_L_MIXER:
471 case RT3261_SPK_R_MIXER:
472 case RT3261_SPO_L_MIXER:
473 case RT3261_SPO_R_MIXER:
474 case RT3261_SPO_CLSD_RATIO:
475 case RT3261_MONO_MIXER:
476 case RT3261_OUT_L1_MIXER:
477 case RT3261_OUT_L2_MIXER:
478 case RT3261_OUT_L3_MIXER:
479 case RT3261_OUT_R1_MIXER:
480 case RT3261_OUT_R2_MIXER:
481 case RT3261_OUT_R3_MIXER:
482 case RT3261_LOUT_MIXER:
483 case RT3261_PWR_DIG1:
484 case RT3261_PWR_DIG2:
485 case RT3261_PWR_ANLG1:
486 case RT3261_PWR_ANLG2:
487 case RT3261_PWR_MIXER:
489 case RT3261_PRIV_INDEX:
490 case RT3261_PRIV_DATA:
491 case RT3261_I2S1_SDP:
492 case RT3261_I2S2_SDP:
493 case RT3261_I2S3_SDP:
494 case RT3261_ADDA_CLK1:
495 case RT3261_ADDA_CLK2:
498 case RT3261_PLL_CTRL1:
499 case RT3261_PLL_CTRL2:
506 case RT3261_CLS_D_OVCD:
507 case RT3261_CLS_D_OUT:
508 case RT3261_DEPOP_M1:
509 case RT3261_DEPOP_M2:
510 case RT3261_DEPOP_M3:
511 case RT3261_CHARGE_PUMP:
512 case RT3261_PV_DET_SPK_G:
514 case RT3261_EQ_CTRL1:
515 case RT3261_EQ_CTRL2:
516 case RT3261_WIND_FILTER:
517 case RT3261_DRC_AGC_1:
518 case RT3261_DRC_AGC_2:
519 case RT3261_DRC_AGC_3:
521 case RT3261_ANC_CTRL1:
522 case RT3261_ANC_CTRL2:
523 case RT3261_ANC_CTRL3:
526 case RT3261_IRQ_CTRL1:
527 case RT3261_IRQ_CTRL2:
528 case RT3261_INT_IRQ_ST:
529 case RT3261_GPIO_CTRL1:
530 case RT3261_GPIO_CTRL2:
531 case RT3261_GPIO_CTRL3:
532 case RT3261_DSP_CTRL1:
533 case RT3261_DSP_CTRL2:
534 case RT3261_DSP_CTRL3:
535 case RT3261_DSP_CTRL4:
536 case RT3261_PGM_REG_ARR1:
537 case RT3261_PGM_REG_ARR2:
538 case RT3261_PGM_REG_ARR3:
539 case RT3261_PGM_REG_ARR4:
540 case RT3261_PGM_REG_ARR5:
541 case RT3261_SCB_FUNC:
542 case RT3261_SCB_CTRL:
543 case RT3261_BASE_BACK:
544 case RT3261_MP3_PLUS1:
545 case RT3261_MP3_PLUS2:
548 case RT3261_HP_CALIB_AMP_DET:
549 case RT3261_HP_CALIB2:
552 case RT3261_GEN_CTRL1:
553 case RT3261_GEN_CTRL2:
554 case RT3261_GEN_CTRL3:
555 case RT3261_VENDOR_ID:
556 case RT3261_VENDOR_ID1:
557 case RT3261_VENDOR_ID2:
564 void codec_set_spk(bool on)
567 struct snd_soc_codec *codec = rt3261_codec;
568 DBG("%s: %d\n", __func__, on);
573 mutex_lock(&codec->mutex);
575 DBG("snd_soc_dapm_enable_pin\n");
576 snd_soc_dapm_enable_pin(&codec->dapm, "Headphone Jack");
577 snd_soc_dapm_enable_pin(&codec->dapm, "Ext Spk");
579 DBG("snd_soc_dapm_disable_pin\n");
580 snd_soc_dapm_disable_pin(&codec->dapm, "Headphone Jack");
581 snd_soc_dapm_disable_pin(&codec->dapm, "Ext Spk");
583 snd_soc_dapm_sync(&codec->dapm);
584 mutex_unlock(&codec->mutex);
590 * rt3261_headset_mic_detect - Detect headset.
591 * @codec: SoC audio codec device.
592 * @jack_insert: Jack insert or not.
594 * Detect whether is headset or not when jack inserted.
596 * Returns detect status.
598 int rt3261_headset_mic_detect(int jack_insert)
605 if(rt3261_codec == NULL){
610 if (SND_SOC_BIAS_OFF == rt3261_codec->dapm.bias_level) {
611 snd_soc_write(rt3261_codec, RT3261_PWR_ANLG1, 0x2004);
612 snd_soc_write(rt3261_codec, RT3261_MICBIAS, 0x3830);
613 snd_soc_write(rt3261_codec, RT3261_GEN_CTRL1 , 0x3701);
616 sclk_src = snd_soc_read(rt3261_codec, RT3261_GLB_CLK) &
617 RT3261_SCLK_SRC_MASK;
618 snd_soc_update_bits(rt3261_codec, RT3261_GLB_CLK,
619 RT3261_SCLK_SRC_MASK, 0x3 << RT3261_SCLK_SRC_SFT);
621 snd_soc_update_bits(rt3261_codec, RT3261_PWR_ANLG1,
622 RT3261_PWR_LDO2, RT3261_PWR_LDO2);
623 snd_soc_update_bits(rt3261_codec, RT3261_PWR_ANLG2,
624 RT3261_PWR_MB1, RT3261_PWR_MB1);
626 snd_soc_update_bits(rt3261_codec, RT3261_MICBIAS,
627 RT3261_MIC1_OVCD_MASK | RT3261_MIC1_OVTH_MASK |
628 RT3261_PWR_CLK25M_MASK | RT3261_PWR_MB_MASK,
629 RT3261_MIC1_OVCD_EN | RT3261_MIC1_OVTH_600UA |
630 RT3261_PWR_MB_PU | RT3261_PWR_CLK25M_PU);
631 snd_soc_update_bits(rt3261_codec, RT3261_GEN_CTRL1,
634 if (snd_soc_read(rt3261_codec, RT3261_IRQ_CTRL2) & 0x8)
635 jack_type = RT3261_HEADPHO_DET;
637 jack_type = RT3261_HEADSET_DET;
638 snd_soc_update_bits(rt3261_codec, RT3261_IRQ_CTRL2,
639 RT3261_MB1_OC_CLR, 0);
641 snd_soc_update_bits(rt3261_codec, RT3261_GLB_CLK,
642 RT3261_SCLK_SRC_MASK, sclk_src);
645 snd_soc_update_bits(rt3261_codec, RT3261_MICBIAS,
646 RT3261_MIC1_OVCD_MASK,
647 RT3261_MIC1_OVCD_DIS);
649 jack_type = RT3261_NO_JACK;
654 EXPORT_SYMBOL(rt3261_headset_mic_detect);
656 static const char *rt3261_dacr2_src[] = { "TxDC_R", "TxDP_R" };
658 static const SOC_ENUM_SINGLE_DECL(rt3261_dacr2_enum,RT3261_DUMMY_PR3F,
659 14, rt3261_dacr2_src);
660 static const struct snd_kcontrol_new rt3261_dacr2_mux =
661 SOC_DAPM_ENUM("Mono dacr source", rt3261_dacr2_enum);
663 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
664 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
665 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
666 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
667 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
669 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
670 static unsigned int bst_tlv[] = {
671 TLV_DB_RANGE_HEAD(7),
672 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
673 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
674 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
675 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
676 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
677 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
678 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
681 static int rt3261_dmic_get(struct snd_kcontrol *kcontrol,
682 struct snd_ctl_elem_value *ucontrol)
684 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
685 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
687 ucontrol->value.integer.value[0] = rt3261->dmic_en;
692 static int rt3261_dmic_put(struct snd_kcontrol *kcontrol,
693 struct snd_ctl_elem_value *ucontrol)
695 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
696 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
698 if (rt3261->dmic_en == ucontrol->value.integer.value[0])
701 rt3261->dmic_en = ucontrol->value.integer.value[0];
702 switch (rt3261->dmic_en) {
703 case RT3261_DMIC_DIS:
704 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
705 RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK |
707 RT3261_GP2_PIN_GPIO2 | RT3261_GP3_PIN_GPIO3 |
708 RT3261_GP4_PIN_GPIO4);
709 snd_soc_update_bits(codec, RT3261_DMIC,
710 RT3261_DMIC_1_DP_MASK | RT3261_DMIC_2_DP_MASK,
711 RT3261_DMIC_1_DP_GPIO3 | RT3261_DMIC_2_DP_GPIO4);
712 snd_soc_update_bits(codec, RT3261_DMIC,
713 RT3261_DMIC_1_EN_MASK | RT3261_DMIC_2_EN_MASK,
714 RT3261_DMIC_1_DIS | RT3261_DMIC_2_DIS);
718 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
719 RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK,
720 RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP3_PIN_DMIC1_SDA);
721 snd_soc_update_bits(codec, RT3261_DMIC,
722 RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK |
723 RT3261_DMIC_1_DP_MASK,
724 RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING |
725 RT3261_DMIC_1_DP_IN1P);
726 snd_soc_update_bits(codec, RT3261_DMIC,
727 RT3261_DMIC_1_EN_MASK, RT3261_DMIC_1_EN);
731 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
732 RT3261_GP2_PIN_MASK | RT3261_GP4_PIN_MASK,
733 RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP4_PIN_DMIC2_SDA);
734 snd_soc_update_bits(codec, RT3261_DMIC,
735 RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK |
736 RT3261_DMIC_2_DP_MASK,
737 RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING |
738 RT3261_DMIC_2_DP_IN1N);
739 snd_soc_update_bits(codec, RT3261_DMIC,
740 RT3261_DMIC_2_EN_MASK, RT3261_DMIC_2_EN);
750 static int rt3261_asrc_get(struct snd_kcontrol *kcontrol,
751 struct snd_ctl_elem_value *ucontrol)
753 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
754 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
756 printk("%s\n", __FUNCTION__);
757 ucontrol->value.integer.value[0] = rt3261->asrc_en;
762 static int rt3261_asrc_put(struct snd_kcontrol *kcontrol,
763 struct snd_ctl_elem_value *ucontrol)
765 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
766 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
768 printk("%s\n", __FUNCTION__);
769 if (rt3261->asrc_en == ucontrol->value.integer.value[0])
772 rt3261->asrc_en = ucontrol->value.integer.value[0];
773 switch (rt3261->asrc_en) {
774 case RT3261_ASRC_DIS://disable ASRC
775 printk("%s disable\n", __FUNCTION__);
776 snd_soc_write(codec, RT3261_ASRC_1, 0x0);
777 snd_soc_write(codec, RT3261_ASRC_2, 0x0);
778 snd_soc_update_bits(codec, RT3261_GEN_CTRL1, 0x70, 0x0); //bard 8-29
779 mutex_lock(&codec->mutex);
780 snd_soc_dapm_disable_pin(&codec->dapm, "DAC L2 Power"); //bard 9-4
781 snd_soc_dapm_disable_pin(&codec->dapm, "stereo filter"); //bard 9-4
782 snd_soc_dapm_sync(&codec->dapm); //bard 9-4
783 mutex_unlock(&codec->mutex);
786 case RT3261_ASRC_EN://enable ASRC
787 printk("%s enable\n", __FUNCTION__);
788 snd_soc_write(codec, RT3261_ASRC_1, 0x9800);
789 snd_soc_write(codec, RT3261_ASRC_2, 0xF800);
790 snd_soc_update_bits(codec, RT3261_GEN_CTRL1, 0x70, 0x70); //bard 8-29
791 snd_soc_write(codec, RT3261_JD_CTRL, 0x03); //bard 8-29
792 //snd_soc_update_bits(codec, RT3261_PWR_DIG1, 0x0080, 0x0080);
793 //snd_soc_update_bits(codec, RT3261_PWR_DIG2, 0x8000, 0x8000);
794 mutex_lock(&codec->mutex);
795 snd_soc_dapm_force_enable_pin(&codec->dapm, "DAC L2 Power"); //bard 9-4
796 snd_soc_dapm_force_enable_pin(&codec->dapm, "stereo filter"); //bard 9-4
797 snd_soc_dapm_sync(&codec->dapm); //bard 9-4
798 mutex_unlock(&codec->mutex);
799 snd_soc_write(codec, RT3261_ADDA_CLK1, 0x1114);
810 static int rt3261_mic1_get(struct snd_kcontrol *kcontrol,
811 struct snd_ctl_elem_value *ucontrol)
813 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
815 ucontrol->value.integer.value[0] =
816 (snd_soc_read(codec, RT3261_REC_L2_MIXER) & RT3261_M_BST1_RM_L) >> RT3261_M_BST1_RM_L_SFT;
821 static int rt3261_mic1_put(struct snd_kcontrol *kcontrol,
822 struct snd_ctl_elem_value *ucontrol)
824 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
826 if(ucontrol->value.integer.value[0]==0) {
827 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
828 RT3261_M_BST1_RM_L, 0);
829 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
830 RT3261_M_BST1_RM_R, 0);
832 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
833 RT3261_M_BST1_RM_L, RT3261_M_BST1_RM_L);
834 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
835 RT3261_M_BST1_RM_R, RT3261_M_BST1_RM_R);
841 static int rt3261_mic2_get(struct snd_kcontrol *kcontrol,
842 struct snd_ctl_elem_value *ucontrol)
844 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
846 ucontrol->value.integer.value[0] =
847 (snd_soc_read(codec, RT3261_REC_L2_MIXER) & RT3261_M_BST1_RM_L) >> RT3261_M_BST1_RM_L_SFT;
852 static int rt3261_mic2_put(struct snd_kcontrol *kcontrol,
853 struct snd_ctl_elem_value *ucontrol)
855 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
857 if(ucontrol->value.integer.value[0]==0) {
858 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
859 RT3261_M_BST4_RM_L, 0);
860 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
861 RT3261_M_BST4_RM_R, 0);
863 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
864 RT3261_M_BST4_RM_L, RT3261_M_BST4_RM_L);
865 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
866 RT3261_M_BST4_RM_R, RT3261_M_BST4_RM_R);
873 void hp_amp_power(struct snd_soc_codec *codec, int on)
875 static int hp_amp_power_count;
876 printk("hp_amp_power on=%d hp_amp_power_count=%d\n",on,hp_amp_power_count);
879 if(hp_amp_power_count <= 0) {
880 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
881 RT3261_PWR_I2S1, RT3261_PWR_I2S1);
882 /* depop parameters */
883 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0200); //bard 12-6
884 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
885 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
886 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
887 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
888 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
889 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
890 /* headphone amp power on */
891 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
892 RT3261_PWR_FV1 | RT3261_PWR_FV2 , 0);
893 snd_soc_update_bits(codec, RT3261_PWR_VOL,
894 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
895 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
896 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
897 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA , //bard 10-18
898 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA); //bard 10-18
900 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
901 RT3261_PWR_FV1 | RT3261_PWR_FV2,
902 RT3261_PWR_FV1 | RT3261_PWR_FV2);
904 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
905 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
906 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
907 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
908 RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
909 RT3261_HP_CO_EN | RT3261_HP_SG_EN);
910 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0400); //bard 12-6
912 hp_amp_power_count++;
914 hp_amp_power_count--;
915 if(hp_amp_power_count <= 0) {
916 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
917 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
918 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
919 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
920 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
921 /* headphone amp power down */
922 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
923 RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
924 RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
925 RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
926 RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
927 RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
928 RT3261_HP_SG_EN | RT3261_HP_CB_PD);
929 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
930 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA , //bard 10-18
936 static int rt3261_hp_mute_get(struct snd_kcontrol *kcontrol,
937 struct snd_ctl_elem_value *ucontrol)
939 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
941 ucontrol->value.integer.value[0] =
942 !((snd_soc_read(codec, RT3261_HP_VOL) & RT3261_L_MUTE) >> RT3261_L_MUTE_SFT);
947 static int rt3261_hp_mute_put(struct snd_kcontrol *kcontrol,
948 struct snd_ctl_elem_value *ucontrol)
950 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
952 if(ucontrol->value.integer.value[0]) {
953 /* headphone unmute sequence */
954 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
955 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
956 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
957 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
958 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
959 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
960 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
961 RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
962 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
963 RT3261_RSTN_MASK, RT3261_RSTN_EN);
964 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
965 RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
966 RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
967 snd_soc_update_bits(codec, RT3261_HP_VOL,
968 RT3261_L_MUTE | RT3261_R_MUTE, 0);
970 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
971 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
972 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
973 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
976 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
977 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
980 /* headphone mute sequence */
981 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
982 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
983 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
984 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
985 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
986 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
987 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
988 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
989 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
990 RT3261_RSTP_MASK, RT3261_RSTP_EN);
991 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
992 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
993 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
994 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
996 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
997 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
1000 snd_soc_update_bits(codec, RT3261_HP_VOL,
1001 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
1003 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1004 RT3261_HP_R_SMT_MASK | RT3261_HP_L_SMT_MASK,
1005 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
1010 #if defined (CONFIG_SND_SOC_RT5623)
1011 static int rt3261_modem_input_switch_get(struct snd_kcontrol *kcontrol,
1012 struct snd_ctl_elem_value *ucontrol)
1014 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1015 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
1017 ucontrol->value.integer.value[0] = rt3261->modem_is_open;
1021 static int rt3261_modem_input_switch_put(struct snd_kcontrol *kcontrol,
1022 struct snd_ctl_elem_value *ucontrol)
1024 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1025 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
1027 if(ucontrol->value.integer.value[0]) {
1029 rt3261->modem_is_open = 1;
1032 rt3261->modem_is_open = 0;
1038 static int rt3261_modem_input_switch_get(struct snd_kcontrol *kcontrol,
1039 struct snd_ctl_elem_value *ucontrol)
1044 static int rt3261_modem_input_switch_put(struct snd_kcontrol *kcontrol,
1045 struct snd_ctl_elem_value *ucontrol)
1051 static int rt3261_dacr_sel_get(struct snd_kcontrol *kcontrol,
1052 struct snd_ctl_elem_value *ucontrol)
1054 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1056 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x4000) >> 14;
1061 static int rt3261_dacr_sel_put(struct snd_kcontrol *kcontrol,
1062 struct snd_ctl_elem_value *ucontrol)
1064 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1066 if(ucontrol->value.integer.value[0])
1067 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x4000, 0x4000);
1069 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x4000, 0x0);
1075 static int rt3261_rxdp_sel_get(struct snd_kcontrol *kcontrol,
1076 struct snd_ctl_elem_value *ucontrol)
1078 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1080 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x0400) >> 10;
1085 static int rt3261_rxdp_sel_put(struct snd_kcontrol *kcontrol,
1086 struct snd_ctl_elem_value *ucontrol)
1088 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1090 if(ucontrol->value.integer.value[0])
1091 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0400, 0x0400);
1093 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0400, 0x0);
1099 static int rt3261_rxdp1_sel_get(struct snd_kcontrol *kcontrol,
1100 struct snd_ctl_elem_value *ucontrol)
1102 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1104 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x0200) >> 9;
1109 static int rt3261_rxdp1_sel_put(struct snd_kcontrol *kcontrol,
1110 struct snd_ctl_elem_value *ucontrol)
1112 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1114 if(ucontrol->value.integer.value[0])
1115 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0200, 0x0200);
1117 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0200, 0x0);
1123 /* IN1/IN2 Input Type */
1124 static const char *rt3261_input_mode[] = {
1125 "Single ended", "Differential"};
1127 static const SOC_ENUM_SINGLE_DECL(
1128 rt3261_in1_mode_enum, RT3261_IN1_IN2,
1129 RT3261_IN_SFT1, rt3261_input_mode);
1131 static const SOC_ENUM_SINGLE_DECL(
1132 rt3261_in2_mode_enum, RT3261_IN3_IN4,
1133 RT3261_IN_SFT2, rt3261_input_mode);
1135 static const SOC_ENUM_SINGLE_DECL(
1136 rt3261_in3_mode_enum, RT3261_IN1_IN2,
1137 RT3261_IN_SFT2, rt3261_input_mode);
1140 static const char *rt3261_output_mode[] = {
1141 "Single ended", "Differential"};
1143 static const SOC_ENUM_SINGLE_DECL(
1144 rt3261_lout_mode_enum, RT3261_GEN_CTRL1,
1145 RT3261_LOUT_DF, rt3261_output_mode);
1148 /* Interface data select */
1149 static const char *rt3261_data_select[] = {
1150 "Normal", "Swap", "left copy to right", "right copy to left"};
1152 static const SOC_ENUM_SINGLE_DECL(rt3261_if1_dac_enum, RT3261_DIG_INF_DATA,
1153 RT3261_IF1_DAC_SEL_SFT, rt3261_data_select);
1155 static const SOC_ENUM_SINGLE_DECL(rt3261_if1_adc_enum, RT3261_DIG_INF_DATA,
1156 RT3261_IF1_ADC_SEL_SFT, rt3261_data_select);
1158 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_dac_enum, RT3261_DIG_INF_DATA,
1159 RT3261_IF2_DAC_SEL_SFT, rt3261_data_select);
1161 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_enum, RT3261_DIG_INF_DATA,
1162 RT3261_IF2_ADC_SEL_SFT, rt3261_data_select);
1164 static const SOC_ENUM_SINGLE_DECL(rt3261_if3_dac_enum, RT3261_DIG_INF_DATA,
1165 RT3261_IF3_DAC_SEL_SFT, rt3261_data_select);
1167 static const SOC_ENUM_SINGLE_DECL(rt3261_if3_adc_enum, RT3261_DIG_INF_DATA,
1168 RT3261_IF3_ADC_SEL_SFT, rt3261_data_select);
1170 /* Class D speaker gain ratio */
1171 static const char *rt3261_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
1172 "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
1174 static const SOC_ENUM_SINGLE_DECL(
1175 rt3261_clsd_spk_ratio_enum, RT3261_CLS_D_OUT,
1176 RT3261_CLSD_RATIO_SFT, rt3261_clsd_spk_ratio);
1179 static const char *rt3261_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
1181 static const SOC_ENUM_SINGLE_DECL(rt3261_dmic_enum, 0, 0, rt3261_dmic_mode);
1183 static const char *rt3261_asrc_mode[] = {"Disable", "Enable"};
1185 static const SOC_ENUM_SINGLE_DECL(rt3261_asrc_enum, 0, 0, rt3261_asrc_mode);
1188 static const char *rt3261_dacr_sel_mode[] = {"IF2_DAC", "IF2_ADC"};
1190 static const SOC_ENUM_SINGLE_DECL(rt3261_dacr_sel_enum, 0, 0, rt3261_dacr_sel_mode);
1192 static const char *rt3261_rxdp_sel_mode[] = {"RxDP2", "RxDP1"};
1194 static const SOC_ENUM_SINGLE_DECL(rt3261_rxdp_sel_enum, 0, 0, rt3261_rxdp_sel_mode);
1196 static const char *rt3261_rxdp1_sel_mode[] = {"DAC1", "IF1_DAC"};
1198 static const SOC_ENUM_SINGLE_DECL(rt3261_rxdp1_sel_enum, 0, 0, rt3261_rxdp1_sel_mode);
1202 static const char *rt3261_mic_mode[] = {"off", "on",};
1203 static const SOC_ENUM_SINGLE_DECL(rt3261_mic_enum, 0, 0, rt3261_mic_mode);
1206 static const char *rt3261_hp_mute_mode[] = {"off", "on",};
1208 static const SOC_ENUM_SINGLE_DECL(rt3261_hp_mute_enum, 0, 0, rt3261_hp_mute_mode);
1210 static const char *rt3261_modem_input_switch_mode[] = {"off", "on",};
1212 static const SOC_ENUM_SINGLE_DECL(rt3261_modem_input_switch_enum, 0, 0, rt3261_modem_input_switch_mode);
1214 #ifdef RT3261_REG_RW
1215 #define REGVAL_MAX 0xffff
1216 static unsigned int regctl_addr;
1217 static int rt3261_regctl_info(struct snd_kcontrol *kcontrol,
1218 struct snd_ctl_elem_info *uinfo)
1220 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1222 uinfo->value.integer.min = 0;
1223 uinfo->value.integer.max = REGVAL_MAX;
1227 static int rt3261_regctl_get(struct snd_kcontrol *kcontrol,
1228 struct snd_ctl_elem_value *ucontrol)
1230 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1231 ucontrol->value.integer.value[0] = regctl_addr;
1232 ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
1236 static int rt3261_regctl_put(struct snd_kcontrol *kcontrol,
1237 struct snd_ctl_elem_value *ucontrol)
1239 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1240 regctl_addr = ucontrol->value.integer.value[0];
1241 if(ucontrol->value.integer.value[1] <= REGVAL_MAX)
1242 snd_soc_write(codec, regctl_addr, ucontrol->value.integer.value[1]);
1248 static int rt3261_vol_rescale_get(struct snd_kcontrol *kcontrol,
1249 struct snd_ctl_elem_value *ucontrol)
1251 struct soc_mixer_control *mc =
1252 (struct soc_mixer_control *)kcontrol->private_value;
1253 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1254 unsigned int val = snd_soc_read(codec, mc->reg);
1256 ucontrol->value.integer.value[0] = RT3261_VOL_RSCL_MAX -
1257 ((val & RT3261_L_VOL_MASK) >> mc->shift);
1258 ucontrol->value.integer.value[1] = RT3261_VOL_RSCL_MAX -
1259 (val & RT3261_R_VOL_MASK);
1264 static int rt3261_vol_rescale_put(struct snd_kcontrol *kcontrol,
1265 struct snd_ctl_elem_value *ucontrol)
1267 struct soc_mixer_control *mc =
1268 (struct soc_mixer_control *)kcontrol->private_value;
1269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1270 unsigned int val, val2;
1272 val = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[0];
1273 val2 = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[1];
1274 return snd_soc_update_bits_locked(codec, mc->reg, RT3261_L_VOL_MASK |
1275 RT3261_R_VOL_MASK, val << mc->shift | val2);
1279 static const struct snd_kcontrol_new rt3261_snd_controls[] = {
1280 /* Speaker Output Volume */
1281 SOC_DOUBLE("Speaker Playback Switch", RT3261_SPK_VOL,
1282 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1283 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT3261_SPK_VOL,
1284 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1285 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1286 SOC_DOUBLE_EXT_TLV("Earpiece Playback Volume", RT3261_SPK_VOL,
1287 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1288 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1289 /* Headphone Output Volume */
1290 SOC_DOUBLE("HP Playback Switch", RT3261_HP_VOL,
1291 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1292 SOC_DOUBLE_EXT_TLV("Headphone Playback Volume", RT3261_HP_VOL,
1293 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1294 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1295 /* OUTPUT Control */
1296 SOC_DOUBLE("OUT Playback Switch", RT3261_OUTPUT,
1297 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1298 SOC_DOUBLE("OUT Channel Switch", RT3261_OUTPUT,
1299 RT3261_VOL_L_SFT, RT3261_VOL_R_SFT, 1, 1),
1300 SOC_DOUBLE_TLV("OUT Playback Volume", RT3261_OUTPUT,
1301 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, 39, 1, out_vol_tlv),
1302 /* MONO Output Control */
1303 SOC_SINGLE("Mono Playback Switch", RT3261_MONO_OUT,
1304 RT3261_L_MUTE_SFT, 1, 1),
1305 /* DAC Digital Volume */
1306 SOC_DOUBLE("DAC2 Playback Switch", RT3261_DAC2_CTRL,
1307 RT3261_M_DAC_L2_VOL_SFT, RT3261_M_DAC_R2_VOL_SFT, 1, 1),
1308 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT3261_DAC1_DIG_VOL,
1309 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1310 175, 0, dac_vol_tlv),
1311 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT3261_DAC2_DIG_VOL,
1312 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1313 175, 0, dac_vol_tlv),
1314 /* IN1/IN2 Control */
1315 SOC_ENUM("IN1 Mode Control", rt3261_in1_mode_enum),
1316 SOC_SINGLE_TLV("IN1 Boost", RT3261_IN1_IN2,
1317 RT3261_BST_SFT1, 8, 0, bst_tlv),
1318 SOC_ENUM("IN2 Mode Control", rt3261_in2_mode_enum),
1319 SOC_SINGLE_TLV("IN2 Boost", RT3261_IN3_IN4,
1320 RT3261_BST_SFT2, 8, 0, bst_tlv),
1321 SOC_ENUM("IN3 Mode Control", rt3261_in3_mode_enum),
1322 SOC_SINGLE_TLV("IN3 Boost", RT3261_IN1_IN2,
1323 RT3261_BST_SFT2, 8, 0, bst_tlv),
1325 SOC_ENUM("LOUT Mode Control", rt3261_lout_mode_enum),
1326 /* INL/INR Volume Control */
1327 SOC_DOUBLE_TLV("IN Capture Volume", RT3261_INL_INR_VOL,
1328 RT3261_INL_VOL_SFT, RT3261_INR_VOL_SFT,
1330 /* ADC Digital Volume Control */
1331 SOC_DOUBLE("ADC Capture Switch", RT3261_ADC_DIG_VOL,
1332 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1333 SOC_DOUBLE_TLV("ADC Capture Volume", RT3261_ADC_DIG_VOL,
1334 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1335 127, 0, adc_vol_tlv),
1336 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT3261_ADC_DATA,
1337 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1338 127, 0, adc_vol_tlv),
1339 /* ADC Boost Volume Control */
1340 SOC_DOUBLE_TLV("ADC Boost Gain", RT3261_ADC_BST_VOL,
1341 RT3261_ADC_L_BST_SFT, RT3261_ADC_R_BST_SFT,
1343 /* Class D speaker gain ratio */
1344 SOC_ENUM("Class D SPK Ratio Control", rt3261_clsd_spk_ratio_enum),
1346 SOC_ENUM_EXT("DMIC Switch", rt3261_dmic_enum,
1347 rt3261_dmic_get, rt3261_dmic_put),
1349 SOC_ENUM_EXT("ASRC Switch", rt3261_asrc_enum,
1350 rt3261_asrc_get, rt3261_asrc_put),
1352 SOC_ENUM_EXT("DACR Select", rt3261_dacr_sel_enum,
1353 rt3261_dacr_sel_get, rt3261_dacr_sel_put),
1354 SOC_ENUM_EXT("RxDP Select", rt3261_rxdp_sel_enum,
1355 rt3261_rxdp_sel_get, rt3261_rxdp_sel_put),
1356 SOC_ENUM_EXT("RxDP1 Select", rt3261_rxdp1_sel_enum,
1357 rt3261_rxdp1_sel_get, rt3261_rxdp1_sel_put),
1358 #ifdef RT3261_REG_RW
1360 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1361 .name = "Register Control",
1362 .info = rt3261_regctl_info,
1363 .get = rt3261_regctl_get,
1364 .put = rt3261_regctl_put,
1368 SOC_SINGLE_TLV("Main Mic Capture Volume", RT3261_IN1_IN2,
1369 RT3261_BST_SFT1, 8, 0, bst_tlv),
1370 SOC_SINGLE_TLV("Headset Mic Capture Volume", RT3261_IN3_IN4,
1371 RT3261_BST_SFT2, 8, 0, bst_tlv),
1372 SOC_ENUM_EXT("Main Mic Capture Switch", rt3261_mic_enum,
1373 rt3261_mic1_get, rt3261_mic1_put),
1374 SOC_ENUM_EXT("Headset Mic Capture Switch", rt3261_mic_enum,
1375 rt3261_mic2_get, rt3261_mic2_put),
1378 SOC_ENUM_EXT("HP mute Switch", rt3261_hp_mute_enum,
1379 rt3261_hp_mute_get, rt3261_hp_mute_put),
1381 SOC_ENUM_EXT("Modem Input Switch", rt3261_modem_input_switch_enum,
1382 rt3261_modem_input_switch_get, rt3261_modem_input_switch_put),
1384 SOC_ENUM("ADC IF1 Data Switch", rt3261_if1_adc_enum),
1385 SOC_ENUM("DAC IF1 Data Switch", rt3261_if1_dac_enum),
1386 SOC_ENUM("ADC IF2 Data Switch", rt3261_if2_adc_enum),
1387 SOC_ENUM("DAC IF2 Data Switch", rt3261_if2_dac_enum),
1391 * set_dmic_clk - Set parameter of dmic.
1394 * @kcontrol: The kcontrol of this widget.
1397 * Choose dmic clock between 1MHz and 3MHz.
1398 * It is better for clock to approximate 3MHz.
1400 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1401 struct snd_kcontrol *kcontrol, int event)
1403 struct snd_soc_codec *codec = w->codec;
1404 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
1405 int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
1407 rate = rt3261->lrck[rt3261->aif_pu] << 8;
1409 for (i = 0; i < ARRAY_SIZE(div); i++) {
1410 bound = div[i] * 3000000;
1413 temp = bound - rate;
1420 dev_err(codec->dev, "Failed to set DMIC clock\n");
1422 snd_soc_update_bits(codec, RT3261_DMIC, RT3261_DMIC_CLK_MASK,
1423 idx << RT3261_DMIC_CLK_SFT);
1427 static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
1428 struct snd_soc_dapm_widget *sink)
1432 val = snd_soc_read(source->codec, RT3261_GLB_CLK);
1433 val &= RT3261_SCLK_SRC_MASK;
1434 if (val == RT3261_SCLK_SRC_PLL1)
1441 static const struct snd_kcontrol_new rt3261_sto_adc_l_mix[] = {
1442 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
1443 RT3261_M_ADC_L1_SFT, 1, 1),
1444 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
1445 RT3261_M_ADC_L2_SFT, 1, 1),
1448 static const struct snd_kcontrol_new rt3261_sto_adc_r_mix[] = {
1449 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
1450 RT3261_M_ADC_R1_SFT, 1, 1),
1451 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
1452 RT3261_M_ADC_R2_SFT, 1, 1),
1455 static const struct snd_kcontrol_new rt3261_mono_adc_l_mix[] = {
1456 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
1457 RT3261_M_MONO_ADC_L1_SFT, 1, 1),
1458 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
1459 RT3261_M_MONO_ADC_L2_SFT, 1, 1),
1462 static const struct snd_kcontrol_new rt3261_mono_adc_r_mix[] = {
1463 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
1464 RT3261_M_MONO_ADC_R1_SFT, 1, 1),
1465 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
1466 RT3261_M_MONO_ADC_R2_SFT, 1, 1),
1469 static const struct snd_kcontrol_new rt3261_dac_l_mix[] = {
1470 SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
1471 RT3261_M_ADCMIX_L_SFT, 1, 1),
1472 SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
1473 RT3261_M_IF1_DAC_L_SFT, 1, 1),
1476 static const struct snd_kcontrol_new rt3261_dac_r_mix[] = {
1477 SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
1478 RT3261_M_ADCMIX_R_SFT, 1, 1),
1479 SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
1480 RT3261_M_IF1_DAC_R_SFT, 1, 1),
1483 static const struct snd_kcontrol_new rt3261_sto_dac_l_mix[] = {
1484 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_STO_DAC_MIXER,
1485 RT3261_M_DAC_L1_SFT, 1, 1),
1486 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_STO_DAC_MIXER,
1487 RT3261_M_DAC_L2_SFT, 1, 1),
1488 SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
1489 RT3261_M_ANC_DAC_L_SFT, 1, 1),
1492 static const struct snd_kcontrol_new rt3261_sto_dac_r_mix[] = {
1493 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_STO_DAC_MIXER,
1494 RT3261_M_DAC_R1_SFT, 1, 1),
1495 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_STO_DAC_MIXER,
1496 RT3261_M_DAC_R2_SFT, 1, 1),
1497 SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
1498 RT3261_M_ANC_DAC_R_SFT, 1, 1),
1501 static const struct snd_kcontrol_new rt3261_mono_dac_l_mix[] = {
1502 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_MONO_DAC_MIXER,
1503 RT3261_M_DAC_L1_MONO_L_SFT, 1, 1),
1504 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
1505 RT3261_M_DAC_L2_MONO_L_SFT, 1, 1),
1506 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
1507 RT3261_M_DAC_R2_MONO_L_SFT, 1, 1),
1510 static const struct snd_kcontrol_new rt3261_mono_dac_r_mix[] = {
1511 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_MONO_DAC_MIXER,
1512 RT3261_M_DAC_R1_MONO_R_SFT, 1, 1),
1513 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
1514 RT3261_M_DAC_R2_MONO_R_SFT, 1, 1),
1515 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
1516 RT3261_M_DAC_L2_MONO_R_SFT, 1, 1),
1519 static const struct snd_kcontrol_new rt3261_dig_l_mix[] = {
1520 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_DIG_MIXER,
1521 RT3261_M_STO_L_DAC_L_SFT, 1, 1),
1522 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_DIG_MIXER,
1523 RT3261_M_DAC_L2_DAC_L_SFT, 1, 1),
1526 static const struct snd_kcontrol_new rt3261_dig_r_mix[] = {
1527 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_DIG_MIXER,
1528 RT3261_M_STO_R_DAC_R_SFT, 1, 1),
1529 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_DIG_MIXER,
1530 RT3261_M_DAC_R2_DAC_R_SFT, 1, 1),
1533 /* Analog Input Mixer */
1534 static const struct snd_kcontrol_new rt3261_rec_l_mix[] = {
1535 SOC_DAPM_SINGLE("HPOL Switch", RT3261_REC_L2_MIXER,
1536 RT3261_M_HP_L_RM_L_SFT, 1, 1),
1537 SOC_DAPM_SINGLE("INL Switch", RT3261_REC_L2_MIXER,
1538 RT3261_M_IN_L_RM_L_SFT, 1, 1),
1539 SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_L2_MIXER,
1540 RT3261_M_BST2_RM_L, 1, 1),
1541 SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_L2_MIXER,
1542 RT3261_M_BST4_RM_L_SFT, 1, 1),
1543 SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_L2_MIXER,
1544 RT3261_M_BST1_RM_L_SFT, 1, 1),
1545 SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_REC_L2_MIXER,
1546 RT3261_M_OM_L_RM_L_SFT, 1, 1),
1549 static const struct snd_kcontrol_new rt3261_rec_r_mix[] = {
1550 SOC_DAPM_SINGLE("HPOR Switch", RT3261_REC_R2_MIXER,
1551 RT3261_M_HP_R_RM_R_SFT, 1, 1),
1552 SOC_DAPM_SINGLE("INR Switch", RT3261_REC_R2_MIXER,
1553 RT3261_M_IN_R_RM_R_SFT, 1, 1),
1554 SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_R2_MIXER,
1555 RT3261_M_BST2_RM_R_SFT, 1, 1),
1556 SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_R2_MIXER,
1557 RT3261_M_BST4_RM_R_SFT, 1, 1),
1558 SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_R2_MIXER,
1559 RT3261_M_BST1_RM_R_SFT, 1, 1),
1560 SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_REC_R2_MIXER,
1561 RT3261_M_OM_R_RM_R_SFT, 1, 1),
1564 /* Analog Output Mixer */
1565 static const struct snd_kcontrol_new rt3261_spk_l_mix[] = {
1566 SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_SPK_L_MIXER,
1567 RT3261_M_RM_L_SM_L_SFT, 1, 1),
1568 SOC_DAPM_SINGLE("INL Switch", RT3261_SPK_L_MIXER,
1569 RT3261_M_IN_L_SM_L_SFT, 1, 1),
1570 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPK_L_MIXER,
1571 RT3261_M_DAC_L1_SM_L_SFT, 1, 1),
1572 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_SPK_L_MIXER,
1573 RT3261_M_DAC_L2_SM_L_SFT, 1, 1),
1574 SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_SPK_L_MIXER,
1575 RT3261_M_OM_L_SM_L_SFT, 1, 1),
1578 static const struct snd_kcontrol_new rt3261_spk_r_mix[] = {
1579 SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_SPK_R_MIXER,
1580 RT3261_M_RM_R_SM_R_SFT, 1, 1),
1581 SOC_DAPM_SINGLE("INR Switch", RT3261_SPK_R_MIXER,
1582 RT3261_M_IN_R_SM_R_SFT, 1, 1),
1583 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPK_R_MIXER,
1584 RT3261_M_DAC_R1_SM_R_SFT, 1, 1),
1585 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_SPK_R_MIXER,
1586 RT3261_M_DAC_R2_SM_R_SFT, 1, 1),
1587 SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_SPK_R_MIXER,
1588 RT3261_M_OM_R_SM_R_SFT, 1, 1),
1591 static const struct snd_kcontrol_new rt3261_out_l_mix[] = {
1592 SOC_DAPM_SINGLE("SPK MIXL Switch", RT3261_OUT_L3_MIXER,
1593 RT3261_M_SM_L_OM_L_SFT, 1, 1),
1594 SOC_DAPM_SINGLE("BST3 Switch", RT3261_OUT_L3_MIXER,
1595 RT3261_M_BST2_OM_L_SFT, 1, 1),
1596 SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_L3_MIXER,
1597 RT3261_M_BST1_OM_L_SFT, 1, 1),
1598 SOC_DAPM_SINGLE("INL Switch", RT3261_OUT_L3_MIXER,
1599 RT3261_M_IN_L_OM_L_SFT, 1, 1),
1600 SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_OUT_L3_MIXER,
1601 RT3261_M_RM_L_OM_L_SFT, 1, 1),
1602 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_L3_MIXER,
1603 RT3261_M_DAC_R2_OM_L_SFT, 1, 1),
1604 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_L3_MIXER,
1605 RT3261_M_DAC_L2_OM_L_SFT, 1, 1),
1606 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_OUT_L3_MIXER,
1607 RT3261_M_DAC_L1_OM_L_SFT, 1, 1),
1610 static const struct snd_kcontrol_new rt3261_out_r_mix[] = {
1611 SOC_DAPM_SINGLE("SPK MIXR Switch", RT3261_OUT_R3_MIXER,
1612 RT3261_M_SM_L_OM_R_SFT, 1, 1),
1613 SOC_DAPM_SINGLE("BST3 Switch", RT3261_OUT_R3_MIXER,
1614 RT3261_M_BST2_OM_R_SFT, 1, 1),
1615 SOC_DAPM_SINGLE("BST2 Switch", RT3261_OUT_R3_MIXER,
1616 RT3261_M_BST4_OM_R_SFT, 1, 1),
1617 SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_R3_MIXER,
1618 RT3261_M_BST1_OM_R_SFT, 1, 1),
1619 SOC_DAPM_SINGLE("INR Switch", RT3261_OUT_R3_MIXER,
1620 RT3261_M_IN_R_OM_R_SFT, 1, 1),
1621 SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_OUT_R3_MIXER,
1622 RT3261_M_RM_R_OM_R_SFT, 1, 1),
1623 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_R3_MIXER,
1624 RT3261_M_DAC_L2_OM_R_SFT, 1, 1),
1625 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_R3_MIXER,
1626 RT3261_M_DAC_R2_OM_R_SFT, 1, 1),
1627 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_OUT_R3_MIXER,
1628 RT3261_M_DAC_R1_OM_R_SFT, 1, 1),
1631 static const struct snd_kcontrol_new rt3261_spo_l_mix[] = {
1633 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
1634 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1635 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
1636 RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
1638 SOC_DAPM_SINGLE("DAC Switch", RT3261_DUMMY_SPKMIXER,
1639 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1641 SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_L_MIXER,
1642 RT3261_M_SV_R_SPM_L_SFT, 1, 1),
1643 SOC_DAPM_SINGLE("SPKVOL L Switch", RT3261_SPO_L_MIXER,
1644 RT3261_M_SV_L_SPM_L_SFT, 1, 1),
1645 SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_L_MIXER,
1646 RT3261_M_BST1_SPM_L_SFT, 1, 1),
1649 static const struct snd_kcontrol_new rt3261_spo_dac_mix[] = {
1650 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
1651 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1652 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
1653 RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
1657 static const struct snd_kcontrol_new rt3261_spo_r_mix[] = {
1658 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_R_MIXER,
1659 RT3261_M_DAC_R1_SPM_R_SFT, 1, 1),
1660 SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_R_MIXER,
1661 RT3261_M_SV_R_SPM_R_SFT, 1, 1),
1662 SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_R_MIXER,
1663 RT3261_M_BST1_SPM_R_SFT, 1, 1),
1666 static const struct snd_kcontrol_new rt3261_hpo_mix[] = {
1667 SOC_DAPM_SINGLE("DAC2 Switch", RT3261_HPO_MIXER,
1668 RT3261_M_DAC2_HM_SFT, 1, 1),
1669 SOC_DAPM_SINGLE("DAC1 Switch", RT3261_HPO_MIXER,
1670 RT3261_M_DAC1_HM_SFT, 1, 1),
1671 SOC_DAPM_SINGLE("HPVOL Switch", RT3261_HPO_MIXER,
1672 RT3261_M_HPVOL_HM_SFT, 1, 1),
1675 static const struct snd_kcontrol_new rt3261_lout_mix[] = {
1676 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_LOUT_MIXER,
1677 RT3261_M_DAC_L1_LM_SFT, 1, 1),
1678 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_LOUT_MIXER,
1679 RT3261_M_DAC_R1_LM_SFT, 1, 1),
1680 SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_LOUT_MIXER,
1681 RT3261_M_OV_L_LM_SFT, 1, 1),
1682 SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_LOUT_MIXER,
1683 RT3261_M_OV_R_LM_SFT, 1, 1),
1686 static const struct snd_kcontrol_new rt3261_mono_mix[] = {
1687 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_MIXER,
1688 RT3261_M_DAC_R2_MM_SFT, 1, 1),
1689 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_MIXER,
1690 RT3261_M_DAC_L2_MM_SFT, 1, 1),
1691 SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_MONO_MIXER,
1692 RT3261_M_OV_R_MM_SFT, 1, 1),
1693 SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_MONO_MIXER,
1694 RT3261_M_OV_L_MM_SFT, 1, 1),
1695 SOC_DAPM_SINGLE("BST1 Switch", RT3261_MONO_MIXER,
1696 RT3261_M_BST1_MM_SFT, 1, 1),
1700 static const char *rt3261_inl_src[] = {"IN2P", "MonoP"};
1702 static const SOC_ENUM_SINGLE_DECL(
1703 rt3261_inl_enum, RT3261_INL_INR_VOL,
1704 RT3261_INL_SEL_SFT, rt3261_inl_src);
1706 static const struct snd_kcontrol_new rt3261_inl_mux =
1707 SOC_DAPM_ENUM("INL source", rt3261_inl_enum);
1709 static const char *rt3261_inr_src[] = {"IN2N", "MonoN"};
1711 static const SOC_ENUM_SINGLE_DECL(
1712 rt3261_inr_enum, RT3261_INL_INR_VOL,
1713 RT3261_INR_SEL_SFT, rt3261_inr_src);
1715 static const struct snd_kcontrol_new rt3261_inr_mux =
1716 SOC_DAPM_ENUM("INR source", rt3261_inr_enum);
1718 /* Stereo ADC source */
1719 static const char *rt3261_stereo_adc1_src[] = {"DIG MIX", "ADC"};
1721 static const SOC_ENUM_SINGLE_DECL(
1722 rt3261_stereo_adc1_enum, RT3261_STO_ADC_MIXER,
1723 RT3261_ADC_1_SRC_SFT, rt3261_stereo_adc1_src);
1725 static const struct snd_kcontrol_new rt3261_sto_adc_l1_mux =
1726 SOC_DAPM_ENUM("Stereo ADC L1 source", rt3261_stereo_adc1_enum);
1728 static const struct snd_kcontrol_new rt3261_sto_adc_r1_mux =
1729 SOC_DAPM_ENUM("Stereo ADC R1 source", rt3261_stereo_adc1_enum);
1731 static const char *rt3261_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
1733 static const SOC_ENUM_SINGLE_DECL(
1734 rt3261_stereo_adc2_enum, RT3261_STO_ADC_MIXER,
1735 RT3261_ADC_2_SRC_SFT, rt3261_stereo_adc2_src);
1737 static const struct snd_kcontrol_new rt3261_sto_adc_l2_mux =
1738 SOC_DAPM_ENUM("Stereo ADC L2 source", rt3261_stereo_adc2_enum);
1740 static const struct snd_kcontrol_new rt3261_sto_adc_r2_mux =
1741 SOC_DAPM_ENUM("Stereo ADC R2 source", rt3261_stereo_adc2_enum);
1743 /* Mono ADC source */
1744 static const char *rt3261_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
1746 static const SOC_ENUM_SINGLE_DECL(
1747 rt3261_mono_adc_l1_enum, RT3261_MONO_ADC_MIXER,
1748 RT3261_MONO_ADC_L1_SRC_SFT, rt3261_mono_adc_l1_src);
1750 static const struct snd_kcontrol_new rt3261_mono_adc_l1_mux =
1751 SOC_DAPM_ENUM("Mono ADC1 left source", rt3261_mono_adc_l1_enum);
1753 static const char *rt3261_mono_adc_l2_src[] =
1754 {"DMIC L1", "DMIC L2", "Mono DAC MIXL"};
1756 static const SOC_ENUM_SINGLE_DECL(
1757 rt3261_mono_adc_l2_enum, RT3261_MONO_ADC_MIXER,
1758 RT3261_MONO_ADC_L2_SRC_SFT, rt3261_mono_adc_l2_src);
1760 static const struct snd_kcontrol_new rt3261_mono_adc_l2_mux =
1761 SOC_DAPM_ENUM("Mono ADC2 left source", rt3261_mono_adc_l2_enum);
1763 static const char *rt3261_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
1765 static const SOC_ENUM_SINGLE_DECL(
1766 rt3261_mono_adc_r1_enum, RT3261_MONO_ADC_MIXER,
1767 RT3261_MONO_ADC_R1_SRC_SFT, rt3261_mono_adc_r1_src);
1769 static const struct snd_kcontrol_new rt3261_mono_adc_r1_mux =
1770 SOC_DAPM_ENUM("Mono ADC1 right source", rt3261_mono_adc_r1_enum);
1772 static const char *rt3261_mono_adc_r2_src[] =
1773 {"DMIC R1", "DMIC R2", "Mono DAC MIXR"};
1775 static const SOC_ENUM_SINGLE_DECL(
1776 rt3261_mono_adc_r2_enum, RT3261_MONO_ADC_MIXER,
1777 RT3261_MONO_ADC_R2_SRC_SFT, rt3261_mono_adc_r2_src);
1779 static const struct snd_kcontrol_new rt3261_mono_adc_r2_mux =
1780 SOC_DAPM_ENUM("Mono ADC2 right source", rt3261_mono_adc_r2_enum);
1782 /* DAC2 channel source */
1783 static const char *rt3261_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
1785 static const SOC_ENUM_SINGLE_DECL(rt3261_dac_l2_enum, RT3261_DSP_PATH2,
1786 RT3261_DAC_L2_SEL_SFT, rt3261_dac_l2_src);
1788 static const struct snd_kcontrol_new rt3261_dac_l2_mux =
1789 SOC_DAPM_ENUM("DAC2 left channel source", rt3261_dac_l2_enum);
1791 static const char *rt3261_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
1793 static const SOC_ENUM_SINGLE_DECL(
1794 rt3261_dac_r2_enum, RT3261_DSP_PATH2,
1795 RT3261_DAC_R2_SEL_SFT, rt3261_dac_r2_src);
1797 static const struct snd_kcontrol_new rt3261_dac_r2_mux =
1798 SOC_DAPM_ENUM("DAC2 right channel source", rt3261_dac_r2_enum);
1800 /* Interface 2 ADC channel source */
1801 static const char *rt3261_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
1803 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_l_enum, RT3261_DSP_PATH2,
1804 RT3261_IF2_ADC_L_SEL_SFT, rt3261_if2_adc_l_src);
1806 static const struct snd_kcontrol_new rt3261_if2_adc_l_mux =
1807 SOC_DAPM_ENUM("IF2 ADC left channel source", rt3261_if2_adc_l_enum);
1809 static const char *rt3261_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
1811 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_r_enum, RT3261_DSP_PATH2,
1812 RT3261_IF2_ADC_R_SEL_SFT, rt3261_if2_adc_r_src);
1814 static const struct snd_kcontrol_new rt3261_if2_adc_r_mux =
1815 SOC_DAPM_ENUM("IF2 ADC right channel source", rt3261_if2_adc_r_enum);
1817 /* digital interface and iis interface map */
1818 static const char *rt3261_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
1819 "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
1820 "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
1822 static const SOC_ENUM_SINGLE_DECL(
1823 rt3261_dai_iis_map_enum, RT3261_I2S1_SDP,
1824 RT3261_I2S_IF_SFT, rt3261_dai_iis_map);
1826 static const struct snd_kcontrol_new rt3261_dai_mux =
1827 SOC_DAPM_ENUM("DAI select", rt3261_dai_iis_map_enum);
1830 static const char *rt3261_sdi_sel[] = {"IF1", "IF2"};
1832 static const SOC_ENUM_SINGLE_DECL(
1833 rt3261_sdi_sel_enum, RT3261_I2S2_SDP,
1834 RT3261_I2S2_SDI_SFT, rt3261_sdi_sel);
1836 static const struct snd_kcontrol_new rt3261_sdi_mux =
1837 SOC_DAPM_ENUM("SDI select", rt3261_sdi_sel_enum);
1839 static int rt3261_adc_event(struct snd_soc_dapm_widget *w,
1840 struct snd_kcontrol *kcontrol, int event)
1842 struct snd_soc_codec *codec = w->codec;
1843 unsigned int val, mask;
1846 case SND_SOC_DAPM_POST_PMU:
1847 //rt3261_index_update_bits(codec,
1848 // RT3261_CHOP_DAC_ADC, 0x1000, 0x1000);
1850 val = snd_soc_read(codec, RT3261_MONO_ADC_MIXER);
1851 mask = RT3261_M_MONO_ADC_L1 | RT3261_M_MONO_ADC_L2 |
1852 RT3261_M_MONO_ADC_R1 | RT3261_M_MONO_ADC_R2;
1853 if ((val & mask) ^ mask)
1854 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1855 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R, 0);
1859 case SND_SOC_DAPM_POST_PMD:
1861 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1862 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R,
1863 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R);
1865 //rt3261_index_update_bits(codec,
1866 // RT3261_CHOP_DAC_ADC, 0x1000, 0x0000);
1877 static int rt3261_mono_adcl_event(struct snd_soc_dapm_widget *w,
1878 struct snd_kcontrol *kcontrol, int event)
1880 struct snd_soc_codec *codec = w->codec;
1881 unsigned int val, mask;
1884 case SND_SOC_DAPM_POST_PMU:
1885 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1886 RT3261_M_MAMIX_L, 0);
1888 case SND_SOC_DAPM_PRE_PMD:
1889 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1901 static int rt3261_mono_adcr_event(struct snd_soc_dapm_widget *w,
1902 struct snd_kcontrol *kcontrol, int event)
1904 struct snd_soc_codec *codec = w->codec;
1905 unsigned int val, mask;
1908 case SND_SOC_DAPM_POST_PMU:
1909 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1910 RT3261_M_MAMIX_R, 0);
1912 case SND_SOC_DAPM_PRE_PMD:
1913 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1925 static int rt3261_spk_event(struct snd_soc_dapm_widget *w,
1926 struct snd_kcontrol *kcontrol, int event)
1928 struct snd_soc_codec *codec = w->codec;
1932 case SND_SOC_DAPM_POST_PMU:
1934 val = snd_soc_read(codec, RT3261_PWR_DIG1);
1935 if(val & (RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1)) {
1936 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1937 RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1,
1938 RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1);
1941 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1942 RT3261_PWR_CLS_D, RT3261_PWR_CLS_D);
1943 rt3261_index_update_bits(codec,
1944 RT3261_CLSD_INT_REG1, 0xf000, 0xf000);
1945 snd_soc_update_bits(codec, RT3261_SPK_VOL,
1946 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1949 case SND_SOC_DAPM_PRE_PMD:
1950 snd_soc_update_bits(codec, RT3261_SPK_VOL,
1951 RT3261_L_MUTE | RT3261_R_MUTE,
1952 RT3261_L_MUTE | RT3261_R_MUTE);
1953 rt3261_index_update_bits(codec,
1954 RT3261_CLSD_INT_REG1, 0xf000, 0x0000);
1955 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1956 RT3261_PWR_CLS_D, 0);
1967 static void rt3261_pmu_depop(struct snd_soc_codec *codec)
1970 /* depop parameters */
1971 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0200); //bard 12-6
1972 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
1973 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
1974 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1975 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1976 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
1977 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
1978 /* headphone amp power on */
1979 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1980 RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
1981 snd_soc_update_bits(codec, RT3261_PWR_VOL,
1982 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
1983 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
1984 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1985 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1986 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
1988 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1989 RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
1990 RT3261_PWR_HP_R | RT3261_PWR_HA,
1991 RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
1992 RT3261_PWR_HP_R | RT3261_PWR_HA);
1993 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
1994 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
1995 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
1996 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1997 RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
1998 RT3261_HP_CO_EN | RT3261_HP_SG_EN);
1999 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0400); //bard 12-6
2001 hp_amp_power(codec, 1);
2003 /* headphone unmute sequence */
2004 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
2005 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
2006 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
2007 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
2008 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
2009 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
2010 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2011 RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
2012 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2013 RT3261_RSTN_MASK, RT3261_RSTN_EN);
2014 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2015 RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
2016 RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
2017 snd_soc_update_bits(codec, RT3261_HP_VOL,
2018 RT3261_L_MUTE | RT3261_R_MUTE, 0);
2020 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2021 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
2022 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
2023 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
2026 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2027 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
2031 static void rt3261_pmd_depop(struct snd_soc_codec *codec)
2033 /* headphone mute sequence */
2034 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
2035 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
2036 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
2037 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
2038 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
2039 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
2040 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2041 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
2042 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2043 RT3261_RSTP_MASK, RT3261_RSTP_EN);
2044 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2045 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
2046 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
2047 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
2049 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2050 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
2053 snd_soc_update_bits(codec, RT3261_HP_VOL,
2054 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
2057 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
2058 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2059 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
2060 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
2061 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
2062 /* headphone amp power down */
2063 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2064 RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
2065 RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
2066 RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
2067 RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
2068 RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
2069 RT3261_HP_SG_EN | RT3261_HP_CB_PD);
2070 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2071 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
2074 hp_amp_power(codec, 0);
2078 static void rt3261_pmu_depop(struct snd_soc_codec *codec)
2080 /* depop parameters */
2081 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0200); //bard 12-6
2082 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
2083 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
2084 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2085 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
2086 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
2087 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
2088 /* headphone amp power on */
2089 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2090 RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
2091 snd_soc_update_bits(codec, RT3261_PWR_VOL,
2092 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
2093 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
2094 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2095 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
2096 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
2098 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2099 RT3261_PWR_FV1 | RT3261_PWR_FV2 ,
2100 RT3261_PWR_FV1 | RT3261_PWR_FV2 );
2101 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
2102 /* headphone unmute sequence */
2103 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
2104 RT3261_DEPOP_MASK | RT3261_DIG_DP_MASK,
2105 RT3261_DEPOP_AUTO | RT3261_DIG_DP_EN);
2106 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
2107 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
2108 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
2109 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
2110 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
2111 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
2112 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
2113 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2114 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK,
2115 RT3261_HP_CP_PD | RT3261_HP_SG_EN);
2116 rt3261_index_update_bits(codec, RT3261_CHPUMP_INT_REG1,0x0700, 0x0400); //bard 12-6
2118 snd_soc_update_bits(codec, RT3261_HP_VOL,
2119 RT3261_L_MUTE | RT3261_R_MUTE, 0);
2120 msleep(70); //bard 10-18
2122 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2123 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
2127 static void rt3261_pmd_depop(struct snd_soc_codec *codec)
2130 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
2131 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
2133 snd_soc_update_bits(codec, RT3261_HP_VOL,
2134 RT3261_L_MUTE | RT3261_R_MUTE,
2135 RT3261_L_MUTE | RT3261_R_MUTE);
2137 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
2138 RT3261_HP_CB_MASK, RT3261_HP_CB_PD);
2140 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
2141 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2142 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
2147 static int rt3261_hp_event(struct snd_soc_dapm_widget *w,
2148 struct snd_kcontrol *kcontrol, int event)
2150 struct snd_soc_codec *codec = w->codec;
2153 case SND_SOC_DAPM_POST_PMU:
2154 rt3261_pmu_depop(codec);
2157 case SND_SOC_DAPM_PRE_PMD:
2158 rt3261_pmd_depop(codec);
2168 static int rt3261_mono_event(struct snd_soc_dapm_widget *w,
2169 struct snd_kcontrol *kcontrol, int event)
2171 struct snd_soc_codec *codec = w->codec;
2174 case SND_SOC_DAPM_POST_PMU:
2175 snd_soc_update_bits(codec, RT3261_MONO_OUT,
2179 case SND_SOC_DAPM_PRE_PMD:
2180 snd_soc_update_bits(codec, RT3261_MONO_OUT,
2181 RT3261_L_MUTE, RT3261_L_MUTE);
2191 static int rt3261_lout_event(struct snd_soc_dapm_widget *w,
2192 struct snd_kcontrol *kcontrol, int event)
2194 struct snd_soc_codec *codec = w->codec;
2197 case SND_SOC_DAPM_POST_PMU:
2198 hp_amp_power(codec,1);
2199 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2200 RT3261_PWR_LM, RT3261_PWR_LM); //bard 10-18
2201 snd_soc_update_bits(codec, RT3261_OUTPUT,
2202 RT3261_L_MUTE | RT3261_R_MUTE, 0);
2205 case SND_SOC_DAPM_PRE_PMD:
2206 snd_soc_update_bits(codec, RT3261_OUTPUT,
2207 RT3261_L_MUTE | RT3261_R_MUTE,
2208 RT3261_L_MUTE | RT3261_R_MUTE);
2209 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2210 RT3261_PWR_LM, 0); //bard 10-18
2211 hp_amp_power(codec,0);
2221 static int rt3261_dac_event(struct snd_soc_dapm_widget *w,
2222 struct snd_kcontrol *kcontrol, int event)
2224 struct snd_soc_codec *codec = w->codec;
2225 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2228 case SND_SOC_DAPM_POST_PMU:
2229 if( rt3261->asrc_en == RT3261_ASRC_EN)
2230 rt3261_update_eqmode(codec, 2);//BT_VOIP
2233 case SND_SOC_DAPM_PRE_PMD:
2234 rt3261_update_eqmode(codec, 0);//NORMAL
2244 static const struct snd_soc_dapm_widget rt3261_dapm_widgets[] = {
2245 SND_SOC_DAPM_SUPPLY("PLL1", RT3261_PWR_ANLG2,
2246 RT3261_PWR_PLL_BIT, 0, NULL, 0),
2249 SND_SOC_DAPM_SUPPLY("LDO2", RT3261_PWR_ANLG1,
2250 RT3261_PWR_LDO2_BIT, 0, NULL, 0),
2252 SND_SOC_DAPM_MICBIAS("micbias1", RT3261_PWR_ANLG2,
2253 RT3261_PWR_MB1_BIT, 0),
2255 SND_SOC_DAPM_MICBIAS("micbias1", SND_SOC_NOPM,
2258 SND_SOC_DAPM_MICBIAS("micbias2", RT3261_PWR_ANLG2,
2259 RT3261_PWR_MB2_BIT, 0),
2261 SND_SOC_DAPM_INPUT("MIC1"),
2262 SND_SOC_DAPM_INPUT("MIC2"),
2263 SND_SOC_DAPM_INPUT("MIC3"),
2264 SND_SOC_DAPM_INPUT("DMIC1"),
2265 SND_SOC_DAPM_INPUT("DMIC2"),
2267 SND_SOC_DAPM_INPUT("IN1P"),
2268 SND_SOC_DAPM_INPUT("IN1N"),
2269 SND_SOC_DAPM_INPUT("IN2P"),
2270 SND_SOC_DAPM_INPUT("IN2N"),
2271 SND_SOC_DAPM_INPUT("IN3P"),
2272 SND_SOC_DAPM_INPUT("IN3N"),
2273 SND_SOC_DAPM_INPUT("DMIC L1"),
2274 SND_SOC_DAPM_INPUT("DMIC R1"),
2275 SND_SOC_DAPM_INPUT("DMIC L2"),
2276 SND_SOC_DAPM_INPUT("DMIC R2"),
2277 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2278 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2280 SND_SOC_DAPM_PGA("BST1", RT3261_PWR_ANLG2,
2281 RT3261_PWR_BST1_BIT, 0, NULL, 0),
2282 SND_SOC_DAPM_PGA("BST2", RT3261_PWR_ANLG2,
2283 RT3261_PWR_BST4_BIT, 0, NULL, 0),
2284 SND_SOC_DAPM_PGA("BST3", RT3261_PWR_ANLG2,
2285 RT3261_PWR_BST2_BIT, 0, NULL, 0),
2287 SND_SOC_DAPM_PGA("INL VOL", RT3261_PWR_VOL,
2288 RT3261_PWR_IN_L_BIT, 0, NULL, 0),
2289 SND_SOC_DAPM_PGA("INR VOL", RT3261_PWR_VOL,
2290 RT3261_PWR_IN_R_BIT, 0, NULL, 0),
2292 SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt3261_inl_mux),
2293 SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt3261_inr_mux),
2295 SND_SOC_DAPM_MIXER("RECMIXL", RT3261_PWR_MIXER, RT3261_PWR_RM_L_BIT, 0,
2296 rt3261_rec_l_mix, ARRAY_SIZE(rt3261_rec_l_mix)),
2297 SND_SOC_DAPM_MIXER("RECMIXR", RT3261_PWR_MIXER, RT3261_PWR_RM_R_BIT, 0,
2298 rt3261_rec_r_mix, ARRAY_SIZE(rt3261_rec_r_mix)),
2300 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM,
2302 SND_SOC_DAPM_ADC_E("ADC R", NULL, SND_SOC_NOPM,
2303 0, 0, rt3261_adc_event,
2304 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
2306 SND_SOC_DAPM_SUPPLY("ADC L power",RT3261_PWR_DIG1,
2307 RT3261_PWR_ADC_L_BIT, 0, NULL, 0),
2308 SND_SOC_DAPM_SUPPLY("ADC R power",RT3261_PWR_DIG1,
2309 RT3261_PWR_ADC_R_BIT, 0, NULL, 0),
2311 SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2312 &rt3261_sto_adc_l2_mux),
2313 SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2314 &rt3261_sto_adc_r2_mux),
2315 SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2316 &rt3261_sto_adc_l1_mux),
2317 SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2318 &rt3261_sto_adc_r1_mux),
2319 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2320 &rt3261_mono_adc_l2_mux),
2321 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2322 &rt3261_mono_adc_l1_mux),
2323 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2324 &rt3261_mono_adc_r1_mux),
2325 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2326 &rt3261_mono_adc_r2_mux),
2328 SND_SOC_DAPM_SUPPLY("stereo filter", RT3261_PWR_DIG2,
2329 RT3261_PWR_ADC_SF_BIT, 0, NULL, 0),
2330 SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
2331 rt3261_sto_adc_l_mix, ARRAY_SIZE(rt3261_sto_adc_l_mix)),
2332 SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
2333 rt3261_sto_adc_r_mix, ARRAY_SIZE(rt3261_sto_adc_r_mix)),
2334 SND_SOC_DAPM_SUPPLY("mono left filter", RT3261_PWR_DIG2,
2335 RT3261_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2336 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2337 rt3261_mono_adc_l_mix, ARRAY_SIZE(rt3261_mono_adc_l_mix),
2338 rt3261_mono_adcl_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), //bard 3-26
2339 SND_SOC_DAPM_SUPPLY("mono right filter", RT3261_PWR_DIG2,
2340 RT3261_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2341 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2342 rt3261_mono_adc_r_mix, ARRAY_SIZE(rt3261_mono_adc_r_mix),
2343 rt3261_mono_adcr_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), //bard 3-26
2346 SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2347 &rt3261_if2_adc_l_mux),
2348 SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2349 &rt3261_if2_adc_r_mux),
2351 /* Digital Interface */
2352 SND_SOC_DAPM_SUPPLY("I2S1", RT3261_PWR_DIG1,
2353 RT3261_PWR_I2S1_BIT, 0, NULL, 0),
2354 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2355 SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2356 SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2357 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2358 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2359 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2360 SND_SOC_DAPM_SUPPLY("I2S2", RT3261_PWR_DIG1,
2361 RT3261_PWR_I2S2_BIT, 0, NULL, 0),
2362 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2363 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2364 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2365 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2366 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2367 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2368 SND_SOC_DAPM_SUPPLY("I2S3", RT3261_PWR_DIG1,
2369 RT3261_PWR_I2S3_BIT, 0, NULL, 0),
2370 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2371 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2372 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2373 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2374 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2375 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2377 /* Digital Interface Select */
2378 SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2379 SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2380 SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2381 SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2382 SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
2384 SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2385 SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2386 SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2387 SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2388 SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
2390 SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2391 SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2393 /* Audio Interface */
2394 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2395 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2396 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2397 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2398 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2399 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2402 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2405 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
2408 /* DAC mixer before sound effect */
2410 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2411 rt3261_dac_l_mix, ARRAY_SIZE(rt3261_dac_l_mix)),
2412 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2413 rt3261_dac_r_mix, ARRAY_SIZE(rt3261_dac_r_mix)),
2415 SND_SOC_DAPM_MIXER_E("DAC MIXL", SND_SOC_NOPM, 0, 0,
2416 rt3261_dac_l_mix, ARRAY_SIZE(rt3261_dac_l_mix),
2417 rt3261_dac_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2418 SND_SOC_DAPM_MIXER_E("DAC MIXR", SND_SOC_NOPM, 0, 0,
2419 rt3261_dac_r_mix, ARRAY_SIZE(rt3261_dac_r_mix),
2420 rt3261_dac_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2423 /* DAC2 channel Mux */
2424 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
2425 &rt3261_dac_l2_mux),
2426 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
2427 &rt3261_dac_r2_mux),
2429 SND_SOC_DAPM_PGA("DAC L2 Volume", RT3261_PWR_DIG1,
2430 RT3261_PWR_DAC_L2_BIT, 0, NULL, 0),
2431 SND_SOC_DAPM_PGA("DAC R2 Volume", RT3261_PWR_DIG1,
2432 RT3261_PWR_DAC_R2_BIT, 0, NULL, 0),
2434 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM,
2436 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM,
2438 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT3261_PWR_DIG1,
2439 RT3261_PWR_DAC_L1_BIT, 0, NULL, 0),
2440 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT3261_PWR_DIG1,
2441 RT3261_PWR_DAC_R1_BIT, 0, NULL, 0),
2442 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT3261_PWR_DIG1,
2443 RT3261_PWR_DAC_L2_BIT, 0, NULL, 0),
2444 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT3261_PWR_DIG1,
2445 RT3261_PWR_DAC_R2_BIT, 0, NULL, 0),
2449 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2450 rt3261_sto_dac_l_mix, ARRAY_SIZE(rt3261_sto_dac_l_mix)),
2451 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2452 rt3261_sto_dac_r_mix, ARRAY_SIZE(rt3261_sto_dac_r_mix)),
2453 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2454 rt3261_mono_dac_l_mix, ARRAY_SIZE(rt3261_mono_dac_l_mix)),
2455 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2456 rt3261_mono_dac_r_mix, ARRAY_SIZE(rt3261_mono_dac_r_mix)),
2457 SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
2458 rt3261_dig_l_mix, ARRAY_SIZE(rt3261_dig_l_mix)),
2459 SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
2460 rt3261_dig_r_mix, ARRAY_SIZE(rt3261_dig_r_mix)),
2461 SND_SOC_DAPM_MUX("Mono dacr Mux", SND_SOC_NOPM, 0, 0,
2466 SND_SOC_DAPM_DAC("DAC L1", NULL, RT3261_PWR_DIG1,
2467 RT3261_PWR_DAC_L1_BIT, 0),
2468 SND_SOC_DAPM_DAC("DAC L2", NULL, RT3261_PWR_DIG1,
2469 RT3261_PWR_DAC_L2_BIT, 0),
2470 SND_SOC_DAPM_DAC("DAC R1", NULL, RT3261_PWR_DIG1,
2471 RT3261_PWR_DAC_R1_BIT, 0),
2472 SND_SOC_DAPM_DAC("DAC R2", NULL, RT3261_PWR_DIG1,
2473 RT3261_PWR_DAC_R2_BIT, 0),
2475 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
2476 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
2477 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
2478 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
2480 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
2482 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM,
2485 SND_SOC_DAPM_MIXER("SPK MIXL", RT3261_PWR_MIXER, RT3261_PWR_SM_L_BIT,
2486 0, rt3261_spk_l_mix, ARRAY_SIZE(rt3261_spk_l_mix)),
2487 SND_SOC_DAPM_MIXER("SPK MIXR", RT3261_PWR_MIXER, RT3261_PWR_SM_R_BIT,
2488 0, rt3261_spk_r_mix, ARRAY_SIZE(rt3261_spk_r_mix)),
2489 SND_SOC_DAPM_MIXER("OUT MIXL", RT3261_PWR_MIXER, RT3261_PWR_OM_L_BIT,
2490 0, rt3261_out_l_mix, ARRAY_SIZE(rt3261_out_l_mix)),
2491 SND_SOC_DAPM_MIXER("OUT MIXR", RT3261_PWR_MIXER, RT3261_PWR_OM_R_BIT,
2492 0, rt3261_out_r_mix, ARRAY_SIZE(rt3261_out_r_mix)),
2494 SND_SOC_DAPM_PGA("SPKVOL L", RT3261_PWR_VOL,
2495 RT3261_PWR_SV_L_BIT, 0, NULL, 0),
2496 SND_SOC_DAPM_PGA("SPKVOL R", RT3261_PWR_VOL,
2497 RT3261_PWR_SV_R_BIT, 0, NULL, 0),
2498 SND_SOC_DAPM_PGA("OUTVOL L", RT3261_PWR_VOL,
2499 RT3261_PWR_OV_L_BIT, 0, NULL, 0),
2500 SND_SOC_DAPM_PGA("OUTVOL R", RT3261_PWR_VOL,
2501 RT3261_PWR_OV_R_BIT, 0, NULL, 0),
2502 SND_SOC_DAPM_PGA("HPOVOL L", RT3261_PWR_VOL,
2503 RT3261_PWR_HV_L_BIT, 0, NULL, 0),
2504 SND_SOC_DAPM_PGA("HPOVOL R", RT3261_PWR_VOL,
2505 RT3261_PWR_HV_R_BIT, 0, NULL, 0),
2506 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM,
2508 /* SPO/HPO/LOUT/Mono Mixer */
2509 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
2510 0, rt3261_spo_l_mix, ARRAY_SIZE(rt3261_spo_l_mix)),
2511 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
2512 0, rt3261_spo_r_mix, ARRAY_SIZE(rt3261_spo_r_mix)),
2513 SND_SOC_DAPM_MIXER("DAC SPK", SND_SOC_NOPM, 0,
2514 0, rt3261_spo_dac_mix, ARRAY_SIZE(rt3261_spo_dac_mix)), //bard 8-27
2515 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
2516 rt3261_hpo_mix, ARRAY_SIZE(rt3261_hpo_mix)),
2517 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
2518 rt3261_lout_mix, ARRAY_SIZE(rt3261_lout_mix)),
2519 SND_SOC_DAPM_MIXER("Mono MIX", RT3261_PWR_ANLG1, RT3261_PWR_MM_BIT, 0,
2520 rt3261_mono_mix, ARRAY_SIZE(rt3261_mono_mix)),
2522 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0,
2523 rt3261_hp_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2524 SND_SOC_DAPM_PGA_S("SPK amp", 1, SND_SOC_NOPM, 0, 0,
2525 rt3261_spk_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2526 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
2527 rt3261_lout_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2528 SND_SOC_DAPM_PGA_S("Mono amp", 1, RT3261_PWR_ANLG1,
2529 RT3261_PWR_MA_BIT, 0, rt3261_mono_event,
2530 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2533 SND_SOC_DAPM_OUTPUT("SPOLP"),
2534 SND_SOC_DAPM_OUTPUT("SPOLN"),
2535 SND_SOC_DAPM_OUTPUT("SPORP"),
2536 SND_SOC_DAPM_OUTPUT("SPORN"),
2537 SND_SOC_DAPM_OUTPUT("HPOL"),
2538 SND_SOC_DAPM_OUTPUT("HPOR"),
2539 SND_SOC_DAPM_OUTPUT("LOUTL"),
2540 SND_SOC_DAPM_OUTPUT("LOUTR"),
2541 SND_SOC_DAPM_OUTPUT("MonoP"),
2542 SND_SOC_DAPM_OUTPUT("MonoN"),
2545 static const struct snd_soc_dapm_route rt3261_dapm_routes[] = {
2546 {"IN1P", NULL, "LDO2"},
2547 {"IN2P", NULL, "LDO2"},
2548 {"IN3P", NULL, "LDO2"},
2550 {"IN1P", NULL, "MIC1"},
2551 {"IN1N", NULL, "MIC1"},
2552 {"IN2P", NULL, "MIC2"},
2553 {"IN2N", NULL, "MIC2"},
2554 {"IN3P", NULL, "MIC3"},
2555 {"IN3N", NULL, "MIC3"},
2557 {"DMIC L1", NULL, "DMIC1"},
2558 {"DMIC R1", NULL, "DMIC1"},
2559 {"DMIC L2", NULL, "DMIC2"},
2560 {"DMIC R2", NULL, "DMIC2"},
2562 {"BST1", NULL, "IN1P"},
2563 {"BST1", NULL, "IN1N"},
2564 {"BST2", NULL, "IN2P"},
2565 {"BST2", NULL, "IN2N"},
2566 {"BST3", NULL, "IN3P"},
2567 {"BST3", NULL, "IN3N"},
2569 {"INL VOL", NULL, "IN2P"},
2570 {"INR VOL", NULL, "IN2N"},
2572 {"RECMIXL", "HPOL Switch", "HPOL"},
2573 {"RECMIXL", "INL Switch", "INL VOL"},
2574 {"RECMIXL", "BST3 Switch", "BST3"},
2575 {"RECMIXL", "BST2 Switch", "BST2"},
2576 {"RECMIXL", "BST1 Switch", "BST1"},
2577 {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
2579 {"RECMIXR", "HPOR Switch", "HPOR"},
2580 {"RECMIXR", "INR Switch", "INR VOL"},
2581 {"RECMIXR", "BST3 Switch", "BST3"},
2582 {"RECMIXR", "BST2 Switch", "BST2"},
2583 {"RECMIXR", "BST1 Switch", "BST1"},
2584 {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
2586 {"ADC L", NULL, "RECMIXL"},
2587 {"ADC L", NULL, "ADC L power"},
2588 {"ADC R", NULL, "RECMIXR"},
2589 {"ADC R", NULL, "ADC R power"},
2591 {"DMIC L1", NULL, "DMIC CLK"},
2592 {"DMIC L2", NULL, "DMIC CLK"},
2594 {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
2595 {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
2596 {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
2597 {"Stereo ADC L1 Mux", "ADC", "ADC L"},
2598 {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
2600 {"Stereo ADC R1 Mux", "ADC", "ADC R"},
2601 {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
2602 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
2603 {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
2604 {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
2606 {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
2607 {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
2608 {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
2609 {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
2610 {"Mono ADC L1 Mux", "ADCL", "ADC L"},
2612 {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
2613 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
2614 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
2615 {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
2616 {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
2618 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
2619 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
2620 {"Stereo ADC MIXL", NULL, "stereo filter"},
2621 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
2623 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
2624 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
2625 {"Stereo ADC MIXR", NULL, "stereo filter"},
2626 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
2628 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
2629 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
2630 {"Mono ADC MIXL", NULL, "mono left filter"},
2631 {"mono left filter", NULL, "PLL1", check_sysclk1_source},
2633 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
2634 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
2635 {"Mono ADC MIXR", NULL, "mono right filter"},
2636 {"mono right filter", NULL, "PLL1", check_sysclk1_source},
2638 {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
2639 {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
2641 {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
2642 {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
2643 {"IF3 ADC L", NULL, "Mono ADC MIXL"},
2644 {"IF3 ADC R", NULL, "Mono ADC MIXR"},
2645 {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
2646 {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
2648 {"IF1 ADC", NULL, "I2S1"},
2649 {"IF1 ADC", NULL, "IF1 ADC L"},
2650 {"IF1 ADC", NULL, "IF1 ADC R"},
2651 {"IF2 ADC", NULL, "I2S2"},
2652 {"IF2 ADC", NULL, "IF2 ADC L"},
2653 {"IF2 ADC", NULL, "IF2 ADC R"},
2654 {"IF3 ADC", NULL, "I2S3"},
2655 {"IF3 ADC", NULL, "IF3 ADC L"},
2656 {"IF3 ADC", NULL, "IF3 ADC R"},
2658 {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
2659 {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
2660 {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
2661 {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
2662 {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
2663 {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
2664 {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
2665 {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
2666 {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
2667 {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
2669 {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
2670 {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
2671 {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
2672 {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
2673 {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
2674 {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
2675 {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
2676 {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
2677 {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
2678 {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
2680 {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
2681 {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
2682 {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
2683 {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
2684 {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
2685 {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
2686 {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
2687 {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
2689 {"AIF1TX", NULL, "DAI1 TX Mux"},
2690 {"AIF1TX", NULL, "SDI1 TX Mux"},
2691 {"AIF2TX", NULL, "DAI2 TX Mux"},
2692 {"AIF2TX", NULL, "SDI2 TX Mux"},
2693 {"AIF3TX", NULL, "DAI3 TX Mux"},
2695 {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
2696 {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
2697 {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
2698 {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
2699 {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
2700 {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
2701 {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
2702 {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
2704 {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
2705 {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
2706 {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
2707 {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
2708 {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
2709 {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
2710 {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
2711 {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
2713 {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
2714 {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
2715 {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
2716 {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
2717 {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
2718 {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
2719 {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
2720 {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
2722 {"IF1 DAC", NULL, "I2S1"},
2723 {"IF1 DAC", NULL, "DAI1 RX Mux"},
2724 {"IF2 DAC", NULL, "I2S2"},
2725 {"IF2 DAC", NULL, "DAI2 RX Mux"},
2726 {"IF3 DAC", NULL, "I2S3"},
2727 {"IF3 DAC", NULL, "DAI3 RX Mux"},
2729 {"IF1 DAC L", NULL, "IF1 DAC"},
2730 {"IF1 DAC R", NULL, "IF1 DAC"},
2731 {"IF2 DAC L", NULL, "IF2 DAC"},
2732 {"IF2 DAC R", NULL, "IF2 DAC"},
2733 {"IF3 DAC L", NULL, "IF3 DAC"},
2734 {"IF3 DAC R", NULL, "IF3 DAC"},
2736 {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
2737 {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
2738 {"DAC MIXL", NULL, "DAC L1 Power"}, //bard 9-26
2739 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
2740 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
2741 {"DAC MIXR", NULL, "DAC R1 Power"}, //bard 9-26
2743 {"ANC", NULL, "Stereo ADC MIXL"},
2744 {"ANC", NULL, "Stereo ADC MIXR"},
2746 {"Audio DSP", NULL, "DAC MIXL"},
2747 {"Audio DSP", NULL, "DAC MIXR"},
2749 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
2750 {"DAC L2 Mux", "IF3", "IF3 DAC L"},
2751 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
2752 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
2753 {"DAC L2 Volume", NULL, "DAC L2 Power"}, //bard 9-26
2755 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
2756 {"DAC R2 Mux", "IF3", "IF3 DAC R"},
2757 {"DAC R2 Volume", NULL, "Mono dacr Mux"},
2758 {"Mono dacr Mux", "TxDC_R", "DAC R2 Mux"},
2759 {"Mono dacr Mux", "TxDP_R", "IF2 ADC R Mux"},
2760 {"DAC R2 Volume", NULL, "DAC R2 Power"}, //bsrd 9-26
2762 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
2763 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2764 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
2765 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
2766 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2767 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
2769 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
2770 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2771 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume"},
2772 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
2773 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2774 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume"},
2776 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
2777 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2778 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
2779 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2781 {"DAC L1", NULL, "Stereo DAC MIXL"},
2782 {"DAC L1", NULL, "PLL1", check_sysclk1_source},
2783 {"DAC L1", NULL, "DAC L1 Power"}, //bard 9-26
2784 {"DAC R1", NULL, "Stereo DAC MIXR"},
2785 {"DAC R1", NULL, "PLL1", check_sysclk1_source},
2786 {"DAC R1", NULL, "DAC R1 Power"}, //bard 9-26
2787 {"DAC L2", NULL, "Mono DAC MIXL"},
2788 {"DAC L2", NULL, "PLL1", check_sysclk1_source},
2789 {"DAC L2", NULL, "DAC L2 Power"}, //bard 9-26
2790 {"DAC R2", NULL, "Mono DAC MIXR"},
2791 {"DAC R2", NULL, "PLL1", check_sysclk1_source},
2792 {"DAC R2", NULL, "DAC R2 Power"}, //bard 9-26
2794 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
2795 {"SPK MIXL", "INL Switch", "INL VOL"},
2796 {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
2797 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
2798 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
2799 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
2800 {"SPK MIXR", "INR Switch", "INR VOL"},
2801 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
2802 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
2803 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
2805 {"OUT MIXL", "BST3 Switch", "BST3"},
2806 {"OUT MIXL", "BST1 Switch", "BST1"},
2807 {"OUT MIXL", "INL Switch", "INL VOL"},
2808 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
2809 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
2810 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
2811 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
2813 {"OUT MIXR", "BST3 Switch", "BST3"},
2814 {"OUT MIXR", "BST2 Switch", "BST2"},
2815 {"OUT MIXR", "BST1 Switch", "BST1"},
2816 {"OUT MIXR", "INR Switch", "INR VOL"},
2817 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
2818 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
2819 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
2820 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
2822 {"SPKVOL L", NULL, "SPK MIXL"},
2823 {"SPKVOL R", NULL, "SPK MIXR"},
2824 {"HPOVOL L", NULL, "OUT MIXL"},
2825 {"HPOVOL R", NULL, "OUT MIXR"},
2826 {"OUTVOL L", NULL, "OUT MIXL"},
2827 {"OUTVOL R", NULL, "OUT MIXR"},
2829 {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
2830 {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
2832 {"SPOL MIX", "DAC Switch", "DAC SPK"},
2833 {"DAC SPK", "DAC L1 Switch", "DAC L1"},
2834 {"DAC SPK", "DAC R1 Switch", "DAC R1"},
2836 {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
2837 {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
2838 {"SPOL MIX", "BST1 Switch", "BST1"},
2839 {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
2840 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
2841 {"SPOR MIX", "BST1 Switch", "BST1"},
2843 {"DAC 2", NULL, "DAC L2"},
2844 {"DAC 2", NULL, "DAC R2"},
2845 {"DAC 1", NULL, "DAC L1"},
2846 {"DAC 1", NULL, "DAC R1"},
2847 {"HPOVOL", NULL, "HPOVOL L"},
2848 {"HPOVOL", NULL, "HPOVOL R"},
2849 {"HPO MIX", "DAC2 Switch", "DAC 2"},
2850 {"HPO MIX", "DAC1 Switch", "DAC 1"},
2851 {"HPO MIX", "HPVOL Switch", "HPOVOL"},
2853 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
2854 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
2855 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
2856 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
2858 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
2859 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
2860 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
2861 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
2862 {"Mono MIX", "BST1 Switch", "BST1"},
2864 {"SPK amp", NULL, "SPOL MIX"},
2865 {"SPK amp", NULL, "SPOR MIX"},
2866 {"SPOLP", NULL, "SPK amp"},
2867 {"SPOLN", NULL, "SPK amp"},
2868 {"SPORP", NULL, "SPK amp"},
2869 {"SPORN", NULL, "SPK amp"},
2871 {"HP amp", NULL, "HPO MIX"},
2872 {"HPOL", NULL, "HP amp"},
2873 {"HPOR", NULL, "HP amp"},
2875 {"LOUT amp", NULL, "LOUT MIX"},
2876 {"LOUTL", NULL, "LOUT amp"},
2877 {"LOUTR", NULL, "LOUT amp"},
2879 {"Mono amp", NULL, "Mono MIX"},
2880 {"MonoP", NULL, "Mono amp"},
2881 {"MonoN", NULL, "Mono amp"},
2884 static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
2891 val = snd_soc_read(codec, RT3261_I2S1_SDP);
2892 val = (val & RT3261_I2S_IF_MASK) >> RT3261_I2S_IF_SFT;
2895 if (val == RT3261_IF_123 || val == RT3261_IF_132 ||
2896 val == RT3261_IF_113)
2897 ret |= RT3261_U_IF1;
2898 if (val == RT3261_IF_312 || val == RT3261_IF_213 ||
2899 val == RT3261_IF_113)
2900 ret |= RT3261_U_IF2;
2901 if (val == RT3261_IF_321 || val == RT3261_IF_231)
2902 ret |= RT3261_U_IF3;
2906 if (val == RT3261_IF_231 || val == RT3261_IF_213 ||
2907 val == RT3261_IF_223)
2908 ret |= RT3261_U_IF1;
2909 if (val == RT3261_IF_123 || val == RT3261_IF_321 ||
2910 val == RT3261_IF_223)
2911 ret |= RT3261_U_IF2;
2912 if (val == RT3261_IF_132 || val == RT3261_IF_312)
2913 ret |= RT3261_U_IF3;
2924 static int get_clk_info(int sclk, int rate)
2926 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
2927 struct snd_soc_codec *codec = rt3261_codec;
2928 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2930 if (sclk <= 0 || rate <= 0)
2933 if (rt3261->asrc_en)
2937 for (i = 0; i < ARRAY_SIZE(pd); i++)
2938 if (sclk == rate * pd[i])
2944 static int rt3261_hw_params(struct snd_pcm_substream *substream,
2945 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2947 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2948 struct snd_soc_codec *codec = rtd->codec;
2949 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2950 unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
2951 int pre_div, bclk_ms, frame_size;
2953 rt3261->lrck[dai->id] = params_rate(params);
2955 rt3261->lrck[dai->id] = 8000;
2956 pre_div = get_clk_info(rt3261->sysclk, rt3261->lrck[dai->id]);
2958 dev_err(codec->dev, "Unsupported clock setting\n");
2961 frame_size = snd_soc_params_to_frame_size(params);
2962 if (frame_size < 0) {
2963 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2966 bclk_ms = frame_size > 32 ? 1 : 0;
2967 rt3261->bclk[dai->id] = rt3261->lrck[dai->id] * (32 << bclk_ms);
2969 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2970 rt3261->bclk[dai->id], rt3261->lrck[dai->id]);
2971 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2972 bclk_ms, pre_div, dai->id);
2974 switch (params_format(params)) {
2975 case SNDRV_PCM_FORMAT_S16_LE:
2977 case SNDRV_PCM_FORMAT_S20_3LE:
2978 val_len |= RT3261_I2S_DL_20;
2980 case SNDRV_PCM_FORMAT_S24_LE:
2981 val_len |= RT3261_I2S_DL_24;
2983 case SNDRV_PCM_FORMAT_S8:
2984 val_len |= RT3261_I2S_DL_8;
2990 dai_sel = get_sdp_info(codec, dai->id);
2991 dai_sel |= (RT3261_U_IF1 | RT3261_U_IF2);
2993 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
2996 if (dai_sel & RT3261_U_IF1) {
2997 mask_clk = RT3261_I2S_BCLK_MS1_MASK | RT3261_I2S_PD1_MASK;
2998 val_clk = bclk_ms << RT3261_I2S_BCLK_MS1_SFT |
2999 pre_div << RT3261_I2S_PD1_SFT;
3000 snd_soc_update_bits(codec, RT3261_I2S1_SDP,
3001 RT3261_I2S_DL_MASK, val_len);
3002 //snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
3004 if (dai_sel & RT3261_U_IF2) {
3005 mask_clk |= RT3261_I2S_BCLK_MS2_MASK | RT3261_I2S_PD2_MASK;
3006 val_clk |= bclk_ms << RT3261_I2S_BCLK_MS2_SFT |
3007 pre_div << RT3261_I2S_PD2_SFT;
3008 snd_soc_update_bits(codec, RT3261_I2S2_SDP,
3009 RT3261_I2S_DL_MASK, val_len);
3010 //snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
3012 if (rt3261->asrc_en)
3013 snd_soc_write(codec, RT3261_ADDA_CLK1, 0x1114);
3015 snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
3020 static int rt3261_prepare(struct snd_pcm_substream *substream,
3021 struct snd_soc_dai *dai)
3023 struct snd_soc_pcm_runtime *rtd = substream->private_data;
3024 struct snd_soc_codec *codec = rtd->codec;
3025 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3027 rt3261->aif_pu = dai->id;
3031 static int rt3261_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3033 struct snd_soc_codec *codec = dai->codec;
3034 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3035 unsigned int reg_val = 0, dai_sel;
3037 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3038 case SND_SOC_DAIFMT_CBM_CFM:
3039 rt3261->master[dai->id] = 1;
3041 case SND_SOC_DAIFMT_CBS_CFS:
3042 reg_val |= RT3261_I2S_MS_S;
3043 rt3261->master[dai->id] = 0;
3049 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3050 case SND_SOC_DAIFMT_NB_NF:
3052 case SND_SOC_DAIFMT_IB_NF:
3053 reg_val |= RT3261_I2S_BP_INV;
3059 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3060 case SND_SOC_DAIFMT_I2S:
3062 case SND_SOC_DAIFMT_LEFT_J:
3063 reg_val |= RT3261_I2S_DF_LEFT;
3065 case SND_SOC_DAIFMT_DSP_A:
3066 reg_val |= RT3261_I2S_DF_PCM_A;
3068 case SND_SOC_DAIFMT_DSP_B:
3069 reg_val |= RT3261_I2S_DF_PCM_B;
3075 dai_sel = get_sdp_info(codec, dai->id);
3077 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
3080 if (dai_sel & RT3261_U_IF1) {
3081 snd_soc_update_bits(codec, RT3261_I2S1_SDP,
3082 RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
3083 RT3261_I2S_DF_MASK, reg_val);
3085 if (dai_sel & RT3261_U_IF2) {
3086 snd_soc_update_bits(codec, RT3261_I2S2_SDP,
3087 RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
3088 RT3261_I2S_DF_MASK, reg_val);
3094 static int rt3261_set_dai_sysclk(struct snd_soc_dai *dai,
3095 int clk_id, unsigned int freq, int dir)
3097 struct snd_soc_codec *codec = dai->codec;
3098 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3099 unsigned int reg_val = 0;
3101 if (freq == rt3261->sysclk && clk_id == rt3261->sysclk_src)
3105 case RT3261_SCLK_S_MCLK:
3106 reg_val |= RT3261_SCLK_SRC_MCLK;
3108 case RT3261_SCLK_S_PLL1:
3109 reg_val |= RT3261_SCLK_SRC_PLL1;
3111 case RT3261_SCLK_S_RCCLK:
3112 reg_val |= RT3261_SCLK_SRC_RCCLK;
3115 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3118 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3119 RT3261_SCLK_SRC_MASK, reg_val);
3120 rt3261->sysclk = freq;
3121 rt3261->sysclk_src = clk_id;
3123 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3129 * rt3261_pll_calc - Calcualte PLL M/N/K code.
3130 * @freq_in: external clock provided to codec.
3131 * @freq_out: target clock which codec works on.
3132 * @pll_code: Pointer to structure with M, N, K and bypass flag.
3134 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
3135 * which make calculation more efficiently.
3137 * Returns 0 for success or negative error code.
3139 static int rt3261_pll_calc(const unsigned int freq_in,
3140 const unsigned int freq_out, struct rt3261_pll_code *pll_code)
3142 int max_n = RT3261_PLL_N_MAX, max_m = RT3261_PLL_M_MAX;
3143 int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
3144 bool bypass = false;
3146 if (RT3261_PLL_INP_MAX < freq_in || RT3261_PLL_INP_MIN > freq_in)
3149 for (n_t = 0; n_t <= max_n; n_t++) {
3150 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
3153 if (in_t == freq_out) {
3158 for (m_t = 0; m_t <= max_m; m_t++) {
3159 out_t = in_t / (m_t + 2);
3160 red = abs(out_t - freq_out);
3170 pr_debug("Only get approximation about PLL\n");
3174 pll_code->m_bp = bypass;
3175 pll_code->m_code = m;
3176 pll_code->n_code = n;
3177 pll_code->k_code = 2;
3181 static int rt3261_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3182 unsigned int freq_in, unsigned int freq_out)
3184 struct snd_soc_codec *codec = dai->codec;
3185 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3186 struct rt3261_pll_code pll_code;
3189 if (source == rt3261->pll_src && freq_in == rt3261->pll_in &&
3190 freq_out == rt3261->pll_out)
3193 if (!freq_in || !freq_out) {
3194 dev_dbg(codec->dev, "PLL disabled\n");
3197 rt3261->pll_out = 0;
3198 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3199 RT3261_SCLK_SRC_MASK, RT3261_SCLK_SRC_MCLK);
3204 case RT3261_PLL1_S_MCLK:
3205 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3206 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_MCLK);
3208 case RT3261_PLL1_S_BCLK1:
3209 case RT3261_PLL1_S_BCLK2:
3210 dai_sel = get_sdp_info(codec, dai->id);
3213 "Failed to get sdp info: %d\n", dai_sel);
3216 if (dai_sel & RT3261_U_IF1) {
3217 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3218 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK1);
3220 if (dai_sel & RT3261_U_IF2) {
3221 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3222 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK2);
3224 if (dai_sel & RT3261_U_IF3) {
3225 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3226 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK3);
3230 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3234 ret = rt3261_pll_calc(freq_in, freq_out, &pll_code);
3236 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3240 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
3241 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
3243 snd_soc_write(codec, RT3261_PLL_CTRL1,
3244 pll_code.n_code << RT3261_PLL_N_SFT | pll_code.k_code);
3245 snd_soc_write(codec, RT3261_PLL_CTRL2,
3246 (pll_code.m_bp ? 0 : pll_code.m_code) << RT3261_PLL_M_SFT |
3247 pll_code.m_bp << RT3261_PLL_M_BP_SFT);
3249 rt3261->pll_in = freq_in;
3250 rt3261->pll_out = freq_out;
3251 rt3261->pll_src = source;
3257 * rt3261_index_show - Dump private registers.
3258 * @dev: codec device.
3259 * @attr: device attribute.
3260 * @buf: buffer for display.
3262 * To show non-zero values of all private registers.
3264 * Returns buffer length.
3266 static ssize_t rt3261_index_show(struct device *dev,
3267 struct device_attribute *attr, char *buf)
3269 struct i2c_client *client = to_i2c_client(dev);
3270 struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
3271 struct snd_soc_codec *codec = rt3261->codec;
3275 cnt += sprintf(buf, "RT3261 index register\n");
3276 for (i = 0; i < 0xb4; i++) {
3277 if (cnt + RT3261_REG_DISP_LEN >= PAGE_SIZE)
3279 val = rt3261_index_read(codec, i);
3282 cnt += snprintf(buf + cnt, RT3261_REG_DISP_LEN,
3283 "%02x: %04x\n", i, val);
3286 if (cnt >= PAGE_SIZE)
3287 cnt = PAGE_SIZE - 1;
3291 static DEVICE_ATTR(index_reg, 0444, rt3261_index_show, NULL);
3293 static int rt3261_set_bias_level(struct snd_soc_codec *codec,
3294 enum snd_soc_bias_level level)
3297 case SND_SOC_BIAS_ON:
3300 case SND_SOC_BIAS_PREPARE:
3301 snd_soc_update_bits(codec, RT3261_HP_VOL,
3302 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE); //bard 12-7
3303 snd_soc_update_bits(codec, RT3261_SPK_VOL,
3304 RT3261_L_MUTE | RT3261_R_MUTE,
3305 RT3261_L_MUTE | RT3261_R_MUTE);
3306 snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
3307 RT3261_PWR_MB1 | RT3261_PWR_MB2,
3308 RT3261_PWR_MB1 | RT3261_PWR_MB2);
3311 case SND_SOC_BIAS_STANDBY:
3312 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
3313 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3314 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3315 RT3261_PWR_BG | RT3261_PWR_VREF2,
3316 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3317 RT3261_PWR_BG | RT3261_PWR_VREF2);
3319 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3320 RT3261_PWR_FV1 | RT3261_PWR_FV2,
3321 RT3261_PWR_FV1 | RT3261_PWR_FV2);
3322 snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3701);
3323 snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
3324 RT3261_PWR_MB1 | RT3261_PWR_MB2,
3325 RT3261_PWR_MB1 | RT3261_PWR_MB2);
3326 codec->cache_only = false;
3327 codec->cache_sync = 1;
3328 snd_soc_cache_sync(codec);
3329 rt3261_index_sync(codec);
3333 case SND_SOC_BIAS_OFF:
3334 snd_soc_write(codec, RT3261_DEPOP_M1, 0x0004);
3335 snd_soc_write(codec, RT3261_DEPOP_M2, 0x1100);
3336 snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3700);
3337 snd_soc_write(codec, RT3261_PWR_DIG1, 0x0000);
3338 snd_soc_write(codec, RT3261_PWR_DIG2, 0x0000);
3339 snd_soc_write(codec, RT3261_PWR_VOL, 0x0000);
3340 snd_soc_write(codec, RT3261_PWR_MIXER, 0x0000);
3341 snd_soc_write(codec, RT3261_PWR_ANLG1, 0x0000);
3342 snd_soc_write(codec, RT3261_PWR_ANLG2, 0x0000);
3348 codec->dapm.bias_level = level;
3353 static int rt3261_proc_init(void);
3356 static int rt3261_probe(struct snd_soc_codec *codec)
3358 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3361 #if defined (CONFIG_SND_SOC_RT3224)
3362 pr_info("Codec driver version %s, in fact you choose rt3224, no dsp!\n", VERSION);
3364 pr_info("Codec driver version %s, in fact you choose rt3261 with a dsp!\n", VERSION);
3367 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
3369 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
3372 codec->write = rt3261_write;
3378 #if defined (CONFIG_SND_SOC_RT5623)
3379 struct clk *iis_clk;
3380 //for rt5623 MCLK use
3381 iis_clk = clk_get_sys("rk29_i2s.2", "i2s");
3382 if (IS_ERR(iis_clk)) {
3383 DBG("failed to get i2s clk\n");
3384 ret = PTR_ERR(iis_clk);
3386 DBG("I2S2 got i2s clk ok!\n");
3387 clk_enable(iis_clk);
3388 clk_set_rate(iis_clk, 11289600);
3389 rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME, GPIO0D_I2S2_2CH_CLK);
3394 rt3261_reset(codec);
3395 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3396 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3397 RT3261_PWR_BG | RT3261_PWR_VREF2,
3398 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3399 RT3261_PWR_BG | RT3261_PWR_VREF2);
3401 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3402 RT3261_PWR_FV1 | RT3261_PWR_FV2,
3403 RT3261_PWR_FV1 | RT3261_PWR_FV2);
3405 if (rt3261->dmic_en == RT3261_DMIC1) {
3406 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
3407 RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
3408 snd_soc_update_bits(codec, RT3261_DMIC,
3409 RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK,
3410 RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING);
3411 } else if (rt3261->dmic_en == RT3261_DMIC2) {
3412 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
3413 RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
3414 snd_soc_update_bits(codec, RT3261_DMIC,
3415 RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK,
3416 RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING);
3418 snd_soc_write(codec, RT3261_GEN_CTRL2, 0x4040);
3419 ret = snd_soc_read(codec, RT3261_VENDOR_ID);
3420 printk("read codec chip id is 0x%x\n",ret);
3422 snd_soc_update_bits(codec, RT3261_JD_CTRL,
3423 RT3261_JD1_IN4P_MASK | RT3261_JD2_IN4N_MASK,
3424 RT3261_JD1_IN4P_EN | RT3261_JD2_IN4N_EN);
3428 printk("you use an old chip, please use a new one\n");
3430 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3431 RT3261_PWR_HP_L | RT3261_PWR_HP_R,
3433 rt3261_reg_init(codec);
3434 rt3261_customer_redefine(codec, rt3261);
3436 codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
3437 rt3261->codec = codec;
3439 snd_soc_add_controls(codec, rt3261_snd_controls,
3440 ARRAY_SIZE(rt3261_snd_controls));
3441 snd_soc_dapm_new_controls(&codec->dapm, rt3261_dapm_widgets,
3442 ARRAY_SIZE(rt3261_dapm_widgets));
3443 snd_soc_dapm_add_routes(&codec->dapm, rt3261_dapm_routes,
3444 ARRAY_SIZE(rt3261_dapm_routes));
3447 #if defined (CONFIG_SND_SOC_RT3261)
3448 rt3261->dsp_sw = RT3261_DSP_AEC_NS_FENS;
3449 rt3261_dsp_probe(codec);
3453 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
3454 struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
3455 ioctl_ops->index_write = rt3261_index_write;
3456 ioctl_ops->index_read = rt3261_index_read;
3457 ioctl_ops->index_update_bits = rt3261_index_update_bits;
3458 ioctl_ops->ioctl_common = rt3261_ioctl_common;
3459 realtek_ce_init_hwdep(codec);
3464 ret = device_create_file(codec->dev, &dev_attr_index_reg);
3467 "Failed to create index_reg sysfs files: %d\n", ret);
3470 rt3261_codec = codec;
3474 static int rt3261_remove(struct snd_soc_codec *codec)
3476 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3481 static int rt3261_suspend(struct snd_soc_codec *codec, pm_message_t state)
3483 #if defined (CONFIG_SND_SOC_RT3261)
3484 /* After opening LDO of DSP, then close LDO of codec.
3485 * (1) DSP LDO power on
3486 * (2) DSP core power off
3487 * (3) DSP IIS interface power off
3488 * (4) Toggle pin of codec LDO1 to power off
3490 rt3261_dsp_suspend(codec, state);
3492 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3496 static int rt3261_resume(struct snd_soc_codec *codec)
3498 rt3261_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3499 #if defined (CONFIG_SND_SOC_RT3261)
3500 /* After opening LDO of codec, then close LDO of DSP. */
3501 rt3261_dsp_resume(codec);
3506 #define rt3261_suspend NULL
3507 #define rt3261_resume NULL
3510 #define RT3261_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3511 #define RT3261_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3512 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3514 struct snd_soc_dai_ops rt3261_aif_dai_ops = {
3515 .hw_params = rt3261_hw_params,
3516 .prepare = rt3261_prepare,
3517 .set_fmt = rt3261_set_dai_fmt,
3518 .set_sysclk = rt3261_set_dai_sysclk,
3519 .set_pll = rt3261_set_dai_pll,
3522 struct snd_soc_dai_driver rt3261_dai[] = {
3524 .name = "rt3261-aif1",
3527 .stream_name = "AIF1 Playback",
3530 .rates = RT3261_STEREO_RATES,
3531 .formats = RT3261_FORMATS,
3534 .stream_name = "AIF1 Capture",
3537 .rates = RT3261_STEREO_RATES,
3538 .formats = RT3261_FORMATS,
3540 .ops = &rt3261_aif_dai_ops,
3543 .name = "rt3261-aif2",
3546 .stream_name = "AIF2 Playback",
3549 .rates = RT3261_STEREO_RATES,
3550 .formats = RT3261_FORMATS,
3553 .stream_name = "AIF2 Capture",
3556 .rates = RT3261_STEREO_RATES,
3557 .formats = RT3261_FORMATS,
3559 .ops = &rt3261_aif_dai_ops,
3563 static struct snd_soc_codec_driver soc_codec_dev_rt3261 = {
3564 .probe = rt3261_probe,
3565 .remove = rt3261_remove,
3566 .suspend = rt3261_suspend,
3567 .resume = rt3261_resume,
3568 .write = rt3261_write,
3569 .set_bias_level = rt3261_set_bias_level,
3570 .reg_cache_size = RT3261_VENDOR_ID2 + 1,
3571 .reg_word_size = sizeof(u16),
3572 .reg_cache_default = rt3261_reg,
3573 .volatile_register = rt3261_volatile_register,
3574 .readable_register = rt3261_readable_register,
3575 .reg_cache_step = 1,
3578 static const struct i2c_device_id rt3261_i2c_id[] = {
3582 MODULE_DEVICE_TABLE(i2c, rt3261_i2c_id);
3584 static int __devinit rt3261_i2c_probe(struct i2c_client *i2c,
3585 const struct i2c_device_id *id)
3587 struct rt3261_priv *rt3261;
3589 struct rt3261_platform_data *pdata = pdata = i2c->dev.platform_data;
3591 rt3261 = kzalloc(sizeof(struct rt3261_priv), GFP_KERNEL);
3595 rt3261->codec_en_gpio = pdata->codec_en_gpio;
3596 rt3261->io_init = pdata->io_init;
3597 rt3261->spk_num = pdata->spk_num;
3598 rt3261->modem_input_mode = pdata->modem_input_mode;
3599 rt3261->lout_to_modem_mode = pdata->lout_to_modem_mode;
3600 rt3261->spk_amplify = pdata->spk_amplify;
3601 rt3261->playback_if1_data_control = pdata->playback_if1_data_control;
3602 rt3261->playback_if2_data_control = pdata->playback_if2_data_control;
3605 rt3261->io_init(pdata->codec_en_gpio, pdata->codec_en_gpio_info.iomux_name, pdata->codec_en_gpio_info.iomux_mode);
3607 #if defined (CONFIG_SND_SOC_RT5623)
3608 rt3261->modem_is_open = 0;
3611 i2c_set_clientdata(i2c, rt3261);
3612 DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
3613 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt3261,
3614 rt3261_dai, ARRAY_SIZE(rt3261_dai));
3621 static int __devexit rt3261_i2c_remove(struct i2c_client *i2c)
3623 snd_soc_unregister_codec(&i2c->dev);
3624 kfree(i2c_get_clientdata(i2c));
3628 static void rt3261_i2c_shutdown(struct i2c_client *client)
3630 struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
3631 struct snd_soc_codec *codec = rt3261->codec;
3634 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3637 struct i2c_driver rt3261_i2c_driver = {
3640 .owner = THIS_MODULE,
3642 .probe = rt3261_i2c_probe,
3643 .remove = __devexit_p(rt3261_i2c_remove),
3644 .shutdown = rt3261_i2c_shutdown,
3645 .id_table = rt3261_i2c_id,
3648 static int __init rt3261_modinit(void)
3650 return i2c_add_driver(&rt3261_i2c_driver);
3652 module_init(rt3261_modinit);
3654 static void __exit rt3261_modexit(void)
3656 i2c_del_driver(&rt3261_i2c_driver);
3658 module_exit(rt3261_modexit);
3660 MODULE_DESCRIPTION("ASoC RT3261 driver");
3661 MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
3662 MODULE_LICENSE("GPL");
3667 static ssize_t rt3261_proc_write(struct file *file, const char __user *buffer,
3668 unsigned long len, void *data)
3675 #if defined (CONFIG_SND_SOC_RT3261)
3676 struct rt3261_dsp_param param;
3679 cookie_pot = (char *)vmalloc( len );
3686 if (copy_from_user( cookie_pot, buffer, len ))
3690 switch(cookie_pot[0])
3694 printk("Read reg debug\n");
3695 if(cookie_pot[1] ==':')
3697 strsep(&cookie_pot,":");
3698 while((p=strsep(&cookie_pot,",")))
3700 reg = simple_strtol(p,NULL,16);
3701 value = rt3261_read(rt3261_codec,reg);
3702 printk("rt3261_read:0x%04x = 0x%04x\n",reg,value);
3708 printk("Error Read reg debug.\n");
3709 printk("For example: echo r:22,23,24,25>rt3261_ts\n");
3714 printk("Write reg debug\n");
3715 if(cookie_pot[1] ==':')
3717 strsep(&cookie_pot,":");
3718 while((p=strsep(&cookie_pot,"=")))
3720 reg = simple_strtol(p,NULL,16);
3721 p=strsep(&cookie_pot,",");
3722 value = simple_strtol(p,NULL,16);
3723 rt3261_write(rt3261_codec,reg,value);
3724 printk("rt3261_write:0x%04x = 0x%04x\n",reg,value);
3730 printk("Error Write reg debug.\n");
3731 printk("For example: w:22=0,23=0,24=0,25=0>rt3261_ts\n");
3735 printk("Dump rt3261 index reg \n");
3737 for (i = 0; i < 0xb4; i++)
3739 value = rt3261_index_read(rt3261_codec, i);
3740 printk("rt3261_index_read:0x%04x = 0x%04x\n",i,value);
3743 #if defined (CONFIG_SND_SOC_RT3261)
3745 param.cmd_fmt = 0x00e0;
3746 param.cmd = RT3261_DSP_CMD_MW;
3747 printk("Write dsp reg debug\n");
3748 if(cookie_pot[1] ==':')
3750 strsep(&cookie_pot,":");
3751 while((p=strsep(&cookie_pot,"=")))
3753 param.addr = simple_strtol(p,NULL,16);
3754 p=strsep(&cookie_pot,",");
3755 param.data = simple_strtol(p,NULL,16);
3756 rt3261_dsp_write(rt3261_codec,¶m);
3757 printk("rt3261_dsp_write:0x%04x = 0x%04x\n",param.addr,param.data);
3763 printk("Read dsp reg debug\n");
3764 if(cookie_pot[1] ==':')
3766 strsep(&cookie_pot,":");
3767 while((p=strsep(&cookie_pot,",")))
3769 reg = simple_strtol(p,NULL,16);
3770 value = rt3261_dsp_read(rt3261_codec,reg);
3771 printk("rt3261_dsp_read:0x%04x = 0x%04x\n",reg,value);
3778 if(cookie_pot[1] ==':')
3780 strsep(&cookie_pot,":");
3781 while((p=strsep(&cookie_pot,"=")))
3783 reg = simple_strtol(p,NULL,16);
3784 p=strsep(&cookie_pot,",");
3785 value = simple_strtol(p,NULL,16);
3786 rt3261_index_write(rt3261_codec,reg,value);
3787 printk("rt3261_index_write:0x%04x = 0x%04x\n",reg,value);
3793 if(cookie_pot[1] ==':')
3795 strsep(&cookie_pot,":");
3796 while((p=strsep(&cookie_pot,",")))
3798 reg = simple_strtol(p,NULL,16);
3799 value = rt3261_index_read(rt3261_codec,reg);
3800 printk("rt3261_index_read:0x%04x = 0x%04x\n",reg,value);
3806 printk("Help for rt3261_ts .\n-->The Cmd list: \n");
3807 printk("-->'d&&D' Open or Off the debug\n");
3808 printk("-->'r&&R' Read reg debug,Example: echo 'r:22,23,24,25'>rt3261_ts\n");
3809 printk("-->'w&&W' Write reg debug,Example: echo 'w:22=0,23=0,24=0,25=0'>rt3261_ts\n");
3816 static const struct file_operations rt3261_proc_fops = {
3817 .owner = THIS_MODULE,
3820 static int rt3261_proc_init(void)
3822 struct proc_dir_entry *rt3261_proc_entry;
3823 rt3261_proc_entry = create_proc_entry("driver/rt3261_ts", 0777, NULL);
3824 if(rt3261_proc_entry != NULL)
3826 rt3261_proc_entry->write_proc = rt3261_proc_write;
3831 printk("create proc error !\n");