2 * rt3261.c -- RT3261 ALSA SoC audio codec driver
4 * Copyright 2011 Realtek Semiconductor Corp.
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/soc-dapm.h>
25 #include <sound/initval.h>
26 #include <sound/tlv.h>
27 #include <mach/board.h>
28 #include <linux/clk.h>
29 #include <mach/iomux.h>
33 #include <linux/proc_fs.h>
34 #include <linux/seq_file.h>
35 #include <linux/vmalloc.h>
38 static struct snd_soc_codec *rt3261_codec;
41 #define DBG(x...) printk(KERN_INFO x)
48 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
49 #include "rt_codec_ioctl.h"
50 #include "rt3261_ioctl.h"
55 #if defined (CONFIG_SND_SOC_RT3261)
56 #include "rt3261-dsp.h"
59 #define RT3261_REG_RW 1 /* for debug */
60 #define RT3261_DET_EXT_MIC 0
62 #define VERSION "RT3261_V1.2.0"
64 #if defined (CONFIG_SND_SOC_RT5623)
65 extern void rt5623_on(void);
66 extern void rt5623_off(void);
69 struct rt3261_init_reg {
74 static struct rt3261_init_reg init_list[] = {
75 {RT3261_GEN_CTRL1 , 0x3701},//fa[12:13] = 1'b; fa[8~10]=1; fa[0]=1
76 {RT3261_ADDA_CLK1 , 0x1114},//73[2] = 1'b
77 {RT3261_MICBIAS , 0x3030},//93[5:4] = 11'b
78 {RT3261_CLS_D_OUT , 0xa000},//8d[11] = 0'b
79 {RT3261_CLS_D_OVCD , 0x0328},//8c[8] = 1'b
80 {RT3261_PRIV_INDEX , 0x001d},//PR1d[8] = 1'b;
81 {RT3261_PRIV_DATA , 0x0347},
82 {RT3261_PRIV_INDEX , 0x003d},//PR3d[12] = 0'b; PR3d[9] = 1'b
83 {RT3261_PRIV_DATA , 0x3600},
84 {RT3261_PRIV_INDEX , 0x0012},//PR12 = 0aa8'h
85 {RT3261_PRIV_DATA , 0x0aa8},
86 {RT3261_PRIV_INDEX , 0x0014},//PR14 = 8aaa'h
87 {RT3261_PRIV_DATA , 0x8aaa},
88 {RT3261_PRIV_INDEX , 0x0020},//PR20 = 6115'h
89 {RT3261_PRIV_DATA , 0x6115},
90 {RT3261_PRIV_INDEX , 0x0023},//PR23 = 0804'h
91 {RT3261_PRIV_DATA , 0x0804},
92 {RT3261_SPK_VOL , 0x8888},//SPKMIX -> SPKVOL
93 {RT3261_HP_VOL , 0x8888},
94 {RT3261_OUTPUT , 0x8888},//unmute OUTVOLL/R
95 {RT3261_SPO_CLSD_RATIO , 0x0001},
96 {RT3261_I2S1_SDP , 0xd000},
98 #define RT3261_INIT_REG_LEN ARRAY_SIZE(init_list)
100 static int rt3261_reg_init(struct snd_soc_codec *codec)
104 for (i = 0; i < RT3261_INIT_REG_LEN; i++)
105 snd_soc_write(codec, init_list[i].reg, init_list[i].val);
110 static int rt3261_index_sync(struct snd_soc_codec *codec)
114 for (i = 0; i < RT3261_INIT_REG_LEN; i++)
115 if (RT3261_PRIV_INDEX == init_list[i].reg ||
116 RT3261_PRIV_DATA == init_list[i].reg)
117 snd_soc_write(codec, init_list[i].reg,
122 static const u16 rt3261_reg[RT3261_VENDOR_ID2 + 1] = {
123 [RT3261_RESET] = 0x000c,
124 [RT3261_SPK_VOL] = 0xc8c8,
125 [RT3261_HP_VOL] = 0xc8c8,
126 [RT3261_OUTPUT] = 0xc8c8,
127 [RT3261_MONO_OUT] = 0x8000,
128 [RT3261_INL_INR_VOL] = 0x0808,
129 [RT3261_DAC1_DIG_VOL] = 0xafaf,
130 [RT3261_DAC2_DIG_VOL] = 0xafaf,
131 [RT3261_ADC_DIG_VOL] = 0x2f2f,
132 [RT3261_ADC_DATA] = 0x2f2f,
133 [RT3261_STO_ADC_MIXER] = 0x7060,
134 [RT3261_MONO_ADC_MIXER] = 0x7070,
135 [RT3261_AD_DA_MIXER] = 0x8080,
136 [RT3261_STO_DAC_MIXER] = 0x5454,
137 [RT3261_MONO_DAC_MIXER] = 0x5454,
138 [RT3261_DIG_MIXER] = 0xaa00,
139 [RT3261_DSP_PATH2] = 0xa000,
140 [RT3261_REC_L2_MIXER] = 0x007f,
141 [RT3261_REC_R2_MIXER] = 0x007f,
142 [RT3261_HPO_MIXER] = 0xe000,
143 [RT3261_SPK_L_MIXER] = 0x003e,
144 [RT3261_SPK_R_MIXER] = 0x003e,
145 [RT3261_SPO_L_MIXER] = 0xf800,
146 [RT3261_SPO_R_MIXER] = 0x3800,
147 [RT3261_SPO_CLSD_RATIO] = 0x0004,
148 [RT3261_MONO_MIXER] = 0xfc00,
149 [RT3261_OUT_L3_MIXER] = 0x01ff,
150 [RT3261_OUT_R3_MIXER] = 0x01ff,
151 [RT3261_LOUT_MIXER] = 0xf000,
152 [RT3261_PWR_ANLG1] = 0x00c0,
153 [RT3261_I2S1_SDP] = 0x8000,
154 [RT3261_I2S2_SDP] = 0x8000,
155 [RT3261_I2S3_SDP] = 0x8000,
156 [RT3261_ADDA_CLK1] = 0x1110,
157 [RT3261_ADDA_CLK2] = 0x0c00,
158 [RT3261_DMIC] = 0x1d00,
159 [RT3261_ASRC_3] = 0x0008,
160 [RT3261_HP_OVCD] = 0x0600,
161 [RT3261_CLS_D_OVCD] = 0x0228,
162 [RT3261_CLS_D_OUT] = 0xa800,
163 [RT3261_DEPOP_M1] = 0x0004,
164 [RT3261_DEPOP_M2] = 0x1100,
165 [RT3261_DEPOP_M3] = 0x0646,
166 [RT3261_CHARGE_PUMP] = 0x0c00,
167 [RT3261_MICBIAS] = 0x3000,
168 [RT3261_EQ_CTRL1] = 0x2080,
169 [RT3261_DRC_AGC_1] = 0x2206,
170 [RT3261_DRC_AGC_2] = 0x1f00,
171 [RT3261_ANC_CTRL1] = 0x034b,
172 [RT3261_ANC_CTRL2] = 0x0066,
173 [RT3261_ANC_CTRL3] = 0x000b,
174 [RT3261_GPIO_CTRL1] = 0x0400,
175 [RT3261_DSP_CTRL3] = 0x2000,
176 [RT3261_BASE_BACK] = 0x0013,
177 [RT3261_MP3_PLUS1] = 0x0680,
178 [RT3261_MP3_PLUS2] = 0x1c17,
179 [RT3261_3D_HP] = 0x8c00,
180 [RT3261_ADJ_HPF] = 0x2a20,
181 [RT3261_HP_CALIB_AMP_DET] = 0x0400,
182 [RT3261_SV_ZCD1] = 0x0809,
183 [RT3261_VENDOR_ID1] = 0x10ec,
184 [RT3261_VENDOR_ID2] = 0x6231,
187 static int rt3261_reset(struct snd_soc_codec *codec)
189 return snd_soc_write(codec, RT3261_RESET, 0);
192 static unsigned int rt3261_read(struct snd_soc_codec *codec,
197 val = codec->hw_read(codec, reg);
201 static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
202 unsigned int value, const void *data, int len)
206 if (!snd_soc_codec_volatile_register(codec, reg) &&
207 reg < codec->driver->reg_cache_size &&
208 !codec->cache_bypass) {
209 ret = snd_soc_cache_write(codec, reg, value);
214 if (codec->cache_only) {
215 codec->cache_sync = 1;
219 ret = i2c_master_normal_send(codec->control_data, data, len,400*1000);
228 static int rt3261_write(struct snd_soc_codec *codec, unsigned int reg,
234 data[1] = (value >> 8) & 0xff;
235 data[2] = value & 0xff;
237 DBG("rt3261_write 0x%x = 0x%x\n",reg,value);
238 return do_hw_write(codec, reg, value, data, 3);
242 * rt3261_index_write - Write private register.
243 * @codec: SoC audio codec device.
244 * @reg: Private register index.
245 * @value: Private register Data.
247 * Modify private register for advanced setting. It can be written through
248 * private index (0x6a) and data (0x6c) register.
250 * Returns 0 for success or negative error code.
252 static int rt3261_index_write(struct snd_soc_codec *codec,
253 unsigned int reg, unsigned int value)
257 ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
259 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
262 ret = snd_soc_write(codec, RT3261_PRIV_DATA, value);
264 dev_err(codec->dev, "Failed to set private value: %d\n", ret);
274 * rt3261_index_read - Read private register.
275 * @codec: SoC audio codec device.
276 * @reg: Private register index.
278 * Read advanced setting from private register. It can be read through
279 * private index (0x6a) and data (0x6c) register.
281 * Returns private register value or negative error code.
283 static unsigned int rt3261_index_read(
284 struct snd_soc_codec *codec, unsigned int reg)
288 ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
290 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
293 return snd_soc_read(codec, RT3261_PRIV_DATA);
297 * rt3261_index_update_bits - update private register bits
298 * @codec: audio codec
299 * @reg: Private register index.
300 * @mask: register mask
303 * Writes new register value.
305 * Returns 1 for change, 0 for no change, or negative error code.
307 static int rt3261_index_update_bits(struct snd_soc_codec *codec,
308 unsigned int reg, unsigned int mask, unsigned int value)
310 unsigned int old, new;
313 ret = rt3261_index_read(codec, reg);
315 dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
320 new = (old & ~mask) | (value & mask);
323 ret = rt3261_index_write(codec, reg, new);
326 "Failed to write private reg: %d\n", ret);
336 static int rt3261_volatile_register(
337 struct snd_soc_codec *codec, unsigned int reg)
341 case RT3261_PRIV_DATA:
343 case RT3261_EQ_CTRL1:
344 case RT3261_DRC_AGC_1:
345 case RT3261_ANC_CTRL1:
346 case RT3261_IRQ_CTRL2:
347 case RT3261_INT_IRQ_ST:
348 case RT3261_DSP_CTRL2:
349 case RT3261_DSP_CTRL3:
350 case RT3261_PGM_REG_ARR1:
351 case RT3261_PGM_REG_ARR3:
352 case RT3261_VENDOR_ID:
353 case RT3261_VENDOR_ID1:
354 case RT3261_VENDOR_ID2:
361 static int rt3261_readable_register(
362 struct snd_soc_codec *codec, unsigned int reg)
369 case RT3261_MONO_OUT:
372 case RT3261_INL_INR_VOL:
373 case RT3261_DAC1_DIG_VOL:
374 case RT3261_DAC2_DIG_VOL:
375 case RT3261_DAC2_CTRL:
376 case RT3261_ADC_DIG_VOL:
377 case RT3261_ADC_DATA:
378 case RT3261_ADC_BST_VOL:
379 case RT3261_STO_ADC_MIXER:
380 case RT3261_MONO_ADC_MIXER:
381 case RT3261_AD_DA_MIXER:
382 case RT3261_STO_DAC_MIXER:
383 case RT3261_MONO_DAC_MIXER:
384 case RT3261_DIG_MIXER:
385 case RT3261_DSP_PATH1:
386 case RT3261_DSP_PATH2:
387 case RT3261_DIG_INF_DATA:
388 case RT3261_REC_L1_MIXER:
389 case RT3261_REC_L2_MIXER:
390 case RT3261_REC_R1_MIXER:
391 case RT3261_REC_R2_MIXER:
392 case RT3261_HPO_MIXER:
393 case RT3261_SPK_L_MIXER:
394 case RT3261_SPK_R_MIXER:
395 case RT3261_SPO_L_MIXER:
396 case RT3261_SPO_R_MIXER:
397 case RT3261_SPO_CLSD_RATIO:
398 case RT3261_MONO_MIXER:
399 case RT3261_OUT_L1_MIXER:
400 case RT3261_OUT_L2_MIXER:
401 case RT3261_OUT_L3_MIXER:
402 case RT3261_OUT_R1_MIXER:
403 case RT3261_OUT_R2_MIXER:
404 case RT3261_OUT_R3_MIXER:
405 case RT3261_LOUT_MIXER:
406 case RT3261_PWR_DIG1:
407 case RT3261_PWR_DIG2:
408 case RT3261_PWR_ANLG1:
409 case RT3261_PWR_ANLG2:
410 case RT3261_PWR_MIXER:
412 case RT3261_PRIV_INDEX:
413 case RT3261_PRIV_DATA:
414 case RT3261_I2S1_SDP:
415 case RT3261_I2S2_SDP:
416 case RT3261_I2S3_SDP:
417 case RT3261_ADDA_CLK1:
418 case RT3261_ADDA_CLK2:
421 case RT3261_PLL_CTRL1:
422 case RT3261_PLL_CTRL2:
429 case RT3261_CLS_D_OVCD:
430 case RT3261_CLS_D_OUT:
431 case RT3261_DEPOP_M1:
432 case RT3261_DEPOP_M2:
433 case RT3261_DEPOP_M3:
434 case RT3261_CHARGE_PUMP:
435 case RT3261_PV_DET_SPK_G:
437 case RT3261_EQ_CTRL1:
438 case RT3261_EQ_CTRL2:
439 case RT3261_WIND_FILTER:
440 case RT3261_DRC_AGC_1:
441 case RT3261_DRC_AGC_2:
442 case RT3261_DRC_AGC_3:
444 case RT3261_ANC_CTRL1:
445 case RT3261_ANC_CTRL2:
446 case RT3261_ANC_CTRL3:
449 case RT3261_IRQ_CTRL1:
450 case RT3261_IRQ_CTRL2:
451 case RT3261_INT_IRQ_ST:
452 case RT3261_GPIO_CTRL1:
453 case RT3261_GPIO_CTRL2:
454 case RT3261_GPIO_CTRL3:
455 case RT3261_DSP_CTRL1:
456 case RT3261_DSP_CTRL2:
457 case RT3261_DSP_CTRL3:
458 case RT3261_DSP_CTRL4:
459 case RT3261_PGM_REG_ARR1:
460 case RT3261_PGM_REG_ARR2:
461 case RT3261_PGM_REG_ARR3:
462 case RT3261_PGM_REG_ARR4:
463 case RT3261_PGM_REG_ARR5:
464 case RT3261_SCB_FUNC:
465 case RT3261_SCB_CTRL:
466 case RT3261_BASE_BACK:
467 case RT3261_MP3_PLUS1:
468 case RT3261_MP3_PLUS2:
471 case RT3261_HP_CALIB_AMP_DET:
472 case RT3261_HP_CALIB2:
475 case RT3261_GEN_CTRL1:
476 case RT3261_GEN_CTRL2:
477 case RT3261_GEN_CTRL3:
478 case RT3261_VENDOR_ID:
479 case RT3261_VENDOR_ID1:
480 case RT3261_VENDOR_ID2:
488 * rt3261_headset_mic_detect - Detect headset.
489 * @codec: SoC audio codec device.
490 * @jack_insert: Jack insert or not.
492 * Detect whether is headset or not when jack inserted.
494 * Returns detect status.
496 int rt3261_headset_mic_detect(int jack_insert)
502 if (SND_SOC_BIAS_OFF == rt3261_codec->dapm.bias_level) {
503 snd_soc_write(rt3261_codec, RT3261_PWR_ANLG1, 0x2004);
504 snd_soc_write(rt3261_codec, RT3261_MICBIAS, 0x3830);
505 snd_soc_write(rt3261_codec, RT3261_GEN_CTRL1 , 0x3701);
507 sclk_src = snd_soc_read(rt3261_codec, RT3261_GLB_CLK) &
508 RT3261_SCLK_SRC_MASK;
509 snd_soc_update_bits(rt3261_codec, RT3261_GLB_CLK,
510 RT3261_SCLK_SRC_MASK, 0x3 << RT3261_SCLK_SRC_SFT);
511 snd_soc_update_bits(rt3261_codec, RT3261_PWR_ANLG1,
512 RT3261_PWR_LDO2, RT3261_PWR_LDO2);
513 snd_soc_update_bits(rt3261_codec, RT3261_PWR_ANLG2,
514 RT3261_PWR_MB1, RT3261_PWR_MB1);
516 snd_soc_update_bits(rt3261_codec, RT3261_MICBIAS,
517 RT3261_MIC1_OVCD_MASK | RT3261_MIC1_OVTH_MASK |
518 RT3261_PWR_CLK25M_MASK | RT3261_PWR_MB_MASK,
519 RT3261_MIC1_OVCD_EN | RT3261_MIC1_OVTH_600UA |
520 RT3261_PWR_MB_PU | RT3261_PWR_CLK25M_PU);
521 snd_soc_update_bits(rt3261_codec, RT3261_GEN_CTRL1,
524 if (snd_soc_read(rt3261_codec, RT3261_IRQ_CTRL2) & 0x8)
525 jack_type = RT3261_HEADPHO_DET;
527 jack_type = RT3261_HEADSET_DET;
528 snd_soc_update_bits(rt3261_codec, RT3261_IRQ_CTRL2,
529 RT3261_MB1_OC_CLR, 0);
530 snd_soc_update_bits(rt3261_codec, RT3261_GLB_CLK,
531 RT3261_SCLK_SRC_MASK, sclk_src);
533 snd_soc_update_bits(rt3261_codec, RT3261_MICBIAS,
534 RT3261_MIC1_OVCD_MASK,
535 RT3261_MIC1_OVCD_DIS);
537 jack_type = RT3261_NO_JACK;
542 EXPORT_SYMBOL(rt3261_headset_mic_detect);
544 static const char *rt3261_dacr2_src[] = { "TxDC_R", "TxDP_R" };
546 static const SOC_ENUM_SINGLE_DECL(rt3261_dacr2_enum,RT3261_DUMMY_PR3F,
547 14, rt3261_dacr2_src);
548 static const struct snd_kcontrol_new rt3261_dacr2_mux =
549 SOC_DAPM_ENUM("Mono dacr source", rt3261_dacr2_enum);
551 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
552 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
553 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
554 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
555 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
557 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
558 static unsigned int bst_tlv[] = {
559 TLV_DB_RANGE_HEAD(7),
560 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
561 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
562 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
563 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
564 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
565 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
566 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
569 static int rt3261_dmic_get(struct snd_kcontrol *kcontrol,
570 struct snd_ctl_elem_value *ucontrol)
572 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
573 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
575 ucontrol->value.integer.value[0] = rt3261->dmic_en;
580 static int rt3261_dmic_put(struct snd_kcontrol *kcontrol,
581 struct snd_ctl_elem_value *ucontrol)
583 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
584 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
586 if (rt3261->dmic_en == ucontrol->value.integer.value[0])
589 rt3261->dmic_en = ucontrol->value.integer.value[0];
590 switch (rt3261->dmic_en) {
591 case RT3261_DMIC_DIS:
592 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
593 RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK |
595 RT3261_GP2_PIN_GPIO2 | RT3261_GP3_PIN_GPIO3 |
596 RT3261_GP4_PIN_GPIO4);
597 snd_soc_update_bits(codec, RT3261_DMIC,
598 RT3261_DMIC_1_DP_MASK | RT3261_DMIC_2_DP_MASK,
599 RT3261_DMIC_1_DP_GPIO3 | RT3261_DMIC_2_DP_GPIO4);
600 snd_soc_update_bits(codec, RT3261_DMIC,
601 RT3261_DMIC_1_EN_MASK | RT3261_DMIC_2_EN_MASK,
602 RT3261_DMIC_1_DIS | RT3261_DMIC_2_DIS);
606 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
607 RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK,
608 RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP3_PIN_DMIC1_SDA);
609 snd_soc_update_bits(codec, RT3261_DMIC,
610 RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK |
611 RT3261_DMIC_1_DP_MASK,
612 RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING |
613 RT3261_DMIC_1_DP_IN1P);
614 snd_soc_update_bits(codec, RT3261_DMIC,
615 RT3261_DMIC_1_EN_MASK, RT3261_DMIC_1_EN);
619 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
620 RT3261_GP2_PIN_MASK | RT3261_GP4_PIN_MASK,
621 RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP4_PIN_DMIC2_SDA);
622 snd_soc_update_bits(codec, RT3261_DMIC,
623 RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK |
624 RT3261_DMIC_2_DP_MASK,
625 RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING |
626 RT3261_DMIC_2_DP_IN1N);
627 snd_soc_update_bits(codec, RT3261_DMIC,
628 RT3261_DMIC_2_EN_MASK, RT3261_DMIC_2_EN);
640 static int rt3261_mic1_get(struct snd_kcontrol *kcontrol,
641 struct snd_ctl_elem_value *ucontrol)
643 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
645 ucontrol->value.integer.value[0] =
646 (snd_soc_read(codec, RT3261_REC_L2_MIXER) & RT3261_M_BST1_RM_L) >> RT3261_M_BST1_RM_L_SFT;
651 static int rt3261_mic1_put(struct snd_kcontrol *kcontrol,
652 struct snd_ctl_elem_value *ucontrol)
654 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
656 if(ucontrol->value.integer.value[0]) {
657 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
658 RT3261_M_BST1_RM_L, 0);
659 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
660 RT3261_M_BST1_RM_R, 0);
662 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
663 RT3261_M_BST1_RM_L, RT3261_M_BST1_RM_L);
664 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
665 RT3261_M_BST1_RM_R, RT3261_M_BST1_RM_R);
671 static int rt3261_mic2_get(struct snd_kcontrol *kcontrol,
672 struct snd_ctl_elem_value *ucontrol)
674 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
676 ucontrol->value.integer.value[0] =
677 (snd_soc_read(codec, RT3261_REC_L2_MIXER) & RT3261_M_BST1_RM_L) >> RT3261_M_BST1_RM_L_SFT;
682 static int rt3261_mic2_put(struct snd_kcontrol *kcontrol,
683 struct snd_ctl_elem_value *ucontrol)
685 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
687 if(ucontrol->value.integer.value[0]) {
688 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
689 RT3261_M_BST4_RM_L, 0);
690 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
691 RT3261_M_BST4_RM_R, 0);
693 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
694 RT3261_M_BST4_RM_L, RT3261_M_BST4_RM_L);
695 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
696 RT3261_M_BST4_RM_R, RT3261_M_BST4_RM_R);
704 static int rt3261_hp_mute_get(struct snd_kcontrol *kcontrol,
705 struct snd_ctl_elem_value *ucontrol)
707 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
709 ucontrol->value.integer.value[0] =
710 !((snd_soc_read(codec, RT3261_HP_VOL) & RT3261_L_MUTE) >> RT3261_L_MUTE_SFT);
715 static int rt3261_hp_mute_put(struct snd_kcontrol *kcontrol,
716 struct snd_ctl_elem_value *ucontrol)
718 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
720 if(ucontrol->value.integer.value[0]) {
721 /* headphone unmute sequence */
722 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
723 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
724 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
725 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
726 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
727 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
728 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
729 RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
730 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
731 RT3261_RSTN_MASK, RT3261_RSTN_EN);
732 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
733 RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
734 RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
735 snd_soc_update_bits(codec, RT3261_HP_VOL,
736 RT3261_L_MUTE | RT3261_R_MUTE, 0);
738 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
739 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
740 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
741 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
743 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
744 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
746 /* headphone mute sequence */
747 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
748 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
749 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
750 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
751 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
752 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
753 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
754 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
755 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
756 RT3261_RSTP_MASK, RT3261_RSTP_EN);
757 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
758 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
759 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
760 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
761 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
762 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
764 snd_soc_update_bits(codec, RT3261_HP_VOL,
765 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
772 #if defined (CONFIG_SND_SOC_RT5623)
773 static int rt3261_modem_input_switch_get(struct snd_kcontrol *kcontrol,
774 struct snd_ctl_elem_value *ucontrol)
776 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
777 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
779 ucontrol->value.integer.value[0] = rt3261->modem_is_open;
783 static int rt3261_modem_input_switch_put(struct snd_kcontrol *kcontrol,
784 struct snd_ctl_elem_value *ucontrol)
786 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
787 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
789 if(ucontrol->value.integer.value[0]) {
791 rt3261->modem_is_open = 1;
794 rt3261->modem_is_open = 0;
801 /* IN1/IN2 Input Type */
802 static const char *rt3261_input_mode[] = {
803 "Single ended", "Differential"};
805 static const SOC_ENUM_SINGLE_DECL(
806 rt3261_in1_mode_enum, RT3261_IN1_IN2,
807 RT3261_IN_SFT1, rt3261_input_mode);
809 static const SOC_ENUM_SINGLE_DECL(
810 rt3261_in2_mode_enum, RT3261_IN3_IN4,
811 RT3261_IN_SFT2, rt3261_input_mode);
813 static const SOC_ENUM_SINGLE_DECL(
814 rt3261_in3_mode_enum, RT3261_IN1_IN2,
815 RT3261_IN_SFT2, rt3261_input_mode);
818 static const char *rt3261_output_mode[] = {
819 "Single ended", "Differential"};
821 static const SOC_ENUM_SINGLE_DECL(
822 rt3261_lout_mode_enum, RT3261_GEN_CTRL1,
823 RT3261_LOUT_DF, rt3261_output_mode);
826 /* Interface data select */
827 static const char *rt3261_data_select[] = {
828 "Normal", "left copy to right", "right copy to left", "Swap"};
830 static const SOC_ENUM_SINGLE_DECL(rt3261_if1_dac_enum, RT3261_DIG_INF_DATA,
831 RT3261_IF1_DAC_SEL_SFT, rt3261_data_select);
833 static const SOC_ENUM_SINGLE_DECL(rt3261_if1_adc_enum, RT3261_DIG_INF_DATA,
834 RT3261_IF1_ADC_SEL_SFT, rt3261_data_select);
836 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_dac_enum, RT3261_DIG_INF_DATA,
837 RT3261_IF2_DAC_SEL_SFT, rt3261_data_select);
839 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_enum, RT3261_DIG_INF_DATA,
840 RT3261_IF2_ADC_SEL_SFT, rt3261_data_select);
842 static const SOC_ENUM_SINGLE_DECL(rt3261_if3_dac_enum, RT3261_DIG_INF_DATA,
843 RT3261_IF3_DAC_SEL_SFT, rt3261_data_select);
845 static const SOC_ENUM_SINGLE_DECL(rt3261_if3_adc_enum, RT3261_DIG_INF_DATA,
846 RT3261_IF3_ADC_SEL_SFT, rt3261_data_select);
848 /* Class D speaker gain ratio */
849 static const char *rt3261_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
850 "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
852 static const SOC_ENUM_SINGLE_DECL(
853 rt3261_clsd_spk_ratio_enum, RT3261_CLS_D_OUT,
854 RT3261_CLSD_RATIO_SFT, rt3261_clsd_spk_ratio);
857 static const char *rt3261_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
859 static const SOC_ENUM_SINGLE_DECL(rt3261_dmic_enum, 0, 0, rt3261_dmic_mode);
863 static const char *rt3261_mic_mode[] = {"off", "on",};
865 static const SOC_ENUM_SINGLE_DECL(rt3261_mic_enum, 0, 0, rt3261_mic_mode);
869 static const char *rt3261_hp_mute_mode[] = {"off", "on",};
871 static const SOC_ENUM_SINGLE_DECL(rt3261_hp_mute_enum, 0, 0, rt3261_hp_mute_mode);
873 #if defined (CONFIG_SND_SOC_RT5623)
874 static const char *rt3261_modem_input_switch_mode[] = {"off", "on",};
876 static const SOC_ENUM_SINGLE_DECL(rt3261_modem_input_switch_enum, 0, 0, rt3261_modem_input_switch_mode);
880 #define REGVAL_MAX 0xffff
881 static unsigned int regctl_addr;
882 static int rt3261_regctl_info(struct snd_kcontrol *kcontrol,
883 struct snd_ctl_elem_info *uinfo)
885 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
887 uinfo->value.integer.min = 0;
888 uinfo->value.integer.max = REGVAL_MAX;
892 static int rt3261_regctl_get(struct snd_kcontrol *kcontrol,
893 struct snd_ctl_elem_value *ucontrol)
895 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
896 ucontrol->value.integer.value[0] = regctl_addr;
897 ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
901 static int rt3261_regctl_put(struct snd_kcontrol *kcontrol,
902 struct snd_ctl_elem_value *ucontrol)
904 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
905 regctl_addr = ucontrol->value.integer.value[0];
906 if(ucontrol->value.integer.value[1] <= REGVAL_MAX)
907 snd_soc_write(codec, regctl_addr, ucontrol->value.integer.value[1]);
913 static int rt3261_vol_rescale_get(struct snd_kcontrol *kcontrol,
914 struct snd_ctl_elem_value *ucontrol)
916 struct soc_mixer_control *mc =
917 (struct soc_mixer_control *)kcontrol->private_value;
918 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
919 unsigned int val = snd_soc_read(codec, mc->reg);
921 ucontrol->value.integer.value[0] = RT3261_VOL_RSCL_MAX -
922 ((val & RT3261_L_VOL_MASK) >> mc->shift);
923 ucontrol->value.integer.value[1] = RT3261_VOL_RSCL_MAX -
924 (val & RT3261_R_VOL_MASK);
929 static int rt3261_vol_rescale_put(struct snd_kcontrol *kcontrol,
930 struct snd_ctl_elem_value *ucontrol)
932 struct soc_mixer_control *mc =
933 (struct soc_mixer_control *)kcontrol->private_value;
934 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
935 unsigned int val, val2;
937 val = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[0];
938 val2 = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[1];
939 return snd_soc_update_bits_locked(codec, mc->reg, RT3261_L_VOL_MASK |
940 RT3261_R_VOL_MASK, val << mc->shift | val2);
944 static const struct snd_kcontrol_new rt3261_snd_controls[] = {
945 /* Speaker Output Volume */
946 SOC_DOUBLE("Speaker Playback Switch", RT3261_SPK_VOL,
947 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
948 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT3261_SPK_VOL,
949 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
950 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
951 SOC_DOUBLE_EXT_TLV("Earpiece Playback Volume", RT3261_SPK_VOL,
952 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
953 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
954 /* Headphone Output Volume */
955 SOC_DOUBLE("HP Playback Switch", RT3261_HP_VOL,
956 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
957 SOC_DOUBLE_EXT_TLV("Headphone Playback Volume", RT3261_HP_VOL,
958 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_HP_VOL_RSCL_RANGE, 0,
959 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
961 SOC_DOUBLE("OUT Playback Switch", RT3261_OUTPUT,
962 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
963 SOC_DOUBLE("OUT Channel Switch", RT3261_OUTPUT,
964 RT3261_VOL_L_SFT, RT3261_VOL_R_SFT, 1, 1),
965 SOC_DOUBLE_TLV("OUT Playback Volume", RT3261_OUTPUT,
966 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, 39, 1, out_vol_tlv),
967 /* MONO Output Control */
968 SOC_SINGLE("Mono Playback Switch", RT3261_MONO_OUT,
969 RT3261_L_MUTE_SFT, 1, 1),
970 /* DAC Digital Volume */
971 SOC_DOUBLE("DAC2 Playback Switch", RT3261_DAC2_CTRL,
972 RT3261_M_DAC_L2_VOL_SFT, RT3261_M_DAC_R2_VOL_SFT, 1, 1),
973 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT3261_DAC1_DIG_VOL,
974 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
975 175, 0, dac_vol_tlv),
976 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT3261_DAC2_DIG_VOL,
977 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
978 175, 0, dac_vol_tlv),
979 /* IN1/IN2 Control */
980 SOC_ENUM("IN1 Mode Control", rt3261_in1_mode_enum),
981 SOC_SINGLE_TLV("IN1 Boost", RT3261_IN1_IN2,
982 RT3261_BST_SFT1, 8, 0, bst_tlv),
983 SOC_ENUM("IN2 Mode Control", rt3261_in2_mode_enum),
984 SOC_SINGLE_TLV("IN2 Boost", RT3261_IN3_IN4,
985 RT3261_BST_SFT2, 8, 0, bst_tlv),
986 SOC_ENUM("IN3 Mode Control", rt3261_in3_mode_enum),
987 SOC_SINGLE_TLV("IN3 Boost", RT3261_IN1_IN2,
988 RT3261_BST_SFT2, 8, 0, bst_tlv),
990 SOC_ENUM("LOUT Mode Control", rt3261_lout_mode_enum),
991 /* INL/INR Volume Control */
992 SOC_DOUBLE_TLV("IN Capture Volume", RT3261_INL_INR_VOL,
993 RT3261_INL_VOL_SFT, RT3261_INR_VOL_SFT,
995 /* ADC Digital Volume Control */
996 SOC_DOUBLE("ADC Capture Switch", RT3261_ADC_DIG_VOL,
997 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
998 SOC_DOUBLE_TLV("ADC Capture Volume", RT3261_ADC_DIG_VOL,
999 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1000 127, 0, adc_vol_tlv),
1001 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT3261_ADC_DATA,
1002 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1003 127, 0, adc_vol_tlv),
1004 /* ADC Boost Volume Control */
1005 SOC_DOUBLE_TLV("ADC Boost Gain", RT3261_ADC_BST_VOL,
1006 RT3261_ADC_L_BST_SFT, RT3261_ADC_R_BST_SFT,
1008 /* Class D speaker gain ratio */
1009 SOC_ENUM("Class D SPK Ratio Control", rt3261_clsd_spk_ratio_enum),
1011 SOC_ENUM_EXT("DMIC Switch", rt3261_dmic_enum,
1012 rt3261_dmic_get, rt3261_dmic_put),
1014 #ifdef RT3261_REG_RW
1016 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1017 .name = "Register Control",
1018 .info = rt3261_regctl_info,
1019 .get = rt3261_regctl_get,
1020 .put = rt3261_regctl_put,
1025 SOC_SINGLE_TLV("Main Mic Capture Volume", RT3261_IN1_IN2,
1026 RT3261_BST_SFT1, 8, 0, bst_tlv),
1027 SOC_SINGLE_TLV("Headset Mic Capture Volume", RT3261_IN3_IN4,
1028 RT3261_BST_SFT2, 8, 0, bst_tlv),
1029 SOC_ENUM_EXT("Main Mic Capture Switch", rt3261_mic_enum,
1030 rt3261_mic1_get, rt3261_mic1_put),
1031 SOC_ENUM_EXT("Headset Mic Capture Switch", rt3261_mic_enum,
1032 rt3261_mic2_get, rt3261_mic2_put),
1036 SOC_ENUM_EXT("HP mute Switch", rt3261_hp_mute_enum,
1037 rt3261_hp_mute_get, rt3261_hp_mute_put),
1039 #if defined (CONFIG_SND_SOC_RT5623)
1040 SOC_ENUM_EXT("Modem Input Switch", rt3261_modem_input_switch_enum,
1041 rt3261_modem_input_switch_get, rt3261_modem_input_switch_put),
1046 * set_dmic_clk - Set parameter of dmic.
1049 * @kcontrol: The kcontrol of this widget.
1052 * Choose dmic clock between 1MHz and 3MHz.
1053 * It is better for clock to approximate 3MHz.
1055 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1056 struct snd_kcontrol *kcontrol, int event)
1058 struct snd_soc_codec *codec = w->codec;
1059 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
1060 int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
1062 rate = rt3261->lrck[rt3261->aif_pu] << 8;
1064 for (i = 0; i < ARRAY_SIZE(div); i++) {
1065 bound = div[i] * 3000000;
1068 temp = bound - rate;
1075 dev_err(codec->dev, "Failed to set DMIC clock\n");
1077 snd_soc_update_bits(codec, RT3261_DMIC, RT3261_DMIC_CLK_MASK,
1078 idx << RT3261_DMIC_CLK_SFT);
1082 static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
1083 struct snd_soc_dapm_widget *sink)
1087 val = snd_soc_read(source->codec, RT3261_GLB_CLK);
1088 val &= RT3261_SCLK_SRC_MASK;
1089 if (val == RT3261_SCLK_SRC_PLL1)
1096 static const struct snd_kcontrol_new rt3261_sto_adc_l_mix[] = {
1097 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
1098 RT3261_M_ADC_L1_SFT, 1, 1),
1099 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
1100 RT3261_M_ADC_L2_SFT, 1, 1),
1103 static const struct snd_kcontrol_new rt3261_sto_adc_r_mix[] = {
1104 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
1105 RT3261_M_ADC_R1_SFT, 1, 1),
1106 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
1107 RT3261_M_ADC_R2_SFT, 1, 1),
1110 static const struct snd_kcontrol_new rt3261_mono_adc_l_mix[] = {
1111 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
1112 RT3261_M_MONO_ADC_L1_SFT, 1, 1),
1113 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
1114 RT3261_M_MONO_ADC_L2_SFT, 1, 1),
1117 static const struct snd_kcontrol_new rt3261_mono_adc_r_mix[] = {
1118 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
1119 RT3261_M_MONO_ADC_R1_SFT, 1, 1),
1120 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
1121 RT3261_M_MONO_ADC_R2_SFT, 1, 1),
1124 static const struct snd_kcontrol_new rt3261_dac_l_mix[] = {
1125 SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
1126 RT3261_M_ADCMIX_L_SFT, 1, 1),
1127 SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
1128 RT3261_M_IF1_DAC_L_SFT, 1, 1),
1131 static const struct snd_kcontrol_new rt3261_dac_r_mix[] = {
1132 SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
1133 RT3261_M_ADCMIX_R_SFT, 1, 1),
1134 SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
1135 RT3261_M_IF1_DAC_R_SFT, 1, 1),
1138 static const struct snd_kcontrol_new rt3261_sto_dac_l_mix[] = {
1139 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_STO_DAC_MIXER,
1140 RT3261_M_DAC_L1_SFT, 1, 1),
1141 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_STO_DAC_MIXER,
1142 RT3261_M_DAC_L2_SFT, 1, 1),
1143 SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
1144 RT3261_M_ANC_DAC_L_SFT, 1, 1),
1147 static const struct snd_kcontrol_new rt3261_sto_dac_r_mix[] = {
1148 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_STO_DAC_MIXER,
1149 RT3261_M_DAC_R1_SFT, 1, 1),
1150 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_STO_DAC_MIXER,
1151 RT3261_M_DAC_R2_SFT, 1, 1),
1152 SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
1153 RT3261_M_ANC_DAC_R_SFT, 1, 1),
1156 static const struct snd_kcontrol_new rt3261_mono_dac_l_mix[] = {
1157 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_MONO_DAC_MIXER,
1158 RT3261_M_DAC_L1_MONO_L_SFT, 1, 1),
1159 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
1160 RT3261_M_DAC_L2_MONO_L_SFT, 1, 1),
1161 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
1162 RT3261_M_DAC_R2_MONO_L_SFT, 1, 1),
1165 static const struct snd_kcontrol_new rt3261_mono_dac_r_mix[] = {
1166 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_MONO_DAC_MIXER,
1167 RT3261_M_DAC_R1_MONO_R_SFT, 1, 1),
1168 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
1169 RT3261_M_DAC_R2_MONO_R_SFT, 1, 1),
1170 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
1171 RT3261_M_DAC_L2_MONO_R_SFT, 1, 1),
1174 static const struct snd_kcontrol_new rt3261_dig_l_mix[] = {
1175 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_DIG_MIXER,
1176 RT3261_M_STO_L_DAC_L_SFT, 1, 1),
1177 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_DIG_MIXER,
1178 RT3261_M_DAC_L2_DAC_L_SFT, 1, 1),
1181 static const struct snd_kcontrol_new rt3261_dig_r_mix[] = {
1182 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_DIG_MIXER,
1183 RT3261_M_STO_R_DAC_R_SFT, 1, 1),
1184 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_DIG_MIXER,
1185 RT3261_M_DAC_R2_DAC_R_SFT, 1, 1),
1188 /* Analog Input Mixer */
1189 static const struct snd_kcontrol_new rt3261_rec_l_mix[] = {
1190 SOC_DAPM_SINGLE("HPOL Switch", RT3261_REC_L2_MIXER,
1191 RT3261_M_HP_L_RM_L_SFT, 1, 1),
1192 SOC_DAPM_SINGLE("INL Switch", RT3261_REC_L2_MIXER,
1193 RT3261_M_IN_L_RM_L_SFT, 1, 1),
1194 SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_L2_MIXER,
1195 RT3261_M_BST2_RM_L, 1, 1),
1196 SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_L2_MIXER,
1197 RT3261_M_BST4_RM_L_SFT, 1, 1),
1198 SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_L2_MIXER,
1199 RT3261_M_BST1_RM_L_SFT, 1, 1),
1200 SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_REC_L2_MIXER,
1201 RT3261_M_OM_L_RM_L_SFT, 1, 1),
1204 static const struct snd_kcontrol_new rt3261_rec_r_mix[] = {
1205 SOC_DAPM_SINGLE("HPOR Switch", RT3261_REC_R2_MIXER,
1206 RT3261_M_HP_R_RM_R_SFT, 1, 1),
1207 SOC_DAPM_SINGLE("INR Switch", RT3261_REC_R2_MIXER,
1208 RT3261_M_IN_R_RM_R_SFT, 1, 1),
1209 SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_R2_MIXER,
1210 RT3261_M_BST2_RM_R_SFT, 1, 1),
1211 SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_R2_MIXER,
1212 RT3261_M_BST4_RM_R_SFT, 1, 1),
1213 SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_R2_MIXER,
1214 RT3261_M_BST1_RM_R_SFT, 1, 1),
1215 SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_REC_R2_MIXER,
1216 RT3261_M_OM_R_RM_R_SFT, 1, 1),
1219 /* Analog Output Mixer */
1220 static const struct snd_kcontrol_new rt3261_spk_l_mix[] = {
1221 SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_SPK_L_MIXER,
1222 RT3261_M_RM_L_SM_L_SFT, 1, 1),
1223 SOC_DAPM_SINGLE("INL Switch", RT3261_SPK_L_MIXER,
1224 RT3261_M_IN_L_SM_L_SFT, 1, 1),
1225 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPK_L_MIXER,
1226 RT3261_M_DAC_L1_SM_L_SFT, 1, 1),
1227 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_SPK_L_MIXER,
1228 RT3261_M_DAC_L2_SM_L_SFT, 1, 1),
1229 SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_SPK_L_MIXER,
1230 RT3261_M_OM_L_SM_L_SFT, 1, 1),
1233 static const struct snd_kcontrol_new rt3261_spk_r_mix[] = {
1234 SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_SPK_R_MIXER,
1235 RT3261_M_RM_R_SM_R_SFT, 1, 1),
1236 SOC_DAPM_SINGLE("INR Switch", RT3261_SPK_R_MIXER,
1237 RT3261_M_IN_R_SM_R_SFT, 1, 1),
1238 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPK_R_MIXER,
1239 RT3261_M_DAC_R1_SM_R_SFT, 1, 1),
1240 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_SPK_R_MIXER,
1241 RT3261_M_DAC_R2_SM_R_SFT, 1, 1),
1242 SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_SPK_R_MIXER,
1243 RT3261_M_OM_R_SM_R_SFT, 1, 1),
1246 static const struct snd_kcontrol_new rt3261_out_l_mix[] = {
1247 SOC_DAPM_SINGLE("SPK MIXL Switch", RT3261_OUT_L3_MIXER,
1248 RT3261_M_SM_L_OM_L_SFT, 1, 1),
1249 SOC_DAPM_SINGLE("BST3 Switch", RT3261_OUT_L3_MIXER,
1250 RT3261_M_BST2_OM_L_SFT, 1, 1),
1251 SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_L3_MIXER,
1252 RT3261_M_BST1_OM_L_SFT, 1, 1),
1253 SOC_DAPM_SINGLE("INL Switch", RT3261_OUT_L3_MIXER,
1254 RT3261_M_IN_L_OM_L_SFT, 1, 1),
1255 SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_OUT_L3_MIXER,
1256 RT3261_M_RM_L_OM_L_SFT, 1, 1),
1257 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_L3_MIXER,
1258 RT3261_M_DAC_R2_OM_L_SFT, 1, 1),
1259 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_L3_MIXER,
1260 RT3261_M_DAC_L2_OM_L_SFT, 1, 1),
1261 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_OUT_L3_MIXER,
1262 RT3261_M_DAC_L1_OM_L_SFT, 1, 1),
1265 static const struct snd_kcontrol_new rt3261_out_r_mix[] = {
1266 SOC_DAPM_SINGLE("SPK MIXR Switch", RT3261_OUT_R3_MIXER,
1267 RT3261_M_SM_L_OM_R_SFT, 1, 1),
1268 SOC_DAPM_SINGLE("BST3 Switch", RT3261_OUT_R3_MIXER,
1269 RT3261_M_BST2_OM_R_SFT, 1, 1),
1270 SOC_DAPM_SINGLE("BST2 Switch", RT3261_OUT_R3_MIXER,
1271 RT3261_M_BST4_OM_R_SFT, 1, 1),
1272 SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_R3_MIXER,
1273 RT3261_M_BST1_OM_R_SFT, 1, 1),
1274 SOC_DAPM_SINGLE("INR Switch", RT3261_OUT_R3_MIXER,
1275 RT3261_M_IN_R_OM_R_SFT, 1, 1),
1276 SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_OUT_R3_MIXER,
1277 RT3261_M_RM_R_OM_R_SFT, 1, 1),
1278 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_R3_MIXER,
1279 RT3261_M_DAC_L2_OM_R_SFT, 1, 1),
1280 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_R3_MIXER,
1281 RT3261_M_DAC_R2_OM_R_SFT, 1, 1),
1282 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_OUT_R3_MIXER,
1283 RT3261_M_DAC_R1_OM_R_SFT, 1, 1),
1286 static const struct snd_kcontrol_new rt3261_spo_l_mix[] = {
1288 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
1289 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1290 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
1291 RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
1293 SOC_DAPM_SINGLE("DAC Switch", RT3261_DUMMY_SPKMIXER,
1294 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1296 SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_L_MIXER,
1297 RT3261_M_SV_R_SPM_L_SFT, 1, 1),
1298 SOC_DAPM_SINGLE("SPKVOL L Switch", RT3261_SPO_L_MIXER,
1299 RT3261_M_SV_L_SPM_L_SFT, 1, 1),
1300 SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_L_MIXER,
1301 RT3261_M_BST1_SPM_L_SFT, 1, 1),
1304 static const struct snd_kcontrol_new rt3261_spo_dac_mix[] = {
1305 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
1306 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1307 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
1308 RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
1312 static const struct snd_kcontrol_new rt3261_spo_r_mix[] = {
1313 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_R_MIXER,
1314 RT3261_M_DAC_R1_SPM_R_SFT, 1, 1),
1315 SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_R_MIXER,
1316 RT3261_M_SV_R_SPM_R_SFT, 1, 1),
1317 SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_R_MIXER,
1318 RT3261_M_BST1_SPM_R_SFT, 1, 1),
1321 static const struct snd_kcontrol_new rt3261_hpo_mix[] = {
1322 SOC_DAPM_SINGLE("DAC2 Switch", RT3261_HPO_MIXER,
1323 RT3261_M_DAC2_HM_SFT, 1, 1),
1324 SOC_DAPM_SINGLE("DAC1 Switch", RT3261_HPO_MIXER,
1325 RT3261_M_DAC1_HM_SFT, 1, 1),
1326 SOC_DAPM_SINGLE("HPVOL Switch", RT3261_HPO_MIXER,
1327 RT3261_M_HPVOL_HM_SFT, 1, 1),
1330 static const struct snd_kcontrol_new rt3261_lout_mix[] = {
1331 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_LOUT_MIXER,
1332 RT3261_M_DAC_L1_LM_SFT, 1, 1),
1333 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_LOUT_MIXER,
1334 RT3261_M_DAC_R1_LM_SFT, 1, 1),
1335 SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_LOUT_MIXER,
1336 RT3261_M_OV_L_LM_SFT, 1, 1),
1337 SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_LOUT_MIXER,
1338 RT3261_M_OV_R_LM_SFT, 1, 1),
1341 static const struct snd_kcontrol_new rt3261_mono_mix[] = {
1342 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_MIXER,
1343 RT3261_M_DAC_R2_MM_SFT, 1, 1),
1344 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_MIXER,
1345 RT3261_M_DAC_L2_MM_SFT, 1, 1),
1346 SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_MONO_MIXER,
1347 RT3261_M_OV_R_MM_SFT, 1, 1),
1348 SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_MONO_MIXER,
1349 RT3261_M_OV_L_MM_SFT, 1, 1),
1350 SOC_DAPM_SINGLE("BST1 Switch", RT3261_MONO_MIXER,
1351 RT3261_M_BST1_MM_SFT, 1, 1),
1355 static const char *rt3261_inl_src[] = {"IN2P", "MonoP"};
1357 static const SOC_ENUM_SINGLE_DECL(
1358 rt3261_inl_enum, RT3261_INL_INR_VOL,
1359 RT3261_INL_SEL_SFT, rt3261_inl_src);
1361 static const struct snd_kcontrol_new rt3261_inl_mux =
1362 SOC_DAPM_ENUM("INL source", rt3261_inl_enum);
1364 static const char *rt3261_inr_src[] = {"IN2N", "MonoN"};
1366 static const SOC_ENUM_SINGLE_DECL(
1367 rt3261_inr_enum, RT3261_INL_INR_VOL,
1368 RT3261_INR_SEL_SFT, rt3261_inr_src);
1370 static const struct snd_kcontrol_new rt3261_inr_mux =
1371 SOC_DAPM_ENUM("INR source", rt3261_inr_enum);
1373 /* Stereo ADC source */
1374 static const char *rt3261_stereo_adc1_src[] = {"DIG MIX", "ADC"};
1376 static const SOC_ENUM_SINGLE_DECL(
1377 rt3261_stereo_adc1_enum, RT3261_STO_ADC_MIXER,
1378 RT3261_ADC_1_SRC_SFT, rt3261_stereo_adc1_src);
1380 static const struct snd_kcontrol_new rt3261_sto_adc_l1_mux =
1381 SOC_DAPM_ENUM("Stereo ADC L1 source", rt3261_stereo_adc1_enum);
1383 static const struct snd_kcontrol_new rt3261_sto_adc_r1_mux =
1384 SOC_DAPM_ENUM("Stereo ADC R1 source", rt3261_stereo_adc1_enum);
1386 static const char *rt3261_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
1388 static const SOC_ENUM_SINGLE_DECL(
1389 rt3261_stereo_adc2_enum, RT3261_STO_ADC_MIXER,
1390 RT3261_ADC_2_SRC_SFT, rt3261_stereo_adc2_src);
1392 static const struct snd_kcontrol_new rt3261_sto_adc_l2_mux =
1393 SOC_DAPM_ENUM("Stereo ADC L2 source", rt3261_stereo_adc2_enum);
1395 static const struct snd_kcontrol_new rt3261_sto_adc_r2_mux =
1396 SOC_DAPM_ENUM("Stereo ADC R2 source", rt3261_stereo_adc2_enum);
1398 /* Mono ADC source */
1399 static const char *rt3261_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
1401 static const SOC_ENUM_SINGLE_DECL(
1402 rt3261_mono_adc_l1_enum, RT3261_MONO_ADC_MIXER,
1403 RT3261_MONO_ADC_L1_SRC_SFT, rt3261_mono_adc_l1_src);
1405 static const struct snd_kcontrol_new rt3261_mono_adc_l1_mux =
1406 SOC_DAPM_ENUM("Mono ADC1 left source", rt3261_mono_adc_l1_enum);
1408 static const char *rt3261_mono_adc_l2_src[] =
1409 {"DMIC L1", "DMIC L2", "Mono DAC MIXL"};
1411 static const SOC_ENUM_SINGLE_DECL(
1412 rt3261_mono_adc_l2_enum, RT3261_MONO_ADC_MIXER,
1413 RT3261_MONO_ADC_L2_SRC_SFT, rt3261_mono_adc_l2_src);
1415 static const struct snd_kcontrol_new rt3261_mono_adc_l2_mux =
1416 SOC_DAPM_ENUM("Mono ADC2 left source", rt3261_mono_adc_l2_enum);
1418 static const char *rt3261_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
1420 static const SOC_ENUM_SINGLE_DECL(
1421 rt3261_mono_adc_r1_enum, RT3261_MONO_ADC_MIXER,
1422 RT3261_MONO_ADC_R1_SRC_SFT, rt3261_mono_adc_r1_src);
1424 static const struct snd_kcontrol_new rt3261_mono_adc_r1_mux =
1425 SOC_DAPM_ENUM("Mono ADC1 right source", rt3261_mono_adc_r1_enum);
1427 static const char *rt3261_mono_adc_r2_src[] =
1428 {"DMIC R1", "DMIC R2", "Mono DAC MIXR"};
1430 static const SOC_ENUM_SINGLE_DECL(
1431 rt3261_mono_adc_r2_enum, RT3261_MONO_ADC_MIXER,
1432 RT3261_MONO_ADC_R2_SRC_SFT, rt3261_mono_adc_r2_src);
1434 static const struct snd_kcontrol_new rt3261_mono_adc_r2_mux =
1435 SOC_DAPM_ENUM("Mono ADC2 right source", rt3261_mono_adc_r2_enum);
1437 /* DAC2 channel source */
1438 static const char *rt3261_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
1440 static const SOC_ENUM_SINGLE_DECL(rt3261_dac_l2_enum, RT3261_DSP_PATH2,
1441 RT3261_DAC_L2_SEL_SFT, rt3261_dac_l2_src);
1443 static const struct snd_kcontrol_new rt3261_dac_l2_mux =
1444 SOC_DAPM_ENUM("DAC2 left channel source", rt3261_dac_l2_enum);
1446 static const char *rt3261_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
1448 static const SOC_ENUM_SINGLE_DECL(
1449 rt3261_dac_r2_enum, RT3261_DSP_PATH2,
1450 RT3261_DAC_R2_SEL_SFT, rt3261_dac_r2_src);
1452 static const struct snd_kcontrol_new rt3261_dac_r2_mux =
1453 SOC_DAPM_ENUM("DAC2 right channel source", rt3261_dac_r2_enum);
1455 /* Interface 2 ADC channel source */
1456 static const char *rt3261_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
1458 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_l_enum, RT3261_DSP_PATH2,
1459 RT3261_IF2_ADC_L_SEL_SFT, rt3261_if2_adc_l_src);
1461 static const struct snd_kcontrol_new rt3261_if2_adc_l_mux =
1462 SOC_DAPM_ENUM("IF2 ADC left channel source", rt3261_if2_adc_l_enum);
1464 static const char *rt3261_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
1466 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_r_enum, RT3261_DSP_PATH2,
1467 RT3261_IF2_ADC_R_SEL_SFT, rt3261_if2_adc_r_src);
1469 static const struct snd_kcontrol_new rt3261_if2_adc_r_mux =
1470 SOC_DAPM_ENUM("IF2 ADC right channel source", rt3261_if2_adc_r_enum);
1472 /* digital interface and iis interface map */
1473 static const char *rt3261_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
1474 "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
1475 "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
1477 static const SOC_ENUM_SINGLE_DECL(
1478 rt3261_dai_iis_map_enum, RT3261_I2S1_SDP,
1479 RT3261_I2S_IF_SFT, rt3261_dai_iis_map);
1481 static const struct snd_kcontrol_new rt3261_dai_mux =
1482 SOC_DAPM_ENUM("DAI select", rt3261_dai_iis_map_enum);
1485 static const char *rt3261_sdi_sel[] = {"IF1", "IF2"};
1487 static const SOC_ENUM_SINGLE_DECL(
1488 rt3261_sdi_sel_enum, RT3261_I2S2_SDP,
1489 RT3261_I2S2_SDI_SFT, rt3261_sdi_sel);
1491 static const struct snd_kcontrol_new rt3261_sdi_mux =
1492 SOC_DAPM_ENUM("SDI select", rt3261_sdi_sel_enum);
1494 static int rt3261_adc_event(struct snd_soc_dapm_widget *w,
1495 struct snd_kcontrol *kcontrol, int event)
1497 struct snd_soc_codec *codec = w->codec;
1498 unsigned int val, mask;
1501 case SND_SOC_DAPM_POST_PMU:
1502 //rt3261_index_update_bits(codec,
1503 // RT3261_CHOP_DAC_ADC, 0x1000, 0x1000);
1504 val = snd_soc_read(codec, RT3261_MONO_ADC_MIXER);
1505 mask = RT3261_M_MONO_ADC_L1 | RT3261_M_MONO_ADC_L2 |
1506 RT3261_M_MONO_ADC_R1 | RT3261_M_MONO_ADC_R2;
1507 if ((val & mask) ^ mask)
1508 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1509 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R, 0);
1512 case SND_SOC_DAPM_POST_PMD:
1513 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1514 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R,
1515 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R);
1516 //rt3261_index_update_bits(codec,
1517 // RT3261_CHOP_DAC_ADC, 0x1000, 0x0000);
1527 static int rt3261_spk_event(struct snd_soc_dapm_widget *w,
1528 struct snd_kcontrol *kcontrol, int event)
1530 struct snd_soc_codec *codec = w->codec;
1534 case SND_SOC_DAPM_POST_PMU:
1536 val = snd_soc_read(codec, RT3261_PWR_DIG1);
1537 if(val & (RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1)) {
1538 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1539 RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1,
1540 RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1);
1543 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1544 RT3261_PWR_CLS_D, RT3261_PWR_CLS_D);
1545 rt3261_index_update_bits(codec,
1546 RT3261_CLSD_INT_REG1, 0xf000, 0xf000);
1547 snd_soc_update_bits(codec, RT3261_SPK_VOL,
1548 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1551 case SND_SOC_DAPM_PRE_PMD:
1552 snd_soc_update_bits(codec, RT3261_SPK_VOL,
1553 RT3261_L_MUTE | RT3261_R_MUTE,
1554 RT3261_L_MUTE | RT3261_R_MUTE);
1555 rt3261_index_update_bits(codec,
1556 RT3261_CLSD_INT_REG1, 0xf000, 0x0000);
1557 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1558 RT3261_PWR_CLS_D, 0);
1568 void hp_amp_power(struct snd_soc_codec *codec, int on)
1570 static int hp_amp_power_count;
1571 printk("hp_amp_power on=%d hp_amp_power_count=%d\n",on,hp_amp_power_count);
1574 if(hp_amp_power_count <= 0) {
1575 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1576 RT3261_PWR_I2S1, RT3261_PWR_I2S1);
1577 /* depop parameters */
1578 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
1579 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
1580 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1581 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1582 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
1583 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
1584 /* headphone amp power on */
1585 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1586 RT3261_PWR_FV1 | RT3261_PWR_FV2 , 0);
1587 snd_soc_update_bits(codec, RT3261_PWR_VOL,
1588 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
1589 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
1590 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1591 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA | RT3261_PWR_LM,
1592 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA | RT3261_PWR_LM);
1594 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1595 RT3261_PWR_FV1 | RT3261_PWR_FV2,
1596 RT3261_PWR_FV1 | RT3261_PWR_FV2);
1598 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
1599 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
1600 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
1601 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1602 RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
1603 RT3261_HP_CO_EN | RT3261_HP_SG_EN);
1605 hp_amp_power_count++;
1607 hp_amp_power_count--;
1608 if(hp_amp_power_count <= 0) {
1609 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
1610 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1611 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
1612 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
1613 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
1614 /* headphone amp power down */
1615 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1616 RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
1617 RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
1618 RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1619 RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
1620 RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
1621 RT3261_HP_SG_EN | RT3261_HP_CB_PD);
1622 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1623 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA | RT3261_PWR_LM,
1630 static void rt3261_pmu_depop(struct snd_soc_codec *codec)
1633 /* depop parameters */
1634 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
1635 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
1636 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1637 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1638 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
1639 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
1640 /* headphone amp power on */
1641 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1642 RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
1643 snd_soc_update_bits(codec, RT3261_PWR_VOL,
1644 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
1645 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
1646 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1647 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1648 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
1650 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1651 RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
1652 RT3261_PWR_HP_R | RT3261_PWR_HA,
1653 RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
1654 RT3261_PWR_HP_R | RT3261_PWR_HA);
1655 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
1656 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
1657 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
1658 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1659 RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
1660 RT3261_HP_CO_EN | RT3261_HP_SG_EN);
1662 hp_amp_power(codec, 1);
1664 /* headphone unmute sequence */
1665 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
1666 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
1667 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
1668 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
1669 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
1670 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
1671 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1672 RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
1673 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1674 RT3261_RSTN_MASK, RT3261_RSTN_EN);
1675 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1676 RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
1677 RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
1678 snd_soc_update_bits(codec, RT3261_HP_VOL,
1679 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1681 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1682 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
1683 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
1684 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
1686 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
1687 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
1690 static void rt3261_pmd_depop(struct snd_soc_codec *codec)
1692 /* headphone mute sequence */
1693 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
1694 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
1695 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
1696 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
1697 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
1698 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
1699 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1700 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
1701 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1702 RT3261_RSTP_MASK, RT3261_RSTP_EN);
1703 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1704 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
1705 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
1706 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
1707 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
1708 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
1710 snd_soc_update_bits(codec, RT3261_HP_VOL,
1711 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
1714 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
1715 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1716 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
1717 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
1718 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
1719 /* headphone amp power down */
1720 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1721 RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
1722 RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
1723 RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1724 RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
1725 RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
1726 RT3261_HP_SG_EN | RT3261_HP_CB_PD);
1727 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1728 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1731 hp_amp_power(codec, 0);
1735 static void rt3261_pmu_depop(struct snd_soc_codec *codec)
1737 /* depop parameters */
1738 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
1739 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
1740 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1741 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1742 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
1743 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
1744 /* headphone amp power on */
1745 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1746 RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
1747 snd_soc_update_bits(codec, RT3261_PWR_VOL,
1748 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
1749 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
1750 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1751 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1752 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
1754 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1755 RT3261_PWR_FV1 | RT3261_PWR_FV2 ,
1756 RT3261_PWR_FV1 | RT3261_PWR_FV2 );
1757 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
1758 /* headphone unmute sequence */
1759 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
1760 RT3261_DEPOP_MASK | RT3261_DIG_DP_MASK,
1761 RT3261_DEPOP_AUTO | RT3261_DIG_DP_EN);
1762 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
1763 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
1764 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
1765 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
1766 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
1767 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
1768 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
1769 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1770 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK,
1771 RT3261_HP_CP_PD | RT3261_HP_SG_EN);
1773 snd_soc_update_bits(codec, RT3261_HP_VOL,
1774 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1776 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
1777 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
1780 static void rt3261_pmd_depop(struct snd_soc_codec *codec)
1782 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
1783 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
1784 snd_soc_update_bits(codec, RT3261_HP_VOL,
1785 RT3261_L_MUTE | RT3261_R_MUTE,
1786 RT3261_L_MUTE | RT3261_R_MUTE);
1788 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1789 RT3261_HP_CB_MASK, RT3261_HP_CB_PD);
1791 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
1792 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1793 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1798 static int rt3261_hp_event(struct snd_soc_dapm_widget *w,
1799 struct snd_kcontrol *kcontrol, int event)
1801 struct snd_soc_codec *codec = w->codec;
1804 case SND_SOC_DAPM_POST_PMU:
1805 rt3261_pmu_depop(codec);
1808 case SND_SOC_DAPM_PRE_PMD:
1809 rt3261_pmd_depop(codec);
1819 static int rt3261_mono_event(struct snd_soc_dapm_widget *w,
1820 struct snd_kcontrol *kcontrol, int event)
1822 struct snd_soc_codec *codec = w->codec;
1825 case SND_SOC_DAPM_POST_PMU:
1826 snd_soc_update_bits(codec, RT3261_MONO_OUT,
1830 case SND_SOC_DAPM_PRE_PMD:
1831 snd_soc_update_bits(codec, RT3261_MONO_OUT,
1832 RT3261_L_MUTE, RT3261_L_MUTE);
1842 static int rt3261_lout_event(struct snd_soc_dapm_widget *w,
1843 struct snd_kcontrol *kcontrol, int event)
1845 struct snd_soc_codec *codec = w->codec;
1848 case SND_SOC_DAPM_POST_PMU:
1849 hp_amp_power(codec,1);
1850 snd_soc_update_bits(codec, RT3261_OUTPUT,
1851 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1854 case SND_SOC_DAPM_PRE_PMD:
1855 snd_soc_update_bits(codec, RT3261_OUTPUT,
1856 RT3261_L_MUTE | RT3261_R_MUTE,
1857 RT3261_L_MUTE | RT3261_R_MUTE);
1858 hp_amp_power(codec,0);
1868 static int rt3261_index_sync_event(struct snd_soc_dapm_widget *w,
1869 struct snd_kcontrol *kcontrol, int event)
1871 struct snd_soc_codec *codec = w->codec;
1872 printk("enter %s\n",__func__);
1874 case SND_SOC_DAPM_PRE_PMU:
1875 case SND_SOC_DAPM_POST_PMD:
1876 printk("snd_soc_read(codec,RT3261_DUMMY_PR3F)=0x%x\n",snd_soc_read(codec,RT3261_DUMMY_PR3F));
1877 rt3261_index_write(codec, RT3261_MIXER_INT_REG, snd_soc_read(codec,RT3261_DUMMY_PR3F));
1887 static const struct snd_soc_dapm_widget rt3261_dapm_widgets[] = {
1888 SND_SOC_DAPM_SUPPLY("PLL1", RT3261_PWR_ANLG2,
1889 RT3261_PWR_PLL_BIT, 0, NULL, 0),
1892 SND_SOC_DAPM_SUPPLY("LDO2", RT3261_PWR_ANLG1,
1893 RT3261_PWR_LDO2_BIT, 0, NULL, 0),
1895 SND_SOC_DAPM_MICBIAS("micbias1", RT3261_PWR_ANLG2,
1896 RT3261_PWR_MB1_BIT, 0),
1898 SND_SOC_DAPM_MICBIAS("micbias1", SND_SOC_NOPM,
1901 SND_SOC_DAPM_MICBIAS("micbias2", RT3261_PWR_ANLG2,
1902 RT3261_PWR_MB2_BIT, 0),
1904 SND_SOC_DAPM_INPUT("MIC1"),
1905 SND_SOC_DAPM_INPUT("MIC2"),
1906 SND_SOC_DAPM_INPUT("MIC3"),
1907 SND_SOC_DAPM_INPUT("DMIC1"),
1908 SND_SOC_DAPM_INPUT("DMIC2"),
1910 SND_SOC_DAPM_INPUT("IN1P"),
1911 SND_SOC_DAPM_INPUT("IN1N"),
1912 SND_SOC_DAPM_INPUT("IN2P"),
1913 SND_SOC_DAPM_INPUT("IN2N"),
1914 SND_SOC_DAPM_INPUT("IN3P"),
1915 SND_SOC_DAPM_INPUT("IN3N"),
1916 SND_SOC_DAPM_INPUT("DMIC L1"),
1917 SND_SOC_DAPM_INPUT("DMIC R1"),
1918 SND_SOC_DAPM_INPUT("DMIC L2"),
1919 SND_SOC_DAPM_INPUT("DMIC R2"),
1920 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1921 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1923 SND_SOC_DAPM_PGA("BST1", RT3261_PWR_ANLG2,
1924 RT3261_PWR_BST1_BIT, 0, NULL, 0),
1925 SND_SOC_DAPM_PGA("BST2", RT3261_PWR_ANLG2,
1926 RT3261_PWR_BST4_BIT, 0, NULL, 0),
1927 SND_SOC_DAPM_PGA("BST3", RT3261_PWR_ANLG2,
1928 RT3261_PWR_BST2_BIT, 0, NULL, 0),
1930 SND_SOC_DAPM_PGA("INL VOL", RT3261_PWR_VOL,
1931 RT3261_PWR_IN_L_BIT, 0, NULL, 0),
1932 SND_SOC_DAPM_PGA("INR VOL", RT3261_PWR_VOL,
1933 RT3261_PWR_IN_R_BIT, 0, NULL, 0),
1935 SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt3261_inl_mux),
1936 SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt3261_inr_mux),
1938 SND_SOC_DAPM_MIXER("RECMIXL", RT3261_PWR_MIXER, RT3261_PWR_RM_L_BIT, 0,
1939 rt3261_rec_l_mix, ARRAY_SIZE(rt3261_rec_l_mix)),
1940 SND_SOC_DAPM_MIXER("RECMIXR", RT3261_PWR_MIXER, RT3261_PWR_RM_R_BIT, 0,
1941 rt3261_rec_r_mix, ARRAY_SIZE(rt3261_rec_r_mix)),
1943 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM,
1945 SND_SOC_DAPM_ADC_E("ADC R", NULL, SND_SOC_NOPM,
1946 0, 0, rt3261_adc_event,
1947 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
1949 SND_SOC_DAPM_SUPPLY("ADC L power",RT3261_PWR_DIG1,
1950 RT3261_PWR_ADC_L_BIT, 0, NULL, 0),
1951 SND_SOC_DAPM_SUPPLY("ADC R power",RT3261_PWR_DIG1,
1952 RT3261_PWR_ADC_R_BIT, 0, NULL, 0),
1954 SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1955 &rt3261_sto_adc_l2_mux),
1956 SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1957 &rt3261_sto_adc_r2_mux),
1958 SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1959 &rt3261_sto_adc_l1_mux),
1960 SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1961 &rt3261_sto_adc_r1_mux),
1962 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1963 &rt3261_mono_adc_l2_mux),
1964 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1965 &rt3261_mono_adc_l1_mux),
1966 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1967 &rt3261_mono_adc_r1_mux),
1968 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1969 &rt3261_mono_adc_r2_mux),
1971 SND_SOC_DAPM_SUPPLY("stereo filter", RT3261_PWR_DIG2,
1972 RT3261_PWR_ADC_SF_BIT, 0, NULL, 0),
1973 SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
1974 rt3261_sto_adc_l_mix, ARRAY_SIZE(rt3261_sto_adc_l_mix)),
1975 SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
1976 rt3261_sto_adc_r_mix, ARRAY_SIZE(rt3261_sto_adc_r_mix)),
1977 SND_SOC_DAPM_SUPPLY("mono left filter", RT3261_PWR_DIG2,
1978 RT3261_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1979 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1980 rt3261_mono_adc_l_mix, ARRAY_SIZE(rt3261_mono_adc_l_mix)),
1981 SND_SOC_DAPM_SUPPLY("mono right filter", RT3261_PWR_DIG2,
1982 RT3261_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1983 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1984 rt3261_mono_adc_r_mix, ARRAY_SIZE(rt3261_mono_adc_r_mix)),
1987 SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
1988 &rt3261_if2_adc_l_mux),
1989 SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
1990 &rt3261_if2_adc_r_mux),
1992 /* Digital Interface */
1993 SND_SOC_DAPM_SUPPLY("I2S1", RT3261_PWR_DIG1,
1994 RT3261_PWR_I2S1_BIT, 0, NULL, 0),
1995 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1996 SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1997 SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1998 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1999 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2000 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2001 SND_SOC_DAPM_SUPPLY("I2S2", RT3261_PWR_DIG1,
2002 RT3261_PWR_I2S2_BIT, 0, NULL, 0),
2003 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2004 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2005 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2006 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2007 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2008 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2009 SND_SOC_DAPM_SUPPLY("I2S3", RT3261_PWR_DIG1,
2010 RT3261_PWR_I2S3_BIT, 0, NULL, 0),
2011 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2012 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2013 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2014 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2015 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2016 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2018 /* Digital Interface Select */
2019 SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2020 SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2021 SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2022 SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2023 SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
2025 SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2026 SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2027 SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2028 SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2029 SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
2031 SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2032 SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2034 /* Audio Interface */
2035 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2036 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2037 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2038 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2039 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2040 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2043 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2046 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
2049 /* DAC mixer before sound effect */
2050 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2051 rt3261_dac_l_mix, ARRAY_SIZE(rt3261_dac_l_mix)),
2052 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2053 rt3261_dac_r_mix, ARRAY_SIZE(rt3261_dac_r_mix)),
2055 /* DAC2 channel Mux */
2056 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
2057 &rt3261_dac_l2_mux),
2058 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
2059 &rt3261_dac_r2_mux),
2060 SND_SOC_DAPM_PGA("DAC L2 Volume", RT3261_PWR_DIG1,
2061 RT3261_PWR_DAC_L2_BIT, 0, NULL, 0),
2062 SND_SOC_DAPM_PGA("DAC R2 Volume", RT3261_PWR_DIG1,
2063 RT3261_PWR_DAC_R2_BIT, 0, NULL, 0),
2066 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2067 rt3261_sto_dac_l_mix, ARRAY_SIZE(rt3261_sto_dac_l_mix)),
2068 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2069 rt3261_sto_dac_r_mix, ARRAY_SIZE(rt3261_sto_dac_r_mix)),
2070 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2071 rt3261_mono_dac_l_mix, ARRAY_SIZE(rt3261_mono_dac_l_mix)),
2072 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2073 rt3261_mono_dac_r_mix, ARRAY_SIZE(rt3261_mono_dac_r_mix)),
2074 SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
2075 rt3261_dig_l_mix, ARRAY_SIZE(rt3261_dig_l_mix)),
2076 SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
2077 rt3261_dig_r_mix, ARRAY_SIZE(rt3261_dig_r_mix)),
2078 SND_SOC_DAPM_MUX_E("Mono dacr Mux", SND_SOC_NOPM, 0, 0,
2079 &rt3261_dacr2_mux, rt3261_index_sync_event,
2080 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2083 SND_SOC_DAPM_DAC("DAC L1", NULL, RT3261_PWR_DIG1,
2084 RT3261_PWR_DAC_L1_BIT, 0),
2085 SND_SOC_DAPM_DAC("DAC L2", NULL, RT3261_PWR_DIG1,
2086 RT3261_PWR_DAC_L2_BIT, 0),
2087 SND_SOC_DAPM_DAC("DAC R1", NULL, RT3261_PWR_DIG1,
2088 RT3261_PWR_DAC_R1_BIT, 0),
2089 SND_SOC_DAPM_DAC("DAC R2", NULL, RT3261_PWR_DIG1,
2090 RT3261_PWR_DAC_R2_BIT, 0),
2091 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
2093 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM,
2096 SND_SOC_DAPM_MIXER("SPK MIXL", RT3261_PWR_MIXER, RT3261_PWR_SM_L_BIT,
2097 0, rt3261_spk_l_mix, ARRAY_SIZE(rt3261_spk_l_mix)),
2098 SND_SOC_DAPM_MIXER("SPK MIXR", RT3261_PWR_MIXER, RT3261_PWR_SM_R_BIT,
2099 0, rt3261_spk_r_mix, ARRAY_SIZE(rt3261_spk_r_mix)),
2100 SND_SOC_DAPM_MIXER("OUT MIXL", RT3261_PWR_MIXER, RT3261_PWR_OM_L_BIT,
2101 0, rt3261_out_l_mix, ARRAY_SIZE(rt3261_out_l_mix)),
2102 SND_SOC_DAPM_MIXER("OUT MIXR", RT3261_PWR_MIXER, RT3261_PWR_OM_R_BIT,
2103 0, rt3261_out_r_mix, ARRAY_SIZE(rt3261_out_r_mix)),
2105 SND_SOC_DAPM_PGA("SPKVOL L", RT3261_PWR_VOL,
2106 RT3261_PWR_SV_L_BIT, 0, NULL, 0),
2107 SND_SOC_DAPM_PGA("SPKVOL R", RT3261_PWR_VOL,
2108 RT3261_PWR_SV_R_BIT, 0, NULL, 0),
2109 SND_SOC_DAPM_PGA("OUTVOL L", RT3261_PWR_VOL,
2110 RT3261_PWR_OV_L_BIT, 0, NULL, 0),
2111 SND_SOC_DAPM_PGA("OUTVOL R", RT3261_PWR_VOL,
2112 RT3261_PWR_OV_R_BIT, 0, NULL, 0),
2113 SND_SOC_DAPM_PGA("HPOVOL L", RT3261_PWR_VOL,
2114 RT3261_PWR_HV_L_BIT, 0, NULL, 0),
2115 SND_SOC_DAPM_PGA("HPOVOL R", RT3261_PWR_VOL,
2116 RT3261_PWR_HV_R_BIT, 0, NULL, 0),
2117 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM,
2119 /* SPO/HPO/LOUT/Mono Mixer */
2120 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
2121 0, rt3261_spo_l_mix, ARRAY_SIZE(rt3261_spo_l_mix)),
2122 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
2123 0, rt3261_spo_r_mix, ARRAY_SIZE(rt3261_spo_r_mix)),
2124 SND_SOC_DAPM_MIXER("DAC SPK", SND_SOC_NOPM, 0,
2125 0, rt3261_spo_dac_mix, ARRAY_SIZE(rt3261_spo_dac_mix)), //bard 8-27
2126 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
2127 rt3261_hpo_mix, ARRAY_SIZE(rt3261_hpo_mix)),
2128 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
2129 rt3261_lout_mix, ARRAY_SIZE(rt3261_lout_mix)),
2130 SND_SOC_DAPM_MIXER("Mono MIX", RT3261_PWR_ANLG1, RT3261_PWR_MM_BIT, 0,
2131 rt3261_mono_mix, ARRAY_SIZE(rt3261_mono_mix)),
2133 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0,
2134 rt3261_hp_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2135 SND_SOC_DAPM_PGA_S("SPK amp", 1, SND_SOC_NOPM, 0, 0,
2136 rt3261_spk_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2137 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
2138 rt3261_lout_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2139 SND_SOC_DAPM_PGA_S("Mono amp", 1, RT3261_PWR_ANLG1,
2140 RT3261_PWR_MA_BIT, 0, rt3261_mono_event,
2141 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2144 SND_SOC_DAPM_OUTPUT("SPOLP"),
2145 SND_SOC_DAPM_OUTPUT("SPOLN"),
2146 SND_SOC_DAPM_OUTPUT("SPORP"),
2147 SND_SOC_DAPM_OUTPUT("SPORN"),
2148 SND_SOC_DAPM_OUTPUT("HPOL"),
2149 SND_SOC_DAPM_OUTPUT("HPOR"),
2150 SND_SOC_DAPM_OUTPUT("LOUTL"),
2151 SND_SOC_DAPM_OUTPUT("LOUTR"),
2152 SND_SOC_DAPM_OUTPUT("MonoP"),
2153 SND_SOC_DAPM_OUTPUT("MonoN"),
2156 static const struct snd_soc_dapm_route rt3261_dapm_routes[] = {
2157 {"IN1P", NULL, "LDO2"},
2158 {"IN2P", NULL, "LDO2"},
2159 {"IN3P", NULL, "LDO2"},
2161 {"IN1P", NULL, "MIC1"},
2162 {"IN1N", NULL, "MIC1"},
2163 {"IN2P", NULL, "MIC2"},
2164 {"IN2N", NULL, "MIC2"},
2165 {"IN3P", NULL, "MIC3"},
2166 {"IN3N", NULL, "MIC3"},
2168 {"DMIC L1", NULL, "DMIC1"},
2169 {"DMIC R1", NULL, "DMIC1"},
2170 {"DMIC L2", NULL, "DMIC2"},
2171 {"DMIC R2", NULL, "DMIC2"},
2173 {"BST1", NULL, "IN1P"},
2174 {"BST1", NULL, "IN1N"},
2175 {"BST2", NULL, "IN2P"},
2176 {"BST2", NULL, "IN2N"},
2177 {"BST3", NULL, "IN3P"},
2178 {"BST3", NULL, "IN3N"},
2180 {"INL VOL", NULL, "IN2P"},
2181 {"INR VOL", NULL, "IN2N"},
2183 {"RECMIXL", "HPOL Switch", "HPOL"},
2184 {"RECMIXL", "INL Switch", "INL VOL"},
2185 {"RECMIXL", "BST3 Switch", "BST3"},
2186 {"RECMIXL", "BST2 Switch", "BST2"},
2187 {"RECMIXL", "BST1 Switch", "BST1"},
2188 {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
2190 {"RECMIXR", "HPOR Switch", "HPOR"},
2191 {"RECMIXR", "INR Switch", "INR VOL"},
2192 {"RECMIXR", "BST3 Switch", "BST3"},
2193 {"RECMIXR", "BST2 Switch", "BST2"},
2194 {"RECMIXR", "BST1 Switch", "BST1"},
2195 {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
2197 {"ADC L", NULL, "RECMIXL"},
2198 {"ADC L", NULL, "ADC L power"},
2199 {"ADC R", NULL, "RECMIXR"},
2200 {"ADC R", NULL, "ADC R power"},
2202 {"DMIC L1", NULL, "DMIC CLK"},
2203 {"DMIC L2", NULL, "DMIC CLK"},
2205 {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
2206 {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
2207 {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
2208 {"Stereo ADC L1 Mux", "ADC", "ADC L"},
2209 {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
2211 {"Stereo ADC R1 Mux", "ADC", "ADC R"},
2212 {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
2213 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
2214 {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
2215 {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
2217 {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
2218 {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
2219 {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
2220 {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
2221 {"Mono ADC L1 Mux", "ADCL", "ADC L"},
2223 {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
2224 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
2225 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
2226 {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
2227 {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
2229 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
2230 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
2231 {"Stereo ADC MIXL", NULL, "stereo filter"},
2232 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
2234 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
2235 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
2236 {"Stereo ADC MIXR", NULL, "stereo filter"},
2237 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
2239 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
2240 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
2241 {"Mono ADC MIXL", NULL, "mono left filter"},
2242 {"mono left filter", NULL, "PLL1", check_sysclk1_source},
2244 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
2245 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
2246 {"Mono ADC MIXR", NULL, "mono right filter"},
2247 {"mono right filter", NULL, "PLL1", check_sysclk1_source},
2249 {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
2250 {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
2252 {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
2253 {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
2254 {"IF3 ADC L", NULL, "Mono ADC MIXL"},
2255 {"IF3 ADC R", NULL, "Mono ADC MIXR"},
2256 {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
2257 {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
2259 {"IF1 ADC", NULL, "I2S1"},
2260 {"IF1 ADC", NULL, "IF1 ADC L"},
2261 {"IF1 ADC", NULL, "IF1 ADC R"},
2262 {"IF2 ADC", NULL, "I2S2"},
2263 {"IF2 ADC", NULL, "IF2 ADC L"},
2264 {"IF2 ADC", NULL, "IF2 ADC R"},
2265 {"IF3 ADC", NULL, "I2S3"},
2266 {"IF3 ADC", NULL, "IF3 ADC L"},
2267 {"IF3 ADC", NULL, "IF3 ADC R"},
2269 {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
2270 {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
2271 {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
2272 {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
2273 {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
2274 {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
2275 {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
2276 {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
2277 {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
2278 {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
2280 {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
2281 {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
2282 {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
2283 {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
2284 {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
2285 {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
2286 {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
2287 {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
2288 {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
2289 {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
2291 {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
2292 {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
2293 {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
2294 {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
2295 {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
2296 {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
2297 {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
2298 {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
2300 {"AIF1TX", NULL, "DAI1 TX Mux"},
2301 {"AIF1TX", NULL, "SDI1 TX Mux"},
2302 {"AIF2TX", NULL, "DAI2 TX Mux"},
2303 {"AIF2TX", NULL, "SDI2 TX Mux"},
2304 {"AIF3TX", NULL, "DAI3 TX Mux"},
2306 {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
2307 {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
2308 {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
2309 {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
2310 {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
2311 {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
2312 {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
2313 {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
2315 {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
2316 {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
2317 {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
2318 {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
2319 {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
2320 {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
2321 {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
2322 {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
2324 {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
2325 {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
2326 {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
2327 {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
2328 {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
2329 {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
2330 {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
2331 {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
2333 {"IF1 DAC", NULL, "I2S1"},
2334 {"IF1 DAC", NULL, "DAI1 RX Mux"},
2335 {"IF2 DAC", NULL, "I2S2"},
2336 {"IF2 DAC", NULL, "DAI2 RX Mux"},
2337 {"IF3 DAC", NULL, "I2S3"},
2338 {"IF3 DAC", NULL, "DAI3 RX Mux"},
2340 {"IF1 DAC L", NULL, "IF1 DAC"},
2341 {"IF1 DAC R", NULL, "IF1 DAC"},
2342 {"IF2 DAC L", NULL, "IF2 DAC"},
2343 {"IF2 DAC R", NULL, "IF2 DAC"},
2344 {"IF3 DAC L", NULL, "IF3 DAC"},
2345 {"IF3 DAC R", NULL, "IF3 DAC"},
2347 {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
2348 {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
2349 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
2350 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
2352 {"ANC", NULL, "Stereo ADC MIXL"},
2353 {"ANC", NULL, "Stereo ADC MIXR"},
2355 {"Audio DSP", NULL, "DAC MIXL"},
2356 {"Audio DSP", NULL, "DAC MIXR"},
2358 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
2359 {"DAC L2 Mux", "IF3", "IF3 DAC L"},
2360 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
2361 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
2363 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
2364 {"DAC R2 Mux", "IF3", "IF3 DAC R"},
2365 {"DAC R2 Volume", NULL, "Mono dacr Mux"},
2366 {"Mono dacr Mux", "TxDC_R", "DAC R2 Mux"},
2367 {"Mono dacr Mux", "TxDP_R", "IF2 ADC R Mux"},
2369 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
2370 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2371 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
2372 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
2373 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2374 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
2376 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
2377 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2378 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume"},
2379 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
2380 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2381 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume"},
2383 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
2384 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2385 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
2386 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2388 {"DAC L1", NULL, "Stereo DAC MIXL"},
2389 {"DAC L1", NULL, "PLL1", check_sysclk1_source},
2390 {"DAC R1", NULL, "Stereo DAC MIXR"},
2391 {"DAC R1", NULL, "PLL1", check_sysclk1_source},
2392 {"DAC L2", NULL, "Mono DAC MIXL"},
2393 {"DAC L2", NULL, "PLL1", check_sysclk1_source},
2394 {"DAC R2", NULL, "Mono DAC MIXR"},
2395 {"DAC R2", NULL, "PLL1", check_sysclk1_source},
2397 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
2398 {"SPK MIXL", "INL Switch", "INL VOL"},
2399 {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
2400 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
2401 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
2402 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
2403 {"SPK MIXR", "INR Switch", "INR VOL"},
2404 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
2405 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
2406 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
2408 {"OUT MIXL", "BST3 Switch", "BST3"},
2409 {"OUT MIXL", "BST1 Switch", "BST1"},
2410 {"OUT MIXL", "INL Switch", "INL VOL"},
2411 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
2412 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
2413 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
2414 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
2416 {"OUT MIXR", "BST3 Switch", "BST3"},
2417 {"OUT MIXR", "BST2 Switch", "BST2"},
2418 {"OUT MIXR", "BST1 Switch", "BST1"},
2419 {"OUT MIXR", "INR Switch", "INR VOL"},
2420 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
2421 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
2422 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
2423 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
2425 {"SPKVOL L", NULL, "SPK MIXL"},
2426 {"SPKVOL R", NULL, "SPK MIXR"},
2427 {"HPOVOL L", NULL, "OUT MIXL"},
2428 {"HPOVOL R", NULL, "OUT MIXR"},
2429 {"OUTVOL L", NULL, "OUT MIXL"},
2430 {"OUTVOL R", NULL, "OUT MIXR"},
2432 {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
2433 {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
2435 {"SPOL MIX", "DAC Switch", "DAC SPK"},
2436 {"DAC SPK", "DAC L1 Switch", "DAC L1"},
2437 {"DAC SPK", "DAC R1 Switch", "DAC R1"},
2439 {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
2440 {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
2441 {"SPOL MIX", "BST1 Switch", "BST1"},
2442 {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
2443 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
2444 {"SPOR MIX", "BST1 Switch", "BST1"},
2446 {"DAC 2", NULL, "DAC L2"},
2447 {"DAC 2", NULL, "DAC R2"},
2448 {"DAC 1", NULL, "DAC L1"},
2449 {"DAC 1", NULL, "DAC R1"},
2450 {"HPOVOL", NULL, "HPOVOL L"},
2451 {"HPOVOL", NULL, "HPOVOL R"},
2452 {"HPO MIX", "DAC2 Switch", "DAC 2"},
2453 {"HPO MIX", "DAC1 Switch", "DAC 1"},
2454 {"HPO MIX", "HPVOL Switch", "HPOVOL"},
2456 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
2457 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
2458 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
2459 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
2461 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
2462 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
2463 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
2464 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
2465 {"Mono MIX", "BST1 Switch", "BST1"},
2467 {"SPK amp", NULL, "SPOL MIX"},
2468 {"SPK amp", NULL, "SPOR MIX"},
2469 {"SPOLP", NULL, "SPK amp"},
2470 {"SPOLN", NULL, "SPK amp"},
2471 {"SPORP", NULL, "SPK amp"},
2472 {"SPORN", NULL, "SPK amp"},
2474 {"HP amp", NULL, "HPO MIX"},
2475 {"HPOL", NULL, "HP amp"},
2476 {"HPOR", NULL, "HP amp"},
2478 {"LOUT amp", NULL, "LOUT MIX"},
2479 {"LOUTL", NULL, "LOUT amp"},
2480 {"LOUTR", NULL, "LOUT amp"},
2482 {"Mono amp", NULL, "Mono MIX"},
2483 {"MonoP", NULL, "Mono amp"},
2484 {"MonoN", NULL, "Mono amp"},
2487 static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
2494 val = snd_soc_read(codec, RT3261_I2S1_SDP);
2495 val = (val & RT3261_I2S_IF_MASK) >> RT3261_I2S_IF_SFT;
2498 if (val == RT3261_IF_123 || val == RT3261_IF_132 ||
2499 val == RT3261_IF_113)
2500 ret |= RT3261_U_IF1;
2501 if (val == RT3261_IF_312 || val == RT3261_IF_213 ||
2502 val == RT3261_IF_113)
2503 ret |= RT3261_U_IF2;
2504 if (val == RT3261_IF_321 || val == RT3261_IF_231)
2505 ret |= RT3261_U_IF3;
2509 if (val == RT3261_IF_231 || val == RT3261_IF_213 ||
2510 val == RT3261_IF_223)
2511 ret |= RT3261_U_IF1;
2512 if (val == RT3261_IF_123 || val == RT3261_IF_321 ||
2513 val == RT3261_IF_223)
2514 ret |= RT3261_U_IF2;
2515 if (val == RT3261_IF_132 || val == RT3261_IF_312)
2516 ret |= RT3261_U_IF3;
2527 static int get_clk_info(int sclk, int rate)
2529 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
2531 if (sclk <= 0 || rate <= 0)
2535 for (i = 0; i < ARRAY_SIZE(pd); i++)
2536 if (sclk == rate * pd[i])
2542 static int rt3261_hw_params(struct snd_pcm_substream *substream,
2543 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2545 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2546 struct snd_soc_codec *codec = rtd->codec;
2547 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2548 unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
2549 int pre_div, bclk_ms, frame_size;
2551 rt3261->lrck[dai->id] = params_rate(params);
2553 rt3261->lrck[dai->id] = 8000;
2554 pre_div = get_clk_info(rt3261->sysclk, rt3261->lrck[dai->id]);
2556 dev_err(codec->dev, "Unsupported clock setting\n");
2559 frame_size = snd_soc_params_to_frame_size(params);
2560 if (frame_size < 0) {
2561 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2564 bclk_ms = frame_size > 32 ? 1 : 0;
2565 rt3261->bclk[dai->id] = rt3261->lrck[dai->id] * (32 << bclk_ms);
2567 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2568 rt3261->bclk[dai->id], rt3261->lrck[dai->id]);
2569 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2570 bclk_ms, pre_div, dai->id);
2572 switch (params_format(params)) {
2573 case SNDRV_PCM_FORMAT_S16_LE:
2575 case SNDRV_PCM_FORMAT_S20_3LE:
2576 val_len |= RT3261_I2S_DL_20;
2578 case SNDRV_PCM_FORMAT_S24_LE:
2579 val_len |= RT3261_I2S_DL_24;
2581 case SNDRV_PCM_FORMAT_S8:
2582 val_len |= RT3261_I2S_DL_8;
2588 dai_sel = get_sdp_info(codec, dai->id);
2589 dai_sel |= (RT3261_U_IF1 | RT3261_U_IF2);
2591 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
2594 if (dai_sel & RT3261_U_IF1) {
2595 mask_clk = RT3261_I2S_BCLK_MS1_MASK | RT3261_I2S_PD1_MASK;
2596 val_clk = bclk_ms << RT3261_I2S_BCLK_MS1_SFT |
2597 pre_div << RT3261_I2S_PD1_SFT;
2598 snd_soc_update_bits(codec, RT3261_I2S1_SDP,
2599 RT3261_I2S_DL_MASK, val_len);
2600 snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
2602 if (dai_sel & RT3261_U_IF2) {
2603 mask_clk = RT3261_I2S_BCLK_MS2_MASK | RT3261_I2S_PD2_MASK;
2604 val_clk = bclk_ms << RT3261_I2S_BCLK_MS2_SFT |
2605 pre_div << RT3261_I2S_PD2_SFT;
2606 snd_soc_update_bits(codec, RT3261_I2S2_SDP,
2607 RT3261_I2S_DL_MASK, val_len);
2608 snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
2614 static int rt3261_prepare(struct snd_pcm_substream *substream,
2615 struct snd_soc_dai *dai)
2617 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2618 struct snd_soc_codec *codec = rtd->codec;
2619 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2621 rt3261->aif_pu = dai->id;
2625 static int rt3261_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2627 struct snd_soc_codec *codec = dai->codec;
2628 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2629 unsigned int reg_val = 0, dai_sel;
2631 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2632 case SND_SOC_DAIFMT_CBM_CFM:
2633 rt3261->master[dai->id] = 1;
2635 case SND_SOC_DAIFMT_CBS_CFS:
2636 reg_val |= RT3261_I2S_MS_S;
2637 rt3261->master[dai->id] = 0;
2643 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2644 case SND_SOC_DAIFMT_NB_NF:
2646 case SND_SOC_DAIFMT_IB_NF:
2647 reg_val |= RT3261_I2S_BP_INV;
2653 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2654 case SND_SOC_DAIFMT_I2S:
2656 case SND_SOC_DAIFMT_LEFT_J:
2657 reg_val |= RT3261_I2S_DF_LEFT;
2659 case SND_SOC_DAIFMT_DSP_A:
2660 reg_val |= RT3261_I2S_DF_PCM_A;
2662 case SND_SOC_DAIFMT_DSP_B:
2663 reg_val |= RT3261_I2S_DF_PCM_B;
2669 dai_sel = get_sdp_info(codec, dai->id);
2671 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
2674 if (dai_sel & RT3261_U_IF1) {
2675 snd_soc_update_bits(codec, RT3261_I2S1_SDP,
2676 RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
2677 RT3261_I2S_DF_MASK, reg_val);
2679 if (dai_sel & RT3261_U_IF2) {
2680 snd_soc_update_bits(codec, RT3261_I2S2_SDP,
2681 RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
2682 RT3261_I2S_DF_MASK, reg_val);
2688 static int rt3261_set_dai_sysclk(struct snd_soc_dai *dai,
2689 int clk_id, unsigned int freq, int dir)
2691 struct snd_soc_codec *codec = dai->codec;
2692 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2693 unsigned int reg_val = 0;
2695 if (freq == rt3261->sysclk && clk_id == rt3261->sysclk_src)
2699 case RT3261_SCLK_S_MCLK:
2700 reg_val |= RT3261_SCLK_SRC_MCLK;
2702 case RT3261_SCLK_S_PLL1:
2703 reg_val |= RT3261_SCLK_SRC_PLL1;
2705 case RT3261_SCLK_S_RCCLK:
2706 reg_val |= RT3261_SCLK_SRC_RCCLK;
2709 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2712 snd_soc_update_bits(codec, RT3261_GLB_CLK,
2713 RT3261_SCLK_SRC_MASK, reg_val);
2714 rt3261->sysclk = freq;
2715 rt3261->sysclk_src = clk_id;
2717 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2723 * rt3261_pll_calc - Calcualte PLL M/N/K code.
2724 * @freq_in: external clock provided to codec.
2725 * @freq_out: target clock which codec works on.
2726 * @pll_code: Pointer to structure with M, N, K and bypass flag.
2728 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
2729 * which make calculation more efficiently.
2731 * Returns 0 for success or negative error code.
2733 static int rt3261_pll_calc(const unsigned int freq_in,
2734 const unsigned int freq_out, struct rt3261_pll_code *pll_code)
2736 int max_n = RT3261_PLL_N_MAX, max_m = RT3261_PLL_M_MAX;
2737 int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
2738 bool bypass = false;
2740 if (RT3261_PLL_INP_MAX < freq_in || RT3261_PLL_INP_MIN > freq_in)
2743 for (n_t = 0; n_t <= max_n; n_t++) {
2744 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
2747 if (in_t == freq_out) {
2752 for (m_t = 0; m_t <= max_m; m_t++) {
2753 out_t = in_t / (m_t + 2);
2754 red = abs(out_t - freq_out);
2764 pr_debug("Only get approximation about PLL\n");
2768 pll_code->m_bp = bypass;
2769 pll_code->m_code = m;
2770 pll_code->n_code = n;
2771 pll_code->k_code = 2;
2775 static int rt3261_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2776 unsigned int freq_in, unsigned int freq_out)
2778 struct snd_soc_codec *codec = dai->codec;
2779 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2780 struct rt3261_pll_code pll_code;
2783 if (source == rt3261->pll_src && freq_in == rt3261->pll_in &&
2784 freq_out == rt3261->pll_out)
2787 if (!freq_in || !freq_out) {
2788 dev_dbg(codec->dev, "PLL disabled\n");
2791 rt3261->pll_out = 0;
2792 snd_soc_update_bits(codec, RT3261_GLB_CLK,
2793 RT3261_SCLK_SRC_MASK, RT3261_SCLK_SRC_MCLK);
2798 case RT3261_PLL1_S_MCLK:
2799 snd_soc_update_bits(codec, RT3261_GLB_CLK,
2800 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_MCLK);
2802 case RT3261_PLL1_S_BCLK1:
2803 case RT3261_PLL1_S_BCLK2:
2804 dai_sel = get_sdp_info(codec, dai->id);
2807 "Failed to get sdp info: %d\n", dai_sel);
2810 if (dai_sel & RT3261_U_IF1) {
2811 snd_soc_update_bits(codec, RT3261_GLB_CLK,
2812 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK1);
2814 if (dai_sel & RT3261_U_IF2) {
2815 snd_soc_update_bits(codec, RT3261_GLB_CLK,
2816 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK2);
2818 if (dai_sel & RT3261_U_IF3) {
2819 snd_soc_update_bits(codec, RT3261_GLB_CLK,
2820 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK3);
2824 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2828 ret = rt3261_pll_calc(freq_in, freq_out, &pll_code);
2830 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2834 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
2835 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
2837 snd_soc_write(codec, RT3261_PLL_CTRL1,
2838 pll_code.n_code << RT3261_PLL_N_SFT | pll_code.k_code);
2839 snd_soc_write(codec, RT3261_PLL_CTRL2,
2840 (pll_code.m_bp ? 0 : pll_code.m_code) << RT3261_PLL_M_SFT |
2841 pll_code.m_bp << RT3261_PLL_M_BP_SFT);
2843 rt3261->pll_in = freq_in;
2844 rt3261->pll_out = freq_out;
2845 rt3261->pll_src = source;
2851 * rt3261_index_show - Dump private registers.
2852 * @dev: codec device.
2853 * @attr: device attribute.
2854 * @buf: buffer for display.
2856 * To show non-zero values of all private registers.
2858 * Returns buffer length.
2860 static ssize_t rt3261_index_show(struct device *dev,
2861 struct device_attribute *attr, char *buf)
2863 struct i2c_client *client = to_i2c_client(dev);
2864 struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
2865 struct snd_soc_codec *codec = rt3261->codec;
2869 cnt += sprintf(buf, "RT3261 index register\n");
2870 for (i = 0; i < 0xb4; i++) {
2871 if (cnt + RT3261_REG_DISP_LEN >= PAGE_SIZE)
2873 val = rt3261_index_read(codec, i);
2876 cnt += snprintf(buf + cnt, RT3261_REG_DISP_LEN,
2877 "%02x: %04x\n", i, val);
2880 if (cnt >= PAGE_SIZE)
2881 cnt = PAGE_SIZE - 1;
2885 static DEVICE_ATTR(index_reg, 0444, rt3261_index_show, NULL);
2887 static int rt3261_set_bias_level(struct snd_soc_codec *codec,
2888 enum snd_soc_bias_level level)
2891 case SND_SOC_BIAS_ON:
2894 case SND_SOC_BIAS_PREPARE:
2895 snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
2896 RT3261_PWR_MB1 | RT3261_PWR_MB2,
2897 RT3261_PWR_MB1 | RT3261_PWR_MB2);
2900 case SND_SOC_BIAS_STANDBY:
2901 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
2902 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2903 RT3261_PWR_VREF1 | RT3261_PWR_MB |
2904 RT3261_PWR_BG | RT3261_PWR_VREF2,
2905 RT3261_PWR_VREF1 | RT3261_PWR_MB |
2906 RT3261_PWR_BG | RT3261_PWR_VREF2);
2908 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2909 RT3261_PWR_FV1 | RT3261_PWR_FV2,
2910 RT3261_PWR_FV1 | RT3261_PWR_FV2);
2911 snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3701);
2912 codec->cache_only = false;
2913 codec->cache_sync = 1;
2914 snd_soc_cache_sync(codec);
2915 rt3261_index_sync(codec);
2919 case SND_SOC_BIAS_OFF:
2920 snd_soc_write(codec, RT3261_DEPOP_M1, 0x0004);
2921 snd_soc_write(codec, RT3261_DEPOP_M2, 0x1100);
2922 snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3700);
2923 snd_soc_write(codec, RT3261_PWR_DIG1, 0x0000);
2924 snd_soc_write(codec, RT3261_PWR_DIG2, 0x0000);
2925 snd_soc_write(codec, RT3261_PWR_VOL, 0x0000);
2926 snd_soc_write(codec, RT3261_PWR_MIXER, 0x0000);
2927 snd_soc_write(codec, RT3261_PWR_ANLG1, 0x0000);
2928 snd_soc_write(codec, RT3261_PWR_ANLG2, 0x0000);
2934 codec->dapm.bias_level = level;
2939 static int rt3261_proc_init(void);
2942 static int rt3261_probe(struct snd_soc_codec *codec)
2944 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2946 struct clk *iis_clk;
2948 #if defined (CONFIG_SND_SOC_RT3224)
2949 pr_info("Codec driver version %s, in fact you choose rt3224, no dsp!\n", VERSION);
2951 pr_info("Codec driver version %s, in fact you choose rt3261 with a dsp!\n", VERSION);
2954 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
2956 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2959 codec->write = rt3261_write;
2965 #if defined (CONFIG_SND_SOC_RT5623)
2966 //for rt5623 MCLK use
2967 iis_clk = clk_get_sys("rk29_i2s.2", "i2s");
2968 if (IS_ERR(iis_clk)) {
2969 printk("failed to get i2s clk\n");
2970 ret = PTR_ERR(iis_clk);
2972 printk("I2S2 got i2s clk ok!\n");
2973 clk_enable(iis_clk);
2974 clk_set_rate(iis_clk, 11289600);
2975 rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME, GPIO0D_I2S2_2CH_CLK);
2980 rt3261_reset(codec);
2981 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2982 RT3261_PWR_VREF1 | RT3261_PWR_MB |
2983 RT3261_PWR_BG | RT3261_PWR_VREF2,
2984 RT3261_PWR_VREF1 | RT3261_PWR_MB |
2985 RT3261_PWR_BG | RT3261_PWR_VREF2);
2987 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2988 RT3261_PWR_FV1 | RT3261_PWR_FV2,
2989 RT3261_PWR_FV1 | RT3261_PWR_FV2);
2991 if (rt3261->dmic_en == RT3261_DMIC1) {
2992 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
2993 RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
2994 snd_soc_update_bits(codec, RT3261_DMIC,
2995 RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK,
2996 RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING);
2997 } else if (rt3261->dmic_en == RT3261_DMIC2) {
2998 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
2999 RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
3000 snd_soc_update_bits(codec, RT3261_DMIC,
3001 RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK,
3002 RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING);
3004 snd_soc_write(codec, RT3261_GEN_CTRL2, 0x4040);
3005 ret = snd_soc_read(codec, RT3261_VENDOR_ID);
3006 printk("read codec chip id is 0x%x\n",ret);
3008 snd_soc_update_bits(codec, RT3261_JD_CTRL,
3009 RT3261_JD1_IN4P_MASK | RT3261_JD2_IN4N_MASK,
3010 RT3261_JD1_IN4P_EN | RT3261_JD2_IN4N_EN);
3014 printk("you use an old chip, please use a new one\n");
3016 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3017 RT3261_PWR_HP_L | RT3261_PWR_HP_R,
3019 rt3261_reg_init(codec);
3021 codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
3022 rt3261->codec = codec;
3024 snd_soc_add_controls(codec, rt3261_snd_controls,
3025 ARRAY_SIZE(rt3261_snd_controls));
3026 snd_soc_dapm_new_controls(&codec->dapm, rt3261_dapm_widgets,
3027 ARRAY_SIZE(rt3261_dapm_widgets));
3028 snd_soc_dapm_add_routes(&codec->dapm, rt3261_dapm_routes,
3029 ARRAY_SIZE(rt3261_dapm_routes));
3032 #if defined (CONFIG_SND_SOC_RT3261)
3033 rt3261->dsp_sw = RT3261_DSP_AEC_NS_FENS;
3034 rt3261_dsp_probe(codec);
3038 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
3039 struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
3040 ioctl_ops->index_write = rt3261_index_write;
3041 ioctl_ops->index_read = rt3261_index_read;
3042 ioctl_ops->index_update_bits = rt3261_index_update_bits;
3043 ioctl_ops->ioctl_common = rt3261_ioctl_common;
3044 realtek_ce_init_hwdep(codec);
3049 ret = device_create_file(codec->dev, &dev_attr_index_reg);
3052 "Failed to create index_reg sysfs files: %d\n", ret);
3055 rt3261_codec = codec;
3059 static int rt3261_remove(struct snd_soc_codec *codec)
3061 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3066 static int rt3261_suspend(struct snd_soc_codec *codec, pm_message_t state)
3068 #if defined (CONFIG_SND_SOC_RT3261)
3069 /* After opening LDO of DSP, then close LDO of codec.
3070 * (1) DSP LDO power on
3071 * (2) DSP core power off
3072 * (3) DSP IIS interface power off
3073 * (4) Toggle pin of codec LDO1 to power off
3075 rt3261_dsp_suspend(codec, state);
3077 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3081 static int rt3261_resume(struct snd_soc_codec *codec)
3083 rt3261_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3084 #if defined (CONFIG_SND_SOC_RT3261)
3085 /* After opening LDO of codec, then close LDO of DSP. */
3086 rt3261_dsp_resume(codec);
3091 #define rt3261_suspend NULL
3092 #define rt3261_resume NULL
3095 #define RT3261_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3096 #define RT3261_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3097 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3099 struct snd_soc_dai_ops rt3261_aif_dai_ops = {
3100 .hw_params = rt3261_hw_params,
3101 .prepare = rt3261_prepare,
3102 .set_fmt = rt3261_set_dai_fmt,
3103 .set_sysclk = rt3261_set_dai_sysclk,
3104 .set_pll = rt3261_set_dai_pll,
3107 struct snd_soc_dai_driver rt3261_dai[] = {
3109 .name = "rt3261-aif1",
3112 .stream_name = "AIF1 Playback",
3115 .rates = RT3261_STEREO_RATES,
3116 .formats = RT3261_FORMATS,
3119 .stream_name = "AIF1 Capture",
3122 .rates = RT3261_STEREO_RATES,
3123 .formats = RT3261_FORMATS,
3125 .ops = &rt3261_aif_dai_ops,
3128 .name = "rt3261-aif2",
3131 .stream_name = "AIF2 Playback",
3134 .rates = RT3261_STEREO_RATES,
3135 .formats = RT3261_FORMATS,
3138 .stream_name = "AIF2 Capture",
3141 .rates = RT3261_STEREO_RATES,
3142 .formats = RT3261_FORMATS,
3144 .ops = &rt3261_aif_dai_ops,
3148 static struct snd_soc_codec_driver soc_codec_dev_rt3261 = {
3149 .probe = rt3261_probe,
3150 .remove = rt3261_remove,
3151 .suspend = rt3261_suspend,
3152 .resume = rt3261_resume,
3153 .write = rt3261_write,
3154 .set_bias_level = rt3261_set_bias_level,
3155 .reg_cache_size = RT3261_VENDOR_ID2 + 1,
3156 .reg_word_size = sizeof(u16),
3157 .reg_cache_default = rt3261_reg,
3158 .volatile_register = rt3261_volatile_register,
3159 .readable_register = rt3261_readable_register,
3160 .reg_cache_step = 1,
3163 static const struct i2c_device_id rt3261_i2c_id[] = {
3167 MODULE_DEVICE_TABLE(i2c, rt3261_i2c_id);
3169 static int __devinit rt3261_i2c_probe(struct i2c_client *i2c,
3170 const struct i2c_device_id *id)
3172 struct rt3261_priv *rt3261;
3174 struct rt3261_platform_data *pdata = pdata = i2c->dev.platform_data;
3176 rt3261 = kzalloc(sizeof(struct rt3261_priv), GFP_KERNEL);
3180 rt3261->codec_en_gpio = pdata->codec_en_gpio;
3181 rt3261->io_init = pdata->io_init;
3184 rt3261->io_init(pdata->codec_en_gpio, pdata->codec_en_gpio_info.iomux_name, pdata->codec_en_gpio_info.iomux_mode);
3186 #if defined (CONFIG_SND_SOC_RT5623)
3187 rt3261->modem_is_open = 0;
3190 i2c_set_clientdata(i2c, rt3261);
3191 DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
3192 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt3261,
3193 rt3261_dai, ARRAY_SIZE(rt3261_dai));
3200 static int __devexit rt3261_i2c_remove(struct i2c_client *i2c)
3202 snd_soc_unregister_codec(&i2c->dev);
3203 kfree(i2c_get_clientdata(i2c));
3207 static void rt3261_i2c_shutdown(struct i2c_client *client)
3209 struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
3210 struct snd_soc_codec *codec = rt3261->codec;
3213 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3216 struct i2c_driver rt3261_i2c_driver = {
3219 .owner = THIS_MODULE,
3221 .probe = rt3261_i2c_probe,
3222 .remove = __devexit_p(rt3261_i2c_remove),
3223 .shutdown = rt3261_i2c_shutdown,
3224 .id_table = rt3261_i2c_id,
3227 static int __init rt3261_modinit(void)
3229 return i2c_add_driver(&rt3261_i2c_driver);
3231 module_init(rt3261_modinit);
3233 static void __exit rt3261_modexit(void)
3235 i2c_del_driver(&rt3261_i2c_driver);
3237 module_exit(rt3261_modexit);
3239 MODULE_DESCRIPTION("ASoC RT3261 driver");
3240 MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
3241 MODULE_LICENSE("GPL");
3246 static ssize_t rt3261_proc_write(struct file *file, const char __user *buffer,
3247 unsigned long len, void *data)
3254 #if defined (CONFIG_SND_SOC_RT3261)
3255 struct rt3261_dsp_param param;
3258 cookie_pot = (char *)vmalloc( len );
3265 if (copy_from_user( cookie_pot, buffer, len ))
3269 switch(cookie_pot[0])
3273 printk("Read reg debug\n");
3274 if(cookie_pot[1] ==':')
3276 strsep(&cookie_pot,":");
3277 while((p=strsep(&cookie_pot,",")))
3279 reg = simple_strtol(p,NULL,16);
3280 value = rt3261_read(rt3261_codec,reg);
3281 printk("rt3261_read:0x%04x = 0x%04x\n",reg,value);
3287 printk("Error Read reg debug.\n");
3288 printk("For example: echo r:22,23,24,25>rt3261_ts\n");
3293 printk("Write reg debug\n");
3294 if(cookie_pot[1] ==':')
3296 strsep(&cookie_pot,":");
3297 while((p=strsep(&cookie_pot,"=")))
3299 reg = simple_strtol(p,NULL,16);
3300 p=strsep(&cookie_pot,",");
3301 value = simple_strtol(p,NULL,16);
3302 rt3261_write(rt3261_codec,reg,value);
3303 printk("rt3261_write:0x%04x = 0x%04x\n",reg,value);
3309 printk("Error Write reg debug.\n");
3310 printk("For example: w:22=0,23=0,24=0,25=0>rt3261_ts\n");
3314 printk("Dump rt3261 index reg \n");
3316 for (i = 0; i < 0xb4; i++)
3318 value = rt3261_index_read(rt3261_codec, i);
3319 printk("rt3261_index_read:0x%04x = 0x%04x\n",i,value);
3322 #if defined (CONFIG_SND_SOC_RT3261)
3324 param.cmd_fmt = 0x00e0;
3325 param.cmd = RT3261_DSP_CMD_MW;
3326 printk("Write dsp reg debug\n");
3327 if(cookie_pot[1] ==':')
3329 strsep(&cookie_pot,":");
3330 while((p=strsep(&cookie_pot,"=")))
3332 param.addr = simple_strtol(p,NULL,16);
3333 p=strsep(&cookie_pot,",");
3334 param.data = simple_strtol(p,NULL,16);
3335 rt3261_dsp_write(rt3261_codec,¶m);
3336 printk("rt3261_dsp_write:0x%04x = 0x%04x\n",param.addr,param.data);
3342 printk("Read dsp reg debug\n");
3343 if(cookie_pot[1] ==':')
3345 strsep(&cookie_pot,":");
3346 while((p=strsep(&cookie_pot,",")))
3348 reg = simple_strtol(p,NULL,16);
3349 value = rt3261_dsp_read(rt3261_codec,reg);
3350 printk("rt3261_dsp_read:0x%04x = 0x%04x\n",reg,value);
3357 printk("Help for rt3261_ts .\n-->The Cmd list: \n");
3358 printk("-->'d&&D' Open or Off the debug\n");
3359 printk("-->'r&&R' Read reg debug,Example: echo 'r:22,23,24,25'>rt3261_ts\n");
3360 printk("-->'w&&W' Write reg debug,Example: echo 'w:22=0,23=0,24=0,25=0'>rt3261_ts\n");
3367 static const struct file_operations rt3261_proc_fops = {
3368 .owner = THIS_MODULE,
3371 static int rt3261_proc_init(void)
3373 struct proc_dir_entry *rt3261_proc_entry;
3374 rt3261_proc_entry = create_proc_entry("driver/rt3261_ts", 0777, NULL);
3375 if(rt3261_proc_entry != NULL)
3377 rt3261_proc_entry->write_proc = rt3261_proc_write;
3382 printk("create proc error !\n");