2 * rt3261.c -- RT3261 ALSA SoC audio codec driver
4 * Copyright 2011 Realtek Semiconductor Corp.
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/soc-dapm.h>
25 #include <sound/initval.h>
26 #include <sound/tlv.h>
27 #include <mach/board.h>
28 #include <linux/clk.h>
29 #include <mach/iomux.h>
33 #include <linux/proc_fs.h>
34 #include <linux/seq_file.h>
35 #include <linux/vmalloc.h>
39 #define DIFFERENTIAL 1
44 static struct snd_soc_codec *rt3261_codec;
47 #define DBG(x...) printk(KERN_DEBUG x)
54 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
55 #include "rt_codec_ioctl.h"
56 #include "rt3261_ioctl.h"
61 #if defined (CONFIG_SND_SOC_RT3261)
62 #include "rt3261-dsp.h"
65 #define RT3261_REG_RW 1 /* for debug */
66 #define RT3261_DET_EXT_MIC 0
68 #define VERSION "RT3261_V1.3.0"
70 #if defined (CONFIG_SND_SOC_RT5623)
71 extern void rt5623_on(void);
72 extern void rt5623_off(void);
75 struct rt3261_init_reg {
80 static struct rt3261_init_reg init_list[] = {
81 {RT3261_GEN_CTRL1 , 0x3f01},//fa[12:13] = 1'b; fa[8~10]=1; fa[0]=1
82 {RT3261_ADDA_CLK1 , 0x1114},//73[2] = 1'b
83 {RT3261_MICBIAS , 0x3030},//93[5:4] = 11'b
84 {RT3261_CLS_D_OUT , 0xa000},//8d[11] = 0'b
85 {RT3261_CLS_D_OVCD , 0x0334},//8c[8] = 1'b
86 {RT3261_PRIV_INDEX , 0x001d},//PR1d[8] = 1'b;
87 {RT3261_PRIV_DATA , 0x0347},
88 {RT3261_PRIV_INDEX , 0x003d},//PR3d[12] = 0'b; PR3d[9] = 1'b
89 {RT3261_PRIV_DATA , 0x3600},
90 {RT3261_PRIV_INDEX , 0x0012},//PR12 = 0aa8'h
91 {RT3261_PRIV_DATA , 0x0aa8},
92 {RT3261_PRIV_INDEX , 0x0014},//PR14 = 8aaa'h
93 {RT3261_PRIV_DATA , 0x8aaa},
94 {RT3261_PRIV_INDEX , 0x0020},//PR20 = 6115'h
95 {RT3261_PRIV_DATA , 0x6115},
96 {RT3261_PRIV_INDEX , 0x0023},//PR23 = 0804'h
97 {RT3261_PRIV_DATA , 0x0804},
98 {RT3261_SPK_VOL , 0x8888},//SPKMIX -> SPKVOL
99 {RT3261_HP_VOL , 0x8888},
100 {RT3261_OUTPUT , 0x8888},//unmute OUTVOLL/R
101 {RT3261_SPO_CLSD_RATIO , 0x0001},
102 {RT3261_I2S1_SDP , 0xd000},
104 #define RT3261_INIT_REG_LEN ARRAY_SIZE(init_list)
106 static int rt3261_reg_init(struct snd_soc_codec *codec)
110 for (i = 0; i < RT3261_INIT_REG_LEN; i++)
111 snd_soc_write(codec, init_list[i].reg, init_list[i].val);
116 static int rt3261_customer_redefine(struct snd_soc_codec *codec, struct rt3261_priv *rt3261)
118 if(rt3261->spk_num==TWO_SPK)
120 snd_soc_update_bits(codec, RT3261_SPO_L_MIXER,
121 RT3261_M_SV_R_SPM_L | RT3261_M_SV_L_SPM_L,
122 1 << RT3261_M_SV_R_SPM_L_SFT | 0 << RT3261_M_SV_L_SPM_L_SFT);
123 snd_soc_update_bits(codec, RT3261_SPO_R_MIXER,
124 RT3261_M_SV_R_SPM_R, 0 << RT3261_M_SV_R_SPM_R_SFT);
128 snd_soc_update_bits(codec, RT3261_SPO_L_MIXER,
129 RT3261_M_SV_R_SPM_L | RT3261_M_SV_L_SPM_L,
130 0 << RT3261_M_SV_R_SPM_L_SFT | 0 << RT3261_M_SV_L_SPM_L_SFT);
131 snd_soc_update_bits(codec, RT3261_SPO_R_MIXER,
132 RT3261_M_SV_R_SPM_R, 1 << RT3261_M_SV_R_SPM_R_SFT);
136 snd_soc_update_bits(codec, RT3261_IN3_IN4,
137 RT3261_IN_DF2, rt3261->modem_input_mode << RT3261_IN_SFT2);
138 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
139 RT3261_LOUT_DF_MASK, rt3261->lout_to_modem_mode << RT3261_LOUT_DF);
140 snd_soc_update_bits(codec, RT3261_SPO_CLSD_RATIO,
141 RT3261_SPO_CLSD_RATIO_MASK, rt3261->spk_amplify);
142 snd_soc_update_bits(codec, RT3261_DIG_INF_DATA,
143 RT3261_IF1_DAC_SEL_MASK | RT3261_IF2_DAC_SEL_MASK,
144 (rt3261->playback_if1_data_control<<RT3261_IF1_DAC_SEL_SFT) | (rt3261->playback_if2_data_control<<RT3261_IF2_DAC_SEL_SFT));
150 static int rt3261_index_sync(struct snd_soc_codec *codec)
154 for (i = 0; i < RT3261_INIT_REG_LEN; i++)
155 if (RT3261_PRIV_INDEX == init_list[i].reg ||
156 RT3261_PRIV_DATA == init_list[i].reg)
157 snd_soc_write(codec, init_list[i].reg,
162 static const u16 rt3261_reg[RT3261_VENDOR_ID2 + 1] = {
163 [RT3261_RESET] = 0x000c,
164 [RT3261_SPK_VOL] = 0xc8c8,
165 [RT3261_HP_VOL] = 0xc8c8,
166 [RT3261_OUTPUT] = 0xc8c8,
167 [RT3261_MONO_OUT] = 0x8000,
168 [RT3261_INL_INR_VOL] = 0x0808,
169 [RT3261_DAC1_DIG_VOL] = 0xafaf,
170 [RT3261_DAC2_DIG_VOL] = 0xafaf,
171 [RT3261_ADC_DIG_VOL] = 0x2f2f,
172 [RT3261_ADC_DATA] = 0x2f2f,
173 [RT3261_STO_ADC_MIXER] = 0x7060,
174 [RT3261_MONO_ADC_MIXER] = 0x7070,
175 [RT3261_AD_DA_MIXER] = 0x8080,
176 [RT3261_STO_DAC_MIXER] = 0x5454,
177 [RT3261_MONO_DAC_MIXER] = 0x5454,
178 [RT3261_DIG_MIXER] = 0xaa00,
179 [RT3261_DSP_PATH2] = 0xa000,
180 [RT3261_REC_L2_MIXER] = 0x007f,
181 [RT3261_REC_R2_MIXER] = 0x007f,
182 [RT3261_HPO_MIXER] = 0xe000,
183 [RT3261_SPK_L_MIXER] = 0x003e,
184 [RT3261_SPK_R_MIXER] = 0x003e,
185 [RT3261_SPO_L_MIXER] = 0xf800,
186 [RT3261_SPO_R_MIXER] = 0x3800,
187 [RT3261_SPO_CLSD_RATIO] = 0x0004,
188 [RT3261_MONO_MIXER] = 0xfc00,
189 [RT3261_OUT_L3_MIXER] = 0x01ff,
190 [RT3261_OUT_R3_MIXER] = 0x01ff,
191 [RT3261_LOUT_MIXER] = 0xf000,
192 [RT3261_PWR_ANLG1] = 0x00c0,
193 [RT3261_I2S1_SDP] = 0x8000,
194 [RT3261_I2S2_SDP] = 0x8000,
195 [RT3261_I2S3_SDP] = 0x8000,
196 [RT3261_ADDA_CLK1] = 0x1110,
197 [RT3261_ADDA_CLK2] = 0x0c00,
198 [RT3261_DMIC] = 0x1d00,
199 [RT3261_ASRC_3] = 0x0008,
200 [RT3261_HP_OVCD] = 0x0600,
201 [RT3261_CLS_D_OVCD] = 0x0228,
202 [RT3261_CLS_D_OUT] = 0xa800,
203 [RT3261_DEPOP_M1] = 0x0004,
204 [RT3261_DEPOP_M2] = 0x1100,
205 [RT3261_DEPOP_M3] = 0x0646,
206 [RT3261_CHARGE_PUMP] = 0x0c00,
207 [RT3261_MICBIAS] = 0x3000,
208 [RT3261_EQ_CTRL1] = 0x2080,
209 [RT3261_DRC_AGC_1] = 0x2206,
210 [RT3261_DRC_AGC_2] = 0x1f00,
211 [RT3261_ANC_CTRL1] = 0x034b,
212 [RT3261_ANC_CTRL2] = 0x0066,
213 [RT3261_ANC_CTRL3] = 0x000b,
214 [RT3261_GPIO_CTRL1] = 0x0400,
215 [RT3261_DSP_CTRL3] = 0x2000,
216 [RT3261_BASE_BACK] = 0x0013,
217 [RT3261_MP3_PLUS1] = 0x0680,
218 [RT3261_MP3_PLUS2] = 0x1c17,
219 [RT3261_3D_HP] = 0x8c00,
220 [RT3261_ADJ_HPF] = 0x2a20,
221 [RT3261_HP_CALIB_AMP_DET] = 0x0400,
222 [RT3261_SV_ZCD1] = 0x0809,
223 [RT3261_VENDOR_ID1] = 0x10ec,
224 [RT3261_VENDOR_ID2] = 0x6231,
227 static int rt3261_reset(struct snd_soc_codec *codec)
229 return snd_soc_write(codec, RT3261_RESET, 0);
232 static unsigned int rt3261_read(struct snd_soc_codec *codec,
237 val = codec->hw_read(codec, reg);
241 static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
242 unsigned int value, const void *data, int len)
246 if (!snd_soc_codec_volatile_register(codec, reg) &&
247 reg < codec->driver->reg_cache_size &&
248 !codec->cache_bypass) {
249 ret = snd_soc_cache_write(codec, reg, value);
254 if (codec->cache_only) {
255 codec->cache_sync = 1;
259 ret = i2c_master_normal_send(codec->control_data, data, len,400*1000);
268 static int rt3261_write(struct snd_soc_codec *codec, unsigned int reg,
274 data[1] = (value >> 8) & 0xff;
275 data[2] = value & 0xff;
277 DBG("rt3261_write 0x%x = 0x%x\n",reg,value);
278 return do_hw_write(codec, reg, value, data, 3);
282 * rt3261_index_write - Write private register.
283 * @codec: SoC audio codec device.
284 * @reg: Private register index.
285 * @value: Private register Data.
287 * Modify private register for advanced setting. It can be written through
288 * private index (0x6a) and data (0x6c) register.
290 * Returns 0 for success or negative error code.
292 static int rt3261_index_write(struct snd_soc_codec *codec,
293 unsigned int reg, unsigned int value)
297 ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
299 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
302 ret = snd_soc_write(codec, RT3261_PRIV_DATA, value);
304 dev_err(codec->dev, "Failed to set private value: %d\n", ret);
314 * rt3261_index_read - Read private register.
315 * @codec: SoC audio codec device.
316 * @reg: Private register index.
318 * Read advanced setting from private register. It can be read through
319 * private index (0x6a) and data (0x6c) register.
321 * Returns private register value or negative error code.
323 static unsigned int rt3261_index_read(
324 struct snd_soc_codec *codec, unsigned int reg)
328 ret = snd_soc_write(codec, RT3261_PRIV_INDEX, reg);
330 dev_err(codec->dev, "Failed to set private addr: %d\n", ret);
333 return snd_soc_read(codec, RT3261_PRIV_DATA);
337 * rt3261_index_update_bits - update private register bits
338 * @codec: audio codec
339 * @reg: Private register index.
340 * @mask: register mask
343 * Writes new register value.
345 * Returns 1 for change, 0 for no change, or negative error code.
347 static int rt3261_index_update_bits(struct snd_soc_codec *codec,
348 unsigned int reg, unsigned int mask, unsigned int value)
350 unsigned int old, new;
353 ret = rt3261_index_read(codec, reg);
355 dev_err(codec->dev, "Failed to read private reg: %d\n", ret);
360 new = (old & ~mask) | (value & mask);
363 ret = rt3261_index_write(codec, reg, new);
366 "Failed to write private reg: %d\n", ret);
376 static int rt3261_volatile_register(
377 struct snd_soc_codec *codec, unsigned int reg)
381 case RT3261_PRIV_DATA:
383 case RT3261_EQ_CTRL1:
384 case RT3261_DRC_AGC_1:
385 case RT3261_ANC_CTRL1:
386 case RT3261_IRQ_CTRL2:
387 case RT3261_INT_IRQ_ST:
388 case RT3261_DSP_CTRL2:
389 case RT3261_DSP_CTRL3:
390 case RT3261_PGM_REG_ARR1:
391 case RT3261_PGM_REG_ARR3:
392 case RT3261_VENDOR_ID:
393 case RT3261_VENDOR_ID1:
394 case RT3261_VENDOR_ID2:
401 static int rt3261_readable_register(
402 struct snd_soc_codec *codec, unsigned int reg)
409 case RT3261_MONO_OUT:
412 case RT3261_INL_INR_VOL:
413 case RT3261_DAC1_DIG_VOL:
414 case RT3261_DAC2_DIG_VOL:
415 case RT3261_DAC2_CTRL:
416 case RT3261_ADC_DIG_VOL:
417 case RT3261_ADC_DATA:
418 case RT3261_ADC_BST_VOL:
419 case RT3261_STO_ADC_MIXER:
420 case RT3261_MONO_ADC_MIXER:
421 case RT3261_AD_DA_MIXER:
422 case RT3261_STO_DAC_MIXER:
423 case RT3261_MONO_DAC_MIXER:
424 case RT3261_DIG_MIXER:
425 case RT3261_DSP_PATH1:
426 case RT3261_DSP_PATH2:
427 case RT3261_DIG_INF_DATA:
428 case RT3261_REC_L1_MIXER:
429 case RT3261_REC_L2_MIXER:
430 case RT3261_REC_R1_MIXER:
431 case RT3261_REC_R2_MIXER:
432 case RT3261_HPO_MIXER:
433 case RT3261_SPK_L_MIXER:
434 case RT3261_SPK_R_MIXER:
435 case RT3261_SPO_L_MIXER:
436 case RT3261_SPO_R_MIXER:
437 case RT3261_SPO_CLSD_RATIO:
438 case RT3261_MONO_MIXER:
439 case RT3261_OUT_L1_MIXER:
440 case RT3261_OUT_L2_MIXER:
441 case RT3261_OUT_L3_MIXER:
442 case RT3261_OUT_R1_MIXER:
443 case RT3261_OUT_R2_MIXER:
444 case RT3261_OUT_R3_MIXER:
445 case RT3261_LOUT_MIXER:
446 case RT3261_PWR_DIG1:
447 case RT3261_PWR_DIG2:
448 case RT3261_PWR_ANLG1:
449 case RT3261_PWR_ANLG2:
450 case RT3261_PWR_MIXER:
452 case RT3261_PRIV_INDEX:
453 case RT3261_PRIV_DATA:
454 case RT3261_I2S1_SDP:
455 case RT3261_I2S2_SDP:
456 case RT3261_I2S3_SDP:
457 case RT3261_ADDA_CLK1:
458 case RT3261_ADDA_CLK2:
461 case RT3261_PLL_CTRL1:
462 case RT3261_PLL_CTRL2:
469 case RT3261_CLS_D_OVCD:
470 case RT3261_CLS_D_OUT:
471 case RT3261_DEPOP_M1:
472 case RT3261_DEPOP_M2:
473 case RT3261_DEPOP_M3:
474 case RT3261_CHARGE_PUMP:
475 case RT3261_PV_DET_SPK_G:
477 case RT3261_EQ_CTRL1:
478 case RT3261_EQ_CTRL2:
479 case RT3261_WIND_FILTER:
480 case RT3261_DRC_AGC_1:
481 case RT3261_DRC_AGC_2:
482 case RT3261_DRC_AGC_3:
484 case RT3261_ANC_CTRL1:
485 case RT3261_ANC_CTRL2:
486 case RT3261_ANC_CTRL3:
489 case RT3261_IRQ_CTRL1:
490 case RT3261_IRQ_CTRL2:
491 case RT3261_INT_IRQ_ST:
492 case RT3261_GPIO_CTRL1:
493 case RT3261_GPIO_CTRL2:
494 case RT3261_GPIO_CTRL3:
495 case RT3261_DSP_CTRL1:
496 case RT3261_DSP_CTRL2:
497 case RT3261_DSP_CTRL3:
498 case RT3261_DSP_CTRL4:
499 case RT3261_PGM_REG_ARR1:
500 case RT3261_PGM_REG_ARR2:
501 case RT3261_PGM_REG_ARR3:
502 case RT3261_PGM_REG_ARR4:
503 case RT3261_PGM_REG_ARR5:
504 case RT3261_SCB_FUNC:
505 case RT3261_SCB_CTRL:
506 case RT3261_BASE_BACK:
507 case RT3261_MP3_PLUS1:
508 case RT3261_MP3_PLUS2:
511 case RT3261_HP_CALIB_AMP_DET:
512 case RT3261_HP_CALIB2:
515 case RT3261_GEN_CTRL1:
516 case RT3261_GEN_CTRL2:
517 case RT3261_GEN_CTRL3:
518 case RT3261_VENDOR_ID:
519 case RT3261_VENDOR_ID1:
520 case RT3261_VENDOR_ID2:
527 void codec_set_spk(bool on)
530 struct snd_soc_codec *codec = rt3261_codec;
531 DBG("%s: %d\n", __func__, on);
536 mutex_lock(&codec->mutex);
538 DBG("snd_soc_dapm_enable_pin\n");
539 snd_soc_dapm_enable_pin(&codec->dapm, "Headphone Jack");
540 snd_soc_dapm_enable_pin(&codec->dapm, "Ext Spk");
542 DBG("snd_soc_dapm_disable_pin\n");
543 snd_soc_dapm_disable_pin(&codec->dapm, "Headphone Jack");
544 snd_soc_dapm_disable_pin(&codec->dapm, "Ext Spk");
546 snd_soc_dapm_sync(&codec->dapm);
547 mutex_unlock(&codec->mutex);
553 * rt3261_headset_mic_detect - Detect headset.
554 * @codec: SoC audio codec device.
555 * @jack_insert: Jack insert or not.
557 * Detect whether is headset or not when jack inserted.
559 * Returns detect status.
561 int rt3261_headset_mic_detect(int jack_insert)
569 if (SND_SOC_BIAS_OFF == rt3261_codec->dapm.bias_level) {
570 snd_soc_write(rt3261_codec, RT3261_PWR_ANLG1, 0x2004);
571 snd_soc_write(rt3261_codec, RT3261_MICBIAS, 0x3830);
572 snd_soc_write(rt3261_codec, RT3261_GEN_CTRL1 , 0x3701);
575 sclk_src = snd_soc_read(rt3261_codec, RT3261_GLB_CLK) &
576 RT3261_SCLK_SRC_MASK;
577 snd_soc_update_bits(rt3261_codec, RT3261_GLB_CLK,
578 RT3261_SCLK_SRC_MASK, 0x3 << RT3261_SCLK_SRC_SFT);
580 snd_soc_update_bits(rt3261_codec, RT3261_PWR_ANLG1,
581 RT3261_PWR_LDO2, RT3261_PWR_LDO2);
582 snd_soc_update_bits(rt3261_codec, RT3261_PWR_ANLG2,
583 RT3261_PWR_MB1, RT3261_PWR_MB1);
585 snd_soc_update_bits(rt3261_codec, RT3261_MICBIAS,
586 RT3261_MIC1_OVCD_MASK | RT3261_MIC1_OVTH_MASK |
587 RT3261_PWR_CLK25M_MASK | RT3261_PWR_MB_MASK,
588 RT3261_MIC1_OVCD_EN | RT3261_MIC1_OVTH_600UA |
589 RT3261_PWR_MB_PU | RT3261_PWR_CLK25M_PU);
590 snd_soc_update_bits(rt3261_codec, RT3261_GEN_CTRL1,
593 if (snd_soc_read(rt3261_codec, RT3261_IRQ_CTRL2) & 0x8)
594 jack_type = RT3261_HEADPHO_DET;
596 jack_type = RT3261_HEADSET_DET;
597 snd_soc_update_bits(rt3261_codec, RT3261_IRQ_CTRL2,
598 RT3261_MB1_OC_CLR, 0);
600 snd_soc_update_bits(rt3261_codec, RT3261_GLB_CLK,
601 RT3261_SCLK_SRC_MASK, sclk_src);
604 snd_soc_update_bits(rt3261_codec, RT3261_MICBIAS,
605 RT3261_MIC1_OVCD_MASK,
606 RT3261_MIC1_OVCD_DIS);
608 jack_type = RT3261_NO_JACK;
613 EXPORT_SYMBOL(rt3261_headset_mic_detect);
615 static const char *rt3261_dacr2_src[] = { "TxDC_R", "TxDP_R" };
617 static const SOC_ENUM_SINGLE_DECL(rt3261_dacr2_enum,RT3261_DUMMY_PR3F,
618 14, rt3261_dacr2_src);
619 static const struct snd_kcontrol_new rt3261_dacr2_mux =
620 SOC_DAPM_ENUM("Mono dacr source", rt3261_dacr2_enum);
622 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
623 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
624 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
625 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
626 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
628 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
629 static unsigned int bst_tlv[] = {
630 TLV_DB_RANGE_HEAD(7),
631 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
632 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
633 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
634 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
635 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
636 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
637 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
640 static int rt3261_dmic_get(struct snd_kcontrol *kcontrol,
641 struct snd_ctl_elem_value *ucontrol)
643 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
644 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
646 ucontrol->value.integer.value[0] = rt3261->dmic_en;
651 static int rt3261_dmic_put(struct snd_kcontrol *kcontrol,
652 struct snd_ctl_elem_value *ucontrol)
654 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
655 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
657 if (rt3261->dmic_en == ucontrol->value.integer.value[0])
660 rt3261->dmic_en = ucontrol->value.integer.value[0];
661 switch (rt3261->dmic_en) {
662 case RT3261_DMIC_DIS:
663 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
664 RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK |
666 RT3261_GP2_PIN_GPIO2 | RT3261_GP3_PIN_GPIO3 |
667 RT3261_GP4_PIN_GPIO4);
668 snd_soc_update_bits(codec, RT3261_DMIC,
669 RT3261_DMIC_1_DP_MASK | RT3261_DMIC_2_DP_MASK,
670 RT3261_DMIC_1_DP_GPIO3 | RT3261_DMIC_2_DP_GPIO4);
671 snd_soc_update_bits(codec, RT3261_DMIC,
672 RT3261_DMIC_1_EN_MASK | RT3261_DMIC_2_EN_MASK,
673 RT3261_DMIC_1_DIS | RT3261_DMIC_2_DIS);
677 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
678 RT3261_GP2_PIN_MASK | RT3261_GP3_PIN_MASK,
679 RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP3_PIN_DMIC1_SDA);
680 snd_soc_update_bits(codec, RT3261_DMIC,
681 RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK |
682 RT3261_DMIC_1_DP_MASK,
683 RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING |
684 RT3261_DMIC_1_DP_IN1P);
685 snd_soc_update_bits(codec, RT3261_DMIC,
686 RT3261_DMIC_1_EN_MASK, RT3261_DMIC_1_EN);
690 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
691 RT3261_GP2_PIN_MASK | RT3261_GP4_PIN_MASK,
692 RT3261_GP2_PIN_DMIC1_SCL | RT3261_GP4_PIN_DMIC2_SDA);
693 snd_soc_update_bits(codec, RT3261_DMIC,
694 RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK |
695 RT3261_DMIC_2_DP_MASK,
696 RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING |
697 RT3261_DMIC_2_DP_IN1N);
698 snd_soc_update_bits(codec, RT3261_DMIC,
699 RT3261_DMIC_2_EN_MASK, RT3261_DMIC_2_EN);
711 static int rt3261_mic1_get(struct snd_kcontrol *kcontrol,
712 struct snd_ctl_elem_value *ucontrol)
714 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
716 ucontrol->value.integer.value[0] =
717 (snd_soc_read(codec, RT3261_REC_L2_MIXER) & RT3261_M_BST1_RM_L) >> RT3261_M_BST1_RM_L_SFT;
722 static int rt3261_mic1_put(struct snd_kcontrol *kcontrol,
723 struct snd_ctl_elem_value *ucontrol)
725 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
727 if(ucontrol->value.integer.value[0]) {
728 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
729 RT3261_M_BST1_RM_L, 0);
730 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
731 RT3261_M_BST1_RM_R, 0);
733 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
734 RT3261_M_BST1_RM_L, RT3261_M_BST1_RM_L);
735 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
736 RT3261_M_BST1_RM_R, RT3261_M_BST1_RM_R);
742 static int rt3261_mic2_get(struct snd_kcontrol *kcontrol,
743 struct snd_ctl_elem_value *ucontrol)
745 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
747 ucontrol->value.integer.value[0] =
748 (snd_soc_read(codec, RT3261_REC_L2_MIXER) & RT3261_M_BST1_RM_L) >> RT3261_M_BST1_RM_L_SFT;
753 static int rt3261_mic2_put(struct snd_kcontrol *kcontrol,
754 struct snd_ctl_elem_value *ucontrol)
756 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
758 if(ucontrol->value.integer.value[0]) {
759 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
760 RT3261_M_BST4_RM_L, 0);
761 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
762 RT3261_M_BST4_RM_R, 0);
764 snd_soc_update_bits(codec, RT3261_REC_L2_MIXER,
765 RT3261_M_BST4_RM_L, RT3261_M_BST4_RM_L);
766 snd_soc_update_bits(codec, RT3261_REC_R2_MIXER,
767 RT3261_M_BST4_RM_R, RT3261_M_BST4_RM_R);
775 void hp_amp_power(struct snd_soc_codec *codec, int on)
777 static int hp_amp_power_count;
778 printk("hp_amp_power on=%d hp_amp_power_count=%d\n",on,hp_amp_power_count);
781 if(hp_amp_power_count <= 0) {
782 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
783 RT3261_PWR_I2S1, RT3261_PWR_I2S1);
784 /* depop parameters */
785 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
786 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
787 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
788 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
789 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
790 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
791 /* headphone amp power on */
792 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
793 RT3261_PWR_FV1 | RT3261_PWR_FV2 , 0);
794 snd_soc_update_bits(codec, RT3261_PWR_VOL,
795 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
796 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
797 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
798 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA , //bard 10-18
799 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA); //bard 10-18
801 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
802 RT3261_PWR_FV1 | RT3261_PWR_FV2,
803 RT3261_PWR_FV1 | RT3261_PWR_FV2);
805 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
806 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
807 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
808 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
809 RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
810 RT3261_HP_CO_EN | RT3261_HP_SG_EN);
812 hp_amp_power_count++;
814 hp_amp_power_count--;
815 if(hp_amp_power_count <= 0) {
816 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
817 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
818 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
819 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
820 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
821 /* headphone amp power down */
822 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
823 RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
824 RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
825 RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
826 RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
827 RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
828 RT3261_HP_SG_EN | RT3261_HP_CB_PD);
829 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
830 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA , //bard 10-18
836 static int rt3261_hp_mute_get(struct snd_kcontrol *kcontrol,
837 struct snd_ctl_elem_value *ucontrol)
839 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
841 ucontrol->value.integer.value[0] =
842 !((snd_soc_read(codec, RT3261_HP_VOL) & RT3261_L_MUTE) >> RT3261_L_MUTE_SFT);
847 static int rt3261_hp_mute_put(struct snd_kcontrol *kcontrol,
848 struct snd_ctl_elem_value *ucontrol)
850 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
852 if(ucontrol->value.integer.value[0]) {
853 /* headphone unmute sequence */
854 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
855 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
856 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
857 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
858 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
859 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
860 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
861 RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
862 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
863 RT3261_RSTN_MASK, RT3261_RSTN_EN);
864 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
865 RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
866 RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
867 snd_soc_update_bits(codec, RT3261_HP_VOL,
868 RT3261_L_MUTE | RT3261_R_MUTE, 0);
870 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
871 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
872 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
873 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
876 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
877 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
880 /* headphone mute sequence */
881 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
882 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
883 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
884 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
885 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
886 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
887 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
888 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
889 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
890 RT3261_RSTP_MASK, RT3261_RSTP_EN);
891 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
892 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
893 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
894 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
896 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
897 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
900 snd_soc_update_bits(codec, RT3261_HP_VOL,
901 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
903 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
904 RT3261_HP_R_SMT_MASK | RT3261_HP_L_SMT_MASK,
905 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
910 #if defined (CONFIG_SND_SOC_RT5623)
911 static int rt3261_modem_input_switch_get(struct snd_kcontrol *kcontrol,
912 struct snd_ctl_elem_value *ucontrol)
914 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
915 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
917 ucontrol->value.integer.value[0] = rt3261->modem_is_open;
921 static int rt3261_modem_input_switch_put(struct snd_kcontrol *kcontrol,
922 struct snd_ctl_elem_value *ucontrol)
924 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
925 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
927 if(ucontrol->value.integer.value[0]) {
929 rt3261->modem_is_open = 1;
932 rt3261->modem_is_open = 0;
938 static int rt3261_modem_input_switch_get(struct snd_kcontrol *kcontrol,
939 struct snd_ctl_elem_value *ucontrol)
944 static int rt3261_modem_input_switch_put(struct snd_kcontrol *kcontrol,
945 struct snd_ctl_elem_value *ucontrol)
951 static int rt3261_dacr_sel_get(struct snd_kcontrol *kcontrol,
952 struct snd_ctl_elem_value *ucontrol)
954 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
956 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x4000) >> 14;
961 static int rt3261_dacr_sel_put(struct snd_kcontrol *kcontrol,
962 struct snd_ctl_elem_value *ucontrol)
964 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
966 if(ucontrol->value.integer.value[0])
967 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x4000, 0x4000);
969 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x4000, 0x0);
975 static int rt3261_rxdp_sel_get(struct snd_kcontrol *kcontrol,
976 struct snd_ctl_elem_value *ucontrol)
978 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
980 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x0400) >> 10;
985 static int rt3261_rxdp_sel_put(struct snd_kcontrol *kcontrol,
986 struct snd_ctl_elem_value *ucontrol)
988 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
990 if(ucontrol->value.integer.value[0])
991 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0400, 0x0400);
993 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0400, 0x0);
999 static int rt3261_rxdp1_sel_get(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1002 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1004 ucontrol->value.integer.value[0] = (rt3261_index_read(codec, RT3261_MIXER_INT_REG) & 0x0200) >> 9;
1009 static int rt3261_rxdp1_sel_put(struct snd_kcontrol *kcontrol,
1010 struct snd_ctl_elem_value *ucontrol)
1012 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1014 if(ucontrol->value.integer.value[0])
1015 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0200, 0x0200);
1017 rt3261_index_update_bits(codec, RT3261_MIXER_INT_REG, 0x0200, 0x0);
1023 /* IN1/IN2 Input Type */
1024 static const char *rt3261_input_mode[] = {
1025 "Single ended", "Differential"};
1027 static const SOC_ENUM_SINGLE_DECL(
1028 rt3261_in1_mode_enum, RT3261_IN1_IN2,
1029 RT3261_IN_SFT1, rt3261_input_mode);
1031 static const SOC_ENUM_SINGLE_DECL(
1032 rt3261_in2_mode_enum, RT3261_IN3_IN4,
1033 RT3261_IN_SFT2, rt3261_input_mode);
1035 static const SOC_ENUM_SINGLE_DECL(
1036 rt3261_in3_mode_enum, RT3261_IN1_IN2,
1037 RT3261_IN_SFT2, rt3261_input_mode);
1040 static const char *rt3261_output_mode[] = {
1041 "Single ended", "Differential"};
1043 static const SOC_ENUM_SINGLE_DECL(
1044 rt3261_lout_mode_enum, RT3261_GEN_CTRL1,
1045 RT3261_LOUT_DF, rt3261_output_mode);
1048 /* Interface data select */
1049 static const char *rt3261_data_select[] = {
1050 "Normal", "Swap", "left copy to right", "right copy to left"};
1052 static const SOC_ENUM_SINGLE_DECL(rt3261_if1_dac_enum, RT3261_DIG_INF_DATA,
1053 RT3261_IF1_DAC_SEL_SFT, rt3261_data_select);
1055 static const SOC_ENUM_SINGLE_DECL(rt3261_if1_adc_enum, RT3261_DIG_INF_DATA,
1056 RT3261_IF1_ADC_SEL_SFT, rt3261_data_select);
1058 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_dac_enum, RT3261_DIG_INF_DATA,
1059 RT3261_IF2_DAC_SEL_SFT, rt3261_data_select);
1061 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_enum, RT3261_DIG_INF_DATA,
1062 RT3261_IF2_ADC_SEL_SFT, rt3261_data_select);
1064 static const SOC_ENUM_SINGLE_DECL(rt3261_if3_dac_enum, RT3261_DIG_INF_DATA,
1065 RT3261_IF3_DAC_SEL_SFT, rt3261_data_select);
1067 static const SOC_ENUM_SINGLE_DECL(rt3261_if3_adc_enum, RT3261_DIG_INF_DATA,
1068 RT3261_IF3_ADC_SEL_SFT, rt3261_data_select);
1070 /* Class D speaker gain ratio */
1071 static const char *rt3261_clsd_spk_ratio[] = {"1.66x", "1.83x", "1.94x", "2x",
1072 "2.11x", "2.22x", "2.33x", "2.44x", "2.55x", "2.66x", "2.77x"};
1074 static const SOC_ENUM_SINGLE_DECL(
1075 rt3261_clsd_spk_ratio_enum, RT3261_CLS_D_OUT,
1076 RT3261_CLSD_RATIO_SFT, rt3261_clsd_spk_ratio);
1079 static const char *rt3261_dmic_mode[] = {"Disable", "DMIC1", "DMIC2"};
1081 static const SOC_ENUM_SINGLE_DECL(rt3261_dmic_enum, 0, 0, rt3261_dmic_mode);
1084 static const char *rt3261_dacr_sel_mode[] = {"IF2_DAC", "IF2_ADC"};
1086 static const SOC_ENUM_SINGLE_DECL(rt3261_dacr_sel_enum, 0, 0, rt3261_dacr_sel_mode);
1088 static const char *rt3261_rxdp_sel_mode[] = {"RxDP2", "RxDP1"};
1090 static const SOC_ENUM_SINGLE_DECL(rt3261_rxdp_sel_enum, 0, 0, rt3261_rxdp_sel_mode);
1092 static const char *rt3261_rxdp1_sel_mode[] = {"DAC1", "IF1_DAC"};
1094 static const SOC_ENUM_SINGLE_DECL(rt3261_rxdp1_sel_enum, 0, 0, rt3261_rxdp1_sel_mode);
1099 static const char *rt3261_mic_mode[] = {"off", "on",};
1101 static const SOC_ENUM_SINGLE_DECL(rt3261_mic_enum, 0, 0, rt3261_mic_mode);
1105 static const char *rt3261_hp_mute_mode[] = {"off", "on",};
1107 static const SOC_ENUM_SINGLE_DECL(rt3261_hp_mute_enum, 0, 0, rt3261_hp_mute_mode);
1109 static const char *rt3261_modem_input_switch_mode[] = {"off", "on",};
1111 static const SOC_ENUM_SINGLE_DECL(rt3261_modem_input_switch_enum, 0, 0, rt3261_modem_input_switch_mode);
1113 #ifdef RT3261_REG_RW
1114 #define REGVAL_MAX 0xffff
1115 static unsigned int regctl_addr;
1116 static int rt3261_regctl_info(struct snd_kcontrol *kcontrol,
1117 struct snd_ctl_elem_info *uinfo)
1119 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1121 uinfo->value.integer.min = 0;
1122 uinfo->value.integer.max = REGVAL_MAX;
1126 static int rt3261_regctl_get(struct snd_kcontrol *kcontrol,
1127 struct snd_ctl_elem_value *ucontrol)
1129 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1130 ucontrol->value.integer.value[0] = regctl_addr;
1131 ucontrol->value.integer.value[1] = snd_soc_read(codec, regctl_addr);
1135 static int rt3261_regctl_put(struct snd_kcontrol *kcontrol,
1136 struct snd_ctl_elem_value *ucontrol)
1138 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1139 regctl_addr = ucontrol->value.integer.value[0];
1140 if(ucontrol->value.integer.value[1] <= REGVAL_MAX)
1141 snd_soc_write(codec, regctl_addr, ucontrol->value.integer.value[1]);
1147 static int rt3261_vol_rescale_get(struct snd_kcontrol *kcontrol,
1148 struct snd_ctl_elem_value *ucontrol)
1150 struct soc_mixer_control *mc =
1151 (struct soc_mixer_control *)kcontrol->private_value;
1152 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1153 unsigned int val = snd_soc_read(codec, mc->reg);
1155 ucontrol->value.integer.value[0] = RT3261_VOL_RSCL_MAX -
1156 ((val & RT3261_L_VOL_MASK) >> mc->shift);
1157 ucontrol->value.integer.value[1] = RT3261_VOL_RSCL_MAX -
1158 (val & RT3261_R_VOL_MASK);
1163 static int rt3261_vol_rescale_put(struct snd_kcontrol *kcontrol,
1164 struct snd_ctl_elem_value *ucontrol)
1166 struct soc_mixer_control *mc =
1167 (struct soc_mixer_control *)kcontrol->private_value;
1168 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1169 unsigned int val, val2;
1171 val = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[0];
1172 val2 = RT3261_VOL_RSCL_MAX - ucontrol->value.integer.value[1];
1173 return snd_soc_update_bits_locked(codec, mc->reg, RT3261_L_VOL_MASK |
1174 RT3261_R_VOL_MASK, val << mc->shift | val2);
1178 static const struct snd_kcontrol_new rt3261_snd_controls[] = {
1179 /* Speaker Output Volume */
1180 SOC_DOUBLE("Speaker Playback Switch", RT3261_SPK_VOL,
1181 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1182 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT3261_SPK_VOL,
1183 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1184 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1185 SOC_DOUBLE_EXT_TLV("Earpiece Playback Volume", RT3261_SPK_VOL,
1186 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1187 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1188 /* Headphone Output Volume */
1189 SOC_DOUBLE("HP Playback Switch", RT3261_HP_VOL,
1190 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1191 SOC_DOUBLE_EXT_TLV("Headphone Playback Volume", RT3261_HP_VOL,
1192 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, RT3261_VOL_RSCL_RANGE, 0,
1193 rt3261_vol_rescale_get, rt3261_vol_rescale_put, out_vol_tlv),
1194 /* OUTPUT Control */
1195 SOC_DOUBLE("OUT Playback Switch", RT3261_OUTPUT,
1196 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1197 SOC_DOUBLE("OUT Channel Switch", RT3261_OUTPUT,
1198 RT3261_VOL_L_SFT, RT3261_VOL_R_SFT, 1, 1),
1199 SOC_DOUBLE_TLV("OUT Playback Volume", RT3261_OUTPUT,
1200 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT, 39, 1, out_vol_tlv),
1201 /* MONO Output Control */
1202 SOC_SINGLE("Mono Playback Switch", RT3261_MONO_OUT,
1203 RT3261_L_MUTE_SFT, 1, 1),
1204 /* DAC Digital Volume */
1205 SOC_DOUBLE("DAC2 Playback Switch", RT3261_DAC2_CTRL,
1206 RT3261_M_DAC_L2_VOL_SFT, RT3261_M_DAC_R2_VOL_SFT, 1, 1),
1207 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT3261_DAC1_DIG_VOL,
1208 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1209 175, 0, dac_vol_tlv),
1210 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT3261_DAC2_DIG_VOL,
1211 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1212 175, 0, dac_vol_tlv),
1213 /* IN1/IN2 Control */
1214 SOC_ENUM("IN1 Mode Control", rt3261_in1_mode_enum),
1215 SOC_SINGLE_TLV("IN1 Boost", RT3261_IN1_IN2,
1216 RT3261_BST_SFT1, 8, 0, bst_tlv),
1217 SOC_ENUM("IN2 Mode Control", rt3261_in2_mode_enum),
1218 SOC_SINGLE_TLV("IN2 Boost", RT3261_IN3_IN4,
1219 RT3261_BST_SFT2, 8, 0, bst_tlv),
1220 SOC_ENUM("IN3 Mode Control", rt3261_in3_mode_enum),
1221 SOC_SINGLE_TLV("IN3 Boost", RT3261_IN1_IN2,
1222 RT3261_BST_SFT2, 8, 0, bst_tlv),
1224 SOC_ENUM("LOUT Mode Control", rt3261_lout_mode_enum),
1225 /* INL/INR Volume Control */
1226 SOC_DOUBLE_TLV("IN Capture Volume", RT3261_INL_INR_VOL,
1227 RT3261_INL_VOL_SFT, RT3261_INR_VOL_SFT,
1229 /* ADC Digital Volume Control */
1230 SOC_DOUBLE("ADC Capture Switch", RT3261_ADC_DIG_VOL,
1231 RT3261_L_MUTE_SFT, RT3261_R_MUTE_SFT, 1, 1),
1232 SOC_DOUBLE_TLV("ADC Capture Volume", RT3261_ADC_DIG_VOL,
1233 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1234 127, 0, adc_vol_tlv),
1235 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT3261_ADC_DATA,
1236 RT3261_L_VOL_SFT, RT3261_R_VOL_SFT,
1237 127, 0, adc_vol_tlv),
1238 /* ADC Boost Volume Control */
1239 SOC_DOUBLE_TLV("ADC Boost Gain", RT3261_ADC_BST_VOL,
1240 RT3261_ADC_L_BST_SFT, RT3261_ADC_R_BST_SFT,
1242 /* Class D speaker gain ratio */
1243 SOC_ENUM("Class D SPK Ratio Control", rt3261_clsd_spk_ratio_enum),
1245 SOC_ENUM_EXT("DMIC Switch", rt3261_dmic_enum,
1246 rt3261_dmic_get, rt3261_dmic_put),
1249 SOC_ENUM_EXT("DACR Select", rt3261_dacr_sel_enum,
1250 rt3261_dacr_sel_get, rt3261_dacr_sel_put),
1251 SOC_ENUM_EXT("RxDP Select", rt3261_rxdp_sel_enum,
1252 rt3261_rxdp_sel_get, rt3261_rxdp_sel_put),
1253 SOC_ENUM_EXT("RxDP1 Select", rt3261_rxdp1_sel_enum,
1254 rt3261_rxdp1_sel_get, rt3261_rxdp1_sel_put),
1255 #ifdef RT3261_REG_RW
1257 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1258 .name = "Register Control",
1259 .info = rt3261_regctl_info,
1260 .get = rt3261_regctl_get,
1261 .put = rt3261_regctl_put,
1266 SOC_SINGLE_TLV("Main Mic Capture Volume", RT3261_IN1_IN2,
1267 RT3261_BST_SFT1, 8, 0, bst_tlv),
1268 SOC_SINGLE_TLV("Headset Mic Capture Volume", RT3261_IN3_IN4,
1269 RT3261_BST_SFT2, 8, 0, bst_tlv),
1270 SOC_ENUM_EXT("Main Mic Capture Switch", rt3261_mic_enum,
1271 rt3261_mic1_get, rt3261_mic1_put),
1272 SOC_ENUM_EXT("Headset Mic Capture Switch", rt3261_mic_enum,
1273 rt3261_mic2_get, rt3261_mic2_put),
1277 SOC_ENUM_EXT("HP mute Switch", rt3261_hp_mute_enum,
1278 rt3261_hp_mute_get, rt3261_hp_mute_put),
1280 SOC_ENUM_EXT("Modem Input Switch", rt3261_modem_input_switch_enum,
1281 rt3261_modem_input_switch_get, rt3261_modem_input_switch_put),
1283 SOC_ENUM("ADC IF1 Data Switch", rt3261_if1_adc_enum),
1284 SOC_ENUM("DAC IF1 Data Switch", rt3261_if1_dac_enum),
1285 SOC_ENUM("ADC IF2 Data Switch", rt3261_if2_adc_enum),
1286 SOC_ENUM("DAC IF2 Data Switch", rt3261_if2_dac_enum),
1290 * set_dmic_clk - Set parameter of dmic.
1293 * @kcontrol: The kcontrol of this widget.
1296 * Choose dmic clock between 1MHz and 3MHz.
1297 * It is better for clock to approximate 3MHz.
1299 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1300 struct snd_kcontrol *kcontrol, int event)
1302 struct snd_soc_codec *codec = w->codec;
1303 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
1304 int div[] = {2, 3, 4, 6, 12}, idx = -EINVAL, i, rate, red, bound, temp;
1306 rate = rt3261->lrck[rt3261->aif_pu] << 8;
1308 for (i = 0; i < ARRAY_SIZE(div); i++) {
1309 bound = div[i] * 3000000;
1312 temp = bound - rate;
1319 dev_err(codec->dev, "Failed to set DMIC clock\n");
1321 snd_soc_update_bits(codec, RT3261_DMIC, RT3261_DMIC_CLK_MASK,
1322 idx << RT3261_DMIC_CLK_SFT);
1326 static int check_sysclk1_source(struct snd_soc_dapm_widget *source,
1327 struct snd_soc_dapm_widget *sink)
1331 val = snd_soc_read(source->codec, RT3261_GLB_CLK);
1332 val &= RT3261_SCLK_SRC_MASK;
1333 if (val == RT3261_SCLK_SRC_PLL1)
1340 static const struct snd_kcontrol_new rt3261_sto_adc_l_mix[] = {
1341 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
1342 RT3261_M_ADC_L1_SFT, 1, 1),
1343 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
1344 RT3261_M_ADC_L2_SFT, 1, 1),
1347 static const struct snd_kcontrol_new rt3261_sto_adc_r_mix[] = {
1348 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_STO_ADC_MIXER,
1349 RT3261_M_ADC_R1_SFT, 1, 1),
1350 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_STO_ADC_MIXER,
1351 RT3261_M_ADC_R2_SFT, 1, 1),
1354 static const struct snd_kcontrol_new rt3261_mono_adc_l_mix[] = {
1355 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
1356 RT3261_M_MONO_ADC_L1_SFT, 1, 1),
1357 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
1358 RT3261_M_MONO_ADC_L2_SFT, 1, 1),
1361 static const struct snd_kcontrol_new rt3261_mono_adc_r_mix[] = {
1362 SOC_DAPM_SINGLE("ADC1 Switch", RT3261_MONO_ADC_MIXER,
1363 RT3261_M_MONO_ADC_R1_SFT, 1, 1),
1364 SOC_DAPM_SINGLE("ADC2 Switch", RT3261_MONO_ADC_MIXER,
1365 RT3261_M_MONO_ADC_R2_SFT, 1, 1),
1368 static const struct snd_kcontrol_new rt3261_dac_l_mix[] = {
1369 SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
1370 RT3261_M_ADCMIX_L_SFT, 1, 1),
1371 SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
1372 RT3261_M_IF1_DAC_L_SFT, 1, 1),
1375 static const struct snd_kcontrol_new rt3261_dac_r_mix[] = {
1376 SOC_DAPM_SINGLE("Stereo ADC Switch", RT3261_AD_DA_MIXER,
1377 RT3261_M_ADCMIX_R_SFT, 1, 1),
1378 SOC_DAPM_SINGLE("INF1 Switch", RT3261_AD_DA_MIXER,
1379 RT3261_M_IF1_DAC_R_SFT, 1, 1),
1382 static const struct snd_kcontrol_new rt3261_sto_dac_l_mix[] = {
1383 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_STO_DAC_MIXER,
1384 RT3261_M_DAC_L1_SFT, 1, 1),
1385 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_STO_DAC_MIXER,
1386 RT3261_M_DAC_L2_SFT, 1, 1),
1387 SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
1388 RT3261_M_ANC_DAC_L_SFT, 1, 1),
1391 static const struct snd_kcontrol_new rt3261_sto_dac_r_mix[] = {
1392 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_STO_DAC_MIXER,
1393 RT3261_M_DAC_R1_SFT, 1, 1),
1394 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_STO_DAC_MIXER,
1395 RT3261_M_DAC_R2_SFT, 1, 1),
1396 SOC_DAPM_SINGLE("ANC Switch", RT3261_STO_DAC_MIXER,
1397 RT3261_M_ANC_DAC_R_SFT, 1, 1),
1400 static const struct snd_kcontrol_new rt3261_mono_dac_l_mix[] = {
1401 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_MONO_DAC_MIXER,
1402 RT3261_M_DAC_L1_MONO_L_SFT, 1, 1),
1403 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
1404 RT3261_M_DAC_L2_MONO_L_SFT, 1, 1),
1405 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
1406 RT3261_M_DAC_R2_MONO_L_SFT, 1, 1),
1409 static const struct snd_kcontrol_new rt3261_mono_dac_r_mix[] = {
1410 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_MONO_DAC_MIXER,
1411 RT3261_M_DAC_R1_MONO_R_SFT, 1, 1),
1412 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_DAC_MIXER,
1413 RT3261_M_DAC_R2_MONO_R_SFT, 1, 1),
1414 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_DAC_MIXER,
1415 RT3261_M_DAC_L2_MONO_R_SFT, 1, 1),
1418 static const struct snd_kcontrol_new rt3261_dig_l_mix[] = {
1419 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_DIG_MIXER,
1420 RT3261_M_STO_L_DAC_L_SFT, 1, 1),
1421 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_DIG_MIXER,
1422 RT3261_M_DAC_L2_DAC_L_SFT, 1, 1),
1425 static const struct snd_kcontrol_new rt3261_dig_r_mix[] = {
1426 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_DIG_MIXER,
1427 RT3261_M_STO_R_DAC_R_SFT, 1, 1),
1428 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_DIG_MIXER,
1429 RT3261_M_DAC_R2_DAC_R_SFT, 1, 1),
1432 /* Analog Input Mixer */
1433 static const struct snd_kcontrol_new rt3261_rec_l_mix[] = {
1434 SOC_DAPM_SINGLE("HPOL Switch", RT3261_REC_L2_MIXER,
1435 RT3261_M_HP_L_RM_L_SFT, 1, 1),
1436 SOC_DAPM_SINGLE("INL Switch", RT3261_REC_L2_MIXER,
1437 RT3261_M_IN_L_RM_L_SFT, 1, 1),
1438 SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_L2_MIXER,
1439 RT3261_M_BST2_RM_L, 1, 1),
1440 SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_L2_MIXER,
1441 RT3261_M_BST4_RM_L_SFT, 1, 1),
1442 SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_L2_MIXER,
1443 RT3261_M_BST1_RM_L_SFT, 1, 1),
1444 SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_REC_L2_MIXER,
1445 RT3261_M_OM_L_RM_L_SFT, 1, 1),
1448 static const struct snd_kcontrol_new rt3261_rec_r_mix[] = {
1449 SOC_DAPM_SINGLE("HPOR Switch", RT3261_REC_R2_MIXER,
1450 RT3261_M_HP_R_RM_R_SFT, 1, 1),
1451 SOC_DAPM_SINGLE("INR Switch", RT3261_REC_R2_MIXER,
1452 RT3261_M_IN_R_RM_R_SFT, 1, 1),
1453 SOC_DAPM_SINGLE("BST3 Switch", RT3261_REC_R2_MIXER,
1454 RT3261_M_BST2_RM_R_SFT, 1, 1),
1455 SOC_DAPM_SINGLE("BST2 Switch", RT3261_REC_R2_MIXER,
1456 RT3261_M_BST4_RM_R_SFT, 1, 1),
1457 SOC_DAPM_SINGLE("BST1 Switch", RT3261_REC_R2_MIXER,
1458 RT3261_M_BST1_RM_R_SFT, 1, 1),
1459 SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_REC_R2_MIXER,
1460 RT3261_M_OM_R_RM_R_SFT, 1, 1),
1463 /* Analog Output Mixer */
1464 static const struct snd_kcontrol_new rt3261_spk_l_mix[] = {
1465 SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_SPK_L_MIXER,
1466 RT3261_M_RM_L_SM_L_SFT, 1, 1),
1467 SOC_DAPM_SINGLE("INL Switch", RT3261_SPK_L_MIXER,
1468 RT3261_M_IN_L_SM_L_SFT, 1, 1),
1469 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPK_L_MIXER,
1470 RT3261_M_DAC_L1_SM_L_SFT, 1, 1),
1471 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_SPK_L_MIXER,
1472 RT3261_M_DAC_L2_SM_L_SFT, 1, 1),
1473 SOC_DAPM_SINGLE("OUT MIXL Switch", RT3261_SPK_L_MIXER,
1474 RT3261_M_OM_L_SM_L_SFT, 1, 1),
1477 static const struct snd_kcontrol_new rt3261_spk_r_mix[] = {
1478 SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_SPK_R_MIXER,
1479 RT3261_M_RM_R_SM_R_SFT, 1, 1),
1480 SOC_DAPM_SINGLE("INR Switch", RT3261_SPK_R_MIXER,
1481 RT3261_M_IN_R_SM_R_SFT, 1, 1),
1482 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPK_R_MIXER,
1483 RT3261_M_DAC_R1_SM_R_SFT, 1, 1),
1484 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_SPK_R_MIXER,
1485 RT3261_M_DAC_R2_SM_R_SFT, 1, 1),
1486 SOC_DAPM_SINGLE("OUT MIXR Switch", RT3261_SPK_R_MIXER,
1487 RT3261_M_OM_R_SM_R_SFT, 1, 1),
1490 static const struct snd_kcontrol_new rt3261_out_l_mix[] = {
1491 SOC_DAPM_SINGLE("SPK MIXL Switch", RT3261_OUT_L3_MIXER,
1492 RT3261_M_SM_L_OM_L_SFT, 1, 1),
1493 SOC_DAPM_SINGLE("BST3 Switch", RT3261_OUT_L3_MIXER,
1494 RT3261_M_BST2_OM_L_SFT, 1, 1),
1495 SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_L3_MIXER,
1496 RT3261_M_BST1_OM_L_SFT, 1, 1),
1497 SOC_DAPM_SINGLE("INL Switch", RT3261_OUT_L3_MIXER,
1498 RT3261_M_IN_L_OM_L_SFT, 1, 1),
1499 SOC_DAPM_SINGLE("REC MIXL Switch", RT3261_OUT_L3_MIXER,
1500 RT3261_M_RM_L_OM_L_SFT, 1, 1),
1501 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_L3_MIXER,
1502 RT3261_M_DAC_R2_OM_L_SFT, 1, 1),
1503 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_L3_MIXER,
1504 RT3261_M_DAC_L2_OM_L_SFT, 1, 1),
1505 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_OUT_L3_MIXER,
1506 RT3261_M_DAC_L1_OM_L_SFT, 1, 1),
1509 static const struct snd_kcontrol_new rt3261_out_r_mix[] = {
1510 SOC_DAPM_SINGLE("SPK MIXR Switch", RT3261_OUT_R3_MIXER,
1511 RT3261_M_SM_L_OM_R_SFT, 1, 1),
1512 SOC_DAPM_SINGLE("BST3 Switch", RT3261_OUT_R3_MIXER,
1513 RT3261_M_BST2_OM_R_SFT, 1, 1),
1514 SOC_DAPM_SINGLE("BST2 Switch", RT3261_OUT_R3_MIXER,
1515 RT3261_M_BST4_OM_R_SFT, 1, 1),
1516 SOC_DAPM_SINGLE("BST1 Switch", RT3261_OUT_R3_MIXER,
1517 RT3261_M_BST1_OM_R_SFT, 1, 1),
1518 SOC_DAPM_SINGLE("INR Switch", RT3261_OUT_R3_MIXER,
1519 RT3261_M_IN_R_OM_R_SFT, 1, 1),
1520 SOC_DAPM_SINGLE("REC MIXR Switch", RT3261_OUT_R3_MIXER,
1521 RT3261_M_RM_R_OM_R_SFT, 1, 1),
1522 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_OUT_R3_MIXER,
1523 RT3261_M_DAC_L2_OM_R_SFT, 1, 1),
1524 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_OUT_R3_MIXER,
1525 RT3261_M_DAC_R2_OM_R_SFT, 1, 1),
1526 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_OUT_R3_MIXER,
1527 RT3261_M_DAC_R1_OM_R_SFT, 1, 1),
1530 static const struct snd_kcontrol_new rt3261_spo_l_mix[] = {
1532 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
1533 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1534 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
1535 RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
1537 SOC_DAPM_SINGLE("DAC Switch", RT3261_DUMMY_SPKMIXER,
1538 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1540 SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_L_MIXER,
1541 RT3261_M_SV_R_SPM_L_SFT, 1, 1),
1542 SOC_DAPM_SINGLE("SPKVOL L Switch", RT3261_SPO_L_MIXER,
1543 RT3261_M_SV_L_SPM_L_SFT, 1, 1),
1544 SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_L_MIXER,
1545 RT3261_M_BST1_SPM_L_SFT, 1, 1),
1548 static const struct snd_kcontrol_new rt3261_spo_dac_mix[] = {
1549 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_L_MIXER,
1550 RT3261_M_DAC_R1_SPM_L_SFT, 1, 1),
1551 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_SPO_L_MIXER,
1552 RT3261_M_DAC_L1_SPM_L_SFT, 1, 1),
1556 static const struct snd_kcontrol_new rt3261_spo_r_mix[] = {
1557 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_SPO_R_MIXER,
1558 RT3261_M_DAC_R1_SPM_R_SFT, 1, 1),
1559 SOC_DAPM_SINGLE("SPKVOL R Switch", RT3261_SPO_R_MIXER,
1560 RT3261_M_SV_R_SPM_R_SFT, 1, 1),
1561 SOC_DAPM_SINGLE("BST1 Switch", RT3261_SPO_R_MIXER,
1562 RT3261_M_BST1_SPM_R_SFT, 1, 1),
1565 static const struct snd_kcontrol_new rt3261_hpo_mix[] = {
1566 SOC_DAPM_SINGLE("DAC2 Switch", RT3261_HPO_MIXER,
1567 RT3261_M_DAC2_HM_SFT, 1, 1),
1568 SOC_DAPM_SINGLE("DAC1 Switch", RT3261_HPO_MIXER,
1569 RT3261_M_DAC1_HM_SFT, 1, 1),
1570 SOC_DAPM_SINGLE("HPVOL Switch", RT3261_HPO_MIXER,
1571 RT3261_M_HPVOL_HM_SFT, 1, 1),
1574 static const struct snd_kcontrol_new rt3261_lout_mix[] = {
1575 SOC_DAPM_SINGLE("DAC L1 Switch", RT3261_LOUT_MIXER,
1576 RT3261_M_DAC_L1_LM_SFT, 1, 1),
1577 SOC_DAPM_SINGLE("DAC R1 Switch", RT3261_LOUT_MIXER,
1578 RT3261_M_DAC_R1_LM_SFT, 1, 1),
1579 SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_LOUT_MIXER,
1580 RT3261_M_OV_L_LM_SFT, 1, 1),
1581 SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_LOUT_MIXER,
1582 RT3261_M_OV_R_LM_SFT, 1, 1),
1585 static const struct snd_kcontrol_new rt3261_mono_mix[] = {
1586 SOC_DAPM_SINGLE("DAC R2 Switch", RT3261_MONO_MIXER,
1587 RT3261_M_DAC_R2_MM_SFT, 1, 1),
1588 SOC_DAPM_SINGLE("DAC L2 Switch", RT3261_MONO_MIXER,
1589 RT3261_M_DAC_L2_MM_SFT, 1, 1),
1590 SOC_DAPM_SINGLE("OUTVOL R Switch", RT3261_MONO_MIXER,
1591 RT3261_M_OV_R_MM_SFT, 1, 1),
1592 SOC_DAPM_SINGLE("OUTVOL L Switch", RT3261_MONO_MIXER,
1593 RT3261_M_OV_L_MM_SFT, 1, 1),
1594 SOC_DAPM_SINGLE("BST1 Switch", RT3261_MONO_MIXER,
1595 RT3261_M_BST1_MM_SFT, 1, 1),
1599 static const char *rt3261_inl_src[] = {"IN2P", "MonoP"};
1601 static const SOC_ENUM_SINGLE_DECL(
1602 rt3261_inl_enum, RT3261_INL_INR_VOL,
1603 RT3261_INL_SEL_SFT, rt3261_inl_src);
1605 static const struct snd_kcontrol_new rt3261_inl_mux =
1606 SOC_DAPM_ENUM("INL source", rt3261_inl_enum);
1608 static const char *rt3261_inr_src[] = {"IN2N", "MonoN"};
1610 static const SOC_ENUM_SINGLE_DECL(
1611 rt3261_inr_enum, RT3261_INL_INR_VOL,
1612 RT3261_INR_SEL_SFT, rt3261_inr_src);
1614 static const struct snd_kcontrol_new rt3261_inr_mux =
1615 SOC_DAPM_ENUM("INR source", rt3261_inr_enum);
1617 /* Stereo ADC source */
1618 static const char *rt3261_stereo_adc1_src[] = {"DIG MIX", "ADC"};
1620 static const SOC_ENUM_SINGLE_DECL(
1621 rt3261_stereo_adc1_enum, RT3261_STO_ADC_MIXER,
1622 RT3261_ADC_1_SRC_SFT, rt3261_stereo_adc1_src);
1624 static const struct snd_kcontrol_new rt3261_sto_adc_l1_mux =
1625 SOC_DAPM_ENUM("Stereo ADC L1 source", rt3261_stereo_adc1_enum);
1627 static const struct snd_kcontrol_new rt3261_sto_adc_r1_mux =
1628 SOC_DAPM_ENUM("Stereo ADC R1 source", rt3261_stereo_adc1_enum);
1630 static const char *rt3261_stereo_adc2_src[] = {"DMIC1", "DMIC2", "DIG MIX"};
1632 static const SOC_ENUM_SINGLE_DECL(
1633 rt3261_stereo_adc2_enum, RT3261_STO_ADC_MIXER,
1634 RT3261_ADC_2_SRC_SFT, rt3261_stereo_adc2_src);
1636 static const struct snd_kcontrol_new rt3261_sto_adc_l2_mux =
1637 SOC_DAPM_ENUM("Stereo ADC L2 source", rt3261_stereo_adc2_enum);
1639 static const struct snd_kcontrol_new rt3261_sto_adc_r2_mux =
1640 SOC_DAPM_ENUM("Stereo ADC R2 source", rt3261_stereo_adc2_enum);
1642 /* Mono ADC source */
1643 static const char *rt3261_mono_adc_l1_src[] = {"Mono DAC MIXL", "ADCL"};
1645 static const SOC_ENUM_SINGLE_DECL(
1646 rt3261_mono_adc_l1_enum, RT3261_MONO_ADC_MIXER,
1647 RT3261_MONO_ADC_L1_SRC_SFT, rt3261_mono_adc_l1_src);
1649 static const struct snd_kcontrol_new rt3261_mono_adc_l1_mux =
1650 SOC_DAPM_ENUM("Mono ADC1 left source", rt3261_mono_adc_l1_enum);
1652 static const char *rt3261_mono_adc_l2_src[] =
1653 {"DMIC L1", "DMIC L2", "Mono DAC MIXL"};
1655 static const SOC_ENUM_SINGLE_DECL(
1656 rt3261_mono_adc_l2_enum, RT3261_MONO_ADC_MIXER,
1657 RT3261_MONO_ADC_L2_SRC_SFT, rt3261_mono_adc_l2_src);
1659 static const struct snd_kcontrol_new rt3261_mono_adc_l2_mux =
1660 SOC_DAPM_ENUM("Mono ADC2 left source", rt3261_mono_adc_l2_enum);
1662 static const char *rt3261_mono_adc_r1_src[] = {"Mono DAC MIXR", "ADCR"};
1664 static const SOC_ENUM_SINGLE_DECL(
1665 rt3261_mono_adc_r1_enum, RT3261_MONO_ADC_MIXER,
1666 RT3261_MONO_ADC_R1_SRC_SFT, rt3261_mono_adc_r1_src);
1668 static const struct snd_kcontrol_new rt3261_mono_adc_r1_mux =
1669 SOC_DAPM_ENUM("Mono ADC1 right source", rt3261_mono_adc_r1_enum);
1671 static const char *rt3261_mono_adc_r2_src[] =
1672 {"DMIC R1", "DMIC R2", "Mono DAC MIXR"};
1674 static const SOC_ENUM_SINGLE_DECL(
1675 rt3261_mono_adc_r2_enum, RT3261_MONO_ADC_MIXER,
1676 RT3261_MONO_ADC_R2_SRC_SFT, rt3261_mono_adc_r2_src);
1678 static const struct snd_kcontrol_new rt3261_mono_adc_r2_mux =
1679 SOC_DAPM_ENUM("Mono ADC2 right source", rt3261_mono_adc_r2_enum);
1681 /* DAC2 channel source */
1682 static const char *rt3261_dac_l2_src[] = {"IF2", "IF3", "TxDC", "Base L/R"};
1684 static const SOC_ENUM_SINGLE_DECL(rt3261_dac_l2_enum, RT3261_DSP_PATH2,
1685 RT3261_DAC_L2_SEL_SFT, rt3261_dac_l2_src);
1687 static const struct snd_kcontrol_new rt3261_dac_l2_mux =
1688 SOC_DAPM_ENUM("DAC2 left channel source", rt3261_dac_l2_enum);
1690 static const char *rt3261_dac_r2_src[] = {"IF2", "IF3", "TxDC"};
1692 static const SOC_ENUM_SINGLE_DECL(
1693 rt3261_dac_r2_enum, RT3261_DSP_PATH2,
1694 RT3261_DAC_R2_SEL_SFT, rt3261_dac_r2_src);
1696 static const struct snd_kcontrol_new rt3261_dac_r2_mux =
1697 SOC_DAPM_ENUM("DAC2 right channel source", rt3261_dac_r2_enum);
1699 /* Interface 2 ADC channel source */
1700 static const char *rt3261_if2_adc_l_src[] = {"TxDP", "Mono ADC MIXL"};
1702 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_l_enum, RT3261_DSP_PATH2,
1703 RT3261_IF2_ADC_L_SEL_SFT, rt3261_if2_adc_l_src);
1705 static const struct snd_kcontrol_new rt3261_if2_adc_l_mux =
1706 SOC_DAPM_ENUM("IF2 ADC left channel source", rt3261_if2_adc_l_enum);
1708 static const char *rt3261_if2_adc_r_src[] = {"TxDP", "Mono ADC MIXR"};
1710 static const SOC_ENUM_SINGLE_DECL(rt3261_if2_adc_r_enum, RT3261_DSP_PATH2,
1711 RT3261_IF2_ADC_R_SEL_SFT, rt3261_if2_adc_r_src);
1713 static const struct snd_kcontrol_new rt3261_if2_adc_r_mux =
1714 SOC_DAPM_ENUM("IF2 ADC right channel source", rt3261_if2_adc_r_enum);
1716 /* digital interface and iis interface map */
1717 static const char *rt3261_dai_iis_map[] = {"1:1|2:2|3:3", "1:1|2:3|3:2",
1718 "1:3|2:1|3:2", "1:3|2:2|3:1", "1:2|2:3|3:1",
1719 "1:2|2:1|3:3", "1:1|2:1|3:3", "1:2|2:2|3:3"};
1721 static const SOC_ENUM_SINGLE_DECL(
1722 rt3261_dai_iis_map_enum, RT3261_I2S1_SDP,
1723 RT3261_I2S_IF_SFT, rt3261_dai_iis_map);
1725 static const struct snd_kcontrol_new rt3261_dai_mux =
1726 SOC_DAPM_ENUM("DAI select", rt3261_dai_iis_map_enum);
1729 static const char *rt3261_sdi_sel[] = {"IF1", "IF2"};
1731 static const SOC_ENUM_SINGLE_DECL(
1732 rt3261_sdi_sel_enum, RT3261_I2S2_SDP,
1733 RT3261_I2S2_SDI_SFT, rt3261_sdi_sel);
1735 static const struct snd_kcontrol_new rt3261_sdi_mux =
1736 SOC_DAPM_ENUM("SDI select", rt3261_sdi_sel_enum);
1738 static int rt3261_adc_event(struct snd_soc_dapm_widget *w,
1739 struct snd_kcontrol *kcontrol, int event)
1741 struct snd_soc_codec *codec = w->codec;
1742 unsigned int val, mask;
1745 case SND_SOC_DAPM_POST_PMU:
1746 //rt3261_index_update_bits(codec,
1747 // RT3261_CHOP_DAC_ADC, 0x1000, 0x1000);
1748 val = snd_soc_read(codec, RT3261_MONO_ADC_MIXER);
1749 mask = RT3261_M_MONO_ADC_L1 | RT3261_M_MONO_ADC_L2 |
1750 RT3261_M_MONO_ADC_R1 | RT3261_M_MONO_ADC_R2;
1751 if ((val & mask) ^ mask)
1752 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1753 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R, 0);
1756 case SND_SOC_DAPM_POST_PMD:
1757 snd_soc_update_bits(codec, RT3261_GEN_CTRL1,
1758 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R,
1759 RT3261_M_MAMIX_L | RT3261_M_MAMIX_R);
1760 //rt3261_index_update_bits(codec,
1761 // RT3261_CHOP_DAC_ADC, 0x1000, 0x0000);
1771 static int rt3261_spk_event(struct snd_soc_dapm_widget *w,
1772 struct snd_kcontrol *kcontrol, int event)
1774 struct snd_soc_codec *codec = w->codec;
1778 case SND_SOC_DAPM_POST_PMU:
1780 val = snd_soc_read(codec, RT3261_PWR_DIG1);
1781 if(val & (RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1)) {
1782 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1783 RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1,
1784 RT3261_PWR_DAC_L1 | RT3261_PWR_DAC_R1);
1787 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1788 RT3261_PWR_CLS_D, RT3261_PWR_CLS_D);
1789 rt3261_index_update_bits(codec,
1790 RT3261_CLSD_INT_REG1, 0xf000, 0xf000);
1791 snd_soc_update_bits(codec, RT3261_SPK_VOL,
1792 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1795 case SND_SOC_DAPM_PRE_PMD:
1796 snd_soc_update_bits(codec, RT3261_SPK_VOL,
1797 RT3261_L_MUTE | RT3261_R_MUTE,
1798 RT3261_L_MUTE | RT3261_R_MUTE);
1799 rt3261_index_update_bits(codec,
1800 RT3261_CLSD_INT_REG1, 0xf000, 0x0000);
1801 snd_soc_update_bits(codec, RT3261_PWR_DIG1,
1802 RT3261_PWR_CLS_D, 0);
1813 static void rt3261_pmu_depop(struct snd_soc_codec *codec)
1816 /* depop parameters */
1817 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
1818 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
1819 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1820 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1821 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
1822 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
1823 /* headphone amp power on */
1824 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1825 RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
1826 snd_soc_update_bits(codec, RT3261_PWR_VOL,
1827 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
1828 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
1829 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1830 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1831 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
1833 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1834 RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
1835 RT3261_PWR_HP_R | RT3261_PWR_HA,
1836 RT3261_PWR_FV1 | RT3261_PWR_FV2 | RT3261_PWR_HP_L |
1837 RT3261_PWR_HP_R | RT3261_PWR_HA);
1838 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
1839 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
1840 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
1841 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1842 RT3261_HP_CO_MASK | RT3261_HP_SG_MASK,
1843 RT3261_HP_CO_EN | RT3261_HP_SG_EN);
1845 hp_amp_power(codec, 1);
1847 /* headphone unmute sequence */
1848 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
1849 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
1850 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ1_SFT) |
1851 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
1852 (RT3261_CP_FQ_192_KHZ << RT3261_CP_FQ3_SFT));
1853 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
1854 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1855 RT3261_SMT_TRIG_MASK, RT3261_SMT_TRIG_EN);
1856 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1857 RT3261_RSTN_MASK, RT3261_RSTN_EN);
1858 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1859 RT3261_RSTN_MASK | RT3261_HP_L_SMT_MASK | RT3261_HP_R_SMT_MASK,
1860 RT3261_RSTN_DIS | RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
1861 snd_soc_update_bits(codec, RT3261_HP_VOL,
1862 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1864 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1865 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
1866 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
1867 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
1870 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
1871 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
1875 static void rt3261_pmd_depop(struct snd_soc_codec *codec)
1877 /* headphone mute sequence */
1878 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
1879 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
1880 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
1881 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
1882 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
1883 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
1884 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1885 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
1886 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1887 RT3261_RSTP_MASK, RT3261_RSTP_EN);
1888 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1889 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
1890 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
1891 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
1893 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
1894 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
1897 snd_soc_update_bits(codec, RT3261_HP_VOL,
1898 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
1901 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
1902 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1903 RT3261_HP_SG_MASK | RT3261_HP_L_SMT_MASK |
1904 RT3261_HP_R_SMT_MASK, RT3261_HP_SG_DIS |
1905 RT3261_HP_L_SMT_DIS | RT3261_HP_R_SMT_DIS);
1906 /* headphone amp power down */
1907 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1908 RT3261_SMT_TRIG_MASK | RT3261_HP_CD_PD_MASK |
1909 RT3261_HP_CO_MASK | RT3261_HP_CP_MASK |
1910 RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1911 RT3261_SMT_TRIG_DIS | RT3261_HP_CD_PD_EN |
1912 RT3261_HP_CO_DIS | RT3261_HP_CP_PD |
1913 RT3261_HP_SG_EN | RT3261_HP_CB_PD);
1914 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1915 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1918 hp_amp_power(codec, 0);
1922 static void rt3261_pmu_depop(struct snd_soc_codec *codec)
1924 /* depop parameters */
1925 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
1926 RT3261_DEPOP_MASK, RT3261_DEPOP_MAN);
1927 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1928 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK | RT3261_HP_CB_MASK,
1929 RT3261_HP_CP_PU | RT3261_HP_SG_DIS | RT3261_HP_CB_PU);
1930 rt3261_index_write(codec, RT3261_HP_DCC_INT1, 0x9f00);
1931 /* headphone amp power on */
1932 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1933 RT3261_PWR_FV1 | RT3261_PWR_FV2, 0);
1934 snd_soc_update_bits(codec, RT3261_PWR_VOL,
1935 RT3261_PWR_HV_L | RT3261_PWR_HV_R,
1936 RT3261_PWR_HV_L | RT3261_PWR_HV_R);
1937 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1938 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1939 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA);
1941 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1942 RT3261_PWR_FV1 | RT3261_PWR_FV2 ,
1943 RT3261_PWR_FV1 | RT3261_PWR_FV2 );
1944 rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0200);
1945 /* headphone unmute sequence */
1946 snd_soc_update_bits(codec, RT3261_DEPOP_M2,
1947 RT3261_DEPOP_MASK | RT3261_DIG_DP_MASK,
1948 RT3261_DEPOP_AUTO | RT3261_DIG_DP_EN);
1949 snd_soc_update_bits(codec, RT3261_CHARGE_PUMP,
1950 RT3261_PM_HP_MASK, RT3261_PM_HP_HV);
1951 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
1952 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
1953 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
1954 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
1955 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
1956 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1957 RT3261_HP_CP_MASK | RT3261_HP_SG_MASK,
1958 RT3261_HP_CP_PD | RT3261_HP_SG_EN);
1960 snd_soc_update_bits(codec, RT3261_HP_VOL,
1961 RT3261_L_MUTE | RT3261_R_MUTE, 0);
1962 msleep(70); //bard 10-18
1964 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
1965 RT3261_HPD_PS_MASK, RT3261_HPD_PS_EN);
1969 static void rt3261_pmd_depop(struct snd_soc_codec *codec)
1972 snd_soc_update_bits(codec, RT3261_HP_CALIB_AMP_DET,
1973 RT3261_HPD_PS_MASK, RT3261_HPD_PS_DIS);
1975 snd_soc_update_bits(codec, RT3261_HP_VOL,
1976 RT3261_L_MUTE | RT3261_R_MUTE,
1977 RT3261_L_MUTE | RT3261_R_MUTE);
1979 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
1980 RT3261_HP_CB_MASK, RT3261_HP_CB_PD);
1982 //rt3261_index_update_bits(codec, RT3261_CHOP_DAC_ADC, 0x0200, 0x0);
1983 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
1984 RT3261_PWR_HP_L | RT3261_PWR_HP_R | RT3261_PWR_HA,
1989 static int rt3261_hp_event(struct snd_soc_dapm_widget *w,
1990 struct snd_kcontrol *kcontrol, int event)
1992 struct snd_soc_codec *codec = w->codec;
1995 case SND_SOC_DAPM_POST_PMU:
1996 rt3261_pmu_depop(codec);
1999 case SND_SOC_DAPM_PRE_PMD:
2000 rt3261_pmd_depop(codec);
2010 static int rt3261_mono_event(struct snd_soc_dapm_widget *w,
2011 struct snd_kcontrol *kcontrol, int event)
2013 struct snd_soc_codec *codec = w->codec;
2016 case SND_SOC_DAPM_POST_PMU:
2017 snd_soc_update_bits(codec, RT3261_MONO_OUT,
2021 case SND_SOC_DAPM_PRE_PMD:
2022 snd_soc_update_bits(codec, RT3261_MONO_OUT,
2023 RT3261_L_MUTE, RT3261_L_MUTE);
2033 static int rt3261_lout_event(struct snd_soc_dapm_widget *w,
2034 struct snd_kcontrol *kcontrol, int event)
2036 struct snd_soc_codec *codec = w->codec;
2039 case SND_SOC_DAPM_POST_PMU:
2040 hp_amp_power(codec,1);
2041 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2042 RT3261_PWR_LM, RT3261_PWR_LM); //bard 10-18
2043 snd_soc_update_bits(codec, RT3261_OUTPUT,
2044 RT3261_L_MUTE | RT3261_R_MUTE, 0);
2047 case SND_SOC_DAPM_PRE_PMD:
2048 snd_soc_update_bits(codec, RT3261_OUTPUT,
2049 RT3261_L_MUTE | RT3261_R_MUTE,
2050 RT3261_L_MUTE | RT3261_R_MUTE);
2051 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
2052 RT3261_PWR_LM, 0); //bard 10-18
2053 hp_amp_power(codec,0);
2063 static const struct snd_soc_dapm_widget rt3261_dapm_widgets[] = {
2064 SND_SOC_DAPM_SUPPLY("PLL1", RT3261_PWR_ANLG2,
2065 RT3261_PWR_PLL_BIT, 0, NULL, 0),
2068 SND_SOC_DAPM_SUPPLY("LDO2", RT3261_PWR_ANLG1,
2069 RT3261_PWR_LDO2_BIT, 0, NULL, 0),
2071 SND_SOC_DAPM_MICBIAS("micbias1", RT3261_PWR_ANLG2,
2072 RT3261_PWR_MB1_BIT, 0),
2074 SND_SOC_DAPM_MICBIAS("micbias1", SND_SOC_NOPM,
2077 SND_SOC_DAPM_MICBIAS("micbias2", RT3261_PWR_ANLG2,
2078 RT3261_PWR_MB2_BIT, 0),
2080 SND_SOC_DAPM_INPUT("MIC1"),
2081 SND_SOC_DAPM_INPUT("MIC2"),
2082 SND_SOC_DAPM_INPUT("MIC3"),
2083 SND_SOC_DAPM_INPUT("DMIC1"),
2084 SND_SOC_DAPM_INPUT("DMIC2"),
2086 SND_SOC_DAPM_INPUT("IN1P"),
2087 SND_SOC_DAPM_INPUT("IN1N"),
2088 SND_SOC_DAPM_INPUT("IN2P"),
2089 SND_SOC_DAPM_INPUT("IN2N"),
2090 SND_SOC_DAPM_INPUT("IN3P"),
2091 SND_SOC_DAPM_INPUT("IN3N"),
2092 SND_SOC_DAPM_INPUT("DMIC L1"),
2093 SND_SOC_DAPM_INPUT("DMIC R1"),
2094 SND_SOC_DAPM_INPUT("DMIC L2"),
2095 SND_SOC_DAPM_INPUT("DMIC R2"),
2096 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2097 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2099 SND_SOC_DAPM_PGA("BST1", RT3261_PWR_ANLG2,
2100 RT3261_PWR_BST1_BIT, 0, NULL, 0),
2101 SND_SOC_DAPM_PGA("BST2", RT3261_PWR_ANLG2,
2102 RT3261_PWR_BST4_BIT, 0, NULL, 0),
2103 SND_SOC_DAPM_PGA("BST3", RT3261_PWR_ANLG2,
2104 RT3261_PWR_BST2_BIT, 0, NULL, 0),
2106 SND_SOC_DAPM_PGA("INL VOL", RT3261_PWR_VOL,
2107 RT3261_PWR_IN_L_BIT, 0, NULL, 0),
2108 SND_SOC_DAPM_PGA("INR VOL", RT3261_PWR_VOL,
2109 RT3261_PWR_IN_R_BIT, 0, NULL, 0),
2111 SND_SOC_DAPM_MUX("INL Mux", SND_SOC_NOPM, 0, 0, &rt3261_inl_mux),
2112 SND_SOC_DAPM_MUX("INR Mux", SND_SOC_NOPM, 0, 0, &rt3261_inr_mux),
2114 SND_SOC_DAPM_MIXER("RECMIXL", RT3261_PWR_MIXER, RT3261_PWR_RM_L_BIT, 0,
2115 rt3261_rec_l_mix, ARRAY_SIZE(rt3261_rec_l_mix)),
2116 SND_SOC_DAPM_MIXER("RECMIXR", RT3261_PWR_MIXER, RT3261_PWR_RM_R_BIT, 0,
2117 rt3261_rec_r_mix, ARRAY_SIZE(rt3261_rec_r_mix)),
2119 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM,
2121 SND_SOC_DAPM_ADC_E("ADC R", NULL, SND_SOC_NOPM,
2122 0, 0, rt3261_adc_event,
2123 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
2125 SND_SOC_DAPM_SUPPLY("ADC L power",RT3261_PWR_DIG1,
2126 RT3261_PWR_ADC_L_BIT, 0, NULL, 0),
2127 SND_SOC_DAPM_SUPPLY("ADC R power",RT3261_PWR_DIG1,
2128 RT3261_PWR_ADC_R_BIT, 0, NULL, 0),
2130 SND_SOC_DAPM_MUX("Stereo ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2131 &rt3261_sto_adc_l2_mux),
2132 SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2133 &rt3261_sto_adc_r2_mux),
2134 SND_SOC_DAPM_MUX("Stereo ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2135 &rt3261_sto_adc_l1_mux),
2136 SND_SOC_DAPM_MUX("Stereo ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2137 &rt3261_sto_adc_r1_mux),
2138 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2139 &rt3261_mono_adc_l2_mux),
2140 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2141 &rt3261_mono_adc_l1_mux),
2142 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2143 &rt3261_mono_adc_r1_mux),
2144 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2145 &rt3261_mono_adc_r2_mux),
2147 SND_SOC_DAPM_SUPPLY("stereo filter", RT3261_PWR_DIG2,
2148 RT3261_PWR_ADC_SF_BIT, 0, NULL, 0),
2149 SND_SOC_DAPM_MIXER("Stereo ADC MIXL", SND_SOC_NOPM, 0, 0,
2150 rt3261_sto_adc_l_mix, ARRAY_SIZE(rt3261_sto_adc_l_mix)),
2151 SND_SOC_DAPM_MIXER("Stereo ADC MIXR", SND_SOC_NOPM, 0, 0,
2152 rt3261_sto_adc_r_mix, ARRAY_SIZE(rt3261_sto_adc_r_mix)),
2153 SND_SOC_DAPM_SUPPLY("mono left filter", RT3261_PWR_DIG2,
2154 RT3261_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2155 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2156 rt3261_mono_adc_l_mix, ARRAY_SIZE(rt3261_mono_adc_l_mix)),
2157 SND_SOC_DAPM_SUPPLY("mono right filter", RT3261_PWR_DIG2,
2158 RT3261_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2159 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2160 rt3261_mono_adc_r_mix, ARRAY_SIZE(rt3261_mono_adc_r_mix)),
2163 SND_SOC_DAPM_MUX("IF2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2164 &rt3261_if2_adc_l_mux),
2165 SND_SOC_DAPM_MUX("IF2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2166 &rt3261_if2_adc_r_mux),
2168 /* Digital Interface */
2169 SND_SOC_DAPM_SUPPLY("I2S1", RT3261_PWR_DIG1,
2170 RT3261_PWR_I2S1_BIT, 0, NULL, 0),
2171 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2172 SND_SOC_DAPM_PGA("IF1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2173 SND_SOC_DAPM_PGA("IF1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2174 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2175 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2176 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2177 SND_SOC_DAPM_SUPPLY("I2S2", RT3261_PWR_DIG1,
2178 RT3261_PWR_I2S2_BIT, 0, NULL, 0),
2179 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2180 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2181 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2182 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2183 SND_SOC_DAPM_PGA("IF2 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2184 SND_SOC_DAPM_PGA("IF2 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2185 SND_SOC_DAPM_SUPPLY("I2S3", RT3261_PWR_DIG1,
2186 RT3261_PWR_I2S3_BIT, 0, NULL, 0),
2187 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2188 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2189 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2190 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2191 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2192 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2194 /* Digital Interface Select */
2195 SND_SOC_DAPM_MUX("DAI1 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2196 SND_SOC_DAPM_MUX("DAI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2197 SND_SOC_DAPM_MUX("DAI1 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2198 SND_SOC_DAPM_MUX("DAI1 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2199 SND_SOC_DAPM_MUX("SDI1 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
2201 SND_SOC_DAPM_MUX("DAI2 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2202 SND_SOC_DAPM_MUX("DAI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2203 SND_SOC_DAPM_MUX("DAI2 IF1 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2204 SND_SOC_DAPM_MUX("DAI2 IF2 Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2205 SND_SOC_DAPM_MUX("SDI2 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_sdi_mux),
2207 SND_SOC_DAPM_MUX("DAI3 RX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2208 SND_SOC_DAPM_MUX("DAI3 TX Mux", SND_SOC_NOPM, 0, 0, &rt3261_dai_mux),
2210 /* Audio Interface */
2211 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2212 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2213 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2214 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2215 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2216 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2219 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2222 SND_SOC_DAPM_PGA("ANC", SND_SOC_NOPM, 0, 0, NULL, 0),
2225 /* DAC mixer before sound effect */
2226 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2227 rt3261_dac_l_mix, ARRAY_SIZE(rt3261_dac_l_mix)),
2228 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2229 rt3261_dac_r_mix, ARRAY_SIZE(rt3261_dac_r_mix)),
2231 /* DAC2 channel Mux */
2232 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0,
2233 &rt3261_dac_l2_mux),
2234 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
2235 &rt3261_dac_r2_mux),
2237 SND_SOC_DAPM_PGA("DAC L2 Volume", RT3261_PWR_DIG1,
2238 RT3261_PWR_DAC_L2_BIT, 0, NULL, 0),
2239 SND_SOC_DAPM_PGA("DAC R2 Volume", RT3261_PWR_DIG1,
2240 RT3261_PWR_DAC_R2_BIT, 0, NULL, 0),
2242 SND_SOC_DAPM_PGA("DAC L2 Volume", SND_SOC_NOPM,
2244 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM,
2246 SND_SOC_DAPM_SUPPLY("DAC L1 Power", RT3261_PWR_DIG1,
2247 RT3261_PWR_DAC_L1_BIT, 0, NULL, 0),
2248 SND_SOC_DAPM_SUPPLY("DAC R1 Power", RT3261_PWR_DIG1,
2249 RT3261_PWR_DAC_R1_BIT, 0, NULL, 0),
2250 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT3261_PWR_DIG1,
2251 RT3261_PWR_DAC_L2_BIT, 0, NULL, 0),
2252 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT3261_PWR_DIG1,
2253 RT3261_PWR_DAC_R2_BIT, 0, NULL, 0),
2257 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2258 rt3261_sto_dac_l_mix, ARRAY_SIZE(rt3261_sto_dac_l_mix)),
2259 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2260 rt3261_sto_dac_r_mix, ARRAY_SIZE(rt3261_sto_dac_r_mix)),
2261 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2262 rt3261_mono_dac_l_mix, ARRAY_SIZE(rt3261_mono_dac_l_mix)),
2263 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2264 rt3261_mono_dac_r_mix, ARRAY_SIZE(rt3261_mono_dac_r_mix)),
2265 SND_SOC_DAPM_MIXER("DIG MIXL", SND_SOC_NOPM, 0, 0,
2266 rt3261_dig_l_mix, ARRAY_SIZE(rt3261_dig_l_mix)),
2267 SND_SOC_DAPM_MIXER("DIG MIXR", SND_SOC_NOPM, 0, 0,
2268 rt3261_dig_r_mix, ARRAY_SIZE(rt3261_dig_r_mix)),
2269 SND_SOC_DAPM_MUX("Mono dacr Mux", SND_SOC_NOPM, 0, 0,
2274 SND_SOC_DAPM_DAC("DAC L1", NULL, RT3261_PWR_DIG1,
2275 RT3261_PWR_DAC_L1_BIT, 0),
2276 SND_SOC_DAPM_DAC("DAC L2", NULL, RT3261_PWR_DIG1,
2277 RT3261_PWR_DAC_L2_BIT, 0),
2278 SND_SOC_DAPM_DAC("DAC R1", NULL, RT3261_PWR_DIG1,
2279 RT3261_PWR_DAC_R1_BIT, 0),
2280 SND_SOC_DAPM_DAC("DAC R2", NULL, RT3261_PWR_DIG1,
2281 RT3261_PWR_DAC_R2_BIT, 0),
2283 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
2284 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
2285 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
2286 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
2288 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
2290 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM,
2293 SND_SOC_DAPM_MIXER("SPK MIXL", RT3261_PWR_MIXER, RT3261_PWR_SM_L_BIT,
2294 0, rt3261_spk_l_mix, ARRAY_SIZE(rt3261_spk_l_mix)),
2295 SND_SOC_DAPM_MIXER("SPK MIXR", RT3261_PWR_MIXER, RT3261_PWR_SM_R_BIT,
2296 0, rt3261_spk_r_mix, ARRAY_SIZE(rt3261_spk_r_mix)),
2297 SND_SOC_DAPM_MIXER("OUT MIXL", RT3261_PWR_MIXER, RT3261_PWR_OM_L_BIT,
2298 0, rt3261_out_l_mix, ARRAY_SIZE(rt3261_out_l_mix)),
2299 SND_SOC_DAPM_MIXER("OUT MIXR", RT3261_PWR_MIXER, RT3261_PWR_OM_R_BIT,
2300 0, rt3261_out_r_mix, ARRAY_SIZE(rt3261_out_r_mix)),
2302 SND_SOC_DAPM_PGA("SPKVOL L", RT3261_PWR_VOL,
2303 RT3261_PWR_SV_L_BIT, 0, NULL, 0),
2304 SND_SOC_DAPM_PGA("SPKVOL R", RT3261_PWR_VOL,
2305 RT3261_PWR_SV_R_BIT, 0, NULL, 0),
2306 SND_SOC_DAPM_PGA("OUTVOL L", RT3261_PWR_VOL,
2307 RT3261_PWR_OV_L_BIT, 0, NULL, 0),
2308 SND_SOC_DAPM_PGA("OUTVOL R", RT3261_PWR_VOL,
2309 RT3261_PWR_OV_R_BIT, 0, NULL, 0),
2310 SND_SOC_DAPM_PGA("HPOVOL L", RT3261_PWR_VOL,
2311 RT3261_PWR_HV_L_BIT, 0, NULL, 0),
2312 SND_SOC_DAPM_PGA("HPOVOL R", RT3261_PWR_VOL,
2313 RT3261_PWR_HV_R_BIT, 0, NULL, 0),
2314 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM,
2316 /* SPO/HPO/LOUT/Mono Mixer */
2317 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0,
2318 0, rt3261_spo_l_mix, ARRAY_SIZE(rt3261_spo_l_mix)),
2319 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0,
2320 0, rt3261_spo_r_mix, ARRAY_SIZE(rt3261_spo_r_mix)),
2321 SND_SOC_DAPM_MIXER("DAC SPK", SND_SOC_NOPM, 0,
2322 0, rt3261_spo_dac_mix, ARRAY_SIZE(rt3261_spo_dac_mix)), //bard 8-27
2323 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
2324 rt3261_hpo_mix, ARRAY_SIZE(rt3261_hpo_mix)),
2325 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
2326 rt3261_lout_mix, ARRAY_SIZE(rt3261_lout_mix)),
2327 SND_SOC_DAPM_MIXER("Mono MIX", RT3261_PWR_ANLG1, RT3261_PWR_MM_BIT, 0,
2328 rt3261_mono_mix, ARRAY_SIZE(rt3261_mono_mix)),
2330 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0,
2331 rt3261_hp_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2332 SND_SOC_DAPM_PGA_S("SPK amp", 1, SND_SOC_NOPM, 0, 0,
2333 rt3261_spk_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2334 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
2335 rt3261_lout_event, SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2336 SND_SOC_DAPM_PGA_S("Mono amp", 1, RT3261_PWR_ANLG1,
2337 RT3261_PWR_MA_BIT, 0, rt3261_mono_event,
2338 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2341 SND_SOC_DAPM_OUTPUT("SPOLP"),
2342 SND_SOC_DAPM_OUTPUT("SPOLN"),
2343 SND_SOC_DAPM_OUTPUT("SPORP"),
2344 SND_SOC_DAPM_OUTPUT("SPORN"),
2345 SND_SOC_DAPM_OUTPUT("HPOL"),
2346 SND_SOC_DAPM_OUTPUT("HPOR"),
2347 SND_SOC_DAPM_OUTPUT("LOUTL"),
2348 SND_SOC_DAPM_OUTPUT("LOUTR"),
2349 SND_SOC_DAPM_OUTPUT("MonoP"),
2350 SND_SOC_DAPM_OUTPUT("MonoN"),
2353 static const struct snd_soc_dapm_route rt3261_dapm_routes[] = {
2354 {"IN1P", NULL, "LDO2"},
2355 {"IN2P", NULL, "LDO2"},
2356 {"IN3P", NULL, "LDO2"},
2358 {"IN1P", NULL, "MIC1"},
2359 {"IN1N", NULL, "MIC1"},
2360 {"IN2P", NULL, "MIC2"},
2361 {"IN2N", NULL, "MIC2"},
2362 {"IN3P", NULL, "MIC3"},
2363 {"IN3N", NULL, "MIC3"},
2365 {"DMIC L1", NULL, "DMIC1"},
2366 {"DMIC R1", NULL, "DMIC1"},
2367 {"DMIC L2", NULL, "DMIC2"},
2368 {"DMIC R2", NULL, "DMIC2"},
2370 {"BST1", NULL, "IN1P"},
2371 {"BST1", NULL, "IN1N"},
2372 {"BST2", NULL, "IN2P"},
2373 {"BST2", NULL, "IN2N"},
2374 {"BST3", NULL, "IN3P"},
2375 {"BST3", NULL, "IN3N"},
2377 {"INL VOL", NULL, "IN2P"},
2378 {"INR VOL", NULL, "IN2N"},
2380 {"RECMIXL", "HPOL Switch", "HPOL"},
2381 {"RECMIXL", "INL Switch", "INL VOL"},
2382 {"RECMIXL", "BST3 Switch", "BST3"},
2383 {"RECMIXL", "BST2 Switch", "BST2"},
2384 {"RECMIXL", "BST1 Switch", "BST1"},
2385 {"RECMIXL", "OUT MIXL Switch", "OUT MIXL"},
2387 {"RECMIXR", "HPOR Switch", "HPOR"},
2388 {"RECMIXR", "INR Switch", "INR VOL"},
2389 {"RECMIXR", "BST3 Switch", "BST3"},
2390 {"RECMIXR", "BST2 Switch", "BST2"},
2391 {"RECMIXR", "BST1 Switch", "BST1"},
2392 {"RECMIXR", "OUT MIXR Switch", "OUT MIXR"},
2394 {"ADC L", NULL, "RECMIXL"},
2395 {"ADC L", NULL, "ADC L power"},
2396 {"ADC R", NULL, "RECMIXR"},
2397 {"ADC R", NULL, "ADC R power"},
2399 {"DMIC L1", NULL, "DMIC CLK"},
2400 {"DMIC L2", NULL, "DMIC CLK"},
2402 {"Stereo ADC L2 Mux", "DMIC1", "DMIC L1"},
2403 {"Stereo ADC L2 Mux", "DMIC2", "DMIC L2"},
2404 {"Stereo ADC L2 Mux", "DIG MIX", "DIG MIXL"},
2405 {"Stereo ADC L1 Mux", "ADC", "ADC L"},
2406 {"Stereo ADC L1 Mux", "DIG MIX", "DIG MIXL"},
2408 {"Stereo ADC R1 Mux", "ADC", "ADC R"},
2409 {"Stereo ADC R1 Mux", "DIG MIX", "DIG MIXR"},
2410 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
2411 {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
2412 {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
2414 {"Mono ADC L2 Mux", "DMIC L1", "DMIC L1"},
2415 {"Mono ADC L2 Mux", "DMIC L2", "DMIC L2"},
2416 {"Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
2417 {"Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL"},
2418 {"Mono ADC L1 Mux", "ADCL", "ADC L"},
2420 {"Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
2421 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
2422 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
2423 {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
2424 {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
2426 {"Stereo ADC MIXL", "ADC1 Switch", "Stereo ADC L1 Mux"},
2427 {"Stereo ADC MIXL", "ADC2 Switch", "Stereo ADC L2 Mux"},
2428 {"Stereo ADC MIXL", NULL, "stereo filter"},
2429 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
2431 {"Stereo ADC MIXR", "ADC1 Switch", "Stereo ADC R1 Mux"},
2432 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
2433 {"Stereo ADC MIXR", NULL, "stereo filter"},
2434 {"stereo filter", NULL, "PLL1", check_sysclk1_source},
2436 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
2437 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
2438 {"Mono ADC MIXL", NULL, "mono left filter"},
2439 {"mono left filter", NULL, "PLL1", check_sysclk1_source},
2441 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
2442 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
2443 {"Mono ADC MIXR", NULL, "mono right filter"},
2444 {"mono right filter", NULL, "PLL1", check_sysclk1_source},
2446 {"IF2 ADC L Mux", "Mono ADC MIXL", "Mono ADC MIXL"},
2447 {"IF2 ADC R Mux", "Mono ADC MIXR", "Mono ADC MIXR"},
2449 {"IF2 ADC L", NULL, "IF2 ADC L Mux"},
2450 {"IF2 ADC R", NULL, "IF2 ADC R Mux"},
2451 {"IF3 ADC L", NULL, "Mono ADC MIXL"},
2452 {"IF3 ADC R", NULL, "Mono ADC MIXR"},
2453 {"IF1 ADC L", NULL, "Stereo ADC MIXL"},
2454 {"IF1 ADC R", NULL, "Stereo ADC MIXR"},
2456 {"IF1 ADC", NULL, "I2S1"},
2457 {"IF1 ADC", NULL, "IF1 ADC L"},
2458 {"IF1 ADC", NULL, "IF1 ADC R"},
2459 {"IF2 ADC", NULL, "I2S2"},
2460 {"IF2 ADC", NULL, "IF2 ADC L"},
2461 {"IF2 ADC", NULL, "IF2 ADC R"},
2462 {"IF3 ADC", NULL, "I2S3"},
2463 {"IF3 ADC", NULL, "IF3 ADC L"},
2464 {"IF3 ADC", NULL, "IF3 ADC R"},
2466 {"DAI1 TX Mux", "1:1|2:2|3:3", "IF1 ADC"},
2467 {"DAI1 TX Mux", "1:1|2:3|3:2", "IF1 ADC"},
2468 {"DAI1 TX Mux", "1:3|2:1|3:2", "IF2 ADC"},
2469 {"DAI1 TX Mux", "1:2|2:1|3:3", "IF2 ADC"},
2470 {"DAI1 TX Mux", "1:3|2:2|3:1", "IF3 ADC"},
2471 {"DAI1 TX Mux", "1:2|2:3|3:1", "IF3 ADC"},
2472 {"DAI1 IF1 Mux", "1:1|2:1|3:3", "IF1 ADC"},
2473 {"DAI1 IF2 Mux", "1:1|2:1|3:3", "IF2 ADC"},
2474 {"SDI1 TX Mux", "IF1", "DAI1 IF1 Mux"},
2475 {"SDI1 TX Mux", "IF2", "DAI1 IF2 Mux"},
2477 {"DAI2 TX Mux", "1:2|2:3|3:1", "IF1 ADC"},
2478 {"DAI2 TX Mux", "1:2|2:1|3:3", "IF1 ADC"},
2479 {"DAI2 TX Mux", "1:1|2:2|3:3", "IF2 ADC"},
2480 {"DAI2 TX Mux", "1:3|2:2|3:1", "IF2 ADC"},
2481 {"DAI2 TX Mux", "1:1|2:3|3:2", "IF3 ADC"},
2482 {"DAI2 TX Mux", "1:3|2:1|3:2", "IF3 ADC"},
2483 {"DAI2 IF1 Mux", "1:2|2:2|3:3", "IF1 ADC"},
2484 {"DAI2 IF2 Mux", "1:2|2:2|3:3", "IF2 ADC"},
2485 {"SDI2 TX Mux", "IF1", "DAI2 IF1 Mux"},
2486 {"SDI2 TX Mux", "IF2", "DAI2 IF2 Mux"},
2488 {"DAI3 TX Mux", "1:3|2:1|3:2", "IF1 ADC"},
2489 {"DAI3 TX Mux", "1:3|2:2|3:1", "IF1 ADC"},
2490 {"DAI3 TX Mux", "1:1|2:3|3:2", "IF2 ADC"},
2491 {"DAI3 TX Mux", "1:2|2:3|3:1", "IF2 ADC"},
2492 {"DAI3 TX Mux", "1:1|2:2|3:3", "IF3 ADC"},
2493 {"DAI3 TX Mux", "1:2|2:1|3:3", "IF3 ADC"},
2494 {"DAI3 TX Mux", "1:1|2:1|3:3", "IF3 ADC"},
2495 {"DAI3 TX Mux", "1:2|2:2|3:3", "IF3 ADC"},
2497 {"AIF1TX", NULL, "DAI1 TX Mux"},
2498 {"AIF1TX", NULL, "SDI1 TX Mux"},
2499 {"AIF2TX", NULL, "DAI2 TX Mux"},
2500 {"AIF2TX", NULL, "SDI2 TX Mux"},
2501 {"AIF3TX", NULL, "DAI3 TX Mux"},
2503 {"DAI1 RX Mux", "1:1|2:2|3:3", "AIF1RX"},
2504 {"DAI1 RX Mux", "1:1|2:3|3:2", "AIF1RX"},
2505 {"DAI1 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
2506 {"DAI1 RX Mux", "1:2|2:3|3:1", "AIF2RX"},
2507 {"DAI1 RX Mux", "1:2|2:1|3:3", "AIF2RX"},
2508 {"DAI1 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
2509 {"DAI1 RX Mux", "1:3|2:1|3:2", "AIF3RX"},
2510 {"DAI1 RX Mux", "1:3|2:2|3:1", "AIF3RX"},
2512 {"DAI2 RX Mux", "1:3|2:1|3:2", "AIF1RX"},
2513 {"DAI2 RX Mux", "1:2|2:1|3:3", "AIF1RX"},
2514 {"DAI2 RX Mux", "1:1|2:1|3:3", "AIF1RX"},
2515 {"DAI2 RX Mux", "1:1|2:2|3:3", "AIF2RX"},
2516 {"DAI2 RX Mux", "1:3|2:2|3:1", "AIF2RX"},
2517 {"DAI2 RX Mux", "1:2|2:2|3:3", "AIF2RX"},
2518 {"DAI2 RX Mux", "1:1|2:3|3:2", "AIF3RX"},
2519 {"DAI2 RX Mux", "1:2|2:3|3:1", "AIF3RX"},
2521 {"DAI3 RX Mux", "1:3|2:2|3:1", "AIF1RX"},
2522 {"DAI3 RX Mux", "1:2|2:3|3:1", "AIF1RX"},
2523 {"DAI3 RX Mux", "1:1|2:3|3:2", "AIF2RX"},
2524 {"DAI3 RX Mux", "1:3|2:1|3:2", "AIF2RX"},
2525 {"DAI3 RX Mux", "1:1|2:2|3:3", "AIF3RX"},
2526 {"DAI3 RX Mux", "1:2|2:1|3:3", "AIF3RX"},
2527 {"DAI3 RX Mux", "1:1|2:1|3:3", "AIF3RX"},
2528 {"DAI3 RX Mux", "1:2|2:2|3:3", "AIF3RX"},
2530 {"IF1 DAC", NULL, "I2S1"},
2531 {"IF1 DAC", NULL, "DAI1 RX Mux"},
2532 {"IF2 DAC", NULL, "I2S2"},
2533 {"IF2 DAC", NULL, "DAI2 RX Mux"},
2534 {"IF3 DAC", NULL, "I2S3"},
2535 {"IF3 DAC", NULL, "DAI3 RX Mux"},
2537 {"IF1 DAC L", NULL, "IF1 DAC"},
2538 {"IF1 DAC R", NULL, "IF1 DAC"},
2539 {"IF2 DAC L", NULL, "IF2 DAC"},
2540 {"IF2 DAC R", NULL, "IF2 DAC"},
2541 {"IF3 DAC L", NULL, "IF3 DAC"},
2542 {"IF3 DAC R", NULL, "IF3 DAC"},
2544 {"DAC MIXL", "Stereo ADC Switch", "Stereo ADC MIXL"},
2545 {"DAC MIXL", "INF1 Switch", "IF1 DAC L"},
2546 {"DAC MIXL", NULL, "DAC L1 Power"}, //bard 9-26
2547 {"DAC MIXR", "Stereo ADC Switch", "Stereo ADC MIXR"},
2548 {"DAC MIXR", "INF1 Switch", "IF1 DAC R"},
2549 {"DAC MIXR", NULL, "DAC R1 Power"}, //bard 9-26
2551 {"ANC", NULL, "Stereo ADC MIXL"},
2552 {"ANC", NULL, "Stereo ADC MIXR"},
2554 {"Audio DSP", NULL, "DAC MIXL"},
2555 {"Audio DSP", NULL, "DAC MIXR"},
2557 {"DAC L2 Mux", "IF2", "IF2 DAC L"},
2558 {"DAC L2 Mux", "IF3", "IF3 DAC L"},
2559 {"DAC L2 Mux", "Base L/R", "Audio DSP"},
2560 {"DAC L2 Volume", NULL, "DAC L2 Mux"},
2561 {"DAC L2 Volume", NULL, "DAC L2 Power"}, //bard 9-26
2563 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
2564 {"DAC R2 Mux", "IF3", "IF3 DAC R"},
2565 {"DAC R2 Volume", NULL, "Mono dacr Mux"},
2566 {"Mono dacr Mux", "TxDC_R", "DAC R2 Mux"},
2567 {"Mono dacr Mux", "TxDP_R", "IF2 ADC R Mux"},
2568 {"DAC R2 Volume", NULL, "DAC R2 Power"}, //bsrd 9-26
2570 {"Stereo DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
2571 {"Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2572 {"Stereo DAC MIXL", "ANC Switch", "ANC"},
2573 {"Stereo DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
2574 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2575 {"Stereo DAC MIXR", "ANC Switch", "ANC"},
2577 {"Mono DAC MIXL", "DAC L1 Switch", "DAC MIXL"},
2578 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2579 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume"},
2580 {"Mono DAC MIXR", "DAC R1 Switch", "DAC MIXR"},
2581 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2582 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume"},
2584 {"DIG MIXL", "DAC L1 Switch", "DAC MIXL"},
2585 {"DIG MIXL", "DAC L2 Switch", "DAC L2 Volume"},
2586 {"DIG MIXR", "DAC R1 Switch", "DAC MIXR"},
2587 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Volume"},
2589 {"DAC L1", NULL, "Stereo DAC MIXL"},
2590 {"DAC L1", NULL, "PLL1", check_sysclk1_source},
2591 {"DAC L1", NULL, "DAC L1 Power"}, //bard 9-26
2592 {"DAC R1", NULL, "Stereo DAC MIXR"},
2593 {"DAC R1", NULL, "PLL1", check_sysclk1_source},
2594 {"DAC R1", NULL, "DAC R1 Power"}, //bard 9-26
2595 {"DAC L2", NULL, "Mono DAC MIXL"},
2596 {"DAC L2", NULL, "PLL1", check_sysclk1_source},
2597 {"DAC L2", NULL, "DAC L2 Power"}, //bard 9-26
2598 {"DAC R2", NULL, "Mono DAC MIXR"},
2599 {"DAC R2", NULL, "PLL1", check_sysclk1_source},
2600 {"DAC R2", NULL, "DAC R2 Power"}, //bard 9-26
2602 {"SPK MIXL", "REC MIXL Switch", "RECMIXL"},
2603 {"SPK MIXL", "INL Switch", "INL VOL"},
2604 {"SPK MIXL", "DAC L1 Switch", "DAC L1"},
2605 {"SPK MIXL", "DAC L2 Switch", "DAC L2"},
2606 {"SPK MIXL", "OUT MIXL Switch", "OUT MIXL"},
2607 {"SPK MIXR", "REC MIXR Switch", "RECMIXR"},
2608 {"SPK MIXR", "INR Switch", "INR VOL"},
2609 {"SPK MIXR", "DAC R1 Switch", "DAC R1"},
2610 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
2611 {"SPK MIXR", "OUT MIXR Switch", "OUT MIXR"},
2613 {"OUT MIXL", "BST3 Switch", "BST3"},
2614 {"OUT MIXL", "BST1 Switch", "BST1"},
2615 {"OUT MIXL", "INL Switch", "INL VOL"},
2616 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
2617 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
2618 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
2619 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
2621 {"OUT MIXR", "BST3 Switch", "BST3"},
2622 {"OUT MIXR", "BST2 Switch", "BST2"},
2623 {"OUT MIXR", "BST1 Switch", "BST1"},
2624 {"OUT MIXR", "INR Switch", "INR VOL"},
2625 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
2626 {"OUT MIXR", "DAC L2 Switch", "DAC L2"},
2627 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
2628 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
2630 {"SPKVOL L", NULL, "SPK MIXL"},
2631 {"SPKVOL R", NULL, "SPK MIXR"},
2632 {"HPOVOL L", NULL, "OUT MIXL"},
2633 {"HPOVOL R", NULL, "OUT MIXR"},
2634 {"OUTVOL L", NULL, "OUT MIXL"},
2635 {"OUTVOL R", NULL, "OUT MIXR"},
2637 {"SPOL MIX", "DAC R1 Switch", "DAC R1"},
2638 {"SPOL MIX", "DAC L1 Switch", "DAC L1"},
2640 {"SPOL MIX", "DAC Switch", "DAC SPK"},
2641 {"DAC SPK", "DAC L1 Switch", "DAC L1"},
2642 {"DAC SPK", "DAC R1 Switch", "DAC R1"},
2644 {"SPOL MIX", "SPKVOL R Switch", "SPKVOL R"},
2645 {"SPOL MIX", "SPKVOL L Switch", "SPKVOL L"},
2646 {"SPOL MIX", "BST1 Switch", "BST1"},
2647 {"SPOR MIX", "DAC R1 Switch", "DAC R1"},
2648 {"SPOR MIX", "SPKVOL R Switch", "SPKVOL R"},
2649 {"SPOR MIX", "BST1 Switch", "BST1"},
2651 {"DAC 2", NULL, "DAC L2"},
2652 {"DAC 2", NULL, "DAC R2"},
2653 {"DAC 1", NULL, "DAC L1"},
2654 {"DAC 1", NULL, "DAC R1"},
2655 {"HPOVOL", NULL, "HPOVOL L"},
2656 {"HPOVOL", NULL, "HPOVOL R"},
2657 {"HPO MIX", "DAC2 Switch", "DAC 2"},
2658 {"HPO MIX", "DAC1 Switch", "DAC 1"},
2659 {"HPO MIX", "HPVOL Switch", "HPOVOL"},
2661 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
2662 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
2663 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
2664 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
2666 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
2667 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
2668 {"Mono MIX", "OUTVOL R Switch", "OUTVOL R"},
2669 {"Mono MIX", "OUTVOL L Switch", "OUTVOL L"},
2670 {"Mono MIX", "BST1 Switch", "BST1"},
2672 {"SPK amp", NULL, "SPOL MIX"},
2673 {"SPK amp", NULL, "SPOR MIX"},
2674 {"SPOLP", NULL, "SPK amp"},
2675 {"SPOLN", NULL, "SPK amp"},
2676 {"SPORP", NULL, "SPK amp"},
2677 {"SPORN", NULL, "SPK amp"},
2679 {"HP amp", NULL, "HPO MIX"},
2680 {"HPOL", NULL, "HP amp"},
2681 {"HPOR", NULL, "HP amp"},
2683 {"LOUT amp", NULL, "LOUT MIX"},
2684 {"LOUTL", NULL, "LOUT amp"},
2685 {"LOUTR", NULL, "LOUT amp"},
2687 {"Mono amp", NULL, "Mono MIX"},
2688 {"MonoP", NULL, "Mono amp"},
2689 {"MonoN", NULL, "Mono amp"},
2692 static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
2699 val = snd_soc_read(codec, RT3261_I2S1_SDP);
2700 val = (val & RT3261_I2S_IF_MASK) >> RT3261_I2S_IF_SFT;
2703 if (val == RT3261_IF_123 || val == RT3261_IF_132 ||
2704 val == RT3261_IF_113)
2705 ret |= RT3261_U_IF1;
2706 if (val == RT3261_IF_312 || val == RT3261_IF_213 ||
2707 val == RT3261_IF_113)
2708 ret |= RT3261_U_IF2;
2709 if (val == RT3261_IF_321 || val == RT3261_IF_231)
2710 ret |= RT3261_U_IF3;
2714 if (val == RT3261_IF_231 || val == RT3261_IF_213 ||
2715 val == RT3261_IF_223)
2716 ret |= RT3261_U_IF1;
2717 if (val == RT3261_IF_123 || val == RT3261_IF_321 ||
2718 val == RT3261_IF_223)
2719 ret |= RT3261_U_IF2;
2720 if (val == RT3261_IF_132 || val == RT3261_IF_312)
2721 ret |= RT3261_U_IF3;
2732 static int get_clk_info(int sclk, int rate)
2734 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
2736 if (sclk <= 0 || rate <= 0)
2740 for (i = 0; i < ARRAY_SIZE(pd); i++)
2741 if (sclk == rate * pd[i])
2747 static int rt3261_hw_params(struct snd_pcm_substream *substream,
2748 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2750 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2751 struct snd_soc_codec *codec = rtd->codec;
2752 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2753 unsigned int val_len = 0, val_clk, mask_clk, dai_sel;
2754 int pre_div, bclk_ms, frame_size;
2756 rt3261->lrck[dai->id] = params_rate(params);
2758 rt3261->lrck[dai->id] = 8000;
2759 pre_div = get_clk_info(rt3261->sysclk, rt3261->lrck[dai->id]);
2761 dev_err(codec->dev, "Unsupported clock setting\n");
2764 frame_size = snd_soc_params_to_frame_size(params);
2765 if (frame_size < 0) {
2766 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2769 bclk_ms = frame_size > 32 ? 1 : 0;
2770 rt3261->bclk[dai->id] = rt3261->lrck[dai->id] * (32 << bclk_ms);
2772 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2773 rt3261->bclk[dai->id], rt3261->lrck[dai->id]);
2774 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2775 bclk_ms, pre_div, dai->id);
2777 switch (params_format(params)) {
2778 case SNDRV_PCM_FORMAT_S16_LE:
2780 case SNDRV_PCM_FORMAT_S20_3LE:
2781 val_len |= RT3261_I2S_DL_20;
2783 case SNDRV_PCM_FORMAT_S24_LE:
2784 val_len |= RT3261_I2S_DL_24;
2786 case SNDRV_PCM_FORMAT_S8:
2787 val_len |= RT3261_I2S_DL_8;
2793 dai_sel = get_sdp_info(codec, dai->id);
2794 dai_sel |= (RT3261_U_IF1 | RT3261_U_IF2);
2796 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
2799 if (dai_sel & RT3261_U_IF1) {
2800 mask_clk = RT3261_I2S_BCLK_MS1_MASK | RT3261_I2S_PD1_MASK;
2801 val_clk = bclk_ms << RT3261_I2S_BCLK_MS1_SFT |
2802 pre_div << RT3261_I2S_PD1_SFT;
2803 snd_soc_update_bits(codec, RT3261_I2S1_SDP,
2804 RT3261_I2S_DL_MASK, val_len);
2805 snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
2807 if (dai_sel & RT3261_U_IF2) {
2808 mask_clk = RT3261_I2S_BCLK_MS2_MASK | RT3261_I2S_PD2_MASK;
2809 val_clk = bclk_ms << RT3261_I2S_BCLK_MS2_SFT |
2810 pre_div << RT3261_I2S_PD2_SFT;
2811 snd_soc_update_bits(codec, RT3261_I2S2_SDP,
2812 RT3261_I2S_DL_MASK, val_len);
2813 snd_soc_update_bits(codec, RT3261_ADDA_CLK1, mask_clk, val_clk);
2819 static int rt3261_prepare(struct snd_pcm_substream *substream,
2820 struct snd_soc_dai *dai)
2822 struct snd_soc_pcm_runtime *rtd = substream->private_data;
2823 struct snd_soc_codec *codec = rtd->codec;
2824 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2826 rt3261->aif_pu = dai->id;
2830 static int rt3261_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2832 struct snd_soc_codec *codec = dai->codec;
2833 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2834 unsigned int reg_val = 0, dai_sel;
2836 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2837 case SND_SOC_DAIFMT_CBM_CFM:
2838 rt3261->master[dai->id] = 1;
2840 case SND_SOC_DAIFMT_CBS_CFS:
2841 reg_val |= RT3261_I2S_MS_S;
2842 rt3261->master[dai->id] = 0;
2848 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2849 case SND_SOC_DAIFMT_NB_NF:
2851 case SND_SOC_DAIFMT_IB_NF:
2852 reg_val |= RT3261_I2S_BP_INV;
2858 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2859 case SND_SOC_DAIFMT_I2S:
2861 case SND_SOC_DAIFMT_LEFT_J:
2862 reg_val |= RT3261_I2S_DF_LEFT;
2864 case SND_SOC_DAIFMT_DSP_A:
2865 reg_val |= RT3261_I2S_DF_PCM_A;
2867 case SND_SOC_DAIFMT_DSP_B:
2868 reg_val |= RT3261_I2S_DF_PCM_B;
2874 dai_sel = get_sdp_info(codec, dai->id);
2876 dev_err(codec->dev, "Failed to get sdp info: %d\n", dai_sel);
2879 if (dai_sel & RT3261_U_IF1) {
2880 snd_soc_update_bits(codec, RT3261_I2S1_SDP,
2881 RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
2882 RT3261_I2S_DF_MASK, reg_val);
2884 if (dai_sel & RT3261_U_IF2) {
2885 snd_soc_update_bits(codec, RT3261_I2S2_SDP,
2886 RT3261_I2S_MS_MASK | RT3261_I2S_BP_MASK |
2887 RT3261_I2S_DF_MASK, reg_val);
2893 static int rt3261_set_dai_sysclk(struct snd_soc_dai *dai,
2894 int clk_id, unsigned int freq, int dir)
2896 struct snd_soc_codec *codec = dai->codec;
2897 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2898 unsigned int reg_val = 0;
2900 if (freq == rt3261->sysclk && clk_id == rt3261->sysclk_src)
2904 case RT3261_SCLK_S_MCLK:
2905 reg_val |= RT3261_SCLK_SRC_MCLK;
2907 case RT3261_SCLK_S_PLL1:
2908 reg_val |= RT3261_SCLK_SRC_PLL1;
2910 case RT3261_SCLK_S_RCCLK:
2911 reg_val |= RT3261_SCLK_SRC_RCCLK;
2914 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2917 snd_soc_update_bits(codec, RT3261_GLB_CLK,
2918 RT3261_SCLK_SRC_MASK, reg_val);
2919 rt3261->sysclk = freq;
2920 rt3261->sysclk_src = clk_id;
2922 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2928 * rt3261_pll_calc - Calcualte PLL M/N/K code.
2929 * @freq_in: external clock provided to codec.
2930 * @freq_out: target clock which codec works on.
2931 * @pll_code: Pointer to structure with M, N, K and bypass flag.
2933 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
2934 * which make calculation more efficiently.
2936 * Returns 0 for success or negative error code.
2938 static int rt3261_pll_calc(const unsigned int freq_in,
2939 const unsigned int freq_out, struct rt3261_pll_code *pll_code)
2941 int max_n = RT3261_PLL_N_MAX, max_m = RT3261_PLL_M_MAX;
2942 int n, m, red, n_t, m_t, in_t, out_t, red_t = abs(freq_out - freq_in);
2943 bool bypass = false;
2945 if (RT3261_PLL_INP_MAX < freq_in || RT3261_PLL_INP_MIN > freq_in)
2948 for (n_t = 0; n_t <= max_n; n_t++) {
2949 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
2952 if (in_t == freq_out) {
2957 for (m_t = 0; m_t <= max_m; m_t++) {
2958 out_t = in_t / (m_t + 2);
2959 red = abs(out_t - freq_out);
2969 pr_debug("Only get approximation about PLL\n");
2973 pll_code->m_bp = bypass;
2974 pll_code->m_code = m;
2975 pll_code->n_code = n;
2976 pll_code->k_code = 2;
2980 static int rt3261_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2981 unsigned int freq_in, unsigned int freq_out)
2983 struct snd_soc_codec *codec = dai->codec;
2984 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
2985 struct rt3261_pll_code pll_code;
2988 if (source == rt3261->pll_src && freq_in == rt3261->pll_in &&
2989 freq_out == rt3261->pll_out)
2992 if (!freq_in || !freq_out) {
2993 dev_dbg(codec->dev, "PLL disabled\n");
2996 rt3261->pll_out = 0;
2997 snd_soc_update_bits(codec, RT3261_GLB_CLK,
2998 RT3261_SCLK_SRC_MASK, RT3261_SCLK_SRC_MCLK);
3003 case RT3261_PLL1_S_MCLK:
3004 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3005 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_MCLK);
3007 case RT3261_PLL1_S_BCLK1:
3008 case RT3261_PLL1_S_BCLK2:
3009 dai_sel = get_sdp_info(codec, dai->id);
3012 "Failed to get sdp info: %d\n", dai_sel);
3015 if (dai_sel & RT3261_U_IF1) {
3016 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3017 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK1);
3019 if (dai_sel & RT3261_U_IF2) {
3020 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3021 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK2);
3023 if (dai_sel & RT3261_U_IF3) {
3024 snd_soc_update_bits(codec, RT3261_GLB_CLK,
3025 RT3261_PLL1_SRC_MASK, RT3261_PLL1_SRC_BCLK3);
3029 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3033 ret = rt3261_pll_calc(freq_in, freq_out, &pll_code);
3035 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3039 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code.m_bp,
3040 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code);
3042 snd_soc_write(codec, RT3261_PLL_CTRL1,
3043 pll_code.n_code << RT3261_PLL_N_SFT | pll_code.k_code);
3044 snd_soc_write(codec, RT3261_PLL_CTRL2,
3045 (pll_code.m_bp ? 0 : pll_code.m_code) << RT3261_PLL_M_SFT |
3046 pll_code.m_bp << RT3261_PLL_M_BP_SFT);
3048 rt3261->pll_in = freq_in;
3049 rt3261->pll_out = freq_out;
3050 rt3261->pll_src = source;
3056 * rt3261_index_show - Dump private registers.
3057 * @dev: codec device.
3058 * @attr: device attribute.
3059 * @buf: buffer for display.
3061 * To show non-zero values of all private registers.
3063 * Returns buffer length.
3065 static ssize_t rt3261_index_show(struct device *dev,
3066 struct device_attribute *attr, char *buf)
3068 struct i2c_client *client = to_i2c_client(dev);
3069 struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
3070 struct snd_soc_codec *codec = rt3261->codec;
3074 cnt += sprintf(buf, "RT3261 index register\n");
3075 for (i = 0; i < 0xb4; i++) {
3076 if (cnt + RT3261_REG_DISP_LEN >= PAGE_SIZE)
3078 val = rt3261_index_read(codec, i);
3081 cnt += snprintf(buf + cnt, RT3261_REG_DISP_LEN,
3082 "%02x: %04x\n", i, val);
3085 if (cnt >= PAGE_SIZE)
3086 cnt = PAGE_SIZE - 1;
3090 static DEVICE_ATTR(index_reg, 0444, rt3261_index_show, NULL);
3092 static int rt3261_set_bias_level(struct snd_soc_codec *codec,
3093 enum snd_soc_bias_level level)
3096 case SND_SOC_BIAS_ON:
3099 case SND_SOC_BIAS_PREPARE:
3100 /* headphone mute sequence */
3101 snd_soc_update_bits(codec, RT3261_DEPOP_M3,
3102 RT3261_CP_FQ1_MASK | RT3261_CP_FQ2_MASK | RT3261_CP_FQ3_MASK,
3103 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ1_SFT) |
3104 (RT3261_CP_FQ_12_KHZ << RT3261_CP_FQ2_SFT) |
3105 (RT3261_CP_FQ_96_KHZ << RT3261_CP_FQ3_SFT));
3106 rt3261_index_write(codec, RT3261_MAMP_INT_REG2, 0xfc00);
3107 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
3108 RT3261_HP_SG_MASK, RT3261_HP_SG_EN);
3109 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
3110 RT3261_RSTP_MASK, RT3261_RSTP_EN);
3111 snd_soc_update_bits(codec, RT3261_DEPOP_M1,
3112 RT3261_RSTP_MASK | RT3261_HP_L_SMT_MASK |
3113 RT3261_HP_R_SMT_MASK, RT3261_RSTP_DIS |
3114 RT3261_HP_L_SMT_EN | RT3261_HP_R_SMT_EN);
3116 snd_soc_update_bits(codec, RT3261_HP_VOL,
3117 RT3261_L_MUTE | RT3261_R_MUTE, RT3261_L_MUTE | RT3261_R_MUTE);
3119 snd_soc_write(codec, RT3261_DEPOP_M1, 0x0004);
3121 snd_soc_update_bits(codec, RT3261_SPK_VOL,
3122 RT3261_L_MUTE | RT3261_R_MUTE,
3123 RT3261_L_MUTE | RT3261_R_MUTE);
3124 snd_soc_update_bits(codec, RT3261_PWR_ANLG2,
3125 RT3261_PWR_MB1 | RT3261_PWR_MB2,
3126 RT3261_PWR_MB1 | RT3261_PWR_MB2);
3129 case SND_SOC_BIAS_STANDBY:
3130 if (SND_SOC_BIAS_OFF == codec->dapm.bias_level) {
3131 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3132 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3133 RT3261_PWR_BG | RT3261_PWR_VREF2,
3134 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3135 RT3261_PWR_BG | RT3261_PWR_VREF2);
3137 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3138 RT3261_PWR_FV1 | RT3261_PWR_FV2,
3139 RT3261_PWR_FV1 | RT3261_PWR_FV2);
3140 snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3701);
3141 codec->cache_only = false;
3142 codec->cache_sync = 1;
3143 snd_soc_cache_sync(codec);
3144 rt3261_index_sync(codec);
3148 case SND_SOC_BIAS_OFF:
3149 snd_soc_write(codec, RT3261_DEPOP_M1, 0x0004);
3150 snd_soc_write(codec, RT3261_DEPOP_M2, 0x1100);
3151 snd_soc_write(codec, RT3261_GEN_CTRL1, 0x3700);
3152 snd_soc_write(codec, RT3261_PWR_DIG1, 0x0000);
3153 snd_soc_write(codec, RT3261_PWR_DIG2, 0x0000);
3154 snd_soc_write(codec, RT3261_PWR_VOL, 0x0000);
3155 snd_soc_write(codec, RT3261_PWR_MIXER, 0x0000);
3156 snd_soc_write(codec, RT3261_PWR_ANLG1, 0x0000);
3157 snd_soc_write(codec, RT3261_PWR_ANLG2, 0x0000);
3163 codec->dapm.bias_level = level;
3168 static int rt3261_proc_init(void);
3171 static int rt3261_probe(struct snd_soc_codec *codec)
3173 struct rt3261_priv *rt3261 = snd_soc_codec_get_drvdata(codec);
3175 struct clk *iis_clk;
3177 #if defined (CONFIG_SND_SOC_RT3224)
3178 pr_info("Codec driver version %s, in fact you choose rt3224, no dsp!\n", VERSION);
3180 pr_info("Codec driver version %s, in fact you choose rt3261 with a dsp!\n", VERSION);
3183 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
3185 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
3188 codec->write = rt3261_write;
3194 #if defined (CONFIG_SND_SOC_RT5623)
3195 //for rt5623 MCLK use
3196 iis_clk = clk_get_sys("rk29_i2s.2", "i2s");
3197 if (IS_ERR(iis_clk)) {
3198 DBG("failed to get i2s clk\n");
3199 ret = PTR_ERR(iis_clk);
3201 DBG("I2S2 got i2s clk ok!\n");
3202 clk_enable(iis_clk);
3203 clk_set_rate(iis_clk, 11289600);
3204 rk30_mux_api_set(GPIO0D0_I2S22CHCLK_SMCCSN0_NAME, GPIO0D_I2S2_2CH_CLK);
3209 rt3261_reset(codec);
3210 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3211 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3212 RT3261_PWR_BG | RT3261_PWR_VREF2,
3213 RT3261_PWR_VREF1 | RT3261_PWR_MB |
3214 RT3261_PWR_BG | RT3261_PWR_VREF2);
3216 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3217 RT3261_PWR_FV1 | RT3261_PWR_FV2,
3218 RT3261_PWR_FV1 | RT3261_PWR_FV2);
3220 if (rt3261->dmic_en == RT3261_DMIC1) {
3221 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
3222 RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
3223 snd_soc_update_bits(codec, RT3261_DMIC,
3224 RT3261_DMIC_1L_LH_MASK | RT3261_DMIC_1R_LH_MASK,
3225 RT3261_DMIC_1L_LH_FALLING | RT3261_DMIC_1R_LH_RISING);
3226 } else if (rt3261->dmic_en == RT3261_DMIC2) {
3227 snd_soc_update_bits(codec, RT3261_GPIO_CTRL1,
3228 RT3261_GP2_PIN_MASK, RT3261_GP2_PIN_DMIC1_SCL);
3229 snd_soc_update_bits(codec, RT3261_DMIC,
3230 RT3261_DMIC_2L_LH_MASK | RT3261_DMIC_2R_LH_MASK,
3231 RT3261_DMIC_2L_LH_FALLING | RT3261_DMIC_2R_LH_RISING);
3233 snd_soc_write(codec, RT3261_GEN_CTRL2, 0x4040);
3234 ret = snd_soc_read(codec, RT3261_VENDOR_ID);
3235 printk("read codec chip id is 0x%x\n",ret);
3237 snd_soc_update_bits(codec, RT3261_JD_CTRL,
3238 RT3261_JD1_IN4P_MASK | RT3261_JD2_IN4N_MASK,
3239 RT3261_JD1_IN4P_EN | RT3261_JD2_IN4N_EN);
3243 printk("you use an old chip, please use a new one\n");
3245 snd_soc_update_bits(codec, RT3261_PWR_ANLG1,
3246 RT3261_PWR_HP_L | RT3261_PWR_HP_R,
3248 rt3261_reg_init(codec);
3249 rt3261_customer_redefine(codec, rt3261);
3251 codec->dapm.bias_level = SND_SOC_BIAS_STANDBY;
3252 rt3261->codec = codec;
3254 snd_soc_add_controls(codec, rt3261_snd_controls,
3255 ARRAY_SIZE(rt3261_snd_controls));
3256 snd_soc_dapm_new_controls(&codec->dapm, rt3261_dapm_widgets,
3257 ARRAY_SIZE(rt3261_dapm_widgets));
3258 snd_soc_dapm_add_routes(&codec->dapm, rt3261_dapm_routes,
3259 ARRAY_SIZE(rt3261_dapm_routes));
3262 #if defined (CONFIG_SND_SOC_RT3261)
3263 rt3261->dsp_sw = RT3261_DSP_AEC_NS_FENS;
3264 rt3261_dsp_probe(codec);
3268 #if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
3269 struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
3270 ioctl_ops->index_write = rt3261_index_write;
3271 ioctl_ops->index_read = rt3261_index_read;
3272 ioctl_ops->index_update_bits = rt3261_index_update_bits;
3273 ioctl_ops->ioctl_common = rt3261_ioctl_common;
3274 realtek_ce_init_hwdep(codec);
3279 ret = device_create_file(codec->dev, &dev_attr_index_reg);
3282 "Failed to create index_reg sysfs files: %d\n", ret);
3285 rt3261_codec = codec;
3289 static int rt3261_remove(struct snd_soc_codec *codec)
3291 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3296 static int rt3261_suspend(struct snd_soc_codec *codec, pm_message_t state)
3298 #if defined (CONFIG_SND_SOC_RT3261)
3299 /* After opening LDO of DSP, then close LDO of codec.
3300 * (1) DSP LDO power on
3301 * (2) DSP core power off
3302 * (3) DSP IIS interface power off
3303 * (4) Toggle pin of codec LDO1 to power off
3305 rt3261_dsp_suspend(codec, state);
3307 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3311 static int rt3261_resume(struct snd_soc_codec *codec)
3313 rt3261_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3314 #if defined (CONFIG_SND_SOC_RT3261)
3315 /* After opening LDO of codec, then close LDO of DSP. */
3316 rt3261_dsp_resume(codec);
3321 #define rt3261_suspend NULL
3322 #define rt3261_resume NULL
3325 #define RT3261_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3326 #define RT3261_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3327 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3329 struct snd_soc_dai_ops rt3261_aif_dai_ops = {
3330 .hw_params = rt3261_hw_params,
3331 .prepare = rt3261_prepare,
3332 .set_fmt = rt3261_set_dai_fmt,
3333 .set_sysclk = rt3261_set_dai_sysclk,
3334 .set_pll = rt3261_set_dai_pll,
3337 struct snd_soc_dai_driver rt3261_dai[] = {
3339 .name = "rt3261-aif1",
3342 .stream_name = "AIF1 Playback",
3345 .rates = RT3261_STEREO_RATES,
3346 .formats = RT3261_FORMATS,
3349 .stream_name = "AIF1 Capture",
3352 .rates = RT3261_STEREO_RATES,
3353 .formats = RT3261_FORMATS,
3355 .ops = &rt3261_aif_dai_ops,
3358 .name = "rt3261-aif2",
3361 .stream_name = "AIF2 Playback",
3364 .rates = RT3261_STEREO_RATES,
3365 .formats = RT3261_FORMATS,
3368 .stream_name = "AIF2 Capture",
3371 .rates = RT3261_STEREO_RATES,
3372 .formats = RT3261_FORMATS,
3374 .ops = &rt3261_aif_dai_ops,
3378 static struct snd_soc_codec_driver soc_codec_dev_rt3261 = {
3379 .probe = rt3261_probe,
3380 .remove = rt3261_remove,
3381 .suspend = rt3261_suspend,
3382 .resume = rt3261_resume,
3383 .write = rt3261_write,
3384 .set_bias_level = rt3261_set_bias_level,
3385 .reg_cache_size = RT3261_VENDOR_ID2 + 1,
3386 .reg_word_size = sizeof(u16),
3387 .reg_cache_default = rt3261_reg,
3388 .volatile_register = rt3261_volatile_register,
3389 .readable_register = rt3261_readable_register,
3390 .reg_cache_step = 1,
3393 static const struct i2c_device_id rt3261_i2c_id[] = {
3397 MODULE_DEVICE_TABLE(i2c, rt3261_i2c_id);
3399 static int __devinit rt3261_i2c_probe(struct i2c_client *i2c,
3400 const struct i2c_device_id *id)
3402 struct rt3261_priv *rt3261;
3404 struct rt3261_platform_data *pdata = pdata = i2c->dev.platform_data;
3406 rt3261 = kzalloc(sizeof(struct rt3261_priv), GFP_KERNEL);
3410 rt3261->codec_en_gpio = pdata->codec_en_gpio;
3411 rt3261->io_init = pdata->io_init;
3412 rt3261->spk_num = pdata->spk_num;
3413 rt3261->modem_input_mode = pdata->modem_input_mode;
3414 rt3261->lout_to_modem_mode = pdata->lout_to_modem_mode;
3415 rt3261->spk_amplify = pdata->spk_amplify;
3416 rt3261->playback_if1_data_control = pdata->playback_if1_data_control;
3417 rt3261->playback_if2_data_control = pdata->playback_if2_data_control;
3420 rt3261->io_init(pdata->codec_en_gpio, pdata->codec_en_gpio_info.iomux_name, pdata->codec_en_gpio_info.iomux_mode);
3422 #if defined (CONFIG_SND_SOC_RT5623)
3423 rt3261->modem_is_open = 0;
3426 i2c_set_clientdata(i2c, rt3261);
3427 DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
3428 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt3261,
3429 rt3261_dai, ARRAY_SIZE(rt3261_dai));
3436 static int __devexit rt3261_i2c_remove(struct i2c_client *i2c)
3438 snd_soc_unregister_codec(&i2c->dev);
3439 kfree(i2c_get_clientdata(i2c));
3443 static void rt3261_i2c_shutdown(struct i2c_client *client)
3445 struct rt3261_priv *rt3261 = i2c_get_clientdata(client);
3446 struct snd_soc_codec *codec = rt3261->codec;
3449 rt3261_set_bias_level(codec, SND_SOC_BIAS_OFF);
3452 struct i2c_driver rt3261_i2c_driver = {
3455 .owner = THIS_MODULE,
3457 .probe = rt3261_i2c_probe,
3458 .remove = __devexit_p(rt3261_i2c_remove),
3459 .shutdown = rt3261_i2c_shutdown,
3460 .id_table = rt3261_i2c_id,
3463 static int __init rt3261_modinit(void)
3465 return i2c_add_driver(&rt3261_i2c_driver);
3467 module_init(rt3261_modinit);
3469 static void __exit rt3261_modexit(void)
3471 i2c_del_driver(&rt3261_i2c_driver);
3473 module_exit(rt3261_modexit);
3475 MODULE_DESCRIPTION("ASoC RT3261 driver");
3476 MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
3477 MODULE_LICENSE("GPL");
3482 static ssize_t rt3261_proc_write(struct file *file, const char __user *buffer,
3483 unsigned long len, void *data)
3490 #if defined (CONFIG_SND_SOC_RT3261)
3491 struct rt3261_dsp_param param;
3494 cookie_pot = (char *)vmalloc( len );
3501 if (copy_from_user( cookie_pot, buffer, len ))
3505 switch(cookie_pot[0])
3509 printk("Read reg debug\n");
3510 if(cookie_pot[1] ==':')
3512 strsep(&cookie_pot,":");
3513 while((p=strsep(&cookie_pot,",")))
3515 reg = simple_strtol(p,NULL,16);
3516 value = rt3261_read(rt3261_codec,reg);
3517 printk("rt3261_read:0x%04x = 0x%04x\n",reg,value);
3523 printk("Error Read reg debug.\n");
3524 printk("For example: echo r:22,23,24,25>rt3261_ts\n");
3529 printk("Write reg debug\n");
3530 if(cookie_pot[1] ==':')
3532 strsep(&cookie_pot,":");
3533 while((p=strsep(&cookie_pot,"=")))
3535 reg = simple_strtol(p,NULL,16);
3536 p=strsep(&cookie_pot,",");
3537 value = simple_strtol(p,NULL,16);
3538 rt3261_write(rt3261_codec,reg,value);
3539 printk("rt3261_write:0x%04x = 0x%04x\n",reg,value);
3545 printk("Error Write reg debug.\n");
3546 printk("For example: w:22=0,23=0,24=0,25=0>rt3261_ts\n");
3550 printk("Dump rt3261 index reg \n");
3552 for (i = 0; i < 0xb4; i++)
3554 value = rt3261_index_read(rt3261_codec, i);
3555 printk("rt3261_index_read:0x%04x = 0x%04x\n",i,value);
3558 #if defined (CONFIG_SND_SOC_RT3261)
3560 param.cmd_fmt = 0x00e0;
3561 param.cmd = RT3261_DSP_CMD_MW;
3562 printk("Write dsp reg debug\n");
3563 if(cookie_pot[1] ==':')
3565 strsep(&cookie_pot,":");
3566 while((p=strsep(&cookie_pot,"=")))
3568 param.addr = simple_strtol(p,NULL,16);
3569 p=strsep(&cookie_pot,",");
3570 param.data = simple_strtol(p,NULL,16);
3571 rt3261_dsp_write(rt3261_codec,¶m);
3572 printk("rt3261_dsp_write:0x%04x = 0x%04x\n",param.addr,param.data);
3578 printk("Read dsp reg debug\n");
3579 if(cookie_pot[1] ==':')
3581 strsep(&cookie_pot,":");
3582 while((p=strsep(&cookie_pot,",")))
3584 reg = simple_strtol(p,NULL,16);
3585 value = rt3261_dsp_read(rt3261_codec,reg);
3586 printk("rt3261_dsp_read:0x%04x = 0x%04x\n",reg,value);
3593 if(cookie_pot[1] ==':')
3595 strsep(&cookie_pot,":");
3596 while((p=strsep(&cookie_pot,"=")))
3598 reg = simple_strtol(p,NULL,16);
3599 p=strsep(&cookie_pot,",");
3600 value = simple_strtol(p,NULL,16);
3601 rt3261_index_write(rt3261_codec,reg,value);
3602 printk("rt3261_index_write:0x%04x = 0x%04x\n",reg,value);
3608 if(cookie_pot[1] ==':')
3610 strsep(&cookie_pot,":");
3611 while((p=strsep(&cookie_pot,",")))
3613 reg = simple_strtol(p,NULL,16);
3614 value = rt3261_index_read(rt3261_codec,reg);
3615 printk("rt3261_index_read:0x%04x = 0x%04x\n",reg,value);
3621 printk("Help for rt3261_ts .\n-->The Cmd list: \n");
3622 printk("-->'d&&D' Open or Off the debug\n");
3623 printk("-->'r&&R' Read reg debug,Example: echo 'r:22,23,24,25'>rt3261_ts\n");
3624 printk("-->'w&&W' Write reg debug,Example: echo 'w:22=0,23=0,24=0,25=0'>rt3261_ts\n");
3631 static const struct file_operations rt3261_proc_fops = {
3632 .owner = THIS_MODULE,
3635 static int rt3261_proc_init(void)
3637 struct proc_dir_entry *rt3261_proc_entry;
3638 rt3261_proc_entry = create_proc_entry("driver/rt3261_ts", 0777, NULL);
3639 if(rt3261_proc_entry != NULL)
3641 rt3261_proc_entry->write_proc = rt3261_proc_write;
3646 printk("create proc error !\n");