2 * rt3261.h -- RT3261 ALSA SoC audio driver
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
16 #define RT3261_RESET 0x00
17 #define RT3261_VENDOR_ID 0xfd
18 #define RT3261_VENDOR_ID1 0xfe
19 #define RT3261_VENDOR_ID2 0xff
21 #define RT3261_SPK_VOL 0x01
22 #define RT3261_HP_VOL 0x02
23 #define RT3261_OUTPUT 0x03
24 #define RT3261_MONO_OUT 0x04
26 #define RT3261_DUMMY_PR3F 0x05
27 #define RT3261_DUMMY_SPKMIXER 0x06
29 #define RT3261_IN1_IN2 0x0d
30 #define RT3261_IN3_IN4 0x0e
31 #define RT3261_INL_INR_VOL 0x0f
32 /* I/O - ADC/DAC/DMIC */
33 #define RT3261_DAC1_DIG_VOL 0x19
34 #define RT3261_DAC2_DIG_VOL 0x1a
35 #define RT3261_DAC2_CTRL 0x1b
36 #define RT3261_ADC_DIG_VOL 0x1c
37 #define RT3261_ADC_DATA 0x1d
38 #define RT3261_ADC_BST_VOL 0x1e
40 #define RT3261_STO_ADC_MIXER 0x27
41 #define RT3261_MONO_ADC_MIXER 0x28
42 #define RT3261_AD_DA_MIXER 0x29
43 #define RT3261_STO_DAC_MIXER 0x2a
44 #define RT3261_MONO_DAC_MIXER 0x2b
45 #define RT3261_DIG_MIXER 0x2c
46 #define RT3261_DSP_PATH1 0x2d
47 #define RT3261_DSP_PATH2 0x2e
48 #define RT3261_DIG_INF_DATA 0x2f
50 #define RT3261_REC_L1_MIXER 0x3b
51 #define RT3261_REC_L2_MIXER 0x3c
52 #define RT3261_REC_R1_MIXER 0x3d
53 #define RT3261_REC_R2_MIXER 0x3e
55 #define RT3261_HPO_MIXER 0x45
56 #define RT3261_SPK_L_MIXER 0x46
57 #define RT3261_SPK_R_MIXER 0x47
58 #define RT3261_SPO_L_MIXER 0x48
59 #define RT3261_SPO_R_MIXER 0x49
60 #define RT3261_SPO_CLSD_RATIO 0x4a
61 #define RT3261_MONO_MIXER 0x4c
62 #define RT3261_OUT_L1_MIXER 0x4d
63 #define RT3261_OUT_L2_MIXER 0x4e
64 #define RT3261_OUT_L3_MIXER 0x4f
65 #define RT3261_OUT_R1_MIXER 0x50
66 #define RT3261_OUT_R2_MIXER 0x51
67 #define RT3261_OUT_R3_MIXER 0x52
68 #define RT3261_LOUT_MIXER 0x53
70 #define RT3261_PWR_DIG1 0x61
71 #define RT3261_PWR_DIG2 0x62
72 #define RT3261_PWR_ANLG1 0x63
73 #define RT3261_PWR_ANLG2 0x64
74 #define RT3261_PWR_MIXER 0x65
75 #define RT3261_PWR_VOL 0x66
76 /* Private Register Control */
77 #define RT3261_PRIV_INDEX 0x6a
78 #define RT3261_PRIV_DATA 0x6c
79 /* Format - ADC/DAC */
80 #define RT3261_I2S1_SDP 0x70
81 #define RT3261_I2S2_SDP 0x71
82 #define RT3261_I2S3_SDP 0x72
83 #define RT3261_ADDA_CLK1 0x73
84 #define RT3261_ADDA_CLK2 0x74
85 #define RT3261_DMIC 0x75
86 /* Function - Analog */
87 #define RT3261_GLB_CLK 0x80
88 #define RT3261_PLL_CTRL1 0x81
89 #define RT3261_PLL_CTRL2 0x82
90 #define RT3261_ASRC_1 0x83
91 #define RT3261_ASRC_2 0x84
92 #define RT3261_ASRC_3 0x85
93 #define RT3261_ASRC_4 0x89
94 #define RT3261_ASRC_5 0x8a
95 #define RT3261_HP_OVCD 0x8b
96 #define RT3261_CLS_D_OVCD 0x8c
97 #define RT3261_CLS_D_OUT 0x8d
98 #define RT3261_DEPOP_M1 0x8e
99 #define RT3261_DEPOP_M2 0x8f
100 #define RT3261_DEPOP_M3 0x90
101 #define RT3261_CHARGE_PUMP 0x91
102 #define RT3261_PV_DET_SPK_G 0x92
103 #define RT3261_MICBIAS 0x93
104 /* Function - Digital */
105 #define RT3261_EQ_CTRL1 0xb0
106 #define RT3261_EQ_CTRL2 0xb1
107 #define RT3261_WIND_FILTER 0xb2
108 #define RT3261_DRC_AGC_1 0xb4
109 #define RT3261_DRC_AGC_2 0xb5
110 #define RT3261_DRC_AGC_3 0xb6
111 #define RT3261_SVOL_ZC 0xb7
112 #define RT3261_ANC_CTRL1 0xb8
113 #define RT3261_ANC_CTRL2 0xb9
114 #define RT3261_ANC_CTRL3 0xba
115 #define RT3261_JD_CTRL 0xbb
116 #define RT3261_ANC_JD 0xbc
117 #define RT3261_IRQ_CTRL1 0xbd
118 #define RT3261_IRQ_CTRL2 0xbe
119 #define RT3261_INT_IRQ_ST 0xbf
120 #define RT3261_GPIO_CTRL1 0xc0
121 #define RT3261_GPIO_CTRL2 0xc1
122 #define RT3261_GPIO_CTRL3 0xc2
123 #define RT3261_DSP_CTRL1 0xc4
124 #define RT3261_DSP_CTRL2 0xc5
125 #define RT3261_DSP_CTRL3 0xc6
126 #define RT3261_DSP_CTRL4 0xc7
127 #define RT3261_PGM_REG_ARR1 0xc8
128 #define RT3261_PGM_REG_ARR2 0xc9
129 #define RT3261_PGM_REG_ARR3 0xca
130 #define RT3261_PGM_REG_ARR4 0xcb
131 #define RT3261_PGM_REG_ARR5 0xcc
132 #define RT3261_SCB_FUNC 0xcd
133 #define RT3261_SCB_CTRL 0xce
134 #define RT3261_BASE_BACK 0xcf
135 #define RT3261_MP3_PLUS1 0xd0
136 #define RT3261_MP3_PLUS2 0xd1
137 #define RT3261_3D_HP 0xd2
138 #define RT3261_ADJ_HPF 0xd3
139 #define RT3261_HP_CALIB_AMP_DET 0xd6
140 #define RT3261_HP_CALIB2 0xd7
141 #define RT3261_SV_ZCD1 0xd9
142 #define RT3261_SV_ZCD2 0xda
143 /* General Control */
144 #define RT3261_GEN_CTRL1 0xfa
145 #define RT3261_GEN_CTRL2 0xfb
146 #define RT3261_GEN_CTRL3 0xfc
149 /* Index of Codec Private Register definition */
150 #define RT3261_BIAS_CUR1 0x12
151 #define RT3261_BIAS_CUR3 0x14
152 #define RT3261_CLSD_INT_REG1 0x1c
153 #define RT3261_CHPUMP_INT_REG1 0x24 //bard 11-6
154 #define RT3261_MAMP_INT_REG2 0x37
155 #define RT3261_CHOP_DAC_ADC 0x3d
156 #define RT3261_MIXER_INT_REG 0x3f
157 #define RT3261_3D_SPK 0x63
158 #define RT3261_WND_1 0x6c
159 #define RT3261_WND_2 0x6d
160 #define RT3261_WND_3 0x6e
161 #define RT3261_WND_4 0x6f
162 #define RT3261_WND_5 0x70
163 #define RT3261_WND_8 0x73
164 #define RT3261_DIP_SPK_INF 0x75
165 #define RT3261_HP_DCC_INT1 0x77
166 #define RT3261_EQ_BW_LOP 0xa0
167 #define RT3261_EQ_GN_LOP 0xa1
168 #define RT3261_EQ_FC_BP1 0xa2
169 #define RT3261_EQ_BW_BP1 0xa3
170 #define RT3261_EQ_GN_BP1 0xa4
171 #define RT3261_EQ_FC_BP2 0xa5
172 #define RT3261_EQ_BW_BP2 0xa6
173 #define RT3261_EQ_GN_BP2 0xa7
174 #define RT3261_EQ_FC_BP3 0xa8
175 #define RT3261_EQ_BW_BP3 0xa9
176 #define RT3261_EQ_GN_BP3 0xaa
177 #define RT3261_EQ_FC_BP4 0xab
178 #define RT3261_EQ_BW_BP4 0xac
179 #define RT3261_EQ_GN_BP4 0xad
180 #define RT3261_EQ_FC_HIP1 0xae
181 #define RT3261_EQ_GN_HIP1 0xaf
182 #define RT3261_EQ_FC_HIP2 0xb0
183 #define RT3261_EQ_BW_HIP2 0xb1
184 #define RT3261_EQ_GN_HIP2 0xb2
185 #define RT3261_EQ_PRE_VOL 0xb3
186 #define RT3261_EQ_PST_VOL 0xb4
189 /* global definition */
190 #define RT3261_L_MUTE (0x1 << 15)
191 #define RT3261_L_MUTE_SFT 15
192 #define RT3261_VOL_L_MUTE (0x1 << 14)
193 #define RT3261_VOL_L_SFT 14
194 #define RT3261_R_MUTE (0x1 << 7)
195 #define RT3261_R_MUTE_SFT 7
196 #define RT3261_VOL_R_MUTE (0x1 << 6)
197 #define RT3261_VOL_R_SFT 6
198 #define RT3261_L_VOL_MASK (0x3f << 8)
199 #define RT3261_L_VOL_SFT 8
200 #define RT3261_R_VOL_MASK (0x3f)
201 #define RT3261_R_VOL_SFT 0
203 /* IN1 and IN2 Control (0x0d) */
204 /* IN3 and IN4 Control (0x0e) */
205 #define RT3261_BST_MASK1 (0xf<<12)
206 #define RT3261_BST_SFT1 12
207 #define RT3261_BST_MASK2 (0xf<<8)
208 #define RT3261_BST_SFT2 8
209 #define RT3261_IN_DF1 (0x1 << 7)
210 #define RT3261_IN_SFT1 7
211 #define RT3261_IN_DF2 (0x1 << 6)
212 #define RT3261_IN_SFT2 6
214 /* INL and INR Volume Control (0x0f) */
215 #define RT3261_INL_SEL_MASK (0x1 << 15)
216 #define RT3261_INL_SEL_SFT 15
217 #define RT3261_INL_SEL_IN4P (0x0 << 15)
218 #define RT3261_INL_SEL_MONOP (0x1 << 15)
219 #define RT3261_INL_VOL_MASK (0x1f << 8)
220 #define RT3261_INL_VOL_SFT 8
221 #define RT3261_INR_SEL_MASK (0x1 << 7)
222 #define RT3261_INR_SEL_SFT 7
223 #define RT3261_INR_SEL_IN4N (0x0 << 7)
224 #define RT3261_INR_SEL_MONON (0x1 << 7)
225 #define RT3261_INR_VOL_MASK (0x1f)
226 #define RT3261_INR_VOL_SFT 0
228 /* DAC1 Digital Volume (0x19) */
229 #define RT3261_DAC_L1_VOL_MASK (0xff << 8)
230 #define RT3261_DAC_L1_VOL_SFT 8
231 #define RT3261_DAC_R1_VOL_MASK (0xff)
232 #define RT3261_DAC_R1_VOL_SFT 0
234 /* DAC2 Digital Volume (0x1a) */
235 #define RT3261_DAC_L2_VOL_MASK (0xff << 8)
236 #define RT3261_DAC_L2_VOL_SFT 8
237 #define RT3261_DAC_R2_VOL_MASK (0xff)
238 #define RT3261_DAC_R2_VOL_SFT 0
240 /* DAC2 Control (0x1b) */
241 #define RT3261_M_DAC_L2_VOL (0x1 << 13)
242 #define RT3261_M_DAC_L2_VOL_SFT 13
243 #define RT3261_M_DAC_R2_VOL (0x1 << 12)
244 #define RT3261_M_DAC_R2_VOL_SFT 12
246 /* ADC Digital Volume Control (0x1c) */
247 #define RT3261_ADC_L_VOL_MASK (0x7f << 8)
248 #define RT3261_ADC_L_VOL_SFT 8
249 #define RT3261_ADC_R_VOL_MASK (0x7f)
250 #define RT3261_ADC_R_VOL_SFT 0
252 /* Mono ADC Digital Volume Control (0x1d) */
253 #define RT3261_MONO_ADC_L_VOL_MASK (0x7f << 8)
254 #define RT3261_MONO_ADC_L_VOL_SFT 8
255 #define RT3261_MONO_ADC_R_VOL_MASK (0x7f)
256 #define RT3261_MONO_ADC_R_VOL_SFT 0
258 /* ADC Boost Volume Control (0x1e) */
259 #define RT3261_ADC_L_BST_MASK (0x3 << 14)
260 #define RT3261_ADC_L_BST_SFT 14
261 #define RT3261_ADC_R_BST_MASK (0x3 << 12)
262 #define RT3261_ADC_R_BST_SFT 12
263 #define RT3261_ADC_COMP_MASK (0x3 << 10)
264 #define RT3261_ADC_COMP_SFT 10
266 /* Stereo ADC Mixer Control (0x27) */
267 #define RT3261_M_ADC_L1 (0x1 << 14)
268 #define RT3261_M_ADC_L1_SFT 14
269 #define RT3261_M_ADC_L2 (0x1 << 13)
270 #define RT3261_M_ADC_L2_SFT 13
271 #define RT3261_ADC_1_SRC_MASK (0x1 << 12)
272 #define RT3261_ADC_1_SRC_SFT 12
273 #define RT3261_ADC_1_SRC_ADC (0x1 << 12)
274 #define RT3261_ADC_1_SRC_DACMIX (0x0 << 12)
275 #define RT3261_ADC_2_SRC_MASK (0x3 << 10)
276 #define RT3261_ADC_2_SRC_SFT 10
277 #define RT3261_ADC_2_SRC_DMIC1 (0x0 << 10)
278 #define RT3261_ADC_2_SRC_DMIC2 (0x1 << 10)
279 #define RT3261_ADC_2_SRC_DACMIX (0x2 << 10)
280 #define RT3261_M_ADC_R1 (0x1 << 6)
281 #define RT3261_M_ADC_R1_SFT 6
282 #define RT3261_M_ADC_R2 (0x1 << 5)
283 #define RT3261_M_ADC_R2_SFT 5
285 /* Mono ADC Mixer Control (0x28) */
286 #define RT3261_M_MONO_ADC_L1 (0x1 << 14)
287 #define RT3261_M_MONO_ADC_L1_SFT 14
288 #define RT3261_M_MONO_ADC_L2 (0x1 << 13)
289 #define RT3261_M_MONO_ADC_L2_SFT 13
290 #define RT3261_MONO_ADC_L1_SRC_MASK (0x1 << 12)
291 #define RT3261_MONO_ADC_L1_SRC_SFT 12
292 #define RT3261_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
293 #define RT3261_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
294 #define RT3261_MONO_ADC_L2_SRC_MASK (0x3 << 10)
295 #define RT3261_MONO_ADC_L2_SRC_SFT 10
296 #define RT3261_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
297 #define RT3261_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
298 #define RT3261_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
299 #define RT3261_M_MONO_ADC_R1 (0x1 << 6)
300 #define RT3261_M_MONO_ADC_R1_SFT 6
301 #define RT3261_M_MONO_ADC_R2 (0x1 << 5)
302 #define RT3261_M_MONO_ADC_R2_SFT 5
303 #define RT3261_MONO_ADC_R1_SRC_MASK (0x1 << 4)
304 #define RT3261_MONO_ADC_R1_SRC_SFT 4
305 #define RT3261_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
306 #define RT3261_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
307 #define RT3261_MONO_ADC_R2_SRC_MASK (0x3 << 2)
308 #define RT3261_MONO_ADC_R2_SRC_SFT 2
309 #define RT3261_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2)
310 #define RT3261_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
311 #define RT3261_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2)
313 /* ADC Mixer to DAC Mixer Control (0x29) */
314 #define RT3261_M_ADCMIX_L (0x1 << 15)
315 #define RT3261_M_ADCMIX_L_SFT 15
316 #define RT3261_M_IF1_DAC_L (0x1 << 14)
317 #define RT3261_M_IF1_DAC_L_SFT 14
318 #define RT3261_M_ADCMIX_R (0x1 << 7)
319 #define RT3261_M_ADCMIX_R_SFT 7
320 #define RT3261_M_IF1_DAC_R (0x1 << 6)
321 #define RT3261_M_IF1_DAC_R_SFT 6
323 /* Stereo DAC Mixer Control (0x2a) */
324 #define RT3261_M_DAC_L1 (0x1 << 14)
325 #define RT3261_M_DAC_L1_SFT 14
326 #define RT3261_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
327 #define RT3261_DAC_L1_STO_L_VOL_SFT 13
328 #define RT3261_M_DAC_L2 (0x1 << 12)
329 #define RT3261_M_DAC_L2_SFT 12
330 #define RT3261_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
331 #define RT3261_DAC_L2_STO_L_VOL_SFT 11
332 #define RT3261_M_ANC_DAC_L (0x1 << 10)
333 #define RT3261_M_ANC_DAC_L_SFT 10
334 #define RT3261_M_DAC_R1 (0x1 << 6)
335 #define RT3261_M_DAC_R1_SFT 6
336 #define RT3261_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
337 #define RT3261_DAC_R1_STO_R_VOL_SFT 5
338 #define RT3261_M_DAC_R2 (0x1 << 4)
339 #define RT3261_M_DAC_R2_SFT 4
340 #define RT3261_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
341 #define RT3261_DAC_R2_STO_R_VOL_SFT 3
342 #define RT3261_M_ANC_DAC_R (0x1 << 2)
343 #define RT3261_M_ANC_DAC_R_SFT 2
345 /* Mono DAC Mixer Control (0x2b) */
346 #define RT3261_M_DAC_L1_MONO_L (0x1 << 14)
347 #define RT3261_M_DAC_L1_MONO_L_SFT 14
348 #define RT3261_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
349 #define RT3261_DAC_L1_MONO_L_VOL_SFT 13
350 #define RT3261_M_DAC_L2_MONO_L (0x1 << 12)
351 #define RT3261_M_DAC_L2_MONO_L_SFT 12
352 #define RT3261_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
353 #define RT3261_DAC_L2_MONO_L_VOL_SFT 11
354 #define RT3261_M_DAC_R2_MONO_L (0x1 << 10)
355 #define RT3261_M_DAC_R2_MONO_L_SFT 10
356 #define RT3261_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
357 #define RT3261_DAC_R2_MONO_L_VOL_SFT 9
358 #define RT3261_M_DAC_R1_MONO_R (0x1 << 6)
359 #define RT3261_M_DAC_R1_MONO_R_SFT 6
360 #define RT3261_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
361 #define RT3261_DAC_R1_MONO_R_VOL_SFT 5
362 #define RT3261_M_DAC_R2_MONO_R (0x1 << 4)
363 #define RT3261_M_DAC_R2_MONO_R_SFT 4
364 #define RT3261_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
365 #define RT3261_DAC_R2_MONO_R_VOL_SFT 3
366 #define RT3261_M_DAC_L2_MONO_R (0x1 << 2)
367 #define RT3261_M_DAC_L2_MONO_R_SFT 2
368 #define RT3261_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
369 #define RT3261_DAC_L2_MONO_R_VOL_SFT 1
371 /* Digital Mixer Control (0x2c) */
372 #define RT3261_M_STO_L_DAC_L (0x1 << 15)
373 #define RT3261_M_STO_L_DAC_L_SFT 15
374 #define RT3261_STO_L_DAC_L_VOL_MASK (0x1 << 14)
375 #define RT3261_STO_L_DAC_L_VOL_SFT 14
376 #define RT3261_M_DAC_L2_DAC_L (0x1 << 13)
377 #define RT3261_M_DAC_L2_DAC_L_SFT 13
378 #define RT3261_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
379 #define RT3261_DAC_L2_DAC_L_VOL_SFT 12
380 #define RT3261_M_STO_R_DAC_R (0x1 << 11)
381 #define RT3261_M_STO_R_DAC_R_SFT 11
382 #define RT3261_STO_R_DAC_R_VOL_MASK (0x1 << 10)
383 #define RT3261_STO_R_DAC_R_VOL_SFT 10
384 #define RT3261_M_DAC_R2_DAC_R (0x1 << 9)
385 #define RT3261_M_DAC_R2_DAC_R_SFT 9
386 #define RT3261_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
387 #define RT3261_DAC_R2_DAC_R_VOL_SFT 8
389 /* DSP Path Control 1 (0x2d) */
390 #define RT3261_RXDP_SRC_MASK (0x1 << 15)
391 #define RT3261_RXDP_SRC_SFT 15
392 #define RT3261_RXDP_SRC_NOR (0x0 << 15)
393 #define RT3261_RXDP_SRC_DIV3 (0x1 << 15)
394 #define RT3261_TXDP_SRC_MASK (0x1 << 14)
395 #define RT3261_TXDP_SRC_SFT 14
396 #define RT3261_TXDP_SRC_NOR (0x0 << 14)
397 #define RT3261_TXDP_SRC_DIV3 (0x1 << 14)
399 /* DSP Path Control 2 (0x2e) */
400 #define RT3261_DAC_L2_SEL_MASK (0x3 << 14)
401 #define RT3261_DAC_L2_SEL_SFT 14
402 #define RT3261_DAC_L2_SEL_IF2 (0x0 << 14)
403 #define RT3261_DAC_L2_SEL_IF3 (0x1 << 14)
404 #define RT3261_DAC_L2_SEL_TXDC (0x2 << 14)
405 #define RT3261_DAC_L2_SEL_BASS (0x3 << 14)
406 #define RT3261_DAC_R2_SEL_MASK (0x3 << 12)
407 #define RT3261_DAC_R2_SEL_SFT 12
408 #define RT3261_DAC_R2_SEL_IF2 (0x0 << 12)
409 #define RT3261_DAC_R2_SEL_IF3 (0x1 << 12)
410 #define RT3261_DAC_R2_SEL_TXDC (0x2 << 12)
411 #define RT3261_IF2_ADC_L_SEL_MASK (0x1 << 11)
412 #define RT3261_IF2_ADC_L_SEL_SFT 11
413 #define RT3261_IF2_ADC_L_SEL_TXDP (0x0 << 11)
414 #define RT3261_IF2_ADC_L_SEL_PASS (0x1 << 11)
415 #define RT3261_IF2_ADC_R_SEL_MASK (0x1 << 10)
416 #define RT3261_IF2_ADC_R_SEL_SFT 10
417 #define RT3261_IF2_ADC_R_SEL_TXDP (0x0 << 10)
418 #define RT3261_IF2_ADC_R_SEL_PASS (0x1 << 10)
419 #define RT3261_RXDC_SEL_MASK (0x3 << 8)
420 #define RT3261_RXDC_SEL_SFT 8
421 #define RT3261_RXDC_SEL_NOR (0x0 << 8)
422 #define RT3261_RXDC_SEL_L2R (0x1 << 8)
423 #define RT3261_RXDC_SEL_R2L (0x2 << 8)
424 #define RT3261_RXDC_SEL_SWAP (0x3 << 8)
425 #define RT3261_RXDP_SEL_MASK (0x3 << 6)
426 #define RT3261_RXDP_SEL_SFT 6
427 #define RT3261_RXDP_SEL_NOR (0x0 << 6)
428 #define RT3261_RXDP_SEL_L2R (0x1 << 6)
429 #define RT3261_RXDP_SEL_R2L (0x2 << 6)
430 #define RT3261_RXDP_SEL_SWAP (0x3 << 6)
431 #define RT3261_TXDC_SEL_MASK (0x3 << 4)
432 #define RT3261_TXDC_SEL_SFT 4
433 #define RT3261_TXDC_SEL_NOR (0x0 << 4)
434 #define RT3261_TXDC_SEL_L2R (0x1 << 4)
435 #define RT3261_TXDC_SEL_R2L (0x2 << 4)
436 #define RT3261_TXDC_SEL_SWAP (0x3 << 4)
437 #define RT3261_TXDP_SEL_MASK (0x3 << 2)
438 #define RT3261_TXDP_SEL_SFT 2
439 #define RT3261_TXDP_SEL_NOR (0x0 << 2)
440 #define RT3261_TXDP_SEL_L2R (0x1 << 2)
441 #define RT3261_TXDP_SEL_R2L (0x2 << 2)
442 #define RT3261_TRXDP_SEL_SWAP (0x3 << 2)
444 /* Digital Interface Data Control (0x2f) */
445 #define RT3261_IF1_DAC_SEL_MASK (0x3 << 14)
446 #define RT3261_IF1_DAC_SEL_SFT 14
447 #define RT3261_IF1_DAC_SEL_NOR (0x0 << 14)
448 #define RT3261_IF1_DAC_SEL_L2R (0x1 << 14)
449 #define RT3261_IF1_DAC_SEL_R2L (0x2 << 14)
450 #define RT3261_IF1_DAC_SEL_SWAP (0x3 << 14)
451 #define RT3261_IF1_ADC_SEL_MASK (0x3 << 12)
452 #define RT3261_IF1_ADC_SEL_SFT 12
453 #define RT3261_IF1_ADC_SEL_NOR (0x0 << 12)
454 #define RT3261_IF1_ADC_SEL_L2R (0x1 << 12)
455 #define RT3261_IF1_ADC_SEL_R2L (0x2 << 12)
456 #define RT3261_IF1_ADC_SEL_SWAP (0x3 << 12)
457 #define RT3261_IF2_DAC_SEL_MASK (0x3 << 10)
458 #define RT3261_IF2_DAC_SEL_SFT 10
459 #define RT3261_IF2_DAC_SEL_NOR (0x0 << 10)
460 #define RT3261_IF2_DAC_SEL_L2R (0x1 << 10)
461 #define RT3261_IF2_DAC_SEL_R2L (0x2 << 10)
462 #define RT3261_IF2_DAC_SEL_SWAP (0x3 << 10)
463 #define RT3261_IF2_ADC_SEL_MASK (0x3 << 8)
464 #define RT3261_IF2_ADC_SEL_SFT 8
465 #define RT3261_IF2_ADC_SEL_NOR (0x0 << 8)
466 #define RT3261_IF2_ADC_SEL_L2R (0x1 << 8)
467 #define RT3261_IF2_ADC_SEL_R2L (0x2 << 8)
468 #define RT3261_IF2_ADC_SEL_SWAP (0x3 << 8)
469 #define RT3261_IF3_DAC_SEL_MASK (0x3 << 6)
470 #define RT3261_IF3_DAC_SEL_SFT 6
471 #define RT3261_IF3_DAC_SEL_NOR (0x0 << 6)
472 #define RT3261_IF3_DAC_SEL_L2R (0x1 << 6)
473 #define RT3261_IF3_DAC_SEL_R2L (0x2 << 6)
474 #define RT3261_IF3_DAC_SEL_SWAP (0x3 << 6)
475 #define RT3261_IF3_ADC_SEL_MASK (0x3 << 4)
476 #define RT3261_IF3_ADC_SEL_SFT 4
477 #define RT3261_IF3_ADC_SEL_NOR (0x0 << 4)
478 #define RT3261_IF3_ADC_SEL_L2R (0x1 << 4)
479 #define RT3261_IF3_ADC_SEL_R2L (0x2 << 4)
480 #define RT3261_IF3_ADC_SEL_SWAP (0x3 << 4)
482 /* REC Left Mixer Control 1 (0x3b) */
483 #define RT3261_G_HP_L_RM_L_MASK (0x7 << 13)
484 #define RT3261_G_HP_L_RM_L_SFT 13
485 #define RT3261_G_IN_L_RM_L_MASK (0x7 << 10)
486 #define RT3261_G_IN_L_RM_L_SFT 10
487 #define RT3261_G_BST4_RM_L_MASK (0x7 << 7)
488 #define RT3261_G_BST4_RM_L_SFT 7
489 #define RT3261_G_BST3_RM_L_MASK (0x7 << 4)
490 #define RT3261_G_BST3_RM_L_SFT 4
491 #define RT3261_G_BST2_RM_L_MASK (0x7 << 1)
492 #define RT3261_G_BST2_RM_L_SFT 1
494 /* REC Left Mixer Control 2 (0x3c) */
495 #define RT3261_G_BST1_RM_L_MASK (0x7 << 13)
496 #define RT3261_G_BST1_RM_L_SFT 13
497 #define RT3261_G_OM_L_RM_L_MASK (0x7 << 10)
498 #define RT3261_G_OM_L_RM_L_SFT 10
499 #define RT3261_M_HP_L_RM_L (0x1 << 6)
500 #define RT3261_M_HP_L_RM_L_SFT 6
501 #define RT3261_M_IN_L_RM_L (0x1 << 5)
502 #define RT3261_M_IN_L_RM_L_SFT 5
503 #define RT3261_M_BST4_RM_L (0x1 << 4)
504 #define RT3261_M_BST4_RM_L_SFT 4
505 #define RT3261_M_BST3_RM_L (0x1 << 3)
506 #define RT3261_M_BST3_RM_L_SFT 3
507 #define RT3261_M_BST2_RM_L (0x1 << 2)
508 #define RT3261_M_BST2_RM_L_SFT 2
509 #define RT3261_M_BST1_RM_L (0x1 << 1)
510 #define RT3261_M_BST1_RM_L_SFT 1
511 #define RT3261_M_OM_L_RM_L (0x1)
512 #define RT3261_M_OM_L_RM_L_SFT 0
514 /* REC Right Mixer Control 1 (0x3d) */
515 #define RT3261_G_HP_R_RM_R_MASK (0x7 << 13)
516 #define RT3261_G_HP_R_RM_R_SFT 13
517 #define RT3261_G_IN_R_RM_R_MASK (0x7 << 10)
518 #define RT3261_G_IN_R_RM_R_SFT 10
519 #define RT3261_G_BST4_RM_R_MASK (0x7 << 7)
520 #define RT3261_G_BST4_RM_R_SFT 7
521 #define RT3261_G_BST3_RM_R_MASK (0x7 << 4)
522 #define RT3261_G_BST3_RM_R_SFT 4
523 #define RT3261_G_BST2_RM_R_MASK (0x7 << 1)
524 #define RT3261_G_BST2_RM_R_SFT 1
526 /* REC Right Mixer Control 2 (0x3e) */
527 #define RT3261_G_BST1_RM_R_MASK (0x7 << 13)
528 #define RT3261_G_BST1_RM_R_SFT 13
529 #define RT3261_G_OM_R_RM_R_MASK (0x7 << 10)
530 #define RT3261_G_OM_R_RM_R_SFT 10
531 #define RT3261_M_HP_R_RM_R (0x1 << 6)
532 #define RT3261_M_HP_R_RM_R_SFT 6
533 #define RT3261_M_IN_R_RM_R (0x1 << 5)
534 #define RT3261_M_IN_R_RM_R_SFT 5
535 #define RT3261_M_BST4_RM_R (0x1 << 4)
536 #define RT3261_M_BST4_RM_R_SFT 4
537 #define RT3261_M_BST3_RM_R (0x1 << 3)
538 #define RT3261_M_BST3_RM_R_SFT 3
539 #define RT3261_M_BST2_RM_R (0x1 << 2)
540 #define RT3261_M_BST2_RM_R_SFT 2
541 #define RT3261_M_BST1_RM_R (0x1 << 1)
542 #define RT3261_M_BST1_RM_R_SFT 1
543 #define RT3261_M_OM_R_RM_R (0x1)
544 #define RT3261_M_OM_R_RM_R_SFT 0
546 /* HPMIX Control (0x45) */
547 #define RT3261_M_DAC2_HM (0x1 << 15)
548 #define RT3261_M_DAC2_HM_SFT 15
549 #define RT3261_M_DAC1_HM (0x1 << 14)
550 #define RT3261_M_DAC1_HM_SFT 14
551 #define RT3261_M_HPVOL_HM (0x1 << 13)
552 #define RT3261_M_HPVOL_HM_SFT 13
553 #define RT3261_G_HPOMIX_MASK (0x1 << 12)
554 #define RT3261_G_HPOMIX_SFT 12
556 /* SPK Left Mixer Control (0x46) */
557 #define RT3261_G_RM_L_SM_L_MASK (0x3 << 14)
558 #define RT3261_G_RM_L_SM_L_SFT 14
559 #define RT3261_G_IN_L_SM_L_MASK (0x3 << 12)
560 #define RT3261_G_IN_L_SM_L_SFT 12
561 #define RT3261_G_DAC_L1_SM_L_MASK (0x3 << 10)
562 #define RT3261_G_DAC_L1_SM_L_SFT 10
563 #define RT3261_G_DAC_L2_SM_L_MASK (0x3 << 8)
564 #define RT3261_G_DAC_L2_SM_L_SFT 8
565 #define RT3261_G_OM_L_SM_L_MASK (0x3 << 6)
566 #define RT3261_G_OM_L_SM_L_SFT 6
567 #define RT3261_M_RM_L_SM_L (0x1 << 5)
568 #define RT3261_M_RM_L_SM_L_SFT 5
569 #define RT3261_M_IN_L_SM_L (0x1 << 4)
570 #define RT3261_M_IN_L_SM_L_SFT 4
571 #define RT3261_M_DAC_L1_SM_L (0x1 << 3)
572 #define RT3261_M_DAC_L1_SM_L_SFT 3
573 #define RT3261_M_DAC_L2_SM_L (0x1 << 2)
574 #define RT3261_M_DAC_L2_SM_L_SFT 2
575 #define RT3261_M_OM_L_SM_L (0x1 << 1)
576 #define RT3261_M_OM_L_SM_L_SFT 1
578 /* SPK Right Mixer Control (0x47) */
579 #define RT3261_G_RM_R_SM_R_MASK (0x3 << 14)
580 #define RT3261_G_RM_R_SM_R_SFT 14
581 #define RT3261_G_IN_R_SM_R_MASK (0x3 << 12)
582 #define RT3261_G_IN_R_SM_R_SFT 12
583 #define RT3261_G_DAC_R1_SM_R_MASK (0x3 << 10)
584 #define RT3261_G_DAC_R1_SM_R_SFT 10
585 #define RT3261_G_DAC_R2_SM_R_MASK (0x3 << 8)
586 #define RT3261_G_DAC_R2_SM_R_SFT 8
587 #define RT3261_G_OM_R_SM_R_MASK (0x3 << 6)
588 #define RT3261_G_OM_R_SM_R_SFT 6
589 #define RT3261_M_RM_R_SM_R (0x1 << 5)
590 #define RT3261_M_RM_R_SM_R_SFT 5
591 #define RT3261_M_IN_R_SM_R (0x1 << 4)
592 #define RT3261_M_IN_R_SM_R_SFT 4
593 #define RT3261_M_DAC_R1_SM_R (0x1 << 3)
594 #define RT3261_M_DAC_R1_SM_R_SFT 3
595 #define RT3261_M_DAC_R2_SM_R (0x1 << 2)
596 #define RT3261_M_DAC_R2_SM_R_SFT 2
597 #define RT3261_M_OM_R_SM_R (0x1 << 1)
598 #define RT3261_M_OM_R_SM_R_SFT 1
600 /* SPOLMIX Control (0x48) */
601 #define RT3261_M_DAC_R1_SPM_L (0x1 << 15)
602 #define RT3261_M_DAC_R1_SPM_L_SFT 15
603 #define RT3261_M_DAC_L1_SPM_L (0x1 << 14)
604 #define RT3261_M_DAC_L1_SPM_L_SFT 14
605 #define RT3261_M_SV_R_SPM_L (0x1 << 13)
606 #define RT3261_M_SV_R_SPM_L_SFT 13
607 #define RT3261_M_SV_L_SPM_L (0x1 << 12)
608 #define RT3261_M_SV_L_SPM_L_SFT 12
609 #define RT3261_M_BST1_SPM_L (0x1 << 11)
610 #define RT3261_M_BST1_SPM_L_SFT 11
612 /* SPORMIX Control (0x49) */
613 #define RT3261_M_DAC_R1_SPM_R (0x1 << 13)
614 #define RT3261_M_DAC_R1_SPM_R_SFT 13
615 #define RT3261_M_SV_R_SPM_R (0x1 << 12)
616 #define RT3261_M_SV_R_SPM_R_SFT 12
617 #define RT3261_M_BST1_SPM_R (0x1 << 11)
618 #define RT3261_M_BST1_SPM_R_SFT 11
620 /* SPOLMIX / SPORMIX Ratio Control (0x4a) */
621 #define RT3261_SPO_CLSD_RATIO_MASK (0x7)
622 #define RT3261_SPO_CLSD_RATIO_SFT 0
624 /* Mono Output Mixer Control (0x4c) */
625 #define RT3261_M_DAC_R2_MM (0x1 << 15)
626 #define RT3261_M_DAC_R2_MM_SFT 15
627 #define RT3261_M_DAC_L2_MM (0x1 << 14)
628 #define RT3261_M_DAC_L2_MM_SFT 14
629 #define RT3261_M_OV_R_MM (0x1 << 13)
630 #define RT3261_M_OV_R_MM_SFT 13
631 #define RT3261_M_OV_L_MM (0x1 << 12)
632 #define RT3261_M_OV_L_MM_SFT 12
633 #define RT3261_M_BST1_MM (0x1 << 11)
634 #define RT3261_M_BST1_MM_SFT 11
635 #define RT3261_G_MONOMIX_MASK (0x1 << 10)
636 #define RT3261_G_MONOMIX_SFT 10
638 /* Output Left Mixer Control 1 (0x4d) */
639 #define RT3261_G_BST3_OM_L_MASK (0x7 << 13)
640 #define RT3261_G_BST3_OM_L_SFT 13
641 #define RT3261_G_BST2_OM_L_MASK (0x7 << 10)
642 #define RT3261_G_BST2_OM_L_SFT 10
643 #define RT3261_G_BST1_OM_L_MASK (0x7 << 7)
644 #define RT3261_G_BST1_OM_L_SFT 7
645 #define RT3261_G_IN_L_OM_L_MASK (0x7 << 4)
646 #define RT3261_G_IN_L_OM_L_SFT 4
647 #define RT3261_G_RM_L_OM_L_MASK (0x7 << 1)
648 #define RT3261_G_RM_L_OM_L_SFT 1
650 /* Output Left Mixer Control 2 (0x4e) */
651 #define RT3261_G_DAC_R2_OM_L_MASK (0x7 << 13)
652 #define RT3261_G_DAC_R2_OM_L_SFT 13
653 #define RT3261_G_DAC_L2_OM_L_MASK (0x7 << 10)
654 #define RT3261_G_DAC_L2_OM_L_SFT 10
655 #define RT3261_G_DAC_L1_OM_L_MASK (0x7 << 7)
656 #define RT3261_G_DAC_L1_OM_L_SFT 7
658 /* Output Left Mixer Control 3 (0x4f) */
659 #define RT3261_M_SM_L_OM_L (0x1 << 8)
660 #define RT3261_M_SM_L_OM_L_SFT 8
661 #define RT3261_M_BST3_OM_L (0x1 << 7)
662 #define RT3261_M_BST3_OM_L_SFT 7
663 #define RT3261_M_BST2_OM_L (0x1 << 6)
664 #define RT3261_M_BST2_OM_L_SFT 6
665 #define RT3261_M_BST1_OM_L (0x1 << 5)
666 #define RT3261_M_BST1_OM_L_SFT 5
667 #define RT3261_M_IN_L_OM_L (0x1 << 4)
668 #define RT3261_M_IN_L_OM_L_SFT 4
669 #define RT3261_M_RM_L_OM_L (0x1 << 3)
670 #define RT3261_M_RM_L_OM_L_SFT 3
671 #define RT3261_M_DAC_R2_OM_L (0x1 << 2)
672 #define RT3261_M_DAC_R2_OM_L_SFT 2
673 #define RT3261_M_DAC_L2_OM_L (0x1 << 1)
674 #define RT3261_M_DAC_L2_OM_L_SFT 1
675 #define RT3261_M_DAC_L1_OM_L (0x1)
676 #define RT3261_M_DAC_L1_OM_L_SFT 0
678 /* Output Right Mixer Control 1 (0x50) */
679 #define RT3261_G_BST4_OM_R_MASK (0x7 << 13)
680 #define RT3261_G_BST4_OM_R_SFT 13
681 #define RT3261_G_BST2_OM_R_MASK (0x7 << 10)
682 #define RT3261_G_BST2_OM_R_SFT 10
683 #define RT3261_G_BST1_OM_R_MASK (0x7 << 7)
684 #define RT3261_G_BST1_OM_R_SFT 7
685 #define RT3261_G_IN_R_OM_R_MASK (0x7 << 4)
686 #define RT3261_G_IN_R_OM_R_SFT 4
687 #define RT3261_G_RM_R_OM_R_MASK (0x7 << 1)
688 #define RT3261_G_RM_R_OM_R_SFT 1
690 /* Output Right Mixer Control 2 (0x51) */
691 #define RT3261_G_DAC_L2_OM_R_MASK (0x7 << 13)
692 #define RT3261_G_DAC_L2_OM_R_SFT 13
693 #define RT3261_G_DAC_R2_OM_R_MASK (0x7 << 10)
694 #define RT3261_G_DAC_R2_OM_R_SFT 10
695 #define RT3261_G_DAC_R1_OM_R_MASK (0x7 << 7)
696 #define RT3261_G_DAC_R1_OM_R_SFT 7
698 /* Output Right Mixer Control 3 (0x52) */
699 #define RT3261_M_SM_L_OM_R (0x1 << 8)
700 #define RT3261_M_SM_L_OM_R_SFT 8
701 #define RT3261_M_BST4_OM_R (0x1 << 7)
702 #define RT3261_M_BST4_OM_R_SFT 7
703 #define RT3261_M_BST2_OM_R (0x1 << 6)
704 #define RT3261_M_BST2_OM_R_SFT 6
705 #define RT3261_M_BST1_OM_R (0x1 << 5)
706 #define RT3261_M_BST1_OM_R_SFT 5
707 #define RT3261_M_IN_R_OM_R (0x1 << 4)
708 #define RT3261_M_IN_R_OM_R_SFT 4
709 #define RT3261_M_RM_R_OM_R (0x1 << 3)
710 #define RT3261_M_RM_R_OM_R_SFT 3
711 #define RT3261_M_DAC_L2_OM_R (0x1 << 2)
712 #define RT3261_M_DAC_L2_OM_R_SFT 2
713 #define RT3261_M_DAC_R2_OM_R (0x1 << 1)
714 #define RT3261_M_DAC_R2_OM_R_SFT 1
715 #define RT3261_M_DAC_R1_OM_R (0x1)
716 #define RT3261_M_DAC_R1_OM_R_SFT 0
718 /* LOUT Mixer Control (0x53) */
719 #define RT3261_M_DAC_L1_LM (0x1 << 15)
720 #define RT3261_M_DAC_L1_LM_SFT 15
721 #define RT3261_M_DAC_R1_LM (0x1 << 14)
722 #define RT3261_M_DAC_R1_LM_SFT 14
723 #define RT3261_M_OV_L_LM (0x1 << 13)
724 #define RT3261_M_OV_L_LM_SFT 13
725 #define RT3261_M_OV_R_LM (0x1 << 12)
726 #define RT3261_M_OV_R_LM_SFT 12
727 #define RT3261_G_LOUTMIX_MASK (0x1 << 11)
728 #define RT3261_G_LOUTMIX_SFT 11
730 /* Power Management for Digital 1 (0x61) */
731 #define RT3261_PWR_I2S1 (0x1 << 15)
732 #define RT3261_PWR_I2S1_BIT 15
733 #define RT3261_PWR_I2S2 (0x1 << 14)
734 #define RT3261_PWR_I2S2_BIT 14
735 #define RT3261_PWR_I2S3 (0x1 << 13)
736 #define RT3261_PWR_I2S3_BIT 13
737 #define RT3261_PWR_DAC_L1 (0x1 << 12)
738 #define RT3261_PWR_DAC_L1_BIT 12
739 #define RT3261_PWR_DAC_R1 (0x1 << 11)
740 #define RT3261_PWR_DAC_R1_BIT 11
741 #define RT3261_PWR_DAC_L2 (0x1 << 7)
742 #define RT3261_PWR_DAC_L2_BIT 7
743 #define RT3261_PWR_DAC_R2 (0x1 << 6)
744 #define RT3261_PWR_DAC_R2_BIT 6
745 #define RT3261_PWR_ADC_L (0x1 << 2)
746 #define RT3261_PWR_ADC_L_BIT 2
747 #define RT3261_PWR_ADC_R (0x1 << 1)
748 #define RT3261_PWR_ADC_R_BIT 1
749 #define RT3261_PWR_CLS_D (0x1)
750 #define RT3261_PWR_CLS_D_BIT 0
752 /* Power Management for Digital 2 (0x62) */
753 #define RT3261_PWR_ADC_SF (0x1 << 15)
754 #define RT3261_PWR_ADC_SF_BIT 15
755 #define RT3261_PWR_ADC_MF_L (0x1 << 14)
756 #define RT3261_PWR_ADC_MF_L_BIT 14
757 #define RT3261_PWR_ADC_MF_R (0x1 << 13)
758 #define RT3261_PWR_ADC_MF_R_BIT 13
759 #define RT3261_PWR_I2S_DSP (0x1 << 12)
760 #define RT3261_PWR_I2S_DSP_BIT 12
762 /* Power Management for Analog 1 (0x63) */
763 #define RT3261_PWR_VREF1 (0x1 << 15)
764 #define RT3261_PWR_VREF1_BIT 15
765 #define RT3261_PWR_FV1 (0x1 << 14)
766 #define RT3261_PWR_FV1_BIT 14
767 #define RT3261_PWR_MB (0x1 << 13)
768 #define RT3261_PWR_MB_BIT 13
769 #define RT3261_PWR_LM (0x1 << 12)
770 #define RT3261_PWR_LM_BIT 12
771 #define RT3261_PWR_BG (0x1 << 11)
772 #define RT3261_PWR_BG_BIT 11
773 #define RT3261_PWR_MM (0x1 << 10)
774 #define RT3261_PWR_MM_BIT 10
775 #define RT3261_PWR_MA (0x1 << 8)
776 #define RT3261_PWR_MA_BIT 8
777 #define RT3261_PWR_HP_L (0x1 << 7)
778 #define RT3261_PWR_HP_L_BIT 7
779 #define RT3261_PWR_HP_R (0x1 << 6)
780 #define RT3261_PWR_HP_R_BIT 6
781 #define RT3261_PWR_HA (0x1 << 5)
782 #define RT3261_PWR_HA_BIT 5
783 #define RT3261_PWR_VREF2 (0x1 << 4)
784 #define RT3261_PWR_VREF2_BIT 4
785 #define RT3261_PWR_FV2 (0x1 << 3)
786 #define RT3261_PWR_FV2_BIT 3
787 #define RT3261_PWR_LDO2 (0x1 << 2)
788 #define RT3261_PWR_LDO2_BIT 2
790 /* Power Management for Analog 2 (0x64) */
791 #define RT3261_PWR_BST1 (0x1 << 15)
792 #define RT3261_PWR_BST1_BIT 15
793 #define RT3261_PWR_BST2 (0x1 << 14)
794 #define RT3261_PWR_BST2_BIT 14
795 #define RT3261_PWR_BST3 (0x1 << 13)
796 #define RT3261_PWR_BST3_BIT 13
797 #define RT3261_PWR_BST4 (0x1 << 12)
798 #define RT3261_PWR_BST4_BIT 12
799 #define RT3261_PWR_MB1 (0x1 << 11)
800 #define RT3261_PWR_MB1_BIT 11
801 #define RT3261_PWR_MB2 (0x1 << 10)
802 #define RT3261_PWR_MB2_BIT 10
803 #define RT3261_PWR_PLL (0x1 << 9)
804 #define RT3261_PWR_PLL_BIT 9
806 /* Power Management for Mixer (0x65) */
807 #define RT3261_PWR_OM_L (0x1 << 15)
808 #define RT3261_PWR_OM_L_BIT 15
809 #define RT3261_PWR_OM_R (0x1 << 14)
810 #define RT3261_PWR_OM_R_BIT 14
811 #define RT3261_PWR_SM_L (0x1 << 13)
812 #define RT3261_PWR_SM_L_BIT 13
813 #define RT3261_PWR_SM_R (0x1 << 12)
814 #define RT3261_PWR_SM_R_BIT 12
815 #define RT3261_PWR_RM_L (0x1 << 11)
816 #define RT3261_PWR_RM_L_BIT 11
817 #define RT3261_PWR_RM_R (0x1 << 10)
818 #define RT3261_PWR_RM_R_BIT 10
820 /* Power Management for Volume (0x66) */
821 #define RT3261_PWR_SV_L (0x1 << 15)
822 #define RT3261_PWR_SV_L_BIT 15
823 #define RT3261_PWR_SV_R (0x1 << 14)
824 #define RT3261_PWR_SV_R_BIT 14
825 #define RT3261_PWR_OV_L (0x1 << 13)
826 #define RT3261_PWR_OV_L_BIT 13
827 #define RT3261_PWR_OV_R (0x1 << 12)
828 #define RT3261_PWR_OV_R_BIT 12
829 #define RT3261_PWR_HV_L (0x1 << 11)
830 #define RT3261_PWR_HV_L_BIT 11
831 #define RT3261_PWR_HV_R (0x1 << 10)
832 #define RT3261_PWR_HV_R_BIT 10
833 #define RT3261_PWR_IN_L (0x1 << 9)
834 #define RT3261_PWR_IN_L_BIT 9
835 #define RT3261_PWR_IN_R (0x1 << 8)
836 #define RT3261_PWR_IN_R_BIT 8
838 /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
839 #define RT3261_I2S_MS_MASK (0x1 << 15)
840 #define RT3261_I2S_MS_SFT 15
841 #define RT3261_I2S_MS_M (0x0 << 15)
842 #define RT3261_I2S_MS_S (0x1 << 15)
843 #define RT3261_I2S_IF_MASK (0x7 << 12)
844 #define RT3261_I2S_IF_SFT 12
845 #define RT3261_I2S_O_CP_MASK (0x3 << 10)
846 #define RT3261_I2S_O_CP_SFT 10
847 #define RT3261_I2S_O_CP_OFF (0x0 << 10)
848 #define RT3261_I2S_O_CP_U_LAW (0x1 << 10)
849 #define RT3261_I2S_O_CP_A_LAW (0x2 << 10)
850 #define RT3261_I2S_I_CP_MASK (0x3 << 8)
851 #define RT3261_I2S_I_CP_SFT 8
852 #define RT3261_I2S_I_CP_OFF (0x0 << 8)
853 #define RT3261_I2S_I_CP_U_LAW (0x1 << 8)
854 #define RT3261_I2S_I_CP_A_LAW (0x2 << 8)
855 #define RT3261_I2S_BP_MASK (0x1 << 7)
856 #define RT3261_I2S_BP_SFT 7
857 #define RT3261_I2S_BP_NOR (0x0 << 7)
858 #define RT3261_I2S_BP_INV (0x1 << 7)
859 #define RT3261_I2S_DL_MASK (0x3 << 2)
860 #define RT3261_I2S_DL_SFT 2
861 #define RT3261_I2S_DL_16 (0x0 << 2)
862 #define RT3261_I2S_DL_20 (0x1 << 2)
863 #define RT3261_I2S_DL_24 (0x2 << 2)
864 #define RT3261_I2S_DL_8 (0x3 << 2)
865 #define RT3261_I2S_DF_MASK (0x3)
866 #define RT3261_I2S_DF_SFT 0
867 #define RT3261_I2S_DF_I2S (0x0)
868 #define RT3261_I2S_DF_LEFT (0x1)
869 #define RT3261_I2S_DF_PCM_A (0x2)
870 #define RT3261_I2S_DF_PCM_B (0x3)
872 /* I2S2 Audio Serial Data Port Control (0x71) */
873 #define RT3261_I2S2_SDI_MASK (0x1 << 6)
874 #define RT3261_I2S2_SDI_SFT 6
875 #define RT3261_I2S2_SDI_I2S1 (0x0 << 6)
876 #define RT3261_I2S2_SDI_I2S2 (0x1 << 6)
878 /* ADC/DAC Clock Control 1 (0x73) */
879 #define RT3261_I2S_BCLK_MS1_MASK (0x1 << 15)
880 #define RT3261_I2S_BCLK_MS1_SFT 15
881 #define RT3261_I2S_BCLK_MS1_32 (0x0 << 15)
882 #define RT3261_I2S_BCLK_MS1_64 (0x1 << 15)
883 #define RT3261_I2S_PD1_MASK (0x7 << 12)
884 #define RT3261_I2S_PD1_SFT 12
885 #define RT3261_I2S_PD1_1 (0x0 << 12)
886 #define RT3261_I2S_PD1_2 (0x1 << 12)
887 #define RT3261_I2S_PD1_3 (0x2 << 12)
888 #define RT3261_I2S_PD1_4 (0x3 << 12)
889 #define RT3261_I2S_PD1_6 (0x4 << 12)
890 #define RT3261_I2S_PD1_8 (0x5 << 12)
891 #define RT3261_I2S_PD1_12 (0x6 << 12)
892 #define RT3261_I2S_PD1_16 (0x7 << 12)
893 #define RT3261_I2S_BCLK_MS2_MASK (0x1 << 11)
894 #define RT3261_I2S_BCLK_MS2_SFT 11
895 #define RT3261_I2S_BCLK_MS2_32 (0x0 << 11)
896 #define RT3261_I2S_BCLK_MS2_64 (0x1 << 11)
897 #define RT3261_I2S_PD2_MASK (0x7 << 8)
898 #define RT3261_I2S_PD2_SFT 8
899 #define RT3261_I2S_PD2_1 (0x0 << 8)
900 #define RT3261_I2S_PD2_2 (0x1 << 8)
901 #define RT3261_I2S_PD2_3 (0x2 << 8)
902 #define RT3261_I2S_PD2_4 (0x3 << 8)
903 #define RT3261_I2S_PD2_6 (0x4 << 8)
904 #define RT3261_I2S_PD2_8 (0x5 << 8)
905 #define RT3261_I2S_PD2_12 (0x6 << 8)
906 #define RT3261_I2S_PD2_16 (0x7 << 8)
907 #define RT3261_I2S_BCLK_MS3_MASK (0x1 << 7)
908 #define RT3261_I2S_BCLK_MS3_SFT 7
909 #define RT3261_I2S_BCLK_MS3_32 (0x0 << 7)
910 #define RT3261_I2S_BCLK_MS3_64 (0x1 << 7)
911 #define RT3261_I2S_PD3_MASK (0x7 << 4)
912 #define RT3261_I2S_PD3_SFT 4
913 #define RT3261_I2S_PD3_1 (0x0 << 4)
914 #define RT3261_I2S_PD3_2 (0x1 << 4)
915 #define RT3261_I2S_PD3_3 (0x2 << 4)
916 #define RT3261_I2S_PD3_4 (0x3 << 4)
917 #define RT3261_I2S_PD3_6 (0x4 << 4)
918 #define RT3261_I2S_PD3_8 (0x5 << 4)
919 #define RT3261_I2S_PD3_12 (0x6 << 4)
920 #define RT3261_I2S_PD3_16 (0x7 << 4)
921 #define RT3261_DAC_OSR_MASK (0x3 << 2)
922 #define RT3261_DAC_OSR_SFT 2
923 #define RT3261_DAC_OSR_128 (0x0 << 2)
924 #define RT3261_DAC_OSR_64 (0x1 << 2)
925 #define RT3261_DAC_OSR_32 (0x2 << 2)
926 #define RT3261_DAC_OSR_16 (0x3 << 2)
927 #define RT3261_ADC_OSR_MASK (0x3)
928 #define RT3261_ADC_OSR_SFT 0
929 #define RT3261_ADC_OSR_128 (0x0)
930 #define RT3261_ADC_OSR_64 (0x1)
931 #define RT3261_ADC_OSR_32 (0x2)
932 #define RT3261_ADC_OSR_16 (0x3)
934 /* ADC/DAC Clock Control 2 (0x74) */
935 #define RT3261_DAC_L_OSR_MASK (0x3 << 14)
936 #define RT3261_DAC_L_OSR_SFT 14
937 #define RT3261_DAC_L_OSR_128 (0x0 << 14)
938 #define RT3261_DAC_L_OSR_64 (0x1 << 14)
939 #define RT3261_DAC_L_OSR_32 (0x2 << 14)
940 #define RT3261_DAC_L_OSR_16 (0x3 << 14)
941 #define RT3261_ADC_R_OSR_MASK (0x3 << 12)
942 #define RT3261_ADC_R_OSR_SFT 12
943 #define RT3261_ADC_R_OSR_128 (0x0 << 12)
944 #define RT3261_ADC_R_OSR_64 (0x1 << 12)
945 #define RT3261_ADC_R_OSR_32 (0x2 << 12)
946 #define RT3261_ADC_R_OSR_16 (0x3 << 12)
947 #define RT3261_DAHPF_EN (0x1 << 11)
948 #define RT3261_DAHPF_EN_SFT 11
949 #define RT3261_ADHPF_EN (0x1 << 10)
950 #define RT3261_ADHPF_EN_SFT 10
952 /* Digital Microphone Control (0x75) */
953 #define RT3261_DMIC_1_EN_MASK (0x1 << 15)
954 #define RT3261_DMIC_1_EN_SFT 15
955 #define RT3261_DMIC_1_DIS (0x0 << 15)
956 #define RT3261_DMIC_1_EN (0x1 << 15)
957 #define RT3261_DMIC_2_EN_MASK (0x1 << 14)
958 #define RT3261_DMIC_2_EN_SFT 14
959 #define RT3261_DMIC_2_DIS (0x0 << 14)
960 #define RT3261_DMIC_2_EN (0x1 << 14)
961 #define RT3261_DMIC_1L_LH_MASK (0x1 << 13)
962 #define RT3261_DMIC_1L_LH_SFT 13
963 #define RT3261_DMIC_1L_LH_FALLING (0x0 << 13)
964 #define RT3261_DMIC_1L_LH_RISING (0x1 << 13)
965 #define RT3261_DMIC_1R_LH_MASK (0x1 << 12)
966 #define RT3261_DMIC_1R_LH_SFT 12
967 #define RT3261_DMIC_1R_LH_FALLING (0x0 << 12)
968 #define RT3261_DMIC_1R_LH_RISING (0x1 << 12)
969 #define RT3261_DMIC_1_DP_MASK (0x1 << 11)
970 #define RT3261_DMIC_1_DP_SFT 11
971 #define RT3261_DMIC_1_DP_GPIO3 (0x0 << 11)
972 #define RT3261_DMIC_1_DP_IN1P (0x1 << 11)
973 #define RT3261_DMIC_2_DP_MASK (0x1 << 10)
974 #define RT3261_DMIC_2_DP_SFT 10
975 #define RT3261_DMIC_2_DP_GPIO4 (0x0 << 10)
976 #define RT3261_DMIC_2_DP_IN1N (0x1 << 10)
977 #define RT3261_DMIC_2L_LH_MASK (0x1 << 9)
978 #define RT3261_DMIC_2L_LH_SFT 9
979 #define RT3261_DMIC_2L_LH_FALLING (0x0 << 9)
980 #define RT3261_DMIC_2L_LH_RISING (0x1 << 9)
981 #define RT3261_DMIC_2R_LH_MASK (0x1 << 8)
982 #define RT3261_DMIC_2R_LH_SFT 8
983 #define RT3261_DMIC_2R_LH_FALLING (0x0 << 8)
984 #define RT3261_DMIC_2R_LH_RISING (0x1 << 8)
985 #define RT3261_DMIC_CLK_MASK (0x7 << 5)
986 #define RT3261_DMIC_CLK_SFT 5
988 /* Global Clock Control (0x80) */
989 #define RT3261_SCLK_SRC_MASK (0x3 << 14)
990 #define RT3261_SCLK_SRC_SFT 14
991 #define RT3261_SCLK_SRC_MCLK (0x0 << 14)
992 #define RT3261_SCLK_SRC_PLL1 (0x1 << 14)
993 #define RT3261_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
994 #define RT3261_PLL1_SRC_MASK (0x3 << 12)
995 #define RT3261_PLL1_SRC_SFT 12
996 #define RT3261_PLL1_SRC_MCLK (0x0 << 12)
997 #define RT3261_PLL1_SRC_BCLK1 (0x1 << 12)
998 #define RT3261_PLL1_SRC_BCLK2 (0x2 << 12)
999 #define RT3261_PLL1_SRC_BCLK3 (0x3 << 12)
1000 #define RT3261_PLL1_PD_MASK (0x1 << 3)
1001 #define RT3261_PLL1_PD_SFT 3
1002 #define RT3261_PLL1_PD_1 (0x0 << 3)
1003 #define RT3261_PLL1_PD_2 (0x1 << 3)
1005 #define RT3261_PLL_INP_MAX 40000000
1006 #define RT3261_PLL_INP_MIN 256000
1007 /* PLL M/N/K Code Control 1 (0x81) */
1008 #define RT3261_PLL_N_MAX 0x1ff
1009 #define RT3261_PLL_N_MASK (RT3261_PLL_N_MAX << 7)
1010 #define RT3261_PLL_N_SFT 7
1011 #define RT3261_PLL_K_MAX 0x1f
1012 #define RT3261_PLL_K_MASK (RT3261_PLL_K_MAX)
1013 #define RT3261_PLL_K_SFT 0
1015 /* PLL M/N/K Code Control 2 (0x82) */
1016 #define RT3261_PLL_M_MAX 0xf
1017 #define RT3261_PLL_M_MASK (RT3261_PLL_M_MAX << 12)
1018 #define RT3261_PLL_M_SFT 12
1019 #define RT3261_PLL_M_BP (0x1 << 11)
1020 #define RT3261_PLL_M_BP_SFT 11
1022 /* ASRC Control 1 (0x83) */
1023 #define RT3261_STO_T_MASK (0x1 << 15)
1024 #define RT3261_STO_T_SFT 15
1025 #define RT3261_STO_T_SCLK (0x0 << 15)
1026 #define RT3261_STO_T_LRCK1 (0x1 << 15)
1027 #define RT3261_M1_T_MASK (0x1 << 14)
1028 #define RT3261_M1_T_SFT 14
1029 #define RT3261_M1_T_I2S2 (0x0 << 14)
1030 #define RT3261_M1_T_I2S2_D3 (0x1 << 14)
1031 #define RT3261_I2S2_F_MASK (0x1 << 12)
1032 #define RT3261_I2S2_F_SFT 12
1033 #define RT3261_I2S2_F_I2S2_D2 (0x0 << 12)
1034 #define RT3261_I2S2_F_I2S1_TCLK (0x1 << 12)
1035 #define RT3261_DMIC_1_M_MASK (0x1 << 9)
1036 #define RT3261_DMIC_1_M_SFT 9
1037 #define RT3261_DMIC_1_M_NOR (0x0 << 9)
1038 #define RT3261_DMIC_1_M_ASYN (0x1 << 9)
1039 #define RT3261_DMIC_2_M_MASK (0x1 << 8)
1040 #define RT3261_DMIC_2_M_SFT 8
1041 #define RT3261_DMIC_2_M_NOR (0x0 << 8)
1042 #define RT3261_DMIC_2_M_ASYN (0x1 << 8)
1044 /* ASRC Control 2 (0x84) */
1045 #define RT3261_MDA_L_M_MASK (0x1 << 15)
1046 #define RT3261_MDA_L_M_SFT 15
1047 #define RT3261_MDA_L_M_NOR (0x0 << 15)
1048 #define RT3261_MDA_L_M_ASYN (0x1 << 15)
1049 #define RT3261_MDA_R_M_MASK (0x1 << 14)
1050 #define RT3261_MDA_R_M_SFT 14
1051 #define RT3261_MDA_R_M_NOR (0x0 << 14)
1052 #define RT3261_MDA_R_M_ASYN (0x1 << 14)
1053 #define RT3261_MAD_L_M_MASK (0x1 << 13)
1054 #define RT3261_MAD_L_M_SFT 13
1055 #define RT3261_MAD_L_M_NOR (0x0 << 13)
1056 #define RT3261_MAD_L_M_ASYN (0x1 << 13)
1057 #define RT3261_MAD_R_M_MASK (0x1 << 12)
1058 #define RT3261_MAD_R_M_SFT 12
1059 #define RT3261_MAD_R_M_NOR (0x0 << 12)
1060 #define RT3261_MAD_R_M_ASYN (0x1 << 12)
1061 #define RT3261_ADC_M_MASK (0x1 << 11)
1062 #define RT3261_ADC_M_SFT 11
1063 #define RT3261_ADC_M_NOR (0x0 << 11)
1064 #define RT3261_ADC_M_ASYN (0x1 << 11)
1065 #define RT3261_STO_DAC_M_MASK (0x1 << 5)
1066 #define RT3261_STO_DAC_M_SFT 5
1067 #define RT3261_STO_DAC_M_NOR (0x0 << 5)
1068 #define RT3261_STO_DAC_M_ASYN (0x1 << 5)
1069 #define RT3261_I2S1_R_D_MASK (0x1 << 4)
1070 #define RT3261_I2S1_R_D_SFT 4
1071 #define RT3261_I2S1_R_D_DIS (0x0 << 4)
1072 #define RT3261_I2S1_R_D_EN (0x1 << 4)
1073 #define RT3261_I2S2_R_D_MASK (0x1 << 3)
1074 #define RT3261_I2S2_R_D_SFT 3
1075 #define RT3261_I2S2_R_D_DIS (0x0 << 3)
1076 #define RT3261_I2S2_R_D_EN (0x1 << 3)
1077 #define RT3261_PRE_SCLK_MASK (0x3)
1078 #define RT3261_PRE_SCLK_SFT 0
1079 #define RT3261_PRE_SCLK_512 (0x0)
1080 #define RT3261_PRE_SCLK_1024 (0x1)
1081 #define RT3261_PRE_SCLK_2048 (0x2)
1083 /* ASRC Control 3 (0x85) */
1084 #define RT3261_I2S1_RATE_MASK (0xf << 12)
1085 #define RT3261_I2S1_RATE_SFT 12
1086 #define RT3261_I2S2_RATE_MASK (0xf << 8)
1087 #define RT3261_I2S2_RATE_SFT 8
1089 /* ASRC Control 4 (0x89) */
1090 #define RT3261_I2S1_PD_MASK (0x7 << 12)
1091 #define RT3261_I2S1_PD_SFT 12
1092 #define RT3261_I2S2_PD_MASK (0x7 << 8)
1093 #define RT3261_I2S2_PD_SFT 8
1095 /* HPOUT Over Current Detection (0x8b) */
1096 #define RT3261_HP_OVCD_MASK (0x1 << 10)
1097 #define RT3261_HP_OVCD_SFT 10
1098 #define RT3261_HP_OVCD_DIS (0x0 << 10)
1099 #define RT3261_HP_OVCD_EN (0x1 << 10)
1100 #define RT3261_HP_OC_TH_MASK (0x3 << 8)
1101 #define RT3261_HP_OC_TH_SFT 8
1102 #define RT3261_HP_OC_TH_90 (0x0 << 8)
1103 #define RT3261_HP_OC_TH_105 (0x1 << 8)
1104 #define RT3261_HP_OC_TH_120 (0x2 << 8)
1105 #define RT3261_HP_OC_TH_135 (0x3 << 8)
1107 /* Class D Over Current Control (0x8c) */
1108 #define RT3261_CLSD_OC_MASK (0x1 << 9)
1109 #define RT3261_CLSD_OC_SFT 9
1110 #define RT3261_CLSD_OC_PU (0x0 << 9)
1111 #define RT3261_CLSD_OC_PD (0x1 << 9)
1112 #define RT3261_AUTO_PD_MASK (0x1 << 8)
1113 #define RT3261_AUTO_PD_SFT 8
1114 #define RT3261_AUTO_PD_DIS (0x0 << 8)
1115 #define RT3261_AUTO_PD_EN (0x1 << 8)
1116 #define RT3261_CLSD_OC_TH_MASK (0x3f)
1117 #define RT3261_CLSD_OC_TH_SFT 0
1119 /* Class D Output Control (0x8d) */
1120 #define RT3261_CLSD_RATIO_MASK (0xf << 12)
1121 #define RT3261_CLSD_RATIO_SFT 12
1122 #define RT3261_CLSD_OM_MASK (0x1 << 11)
1123 #define RT3261_CLSD_OM_SFT 11
1124 #define RT3261_CLSD_OM_MONO (0x0 << 11)
1125 #define RT3261_CLSD_OM_STO (0x1 << 11)
1126 #define RT3261_CLSD_SCH_MASK (0x1 << 10)
1127 #define RT3261_CLSD_SCH_SFT 10
1128 #define RT3261_CLSD_SCH_L (0x0 << 10)
1129 #define RT3261_CLSD_SCH_S (0x1 << 10)
1131 /* Depop Mode Control 1 (0x8e) */
1132 #define RT3261_SMT_TRIG_MASK (0x1 << 15)
1133 #define RT3261_SMT_TRIG_SFT 15
1134 #define RT3261_SMT_TRIG_DIS (0x0 << 15)
1135 #define RT3261_SMT_TRIG_EN (0x1 << 15)
1136 #define RT3261_HP_L_SMT_MASK (0x1 << 9)
1137 #define RT3261_HP_L_SMT_SFT 9
1138 #define RT3261_HP_L_SMT_DIS (0x0 << 9)
1139 #define RT3261_HP_L_SMT_EN (0x1 << 9)
1140 #define RT3261_HP_R_SMT_MASK (0x1 << 8)
1141 #define RT3261_HP_R_SMT_SFT 8
1142 #define RT3261_HP_R_SMT_DIS (0x0 << 8)
1143 #define RT3261_HP_R_SMT_EN (0x1 << 8)
1144 #define RT3261_HP_CD_PD_MASK (0x1 << 7)
1145 #define RT3261_HP_CD_PD_SFT 7
1146 #define RT3261_HP_CD_PD_DIS (0x0 << 7)
1147 #define RT3261_HP_CD_PD_EN (0x1 << 7)
1148 #define RT3261_RSTN_MASK (0x1 << 6)
1149 #define RT3261_RSTN_SFT 6
1150 #define RT3261_RSTN_DIS (0x0 << 6)
1151 #define RT3261_RSTN_EN (0x1 << 6)
1152 #define RT3261_RSTP_MASK (0x1 << 5)
1153 #define RT3261_RSTP_SFT 5
1154 #define RT3261_RSTP_DIS (0x0 << 5)
1155 #define RT3261_RSTP_EN (0x1 << 5)
1156 #define RT3261_HP_CO_MASK (0x1 << 4)
1157 #define RT3261_HP_CO_SFT 4
1158 #define RT3261_HP_CO_DIS (0x0 << 4)
1159 #define RT3261_HP_CO_EN (0x1 << 4)
1160 #define RT3261_HP_CP_MASK (0x1 << 3)
1161 #define RT3261_HP_CP_SFT 3
1162 #define RT3261_HP_CP_PD (0x0 << 3)
1163 #define RT3261_HP_CP_PU (0x1 << 3)
1164 #define RT3261_HP_SG_MASK (0x1 << 2)
1165 #define RT3261_HP_SG_SFT 2
1166 #define RT3261_HP_SG_DIS (0x0 << 2)
1167 #define RT3261_HP_SG_EN (0x1 << 2)
1168 #define RT3261_HP_DP_MASK (0x1 << 1)
1169 #define RT3261_HP_DP_SFT 1
1170 #define RT3261_HP_DP_PD (0x0 << 1)
1171 #define RT3261_HP_DP_PU (0x1 << 1)
1172 #define RT3261_HP_CB_MASK (0x1)
1173 #define RT3261_HP_CB_SFT 0
1174 #define RT3261_HP_CB_PD (0x0)
1175 #define RT3261_HP_CB_PU (0x1)
1177 /* Depop Mode Control 2 (0x8f) */
1178 #define RT3261_DEPOP_MASK (0x1 << 13)
1179 #define RT3261_DEPOP_SFT 13
1180 #define RT3261_DEPOP_AUTO (0x0 << 13)
1181 #define RT3261_DEPOP_MAN (0x1 << 13)
1182 #define RT3261_RAMP_MASK (0x1 << 12)
1183 #define RT3261_RAMP_SFT 12
1184 #define RT3261_RAMP_DIS (0x0 << 12)
1185 #define RT3261_RAMP_EN (0x1 << 12)
1186 #define RT3261_BPS_MASK (0x1 << 11)
1187 #define RT3261_BPS_SFT 11
1188 #define RT3261_BPS_DIS (0x0 << 11)
1189 #define RT3261_BPS_EN (0x1 << 11)
1190 #define RT3261_FAST_UPDN_MASK (0x1 << 10)
1191 #define RT3261_FAST_UPDN_SFT 10
1192 #define RT3261_FAST_UPDN_DIS (0x0 << 10)
1193 #define RT3261_FAST_UPDN_EN (0x1 << 10)
1194 #define RT3261_MRES_MASK (0x3 << 8)
1195 #define RT3261_MRES_SFT 8
1196 #define RT3261_MRES_15MO (0x0 << 8)
1197 #define RT3261_MRES_25MO (0x1 << 8)
1198 #define RT3261_MRES_35MO (0x2 << 8)
1199 #define RT3261_MRES_45MO (0x3 << 8)
1200 #define RT3261_VLO_MASK (0x1 << 7)
1201 #define RT3261_VLO_SFT 7
1202 #define RT3261_VLO_3V (0x0 << 7)
1203 #define RT3261_VLO_32V (0x1 << 7)
1204 #define RT3261_DIG_DP_MASK (0x1 << 6)
1205 #define RT3261_DIG_DP_SFT 6
1206 #define RT3261_DIG_DP_DIS (0x0 << 6)
1207 #define RT3261_DIG_DP_EN (0x1 << 6)
1208 #define RT3261_DP_TH_MASK (0x3 << 4)
1209 #define RT3261_DP_TH_SFT 4
1211 /* Depop Mode Control 3 (0x90) */
1212 #define RT3261_CP_SYS_MASK (0x7 << 12)
1213 #define RT3261_CP_SYS_SFT 12
1214 #define RT3261_CP_FQ1_MASK (0x7 << 8)
1215 #define RT3261_CP_FQ1_SFT 8
1216 #define RT3261_CP_FQ2_MASK (0x7 << 4)
1217 #define RT3261_CP_FQ2_SFT 4
1218 #define RT3261_CP_FQ3_MASK (0x7)
1219 #define RT3261_CP_FQ3_SFT 0
1220 #define RT3261_CP_FQ_1_5_KHZ 0
1221 #define RT3261_CP_FQ_3_KHZ 1
1222 #define RT3261_CP_FQ_6_KHZ 2
1223 #define RT3261_CP_FQ_12_KHZ 3
1224 #define RT3261_CP_FQ_24_KHZ 4
1225 #define RT3261_CP_FQ_48_KHZ 5
1226 #define RT3261_CP_FQ_96_KHZ 6
1227 #define RT3261_CP_FQ_192_KHZ 7
1229 /* HPOUT charge pump (0x91) */
1230 #define RT3261_OSW_L_MASK (0x1 << 11)
1231 #define RT3261_OSW_L_SFT 11
1232 #define RT3261_OSW_L_DIS (0x0 << 11)
1233 #define RT3261_OSW_L_EN (0x1 << 11)
1234 #define RT3261_OSW_R_MASK (0x1 << 10)
1235 #define RT3261_OSW_R_SFT 10
1236 #define RT3261_OSW_R_DIS (0x0 << 10)
1237 #define RT3261_OSW_R_EN (0x1 << 10)
1238 #define RT3261_PM_HP_MASK (0x3 << 8)
1239 #define RT3261_PM_HP_SFT 8
1240 #define RT3261_PM_HP_LV (0x0 << 8)
1241 #define RT3261_PM_HP_MV (0x1 << 8)
1242 #define RT3261_PM_HP_HV (0x2 << 8)
1243 #define RT3261_IB_HP_MASK (0x3 << 6)
1244 #define RT3261_IB_HP_SFT 6
1245 #define RT3261_IB_HP_125IL (0x0 << 6)
1246 #define RT3261_IB_HP_25IL (0x1 << 6)
1247 #define RT3261_IB_HP_5IL (0x2 << 6)
1248 #define RT3261_IB_HP_1IL (0x3 << 6)
1250 /* PV detection and SPK gain control (0x92) */
1251 #define RT3261_PVDD_DET_MASK (0x1 << 15)
1252 #define RT3261_PVDD_DET_SFT 15
1253 #define RT3261_PVDD_DET_DIS (0x0 << 15)
1254 #define RT3261_PVDD_DET_EN (0x1 << 15)
1255 #define RT3261_SPK_AG_MASK (0x1 << 14)
1256 #define RT3261_SPK_AG_SFT 14
1257 #define RT3261_SPK_AG_DIS (0x0 << 14)
1258 #define RT3261_SPK_AG_EN (0x1 << 14)
1260 /* Micbias Control (0x93) */
1261 #define RT3261_MIC1_BS_MASK (0x1 << 15)
1262 #define RT3261_MIC1_BS_SFT 15
1263 #define RT3261_MIC1_BS_9AV (0x0 << 15)
1264 #define RT3261_MIC1_BS_75AV (0x1 << 15)
1265 #define RT3261_MIC2_BS_MASK (0x1 << 14)
1266 #define RT3261_MIC2_BS_SFT 14
1267 #define RT3261_MIC2_BS_9AV (0x0 << 14)
1268 #define RT3261_MIC2_BS_75AV (0x1 << 14)
1269 #define RT3261_MIC1_CLK_MASK (0x1 << 13)
1270 #define RT3261_MIC1_CLK_SFT 13
1271 #define RT3261_MIC1_CLK_DIS (0x0 << 13)
1272 #define RT3261_MIC1_CLK_EN (0x1 << 13)
1273 #define RT3261_MIC2_CLK_MASK (0x1 << 12)
1274 #define RT3261_MIC2_CLK_SFT 12
1275 #define RT3261_MIC2_CLK_DIS (0x0 << 12)
1276 #define RT3261_MIC2_CLK_EN (0x1 << 12)
1277 #define RT3261_MIC1_OVCD_MASK (0x1 << 11)
1278 #define RT3261_MIC1_OVCD_SFT 11
1279 #define RT3261_MIC1_OVCD_DIS (0x0 << 11)
1280 #define RT3261_MIC1_OVCD_EN (0x1 << 11)
1281 #define RT3261_MIC1_OVTH_MASK (0x3 << 9)
1282 #define RT3261_MIC1_OVTH_SFT 9
1283 #define RT3261_MIC1_OVTH_600UA (0x0 << 9)
1284 #define RT3261_MIC1_OVTH_1500UA (0x1 << 9)
1285 #define RT3261_MIC1_OVTH_2000UA (0x2 << 9)
1286 #define RT3261_MIC2_OVCD_MASK (0x1 << 8)
1287 #define RT3261_MIC2_OVCD_SFT 8
1288 #define RT3261_MIC2_OVCD_DIS (0x0 << 8)
1289 #define RT3261_MIC2_OVCD_EN (0x1 << 8)
1290 #define RT3261_MIC2_OVTH_MASK (0x3 << 6)
1291 #define RT3261_MIC2_OVTH_SFT 6
1292 #define RT3261_MIC2_OVTH_600UA (0x0 << 6)
1293 #define RT3261_MIC2_OVTH_1500UA (0x1 << 6)
1294 #define RT3261_MIC2_OVTH_2000UA (0x2 << 6)
1295 #define RT3261_PWR_MB_MASK (0x1 << 5)
1296 #define RT3261_PWR_MB_SFT 5
1297 #define RT3261_PWR_MB_PD (0x0 << 5)
1298 #define RT3261_PWR_MB_PU (0x1 << 5)
1299 #define RT3261_PWR_CLK25M_MASK (0x1 << 4)
1300 #define RT3261_PWR_CLK25M_SFT 4
1301 #define RT3261_PWR_CLK25M_PD (0x0 << 4)
1302 #define RT3261_PWR_CLK25M_PU (0x1 << 4)
1304 /* EQ Control 1 (0xb0) */
1305 #define RT3261_EQ_SRC_MASK (0x1 << 15)
1306 #define RT3261_EQ_SRC_SFT 15
1307 #define RT3261_EQ_SRC_DAC (0x0 << 15)
1308 #define RT3261_EQ_SRC_ADC (0x1 << 15)
1309 #define RT3261_EQ_UPD (0x1 << 14)
1310 #define RT3261_EQ_UPD_BIT 14
1311 #define RT3261_EQ_CD_MASK (0x1 << 13)
1312 #define RT3261_EQ_CD_SFT 13
1313 #define RT3261_EQ_CD_DIS (0x0 << 13)
1314 #define RT3261_EQ_CD_EN (0x1 << 13)
1315 #define RT3261_EQ_DITH_MASK (0x3 << 8)
1316 #define RT3261_EQ_DITH_SFT 8
1317 #define RT3261_EQ_DITH_NOR (0x0 << 8)
1318 #define RT3261_EQ_DITH_LSB (0x1 << 8)
1319 #define RT3261_EQ_DITH_LSB_1 (0x2 << 8)
1320 #define RT3261_EQ_DITH_LSB_2 (0x3 << 8)
1322 /* EQ Control 2 (0xb1) */
1323 #define RT3261_EQ_HPF1_M_MASK (0x1 << 8)
1324 #define RT3261_EQ_HPF1_M_SFT 8
1325 #define RT3261_EQ_HPF1_M_HI (0x0 << 8)
1326 #define RT3261_EQ_HPF1_M_1ST (0x1 << 8)
1327 #define RT3261_EQ_LPF1_M_MASK (0x1 << 7)
1328 #define RT3261_EQ_LPF1_M_SFT 7
1329 #define RT3261_EQ_LPF1_M_LO (0x0 << 7)
1330 #define RT3261_EQ_LPF1_M_1ST (0x1 << 7)
1331 #define RT3261_EQ_HPF2_MASK (0x1 << 6)
1332 #define RT3261_EQ_HPF2_SFT 6
1333 #define RT3261_EQ_HPF2_DIS (0x0 << 6)
1334 #define RT3261_EQ_HPF2_EN (0x1 << 6)
1335 #define RT3261_EQ_HPF1_MASK (0x1 << 5)
1336 #define RT3261_EQ_HPF1_SFT 5
1337 #define RT3261_EQ_HPF1_DIS (0x0 << 5)
1338 #define RT3261_EQ_HPF1_EN (0x1 << 5)
1339 #define RT3261_EQ_BPF4_MASK (0x1 << 4)
1340 #define RT3261_EQ_BPF4_SFT 4
1341 #define RT3261_EQ_BPF4_DIS (0x0 << 4)
1342 #define RT3261_EQ_BPF4_EN (0x1 << 4)
1343 #define RT3261_EQ_BPF3_MASK (0x1 << 3)
1344 #define RT3261_EQ_BPF3_SFT 3
1345 #define RT3261_EQ_BPF3_DIS (0x0 << 3)
1346 #define RT3261_EQ_BPF3_EN (0x1 << 3)
1347 #define RT3261_EQ_BPF2_MASK (0x1 << 2)
1348 #define RT3261_EQ_BPF2_SFT 2
1349 #define RT3261_EQ_BPF2_DIS (0x0 << 2)
1350 #define RT3261_EQ_BPF2_EN (0x1 << 2)
1351 #define RT3261_EQ_BPF1_MASK (0x1 << 1)
1352 #define RT3261_EQ_BPF1_SFT 1
1353 #define RT3261_EQ_BPF1_DIS (0x0 << 1)
1354 #define RT3261_EQ_BPF1_EN (0x1 << 1)
1355 #define RT3261_EQ_LPF_MASK (0x1)
1356 #define RT3261_EQ_LPF_SFT 0
1357 #define RT3261_EQ_LPF_DIS (0x0)
1358 #define RT3261_EQ_LPF_EN (0x1)
1359 #define RT3261_EQ_CTRL_MASK (0x7f)
1361 /* Memory Test (0xb2) */
1362 #define RT3261_MT_MASK (0x1 << 15)
1363 #define RT3261_MT_SFT 15
1364 #define RT3261_MT_DIS (0x0 << 15)
1365 #define RT3261_MT_EN (0x1 << 15)
1367 /* DRC/AGC Control 1 (0xb4) */
1368 #define RT3261_DRC_AGC_P_MASK (0x1 << 15)
1369 #define RT3261_DRC_AGC_P_SFT 15
1370 #define RT3261_DRC_AGC_P_DAC (0x0 << 15)
1371 #define RT3261_DRC_AGC_P_ADC (0x1 << 15)
1372 #define RT3261_DRC_AGC_MASK (0x1 << 14)
1373 #define RT3261_DRC_AGC_SFT 14
1374 #define RT3261_DRC_AGC_DIS (0x0 << 14)
1375 #define RT3261_DRC_AGC_EN (0x1 << 14)
1376 #define RT3261_DRC_AGC_UPD (0x1 << 13)
1377 #define RT3261_DRC_AGC_UPD_BIT 13
1378 #define RT3261_DRC_AGC_AR_MASK (0x1f << 8)
1379 #define RT3261_DRC_AGC_AR_SFT 8
1380 #define RT3261_DRC_AGC_R_MASK (0x7 << 5)
1381 #define RT3261_DRC_AGC_R_SFT 5
1382 #define RT3261_DRC_AGC_R_48K (0x1 << 5)
1383 #define RT3261_DRC_AGC_R_96K (0x2 << 5)
1384 #define RT3261_DRC_AGC_R_192K (0x3 << 5)
1385 #define RT3261_DRC_AGC_R_441K (0x5 << 5)
1386 #define RT3261_DRC_AGC_R_882K (0x6 << 5)
1387 #define RT3261_DRC_AGC_R_1764K (0x7 << 5)
1388 #define RT3261_DRC_AGC_RC_MASK (0x1f)
1389 #define RT3261_DRC_AGC_RC_SFT 0
1391 /* DRC/AGC Control 2 (0xb5) */
1392 #define RT3261_DRC_AGC_POB_MASK (0x3f << 8)
1393 #define RT3261_DRC_AGC_POB_SFT 8
1394 #define RT3261_DRC_AGC_CP_MASK (0x1 << 7)
1395 #define RT3261_DRC_AGC_CP_SFT 7
1396 #define RT3261_DRC_AGC_CP_DIS (0x0 << 7)
1397 #define RT3261_DRC_AGC_CP_EN (0x1 << 7)
1398 #define RT3261_DRC_AGC_CPR_MASK (0x3 << 5)
1399 #define RT3261_DRC_AGC_CPR_SFT 5
1400 #define RT3261_DRC_AGC_CPR_1_1 (0x0 << 5)
1401 #define RT3261_DRC_AGC_CPR_1_2 (0x1 << 5)
1402 #define RT3261_DRC_AGC_CPR_1_3 (0x2 << 5)
1403 #define RT3261_DRC_AGC_CPR_1_4 (0x3 << 5)
1404 #define RT3261_DRC_AGC_PRB_MASK (0x1f)
1405 #define RT3261_DRC_AGC_PRB_SFT 0
1407 /* DRC/AGC Control 3 (0xb6) */
1408 #define RT3261_DRC_AGC_NGB_MASK (0xf << 12)
1409 #define RT3261_DRC_AGC_NGB_SFT 12
1410 #define RT3261_DRC_AGC_TAR_MASK (0x1f << 7)
1411 #define RT3261_DRC_AGC_TAR_SFT 7
1412 #define RT3261_DRC_AGC_NG_MASK (0x1 << 6)
1413 #define RT3261_DRC_AGC_NG_SFT 6
1414 #define RT3261_DRC_AGC_NG_DIS (0x0 << 6)
1415 #define RT3261_DRC_AGC_NG_EN (0x1 << 6)
1416 #define RT3261_DRC_AGC_NGH_MASK (0x1 << 5)
1417 #define RT3261_DRC_AGC_NGH_SFT 5
1418 #define RT3261_DRC_AGC_NGH_DIS (0x0 << 5)
1419 #define RT3261_DRC_AGC_NGH_EN (0x1 << 5)
1420 #define RT3261_DRC_AGC_NGT_MASK (0x1f)
1421 #define RT3261_DRC_AGC_NGT_SFT 0
1423 /* ANC Control 1 (0xb8) */
1424 #define RT3261_ANC_M_MASK (0x1 << 15)
1425 #define RT3261_ANC_M_SFT 15
1426 #define RT3261_ANC_M_NOR (0x0 << 15)
1427 #define RT3261_ANC_M_REV (0x1 << 15)
1428 #define RT3261_ANC_MASK (0x1 << 14)
1429 #define RT3261_ANC_SFT 14
1430 #define RT3261_ANC_DIS (0x0 << 14)
1431 #define RT3261_ANC_EN (0x1 << 14)
1432 #define RT3261_ANC_MD_MASK (0x3 << 12)
1433 #define RT3261_ANC_MD_SFT 12
1434 #define RT3261_ANC_MD_DIS (0x0 << 12)
1435 #define RT3261_ANC_MD_67MS (0x1 << 12)
1436 #define RT3261_ANC_MD_267MS (0x2 << 12)
1437 #define RT3261_ANC_MD_1067MS (0x3 << 12)
1438 #define RT3261_ANC_SN_MASK (0x1 << 11)
1439 #define RT3261_ANC_SN_SFT 11
1440 #define RT3261_ANC_SN_DIS (0x0 << 11)
1441 #define RT3261_ANC_SN_EN (0x1 << 11)
1442 #define RT3261_ANC_CLK_MASK (0x1 << 10)
1443 #define RT3261_ANC_CLK_SFT 10
1444 #define RT3261_ANC_CLK_ANC (0x0 << 10)
1445 #define RT3261_ANC_CLK_REG (0x1 << 10)
1446 #define RT3261_ANC_ZCD_MASK (0x3 << 8)
1447 #define RT3261_ANC_ZCD_SFT 8
1448 #define RT3261_ANC_ZCD_DIS (0x0 << 8)
1449 #define RT3261_ANC_ZCD_T1 (0x1 << 8)
1450 #define RT3261_ANC_ZCD_T2 (0x2 << 8)
1451 #define RT3261_ANC_ZCD_WT (0x3 << 8)
1452 #define RT3261_ANC_CS_MASK (0x1 << 7)
1453 #define RT3261_ANC_CS_SFT 7
1454 #define RT3261_ANC_CS_DIS (0x0 << 7)
1455 #define RT3261_ANC_CS_EN (0x1 << 7)
1456 #define RT3261_ANC_SW_MASK (0x1 << 6)
1457 #define RT3261_ANC_SW_SFT 6
1458 #define RT3261_ANC_SW_NOR (0x0 << 6)
1459 #define RT3261_ANC_SW_AUTO (0x1 << 6)
1460 #define RT3261_ANC_CO_L_MASK (0x3f)
1461 #define RT3261_ANC_CO_L_SFT 0
1463 /* ANC Control 2 (0xb6) */
1464 #define RT3261_ANC_FG_R_MASK (0xf << 12)
1465 #define RT3261_ANC_FG_R_SFT 12
1466 #define RT3261_ANC_FG_L_MASK (0xf << 8)
1467 #define RT3261_ANC_FG_L_SFT 8
1468 #define RT3261_ANC_CG_R_MASK (0xf << 4)
1469 #define RT3261_ANC_CG_R_SFT 4
1470 #define RT3261_ANC_CG_L_MASK (0xf)
1471 #define RT3261_ANC_CG_L_SFT 0
1473 /* ANC Control 3 (0xb6) */
1474 #define RT3261_ANC_CD_MASK (0x1 << 6)
1475 #define RT3261_ANC_CD_SFT 6
1476 #define RT3261_ANC_CD_BOTH (0x0 << 6)
1477 #define RT3261_ANC_CD_IND (0x1 << 6)
1478 #define RT3261_ANC_CO_R_MASK (0x3f)
1479 #define RT3261_ANC_CO_R_SFT 0
1481 /* Jack Detect Control (0xbb) */
1482 #define RT3261_JD_MASK (0x7 << 13)
1483 #define RT3261_JD_SFT 13
1484 #define RT3261_JD_DIS (0x0 << 13)
1485 #define RT3261_JD_GPIO1 (0x1 << 13)
1486 #define RT3261_JD_JD1_IN4P (0x2 << 13)
1487 #define RT3261_JD_JD2_IN4N (0x3 << 13)
1488 #define RT3261_JD_GPIO2 (0x4 << 13)
1489 #define RT3261_JD_GPIO3 (0x5 << 13)
1490 #define RT3261_JD_GPIO4 (0x6 << 13)
1491 #define RT3261_JD_HP_MASK (0x1 << 11)
1492 #define RT3261_JD_HP_SFT 11
1493 #define RT3261_JD_HP_DIS (0x0 << 11)
1494 #define RT3261_JD_HP_EN (0x1 << 11)
1495 #define RT3261_JD_HP_TRG_MASK (0x1 << 10)
1496 #define RT3261_JD_HP_TRG_SFT 10
1497 #define RT3261_JD_HP_TRG_LO (0x0 << 10)
1498 #define RT3261_JD_HP_TRG_HI (0x1 << 10)
1499 #define RT3261_JD_SPL_MASK (0x1 << 9)
1500 #define RT3261_JD_SPL_SFT 9
1501 #define RT3261_JD_SPL_DIS (0x0 << 9)
1502 #define RT3261_JD_SPL_EN (0x1 << 9)
1503 #define RT3261_JD_SPL_TRG_MASK (0x1 << 8)
1504 #define RT3261_JD_SPL_TRG_SFT 8
1505 #define RT3261_JD_SPL_TRG_LO (0x0 << 8)
1506 #define RT3261_JD_SPL_TRG_HI (0x1 << 8)
1507 #define RT3261_JD_SPR_MASK (0x1 << 7)
1508 #define RT3261_JD_SPR_SFT 7
1509 #define RT3261_JD_SPR_DIS (0x0 << 7)
1510 #define RT3261_JD_SPR_EN (0x1 << 7)
1511 #define RT3261_JD_SPR_TRG_MASK (0x1 << 6)
1512 #define RT3261_JD_SPR_TRG_SFT 6
1513 #define RT3261_JD_SPR_TRG_LO (0x0 << 6)
1514 #define RT3261_JD_SPR_TRG_HI (0x1 << 6)
1515 #define RT3261_JD_MO_MASK (0x1 << 5)
1516 #define RT3261_JD_MO_SFT 5
1517 #define RT3261_JD_MO_DIS (0x0 << 5)
1518 #define RT3261_JD_MO_EN (0x1 << 5)
1519 #define RT3261_JD_MO_TRG_MASK (0x1 << 4)
1520 #define RT3261_JD_MO_TRG_SFT 4
1521 #define RT3261_JD_MO_TRG_LO (0x0 << 4)
1522 #define RT3261_JD_MO_TRG_HI (0x1 << 4)
1523 #define RT3261_JD_LO_MASK (0x1 << 3)
1524 #define RT3261_JD_LO_SFT 3
1525 #define RT3261_JD_LO_DIS (0x0 << 3)
1526 #define RT3261_JD_LO_EN (0x1 << 3)
1527 #define RT3261_JD_LO_TRG_MASK (0x1 << 2)
1528 #define RT3261_JD_LO_TRG_SFT 2
1529 #define RT3261_JD_LO_TRG_LO (0x0 << 2)
1530 #define RT3261_JD_LO_TRG_HI (0x1 << 2)
1531 #define RT3261_JD1_IN4P_MASK (0x1 << 1)
1532 #define RT3261_JD1_IN4P_SFT 1
1533 #define RT3261_JD1_IN4P_DIS (0x0 << 1)
1534 #define RT3261_JD1_IN4P_EN (0x1 << 1)
1535 #define RT3261_JD2_IN4N_MASK (0x1)
1536 #define RT3261_JD2_IN4N_SFT 0
1537 #define RT3261_JD2_IN4N_DIS (0x0)
1538 #define RT3261_JD2_IN4N_EN (0x1)
1540 /* Jack detect for ANC (0xbc) */
1541 #define RT3261_ANC_DET_MASK (0x3 << 4)
1542 #define RT3261_ANC_DET_SFT 4
1543 #define RT3261_ANC_DET_DIS (0x0 << 4)
1544 #define RT3261_ANC_DET_MB1 (0x1 << 4)
1545 #define RT3261_ANC_DET_MB2 (0x2 << 4)
1546 #define RT3261_ANC_DET_JD (0x3 << 4)
1547 #define RT3261_AD_TRG_MASK (0x1 << 3)
1548 #define RT3261_AD_TRG_SFT 3
1549 #define RT3261_AD_TRG_LO (0x0 << 3)
1550 #define RT3261_AD_TRG_HI (0x1 << 3)
1551 #define RT3261_ANCM_DET_MASK (0x3 << 4)
1552 #define RT3261_ANCM_DET_SFT 4
1553 #define RT3261_ANCM_DET_DIS (0x0 << 4)
1554 #define RT3261_ANCM_DET_MB1 (0x1 << 4)
1555 #define RT3261_ANCM_DET_MB2 (0x2 << 4)
1556 #define RT3261_ANCM_DET_JD (0x3 << 4)
1557 #define RT3261_AMD_TRG_MASK (0x1 << 3)
1558 #define RT3261_AMD_TRG_SFT 3
1559 #define RT3261_AMD_TRG_LO (0x0 << 3)
1560 #define RT3261_AMD_TRG_HI (0x1 << 3)
1562 /* IRQ Control 1 (0xbd) */
1563 #define RT3261_IRQ_JD_MASK (0x1 << 15)
1564 #define RT3261_IRQ_JD_SFT 15
1565 #define RT3261_IRQ_JD_BP (0x0 << 15)
1566 #define RT3261_IRQ_JD_NOR (0x1 << 15)
1567 #define RT3261_IRQ_OT_MASK (0x1 << 14)
1568 #define RT3261_IRQ_OT_SFT 14
1569 #define RT3261_IRQ_OT_BP (0x0 << 14)
1570 #define RT3261_IRQ_OT_NOR (0x1 << 14)
1571 #define RT3261_JD_STKY_MASK (0x1 << 13)
1572 #define RT3261_JD_STKY_SFT 13
1573 #define RT3261_JD_STKY_DIS (0x0 << 13)
1574 #define RT3261_JD_STKY_EN (0x1 << 13)
1575 #define RT3261_OT_STKY_MASK (0x1 << 12)
1576 #define RT3261_OT_STKY_SFT 12
1577 #define RT3261_OT_STKY_DIS (0x0 << 12)
1578 #define RT3261_OT_STKY_EN (0x1 << 12)
1579 #define RT3261_JD_P_MASK (0x1 << 11)
1580 #define RT3261_JD_P_SFT 11
1581 #define RT3261_JD_P_NOR (0x0 << 11)
1582 #define RT3261_JD_P_INV (0x1 << 11)
1583 #define RT3261_OT_P_MASK (0x1 << 10)
1584 #define RT3261_OT_P_SFT 10
1585 #define RT3261_OT_P_NOR (0x0 << 10)
1586 #define RT3261_OT_P_INV (0x1 << 10)
1588 /* IRQ Control 2 (0xbe) */
1589 #define RT3261_IRQ_MB1_OC_MASK (0x1 << 15)
1590 #define RT3261_IRQ_MB1_OC_SFT 15
1591 #define RT3261_IRQ_MB1_OC_BP (0x0 << 15)
1592 #define RT3261_IRQ_MB1_OC_NOR (0x1 << 15)
1593 #define RT3261_IRQ_MB2_OC_MASK (0x1 << 14)
1594 #define RT3261_IRQ_MB2_OC_SFT 14
1595 #define RT3261_IRQ_MB2_OC_BP (0x0 << 14)
1596 #define RT3261_IRQ_MB2_OC_NOR (0x1 << 14)
1597 #define RT3261_MB1_OC_STKY_MASK (0x1 << 11)
1598 #define RT3261_MB1_OC_STKY_SFT 11
1599 #define RT3261_MB1_OC_STKY_DIS (0x0 << 11)
1600 #define RT3261_MB1_OC_STKY_EN (0x1 << 11)
1601 #define RT3261_MB2_OC_STKY_MASK (0x1 << 10)
1602 #define RT3261_MB2_OC_STKY_SFT 10
1603 #define RT3261_MB2_OC_STKY_DIS (0x0 << 10)
1604 #define RT3261_MB2_OC_STKY_EN (0x1 << 10)
1605 #define RT3261_MB1_OC_P_MASK (0x1 << 7)
1606 #define RT3261_MB1_OC_P_SFT 7
1607 #define RT3261_MB1_OC_P_NOR (0x0 << 7)
1608 #define RT3261_MB1_OC_P_INV (0x1 << 7)
1609 #define RT3261_MB2_OC_P_MASK (0x1 << 6)
1610 #define RT3261_MB2_OC_P_SFT 6
1611 #define RT3261_MB2_OC_P_NOR (0x0 << 6)
1612 #define RT3261_MB2_OC_P_INV (0x1 << 6)
1613 #define RT3261_MB1_OC_CLR (0x1 << 3)
1614 #define RT3261_MB1_OC_CLR_SFT 3
1615 #define RT3261_MB2_OC_CLR (0x1 << 2)
1616 #define RT3261_MB2_OC_CLR_SFT 2
1618 /* GPIO Control 1 (0xc0) */
1619 #define RT3261_GP1_PIN_MASK (0x1 << 15)
1620 #define RT3261_GP1_PIN_SFT 15
1621 #define RT3261_GP1_PIN_GPIO1 (0x0 << 15)
1622 #define RT3261_GP1_PIN_IRQ (0x1 << 15)
1623 #define RT3261_GP2_PIN_MASK (0x1 << 14)
1624 #define RT3261_GP2_PIN_SFT 14
1625 #define RT3261_GP2_PIN_GPIO2 (0x0 << 14)
1626 #define RT3261_GP2_PIN_DMIC1_SCL (0x1 << 14)
1627 #define RT3261_GP3_PIN_MASK (0x3 << 12)
1628 #define RT3261_GP3_PIN_SFT 12
1629 #define RT3261_GP3_PIN_GPIO3 (0x0 << 12)
1630 #define RT3261_GP3_PIN_DMIC1_SDA (0x1 << 12)
1631 #define RT3261_GP3_PIN_IRQ (0x2 << 12)
1632 #define RT3261_GP4_PIN_MASK (0x1 << 11)
1633 #define RT3261_GP4_PIN_SFT 11
1634 #define RT3261_GP4_PIN_GPIO4 (0x0 << 11)
1635 #define RT3261_GP4_PIN_DMIC2_SDA (0x1 << 11)
1636 #define RT3261_DP_SIG_MASK (0x1 << 10)
1637 #define RT3261_DP_SIG_SFT 10
1638 #define RT3261_DP_SIG_TEST (0x0 << 10)
1639 #define RT3261_DP_SIG_AP (0x1 << 10)
1640 #define RT3261_GPIO_M_MASK (0x1 << 9)
1641 #define RT3261_GPIO_M_SFT 9
1642 #define RT3261_GPIO_M_FLT (0x0 << 9)
1643 #define RT3261_GPIO_M_PH (0x1 << 9)
1645 /* GPIO Control 3 (0xc2) */
1646 #define RT3261_GP4_PF_MASK (0x1 << 11)
1647 #define RT3261_GP4_PF_SFT 11
1648 #define RT3261_GP4_PF_IN (0x0 << 11)
1649 #define RT3261_GP4_PF_OUT (0x1 << 11)
1650 #define RT3261_GP4_OUT_MASK (0x1 << 10)
1651 #define RT3261_GP4_OUT_SFT 10
1652 #define RT3261_GP4_OUT_LO (0x0 << 10)
1653 #define RT3261_GP4_OUT_HI (0x1 << 10)
1654 #define RT3261_GP4_P_MASK (0x1 << 9)
1655 #define RT3261_GP4_P_SFT 9
1656 #define RT3261_GP4_P_NOR (0x0 << 9)
1657 #define RT3261_GP4_P_INV (0x1 << 9)
1658 #define RT3261_GP3_PF_MASK (0x1 << 8)
1659 #define RT3261_GP3_PF_SFT 8
1660 #define RT3261_GP3_PF_IN (0x0 << 8)
1661 #define RT3261_GP3_PF_OUT (0x1 << 8)
1662 #define RT3261_GP3_OUT_MASK (0x1 << 7)
1663 #define RT3261_GP3_OUT_SFT 7
1664 #define RT3261_GP3_OUT_LO (0x0 << 7)
1665 #define RT3261_GP3_OUT_HI (0x1 << 7)
1666 #define RT3261_GP3_P_MASK (0x1 << 6)
1667 #define RT3261_GP3_P_SFT 6
1668 #define RT3261_GP3_P_NOR (0x0 << 6)
1669 #define RT3261_GP3_P_INV (0x1 << 6)
1670 #define RT3261_GP2_PF_MASK (0x1 << 5)
1671 #define RT3261_GP2_PF_SFT 5
1672 #define RT3261_GP2_PF_IN (0x0 << 5)
1673 #define RT3261_GP2_PF_OUT (0x1 << 5)
1674 #define RT3261_GP2_OUT_MASK (0x1 << 4)
1675 #define RT3261_GP2_OUT_SFT 4
1676 #define RT3261_GP2_OUT_LO (0x0 << 4)
1677 #define RT3261_GP2_OUT_HI (0x1 << 4)
1678 #define RT3261_GP2_P_MASK (0x1 << 3)
1679 #define RT3261_GP2_P_SFT 3
1680 #define RT3261_GP2_P_NOR (0x0 << 3)
1681 #define RT3261_GP2_P_INV (0x1 << 3)
1682 #define RT3261_GP1_PF_MASK (0x1 << 2)
1683 #define RT3261_GP1_PF_SFT 2
1684 #define RT3261_GP1_PF_IN (0x0 << 2)
1685 #define RT3261_GP1_PF_OUT (0x1 << 2)
1686 #define RT3261_GP1_OUT_MASK (0x1 << 1)
1687 #define RT3261_GP1_OUT_SFT 1
1688 #define RT3261_GP1_OUT_LO (0x0 << 1)
1689 #define RT3261_GP1_OUT_HI (0x1 << 1)
1690 #define RT3261_GP1_P_MASK (0x1)
1691 #define RT3261_GP1_P_SFT 0
1692 #define RT3261_GP1_P_NOR (0x0)
1693 #define RT3261_GP1_P_INV (0x1)
1695 /* FM34-500 Register Control 1 (0xc4) */
1696 #define RT3261_DSP_ADD_SFT 0
1698 /* FM34-500 Register Control 2 (0xc5) */
1699 #define RT3261_DSP_DAT_SFT 0
1701 /* FM34-500 Register Control 3 (0xc6) */
1702 #define RT3261_DSP_BUSY_MASK (0x1 << 15)
1703 #define RT3261_DSP_BUSY_BIT 15
1704 #define RT3261_DSP_DS_MASK (0x1 << 14)
1705 #define RT3261_DSP_DS_SFT 14
1706 #define RT3261_DSP_DS_FM3010 (0x1 << 14)
1707 #define RT3261_DSP_DS_TEMP (0x1 << 14)
1708 #define RT3261_DSP_CLK_MASK (0x3 << 12)
1709 #define RT3261_DSP_CLK_SFT 12
1710 #define RT3261_DSP_CLK_384K (0x0 << 12)
1711 #define RT3261_DSP_CLK_192K (0x1 << 12)
1712 #define RT3261_DSP_CLK_96K (0x2 << 12)
1713 #define RT3261_DSP_CLK_64K (0x3 << 12)
1714 #define RT3261_DSP_PD_PIN_MASK (0x1 << 11)
1715 #define RT3261_DSP_PD_PIN_SFT 11
1716 #define RT3261_DSP_PD_PIN_LO (0x0 << 11)
1717 #define RT3261_DSP_PD_PIN_HI (0x1 << 11)
1718 #define RT3261_DSP_RST_PIN_MASK (0x1 << 10)
1719 #define RT3261_DSP_RST_PIN_SFT 10
1720 #define RT3261_DSP_RST_PIN_LO (0x0 << 10)
1721 #define RT3261_DSP_RST_PIN_HI (0x1 << 10)
1722 #define RT3261_DSP_R_EN (0x1 << 9)
1723 #define RT3261_DSP_W_EN (0x1 << 8)
1724 #define RT3261_DSP_CMD_MASK (0xff)
1725 #define RT3261_DSP_CMD_PE (0x0d) /* Patch Entry */
1726 #define RT3261_DSP_CMD_MW (0x3b) /* Memory Write */
1727 #define RT3261_DSP_CMD_MR (0x37) /* Memory Read */
1728 #define RT3261_DSP_CMD_RR (0x60) /* Register Read */
1729 #define RT3261_DSP_CMD_RW (0x68) /* Register Write */
1730 #define RT3261_DSP_REG_DATHI (0x26) /* High Data Addr */
1731 #define RT3261_DSP_REG_DATLO (0x25) /* Low Data Addr */
1733 /* Programmable Register Array Control 1 (0xc8) */
1734 #define RT3261_REG_SEQ_MASK (0xf << 12)
1735 #define RT3261_REG_SEQ_SFT 12
1736 #define RT3261_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1737 #define RT3261_SEQ1_ST_SFT 11
1738 #define RT3261_SEQ1_ST_RUN (0x0 << 11)
1739 #define RT3261_SEQ1_ST_FIN (0x1 << 11)
1740 #define RT3261_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1741 #define RT3261_SEQ2_ST_SFT 10
1742 #define RT3261_SEQ2_ST_RUN (0x0 << 10)
1743 #define RT3261_SEQ2_ST_FIN (0x1 << 10)
1744 #define RT3261_REG_LV_MASK (0x1 << 9)
1745 #define RT3261_REG_LV_SFT 9
1746 #define RT3261_REG_LV_MX (0x0 << 9)
1747 #define RT3261_REG_LV_PR (0x1 << 9)
1748 #define RT3261_SEQ_2_PT_MASK (0x1 << 8)
1749 #define RT3261_SEQ_2_PT_BIT 8
1750 #define RT3261_REG_IDX_MASK (0xff)
1751 #define RT3261_REG_IDX_SFT 0
1753 /* Programmable Register Array Control 2 (0xc9) */
1754 #define RT3261_REG_DAT_MASK (0xffff)
1755 #define RT3261_REG_DAT_SFT 0
1757 /* Programmable Register Array Control 3 (0xca) */
1758 #define RT3261_SEQ_DLY_MASK (0xff << 8)
1759 #define RT3261_SEQ_DLY_SFT 8
1760 #define RT3261_PROG_MASK (0x1 << 7)
1761 #define RT3261_PROG_SFT 7
1762 #define RT3261_PROG_DIS (0x0 << 7)
1763 #define RT3261_PROG_EN (0x1 << 7)
1764 #define RT3261_SEQ1_PT_RUN (0x1 << 6)
1765 #define RT3261_SEQ1_PT_RUN_BIT 6
1766 #define RT3261_SEQ2_PT_RUN (0x1 << 5)
1767 #define RT3261_SEQ2_PT_RUN_BIT 5
1769 /* Programmable Register Array Control 4 (0xcb) */
1770 #define RT3261_SEQ1_START_MASK (0xf << 8)
1771 #define RT3261_SEQ1_START_SFT 8
1772 #define RT3261_SEQ1_END_MASK (0xf)
1773 #define RT3261_SEQ1_END_SFT 0
1775 /* Programmable Register Array Control 5 (0xcc) */
1776 #define RT3261_SEQ2_START_MASK (0xf << 8)
1777 #define RT3261_SEQ2_START_SFT 8
1778 #define RT3261_SEQ2_END_MASK (0xf)
1779 #define RT3261_SEQ2_END_SFT 0
1781 /* Scramble Function (0xcd) */
1782 #define RT3261_SCB_KEY_MASK (0xff)
1783 #define RT3261_SCB_KEY_SFT 0
1785 /* Scramble Control (0xce) */
1786 #define RT3261_SCB_SWAP_MASK (0x1 << 15)
1787 #define RT3261_SCB_SWAP_SFT 15
1788 #define RT3261_SCB_SWAP_DIS (0x0 << 15)
1789 #define RT3261_SCB_SWAP_EN (0x1 << 15)
1790 #define RT3261_SCB_MASK (0x1 << 14)
1791 #define RT3261_SCB_SFT 14
1792 #define RT3261_SCB_DIS (0x0 << 14)
1793 #define RT3261_SCB_EN (0x1 << 14)
1795 /* Baseback Control (0xcf) */
1796 #define RT3261_BB_MASK (0x1 << 15)
1797 #define RT3261_BB_SFT 15
1798 #define RT3261_BB_DIS (0x0 << 15)
1799 #define RT3261_BB_EN (0x1 << 15)
1800 #define RT3261_BB_CT_MASK (0x7 << 12)
1801 #define RT3261_BB_CT_SFT 12
1802 #define RT3261_BB_CT_A (0x0 << 12)
1803 #define RT3261_BB_CT_B (0x1 << 12)
1804 #define RT3261_BB_CT_C (0x2 << 12)
1805 #define RT3261_BB_CT_D (0x3 << 12)
1806 #define RT3261_M_BB_L_MASK (0x1 << 9)
1807 #define RT3261_M_BB_L_SFT 9
1808 #define RT3261_M_BB_R_MASK (0x1 << 8)
1809 #define RT3261_M_BB_R_SFT 8
1810 #define RT3261_M_BB_HPF_L_MASK (0x1 << 7)
1811 #define RT3261_M_BB_HPF_L_SFT 7
1812 #define RT3261_M_BB_HPF_R_MASK (0x1 << 6)
1813 #define RT3261_M_BB_HPF_R_SFT 6
1814 #define RT3261_G_BB_BST_MASK (0x3f)
1815 #define RT3261_G_BB_BST_SFT 0
1817 /* MP3 Plus Control 1 (0xd0) */
1818 #define RT3261_M_MP3_L_MASK (0x1 << 15)
1819 #define RT3261_M_MP3_L_SFT 15
1820 #define RT3261_M_MP3_R_MASK (0x1 << 14)
1821 #define RT3261_M_MP3_R_SFT 14
1822 #define RT3261_M_MP3_MASK (0x1 << 13)
1823 #define RT3261_M_MP3_SFT 13
1824 #define RT3261_M_MP3_DIS (0x0 << 13)
1825 #define RT3261_M_MP3_EN (0x1 << 13)
1826 #define RT3261_EG_MP3_MASK (0x1f << 8)
1827 #define RT3261_EG_MP3_SFT 8
1828 #define RT3261_MP3_HLP_MASK (0x1 << 7)
1829 #define RT3261_MP3_HLP_SFT 7
1830 #define RT3261_MP3_HLP_DIS (0x0 << 7)
1831 #define RT3261_MP3_HLP_EN (0x1 << 7)
1832 #define RT3261_M_MP3_ORG_L_MASK (0x1 << 6)
1833 #define RT3261_M_MP3_ORG_L_SFT 6
1834 #define RT3261_M_MP3_ORG_R_MASK (0x1 << 5)
1835 #define RT3261_M_MP3_ORG_R_SFT 5
1837 /* MP3 Plus Control 2 (0xd1) */
1838 #define RT3261_MP3_WT_MASK (0x1 << 13)
1839 #define RT3261_MP3_WT_SFT 13
1840 #define RT3261_MP3_WT_1_4 (0x0 << 13)
1841 #define RT3261_MP3_WT_1_2 (0x1 << 13)
1842 #define RT3261_OG_MP3_MASK (0x1f << 8)
1843 #define RT3261_OG_MP3_SFT 8
1844 #define RT3261_HG_MP3_MASK (0x3f)
1845 #define RT3261_HG_MP3_SFT 0
1847 /* 3D HP Control 1 (0xd2) */
1848 #define RT3261_3D_CF_MASK (0x1 << 15)
1849 #define RT3261_3D_CF_SFT 15
1850 #define RT3261_3D_CF_DIS (0x0 << 15)
1851 #define RT3261_3D_CF_EN (0x1 << 15)
1852 #define RT3261_3D_HP_MASK (0x1 << 14)
1853 #define RT3261_3D_HP_SFT 14
1854 #define RT3261_3D_HP_DIS (0x0 << 14)
1855 #define RT3261_3D_HP_EN (0x1 << 14)
1856 #define RT3261_3D_BT_MASK (0x1 << 13)
1857 #define RT3261_3D_BT_SFT 13
1858 #define RT3261_3D_BT_DIS (0x0 << 13)
1859 #define RT3261_3D_BT_EN (0x1 << 13)
1860 #define RT3261_3D_1F_MIX_MASK (0x3 << 11)
1861 #define RT3261_3D_1F_MIX_SFT 11
1862 #define RT3261_3D_HP_M_MASK (0x1 << 10)
1863 #define RT3261_3D_HP_M_SFT 10
1864 #define RT3261_3D_HP_M_SUR (0x0 << 10)
1865 #define RT3261_3D_HP_M_FRO (0x1 << 10)
1866 #define RT3261_M_3D_HRTF_MASK (0x1 << 9)
1867 #define RT3261_M_3D_HRTF_SFT 9
1868 #define RT3261_M_3D_D2H_MASK (0x1 << 8)
1869 #define RT3261_M_3D_D2H_SFT 8
1870 #define RT3261_M_3D_D2R_MASK (0x1 << 7)
1871 #define RT3261_M_3D_D2R_SFT 7
1872 #define RT3261_M_3D_REVB_MASK (0x1 << 6)
1873 #define RT3261_M_3D_REVB_SFT 6
1875 /* Adjustable high pass filter control 1 (0xd3) */
1876 #define RT3261_2ND_HPF_MASK (0x1 << 15)
1877 #define RT3261_2ND_HPF_SFT 15
1878 #define RT3261_2ND_HPF_DIS (0x0 << 15)
1879 #define RT3261_2ND_HPF_EN (0x1 << 15)
1880 #define RT3261_HPF_CF_L_MASK (0x7 << 12)
1881 #define RT3261_HPF_CF_L_SFT 12
1882 #define RT3261_1ST_HPF_MASK (0x1 << 11)
1883 #define RT3261_1ST_HPF_SFT 11
1884 #define RT3261_1ST_HPF_DIS (0x0 << 11)
1885 #define RT3261_1ST_HPF_EN (0x1 << 11)
1886 #define RT3261_HPF_CF_R_MASK (0x7 << 8)
1887 #define RT3261_HPF_CF_R_SFT 8
1888 #define RT3261_ZD_T_MASK (0x3 << 6)
1889 #define RT3261_ZD_T_SFT 6
1890 #define RT3261_ZD_F_MASK (0x3 << 4)
1891 #define RT3261_ZD_F_SFT 4
1892 #define RT3261_ZD_F_IM (0x0 << 4)
1893 #define RT3261_ZD_F_ZC_IM (0x1 << 4)
1894 #define RT3261_ZD_F_ZC_IOD (0x2 << 4)
1895 #define RT3261_ZD_F_UN (0x3 << 4)
1897 /* HP calibration control and Amp detection (0xd6) */
1898 #define RT3261_SI_DAC_MASK (0x1 << 11)
1899 #define RT3261_SI_DAC_SFT 11
1900 #define RT3261_SI_DAC_AUTO (0x0 << 11)
1901 #define RT3261_SI_DAC_TEST (0x1 << 11)
1902 #define RT3261_DC_CAL_M_MASK (0x1 << 10)
1903 #define RT3261_DC_CAL_M_SFT 10
1904 #define RT3261_DC_CAL_M_CAL (0x0 << 10)
1905 #define RT3261_DC_CAL_M_NOR (0x1 << 10)
1906 #define RT3261_DC_CAL_MASK (0x1 << 9)
1907 #define RT3261_DC_CAL_SFT 9
1908 #define RT3261_DC_CAL_DIS (0x0 << 9)
1909 #define RT3261_DC_CAL_EN (0x1 << 9)
1910 #define RT3261_HPD_RCV_MASK (0x7 << 6)
1911 #define RT3261_HPD_RCV_SFT 6
1912 #define RT3261_HPD_PS_MASK (0x1 << 5)
1913 #define RT3261_HPD_PS_SFT 5
1914 #define RT3261_HPD_PS_DIS (0x0 << 5)
1915 #define RT3261_HPD_PS_EN (0x1 << 5)
1916 #define RT3261_CAL_M_MASK (0x1 << 4)
1917 #define RT3261_CAL_M_SFT 4
1918 #define RT3261_CAL_M_DEP (0x0 << 4)
1919 #define RT3261_CAL_M_CAL (0x1 << 4)
1920 #define RT3261_CAL_MASK (0x1 << 3)
1921 #define RT3261_CAL_SFT 3
1922 #define RT3261_CAL_DIS (0x0 << 3)
1923 #define RT3261_CAL_EN (0x1 << 3)
1924 #define RT3261_CAL_TEST_MASK (0x1 << 2)
1925 #define RT3261_CAL_TEST_SFT 2
1926 #define RT3261_CAL_TEST_DIS (0x0 << 2)
1927 #define RT3261_CAL_TEST_EN (0x1 << 2)
1928 #define RT3261_CAL_P_MASK (0x3)
1929 #define RT3261_CAL_P_SFT 0
1930 #define RT3261_CAL_P_NONE (0x0)
1931 #define RT3261_CAL_P_CAL (0x1)
1932 #define RT3261_CAL_P_DAC_CAL (0x2)
1934 /* Soft volume and zero cross control 1 (0xd9) */
1935 #define RT3261_SV_MASK (0x1 << 15)
1936 #define RT3261_SV_SFT 15
1937 #define RT3261_SV_DIS (0x0 << 15)
1938 #define RT3261_SV_EN (0x1 << 15)
1939 #define RT3261_SPO_SV_MASK (0x1 << 14)
1940 #define RT3261_SPO_SV_SFT 14
1941 #define RT3261_SPO_SV_DIS (0x0 << 14)
1942 #define RT3261_SPO_SV_EN (0x1 << 14)
1943 #define RT3261_OUT_SV_MASK (0x1 << 13)
1944 #define RT3261_OUT_SV_SFT 13
1945 #define RT3261_OUT_SV_DIS (0x0 << 13)
1946 #define RT3261_OUT_SV_EN (0x1 << 13)
1947 #define RT3261_HP_SV_MASK (0x1 << 12)
1948 #define RT3261_HP_SV_SFT 12
1949 #define RT3261_HP_SV_DIS (0x0 << 12)
1950 #define RT3261_HP_SV_EN (0x1 << 12)
1951 #define RT3261_ZCD_DIG_MASK (0x1 << 11)
1952 #define RT3261_ZCD_DIG_SFT 11
1953 #define RT3261_ZCD_DIG_DIS (0x0 << 11)
1954 #define RT3261_ZCD_DIG_EN (0x1 << 11)
1955 #define RT3261_ZCD_MASK (0x1 << 10)
1956 #define RT3261_ZCD_SFT 10
1957 #define RT3261_ZCD_PD (0x0 << 10)
1958 #define RT3261_ZCD_PU (0x1 << 10)
1959 #define RT3261_M_ZCD_MASK (0x3f << 4)
1960 #define RT3261_M_ZCD_SFT 4
1961 #define RT3261_M_ZCD_RM_L (0x1 << 9)
1962 #define RT3261_M_ZCD_RM_R (0x1 << 8)
1963 #define RT3261_M_ZCD_SM_L (0x1 << 7)
1964 #define RT3261_M_ZCD_SM_R (0x1 << 6)
1965 #define RT3261_M_ZCD_OM_L (0x1 << 5)
1966 #define RT3261_M_ZCD_OM_R (0x1 << 4)
1967 #define RT3261_SV_DLY_MASK (0xf)
1968 #define RT3261_SV_DLY_SFT 0
1970 /* Soft volume and zero cross control 2 (0xda) */
1971 #define RT3261_ZCD_HP_MASK (0x1 << 15)
1972 #define RT3261_ZCD_HP_SFT 15
1973 #define RT3261_ZCD_HP_DIS (0x0 << 15)
1974 #define RT3261_ZCD_HP_EN (0x1 << 15)
1977 /* Codec Private Register definition */
1978 /* 3D Speaker Control (0x63) */
1979 #define RT3261_3D_SPK_MASK (0x1 << 15)
1980 #define RT3261_3D_SPK_SFT 15
1981 #define RT3261_3D_SPK_DIS (0x0 << 15)
1982 #define RT3261_3D_SPK_EN (0x1 << 15)
1983 #define RT3261_3D_SPK_M_MASK (0x3 << 13)
1984 #define RT3261_3D_SPK_M_SFT 13
1985 #define RT3261_3D_SPK_CG_MASK (0x1f << 8)
1986 #define RT3261_3D_SPK_CG_SFT 8
1987 #define RT3261_3D_SPK_SG_MASK (0x1f)
1988 #define RT3261_3D_SPK_SG_SFT 0
1990 /* Wind Noise Detection Control 1 (0x6c) */
1991 #define RT3261_WND_MASK (0x1 << 15)
1992 #define RT3261_WND_SFT 15
1993 #define RT3261_WND_DIS (0x0 << 15)
1994 #define RT3261_WND_EN (0x1 << 15)
1996 /* Wind Noise Detection Control 2 (0x6d) */
1997 #define RT3261_WND_FC_NW_MASK (0x3f << 10)
1998 #define RT3261_WND_FC_NW_SFT 10
1999 #define RT3261_WND_FC_WK_MASK (0x3f << 4)
2000 #define RT3261_WND_FC_WK_SFT 4
2002 /* Wind Noise Detection Control 3 (0x6e) */
2003 #define RT3261_HPF_FC_MASK (0x3f << 6)
2004 #define RT3261_HPF_FC_SFT 6
2005 #define RT3261_WND_FC_ST_MASK (0x3f)
2006 #define RT3261_WND_FC_ST_SFT 0
2008 /* Wind Noise Detection Control 4 (0x6f) */
2009 #define RT3261_WND_TH_LO_MASK (0x3ff)
2010 #define RT3261_WND_TH_LO_SFT 0
2012 /* Wind Noise Detection Control 5 (0x70) */
2013 #define RT3261_WND_TH_HI_MASK (0x3ff)
2014 #define RT3261_WND_TH_HI_SFT 0
2016 /* Wind Noise Detection Control 8 (0x73) */
2017 #define RT3261_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2018 #define RT3261_WND_WIND_SFT 13
2019 #define RT3261_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2020 #define RT3261_WND_STRONG_SFT 12
2027 /* Dipole Speaker Interface (0x75) */
2028 #define RT3261_DP_ATT_MASK (0x3 << 14)
2029 #define RT3261_DP_ATT_SFT 14
2030 #define RT3261_DP_SPK_MASK (0x1 << 10)
2031 #define RT3261_DP_SPK_SFT 10
2032 #define RT3261_DP_SPK_DIS (0x0 << 10)
2033 #define RT3261_DP_SPK_EN (0x1 << 10)
2035 /* EQ Pre Volume Control (0xb3) */
2036 #define RT3261_EQ_PRE_VOL_MASK (0xffff)
2037 #define RT3261_EQ_PRE_VOL_SFT 0
2039 /* EQ Post Volume Control (0xb4) */
2040 #define RT3261_EQ_PST_VOL_MASK (0xffff)
2041 #define RT3261_EQ_PST_VOL_SFT 0
2043 /* General Control1 (0xfa) */
2044 #define RT3261_LOUT_DF_MASK (0x1 << 14)
2045 #define RT3261_LOUT_DF 14
2046 #define RT3261_M_MAMIX_L (0x1 << 13)
2047 #define RT3261_M_MAMIX_R (0x1 << 12)
2049 /* General Control2 (0xfb) */
2050 #define RT3261_RXDC_SRC_MASK (0x1 << 7)
2051 #define RT3261_RXDC_SRC_STO (0x0 << 7)
2052 #define RT3261_RXDC_SRC_MONO (0x1 << 7)
2053 #define RT3261_RXDC_SRC_SFT (7)
2054 #define RT3261_RXDP2_SEL_MASK (0x1 << 3)
2055 #define RT3261_RXDP2_SEL_IF2 (0x0 << 3)
2056 #define RT3261_RXDP2_SEL_ADC (0x1 << 3)
2057 #define RT3261_RXDP2_SEL_SFT (3)
2060 /* Vendor ID (0xfd) */
2061 #define RT3261_VER_C 0x2
2062 #define RT3261_VER_D 0x3
2065 /* Volume Rescale */
2066 #define RT3261_VOL_RSCL_MAX 0x27
2067 #define RT3261_VOL_RSCL_RANGE 0x1F
2068 #define RT3261_HP_VOL_RSCL_RANGE 0x19
2069 /* Debug String Length */
2070 #define RT3261_REG_DISP_LEN 10
2072 #define RT3261_NO_JACK BIT(0)
2073 #define RT3261_HEADSET_DET BIT(1)
2074 #define RT3261_HEADPHO_DET BIT(2)
2076 /* System Clock Source */
2080 RT3261_SCLK_S_RCCLK,
2086 RT3261_PLL1_S_BCLK1,
2087 RT3261_PLL1_S_BCLK2,
2088 RT3261_PLL1_S_BCLK3,
2098 #define RT3261_U_IF1 (0x1)
2099 #define RT3261_U_IF2 (0x1 << 1)
2100 #define RT3261_U_IF3 (0x1 << 2)
2125 struct rt3261_pll_code {
2126 bool m_bp; /* Indicates bypass m code or not. */
2132 struct rt3261_priv {
2133 struct i2c_client *i2c;
2134 struct snd_soc_codec *codec;
2135 struct delayed_work patch_work;
2140 int lrck[RT3261_AIFS];
2141 int bclk[RT3261_AIFS];
2142 int master[RT3261_AIFS];
2150 int dsp_sw; /* expected parameter setting */
2156 unsigned int modem_is_open;
2157 unsigned int spk_num;
2158 unsigned int modem_input_mode;
2159 unsigned int lout_to_modem_mode;
2160 unsigned int spk_amplify;
2161 unsigned int playback_if1_data_control;
2162 unsigned int playback_if2_data_control;
2165 int rt3261_conn_mux_path(struct snd_soc_codec *codec,
2166 char *widget_name, char *path_name);
2168 int rt3261_headset_mic_detect(int jack_insert);
2170 #endif /* __RT3261_H__ */