2 * rt5621.h -- RT5621 ALSA SoC audio driver
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 #define RT5621_RESET 0X00 //RESET CODEC TO DEFAULT
16 #define RT5621_SPK_OUT_VOL 0X02 //SPEAKER OUT VOLUME
17 #define RT5621_HP_OUT_VOL 0X04 //HEADPHONE OUTPUT VOLUME
18 #define RT5621_MONO_AUX_OUT_VOL 0X06 //MONO OUTPUT/AUXOUT VOLUME
19 #define RT5621_AUXIN_VOL 0X08 //AUXIN VOLUME
20 #define RT5621_LINE_IN_VOL 0X0A //LINE IN VOLUME
21 #define RT5621_STEREO_DAC_VOL 0X0C //STEREO DAC VOLUME
22 #define RT5621_MIC_VOL 0X0E //MICROPHONE VOLUME
23 #define RT5621_MIC_ROUTING_CTRL 0X10 //MIC ROUTING CONTROL
24 #define RT5621_ADC_REC_GAIN 0X12 //ADC RECORD GAIN
25 #define RT5621_ADC_REC_MIXER 0X14 //ADC RECORD MIXER CONTROL
26 #define RT5621_SOFT_VOL_CTRL_TIME 0X16 //SOFT VOLUME CONTROL TIME
27 #define RT5621_OUTPUT_MIXER_CTRL 0X1C //OUTPUT MIXER CONTROL
28 #define RT5621_MIC_CTRL 0X22 //MICROPHONE CONTROL
29 #define RT5621_AUDIO_INTERFACE 0X34 //AUDIO INTERFACE
30 #define RT5621_STEREO_AD_DA_CLK_CTRL 0X36 //STEREO AD/DA CLOCK CONTROL
31 #define RT5621_COMPANDING_CTRL 0X38 //COMPANDING CONTROL
32 #define RT5621_PWR_MANAG_ADD1 0X3A //POWER MANAGMENT ADDITION 1
33 #define RT5621_PWR_MANAG_ADD2 0X3C //POWER MANAGMENT ADDITION 2
34 #define RT5621_PWR_MANAG_ADD3 0X3E //POWER MANAGMENT ADDITION 3
35 #define RT5621_ADD_CTRL_REG 0X40 //ADDITIONAL CONTROL REGISTER
36 #define RT5621_GLOBAL_CLK_CTRL_REG 0X42 //GLOBAL CLOCK CONTROL REGISTER
37 #define RT5621_PLL_CTRL 0X44 //PLL CONTROL
38 #define RT5621_GPIO_OUTPUT_PIN_CTRL 0X4A //GPIO OUTPUT PIN CONTROL
39 #define RT5621_GPIO_PIN_CONFIG 0X4C //GPIO PIN CONFIGURATION
40 #define RT5621_GPIO_PIN_POLARITY 0X4E //GPIO PIN POLARITY/TYPE
41 #define RT5621_GPIO_PIN_STICKY 0X50 //GPIO PIN STICKY
42 #define RT5621_GPIO_PIN_WAKEUP 0X52 //GPIO PIN WAKE UP
43 #define RT5621_GPIO_PIN_STATUS 0X54 //GPIO PIN STATUS
44 #define RT5621_GPIO_PIN_SHARING 0X56 //GPIO PIN SHARING
45 #define RT5621_OVER_TEMP_CURR_STATUS 0X58 //OVER TEMPERATURE AND CURRENT STATUS
46 #define RT5621_JACK_DET_CTRL 0X5A //JACK DETECT CONTROL REGISTER
47 #define RT5621_MISC_CTRL 0X5E //MISC CONTROL
48 #define RT5621_PSEDUEO_SPATIAL_CTRL 0X60 //PSEDUEO STEREO & SPATIAL EFFECT BLOCK CONTROL
49 #define RT5621_EQ_CTRL 0X62 //EQ CONTROL
50 #define RT5621_EQ_MODE_ENABLE 0X66 //EQ MODE CHANGE ENABLE
51 #define RT5621_AVC_CTRL 0X68 //AVC CONTROL
52 #define RT5621_HID_CTRL_INDEX 0X6A //HIDDEN CONTROL INDEX PORT
53 #define RT5621_HID_CTRL_DATA 0X6C //HIDDEN CONTROL DATA PORT
54 #define RT5621_VENDOR_ID1 0x7C //VENDOR ID1
55 #define RT5621_VENDOR_ID2 0x7E //VENDOR ID2
59 #define RT_L_MUTE (0x1<<15) //MUTE LEFT CONTROL BIT
60 #define RT_L_ZC (0x1<<14) //LEFT ZERO CROSS CONTROL BIT
61 #define RT_L_SM (0x1<<13) //LEFT SOFTMUTE CONTROL BIT
62 #define RT_R_MUTE (0x1<<7) //MUTE RIGHT CONTROL BIT
63 #define RT_R_ZC (0x1<<6) //RIGHT ZERO CROSS CONTROL BIT
64 #define RT_R_SM (0x1<<5) //RIGHT SOFTMUTE CONTROL BIT
65 #define RT_M_HP_MIXER (0x1<<15) //Mute source to HP Mixer
66 #define RT_M_SPK_MIXER (0x1<<14) //Mute source to Speaker Mixer
67 #define RT_M_MONO_MIXER (0x1<<13) //Mute source to Mono Mixer
68 #define SPK_CLASS_AB 0
71 //Mic Routing Control(0x10)
72 #define M_MIC1_TO_HP_MIXER (0x1<<15) //Mute MIC1 to HP mixer
73 #define M_MIC1_TO_SPK_MIXER (0x1<<14) //Mute MiC1 to SPK mixer
74 #define M_MIC1_TO_MONO_MIXER (0x1<<13) //Mute MIC1 to MONO mixer
75 #define MIC1_DIFF_INPUT_CTRL (0x1<<12) //MIC1 different input control
76 #define M_MIC2_TO_HP_MIXER (0x1<<7) //Mute MIC2 to HP mixer
77 #define M_MIC2_TO_SPK_MIXER (0x1<<6) //Mute MiC2 to SPK mixer
78 #define M_MIC2_TO_MONO_MIXER (0x1<<5) //Mute MIC2 to MONO mixer
79 #define MIC2_DIFF_INPUT_CTRL (0x1<<4) //MIC2 different input control
81 //ADC Record Gain(0x12)
82 #define M_ADC_L_TO_HP_MIXER (0x1<<15) //Mute left of ADC to HP Mixer
83 #define M_ADC_R_TO_HP_MIXER (0x1<<14) //Mute right of ADC to HP Mixer
84 #define M_ADC_L_TO_MONO_MIXER (0x1<<13) //Mute left of ADC to MONO Mixer
85 #define M_ADC_R_TO_MONO_MIXER (0x1<<12) //Mute right of ADC to MONO Mixer
86 #define ADC_L_GAIN_MASK (0x1f<<7) //ADC Record Gain Left channel Mask
87 #define ADC_L_ZC_DET (0x1<<6) //ADC Zero-Cross Detector Control
88 #define ADC_R_ZC_DET (0x1<<5) //ADC Zero-Cross Detector Control
89 #define ADC_R_GAIN_MASK (0x1f<<0) //ADC Record Gain Right channel Mask
91 //ADC Input Mixer Control(0x14)
92 #define M_MIC1_TO_ADC_L_MIXER (0x1<<14) //Mute mic1 to left channel of ADC mixer
93 #define M_MIC2_TO_ADC_L_MIXER (0x1<<13) //Mute mic2 to left channel of ADC mixer
94 #define M_LINEIN_L_TO_ADC_L_MIXER (0x1<<12) //Mute line In left channel to left channel of ADC mixer
95 #define M_AUXIN_L_TO_ADC_L_MIXER (0x1<<11) //Mute aux In left channel to left channel of ADC mixer
96 #define M_HPMIXER_L_TO_ADC_L_MIXER (0x1<<10) //Mute HP mixer left channel to left channel of ADC mixer
97 #define M_SPKMIXER_L_TO_ADC_L_MIXER (0x1<<9) //Mute SPK mixer left channel to left channel of ADC mixer
98 #define M_MONOMIXER_L_TO_ADC_L_MIXER (0x1<<8) //Mute MONO mixer left channel to left channel of ADC mixer
99 #define M_MIC1_TO_ADC_R_MIXER (0x1<<6) //Mute mic1 to right channel of ADC mixer
100 #define M_MIC2_TO_ADC_R_MIXER (0x1<<5) //Mute mic2 to right channel of ADC mixer
101 #define M_LINEIN_R_TO_ADC_R_MIXER (0x1<<4) //Mute lineIn right channel to right channel of ADC mixer
102 #define M_AUXIN_R_TO_ADC_R_MIXER (0x1<<3) //Mute aux In right channel to right channel of ADC mixer
103 #define M_HPMIXER_R_TO_ADC_R_MIXER (0x1<<2) //Mute HP mixer right channel to right channel of ADC mixer
104 #define M_SPKMIXER_R_TO_ADC_R_MIXER (0x1<<1) //Mute SPK mixer right channel to right channel of ADC mixer
105 #define M_MONOMIXER_R_TO_ADC_R_MIXER (0x1<<0) //Mute MONO mixer right channel to right channel of ADC mixer
107 //Output Mixer Control(0x1C)
108 #define SPKOUT_N_SOUR_MASK (0x3<<14)
109 #define SPKOUT_N_SOUR_LN (0x2<<14)
110 #define SPKOUT_N_SOUR_RP (0x1<<14)
111 #define SPKOUT_N_SOUR_RN (0x0<<14)
112 #define SPK_OUTPUT_CLASS_AB (0x0<<13)
113 #define SPK_OUTPUT_CLASS_D (0x1<<13)
114 #define SPK_CLASS_AB_S_AMP (0x0<<12)
115 #define SPK_CALSS_AB_W_AMP (0x1<<12)
116 #define SPKOUT_INPUT_SEL_MASK (0x3<<10)
117 #define SPKOUT_INPUT_SEL_MONOMIXER (0x3<<10)
118 #define SPKOUT_INPUT_SEL_SPKMIXER (0x2<<10)
119 #define SPKOUT_INPUT_SEL_HPMIXER (0x1<<10)
120 #define SPKOUT_INPUT_SEL_VMID (0x0<<10)
121 #define HPL_INPUT_SEL_HPLMIXER (0x1<<9)
122 #define HPR_INPUT_SEL_HPRMIXER (0x1<<8)
123 #define MONO_AUX_INPUT_SEL_MASK (0x3<<6)
124 #define MONO_AUX_INPUT_SEL_MONO (0x3<<6)
125 #define MONO_AUX_INPUT_SEL_SPK (0x2<<6)
126 #define MONO_AUX_INPUT_SEL_HP (0x1<<6)
127 #define MONO_AUX_INPUT_SEL_VMID (0x0<<6)
129 //Micphone Control define(0x22)
132 #define MIC_BIAS_90_PRECNET_AVDD 1
133 #define MIC_BIAS_75_PRECNET_AVDD 2
135 #define MIC1_BOOST_CTRL_MASK (0x3<<10)
136 #define MIC1_BOOST_CTRL_BYPASS (0x0<<10)
137 #define MIC1_BOOST_CTRL_20DB (0x1<<10)
138 #define MIC1_BOOST_CTRL_30DB (0x2<<10)
139 #define MIC1_BOOST_CTRL_40DB (0x3<<10)
141 #define MIC2_BOOST_CTRL_MASK (0x3<<8)
142 #define MIC2_BOOST_CTRL_BYPASS (0x0<<8)
143 #define MIC2_BOOST_CTRL_20DB (0x1<<8)
144 #define MIC2_BOOST_CTRL_30DB (0x2<<8)
145 #define MIC2_BOOST_CTRL_40DB (0x3<<8)
147 #define MICBIAS_VOLT_CTRL_MASK (0x1<<5)
148 #define MICBIAS_VOLT_CTRL_90P (0x0<<5)
149 #define MICBIAS_VOLT_CTRL_75P (0x1<<5)
151 #define MICBIAS_SHORT_CURR_DET_MASK (0x3)
152 #define MICBIAS_SHORT_CURR_DET_600UA (0x0)
153 #define MICBIAS_SHORT_CURR_DET_1200UA (0x1)
154 #define MICBIAS_SHORT_CURR_DET_1800UA (0x2)
156 //Audio Interface(0x34)
157 #define SDP_MASTER_MODE (0x0<<15) //Main I2S interface select Master mode
158 #define SDP_SLAVE_MODE (0x1<<15) //Main I2S interface select Slave mode
159 #define I2S_PCM_MODE (0x1<<14) //PCM 0:mode A ,1:mode B
160 #define MAIN_I2S_BCLK_POL_CTRL (0x1<<7) //0:Normal 1:Invert
161 #define ADC_DATA_L_R_SWAP (0x1<<5) //0:ADC data appear at left phase of LRCK
162 //1:ADC data appear at right phase of LRCK
163 #define DAC_DATA_L_R_SWAP (0x1<<4) //0:DAC data appear at left phase of LRCK
164 //1:DAC data appear at right phase of LRCK
165 //Data Length Slection
166 #define I2S_DL_MASK (0x3<<2) //main i2s Data Length mask
167 #define I2S_DL_16 (0x0<<2) //16 bits
168 #define I2S_DL_20 (0x1<<2) //20 bits
169 #define I2S_DL_24 (0x2<<2) //24 bits
170 #define I2S_DL_32 (0x3<<2) //32 bits
172 //PCM Data Format Selection
173 #define I2S_DF_MASK (0x3) //main i2s Data Format mask
174 #define I2S_DF_I2S (0x0) //I2S FORMAT
175 #define I2S_DF_RIGHT (0x1) //RIGHT JUSTIFIED format
176 #define I2S_DF_LEFT (0x2) //LEFT JUSTIFIED format
177 #define I2S_DF_PCM (0x3) //PCM format
179 //Stereo AD/DA Clock Control(0x36h)
180 #define I2S_PRE_DIV_MASK (0x7<<12)
181 #define I2S_PRE_DIV_1 (0x0<<12) //DIV 1
182 #define I2S_PRE_DIV_2 (0x1<<12) //DIV 2
183 #define I2S_PRE_DIV_4 (0x2<<12) //DIV 4
184 #define I2S_PRE_DIV_8 (0x3<<12) //DIV 8
185 #define I2S_PRE_DIV_16 (0x4<<12) //DIV 16
186 #define I2S_PRE_DIV_32 (0x5<<12) //DIV 32
188 #define I2S_SCLK_DIV_MASK (0x7<<9)
189 #define I2S_SCLK_DIV_1 (0x0<<9) //DIV 1
190 #define I2S_SCLK_DIV_2 (0x1<<9) //DIV 2
191 #define I2S_SCLK_DIV_3 (0x2<<9) //DIV 3
192 #define I2S_SCLK_DIV_4 (0x3<<9) //DIV 4
193 #define I2S_SCLK_DIV_6 (0x4<<9) //DIV 6
194 #define I2S_SCLK_DIV_8 (0x5<<9) //DIV 8
195 #define I2S_SCLK_DIV_12 (0x6<<9) //DIV 12
196 #define I2S_SCLK_DIV_16 (0x7<<9) //DIV 16
198 #define I2S_WCLK_DIV_PRE_MASK (0xF<<5)
199 #define I2S_WCLK_PRE_DIV_1 (0x0<<5) //DIV 1
200 #define I2S_WCLK_PRE_DIV_2 (0x1<<5) //DIV 2
201 #define I2S_WCLK_PRE_DIV_3 (0x2<<5) //DIV 3
202 #define I2S_WCLK_PRE_DIV_4 (0x3<<5) //DIV 4
203 #define I2S_WCLK_PRE_DIV_5 (0x4<<5) //DIV 5
204 #define I2S_WCLK_PRE_DIV_6 (0x5<<5) //DIV 6
205 #define I2S_WCLK_PRE_DIV_7 (0x6<<5) //DIV 7
206 #define I2S_WCLK_PRE_DIV_8 (0x7<<5) //DIV 8
207 //........................
209 #define I2S_WCLK_DIV_MASK (0x7<<2)
210 #define I2S_WCLK_DIV_2 (0x0<<2) //DIV 2
211 #define I2S_WCLK_DIV_4 (0x1<<2) //DIV 4
212 #define I2S_WCLK_DIV_8 (0x2<<2) //DIV 8
213 #define I2S_WCLK_DIV_16 (0x3<<2) //DIV 16
214 #define I2S_WCLK_DIV_32 (0x4<<2) //DIV 32
216 #define ADDA_FILTER_CLK_SEL_256FS (0<<1) //256FS
217 #define ADDA_FILTER_CLK_SEL_384FS (1<<1) //384FS
219 #define ADDA_OSR_SEL_64FS (0) //64FS
220 #define ADDA_OSR_SEL_128FS (1) //128FS
222 //Power managment addition 1 (0x3A),0:Disable,1:Enable
223 #define PWR_MAIN_I2S_EN (0x1<<15)
224 #define PWR_ZC_DET_PD_EN (0x1<<14)
225 #define PWR_MIC1_BIAS_EN (0x1<<11)
226 #define PWR_SHORT_CURR_DET_EN (0x1<<10)
227 #define PWR_SOFTGEN_EN (0x1<<8)
228 #define PWR_DEPOP_BUF_HP (0x1<<6)
229 #define PWR_HP_OUT_AMP (0x1<<5)
230 #define PWR_HP_OUT_ENH_AMP (0x1<<4)
231 #define PWR_DEPOP_BUF_AUX (0x1<<2)
232 #define PWR_AUX_OUT_AMP (0x1<<1)
233 #define PWR_AUX_OUT_ENH_AMP (0x1)
236 //Power managment addition 2(0x3C),0:Disable,1:Enable
237 #define PWR_CLASS_AB (0x1<<15)
238 #define PWR_CLASS_D (0x1<<14)
239 #define PWR_VREF (0x1<<13)
240 #define PWR_PLL (0x1<<12)
241 #define PWR_DAC_REF_CIR (0x1<<10)
242 #define PWR_L_DAC_CLK (0x1<<9)
243 #define PWR_R_DAC_CLK (0x1<<8)
244 #define PWR_L_ADC_CLK_GAIN (0x1<<7)
245 #define PWR_R_ADC_CLK_GAIN (0x1<<6)
246 #define PWR_L_HP_MIXER (0x1<<5)
247 #define PWR_R_HP_MIXER (0x1<<4)
248 #define PWR_SPK_MIXER (0x1<<3)
249 #define PWR_MONO_MIXER (0x1<<2)
250 #define PWR_L_ADC_REC_MIXER (0x1<<1)
251 #define PWR_R_ADC_REC_MIXER (0x1)
253 //Power managment addition 3(0x3E),0:Disable,1:Enable
254 #define PWR_MAIN_BIAS (0x1<<15)
255 #define PWR_AUXOUT_L_VOL_AMP (0x1<<14)
256 #define PWR_AUXOUT_R_VOL_AMP (0x1<<13)
257 #define PWR_SPK_OUT (0x1<<12)
258 #define PWR_HP_L_OUT_VOL (0x1<<10)
259 #define PWR_HP_R_OUT_VOL (0x1<<9)
260 #define PWR_LINEIN_L_VOL (0x1<<7)
261 #define PWR_LINEIN_R_VOL (0x1<<6)
262 #define PWR_AUXIN_L_VOL (0x1<<5)
263 #define PWR_AUXIN_R_VOL (0x1<<4)
264 #define PWR_MIC1_FUN_CTRL (0x1<<3)
265 #define PWR_MIC2_FUN_CTRL (0x1<<2)
266 #define PWR_MIC1_BOOST_MIXER (0x1<<1)
267 #define PWR_MIC2_BOOST_MIXER (0x1)
270 //Additional Control Register(0x40)
271 #define AUXOUT_SEL_DIFF (0x1<<15) //Differential Mode
272 #define AUXOUT_SEL_SE (0x1<<15) //Single-End Mode
274 #define SPK_AB_AMP_CTRL_MASK (0x7<<12)
275 #define SPK_AB_AMP_CTRL_RATIO_225 (0x0<<12) //2.25 Vdd
276 #define SPK_AB_AMP_CTRL_RATIO_200 (0x1<<12) //2.00 Vdd
277 #define SPK_AB_AMP_CTRL_RATIO_175 (0x2<<12) //1.75 Vdd
278 #define SPK_AB_AMP_CTRL_RATIO_150 (0x3<<12) //1.50 Vdd
279 #define SPK_AB_AMP_CTRL_RATIO_125 (0x4<<12) //1.25 Vdd
280 #define SPK_AB_AMP_CTRL_RATIO_100 (0x5<<12) //1.00 Vdd
282 #define SPK_D_AMP_CTRL_MASK (0x3<<10)
283 #define SPK_D_AMP_CTRL_RATIO_175 (0x0<<10) //1.75 Vdd
284 #define SPK_D_AMP_CTRL_RATIO_150 (0x1<<10) //1.50 Vdd
285 #define SPK_D_AMP_CTRL_RATIO_125 (0x2<<10) //1.25 Vdd
286 #define SPK_D_AMP_CTRL_RATIO_100 (0x3<<10) //1.00 Vdd
288 #define STEREO_DAC_HI_PASS_FILTER_EN (0x1<<9) //Stereo DAC high pass filter enable
289 #define STEREO_ADC_HI_PASS_FILTER_EN (0x1<<8) //Stereo ADC high pass filter enable
291 #define DIG_VOL_BOOST_MASK (0x3<<4) //Digital volume Boost mask
292 #define DIG_VOL_BOOST_0DB (0x0<<4) //Digital volume Boost 0DB
293 #define DIG_VOL_BOOST_6DB (0x1<<4) //Digital volume Boost 6DB
294 #define DIG_VOL_BOOST_12DB (0x2<<4) //Digital volume Boost 12DB
295 #define DIG_VOL_BOOST_18DB (0x3<<4) //Digital volume Boost 18DB
298 //Global Clock Control Register(0x42)
299 #define SYSCLK_SOUR_SEL_MASK (0x1<<15)
300 #define SYSCLK_SOUR_SEL_MCLK (0x0<<15) //system Clock source from MCLK
301 #define SYSCLK_SOUR_SEL_PLL (0x1<<15) //system Clock source from PLL
302 #define PLLCLK_SOUR_SEL_MCLK (0x0<<14) //PLL clock source from MCLK
303 #define PLLCLK_SOUR_SEL_BITCLK (0x1<<14) //PLL clock source from BITCLK
305 #define PLLCLK_DIV_RATIO_MASK (0x3<<1)
306 #define PLLCLK_DIV_RATIO_DIV1 (0x0<<1) //DIV 1
307 #define PLLCLK_DIV_RATIO_DIV2 (0x1<<1) //DIV 2
308 #define PLLCLK_DIV_RATIO_DIV4 (0x2<<1) //DIV 4
309 #define PLLCLK_DIV_RATIO_DIV8 (0x3<<1) //DIV 8
311 #define PLLCLK_PRE_DIV1 (0x0) //DIV 1
312 #define PLLCLK_PRE_DIV2 (0x1) //DIV 2
316 #define PLL_CTRL_M_VAL(m) ((m)&0xf)
317 #define PLL_CTRL_K_VAL(k) (((k)&0x7)<<4)
318 #define PLL_CTRL_N_VAL(n) (((n)&0xff)<<8)
320 //GPIO Pin Configuration(0x4C)
321 #define GPIO_PIN_MASK (0x1<<1)
322 #define GPIO_PIN_SET_INPUT (0x1<<1)
323 #define GPIO_PIN_SET_OUTPUT (0x0<<1)
326 #define LINEIN_L_PIN_SHARING (0x1<<15)
327 #define LINEIN_L_PIN_AS_LINEIN_L (0x0<<15)
328 #define LINEIN_L_PIN_AS_JD1 (0x1<<15)
330 #define LINEIN_R_PIN_SHARING (0x1<<14)
331 #define LINEIN_R_PIN_AS_LINEIN_R (0x0<<14)
332 #define LINEIN_R_PIN_AS_JD2 (0x1<<14)
334 #define GPIO_PIN_SHARING (0x3)
335 #define GPIO_PIN_AS_GPIO (0x0)
336 #define GPIO_PIN_AS_IRQOUT (0x1)
337 #define GPIO_PIN_AS_PLLOUT (0x3)
339 //Jack Detect Control Register(0x5A)
340 #define JACK_DETECT_MASK (0x3<<14)
341 #define JACK_DETECT_USE_JD2 (0x3<<14)
342 #define JACK_DETECT_USE_JD1 (0x2<<14)
343 #define JACK_DETECT_USE_GPIO (0x1<<14)
344 #define JACK_DETECT_OFF (0x0<<14)
346 #define SPK_EN_IN_HI (0x1<<11)
347 #define AUX_R_EN_IN_HI (0x1<<10)
348 #define AUX_L_EN_IN_HI (0x1<<9)
349 #define HP_EN_IN_HI (0x1<<8)
350 #define SPK_EN_IN_LO (0x1<<7)
351 #define AUX_R_EN_IN_LO (0x1<<6)
352 #define AUX_L_EN_IN_LO (0x1<<5)
353 #define HP_EN_IN_LO (0x1<<4)
355 ////MISC CONTROL(0x5E)
356 #define DISABLE_FAST_VREG (0x1<<15)
357 #define SPK_CLASS_AB_OC_PD (0x1<<13)
358 #define SPK_CLASS_AB_OC_DET (0x1<<12)
359 #define HP_DEPOP_MODE3_EN (0x1<<10)
360 #define HP_DEPOP_MODE2_EN (0x1<<9)
361 #define HP_DEPOP_MODE1_EN (0x1<<8)
362 #define AUXOUT_DEPOP_MODE3_EN (0x1<<6)
363 #define AUXOUT_DEPOP_MODE2_EN (0x1<<5)
364 #define AUXOUT_DEPOP_MODE1_EN (0x1<<4)
365 #define M_DAC_L_INPUT (0x1<<3)
366 #define M_DAC_R_INPUT (0x1<<2)
367 #define IRQOUT_INV_CTRL (0x1<<0)
369 //Psedueo Stereo & Spatial Effect Block Control(0x60)
370 #define SPATIAL_CTRL_EN (0x1<<15)
371 #define ALL_PASS_FILTER_EN (0x1<<14)
372 #define PSEUDO_STEREO_EN (0x1<<13)
373 #define STEREO_EXPENSION_EN (0x1<<12)
375 #define GAIN_3D_PARA_L_MASK (0x7<<9)
376 #define GAIN_3D_PARA_L_1_00 (0x0<<9)
377 #define GAIN_3D_PARA_L_1_25 (0x1<<9)
378 #define GAIN_3D_PARA_L_1_50 (0x2<<9)
379 #define GAIN_3D_PARA_L_1_75 (0x3<<9)
380 #define GAIN_3D_PARA_L_2_00 (0x4<<9)
382 #define GAIN_3D_PARA_R_MASK (0x7<<6)
383 #define GAIN_3D_PARA_R_1_00 (0x0<<6)
384 #define GAIN_3D_PARA_R_1_25 (0x1<<6)
385 #define GAIN_3D_PARA_R_1_50 (0x2<<6)
386 #define GAIN_3D_PARA_R_1_75 (0x3<<6)
387 #define GAIN_3D_PARA_R_2_00 (0x4<<6)
389 #define RATIO_3D_L_MASK (0x3<<4)
390 #define RATIO_3D_L_0_0 (0x0<<4)
391 #define RATIO_3D_L_0_66 (0x1<<4)
392 #define RATIO_3D_L_1_0 (0x2<<4)
394 #define RATIO_3D_R_MASK (0x3<<2)
395 #define RATIO_3D_R_0_0 (0x0<<2)
396 #define RATIO_3D_R_0_66 (0x1<<2)
397 #define RATIO_3D_R_1_0 (0x2<<2)
399 #define APF_MASK (0x3)
400 #define APF_FOR_48K (0x3)
401 #define APF_FOR_44_1K (0x2)
402 #define APF_FOR_32K (0x1)
406 #define EN_HW_EQ_BLK (0x1<<15) //HW EQ block control
407 #define EN_HW_EQ_HPF_MODE (0x1<<14) //High Frequency shelving filter mode
408 #define EN_HW_EQ_SOUR (0x1<<11) //0:DAC PATH,1:ADC PATH
409 #define EN_HW_EQ_HPF (0x1<<4) //EQ High Pass Filter Control
410 #define EN_HW_EQ_BP3 (0x1<<3) //EQ Band-3 Control
411 #define EN_HW_EQ_BP2 (0x1<<2) //EQ Band-2 Control
412 #define EN_HW_EQ_BP1 (0x1<<1) //EQ Band-1 Control
413 #define EN_HW_EQ_LPF (0x1<<0) //EQ Low Pass Filter Control
415 //EQ Mode Change Enable(0x66)
416 #define EQ_HPF_CHANGE_EN (0x1<<4) //EQ High Pass Filter Mode Change Enable
417 #define EQ_BP3_CHANGE_EN (0x1<<3) //EQ Band-3 Pass Filter Mode Change Enable
418 #define EQ_BP2_CHANGE_EN (0x1<<2) //EQ Band-2 Pass Filter Mode Change Enable
419 #define EQ_BP1_CHANGE_EN (0x1<<1) //EQ Band-1 Pass Filter Mode Change Enable
420 #define EQ_LPF_CHANGE_EN (0x1<<0) //EQ Low Pass Filter Mode Change Enable
424 #define AVC_ENABLE (0x1<<15)
425 #define AVC_TARTGET_SEL_MASK (0x1<<14)
426 #define AVC_TARTGET_SEL_R (0x1<<14)
427 #define AVC_TARTGET_SEL_L (0x0<<14)
430 #define RT5621_PLL_FR_MCLK 0
431 #define RT5621_PLL_FR_BCLK 1
434 #define REALTEK_HWDEP 0
436 //WaveOut channel for realtek codec
439 RT_WAVOUT_SPK =(0x1<<0),
440 RT_WAVOUT_SPK_R =(0x1<<1),
441 RT_WAVOUT_SPK_L =(0x1<<2),
442 RT_WAVOUT_HP =(0x1<<3),
443 RT_WAVOUT_HP_R =(0x1<<4),
444 RT_WAVOUT_HP_L =(0x1<<5),
445 RT_WAVOUT_MONO =(0x1<<6),
446 RT_WAVOUT_AUXOUT =(0x1<<7),
447 RT_WAVOUT_AUXOUT_R =(0x1<<8),
448 RT_WAVOUT_AUXOUT_L =(0x1<<9),
449 RT_WAVOUT_LINEOUT =(0x1<<10),
450 RT_WAVOUT_LINEOUT_R =(0x1<<11),
451 RT_WAVOUT_LINEOUT_L =(0x1<<12),
452 RT_WAVOUT_DAC =(0x1<<13),
453 RT_WAVOUT_ALL_ON =(0x1<<14),
456 //WaveIn channel for realtek codec
459 RT_WAVIN_R_MONO_MIXER =(0x1<<0),
460 RT_WAVIN_R_SPK_MIXER =(0x1<<1),
461 RT_WAVIN_R_HP_MIXER =(0x1<<2),
462 RT_WAVIN_R_PHONE =(0x1<<3),
463 RT_WAVIN_R_AUXIN =(0x1<<3),
464 RT_WAVIN_R_LINE_IN =(0x1<<4),
465 RT_WAVIN_R_MIC2 =(0x1<<5),
466 RT_WAVIN_R_MIC1 =(0x1<<6),
468 RT_WAVIN_L_MONO_MIXER =(0x1<<8),
469 RT_WAVIN_L_SPK_MIXER =(0x1<<9),
470 RT_WAVIN_L_HP_MIXER =(0x1<<10),
471 RT_WAVIN_L_PHONE =(0x1<<11),
472 RT_WAVIN_L_AUXIN =(0x1<<11),
473 RT_WAVIN_L_LINE_IN =(0x1<<12),
474 RT_WAVIN_L_MIC2 =(0x1<<13),
475 RT_WAVIN_L_MIC1 =(0x1<<14),
482 POWER_STATE_D1_PLAYBACK,
483 POWER_STATE_D1_RECORD,
485 POWER_STATE_D2_PLAYBACK,
486 POWER_STATE_D2_RECORD,
494 struct rt56xx_reg_state
496 unsigned int reg_index;
497 unsigned int reg_value;
503 struct rt56xx_reg_state __user *buf;
508 RT_READ_CODEC_REG_IOCTL = _IOR('R', 0x01, struct rt56xx_cmd),
509 RT_READ_ALL_CODEC_REG_IOCTL = _IOR('R', 0x02, struct rt56xx_cmd),
510 RT_WRITE_CODEC_REG_IOCTL = _IOW('R', 0x03, struct rt56xx_cmd),
515 #endif /* __RT5621_H__ */