2 * rt5625.h -- RT5625 ALSA SoC audio driver
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 #define RT5625_RESET 0x00
16 #define RT5625_SPK_OUT_VOL 0x02
17 #define RT5625_HP_OUT_VOL 0x04
18 #define RT5625_AUX_OUT_VOL 0x06
19 #define RT5625_PHONEIN_VOL 0x08
20 #define RT5625_LINE_IN_VOL 0x0a
21 #define RT5625_DAC_VOL 0x0c
22 #define RT5625_MIC_VOL 0x0e
23 #define RT5625_DAC_MIC_CTRL 0x10
24 #define RT5625_ADC_REC_GAIN 0x12
25 #define RT5625_ADC_REC_MIXER 0x14
26 #define RT5625_VDAC_OUT_VOL 0x18
27 #define RT5625_VODSP_PDM_CTL 0x1a
28 #define RT5625_OUTMIX_CTRL 0x1c
29 #define RT5625_VODSP_CTL 0x1e
30 #define RT5625_MIC_CTRL 0x22
31 #define RT5625_DMIC_CTRL 0x24
32 #define RT5625_PD_CTRL 0x26
33 #define RT5625_F_DAC_ADC_VDAC 0x2e
34 #define RT5625_SDP_CTRL 0x34
35 #define RT5625_EXT_SDP_CTRL 0x36
36 #define RT5625_PWR_ADD1 0x3a
37 #define RT5625_PWR_ADD2 0x3c
38 #define RT5625_PWR_ADD3 0x3e
39 #define RT5625_GEN_CTRL1 0x40
40 #define RT5625_GEN_CTRL2 0x42
41 #define RT5625_PLL_CTRL 0x44
42 #define RT5625_PLL2_CTRL 0x46
43 #define RT5625_LDO_CTRL 0x48
44 #define RT5625_GPIO_CONFIG 0x4c
45 #define RT5625_GPIO_POLAR 0x4e
46 #define RT5625_GPIO_STICKY 0x50
47 #define RT5625_GPIO_WAKEUP 0x52
48 #define RT5625_GPIO_STATUS 0x54
49 #define RT5625_GPIO_SHARING 0x56
50 #define RT5625_OTC_STATUS 0x58
51 #define RT5625_SOFT_VOL_CTRL 0x5a
52 #define RT5625_GPIO_OUT_CTRL 0x5c
53 #define RT5625_MISC_CTRL 0x5e
54 #define RT5625_DAC_CLK_CTRL1 0x60
55 #define RT5625_DAC_CLK_CTRL2 0x62
56 #define RT5625_VDAC_CLK_CTRL1 0x64
57 #define RT5625_PS_CTRL 0x68
58 #define RT5625_PRIV_INDEX 0x6a
59 #define RT5625_PRIV_DATA 0x6c
60 #define RT5625_EQ_CTRL 0x6e
61 #define RT5625_DSP_ADDR 0x70
62 #define RT5625_DSP_DATA 0x72
63 #define RT5625_DSP_CMD 0x74
64 #define RT5625_VENDOR_ID1 0x7c
65 #define RT5625_VENDOR_ID2 0x7e
67 /* global definition */
68 #define RT5625_L_MUTE (0x1 << 15)
69 #define RT5625_L_MUTE_SFT 15
70 #define RT5625_L_ZC (0x1 << 14)
71 #define RT5625_L_VOL_MASK (0x1f << 8)
72 #define RT5625_L_HVOL_MASK (0x3f << 8)
73 #define RT5625_L_VOL_SFT 8
74 #define RT5625_R_MUTE (0x1 << 7)
75 #define RT5625_R_MUTE_SFT 7
76 #define RT5625_R_ZC (0x1 << 6)
77 #define RT5625_R_VOL_MASK (0x1f)
78 #define RT5625_R_HVOL_MASK (0x3f)
79 #define RT5625_R_VOL_SFT 0
80 #define RT5625_M_HPMIX (0x1 << 15)
81 #define RT5625_M_SPKMIX (0x1 << 14)
82 #define RT5625_M_MONOMIX (0x1 << 13)
84 /* Phone Input (0x08) */
85 #define RT5625_M_PHO_HM (0x1 << 15)
86 #define RT5625_M_PHO_HM_SFT 15
87 #define RT5625_M_PHO_SM (0x1 << 14)
88 #define RT5625_M_PHO_SM_SFT 14
89 #define RT5625_PHO_DIFF (0x1 << 13)
90 #define RT5625_PHO_DIFF_SFT 13
91 #define RT5625_PHO_DIFF_DIS (0x0 << 13)
92 #define RT5625_PHO_DIFF_EN (0x1 << 13)
94 /* Linein Volume (0x0a) */
95 #define RT5625_M_LI_HM (0x1 << 15)
96 #define RT5625_M_LI_HM_SFT 15
97 #define RT5625_M_LI_SM (0x1 << 14)
98 #define RT5625_M_LI_SM_SFT 14
99 #define RT5625_M_LI_MM (0x1 << 13)
100 #define RT5625_M_LI_MM_SFT 13
102 /* MIC Input Volume (0x0e) */
103 #define RT5625_MIC1_DIFF_MASK (0x1 << 15)
104 #define RT5625_MIC1_DIFF_SFT 15
105 #define RT5625_MIC1_DIFF_DIS (0x0 << 15)
106 #define RT5625_MIC1_DIFF_EN (0x1 << 15)
107 #define RT5625_MIC2_DIFF_MASK (0x1 << 7)
108 #define RT5625_MIC2_DIFF_SFT 7
109 #define RT5625_MIC2_DIFF_DIS (0x0 << 7)
110 #define RT5625_MIC2_DIFF_EN (0x1 << 7)
112 /* Stereo DAC and MIC Routing Control (0x10) */
113 #define RT5625_M_MIC1_HM (0x1 << 15)
114 #define RT5625_M_MIC1_HM_SFT 15
115 #define RT5625_M_MIC1_SM (0x1 << 14)
116 #define RT5625_M_MIC1_SM_SFT 14
117 #define RT5625_M_MIC1_MM (0x1 << 13)
118 #define RT5625_M_MIC1_MM_SFT 13
119 #define RT5625_M_MIC2_HM (0x1 << 11)
120 #define RT5625_M_MIC2_HM_SFT 11
121 #define RT5625_M_MIC2_SM (0x1 << 10)
122 #define RT5625_M_MIC2_SM_SFT 10
123 #define RT5625_M_MIC2_MM (0x1 << 9)
124 #define RT5625_M_MIC2_MM_SFT 9
125 #define RT5625_M_DACL_HM (0x1 << 3)
126 #define RT5625_M_DACL_HM_SFT 3
127 #define RT5625_M_DACR_HM (0x1 << 2)
128 #define RT5625_M_DACR_HM_SFT 2
129 #define RT5625_M_DAC_SM (0x1 << 1)
130 #define RT5625_M_DAC_SM_SFT 1
131 #define RT5625_M_DAC_MM (0x1)
132 #define RT5625_M_DAC_MM_SFT 0
134 /* ADC Record Gain (0x12) */
135 #define RT5625_M_ADCL_HM (0x1 << 15)
136 #define RT5625_M_ADCL_HM_SFT 15
137 #define RT5625_M_ADCL_MM (0x1 << 14)
138 #define RT5625_M_ADCL_MM_SFT 14
139 #define RT5625_ADCL_ZCD (0x1 << 13)
140 #define RT5625_G_ADCL_MASK (0x1f << 8)
141 #define RT5625_M_ADCR_HM (0x1 << 7)
142 #define RT5625_M_ADCR_HM_SFT 7
143 #define RT5625_M_ADCR_MM (0x1 << 6)
144 #define RT5625_M_ADCR_MM_SFT 6
145 #define RT5625_ADCR_ZCD (0x1 << 5)
146 #define RT5625_G_ADCR_MASK (0x1f)
148 /* ADC Record Mixer Control (0x14) */
149 #define RT5625_M_RM_L_MIC1 (0x1 << 14)
150 #define RT5625_M_RM_L_MIC1_SFT 14
151 #define RT5625_M_RM_L_MIC2 (0x1 << 13)
152 #define RT5625_M_RM_L_MIC2_SFT 13
153 #define RT5625_M_RM_L_LINE (0x1 << 12)
154 #define RT5625_M_RM_L_LINE_SFT 12
155 #define RT5625_M_RM_L_PHO (0x1 << 11)
156 #define RT5625_M_RM_L_PHO_SFT 11
157 #define RT5625_M_RM_L_HM (0x1 << 10)
158 #define RT5625_M_RM_L_HM_SFT 10
159 #define RT5625_M_RM_L_SM (0x1 << 9)
160 #define RT5625_M_RM_L_SM_SFT 9
161 #define RT5625_M_RM_L_MM (0x1 << 8)
162 #define RT5625_M_RM_L_MM_SFT 8
163 #define RT5625_M_RM_R_MIC1 (0x1 << 6)
164 #define RT5625_M_RM_R_MIC1_SFT 6
165 #define RT5625_M_RM_R_MIC2 (0x1 << 5)
166 #define RT5625_M_RM_R_MIC2_SFT 5
167 #define RT5625_M_RM_R_LINE (0x1 << 4)
168 #define RT5625_M_RM_R_LINE_SFT 4
169 #define RT5625_M_RM_R_PHO (0x1 << 3)
170 #define RT5625_M_RM_R_PHO_SFT 3
171 #define RT5625_M_RM_R_HM (0x1 << 2)
172 #define RT5625_M_RM_R_HM_SFT 2
173 #define RT5625_M_RM_R_SM (0x1 << 1)
174 #define RT5625_M_RM_R_SM_SFT 1
175 #define RT5625_M_RM_R_MM (0x1)
176 #define RT5625_M_RM_R_MM_SFT 0
178 /* Voice DAC Volume (0x18) */
179 #define RT5625_M_VDAC_HM (0x1 << 15)
180 #define RT5625_M_VDAC_HM_SFT 15
181 #define RT5625_M_VDAC_SM (0x1 << 14)
182 #define RT5625_M_VDAC_SM_SFT 14
183 #define RT5625_M_VDAC_MM (0x1 << 13)
184 #define RT5625_M_VDAC_MM_SFT 13
186 /* AEC & PDM Control (0x1a) */
187 #define RT5625_SRC1_PWR (0x1 << 15)
188 #define RT5625_SRC1_PWR_SFT 15
189 #define RT5625_SRC2_PWR (0x1 << 13)
190 #define RT5625_SRC2_PWR_SFT 13
191 #define RT5625_SRC2_S_MASK (0x1 << 12)
192 #define RT5625_SRC2_S_SFT 12
193 #define RT5625_SRC2_S_TXDP (0x0 << 12)
194 #define RT5625_SRC2_S_TXDC (0x1 << 12)
195 #define RT5625_RXDP_PWR (0x1 << 11)
196 #define RT5625_RXDP_PWR_SFT 11
197 #define RT5625_RXDP_S_MASK (0x3 << 9)
198 #define RT5625_RXDP_S_SFT 9
199 #define RT5625_RXDP_S_SRC1 (0x0 << 9)
200 #define RT5625_RXDP_S_ADCL (0x1 << 9)
201 #define RT5625_RXDP_S_VOICE (0x2 << 9)
202 #define RT5625_RXDP_S_ADCR (0x3 << 9)
203 #define RT5625_RXDC_PWR (0x1 << 8)
204 #define RT5625_RXDC_PWR_SFT 8
205 #define RT5625_PCM_S_MASK (0x1 << 7)
206 #define RT5625_PCM_S_SFT 7
207 #define RT5625_PCM_S_ADCR (0x0 << 7)
208 #define RT5625_PCM_S_TXDP (0x1 << 7)
209 #define RT5625_REC_IIS_S_MASK (0x3 << 4)
210 #define RT5625_REC_IIS_S_SFT 4
211 #define RT5625_REC_IIS_S_ADC (0x0 << 4)
212 #define RT5625_REC_IIS_S_VOICE (0x1 << 4)
213 #define RT5625_REC_IIS_S_SRC2 (0x2 << 4)
215 /* Output Mixer Control (0x1c) */
216 #define RT5625_SPKN_S_MASK (0x3 << 14)
217 #define RT5625_SPKN_S_SFT 14
218 #define RT5625_SPKN_S_LN (0x2 << 14)
219 #define RT5625_SPKN_S_RP (0x1 << 14)
220 #define RT5625_SPKN_S_RN (0x0 << 14)
221 #define RT5625_SPK_T_MASK (0x1 << 13)
222 #define RT5625_SPK_T_SFT 13
223 #define RT5625_SPK_T_CLS_D (0x1 << 13)
224 #define RT5625_SPK_T_CLS_AB (0x0 << 13)
225 #define RT5625_CLS_AB_MASK (0x1 << 12)
226 #define RT5625_CLS_AB_SFT 12
227 #define RT5625_CLS_AB_S_AMP (0x0 << 12)
228 #define RT5625_CLS_AB_W_AMP (0x1 << 12)
229 #define RT5625_SPKVOL_S_MASK (0x3 << 10)
230 #define RT5625_SPKVOL_S_SFT 10
231 #define RT5625_SPKVOL_S_MM (0x3 << 10)
232 #define RT5625_SPKVOL_S_SM (0x2 << 10)
233 #define RT5625_SPKVOL_S_HM (0x1 << 10)
234 #define RT5625_SPKVOL_S_VMID (0x0 << 10)
235 #define RT5625_HPVOL_L_S_MASK (0x1 << 9)
236 #define RT5625_HPVOL_L_S_SFT 9
237 #define RT5625_HPVOL_L_S_HM (0x1 << 9)
238 #define RT5625_HPVOL_L_S_VMID (0x0 << 9)
239 #define RT5625_HPVOL_R_S_MASK (0x1 << 8)
240 #define RT5625_HPVOL_R_S_SFT 8
241 #define RT5625_HPVOL_R_S_HM (0x1 << 8)
242 #define RT5625_HPVOL_R_S_VMID (0x0 << 8)
243 #define RT5625_AUXVOL_S_MASK (0x3 << 6)
244 #define RT5625_AUXVOL_S_SFT 6
245 #define RT5625_AUXVOL_S_MM (0x3 << 6)
246 #define RT5625_AUXVOL_S_SM (0x2 << 6)
247 #define RT5625_AUXVOL_S_HM (0x1 << 6)
248 #define RT5625_AUXVOL_S_VMID (0x0 << 6)
249 #define RT5625_AUXOUT_MODE (0x1 << 4)
250 #define RT5625_AUXOUT_MODE_SFT 4
251 #define RT5625_DACL_HP_MASK (0x1 << 1)
252 #define RT5625_DACL_HP_SFT 1
253 #define RT5625_DACL_HP_MUTE (0x0 << 1)
254 #define RT5625_DACL_HP_ON (0x1 << 1)
255 #define RT5625_DACR_HP_MASK (0x1)
256 #define RT5625_DACR_HP_SFT 0
257 #define RT5625_DACR_HP_MUTE (0x0)
258 #define RT5625_DACR_HP_ON (0x1)
260 /* VoDSP Control (0x1e) */
261 #define RT5625_DSP_SCLK_S_MASK (0x1 << 15)
262 #define RT5625_DSP_SCLK_S_SFT 15
263 #define RT5625_DSP_SCLK_S_MCLK (0x0 << 15)
264 #define RT5625_DSP_SCLK_S_VCLK (0x1 << 15)
265 #define RT5625_DSP_LRCK_MASK (0x1 << 13)
266 #define RT5625_DSP_LRCK_SFT 13
267 #define RT5625_DSP_LRCK_8K (0x0 << 13)
268 #define RT5625_DSP_LRCK_16K (0x1 << 13)
269 #define RT5625_DSP_TP_MASK (0x1 << 3)
270 #define RT5625_DSP_TP_SFT 3
271 #define RT5625_DSP_TP_NOR (0x0 << 3)
272 #define RT5625_DSP_TP_TEST (0x1 << 3)
273 #define RT5625_DSP_BP_MASK (0x1 << 2)
274 #define RT5625_DSP_BP_SFT 2
275 #define RT5625_DSP_BP_EN (0x0 << 2)
276 #define RT5625_DSP_BP_NOR (0x1 << 2)
277 #define RT5625_DSP_PD_MASK (0x1 << 1)
278 #define RT5625_DSP_PD_SFT 1
279 #define RT5625_DSP_PD_EN (0x0 << 1)
280 #define RT5625_DSP_PD_NOR (0x1 << 1)
281 #define RT5625_DSP_RST_MASK (0x1)
282 #define RT5625_DSP_RST_SFT 0
283 #define RT5625_DSP_RST_EN (0x0)
284 #define RT5625_DSP_RST_NOR (0x1)
286 /* Microphone Control (0x22) */
287 #define RT5625_MIC1_BST_MASK (0x3 << 10)
288 #define RT5625_MIC1_BST_SFT 10
289 #define RT5625_MIC1_BST_BYPASS (0x0 << 10)
290 #define RT5625_MIC1_BST_20DB (0x1 << 10)
291 #define RT5625_MIC1_BST_30DB (0x2 << 10)
292 #define RT5625_MIC1_BST_40DB (0x3 << 10)
293 #define RT5625_MIC2_BST_MASK (0x3 << 8)
294 #define RT5625_MIC2_BST_SFT 8
295 #define RT5625_MIC2_BST_BYPASS (0x0 << 8)
296 #define RT5625_MIC2_BST_20DB (0x1 << 8)
297 #define RT5625_MIC2_BST_30DB (0x2 << 8)
298 #define RT5625_MIC2_BST_40DB (0x3 << 8)
299 #define RT5625_MB1_OV_MASK (0x1 << 5)
300 #define RT5625_MB1_OV_90P (0x0 << 5)
301 #define RT5625_MB1_OV_75P (0x1 << 5)
302 #define RT5625_MB2_OV_MASK (0x1 << 4)
303 #define RT5625_MB2_OV_90P (0x0 << 4)
304 #define RT5625_MB2_OV_75P (0x1 << 4)
305 #define RT5625_SCD_THD_MASK (0x3)
306 #define RT5625_SCD_THD_600UA (0x0)
307 #define RT5625_SCD_THD_1500UA (0x1)
308 #define RT5625_SCD_THD_2000UA (0x2)
310 /* Digital Boost Control (0x24) */
311 #define RT5625_DIG_BST_MASK (0x7)
312 #define RT5625_DIG_BST_SFT 0
314 /* Power Down Control/Status (0x26) */
315 #define RT5625_PWR_PR7 (0x1 << 15)
316 #define RT5625_PWR_PR6 (0x1 << 14)
317 #define RT5625_PWR_PR5 (0x1 << 13)
318 #define RT5625_PWR_PR3 (0x1 << 11)
319 #define RT5625_PWR_PR2 (0x1 << 10)
320 #define RT5625_PWR_PR1 (0x1 << 9)
321 #define RT5625_PWR_PR0 (0x1 << 8)
322 #define RT5625_PWR_REF_ST (0x1 << 3)
323 #define RT5625_PWR_AM_ST (0x1 << 2)
324 #define RT5625_PWR_DAC_ST (0x1 << 1)
325 #define RT5625_PWR_ADC_ST (0x1)
327 /* Stereo DAC/Voice DAC/Stereo ADC Function Select (0x2e) */
328 #define RT5625_DAC_F_MASK (0x3 << 12)
329 #define RT5625_DAC_F_SFT 12
330 #define RT5625_DAC_F_DAC (0x0 << 12)
331 #define RT5625_DAC_F_SRC2 (0x1 << 12)
332 #define RT5625_DAC_F_TXDP (0x2 << 12)
333 #define RT5625_DAC_F_TXDC (0x3 << 12)
334 #define RT5625_VDAC_S_MASK (0x7 << 8)
335 #define RT5625_VDAC_S_SFT 8
336 #define RT5625_VDAC_S_VOICE (0x0 << 8)
337 #define RT5625_VDAC_S_SRC2 (0x1 << 8)
338 #define RT5625_VDAC_S_TXDP (0x2 << 8)
339 #define RT5625_VDAC_S_TXDC (0x3 << 8)
340 #define RT5625_ADCR_F_MASK (0x3 << 4)
341 #define RT5625_ADCR_F_SFT 4
342 #define RT5625_ADCR_F_ADC (0x0 << 4)
343 #define RT5625_ADCR_F_VADC (0x1 << 4)
344 #define RT5625_ADCR_F_DSP (0x2 << 4)
345 #define RT5625_ADCR_F_PDM (0x3 << 4)
346 #define RT5625_ADCL_F_MASK (0x1)
347 #define RT5625_ADCL_F_SFT 0
348 #define RT5625_ADCL_F_ADC (0x0)
349 #define RT5625_ADCL_F_DSP (0x1)
351 /* Main Serial Data Port Control (Stereo IIS) (0x34) */
352 #define RT5625_I2S_M_MASK (0x1 << 15)
353 #define RT5625_I2S_M_SFT 15
354 #define RT5625_I2S_M_MST (0x0 << 15)
355 #define RT5625_I2S_M_SLV (0x1 << 15)
356 #define RT5625_I2S_SAD_MASK (0x1 << 14)
357 #define RT5625_I2S_SAD_SFT 14
358 #define RT5625_I2S_SAD_DIS (0x0 << 14)
359 #define RT5625_I2S_SAD_EN (0x1 << 14)
360 #define RT5625_I2S_S_MASK (0x1 << 8)
361 #define RT5625_I2S_S_SFT 8
362 #define RT5625_I2S_S_MSCLK (0x0 << 8)
363 #define RT5625_I2S_S_VSCLK (0x1 << 8)
364 #define RT5625_I2S_BP_MASK (0x1 << 7)
365 #define RT5625_I2S_BP_SFT 7
366 #define RT5625_I2S_BP_NOR (0x0 << 7)
367 #define RT5625_I2S_BP_INV (0x1 << 7)
368 #define RT5625_I2S_LRCK_MASK (0x1 << 6)
369 #define RT5625_I2S_LRCK_SFT 6
370 #define RT5625_I2S_LRCK_NOR (0x0 << 6)
371 #define RT5625_I2S_LRCK_INV (0x1 << 6)
372 #define RT5625_I2S_DL_MASK (0x3 << 2)
373 #define RT5625_I2S_DL_SFT 2
374 #define RT5625_I2S_DL_16 (0x0 << 2)
375 #define RT5625_I2S_DL_20 (0x1 << 2)
376 #define RT5625_I2S_DL_24 (0x2 << 2)
377 #define RT5625_I2S_DL_8 (0x3 << 2)
378 #define RT5625_I2S_DF_MASK (0x3)
379 #define RT5625_I2S_DF_SFT 0
380 #define RT5625_I2S_DF_I2S (0x0)
381 #define RT5625_I2S_DF_LEFT (0x1)
382 #define RT5625_I2S_DF_PCM_A (0x2)
383 #define RT5625_I2S_DF_PCM_B (0x3)
385 /* Extend Serial Data Port Control (0x36) */
386 #define RT5625_PCM_F_MASK (0x1 << 15)
387 #define RT5625_PCM_F_SFT 15
388 #define RT5625_PCM_F_GPIO (0x0 << 15)
389 #define RT5625_PCM_F_PCM (0x1 << 15)
390 #define RT5625_PCM_M_MASK (0x1 << 14)
391 #define RT5625_PCM_M_SFT 14
392 #define RT5625_PCM_M_MST (0x0 << 14)
393 #define RT5625_PCM_M_SLV (0x1 << 14)
394 #define RT5625_PCM_CS_MASK (0x1 << 8)
395 #define RT5625_PCM_CS_SFT 8
396 #define RT5625_PCM_CS_SCLK (0x0 << 8)
397 #define RT5625_PCM_CS_VSCLK (0x1 << 8)
399 /* Power Management Addition 1 (0x3a) */
400 #define RT5625_P_DACL_MIX (0x1 << 15)
401 #define RT5625_P_DACL_MIX_BIT 15
402 #define RT5625_P_DACR_MIX (0x1 << 14)
403 #define RT5625_P_DACR_MIX_BIT 14
404 #define RT5625_P_ZCD (0x1 << 13)
405 #define RT5625_P_ZCD_BIT 13
406 #define RT5625_P_I2S (0x1 << 11)
407 #define RT5625_P_I2S_BIT 11
408 #define RT5625_P_SPK_AMP (0x1 << 10)
409 #define RT5625_P_SPK_AMP_BIT 10
410 #define RT5625_P_HPO_AMP (0x1 << 9)
411 #define RT5625_P_HPO_AMP_BIT 9
412 #define RT5625_P_HPO_ENH (0x1 << 8)
413 #define RT5625_P_HPO_ENH_BIT 8
414 #define RT5625_P_VDAC_MIX (0x1 << 7)
415 #define RT5625_P_VDAC_MIX_BIT 7
416 #define RT5625_P_SG_EN (0x1 << 6)
417 #define RT5625_P_SG_EN_BIT 6
418 #define RT5625_P_MB1_SCD (0x1 << 5)
419 #define RT5625_P_MB1_SCD_BIT 5
420 #define RT5625_P_MB2_SCD (0x1 << 4)
421 #define RT5625_P_MB2_SCD_BIT 4
422 #define RT5625_P_MB1 (0x1 << 3)
423 #define RT5625_P_MB1_BIT 3
424 #define RT5625_P_MB2 (0x1 << 2)
425 #define RT5625_P_MB2_BIT 2
426 #define RT5625_P_MAIN_BIAS (0x1 << 1)
427 #define RT5625_P_MAIN_BIAS_BIT 1
428 #define RT5625_P_DAC_REF (0x1)
429 #define RT5625_P_DAC_REF_BIT 0
431 /* Power Management Addition 2 (0x3c) */
432 #define RT5625_P_PLL1 (0x1 << 15)
433 #define RT5625_P_PLL1_BIT 15
434 #define RT5625_P_PLL2 (0x1 << 14)
435 #define RT5625_P_PLL2_BIT 14
436 #define RT5625_P_VREF (0x1 << 13)
437 #define RT5625_P_VREF_BIT 13
438 #define RT5625_P_OVT (0x1 << 12)
439 #define RT5625_P_OVT_BIT 12
440 #define RT5625_P_AUX_ADC (0x1 << 11)
441 #define RT5625_P_AUX_ADC_BIT 11
442 #define RT5625_P_VDAC (0x1 << 10)
443 #define RT5625_P_VDAC_BIT 10
444 #define RT5625_P_DACL (0x1 << 9)
445 #define RT5625_P_DACL_BIT 9
446 #define RT5625_P_DACR (0x1 << 8)
447 #define RT5625_P_DACR_BIT 8
448 #define RT5625_P_ADCL (0x1 << 7)
449 #define RT5625_P_ADCL_BIT 7
450 #define RT5625_P_ADCR (0x1 << 6)
451 #define RT5625_P_ADCR_BIT 6
452 #define RT5625_P_HM_L (0x1 << 5)
453 #define RT5625_P_HM_L_BIT 5
454 #define RT5625_P_HM_R (0x1 << 4)
455 #define RT5625_P_HM_R_BIT 4
456 #define RT5625_P_SM (0x1 << 3)
457 #define RT5625_P_SM_BIT 3
458 #define RT5625_P_MM (0x1 << 2)
459 #define RT5625_P_MM_BIT 2
460 #define RT5625_P_ADCL_RM (0x1 << 1)
461 #define RT5625_P_ADCL_RM_BIT 1
462 #define RT5625_P_ADCR_RM (0x1)
463 #define RT5625_P_ADCR_RM_BIT 0
465 /* Power Management Addition 3 (0x3e) */
466 #define RT5625_P_OSC_EN (0x1 << 15)
467 #define RT5625_P_OSC_EN_BIT 15
468 #define RT5625_P_AUX_VOL (0x1 << 14)
469 #define RT5625_P_AUX_VOL_BIT 14
470 #define RT5625_P_SPKL_VOL (0x1 << 13)
471 #define RT5625_P_SPKL_VOL_BIT 13
472 #define RT5625_P_SPKR_VOL (0x1 << 12)
473 #define RT5625_P_SPKR_VOL_BIT 12
474 #define RT5625_P_HPL_VOL (0x1 << 11)
475 #define RT5625_P_HPL_VOL_BIT 11
476 #define RT5625_P_HPR_VOL (0x1 << 10)
477 #define RT5625_P_HPR_VOL_BIT 10
478 #define RT5625_P_DSP_IF (0x1 << 9)
479 #define RT5625_P_DSP_IF_BIT 9
480 #define RT5625_P_DSP_I2C (0x1 << 8)
481 #define RT5625_P_DSP_I2C_BIT 8
482 #define RT5625_P_LV_L (0x1 << 7)
483 #define RT5625_P_LV_L_BIT 7
484 #define RT5625_P_LV_R (0x1 << 6)
485 #define RT5625_P_LV_R_BIT 6
486 #define RT5625_P_PH_VOL (0x1 << 5)
487 #define RT5625_P_PH_VOL_BIT 5
488 #define RT5625_P_PH_ADMIX (0x1 << 4)
489 #define RT5625_P_PH_ADMIX_BIT 4
490 #define RT5625_P_MIC1_VOL (0x1 << 3)
491 #define RT5625_P_MIC1_VOL_BIT 3
492 #define RT5625_P_MIC2_VOL (0x1 << 2)
493 #define RT5625_P_MIC2_VOL_BIT 2
494 #define RT5625_P_MIC1_BST (0x1 << 1)
495 #define RT5625_P_MIC1_BST_BIT 1
496 #define RT5625_P_MIC2_BST (0x1)
497 #define RT5625_P_MIC2_BST_BIT 0
499 /* General Purpose Control Register 1 (0x40) */
500 #define RT5625_SCLK_MASK (0x1 << 15)
501 #define RT5625_SCLK_SFT 15
502 #define RT5625_SCLK_MCLK (0x0 << 15)
503 #define RT5625_SCLK_PLL1 (0x1 << 15)
504 #define RT5625_VSCLK_MASK (0x1 << 4)
505 #define RT5625_VSCLK_SFT 4
506 #define RT5625_VSCLK_PLL2 (0x0<<4)
507 #define RT5625_VSCLK_EXTCLK (0x1<<4)
508 #define RT5625_SPK_R_MASK (0x7 << 1)
509 #define RT5625_SPK_R_SFT 1
510 #define RT5625_SPK_R_225V (0x0 << 1)
511 #define RT5625_SPK_R_200V (0x1 << 1)
512 #define RT5625_SPK_R_175V (0x2 << 1)
513 #define RT5625_SPK_R_150V (0x3 << 1)
514 #define RT5625_SPK_R_125V (0x4 << 1)
515 #define RT5625_SPK_R_100V (0x5 << 1)
517 /* General Purpose Control Register 2 (0x42) */
518 #define RT5625_PLL1_S_MASK (0x3 << 12)
519 #define RT5625_PLL1_S_SFT 12
520 #define RT5625_PLL1_S_MCLK (0x0 << 12)
521 #define RT5625_PLL1_S_BCLK (0x2 << 12)
522 #define RT5625_PLL1_S_VBCLK (0x3 << 12)
524 /* PLL2 Control (0x46) */
525 #define RT5625_PLL2_MASK (0x1 << 15)
526 #define RT5625_PLL2_DIS (0x0 << 15)
527 #define RT5625_PLL2_EN (0x1 << 15)
528 #define RT5625_PLL2_R_MASK (0x1)
529 #define RT5625_PLL2_R_8X (0x0)
530 #define RT5625_PLL2_R_16X (0x1)
532 /* LDO Control (0x48) */
533 #define RT5625_LDO_MASK (0x1 << 15)
534 #define RT5625_LDO_DIS (0x0 << 15)
535 #define RT5625_LDO_EN (0x1 << 15)
536 #define RT5625_LDO_VC_MASK (0xf)
537 #define RT5625_LDO_VC_1_55V (0xf<<0)
538 #define RT5625_LDO_VC_1_50V (0xe<<0)
539 #define RT5625_LDO_VC_1_45V (0xd<<0)
540 #define RT5625_LDO_VC_1_40V (0xc<<0)
541 #define RT5625_LDO_VC_1_35V (0xb<<0)
542 #define RT5625_LDO_VC_1_30V (0xa<<0)
543 #define RT5625_LDO_VC_1_25V (0x9<<0)
544 #define RT5625_LDO_VC_1_20V (0x8<<0)
545 #define RT5625_LDO_VC_1_15V (0x7<<0)
546 #define RT5625_LDO_VC_1_05V (0x6<<0)
547 #define RT5625_LDO_VC_1_00V (0x5<<0)
548 #define RT5625_LDO_VC_0_95V (0x4<<0)
549 #define RT5625_LDO_VC_0_90V (0x3<<0)
550 #define RT5625_LDO_VC_0_85V (0x2<<0)
551 #define RT5625_LDO_VC_0_80V (0x1<<0)
552 #define RT5625_LDO_VC_0_75V (0x0<<0)
554 /* GPIO Pin Configuration (0x4c) */
555 #define RT5625_GPIO_5 (0x1 << 5)
556 #define RT5625_GPIO_4 (0x1 << 4)
557 #define RT5625_GPIO_3 (0x1 << 3)
558 #define RT5625_GPIO_2 (0x1 << 2)
559 #define RT5625_GPIO_1 (0x1 << 1)
561 /* MISC Control (0x5e) */
562 #define RT5625_FAST_VREF_MASK (0x1 << 15)
563 #define RT5625_FAST_VREF_EN (0x0 << 15)
564 #define RT5625_FAST_VREF_DIS (0x1 << 15)
565 #define RT5625_HP_DEPOP_M2 (0x1 << 8)
566 #define RT5625_HP_DEPOP_M1 (0x1 << 9)
567 #define RT5625_HPL_MUM_DEPOP (0x1 << 7)
568 #define RT5625_HPR_MUM_DEPOP (0x1 << 6)
569 #define RT5625_MUM_DEPOP (0x1 << 5)
571 /* Stereo DAC Clock Control 1 (0x60) */
572 #define RT5625_BCLK_DIV1_MASK (0xf << 12)
573 #define RT5625_BCLK_DIV1_1 (0x0 << 12)
574 #define RT5625_BCLK_DIV1_2 (0x1 << 12)
575 #define RT5625_BCLK_DIV1_3 (0x2 << 12)
576 #define RT5625_BCLK_DIV1_4 (0x3 << 12)
577 #define RT5625_BCLK_DIV1_5 (0x4 << 12)
578 #define RT5625_BCLK_DIV1_6 (0x5 << 12)
579 #define RT5625_BCLK_DIV1_7 (0x6 << 12)
580 #define RT5625_BCLK_DIV1_8 (0x7 << 12)
581 #define RT5625_BCLK_DIV1_9 (0x8 << 12)
582 #define RT5625_BCLK_DIV1_10 (0x9 << 12)
583 #define RT5625_BCLK_DIV1_11 (0xa << 12)
584 #define RT5625_BCLK_DIV1_12 (0xb << 12)
585 #define RT5625_BCLK_DIV1_13 (0xc << 12)
586 #define RT5625_BCLK_DIV1_14 (0xd << 12)
587 #define RT5625_BCLK_DIV1_15 (0xe << 12)
588 #define RT5625_BCLK_DIV1_16 (0xf << 12)
589 #define RT5625_BCLK_DIV2_MASK (0x7 << 8)
590 #define RT5625_BCLK_DIV2_2 (0x0 << 8)
591 #define RT5625_BCLK_DIV2_4 (0x1 << 8)
592 #define RT5625_BCLK_DIV2_8 (0x2 << 8)
593 #define RT5625_BCLK_DIV2_16 (0x3 << 8)
594 #define RT5625_BCLK_DIV2_32 (0x4 << 8)
595 #define RT5625_AD_LRCK_DIV1_MASK (0xf << 4)
596 #define RT5625_AD_LRCK_DIV1_1 (0x0 << 4)
597 #define RT5625_AD_LRCK_DIV1_2 (0x1 << 4)
598 #define RT5625_AD_LRCK_DIV1_3 (0x2 << 4)
599 #define RT5625_AD_LRCK_DIV1_4 (0x3 << 4)
600 #define RT5625_AD_LRCK_DIV1_5 (0x4 << 4)
601 #define RT5625_AD_LRCK_DIV1_6 (0x5 << 4)
602 #define RT5625_AD_LRCK_DIV1_7 (0x6 << 4)
603 #define RT5625_AD_LRCK_DIV1_8 (0x7 << 4)
604 #define RT5625_AD_LRCK_DIV1_9 (0x8 << 4)
605 #define RT5625_AD_LRCK_DIV1_10 (0x9 << 4)
606 #define RT5625_AD_LRCK_DIV1_11 (0xa << 4)
607 #define RT5625_AD_LRCK_DIV1_12 (0xb << 4)
608 #define RT5625_AD_LRCK_DIV1_13 (0xc << 4)
609 #define RT5625_AD_LRCK_DIV1_14 (0xd << 4)
610 #define RT5625_AD_LRCK_DIV1_15 (0xe << 4)
611 #define RT5625_AD_LRCK_DIV1_16 (0xf << 4)
612 #define RT5625_AD_LRCK_DIV2_MASK (0x7 << 1)
613 #define RT5625_AD_LRCK_DIV2_2 (0x0 << 1)
614 #define RT5625_AD_LRCK_DIV2_4 (0x1 << 1)
615 #define RT5625_AD_LRCK_DIV2_8 (0x2 << 1)
616 #define RT5625_AD_LRCK_DIV2_16 (0x3 << 1)
617 #define RT5625_AD_LRCK_DIV2_32 (0x4 << 1)
618 #define RT5625_DA_LRCK_DIV_MASK (1)
619 #define RT5625_DA_LRCK_DIV_32 (0)
620 #define RT5625_DA_LRCK_DIV_64 (1)
622 /* Stereo DAC Clock Control 2 (0x62) */
623 #define RT5625_DF_DIV1_MASK (0xF << 12)
624 #define RT5625_DF_DIV1_1 (0x0 << 12)
625 #define RT5625_DF_DIV1_2 (0x1 << 12)
626 #define RT5625_DF_DIV1_3 (0x2 << 12)
627 #define RT5625_DF_DIV1_4 (0x3 << 12)
628 #define RT5625_DF_DIV1_5 (0x4 << 12)
629 #define RT5625_DF_DIV1_6 (0x5 << 12)
630 #define RT5625_DF_DIV1_7 (0x6 << 12)
631 #define RT5625_DF_DIV1_8 (0x7 << 12)
632 #define RT5625_DF_DIV1_9 (0x8 << 12)
633 #define RT5625_DF_DIV1_10 (0x9 << 12)
634 #define RT5625_DF_DIV1_11 (0xA << 12)
635 #define RT5625_DF_DIV1_12 (0xB << 12)
636 #define RT5625_DF_DIV1_13 (0xC << 12)
637 #define RT5625_DF_DIV1_14 (0xD << 12)
638 #define RT5625_DF_DIV1_15 (0xE << 12)
639 #define RT5625_DF_DIV1_16 (0xF << 12)
640 #define RT5625_DF_DIV2_MASK (0x7 << 9)
641 #define RT5625_DF_DIV2_2 (0x0 << 9)
642 #define RT5625_DF_DIV2_4 (0x1 << 9)
643 #define RT5625_DF_DIV2_8 (0x2 << 9)
644 #define RT5625_DF_DIV2_16 (0x3 << 9)
645 #define RT5625_DF_DIV2_32 (0x4 << 9)
646 #define RT5625_AF_DIV1_MASK (0xF << 4)
647 #define RT5625_AF_DIV1_1 (0x0 << 4)
648 #define RT5625_AF_DIV1_2 (0x1 << 4)
649 #define RT5625_AF_DIV1_3 (0x2 << 4)
650 #define RT5625_AF_DIV1_4 (0x3 << 4)
651 #define RT5625_AF_DIV1_5 (0x4 << 4)
652 #define RT5625_AF_DIV1_6 (0x5 << 4)
653 #define RT5625_AF_DIV1_7 (0x6 << 4)
654 #define RT5625_AF_DIV1_8 (0x7 << 4)
655 #define RT5625_AF_DIV1_9 (0x8 << 4)
656 #define RT5625_AF_DIV1_10 (0x9 << 4)
657 #define RT5625_AF_DIV1_11 (0xA << 4)
658 #define RT5625_AF_DIV1_12 (0xB << 4)
659 #define RT5625_AF_DIV1_13 (0xC << 4)
660 #define RT5625_AF_DIV1_14 (0xD << 4)
661 #define RT5625_AF_DIV1_15 (0xE << 4)
662 #define RT5625_AF_DIV1_16 (0xF << 4)
663 #define RT5625_AF_DIV2_MASK (0x7 << 1)
664 #define RT5625_AF_DIV2_1 (0x0 << 1)
665 #define RT5625_AF_DIV2_2 (0x1 << 1)
666 #define RT5625_AF_DIV2_4 (0x2 << 1)
667 #define RT5625_AF_DIV2_8 (0x3 << 1)
668 #define RT5625_AF_DIV2_16 (0x4 << 1)
669 #define RT5625_AF_DIV2_32 (0x5 << 1)
671 /* Voice DAC PCM Clock Control 1 (0x64) */
672 #define RT5625_VBCLK_DIV1_MASK (0xF << 12)
673 #define RT5625_VBCLK_DIV1_1 (0x0 << 12)
674 #define RT5625_VBCLK_DIV1_2 (0x1 << 12)
675 #define RT5625_VBCLK_DIV1_3 (0x2 << 12)
676 #define RT5625_VBCLK_DIV1_4 (0x3 << 12)
677 #define RT5625_VBCLK_DIV1_5 (0x4 << 12)
678 #define RT5625_VBCLK_DIV1_6 (0x5 << 12)
679 #define RT5625_VBCLK_DIV1_7 (0x6 << 12)
680 #define RT5625_VBCLK_DIV1_8 (0x7 << 12)
681 #define RT5625_VBCLK_DIV1_9 (0x8 << 12)
682 #define RT5625_VBCLK_DIV1_10 (0x9 << 12)
683 #define RT5625_VBCLK_DIV1_11 (0xA << 12)
684 #define RT5625_VBCLK_DIV1_12 (0xB << 12)
685 #define RT5625_VBCLK_DIV1_13 (0xC << 12)
686 #define RT5625_VBCLK_DIV1_14 (0xD << 12)
687 #define RT5625_VBCLK_DIV1_15 (0xE << 12)
688 #define RT5625_VBCLK_DIV1_16 (0xF << 12)
689 #define RT5625_VBCLK_DIV2_MASK (0x7 << 8)
690 #define RT5625_VBCLK_DIV2_2 (0x0 << 8)
691 #define RT5625_VBCLK_DIV2_4 (0x1 << 8)
692 #define RT5625_VBCLK_DIV2_8 (0x2 << 8)
693 #define RT5625_VBCLK_DIV2_16 (0x3 << 8)
694 #define RT5625_VBCLK_DIV2_32 (0x4 << 8)
695 #define RT5625_AD_VLRCK_DIV1_MASK (0xF << 4)
696 #define RT5625_AD_VLRCK_DIV1_1 (0x0 << 4)
697 #define RT5625_AD_VLRCK_DIV1_2 (0x1 << 4)
698 #define RT5625_AD_VLRCK_DIV1_3 (0x2 << 4)
699 #define RT5625_AD_VLRCK_DIV1_4 (0x3 << 4)
700 #define RT5625_AD_VLRCK_DIV1_5 (0x4 << 4)
701 #define RT5625_AD_VLRCK_DIV1_6 (0x5 << 4)
702 #define RT5625_AD_VLRCK_DIV1_7 (0x6 << 4)
703 #define RT5625_AD_VLRCK_DIV1_8 (0x7 << 4)
704 #define RT5625_AD_VLRCK_DIV1_9 (0x8 << 4)
705 #define RT5625_AD_VLRCK_DIV1_10 (0x9 << 4)
706 #define RT5625_AD_VLRCK_DIV1_11 (0xA << 4)
707 #define RT5625_AD_VLRCK_DIV1_12 (0xB << 4)
708 #define RT5625_AD_VLRCK_DIV1_13 (0xC << 4)
709 #define RT5625_AD_VLRCK_DIV1_14 (0xD << 4)
710 #define RT5625_AD_VLRCK_DIV1_15 (0xE << 4)
711 #define RT5625_AD_VLRCK_DIV1_16 (0xF << 4)
712 #define RT5625_AD_VLRCK_DIV2_MASK (0x7 << 1)
713 #define RT5625_AD_VLRCK_DIV2_2 (0x0 << 1)
714 #define RT5625_AD_VLRCK_DIV2_4 (0x1 << 1)
715 #define RT5625_AD_VLRCK_DIV2_8 (0x2 << 1)
716 #define RT5625_AD_VLRCK_DIV2_16 (0x3 << 1)
717 #define RT5625_AD_VLRCK_DIV2_32 (0x4 << 1)
718 #define RT5625_DA_VLRCK_DIV_MASK (1)
719 #define RT5625_DA_VLRCK_DIV_32 (0)
720 #define RT5625_DA_VLRCK_DIV_64 (1)
722 /* Psedueo Stereo & Spatial Effect Block Control (0x68) */
723 #define RT5625_SP_CTRL_EN (0x1 << 15)
724 #define RT5625_APF_EN (0x1 << 14)
725 #define RT5625_PS_EN (0x1 << 13)
726 #define RT5625_STO_EXP_EN (0x1 << 12)
727 #define RT5625_SP_3D_G1_MASK (0x3 << 10)
728 #define RT5625_SP_3D_G1_1_0 (0x0 << 10)
729 #define RT5625_SP_3D_G1_1_5 (0x1 << 10)
730 #define RT5625_SP_3D_G1_2_0 (0x2 << 10)
731 #define RT5625_SP_3D_R1_MASK (0x3 << 8)
732 #define RT5625_SP_3D_R1_0_0 (0x0 << 8)
733 #define RT5625_SP_3D_R1_0_66 (0x1 << 8)
734 #define RT5625_SP_3D_R1_1_0 (0x2 << 8)
735 #define RT5625_SP_3D_G2_MASK (0x3 << 6)
736 #define RT5625_SP_3D_G2_1_0 (0x0 << 6)
737 #define RT5625_SP_3D_G2_1_5 (0x1 << 6)
738 #define RT5625_SP_3D_G2_2_0 (0x2 << 6)
739 #define RT5625_SP_3D_R2_MASK (0x3 << 4)
740 #define RT5625_SP_3D_R2_0_0 (0x0 << 4)
741 #define RT5625_SP_3D_R2_0_66 (0x1 << 4)
742 #define RT5625_SP_3D_R2_1_0 (0x2 << 4)
743 #define RT5625_APF_MASK (0x3)
744 #define RT5625_APF_48K (0x3)
745 #define RT5625_APF_44_1K (0x2)
746 #define RT5625_APF_32K (0x1)
748 /* EQ Control and Status /ADC HPF Control (0x6E) */
749 #define RT5625_EN_HW_EQ_BLK (0x1 << 15)
750 #define RT5625_EQ_SRC_DAC (0x0 << 14)
751 #define RT5625_EQ_SRC_ADC (0x1 << 14)
752 #define RT5625_EQ_CHG_EN (0x1 << 7)
753 #define RT5625_EN_HW_EQ_HPF (0x1 << 4)
754 #define RT5625_EN_HW_EQ_BP3 (0x1 << 3)
755 #define RT5625_EN_HW_EQ_BP2 (0x1 << 2)
756 #define RT5625_EN_HW_EQ_BP1 (0x1 << 1)
757 #define RT5625_EN_HW_EQ_LPF (0x1 << 0)
759 /* VoDSP Register Command (0x74) */
760 #define RT5625_DSP_BUSY_MASK (0x1 << 15)
761 #define RT5625_DSP_DS_MASK (0x1 << 14)
762 #define RT5625_DSP_DS_VODSP (0x0 << 14)
763 #define RT5625_DSP_DS_REG72 (0x1 << 14)
764 #define RT5625_DSP_CLK_MASK (0x3 << 12)
765 #define RT5625_DSP_CLK_12_288M (0x0 << 12)
766 #define RT5625_DSP_CLK_6_144M (0x1 << 12)
767 #define RT5625_DSP_CLK_3_072M (0x2 << 12)
768 #define RT5625_DSP_CLK_2_048M (0x3 << 12)
769 #define RT5625_DSP_R_EN (0x1 << 9)
770 #define RT5625_DSP_W_EN (0x1 << 8)
771 #define RT5625_DSP_CMD_MASK (0xff)
772 #define RT5625_DSP_CMD_SFT 0
773 #define RT5625_DSP_CMD_MW (0x3B) /* Memory Write */
774 #define RT5625_DSP_CMD_MR (0x37) /* Memory Read */
775 #define RT5625_DSP_CMD_RR (0x60) /* Register Read */
776 #define RT5625_DSP_CMD_RW (0x68) /* Register Write */
779 /* Index(0x20) for Auto Volume Control */
780 #define RT5625_AVC_CH_MASK (0x1 << 7)
781 #define RT5625_AVC_CH_L_CH (0x0 << 7)
782 #define RT5625_AVC_CH_R_CH (0x1 << 7)
783 #define RT5625_AVC_GAIN_EN (0x1 << 15)
792 /* System Clock Source */
800 RT5625_PLL_MCLK_TO_VSYSCLK,
810 //#ifdef RT5625_F_SMT_PHO
813 RT5625_PLL_112896_225792,
814 RT5625_PLL_112896_24576,
819 unsigned short index;
820 unsigned short value;