sound/soc/codecs/rt5625.h

   1 #ifndef _RT5625_H
   2 #define _RT5625_H
   3
   4 #define RT5625_RESET                                            0X00                    //RESET CODEC TO DEFAULT
   5 #define RT5625_SPK_OUT_VOL                                      0X02                    //SPEAKER OUT VOLUME
   6 #define RT5625_HP_OUT_VOL                                       0X04                    //HEADPHONE OUTPUT VOLUME
   7 #define RT5625_AUX_OUT_VOL                                      0X06                    //AUXOUT VOLUME
   8 #define RT5625_PHONEIN_VOL                                      0X08                    //PHONE INPUT VOLUME
   9 #define RT5625_LINE_IN_VOL                                      0X0A                    //LINE IN VOLUME
  10 #define RT5625_STEREO_DAC_VOL                           0X0C                    //STEREO DAC VOLUME
  11 #define RT5625_MIC_VOL                                          0X0E                    //MICROPHONE VOLUME
  12 #define RT5625_DAC_AND_MIC_CTRL                         0X10                    //STEREO DAC AND MIC ROUTING CONTROL
  13 #define RT5625_ADC_REC_GAIN                                     0X12                    //ADC RECORD GAIN
  14 #define RT5625_ADC_REC_MIXER                            0X14                    //ADC RECORD MIXER CONTROL
  15 #define RT5625_VOICE_DAC_OUT_VOL                        0X18                    //VOICE DAC OUTPUT VOLUME
  16 #define RT5625_VODSP_PDM_CTL                            0X1A                    //VODSP & PDM CONTROL
  17 #define RT5625_OUTPUT_MIXER_CTRL                        0X1C                    //OUTPUT MIXER CONTROL
  18 #define RT5625_VODSP_CTL                                        0X1E                    //VODSP CONTROL
  19 #define RT5625_MIC_CTRL                                         0X22                    //MICROPHONE CONTROL
  20 #define RT5625_DMIC_CTRL                                        0x24
  21 #define RT5625_PD_CTRL_STAT                                     0X26                    //POWER DOWN CONTROL/STATUS
  22 #define RT5625_DAC_ADC_VODAC_FUN_SEL            0X2E                    //STEREO DAC,VOICE DAC,STEREO ADC FUNCTION SELECT
  23 #define RT5625_MAIN_SDP_CTRL                            0X34                    //MAIN SERIAL DATA PORT CONTROL(STEREO I2S)
  24 #define RT5625_EXTEND_SDP_CTRL                          0X36                    //EXTEND SERIAL DATA PORT CONTROL(VOICE I2S/PCM)
  25 #define RT5625_PWR_MANAG_ADD1                           0X3A                    //POWER MANAGMENT ADDITION 1
  26 #define RT5625_PWR_MANAG_ADD2                           0X3C                    //POWER MANAGMENT ADDITION 2
  27 #define RT5625_PWR_MANAG_ADD3                           0X3E                    //POWER MANAGMENT ADDITION 3
  28 #define RT5625_GEN_CTRL_REG1                            0X40                    //GENERAL PURPOSE CONTROL REGISTER 1
  29 #define RT5625_GEN_CTRL_REG2                            0X42                    //GENERAL PURPOSE CONTROL REGISTER 2
  30 #define RT5625_PLL_CTRL                                         0X44                    //PLL1 CONTROL
  31 #define RT5625_PLL2_CTRL                                        0X46                    //PLL2 CONTROL
  32 #define RT5625_LDO_CTRL                                         0X48                    //LDO CONTROL
  33 #define RT5625_GPIO_PIN_CONFIG                          0X4C                    //GPIO PIN CONFIGURATION
  34 #define RT5625_GPIO_PIN_POLARITY                        0X4E                    //GPIO PIN POLARITY
  35 #define RT5625_GPIO_PIN_STICKY                          0X50                    //GPIO PIN STICKY
  36 #define RT5625_GPIO_PIN_WAKEUP                          0X52                    //GPIO PIN WAKE UP
  37 #define RT5625_GPIO_PIN_STATUS                          0X54                    //GPIO PIN STATUS
  38 #define RT5625_GPIO_PIN_SHARING                         0X56                    //GPIO PIN SHARING
  39 #define RT5625_OVER_TEMP_CURR_STATUS            0X58                    //OVER TEMPERATURE AND CURRENT STATUS
  40 #define RT5625_SOFT_VOL_CTRL                            0X5A                    //SOFT VOLUME CONTROL SETTING
  41 #define RT5625_GPIO_OUT_CTRL                            0X5C                    //GPIO OUTPUT PIN CONTRL
  42 #define RT5625_MISC_CTRL                                        0X5E                    //MISC CONTROL
  43 #define RT5625_STEREO_DAC_CLK_CTRL1                     0X60                    //STEREO DAC CLOCK CONTROL 1
  44 #define RT5625_STEREO_DAC_CLK_CTRL2                     0X62                    //STEREO DAC CLOCK CONTROL 2
  45 #define RT5625_VOICE_DAC_PCMCLK_CTRL1           0X64                    //VOICE/PCM DAC CLOCK CONTROL 1
  46 #define RT5625_PSEDUEO_SPATIAL_CTRL                     0X68                    //PSEDUEO STEREO /SPATIAL EFFECT BLOCK CONTROL
  47 #define RT5625_PRIV_ADDR                                        0X6A                    //PRIVATE ADDRESS
  48 #define RT5625_PRIV_DATA                                        0X6C                    //PRIVATE DATA
  49 #define RT5625_EQ_CTRL_ADC_HPF                          0X6E                    //EQ CONTROL AND STATUS /ADC HPF CONTROL
  50 #define RT5625_VODSP_REG_ADDR                   0x70                    //VODSP REGISTER ADDRESS
  51 #define RT5625_VODSP_REG_DATA                   0x72                    //VODSP REGISTER DATA
  52 #define RT5625_VODSP_REG_CMD                        0x74                        //VODSP REGISTER COMMAND
  53
  54
  55 /**************************************************************************************************
  56  *Bit define of Codec Register
  57  *************************************************************************************************/
  58 //global definition
  59 #define RT_L_MUTE                                               (0x1<<15)               //Mute Left Control
  60 #define RT_L_ZC                                                 (0x1<<14)               //Mute Left Zero-Cross Detector Control
  61 #define RT_R_MUTE                                               (0x1<<7)                //Mute Right Control
  62 #define RT_R_ZC                                                 (0x1<<6)                //Mute Right Zero-Cross Detector Control
  63 #define RT_M_HP_MIXER                                   (0x1<<15)               //Mute source to HP Mixer
  64 #define RT_M_SPK_MIXER                                  (0x1<<14)               //Mute source to Speaker Mixer
  65 #define RT_M_MONO_MIXER                                 (0x1<<13)               //Mute source to Mono Mixer
  66
  67 //Phone Input Volume(0x08)
  68 #define M_PHONEIN_TO_HP_MIXER                   (0x1<<15)               //Mute Phone In volume to HP mixer
  69 #define M_PHONEIN_TO_SPK_MIXER                  (0x1<<14)               //Mute Phone In volume to speaker mixer
  70
  71
  72 //Mic Routing Control(0x10)
  73 #define M_MIC1_TO_HP_MIXER                              (0x1<<15)               //Mute MIC1 to HP mixer
  74 #define M_MIC1_TO_SPK_MIXER                             (0x1<<14)               //Mute MiC1 to SPK mixer
  75 #define M_MIC1_TO_MONO_MIXER                    (0x1<<13)               //Mute MIC1 to MONO mixer
  76 #define M_MIC2_TO_HP_MIXER                              (0x1<<11)               //Mute MIC2 to HP mixer
  77 #define M_MIC2_TO_SPK_MIXER                             (0x1<<10)               //Mute MiC2 to SPK mixer
  78 #define M_MIC2_TO_MONO_MIXER                    (0x1<<9)                //Mute MIC2 to MONO mixer
  79 #define M_DAC_TO_HPL_MIXER                              (0x1<<3)                //Mute DAC to HP left mixer
  80 #define M_DAC_TO_HPR_MIXER                              (0x1<<2)                //Mute DAC to HP right mixer
  81 #define M_DAC_TO_SPK_MIXER                              (0x1<<1)                //Mute DAC to SPK mixer
  82 #define M_DAC_TO_MONO_MIXER                             (0x1<<0)                //Mute DAC to MONO mixer
  83
  84
  85
  86 //ADC Record Gain(0x12)
  87 #define M_ADC_L_TO_HP_MIXER                             (0x1<<15)               //Mute left of ADC to HP Mixer
  88 #define M_ADC_L_TO_MONO_MIXER                   (0x1<<14)               //Mute left of ADC to MONO Mixer
  89 #define ADC_L_ZC_DET                                    (0x1<<13)               //ADC Zero-Cross Detector Control
  90 #define ADC_L_GAIN_MASK                                 (0x1f<<8)               //ADC Record Gain Left channel Mask
  91 #define M_ADC_R_TO_HP_MIXER                             (0x1<<7)                //Mute right of ADC to HP Mixer
  92 #define M_ADC_R_TO_MONO_MIXER                   (0x1<<6)                //Mute right of ADC to MONO Mixer
  93 #define ADC_R_ZC_DET                                    (0x1<<5)                //ADC Zero-Cross Detector Control
  94 #define ADC_R_GAIN_MASK                                 (0x1f<<0)               //ADC Record Gain Right channel Mask
  95
  96 //Voice DAC Output Volume(0x18)
  97 #define M_V_DAC_TO_HP_MIXER                             (0x1<<15)
  98 #define M_V_DAC_TO_SPK_MIXER                    (0x1<<14)
  99 #define M_V_DAC_TO_MONO_MIXER                   (0x1<<13)
 100
 101
 102 //AEC & PDM Control(0x1A)
 103 #define VODSP_SRC1_PWR                                  (0x1<<15)               //Enable SRC1 Power
 104 #define VODSP_SRC2_PWR                                  (0x1<<13)               //Enable SRC2 Power
 105
 106 #define VODSP_SRC2_S_SEL_MASK                   (0x1<<12)
 107 #define VODSP_SRC2_S_SEL_TXDP                   (0x0<<12)               //SRC2 source select AEC_TXDP
 108 #define VODSP_SRC2_S_SEL_TXDC                   (0x1<<12)               //SRC2 source select AEC_TXDC
 109
 110 #define VODSP_RXDP_PWR                                  (0x1<<11)               //Enable AEC RXDP Power
 111
 112 #define VODSP_RXDP_S_SEL_MASK                   (0x3<<9)
 113 #define VODSP_RXDP_S_SEL_SRC1                   (0x0<<9)                //AEC RxDP source select SRC1 Output
 114 #define VODSP_RXDP_S_SEL_ADCL                   (0x1<<9)                //AEC RxDP source select ADC Left to AEC Digital Path
 115 #define VODSP_RXDP_S_SEL_VOICE                  (0x2<<9)                //AEC RxDP source select Voice to Stereo Digital Path
 116 #define VODSP_RXDP_S_SEL_ADCR                   (0x3<<9)                //AEC RxDP source select ADC Right to AEC Digital Path
 117
 118 #define VODSP_RXDC_PWR                                  (0x1<<8)                //Enable AEC RXDC Power
 119
 120 #define VOICE_PCM_S_SEL_MASK                    (0x1<<7)
 121 #define VOICE_PCM_S_SEL_ADC_R                   (0x0<<7)                //VSADC PCM interface source select ADC R
 122 #define VOICE_PCM_S_SEL_AEC_TXDP                (0x1<<7)                //VSADC PCM interface source select AEC_TXDP
 123
 124 #define REC_S_SEL_MASK                                  (0x3<<4)
 125 #define REC_S_SEL_ADC                                   (0x0<<4)                //Main Stereo Record I2S source select ADC L/R
 126 #define REC_S_SEL_VOICE                                 (0x1<<4)                //Main Stereo Record I2S source select Voice to Stereo Digital Path
 127 #define REC_S_SEL_SRC2                                  (0x2<<4)                //Main Stereo Record I2S source select SRC2
 128
 129
 130 //Output Mixer Control(0x1C)
 131 #define SPKOUT_N_SOUR_MASK                              (0x3<<14)
 132 #define SPKOUT_N_SOUR_LN                                (0x2<<14)
 133 #define SPKOUT_N_SOUR_RP                                (0x1<<14)
 134 #define SPKOUT_N_SOUR_RN                                (0x0<<14)
 135
 136 #define SPKOUT_SEL_CLASS_D                              (0x1<<13)
 137 #define SPKOUT_SEL_CLASS_AB                             (0x0<<13)
 138
 139 #define SPK_CLASS_AB_S_AMP                              (0x0<<12)
 140 #define SPK_CALSS_AB_W_AMP                              (0x1<<12)
 141
 142 #define SPKOUT_INPUT_SEL_MASK                   (0x3<<10)
 143 #define SPKOUT_INPUT_SEL_MONOMIXER              (0x3<<10)
 144 #define SPKOUT_INPUT_SEL_SPKMIXER               (0x2<<10)
 145 #define SPKOUT_INPUT_SEL_HPMIXER                (0x1<<10)
 146 #define SPKOUT_INPUT_SEL_VMID                   (0x0<<10)
 147
 148 #define HPL_INPUT_SEL_HPLMIXER                  (0x1<<9)
 149 #define HPR_INPUT_SEL_HPRMIXER                  (0x1<<8)
 150
 151 #define AUXOUT_INPUT_SEL_MASK                   (0x3<<6)
 152 #define AUXOUT_INPUT_SEL_MONOMIXER              (0x3<<6)
 153 #define AUXOUT_INPUT_SEL_SPKMIXER               (0x2<<6)
 154 #define AUXOUT_INPUT_SEL_HPMIXER                (0x1<<6)
 155 #define AUXOUT_INPUT_SEL_VMID                   (0x0<<6)
 156
 157
 158 //Voice DSP Control(0x1E)
 159 #define VODSP_SYSCLK_S_SEL_MASK                 (0x1<<15)
 160 #define VODSP_SYSCLK_S_SEL_M_CLK                (0x0<<15)
 161 #define VODSP_SYSCLK_S_SEL_V_CLK                (0x1<<15)
 162
 163 #define VODSP_LRCK_SEL_MASK                             (0x1<<13)
 164 #define VODSP_LRCK_SEL_8K                               (0x0<<13)
 165 #define VODSP_LRCK_SEL_16K                              (0x1<<13)
 166
 167 #define VODSP_TEST_MODE_ENA                             (0x1<<3)
 168 #define VODSP_NO_BP_MODE_ENA                    (0x1<<2)
 169 #define VODSP_NO_PD_MODE_ENA                    (0x1<<1)
 170 #define VODSP_NO_RST_MODE_ENA                   (0x1<<0)
 171
 172
 173
 174
 175 //Micphone Control define(0x22)
 176 #define MIC1            1
 177 #define MIC2            2
 178 #define MIC_BIAS_90_PRECNET_AVDD        1
 179 #define MIC_BIAS_75_PRECNET_AVDD        2
 180
 181 #define MIC1_BOOST_CONTROL_MASK         (0x3<<10)
 182 #define MIC1_BOOST_CONTROL_BYPASS       (0x0<<10)
 183 #define MIC1_BOOST_CONTROL_20DB         (0x1<<10)
 184 #define MIC1_BOOST_CONTROL_30DB         (0x2<<10)
 185 #define MIC1_BOOST_CONTROL_40DB         (0x3<<10)
 186
 187 #define MIC2_BOOST_CONTROL_MASK         (0x3<<8)
 188 #define MIC2_BOOST_CONTROL_BYPASS       (0x0<<8)
 189 #define MIC2_BOOST_CONTROL_20DB         (0x1<<8)
 190 #define MIC2_BOOST_CONTROL_30DB         (0x2<<8)
 191 #define MIC2_BOOST_CONTROL_40DB         (0x3<<8)
 192
 193 #define MIC1_BIAS_VOLT_CTRL_MASK        (0x1<<5)
 194 #define MIC1_BIAS_VOLT_CTRL_90P         (0x0<<5)
 195 #define MIC1_BIAS_VOLT_CTRL_75P         (0x1<<5)
 196
 197 #define MIC2_BIAS_VOLT_CTRL_MASK        (0x1<<4)
 198 #define MIC2_BIAS_VOLT_CTRL_90P         (0x0<<4)
 199 #define MIC2_BIAS_VOLT_CTRL_75P         (0x1<<4)
 200
 201 //PowerDown control of register(0x26)
 202 //power management bits
 203 #define RT_PWR_PR7                                      (0x1<<15)       //write this bit to power down the Speaker Amplifier
 204 #define RT_PWR_PR6                                      (0x1<<14)       //write this bit to power down the Headphone Out and MonoOut
 205 #define RT_PWR_PR5                                      (0x1<<13)       //write this bit to power down the internal clock(without PLL)
 206 #define RT_PWR_PR3                                      (0x1<<11)       //write this bit to power down the mixer(vref/vrefout out off)
 207 #define RT_PWR_PR2                                      (0x1<<10)       //write this bit to power down the mixer(vref/vrefout still on)
 208 #define RT_PWR_PR1                                      (0x1<<9)        //write this bit to power down the dac
 209 #define RT_PWR_PR0                                      (0x1<<8)        //write this bit to power down the adc
 210 #define RT_PWR_REF                                      (0x1<<3)        //read only
 211 #define RT_PWR_ANL                                      (0x1<<2)        //read only
 212 #define RT_PWR_DAC                                      (0x1<<1)        //read only
 213 #define RT_PWR_ADC                                      (0x1)           //read only
 214
 215
 216 //Stereo DAC/Voice DAC/Stereo ADC function(0x2E)
 217 #define DAC_FUNC_SEL_MASK                       (0x3<<12)
 218 #define DAC_FUNC_SEL_DAC                        (0x0<<12)
 219 #define DAC_FUNC_SEL_SRC2                       (0x1<<12)
 220 #define DAC_FUNC_SEL_VODSP_TXDP         (0x2<<12)
 221 #define DAC_FUNC_SEL_VODSP_TXDC         (0x3<<12)
 222
 223 #define VODAC_SOUR_SEL_MASK                     (0x7<<8)
 224 #define VODAC_SOUR_SEL_VOICE            (0x0<<8)
 225 #define VODAC_SOUR_SEL_SRC2                     (0x1<<8)
 226 #define VODAC_SOUR_SEL_VODSP_TXDP       (0x2<<8)
 227 #define VODAC_SOUR_SEL_VODSP_TXDC       (0x3<<8)
 228
 229 #define ADCR_FUNC_SEL_MASK                      (0x3<<4)
 230 #define ADCR_FUNC_SEL_ADC                       (0x0<<4)
 231 #define ADCR_FUNC_SEL_VOADC                     (0x1<<4)
 232 #define ADCR_FUNC_SEL_VODSP                     (0x2<<4)
 233 #define ADCR_FUNC_SEL_PDM                       (0x3<<4)
 234
 235 #define ADCL_FUNC_SEL_MASK                      (0x3<<0)
 236 #define ADCL_FUNC_SEL_ADC                       (0x0<<0)
 237 #define ADCL_FUNC_SEL_VODSP                     (0x1<<0)
 238
 239 //Main Serial Data Port Control(0x34)
 240 #define MAIN_I2S_MODE_SEL                       (0x1<<15)               //0:Master mode 1:Slave mode
 241 #define MAIN_I2S_SADLRCK_CTRL           (0x1<<14)               //0:Disable,ADC and DAC use the same fs,1:Enable
 242
 243 #define MAIN_I2S_PCM_MODE                       (0x1<<6)                //0:Normal SADLRCK/SDALRCK,1:Invert SADLRCK/SDALRCK
 244 //Data Length Slection
 245 #define MAIN_I2S_DL_MASK                        (0x3<<2)                //main i2s Data Length mask
 246 #define MAIN_I2S_DL_16                          (0x0<<2)                //16 bits
 247 #define MAIN_I2S_DL_20                          (0x1<<2)                //20 bits
 248 #define MAIN_I2S_DL_24                          (0x2<<2)                //24 bits
 249 #define MAIN_I2S_DL_32                          (0x3<<2)                //8 bits
 250
 251 //PCM Data Format Selection
 252 #define MAIN_I2S_DF_MASK                        (0x3)                   //main i2s Data Format mask
 253 #define MAIN_I2S_DF_I2S                         (0x0)                   //I2S FORMAT
 254 #define MAIN_I2S_DF_LEFT                        (0x1)                   //LEFT JUSTIFIED format
 255 #define MAIN_I2S_DF_PCM_A                       (0x2)                   //PCM Mode A
 256 #define MAIN_I2S_DF_PCM_B                               (0x3)                   //PCM Mode B
 257
 258 //Extend Serial Data Port Control(0x36)
 259 #define EXT_I2S_FUNC_ENABLE                     (0x1<<15)               //Enable PCM interface on GPIO 1,3,4,5  0:GPIO function,1:Voice PCM interface
 260 #define EXT_I2S_MODE_SEL                        (0x1<<14)               //0:Master      ,1:Slave
 261 #define EXT_I2S_AUTO_CLK_CTRL           (0x1<<13)               //0:Disable,1:Enable
 262 #define EXT_I2S_BCLK_POLARITY           (0x1<<7)                //0:Normal 1:Invert
 263 #define EXT_I2S_PCM_MODE                        (0x1<<6)                //0:Normal VSLRCK,1:Invert VSLRCK
 264 //Data Length Slection
 265 #define EXT_I2S_DL_MASK                         (0x3<<2)                //Extend i2s Data Length mask
 266 #define EXT_I2S_DL_32                           (0x3<<2)                //8 bits
 267 #define EXT_I2S_DL_24                           (0x2<<2)                //24 bits
 268 #define EXT_I2S_DL_20                           (0x1<<2)                //20 bits
 269 #define EXT_I2S_DL_16                           (0x0<<2)                //16 bits
 270
 271 //Voice Data Format
 272 #define EXT_I2S_DF_MASK                         (0x3)                   //Extend i2s Data Format mask
 273 #define EXT_I2S_DF_I2S                          (0x0)                   //I2S FORMAT
 274 #define EXT_I2S_DF_LEFT                         (0x1)                   //LEFT JUSTIFIED format
 275 #define EXT_I2S_DF_PCM_A                        (0x2)                   //PCM Mode A
 276 #define EXT_I2S_DF_PCM_B                        (0x3)                   //PCM Mode B
 277
 278 //Power managment addition 1 (0x3A),0:Disable,1:Enable
 279 #define PWR_DAC_DF2SE_L                         (0x1<<15)
 280 #define PWR_DAC_DF2SE_R                         (0x1<<14)
 281 #define PWR_ZC_DET_PD                           (0x1<<13)
 282 #define PWR_I2S_INTERFACE                       (0x1<<11)
 283 #define PWR_AMP_POWER                           (0x1<<10)
 284 #define PWR_HP_OUT_AMP                          (0x1<<9)
 285 #define PWR_HP_OUT_ENH_AMP                      (0x1<<8)
 286 #define PWR_VOICE_DF2SE                         (0x1<<7)
 287 #define PWR_SOFTGEN_EN                          (0x1<<6)
 288 #define PWR_MIC_BIAS1_DET                       (0x1<<5)
 289 #define PWR_MIC_BIAS2_DET                       (0x1<<4)
 290 #define PWR_MIC_BIAS1                           (0x1<<3)
 291 #define PWR_MIC_BIAS2                           (0x1<<2)
 292 #define PWR_MAIN_BIAS                           (0x1<<1)
 293 #define PWR_DAC_REF                                     (0x1)
 294
 295
 296 //Power managment addition 2(0x3C),0:Disable,1:Enable
 297 #define PWR_PLL1                                        (0x1<<15)
 298 #define PWR_PLL2                                        (0x1<<14)
 299 #define PWR_MIXER_VREF                          (0x1<<13)
 300 #define PWR_TEMP_SENSOR                         (0x1<<12)
 301 #define PWR_AUX_ADC                                     (0x1<<11)
 302 #define PWR_VOICE_CLOCK                         (0x1<<10)
 303 #define PWR_L_DAC_CLK                           (0x1<<9)
 304 #define PWR_R_DAC_CLK                           (0x1<<8)
 305 #define PWR_L_ADC_CLK                           (0x1<<7)
 306 #define PWR_R_ADC_CLK                           (0x1<<6)
 307 #define PWR_L_HP_MIXER                          (0x1<<5)
 308 #define PWR_R_HP_MIXER                          (0x1<<4)
 309 #define PWR_SPK_MIXER                           (0x1<<3)
 310 #define PWR_MONO_MIXER                          (0x1<<2)
 311 #define PWR_L_ADC_REC_MIXER                     (0x1<<1)
 312 #define PWR_R_ADC_REC_MIXER                     (0x1)
 313
 314
 315 //Power managment addition 3(0x3E),0:Disable,1:Enable
 316 #define PWR_OSC_EN                                      (0x1<<15)
 317 #define PWR_AUXOUT_VOL                          (0x1<<14)
 318 #define PWR_SPK_OUT                                     (0x1<<13)
 319 #define PWR_SPK_OUT_N                           (0x1<<12)
 320 #define PWR_HP_L_OUT_VOL                        (0x1<<11)
 321 #define PWR_HP_R_OUT_VOL                        (0x1<<10)
 322 #define PWR_VODSP_INTERFACE                     (0x1<<9)
 323 #define PWR_I2C_FOR_VODSP                       (0x1<<8)
 324 #define PWR_LINE_IN_L                           (0x1<<7)
 325 #define PWR_LINE_IN_R                           (0x1<<6)
 326 #define PWR_PHONE_VOL                           (0x1<<5)
 327 #define PWR_PHONE_ADMIXER                       (0x1<<4)
 328 #define PWR_MIC1_VOL_CTRL                       (0x1<<3)
 329 #define PWR_MIC2_VOL_CTRL                       (0x1<<2)
 330 #define PWR_MIC1_BOOST                          (0x1<<1)
 331 #define PWR_MIC2_BOOST                          (0x1)
 332
 333 //General Purpose Control Register 1(0x40)
 334 #define GP_CLK_FROM_PLL                         (0x1<<15)
 335 #define GP_CLK_FROM_MCLK                        (0x0<<15)
 336
 337 #define GP_DAC_HI_PA_ENA                        (0x1<<10)       //Enable DAC High Pass Filter
 338
 339 #define GP_EXTCLK_S_SEL_PLL2            (0x1<<6)
 340 #define GP_EXTCLK_S_SEL_PLL1            (0x0<<6)
 341
 342 #define GP_EXTCLK_DIR_SEL_OUTPUT        (0x1<<5)
 343 #define GP_EXTCLK_DIR_SEL_INTPUT        (0x0<<5)
 344
 345 #define GP_VOSYS_S_SEL_PLL2                     (0x0<<4)
 346 #define GP_VOSYS_S_SEL_EXTCLK           (0x1<<4)
 347
 348 #define GP_SPK_AMP_CTRL_MASK            (0x7<<1)
 349 #define GP_SPK_AMP_CTRL_RATIO_225       (0x0<<1)                //2.25 Vdd
 350 #define GP_SPK_AMP_CTRL_RATIO_200       (0x1<<1)                //2.00 Vdd
 351 #define GP_SPK_AMP_CTRL_RATIO_175       (0x2<<1)                //1.75 Vdd
 352 #define GP_SPK_AMP_CTRL_RATIO_150       (0x3<<1)                //1.50 Vdd
 353 #define GP_SPK_AMP_CTRL_RATIO_125       (0x4<<1)                //1.25 Vdd
 354 #define GP_SPK_AMP_CTRL_RATIO_100       (0x5<<1)                //1.00 Vdd
 355
 356 //General Purpose Control Register 2(0x42)
 357 #define GP2_PLL1_SOUR_SEL_MASK          (0x3<<12)
 358 #define GP2_PLL1_SOUR_SEL_MCLK          (0x0<<12)
 359 #define GP2_PLL1_SOUR_SEL_BCLK          (0x2<<12)
 360 #define GP2_PLL1_SOUR_SEL_VBCLK         (0x3<<12)
 361
 362 //PLL Control(0x44)
 363 #define PLL_M_CODE_MASK                         0xF                             //PLL M code mask
 364 #define PLL_K_CODE_MASK                         (0x7<<4)                //PLL K code mask
 365 #define PLL_BYPASS_N                            (0x1<<7)                //bypass PLL N code
 366 #define PLL_N_CODE_MASK                         (0xFF<<8)               //PLL N code mask
 367
 368 #define PLL_CTRL_M_VAL(m)               ((m)&0xf)
 369 #define PLL_CTRL_K_VAL(k)               (((k)&0x7)<<4)
 370 #define PLL_CTRL_N_VAL(n)               (((n)&0xff)<<8)
 371
 372 //PLL2 CONTROL
 373 #define PLL2_ENA                                        (0x1<<15)
 374 #define PLL_2_RATIO_8X                          (0x0)
 375 #define PLL_2_RATIO_16X                         (0x1)
 376
 377 //LDO Control(0x48)
 378 #define LDO_ENABLE                                      (0x1<<15)
 379
 380 #define LDO_OUT_VOL_CTRL_MASK           (0xf<<0)
 381 #define LDO_OUT_VOL_CTRL_1_55V          (0xf<<0)
 382 #define LDO_OUT_VOL_CTRL_1_50V          (0xe<<0)
 383 #define LDO_OUT_VOL_CTRL_1_45V          (0xd<<0)
 384 #define LDO_OUT_VOL_CTRL_1_40V          (0xc<<0)
 385 #define LDO_OUT_VOL_CTRL_1_35V          (0xb<<0)
 386 #define LDO_OUT_VOL_CTRL_1_30V          (0xa<<0)
 387 #define LDO_OUT_VOL_CTRL_1_25V          (0x9<<0)
 388 #define LDO_OUT_VOL_CTRL_1_20V          (0x8<<0)
 389 #define LDO_OUT_VOL_CTRL_1_15V          (0x7<<0)
 390 #define LDO_OUT_VOL_CTRL_1_05V          (0x6<<0)
 391 #define LDO_OUT_VOL_CTRL_1_00V          (0x5<<0)
 392 #define LDO_OUT_VOL_CTRL_0_95V          (0x4<<0)
 393 #define LDO_OUT_VOL_CTRL_0_90V          (0x3<<0)
 394 #define LDO_OUT_VOL_CTRL_0_85V          (0x2<<0)
 395 #define LDO_OUT_VOL_CTRL_0_80V          (0x1<<0)
 396 #define LDO_OUT_VOL_CTRL_0_75V          (0x0<<0)
 397
 398
 399
 400 //GPIO Pin Configuration(0x4C)
 401 #define GPIO_1                                          (0x1<<1)
 402 #define GPIO_2                                          (0x1<<2)
 403 #define GPIO_3                                          (0x1<<3)
 404 #define GPIO_4                                          (0x1<<4)
 405 #define GPIO_5                                          (0x1<<5)
 406
 407
 408 ////INTERRUPT CONTROL(0x5E)
 409 #define DISABLE_FAST_VREG                       (0x1<<15)
 410
 411 #define AVC_TARTGET_SEL_MASK            (0x3<<12)
 412 #define AVC_TARTGET_SEL_NONE            (0x0<<12)
 413 #define AVC_TARTGET_SEL_R                       (0x1<<12)
 414 #define AVC_TARTGET_SEL_L                       (0x2<<12)
 415 #define AVC_TARTGET_SEL_BOTH            (0x3<<12)
 416
 417 #define HP_DEPOP_MODE2_EN                       (0x1<<8)
 418 #define HP_DEPOP_MODE1_EN                       (0x1<<9)
 419 #define HP_L_M_UM_DEPOP_EN                      (0x1<<7)
 420 #define HP_R_M_UM_DEPOP_EN                      (0x1<<6)
 421 #define M_UM_DEPOP_EN                           (0x1<<5)
 422
 423 //Stereo DAC Clock Control 1(0x60)
 424 #define STEREO_BCLK_DIV1_MASK           (0xF<<12)
 425 #define STEREO_BCLK_DIV1_1                      (0x0<<12)
 426 #define STEREO_BCLK_DIV1_2                      (0x1<<12)
 427 #define STEREO_BCLK_DIV1_3                      (0x2<<12)
 428 #define STEREO_BCLK_DIV1_4                      (0x3<<12)
 429 #define STEREO_BCLK_DIV1_5                      (0x4<<12)
 430 #define STEREO_BCLK_DIV1_6                      (0x5<<12)
 431 #define STEREO_BCLK_DIV1_7                      (0x6<<12)
 432 #define STEREO_BCLK_DIV1_8                      (0x7<<12)
 433 #define STEREO_BCLK_DIV1_9                      (0x8<<12)
 434 #define STEREO_BCLK_DIV1_10                     (0x9<<12)
 435 #define STEREO_BCLK_DIV1_11                     (0xA<<12)
 436 #define STEREO_BCLK_DIV1_12                     (0xB<<12)
 437 #define STEREO_BCLK_DIV1_13                     (0xC<<12)
 438 #define STEREO_BCLK_DIV1_14                     (0xD<<12)
 439 #define STEREO_BCLK_DIV1_15                     (0xE<<12)
 440 #define STEREO_BCLK_DIV1_16                     (0xF<<12)
 441
 442 #define STEREO_BCLK_DIV2_MASK           (0x7<<8)
 443 #define STEREO_BCLK_DIV2_2                      (0x0<<8)
 444 #define STEREO_BCLK_DIV2_4                      (0x1<<8)
 445 #define STEREO_BCLK_DIV2_8                      (0x2<<8)
 446 #define STEREO_BCLK_DIV2_16                     (0x3<<8)
 447 #define STEREO_BCLK_DIV2_32                     (0x4<<8)
 448
 449 #define STEREO_AD_LRCK_DIV1_MASK        (0xF<<4)
 450 #define STEREO_AD_LRCK_DIV1_1           (0x0<<4)
 451 #define STEREO_AD_LRCK_DIV1_2           (0x1<<4)
 452 #define STEREO_AD_LRCK_DIV1_3           (0x2<<4)
 453 #define STEREO_AD_LRCK_DIV1_4           (0x3<<4)
 454 #define STEREO_AD_LRCK_DIV1_5           (0x4<<4)
 455 #define STEREO_AD_LRCK_DIV1_6           (0x5<<4)
 456 #define STEREO_AD_LRCK_DIV1_7           (0x6<<4)
 457 #define STEREO_AD_LRCK_DIV1_8           (0x7<<4)
 458 #define STEREO_AD_LRCK_DIV1_9           (0x8<<4)
 459 #define STEREO_AD_LRCK_DIV1_10          (0x9<<4)
 460 #define STEREO_AD_LRCK_DIV1_11          (0xA<<4)
 461 #define STEREO_AD_LRCK_DIV1_12          (0xB<<4)
 462 #define STEREO_AD_LRCK_DIV1_13          (0xC<<4)
 463 #define STEREO_AD_LRCK_DIV1_14          (0xD<<4)
 464 #define STEREO_AD_LRCK_DIV1_15          (0xE<<4)
 465 #define STEREO_AD_LRCK_DIV1_16          (0xF<<4)
 466
 467 #define STEREO_AD_LRCK_DIV2_MASK        (0x7<<1)
 468 #define STEREO_AD_LRCK_DIV2_2           (0x0<<1)
 469 #define STEREO_AD_LRCK_DIV2_4           (0x1<<1)
 470 #define STEREO_AD_LRCK_DIV2_8           (0x2<<1)
 471 #define STEREO_AD_LRCK_DIV2_16          (0x3<<1)
 472 #define STEREO_AD_LRCK_DIV2_32          (0x4<<1)
 473
 474 #define STEREO_DA_LRCK_DIV_MASK         (1)
 475 #define STEREO_DA_LRCK_DIV_32           (0)
 476 #define STEREO_DA_LRCK_DIV_64           (1)
 477
 478 //Stereo DAC Clock Control 2(0x62)
 479 #define STEREO_DA_FILTER_DIV1_MASK      (0xF<<12)
 480 #define STEREO_DA_FILTER_DIV1_1         (0x0<<12)
 481 #define STEREO_DA_FILTER_DIV1_2         (0x1<<12)
 482 #define STEREO_DA_FILTER_DIV1_3         (0x2<<12)
 483 #define STEREO_DA_FILTER_DIV1_4         (0x3<<12)
 484 #define STEREO_DA_FILTER_DIV1_5         (0x4<<12)
 485 #define STEREO_DA_FILTER_DIV1_6         (0x5<<12)
 486 #define STEREO_DA_FILTER_DIV1_7         (0x6<<12)
 487 #define STEREO_DA_FILTER_DIV1_8         (0x7<<12)
 488 #define STEREO_DA_FILTER_DIV1_9         (0x8<<12)
 489 #define STEREO_DA_FILTER_DIV1_10        (0x9<<12)
 490 #define STEREO_DA_FILTER_DIV1_11        (0xA<<12)
 491 #define STEREO_DA_FILTER_DIV1_12        (0xB<<12)
 492 #define STEREO_DA_FILTER_DIV1_13        (0xC<<12)
 493 #define STEREO_DA_FILTER_DIV1_14        (0xD<<12)
 494 #define STEREO_DA_FILTER_DIV1_15        (0xE<<12)
 495 #define STEREO_DA_FILTER_DIV1_16        (0xF<<12)
 496
 497 #define STEREO_DA_FILTER_DIV2_MASK      (0x7<<9)
 498 #define STEREO_DA_FILTER_DIV2_2         (0x0<<9)
 499 #define STEREO_DA_FILTER_DIV2_4         (0x1<<9)
 500 #define STEREO_DA_FILTER_DIV2_8         (0x2<<9)
 501 #define STEREO_DA_FILTER_DIV2_16        (0x3<<9)
 502 #define STEREO_DA_FILTER_DIV2_32        (0x4<<9)
 503
 504 #define STEREO_AD_FILTER_DIV1_MASK      (0xF<<4)
 505 #define STEREO_AD_FILTER_DIV1_1         (0x0<<4)
 506 #define STEREO_AD_FILTER_DIV1_2         (0x1<<4)
 507 #define STEREO_AD_FILTER_DIV1_3         (0x2<<4)
 508 #define STEREO_AD_FILTER_DIV1_4         (0x3<<4)
 509 #define STEREO_AD_FILTER_DIV1_5         (0x4<<4)
 510 #define STEREO_AD_FILTER_DIV1_6         (0x5<<4)
 511 #define STEREO_AD_FILTER_DIV1_7         (0x6<<4)
 512 #define STEREO_AD_FILTER_DIV1_8         (0x7<<4)
 513 #define STEREO_AD_FILTER_DIV1_9         (0x8<<4)
 514 #define STEREO_AD_FILTER_DIV1_10        (0x9<<4)
 515 #define STEREO_AD_FILTER_DIV1_11        (0xA<<4)
 516 #define STEREO_AD_FILTER_DIV1_12        (0xB<<4)
 517 #define STEREO_AD_FILTER_DIV1_13        (0xC<<4)
 518 #define STEREO_AD_FILTER_DIV1_14        (0xD<<4)
 519 #define STEREO_AD_FILTER_DIV1_15        (0xE<<4)
 520 #define STEREO_AD_FILTER_DIV1_16        (0xF<<4)
 521
 522 #define STEREO_AD_FILTER_DIV2_MASK      (0x7<<1)
 523 #define STEREO_AD_FILTER_DIV2_1         (0x0<<1)
 524 #define STEREO_AD_FILTER_DIV2_2         (0x1<<1)
 525 #define STEREO_AD_FILTER_DIV2_4         (0x2<<1)
 526 #define STEREO_AD_FILTER_DIV2_8         (0x3<<1)
 527 #define STEREO_AD_FILTER_DIV2_16        (0x4<<1)
 528 #define STEREO_AD_FILTER_DIV2_32        (0x5<<1)
 529
 530
 531 //Voice DAC PCM Clock Control 1(0x64)
 532 #define VOICE_BCLK_DIV1_MASK            (0xF<<12)
 533 #define VOICE_BCLK_DIV1_1                       (0x0<<12)
 534 #define VOICE_BCLK_DIV1_2                       (0x1<<12)
 535 #define VOICE_BCLK_DIV1_3                       (0x2<<12)
 536 #define VOICE_BCLK_DIV1_4                       (0x3<<12)
 537 #define VOICE_BCLK_DIV1_5                       (0x4<<12)
 538 #define VOICE_BCLK_DIV1_6                       (0x5<<12)
 539 #define VOICE_BCLK_DIV1_7                       (0x6<<12)
 540 #define VOICE_BCLK_DIV1_8                       (0x7<<12)
 541 #define VOICE_BCLK_DIV1_9                       (0x8<<12)
 542 #define VOICE_BCLK_DIV1_10                      (0x9<<12)
 543 #define VOICE_BCLK_DIV1_11                      (0xA<<12)
 544 #define VOICE_BCLK_DIV1_12                      (0xB<<12)
 545 #define VOICE_BCLK_DIV1_13                      (0xC<<12)
 546 #define VOICE_BCLK_DIV1_14                      (0xD<<12)
 547 #define VOICE_BCLK_DIV1_15                      (0xE<<12)
 548 #define VOICE_BCLK_DIV1_16                      (0xF<<12)
 549
 550 #define VOICE_BCLK_DIV2_MASK            (0x7<<8)
 551 #define VOICE_BCLK_DIV2_2                       (0x0<<8)
 552 #define VOICE_BCLK_DIV2_4                       (0x1<<8)
 553 #define VOICE_BCLK_DIV2_8                       (0x2<<8)
 554 #define VOICE_BCLK_DIV2_16                      (0x3<<8)
 555 #define VOICE_BCLK_DIV2_32                      (0x4<<8)
 556
 557 #define VOICE_AD_LRCK_DIV1_MASK (0xF<<4)
 558 #define VOICE_AD_LRCK_DIV1_1            (0x0<<4)
 559 #define VOICE_AD_LRCK_DIV1_2            (0x1<<4)
 560 #define VOICE_AD_LRCK_DIV1_3            (0x2<<4)
 561 #define VOICE_AD_LRCK_DIV1_4            (0x3<<4)
 562 #define VOICE_AD_LRCK_DIV1_5            (0x4<<4)
 563 #define VOICE_AD_LRCK_DIV1_6            (0x5<<4)
 564 #define VOICE_AD_LRCK_DIV1_7            (0x6<<4)
 565 #define VOICE_AD_LRCK_DIV1_8            (0x7<<4)
 566 #define VOICE_AD_LRCK_DIV1_9            (0x8<<4)
 567 #define VOICE_AD_LRCK_DIV1_10           (0x9<<4)
 568 #define VOICE_AD_LRCK_DIV1_11           (0xA<<4)
 569 #define VOICE_AD_LRCK_DIV1_12           (0xB<<4)
 570 #define VOICE_AD_LRCK_DIV1_13           (0xC<<4)
 571 #define VOICE_AD_LRCK_DIV1_14           (0xD<<4)
 572 #define VOICE_AD_LRCK_DIV1_15           (0xE<<4)
 573 #define VOICE_AD_LRCK_DIV1_16           (0xF<<4)
 574
 575 #define VOICE_AD_LRCK_DIV2_MASK (0x7<<1)
 576 #define VOICE_AD_LRCK_DIV2_2            (0x0<<1)
 577 #define VOICE_AD_LRCK_DIV2_4            (0x1<<1)
 578 #define VOICE_AD_LRCK_DIV2_8            (0x2<<1)
 579 #define VOICE_AD_LRCK_DIV2_16           (0x3<<1)
 580 #define VOICE_AD_LRCK_DIV2_32           (0x4<<1)
 581
 582 #define VOICE_DA_LRCK_DIV_MASK          (1)
 583 #define VOICE_DA_LRCK_DIV_32            (0)
 584 #define VOICE_DA_LRCK_DIV_64            (1)
 585
 586
 587 //Psedueo Stereo & Spatial Effect Block Control(0x68)
 588 #define SPATIAL_CTRL_EN                         (0x1<<15)
 589 #define ALL_PASS_FILTER_EN                      (0x1<<14)
 590 #define PSEUDO_STEREO_EN                        (0x1<<13)
 591 #define STEREO_EXPENSION_EN                     (0x1<<12)
 592
 593 #define SPATIAL_3D_GAIN1_MASK                   (0x3<<10)
 594 #define SPATIAL_3D_GAIN1_1_0                    (0x0<<10)
 595 #define SPATIAL_3D_GAIN1_1_5                    (0x1<<10)
 596 #define SPATIAL_3D_GAIN1_2_0                    (0x2<<10)
 597
 598 #define SPATIAL_3D_RATIO1_MASK                  (0x3<<8)
 599 #define SPATIAL_3D_RATIO1_0_0                   (0x0<<8)
 600 #define SPATIAL_3D_RATIO1_0_66                  (0x1<<8)
 601 #define SPATIAL_3D_RATIO1_1_0                   (0x2<<8)
 602
 603 #define SPATIAL_3D_GAIN2_MASK                   (0x3<<6)
 604 #define SPATIAL_3D_GAIN2_1_0                    (0x0<<6)
 605 #define SPATIAL_3D_GAIN2_1_5                    (0x1<<6)
 606 #define SPATIAL_3D_GAIN2_2_0                    (0x2<<6)
 607
 608 #define SPATIAL_3D_RATIO2_MASK                  (0x3<<4)
 609 #define SPATIAL_3D_RATIO2_0_0                   (0x0<<4)
 610 #define SPATIAL_3D_RATIO2_0_66                  (0x1<<4)
 611 #define SPATIAL_3D_RATIO2_1_0                   (0x2<<4)
 612
 613 #define APF_MASK                                        (0x3)
 614 #define APF_FOR_48K                                     (0x3)
 615 #define APF_FOR_44_1K                           (0x2)
 616 #define APF_FOR_32K                                     (0x1)
 617
 618 //EQ Control and Status /ADC HPF Control(0x6E)
 619 #define EN_HW_EQ_BLK                    (0x1<<15)               //HW EQ block control
 620
 621 #define EQ_SOUR_SEL_DAC                 (0x0<<14)
 622 #define EQ_SOUR_SEL_ADC                 (0x1<<14)
 623
 624 #define EQ_CHANGE_EN                    (0x1<<7)                //EQ parameter update control
 625 #define EN_HW_EQ_HPF                    (0x1<<4)                //EQ High Pass Filter Control
 626 #define EN_HW_EQ_BP3                    (0x1<<3)                //EQ Band-3 Control
 627 #define EN_HW_EQ_BP2                    (0x1<<2)                //EQ Band-2 Control
 628 #define EN_HW_EQ_BP1                    (0x1<<1)                //EQ Band-1 Control
 629 #define EN_HW_EQ_LPF                    (0x1<<0)                //EQ Low Pass Filter Control
 630
 631
 632 //AEC register command(0x74)
 633
 634 #define VODSP_BUSY                                      (0x1<<15)       //VODSP I2C busy flag
 635
 636 #define VODSP_S_FROM_VODSP_RD           (0x0<<14)
 637 #define VODSP_S_FROM_MX72                       (0x1<<14)
 638
 639 #define VODSP_CLK_SEL_MASK                      (0x3<<12)       //VODSP CLK select Mask
 640 #define VODSP_CLK_SEL_12_288M           (0x0<<12)       //VODSP CLK select 12.288Mhz
 641 #define VODSP_CLK_SEL_6_144M            (0x1<<12)       //VODSP CLK select 6.144Mhz
 642 #define VODSP_CLK_SEL_3_072M            (0x2<<12)       //VODSP CLK select 3.072Mhz
 643 #define VODSP_CLK_SEL_2_048M            (0x3<<12)       //VODSP CLK select 2.0488Mhz
 644
 645 #define VODSP_READ_ENABLE                       (0x1<<9)        //VODSP Read Enable
 646 #define VODSP_WRITE_ENABLE                      (0x1<<8)        //VODSP Write Enable
 647
 648 #define VODSP_CMD_MASK                          (0xFF<<0)
 649 #define VODSP_CMD_MW                            (0x3B<<0)               //Memory Write
 650 #define VODSP_CMD_MR                            (0x37<<0)               //Memory Read
 651 #define VODSP_CMD_RR                            (0x60<<0)               //Register Read
 652 #define VODSP_CMD_RW                            (0x68<<0)               //Register Write
 653
 654
 655 /*************************************************************************************************
 656   *Index register of codec
 657   *************************************************************************************************/
 658 /*Index(0x20) for Auto Volume Control*/
 659 #define AVC_CH_SEL_MASK                         (0x1<<7)
 660 #define AVC_CH_SEL_L_CH                         (0x0<<7)
 661 #define AVC_CH_SEL_R_CH                         (0x1<<7)
 662 #define ENABLE_AVC_GAIN_CTRL            (0x1<<15)
 663 //*************************************************************************************************
 664 //*************************************************************************************************
 665
 666 #define REALTEK_HWDEP 0
 667
 668 #if REALTEK_HWDEP
 669
 670 struct rt56xx_reg_state
 671 {
 672         unsigned int reg_index;
 673         unsigned int reg_value;
 674 };
 675
 676 struct rt56xx_cmd
 677 {
 678         size_t number;
 679         struct rt56xx_reg_state __user *buf;
 680 };
 681
 682
 683 enum
 684 {
 685         RT_READ_CODEC_REG_IOCTL = _IOR('R', 0x01, struct rt56xx_cmd),
 686         RT_READ_ALL_CODEC_REG_IOCTL = _IOR('R', 0x02, struct rt56xx_cmd),
 687         RT_WRITE_CODEC_REG_IOCTL = _IOW('R', 0x03, struct rt56xx_cmd),
 688 };
 689
 690 #endif
 691
 692
 693 enum pll_sel
 694 {
 695         RT5625_PLL1_FROM_MCLK = 0,
 696         RT5625_PLL1_FROM_BCLK,
 697         RT5625_PLL1_FROM_VBCLK,
 698 };
 699
 700 enum AEC_MODE
 701 {
 702         PCM_IN_PCM_OUT = 0,
 703         ANALOG_IN_ANALOG_OUT,
 704         DAC_IN_ADC_OUT,
 705         VODSP_AEC_DISABLE
 706 };
 707
 708 enum
 709 {
 710         PCM_MASTER_MODE_A=0,
 711         PCM_MASTER_MODE_B,
 712         PCM_SLAVE_MODE_A,
 713         PCM_SLAVE_MODE_B,
 714 };
 715
 716
 717 enum RT5625_FUNC_SEL
 718 {
 719         RT5625_AEC_DISABLE =0,
 720         RT5625_AEC_PCM_IN_OUT,
 721         RT5625_AEC_IIS_IN_OUT,
 722         RT5625_AEC_ANALOG_IN_OUT,
 723
 724 };
 725
 726
 727 struct rt5625_setup_data {
 728         int i2c_bus;
 729         int i2c_address;
 730 };
 731
 732 typedef struct
 733 {
 734         unsigned short int VoiceDSPIndex;
 735         unsigned short int VoiceDSPValue;
 736
 737 }Voice_DSP_Reg;
 738
 739 extern struct snd_soc_dai rt5625_dai[];
 740 extern struct snd_soc_codec_device soc_codec_dev_rt5625;
 741
 742 #endif