2 * rt5639.h -- RT5639 ALSA SoC audio driver
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
16 #define RT5639_RESET 0x00
17 #define RT5639_VENDOR_ID 0xfd
18 #define RT5639_VENDOR_ID1 0xfe
19 #define RT5639_VENDOR_ID2 0xff
21 #define RT5639_SPK_VOL 0x01
22 #define RT5639_HP_VOL 0x02
23 #define RT5639_OUTPUT 0x03
24 #define RT5639_MONO_OUT 0x04
26 #define RT5639_DUMMY_PR3F 0x05
28 #define RT5639_IN1_IN2 0x0d
29 #define RT5639_IN3_IN4 0x0e
30 #define RT5639_INL_INR_VOL 0x0f
31 /* I/O - ADC/DAC/DMIC */
32 #define RT5639_DAC1_DIG_VOL 0x19
33 #define RT5639_DAC2_DIG_VOL 0x1a
34 #define RT5639_DAC2_CTRL 0x1b
35 #define RT5639_ADC_DIG_VOL 0x1c
36 #define RT5639_ADC_DATA 0x1d
37 #define RT5639_ADC_BST_VOL 0x1e
39 #define RT5639_STO_ADC_MIXER 0x27
40 #define RT5639_MONO_ADC_MIXER 0x28
41 #define RT5639_AD_DA_MIXER 0x29
42 #define RT5639_STO_DAC_MIXER 0x2a
43 #define RT5639_MONO_DAC_MIXER 0x2b
44 #define RT5639_DIG_MIXER 0x2c
45 #define RT5639_DSP_PATH1 0x2d
46 #define RT5639_DSP_PATH2 0x2e
47 #define RT5639_DIG_INF_DATA 0x2f
49 #define RT5639_REC_L1_MIXER 0x3b
50 #define RT5639_REC_L2_MIXER 0x3c
51 #define RT5639_REC_R1_MIXER 0x3d
52 #define RT5639_REC_R2_MIXER 0x3e
54 #define RT5639_HPO_MIXER 0x45
55 #define RT5639_SPK_L_MIXER 0x46
56 #define RT5639_SPK_R_MIXER 0x47
57 #define RT5639_SPO_L_MIXER 0x48
58 #define RT5639_SPO_R_MIXER 0x49
59 #define RT5639_SPO_CLSD_RATIO 0x4a
60 #define RT5639_MONO_MIXER 0x4c
61 #define RT5639_OUT_L1_MIXER 0x4d
62 #define RT5639_OUT_L2_MIXER 0x4e
63 #define RT5639_OUT_L3_MIXER 0x4f
64 #define RT5639_OUT_R1_MIXER 0x50
65 #define RT5639_OUT_R2_MIXER 0x51
66 #define RT5639_OUT_R3_MIXER 0x52
67 #define RT5639_LOUT_MIXER 0x53
69 #define RT5639_PWR_DIG1 0x61
70 #define RT5639_PWR_DIG2 0x62
71 #define RT5639_PWR_ANLG1 0x63
72 #define RT5639_PWR_ANLG2 0x64
73 #define RT5639_PWR_MIXER 0x65
74 #define RT5639_PWR_VOL 0x66
75 /* Private Register Control */
76 #define RT5639_PRIV_INDEX 0x6a
77 #define RT5639_PRIV_DATA 0x6c
78 /* Format - ADC/DAC */
79 #define RT5639_I2S1_SDP 0x70
80 #define RT5639_I2S2_SDP 0x71
81 #define RT5639_I2S3_SDP 0x72
82 #define RT5639_ADDA_CLK1 0x73
83 #define RT5639_ADDA_CLK2 0x74
84 #define RT5639_DMIC 0x75
85 /* Function - Analog */
86 #define RT5639_GLB_CLK 0x80
87 #define RT5639_PLL_CTRL1 0x81
88 #define RT5639_PLL_CTRL2 0x82
89 #define RT5639_ASRC_1 0x83
90 #define RT5639_ASRC_2 0x84
91 #define RT5639_ASRC_3 0x85
92 #define RT5639_ASRC_4 0x89
93 #define RT5639_ASRC_5 0x8a
94 #define RT5639_HP_OVCD 0x8b
95 #define RT5639_CLS_D_OVCD 0x8c
96 #define RT5639_CLS_D_OUT 0x8d
97 #define RT5639_DEPOP_M1 0x8e
98 #define RT5639_DEPOP_M2 0x8f
99 #define RT5639_DEPOP_M3 0x90
100 #define RT5639_CHARGE_PUMP 0x91
101 #define RT5639_PV_DET_SPK_G 0x92
102 #define RT5639_MICBIAS 0x93
103 /* Function - Digital */
104 #define RT5639_EQ_CTRL1 0xb0
105 #define RT5639_EQ_CTRL2 0xb1
106 #define RT5639_WIND_FILTER 0xb2
107 #define RT5639_DRC_AGC_1 0xb4
108 #define RT5639_DRC_AGC_2 0xb5
109 #define RT5639_DRC_AGC_3 0xb6
110 #define RT5639_SVOL_ZC 0xb7
111 #define RT5639_ANC_CTRL1 0xb8
112 #define RT5639_ANC_CTRL2 0xb9
113 #define RT5639_ANC_CTRL3 0xba
114 #define RT5639_JD_CTRL 0xbb
115 #define RT5639_ANC_JD 0xbc
116 #define RT5639_IRQ_CTRL1 0xbd
117 #define RT5639_IRQ_CTRL2 0xbe
118 #define RT5639_INT_IRQ_ST 0xbf
119 #define RT5639_GPIO_CTRL1 0xc0
120 #define RT5639_GPIO_CTRL2 0xc1
121 #define RT5639_GPIO_CTRL3 0xc2
122 #define RT5639_DSP_CTRL1 0xc4
123 #define RT5639_DSP_CTRL2 0xc5
124 #define RT5639_DSP_CTRL3 0xc6
125 #define RT5639_DSP_CTRL4 0xc7
126 #define RT5639_PGM_REG_ARR1 0xc8
127 #define RT5639_PGM_REG_ARR2 0xc9
128 #define RT5639_PGM_REG_ARR3 0xca
129 #define RT5639_PGM_REG_ARR4 0xcb
130 #define RT5639_PGM_REG_ARR5 0xcc
131 #define RT5639_SCB_FUNC 0xcd
132 #define RT5639_SCB_CTRL 0xce
133 #define RT5639_BASE_BACK 0xcf
134 #define RT5639_MP3_PLUS1 0xd0
135 #define RT5639_MP3_PLUS2 0xd1
136 #define RT5639_3D_HP 0xd2
137 #define RT5639_ADJ_HPF 0xd3
138 #define RT5639_HP_CALIB_AMP_DET 0xd6
139 #define RT5639_HP_CALIB2 0xd7
140 #define RT5639_SV_ZCD1 0xd9
141 #define RT5639_SV_ZCD2 0xda
142 /* General Control */
143 #define RT5639_GEN_CTRL1 0xfa
144 #define RT5639_GEN_CTRL2 0xfb
145 #define RT5639_GEN_CTRL3 0xfc
148 /* Index of Codec Private Register definition */
149 #define RT5639_BIAS_CUR1 0x12
150 #define RT5639_BIAS_CUR3 0x14
151 #define RT5639_CLSD_INT_REG1 0x1c
152 #define RT5639_CHPUMP_INT_REG1 0x24
153 #define RT5639_MAMP_INT_REG2 0x37
154 #define RT5639_CHOP_DAC_ADC 0x3d
155 #define RT5639_MIXER_INT_REG 0x3f
156 #define RT5639_3D_SPK 0x63
157 #define RT5639_WND_1 0x6c
158 #define RT5639_WND_2 0x6d
159 #define RT5639_WND_3 0x6e
160 #define RT5639_WND_4 0x6f
161 #define RT5639_WND_5 0x70
162 #define RT5639_WND_8 0x73
163 #define RT5639_DIP_SPK_INF 0x75
164 #define RT5639_HP_DCC_INT1 0x77
165 #define RT5639_EQ_BW_LOP 0xa0
166 #define RT5639_EQ_GN_LOP 0xa1
167 #define RT5639_EQ_FC_BP1 0xa2
168 #define RT5639_EQ_BW_BP1 0xa3
169 #define RT5639_EQ_GN_BP1 0xa4
170 #define RT5639_EQ_FC_BP2 0xa5
171 #define RT5639_EQ_BW_BP2 0xa6
172 #define RT5639_EQ_GN_BP2 0xa7
173 #define RT5639_EQ_FC_BP3 0xa8
174 #define RT5639_EQ_BW_BP3 0xa9
175 #define RT5639_EQ_GN_BP3 0xaa
176 #define RT5639_EQ_FC_BP4 0xab
177 #define RT5639_EQ_BW_BP4 0xac
178 #define RT5639_EQ_GN_BP4 0xad
179 #define RT5639_EQ_FC_HIP1 0xae
180 #define RT5639_EQ_GN_HIP1 0xaf
181 #define RT5639_EQ_FC_HIP2 0xb0
182 #define RT5639_EQ_BW_HIP2 0xb1
183 #define RT5639_EQ_GN_HIP2 0xb2
184 #define RT5639_EQ_PRE_VOL 0xb3
185 #define RT5639_EQ_PST_VOL 0xb4
188 /* global definition */
189 #define RT5639_L_MUTE (0x1 << 15)
190 #define RT5639_L_MUTE_SFT 15
191 #define RT5639_VOL_L_MUTE (0x1 << 14)
192 #define RT5639_VOL_L_SFT 14
193 #define RT5639_R_MUTE (0x1 << 7)
194 #define RT5639_R_MUTE_SFT 7
195 #define RT5639_VOL_R_MUTE (0x1 << 6)
196 #define RT5639_VOL_R_SFT 6
197 #define RT5639_L_VOL_MASK (0x3f << 8)
198 #define RT5639_L_VOL_SFT 8
199 #define RT5639_R_VOL_MASK (0x3f)
200 #define RT5639_R_VOL_SFT 0
202 /* IN1 and IN2 Control (0x0d) */
203 /* IN3 and IN4 Control (0x0e) */
204 #define RT5639_BST_MASK1 (0xf<<12)
205 #define RT5639_BST_SFT1 12
206 #define RT5639_BST_MASK2 (0xf<<8)
207 #define RT5639_BST_SFT2 8
208 #define RT5639_IN_DF1 (0x1 << 7)
209 #define RT5639_IN_SFT1 7
210 #define RT5639_IN_DF2 (0x1 << 6)
211 #define RT5639_IN_SFT2 6
213 /* INL and INR Volume Control (0x0f) */
214 #define RT5639_INL_SEL_MASK (0x1 << 15)
215 #define RT5639_INL_SEL_SFT 15
216 #define RT5639_INL_SEL_IN4P (0x0 << 15)
217 #define RT5639_INL_SEL_MONOP (0x1 << 15)
218 #define RT5639_INL_VOL_MASK (0x1f << 8)
219 #define RT5639_INL_VOL_SFT 8
220 #define RT5639_INR_SEL_MASK (0x1 << 7)
221 #define RT5639_INR_SEL_SFT 7
222 #define RT5639_INR_SEL_IN4N (0x0 << 7)
223 #define RT5639_INR_SEL_MONON (0x1 << 7)
224 #define RT5639_INR_VOL_MASK (0x1f)
225 #define RT5639_INR_VOL_SFT 0
227 /* DAC1 Digital Volume (0x19) */
228 #define RT5639_DAC_L1_VOL_MASK (0xff << 8)
229 #define RT5639_DAC_L1_VOL_SFT 8
230 #define RT5639_DAC_R1_VOL_MASK (0xff)
231 #define RT5639_DAC_R1_VOL_SFT 0
233 /* DAC2 Digital Volume (0x1a) */
234 #define RT5639_DAC_L2_VOL_MASK (0xff << 8)
235 #define RT5639_DAC_L2_VOL_SFT 8
236 #define RT5639_DAC_R2_VOL_MASK (0xff)
237 #define RT5639_DAC_R2_VOL_SFT 0
239 /* DAC2 Control (0x1b) */
240 #define RT5639_M_DAC_L2_VOL (0x1 << 13)
241 #define RT5639_M_DAC_L2_VOL_SFT 13
242 #define RT5639_M_DAC_R2_VOL (0x1 << 12)
243 #define RT5639_M_DAC_R2_VOL_SFT 12
245 /* ADC Digital Volume Control (0x1c) */
246 #define RT5639_ADC_L_VOL_MASK (0x7f << 8)
247 #define RT5639_ADC_L_VOL_SFT 8
248 #define RT5639_ADC_R_VOL_MASK (0x7f)
249 #define RT5639_ADC_R_VOL_SFT 0
251 /* Mono ADC Digital Volume Control (0x1d) */
252 #define RT5639_MONO_ADC_L_VOL_MASK (0x7f << 8)
253 #define RT5639_MONO_ADC_L_VOL_SFT 8
254 #define RT5639_MONO_ADC_R_VOL_MASK (0x7f)
255 #define RT5639_MONO_ADC_R_VOL_SFT 0
257 /* ADC Boost Volume Control (0x1e) */
258 #define RT5639_ADC_L_BST_MASK (0x3 << 14)
259 #define RT5639_ADC_L_BST_SFT 14
260 #define RT5639_ADC_R_BST_MASK (0x3 << 12)
261 #define RT5639_ADC_R_BST_SFT 12
262 #define RT5639_ADC_COMP_MASK (0x3 << 10)
263 #define RT5639_ADC_COMP_SFT 10
265 /* Stereo ADC Mixer Control (0x27) */
266 #define RT5639_M_ADC_L1 (0x1 << 14)
267 #define RT5639_M_ADC_L1_SFT 14
268 #define RT5639_M_ADC_L2 (0x1 << 13)
269 #define RT5639_M_ADC_L2_SFT 13
270 #define RT5639_ADC_1_SRC_MASK (0x1 << 12)
271 #define RT5639_ADC_1_SRC_SFT 12
272 #define RT5639_ADC_1_SRC_ADC (0x1 << 12)
273 #define RT5639_ADC_1_SRC_DACMIX (0x0 << 12)
274 #define RT5639_ADC_2_SRC_MASK (0x3 << 10)
275 #define RT5639_ADC_2_SRC_SFT 10
276 #define RT5639_ADC_2_SRC_DMIC1 (0x0 << 10)
277 #define RT5639_ADC_2_SRC_DMIC2 (0x1 << 10)
278 #define RT5639_ADC_2_SRC_DACMIX (0x2 << 10)
279 #define RT5639_M_ADC_R1 (0x1 << 6)
280 #define RT5639_M_ADC_R1_SFT 6
281 #define RT5639_M_ADC_R2 (0x1 << 5)
282 #define RT5639_M_ADC_R2_SFT 5
284 /* Mono ADC Mixer Control (0x28) */
285 #define RT5639_M_MONO_ADC_L1 (0x1 << 14)
286 #define RT5639_M_MONO_ADC_L1_SFT 14
287 #define RT5639_M_MONO_ADC_L2 (0x1 << 13)
288 #define RT5639_M_MONO_ADC_L2_SFT 13
289 #define RT5639_MONO_ADC_L1_SRC_MASK (0x1 << 12)
290 #define RT5639_MONO_ADC_L1_SRC_SFT 12
291 #define RT5639_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
292 #define RT5639_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
293 #define RT5639_MONO_ADC_L2_SRC_MASK (0x3 << 10)
294 #define RT5639_MONO_ADC_L2_SRC_SFT 10
295 #define RT5639_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
296 #define RT5639_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
297 #define RT5639_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
298 #define RT5639_M_MONO_ADC_R1 (0x1 << 6)
299 #define RT5639_M_MONO_ADC_R1_SFT 6
300 #define RT5639_M_MONO_ADC_R2 (0x1 << 5)
301 #define RT5639_M_MONO_ADC_R2_SFT 5
302 #define RT5639_MONO_ADC_R1_SRC_MASK (0x1 << 4)
303 #define RT5639_MONO_ADC_R1_SRC_SFT 4
304 #define RT5639_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
305 #define RT5639_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)
306 #define RT5639_MONO_ADC_R2_SRC_MASK (0x3 << 2)
307 #define RT5639_MONO_ADC_R2_SRC_SFT 2
308 #define RT5639_MONO_ADC_R2_SRC_DMIC_R1 (0x0 << 2)
309 #define RT5639_MONO_ADC_R2_SRC_DMIC_R2 (0x1 << 2)
310 #define RT5639_MONO_ADC_R2_SRC_DACMIXR (0x2 << 2)
312 /* ADC Mixer to DAC Mixer Control (0x29) */
313 #define RT5639_M_ADCMIX_L (0x1 << 15)
314 #define RT5639_M_ADCMIX_L_SFT 15
315 #define RT5639_M_IF1_DAC_L (0x1 << 14)
316 #define RT5639_M_IF1_DAC_L_SFT 14
317 #define RT5639_M_ADCMIX_R (0x1 << 7)
318 #define RT5639_M_ADCMIX_R_SFT 7
319 #define RT5639_M_IF1_DAC_R (0x1 << 6)
320 #define RT5639_M_IF1_DAC_R_SFT 6
322 /* Stereo DAC Mixer Control (0x2a) */
323 #define RT5639_M_DAC_L1 (0x1 << 14)
324 #define RT5639_M_DAC_L1_SFT 14
325 #define RT5639_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
326 #define RT5639_DAC_L1_STO_L_VOL_SFT 13
327 #define RT5639_M_DAC_L2 (0x1 << 12)
328 #define RT5639_M_DAC_L2_SFT 12
329 #define RT5639_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
330 #define RT5639_DAC_L2_STO_L_VOL_SFT 11
331 #define RT5639_M_ANC_DAC_L (0x1 << 10)
332 #define RT5639_M_ANC_DAC_L_SFT 10
333 #define RT5639_M_DAC_R1 (0x1 << 6)
334 #define RT5639_M_DAC_R1_SFT 6
335 #define RT5639_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
336 #define RT5639_DAC_R1_STO_R_VOL_SFT 5
337 #define RT5639_M_DAC_R2 (0x1 << 4)
338 #define RT5639_M_DAC_R2_SFT 4
339 #define RT5639_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
340 #define RT5639_DAC_R2_STO_R_VOL_SFT 3
341 #define RT5639_M_ANC_DAC_R (0x1 << 2)
342 #define RT5639_M_ANC_DAC_R_SFT 2
344 /* Mono DAC Mixer Control (0x2b) */
345 #define RT5639_M_DAC_L1_MONO_L (0x1 << 14)
346 #define RT5639_M_DAC_L1_MONO_L_SFT 14
347 #define RT5639_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
348 #define RT5639_DAC_L1_MONO_L_VOL_SFT 13
349 #define RT5639_M_DAC_L2_MONO_L (0x1 << 12)
350 #define RT5639_M_DAC_L2_MONO_L_SFT 12
351 #define RT5639_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
352 #define RT5639_DAC_L2_MONO_L_VOL_SFT 11
353 #define RT5639_M_DAC_R2_MONO_L (0x1 << 10)
354 #define RT5639_M_DAC_R2_MONO_L_SFT 10
355 #define RT5639_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
356 #define RT5639_DAC_R2_MONO_L_VOL_SFT 9
357 #define RT5639_M_DAC_R1_MONO_R (0x1 << 6)
358 #define RT5639_M_DAC_R1_MONO_R_SFT 6
359 #define RT5639_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
360 #define RT5639_DAC_R1_MONO_R_VOL_SFT 5
361 #define RT5639_M_DAC_R2_MONO_R (0x1 << 4)
362 #define RT5639_M_DAC_R2_MONO_R_SFT 4
363 #define RT5639_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
364 #define RT5639_DAC_R2_MONO_R_VOL_SFT 3
365 #define RT5639_M_DAC_L2_MONO_R (0x1 << 2)
366 #define RT5639_M_DAC_L2_MONO_R_SFT 2
367 #define RT5639_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
368 #define RT5639_DAC_L2_MONO_R_VOL_SFT 1
370 /* Digital Mixer Control (0x2c) */
371 #define RT5639_M_STO_L_DAC_L (0x1 << 15)
372 #define RT5639_M_STO_L_DAC_L_SFT 15
373 #define RT5639_STO_L_DAC_L_VOL_MASK (0x1 << 14)
374 #define RT5639_STO_L_DAC_L_VOL_SFT 14
375 #define RT5639_M_DAC_L2_DAC_L (0x1 << 13)
376 #define RT5639_M_DAC_L2_DAC_L_SFT 13
377 #define RT5639_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
378 #define RT5639_DAC_L2_DAC_L_VOL_SFT 12
379 #define RT5639_M_STO_R_DAC_R (0x1 << 11)
380 #define RT5639_M_STO_R_DAC_R_SFT 11
381 #define RT5639_STO_R_DAC_R_VOL_MASK (0x1 << 10)
382 #define RT5639_STO_R_DAC_R_VOL_SFT 10
383 #define RT5639_M_DAC_R2_DAC_R (0x1 << 9)
384 #define RT5639_M_DAC_R2_DAC_R_SFT 9
385 #define RT5639_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
386 #define RT5639_DAC_R2_DAC_R_VOL_SFT 8
388 /* DSP Path Control 1 (0x2d) */
389 #define RT5639_RXDP_SRC_MASK (0x1 << 15)
390 #define RT5639_RXDP_SRC_SFT 15
391 #define RT5639_RXDP_SRC_NOR (0x0 << 15)
392 #define RT5639_RXDP_SRC_DIV3 (0x1 << 15)
393 #define RT5639_TXDP_SRC_MASK (0x1 << 14)
394 #define RT5639_TXDP_SRC_SFT 14
395 #define RT5639_TXDP_SRC_NOR (0x0 << 14)
396 #define RT5639_TXDP_SRC_DIV3 (0x1 << 14)
398 /* DSP Path Control 2 (0x2e) */
399 #define RT5639_DAC_L2_SEL_MASK (0x3 << 14)
400 #define RT5639_DAC_L2_SEL_SFT 14
401 #define RT5639_DAC_L2_SEL_IF2 (0x0 << 14)
402 #define RT5639_DAC_L2_SEL_IF3 (0x1 << 14)
403 #define RT5639_DAC_L2_SEL_TXDC (0x2 << 14)
404 #define RT5639_DAC_L2_SEL_BASS (0x3 << 14)
405 #define RT5639_DAC_R2_SEL_MASK (0x3 << 12)
406 #define RT5639_DAC_R2_SEL_SFT 12
407 #define RT5639_DAC_R2_SEL_IF2 (0x0 << 12)
408 #define RT5639_DAC_R2_SEL_IF3 (0x1 << 12)
409 #define RT5639_DAC_R2_SEL_TXDC (0x2 << 12)
410 #define RT5639_IF2_ADC_L_SEL_MASK (0x1 << 11)
411 #define RT5639_IF2_ADC_L_SEL_SFT 11
412 #define RT5639_IF2_ADC_L_SEL_TXDP (0x0 << 11)
413 #define RT5639_IF2_ADC_L_SEL_PASS (0x1 << 11)
414 #define RT5639_IF2_ADC_R_SEL_MASK (0x1 << 10)
415 #define RT5639_IF2_ADC_R_SEL_SFT 10
416 #define RT5639_IF2_ADC_R_SEL_TXDP (0x0 << 10)
417 #define RT5639_IF2_ADC_R_SEL_PASS (0x1 << 10)
418 #define RT5639_RXDC_SEL_MASK (0x3 << 8)
419 #define RT5639_RXDC_SEL_SFT 8
420 #define RT5639_RXDC_SEL_NOR (0x0 << 8)
421 #define RT5639_RXDC_SEL_L2R (0x1 << 8)
422 #define RT5639_RXDC_SEL_R2L (0x2 << 8)
423 #define RT5639_RXDC_SEL_SWAP (0x3 << 8)
424 #define RT5639_RXDP_SEL_MASK (0x3 << 6)
425 #define RT5639_RXDP_SEL_SFT 6
426 #define RT5639_RXDP_SEL_NOR (0x0 << 6)
427 #define RT5639_RXDP_SEL_L2R (0x1 << 6)
428 #define RT5639_RXDP_SEL_R2L (0x2 << 6)
429 #define RT5639_RXDP_SEL_SWAP (0x3 << 6)
430 #define RT5639_TXDC_SEL_MASK (0x3 << 4)
431 #define RT5639_TXDC_SEL_SFT 4
432 #define RT5639_TXDC_SEL_NOR (0x0 << 4)
433 #define RT5639_TXDC_SEL_L2R (0x1 << 4)
434 #define RT5639_TXDC_SEL_R2L (0x2 << 4)
435 #define RT5639_TXDC_SEL_SWAP (0x3 << 4)
436 #define RT5639_TXDP_SEL_MASK (0x3 << 2)
437 #define RT5639_TXDP_SEL_SFT 2
438 #define RT5639_TXDP_SEL_NOR (0x0 << 2)
439 #define RT5639_TXDP_SEL_L2R (0x1 << 2)
440 #define RT5639_TXDP_SEL_R2L (0x2 << 2)
441 #define RT5639_TRXDP_SEL_SWAP (0x3 << 2)
443 /* Digital Interface Data Control (0x2f) */
444 #define RT5639_IF1_DAC_SEL_MASK (0x3 << 14)
445 #define RT5639_IF1_DAC_SEL_SFT 14
446 #define RT5639_IF1_DAC_SEL_NOR (0x0 << 14)
447 #define RT5639_IF1_DAC_SEL_L2R (0x1 << 14)
448 #define RT5639_IF1_DAC_SEL_R2L (0x2 << 14)
449 #define RT5639_IF1_DAC_SEL_SWAP (0x3 << 14)
450 #define RT5639_IF1_ADC_SEL_MASK (0x3 << 12)
451 #define RT5639_IF1_ADC_SEL_SFT 12
452 #define RT5639_IF1_ADC_SEL_NOR (0x0 << 12)
453 #define RT5639_IF1_ADC_SEL_L2R (0x1 << 12)
454 #define RT5639_IF1_ADC_SEL_R2L (0x2 << 12)
455 #define RT5639_IF1_ADC_SEL_SWAP (0x3 << 12)
456 #define RT5639_IF2_DAC_SEL_MASK (0x3 << 10)
457 #define RT5639_IF2_DAC_SEL_SFT 10
458 #define RT5639_IF2_DAC_SEL_NOR (0x0 << 10)
459 #define RT5639_IF2_DAC_SEL_L2R (0x1 << 10)
460 #define RT5639_IF2_DAC_SEL_R2L (0x2 << 10)
461 #define RT5639_IF2_DAC_SEL_SWAP (0x3 << 10)
462 #define RT5639_IF2_ADC_SEL_MASK (0x3 << 8)
463 #define RT5639_IF2_ADC_SEL_SFT 8
464 #define RT5639_IF2_ADC_SEL_NOR (0x0 << 8)
465 #define RT5639_IF2_ADC_SEL_L2R (0x1 << 8)
466 #define RT5639_IF2_ADC_SEL_R2L (0x2 << 8)
467 #define RT5639_IF2_ADC_SEL_SWAP (0x3 << 8)
468 #define RT5639_IF3_DAC_SEL_MASK (0x3 << 6)
469 #define RT5639_IF3_DAC_SEL_SFT 6
470 #define RT5639_IF3_DAC_SEL_NOR (0x0 << 6)
471 #define RT5639_IF3_DAC_SEL_L2R (0x1 << 6)
472 #define RT5639_IF3_DAC_SEL_R2L (0x2 << 6)
473 #define RT5639_IF3_DAC_SEL_SWAP (0x3 << 6)
474 #define RT5639_IF3_ADC_SEL_MASK (0x3 << 4)
475 #define RT5639_IF3_ADC_SEL_SFT 4
476 #define RT5639_IF3_ADC_SEL_NOR (0x0 << 4)
477 #define RT5639_IF3_ADC_SEL_L2R (0x1 << 4)
478 #define RT5639_IF3_ADC_SEL_R2L (0x2 << 4)
479 #define RT5639_IF3_ADC_SEL_SWAP (0x3 << 4)
481 /* REC Left Mixer Control 1 (0x3b) */
482 #define RT5639_G_HP_L_RM_L_MASK (0x7 << 13)
483 #define RT5639_G_HP_L_RM_L_SFT 13
484 #define RT5639_G_IN_L_RM_L_MASK (0x7 << 10)
485 #define RT5639_G_IN_L_RM_L_SFT 10
486 #define RT5639_G_BST4_RM_L_MASK (0x7 << 7)
487 #define RT5639_G_BST4_RM_L_SFT 7
488 #define RT5639_G_BST3_RM_L_MASK (0x7 << 4)
489 #define RT5639_G_BST3_RM_L_SFT 4
490 #define RT5639_G_BST2_RM_L_MASK (0x7 << 1)
491 #define RT5639_G_BST2_RM_L_SFT 1
493 /* REC Left Mixer Control 2 (0x3c) */
494 #define RT5639_G_BST1_RM_L_MASK (0x7 << 13)
495 #define RT5639_G_BST1_RM_L_SFT 13
496 #define RT5639_G_OM_L_RM_L_MASK (0x7 << 10)
497 #define RT5639_G_OM_L_RM_L_SFT 10
498 #define RT5639_M_HP_L_RM_L (0x1 << 6)
499 #define RT5639_M_HP_L_RM_L_SFT 6
500 #define RT5639_M_IN_L_RM_L (0x1 << 5)
501 #define RT5639_M_IN_L_RM_L_SFT 5
502 #define RT5639_M_BST4_RM_L (0x1 << 4)
503 #define RT5639_M_BST4_RM_L_SFT 4
504 #define RT5639_M_BST3_RM_L (0x1 << 3)
505 #define RT5639_M_BST3_RM_L_SFT 3
506 #define RT5639_M_BST2_RM_L (0x1 << 2)
507 #define RT5639_M_BST2_RM_L_SFT 2
508 #define RT5639_M_BST1_RM_L (0x1 << 1)
509 #define RT5639_M_BST1_RM_L_SFT 1
510 #define RT5639_M_OM_L_RM_L (0x1)
511 #define RT5639_M_OM_L_RM_L_SFT 0
513 /* REC Right Mixer Control 1 (0x3d) */
514 #define RT5639_G_HP_R_RM_R_MASK (0x7 << 13)
515 #define RT5639_G_HP_R_RM_R_SFT 13
516 #define RT5639_G_IN_R_RM_R_MASK (0x7 << 10)
517 #define RT5639_G_IN_R_RM_R_SFT 10
518 #define RT5639_G_BST4_RM_R_MASK (0x7 << 7)
519 #define RT5639_G_BST4_RM_R_SFT 7
520 #define RT5639_G_BST3_RM_R_MASK (0x7 << 4)
521 #define RT5639_G_BST3_RM_R_SFT 4
522 #define RT5639_G_BST2_RM_R_MASK (0x7 << 1)
523 #define RT5639_G_BST2_RM_R_SFT 1
525 /* REC Right Mixer Control 2 (0x3e) */
526 #define RT5639_G_BST1_RM_R_MASK (0x7 << 13)
527 #define RT5639_G_BST1_RM_R_SFT 13
528 #define RT5639_G_OM_R_RM_R_MASK (0x7 << 10)
529 #define RT5639_G_OM_R_RM_R_SFT 10
530 #define RT5639_M_HP_R_RM_R (0x1 << 6)
531 #define RT5639_M_HP_R_RM_R_SFT 6
532 #define RT5639_M_IN_R_RM_R (0x1 << 5)
533 #define RT5639_M_IN_R_RM_R_SFT 5
534 #define RT5639_M_BST4_RM_R (0x1 << 4)
535 #define RT5639_M_BST4_RM_R_SFT 4
536 #define RT5639_M_BST3_RM_R (0x1 << 3)
537 #define RT5639_M_BST3_RM_R_SFT 3
538 #define RT5639_M_BST2_RM_R (0x1 << 2)
539 #define RT5639_M_BST2_RM_R_SFT 2
540 #define RT5639_M_BST1_RM_R (0x1 << 1)
541 #define RT5639_M_BST1_RM_R_SFT 1
542 #define RT5639_M_OM_R_RM_R (0x1)
543 #define RT5639_M_OM_R_RM_R_SFT 0
545 /* HPMIX Control (0x45) */
546 #define RT5639_M_DAC2_HM (0x1 << 15)
547 #define RT5639_M_DAC2_HM_SFT 15
548 #define RT5639_M_DAC1_HM (0x1 << 14)
549 #define RT5639_M_DAC1_HM_SFT 14
550 #define RT5639_M_HPVOL_HM (0x1 << 13)
551 #define RT5639_M_HPVOL_HM_SFT 13
552 #define RT5639_G_HPOMIX_MASK (0x1 << 12)
553 #define RT5639_G_HPOMIX_SFT 12
555 /* SPK Left Mixer Control (0x46) */
556 #define RT5639_G_RM_L_SM_L_MASK (0x3 << 14)
557 #define RT5639_G_RM_L_SM_L_SFT 14
558 #define RT5639_G_IN_L_SM_L_MASK (0x3 << 12)
559 #define RT5639_G_IN_L_SM_L_SFT 12
560 #define RT5639_G_DAC_L1_SM_L_MASK (0x3 << 10)
561 #define RT5639_G_DAC_L1_SM_L_SFT 10
562 #define RT5639_G_DAC_L2_SM_L_MASK (0x3 << 8)
563 #define RT5639_G_DAC_L2_SM_L_SFT 8
564 #define RT5639_G_OM_L_SM_L_MASK (0x3 << 6)
565 #define RT5639_G_OM_L_SM_L_SFT 6
566 #define RT5639_M_RM_L_SM_L (0x1 << 5)
567 #define RT5639_M_RM_L_SM_L_SFT 5
568 #define RT5639_M_IN_L_SM_L (0x1 << 4)
569 #define RT5639_M_IN_L_SM_L_SFT 4
570 #define RT5639_M_DAC_L1_SM_L (0x1 << 3)
571 #define RT5639_M_DAC_L1_SM_L_SFT 3
572 #define RT5639_M_DAC_L2_SM_L (0x1 << 2)
573 #define RT5639_M_DAC_L2_SM_L_SFT 2
574 #define RT5639_M_OM_L_SM_L (0x1 << 1)
575 #define RT5639_M_OM_L_SM_L_SFT 1
577 /* SPK Right Mixer Control (0x47) */
578 #define RT5639_G_RM_R_SM_R_MASK (0x3 << 14)
579 #define RT5639_G_RM_R_SM_R_SFT 14
580 #define RT5639_G_IN_R_SM_R_MASK (0x3 << 12)
581 #define RT5639_G_IN_R_SM_R_SFT 12
582 #define RT5639_G_DAC_R1_SM_R_MASK (0x3 << 10)
583 #define RT5639_G_DAC_R1_SM_R_SFT 10
584 #define RT5639_G_DAC_R2_SM_R_MASK (0x3 << 8)
585 #define RT5639_G_DAC_R2_SM_R_SFT 8
586 #define RT5639_G_OM_R_SM_R_MASK (0x3 << 6)
587 #define RT5639_G_OM_R_SM_R_SFT 6
588 #define RT5639_M_RM_R_SM_R (0x1 << 5)
589 #define RT5639_M_RM_R_SM_R_SFT 5
590 #define RT5639_M_IN_R_SM_R (0x1 << 4)
591 #define RT5639_M_IN_R_SM_R_SFT 4
592 #define RT5639_M_DAC_R1_SM_R (0x1 << 3)
593 #define RT5639_M_DAC_R1_SM_R_SFT 3
594 #define RT5639_M_DAC_R2_SM_R (0x1 << 2)
595 #define RT5639_M_DAC_R2_SM_R_SFT 2
596 #define RT5639_M_OM_R_SM_R (0x1 << 1)
597 #define RT5639_M_OM_R_SM_R_SFT 1
599 /* SPOLMIX Control (0x48) */
600 #define RT5639_M_DAC_R1_SPM_L (0x1 << 15)
601 #define RT5639_M_DAC_R1_SPM_L_SFT 15
602 #define RT5639_M_DAC_L1_SPM_L (0x1 << 14)
603 #define RT5639_M_DAC_L1_SPM_L_SFT 14
604 #define RT5639_M_SV_R_SPM_L (0x1 << 13)
605 #define RT5639_M_SV_R_SPM_L_SFT 13
606 #define RT5639_M_SV_L_SPM_L (0x1 << 12)
607 #define RT5639_M_SV_L_SPM_L_SFT 12
608 #define RT5639_M_BST1_SPM_L (0x1 << 11)
609 #define RT5639_M_BST1_SPM_L_SFT 11
611 /* SPORMIX Control (0x49) */
612 #define RT5639_M_DAC_R1_SPM_R (0x1 << 13)
613 #define RT5639_M_DAC_R1_SPM_R_SFT 13
614 #define RT5639_M_SV_R_SPM_R (0x1 << 12)
615 #define RT5639_M_SV_R_SPM_R_SFT 12
616 #define RT5639_M_BST1_SPM_R (0x1 << 11)
617 #define RT5639_M_BST1_SPM_R_SFT 11
619 /* SPOLMIX / SPORMIX Ratio Control (0x4a) */
620 #define RT5639_SPO_CLSD_RATIO_MASK (0x7)
621 #define RT5639_SPO_CLSD_RATIO_SFT 0
623 /* Mono Output Mixer Control (0x4c) */
624 #define RT5639_M_DAC_R2_MM (0x1 << 15)
625 #define RT5639_M_DAC_R2_MM_SFT 15
626 #define RT5639_M_DAC_L2_MM (0x1 << 14)
627 #define RT5639_M_DAC_L2_MM_SFT 14
628 #define RT5639_M_OV_R_MM (0x1 << 13)
629 #define RT5639_M_OV_R_MM_SFT 13
630 #define RT5639_M_OV_L_MM (0x1 << 12)
631 #define RT5639_M_OV_L_MM_SFT 12
632 #define RT5639_M_BST1_MM (0x1 << 11)
633 #define RT5639_M_BST1_MM_SFT 11
634 #define RT5639_G_MONOMIX_MASK (0x1 << 10)
635 #define RT5639_G_MONOMIX_SFT 10
637 /* Output Left Mixer Control 1 (0x4d) */
638 #define RT5639_G_BST3_OM_L_MASK (0x7 << 13)
639 #define RT5639_G_BST3_OM_L_SFT 13
640 #define RT5639_G_BST2_OM_L_MASK (0x7 << 10)
641 #define RT5639_G_BST2_OM_L_SFT 10
642 #define RT5639_G_BST1_OM_L_MASK (0x7 << 7)
643 #define RT5639_G_BST1_OM_L_SFT 7
644 #define RT5639_G_IN_L_OM_L_MASK (0x7 << 4)
645 #define RT5639_G_IN_L_OM_L_SFT 4
646 #define RT5639_G_RM_L_OM_L_MASK (0x7 << 1)
647 #define RT5639_G_RM_L_OM_L_SFT 1
649 /* Output Left Mixer Control 2 (0x4e) */
650 #define RT5639_G_DAC_R2_OM_L_MASK (0x7 << 13)
651 #define RT5639_G_DAC_R2_OM_L_SFT 13
652 #define RT5639_G_DAC_L2_OM_L_MASK (0x7 << 10)
653 #define RT5639_G_DAC_L2_OM_L_SFT 10
654 #define RT5639_G_DAC_L1_OM_L_MASK (0x7 << 7)
655 #define RT5639_G_DAC_L1_OM_L_SFT 7
657 /* Output Left Mixer Control 3 (0x4f) */
658 #define RT5639_M_SM_L_OM_L (0x1 << 8)
659 #define RT5639_M_SM_L_OM_L_SFT 8
660 #define RT5639_M_BST3_OM_L (0x1 << 7)
661 #define RT5639_M_BST3_OM_L_SFT 7
662 #define RT5639_M_BST2_OM_L (0x1 << 6)
663 #define RT5639_M_BST2_OM_L_SFT 6
664 #define RT5639_M_BST1_OM_L (0x1 << 5)
665 #define RT5639_M_BST1_OM_L_SFT 5
666 #define RT5639_M_IN_L_OM_L (0x1 << 4)
667 #define RT5639_M_IN_L_OM_L_SFT 4
668 #define RT5639_M_RM_L_OM_L (0x1 << 3)
669 #define RT5639_M_RM_L_OM_L_SFT 3
670 #define RT5639_M_DAC_R2_OM_L (0x1 << 2)
671 #define RT5639_M_DAC_R2_OM_L_SFT 2
672 #define RT5639_M_DAC_L2_OM_L (0x1 << 1)
673 #define RT5639_M_DAC_L2_OM_L_SFT 1
674 #define RT5639_M_DAC_L1_OM_L (0x1)
675 #define RT5639_M_DAC_L1_OM_L_SFT 0
677 /* Output Right Mixer Control 1 (0x50) */
678 #define RT5639_G_BST4_OM_R_MASK (0x7 << 13)
679 #define RT5639_G_BST4_OM_R_SFT 13
680 #define RT5639_G_BST2_OM_R_MASK (0x7 << 10)
681 #define RT5639_G_BST2_OM_R_SFT 10
682 #define RT5639_G_BST1_OM_R_MASK (0x7 << 7)
683 #define RT5639_G_BST1_OM_R_SFT 7
684 #define RT5639_G_IN_R_OM_R_MASK (0x7 << 4)
685 #define RT5639_G_IN_R_OM_R_SFT 4
686 #define RT5639_G_RM_R_OM_R_MASK (0x7 << 1)
687 #define RT5639_G_RM_R_OM_R_SFT 1
689 /* Output Right Mixer Control 2 (0x51) */
690 #define RT5639_G_DAC_L2_OM_R_MASK (0x7 << 13)
691 #define RT5639_G_DAC_L2_OM_R_SFT 13
692 #define RT5639_G_DAC_R2_OM_R_MASK (0x7 << 10)
693 #define RT5639_G_DAC_R2_OM_R_SFT 10
694 #define RT5639_G_DAC_R1_OM_R_MASK (0x7 << 7)
695 #define RT5639_G_DAC_R1_OM_R_SFT 7
697 /* Output Right Mixer Control 3 (0x52) */
698 #define RT5639_M_SM_L_OM_R (0x1 << 8)
699 #define RT5639_M_SM_L_OM_R_SFT 8
700 #define RT5639_M_BST4_OM_R (0x1 << 7)
701 #define RT5639_M_BST4_OM_R_SFT 7
702 #define RT5639_M_BST2_OM_R (0x1 << 6)
703 #define RT5639_M_BST2_OM_R_SFT 6
704 #define RT5639_M_BST1_OM_R (0x1 << 5)
705 #define RT5639_M_BST1_OM_R_SFT 5
706 #define RT5639_M_IN_R_OM_R (0x1 << 4)
707 #define RT5639_M_IN_R_OM_R_SFT 4
708 #define RT5639_M_RM_R_OM_R (0x1 << 3)
709 #define RT5639_M_RM_R_OM_R_SFT 3
710 #define RT5639_M_DAC_L2_OM_R (0x1 << 2)
711 #define RT5639_M_DAC_L2_OM_R_SFT 2
712 #define RT5639_M_DAC_R2_OM_R (0x1 << 1)
713 #define RT5639_M_DAC_R2_OM_R_SFT 1
714 #define RT5639_M_DAC_R1_OM_R (0x1)
715 #define RT5639_M_DAC_R1_OM_R_SFT 0
717 /* LOUT Mixer Control (0x53) */
718 #define RT5639_M_DAC_L1_LM (0x1 << 15)
719 #define RT5639_M_DAC_L1_LM_SFT 15
720 #define RT5639_M_DAC_R1_LM (0x1 << 14)
721 #define RT5639_M_DAC_R1_LM_SFT 14
722 #define RT5639_M_OV_L_LM (0x1 << 13)
723 #define RT5639_M_OV_L_LM_SFT 13
724 #define RT5639_M_OV_R_LM (0x1 << 12)
725 #define RT5639_M_OV_R_LM_SFT 12
726 #define RT5639_G_LOUTMIX_MASK (0x1 << 11)
727 #define RT5639_G_LOUTMIX_SFT 11
729 /* Power Management for Digital 1 (0x61) */
730 #define RT5639_PWR_I2S1 (0x1 << 15)
731 #define RT5639_PWR_I2S1_BIT 15
732 #define RT5639_PWR_I2S2 (0x1 << 14)
733 #define RT5639_PWR_I2S2_BIT 14
734 #define RT5639_PWR_I2S3 (0x1 << 13)
735 #define RT5639_PWR_I2S3_BIT 13
736 #define RT5639_PWR_DAC_L1 (0x1 << 12)
737 #define RT5639_PWR_DAC_L1_BIT 12
738 #define RT5639_PWR_DAC_R1 (0x1 << 11)
739 #define RT5639_PWR_DAC_R1_BIT 11
740 #define RT5639_PWR_DAC_L2 (0x1 << 7)
741 #define RT5639_PWR_DAC_L2_BIT 7
742 #define RT5639_PWR_DAC_R2 (0x1 << 6)
743 #define RT5639_PWR_DAC_R2_BIT 6
744 #define RT5639_PWR_ADC_L (0x1 << 2)
745 #define RT5639_PWR_ADC_L_BIT 2
746 #define RT5639_PWR_ADC_R (0x1 << 1)
747 #define RT5639_PWR_ADC_R_BIT 1
748 #define RT5639_PWR_CLS_D (0x1)
749 #define RT5639_PWR_CLS_D_BIT 0
751 /* Power Management for Digital 2 (0x62) */
752 #define RT5639_PWR_ADC_SF (0x1 << 15)
753 #define RT5639_PWR_ADC_SF_BIT 15
754 #define RT5639_PWR_ADC_MF_L (0x1 << 14)
755 #define RT5639_PWR_ADC_MF_L_BIT 14
756 #define RT5639_PWR_ADC_MF_R (0x1 << 13)
757 #define RT5639_PWR_ADC_MF_R_BIT 13
758 #define RT5639_PWR_I2S_DSP (0x1 << 12)
759 #define RT5639_PWR_I2S_DSP_BIT 12
761 /* Power Management for Analog 1 (0x63) */
762 #define RT5639_PWR_VREF1 (0x1 << 15)
763 #define RT5639_PWR_VREF1_BIT 15
764 #define RT5639_PWR_FV1 (0x1 << 14)
765 #define RT5639_PWR_FV1_BIT 14
766 #define RT5639_PWR_MB (0x1 << 13)
767 #define RT5639_PWR_MB_BIT 13
768 #define RT5639_PWR_LM (0x1 << 12)
769 #define RT5639_PWR_LM_BIT 12
770 #define RT5639_PWR_BG (0x1 << 11)
771 #define RT5639_PWR_BG_BIT 11
772 #define RT5639_PWR_MM (0x1 << 10)
773 #define RT5639_PWR_MM_BIT 10
774 #define RT5639_PWR_MA (0x1 << 8)
775 #define RT5639_PWR_MA_BIT 8
776 #define RT5639_PWR_HP_L (0x1 << 7)
777 #define RT5639_PWR_HP_L_BIT 7
778 #define RT5639_PWR_HP_R (0x1 << 6)
779 #define RT5639_PWR_HP_R_BIT 6
780 #define RT5639_PWR_HA (0x1 << 5)
781 #define RT5639_PWR_HA_BIT 5
782 #define RT5639_PWR_VREF2 (0x1 << 4)
783 #define RT5639_PWR_VREF2_BIT 4
784 #define RT5639_PWR_FV2 (0x1 << 3)
785 #define RT5639_PWR_FV2_BIT 3
786 #define RT5639_PWR_LDO2 (0x1 << 2)
787 #define RT5639_PWR_LDO2_BIT 2
789 /* Power Management for Analog 2 (0x64) */
790 #define RT5639_PWR_BST1 (0x1 << 15)
791 #define RT5639_PWR_BST1_BIT 15
792 #define RT5639_PWR_BST2 (0x1 << 14)
793 #define RT5639_PWR_BST2_BIT 14
794 #define RT5639_PWR_BST3 (0x1 << 13)
795 #define RT5639_PWR_BST3_BIT 13
796 #define RT5639_PWR_BST4 (0x1 << 12)
797 #define RT5639_PWR_BST4_BIT 12
798 #define RT5639_PWR_MB1 (0x1 << 11)
799 #define RT5639_PWR_MB1_BIT 11
800 #define RT5639_PWR_MB2 (0x1 << 10)
801 #define RT5639_PWR_MB2_BIT 10
802 #define RT5639_PWR_PLL (0x1 << 9)
803 #define RT5639_PWR_PLL_BIT 9
805 /* Power Management for Mixer (0x65) */
806 #define RT5639_PWR_OM_L (0x1 << 15)
807 #define RT5639_PWR_OM_L_BIT 15
808 #define RT5639_PWR_OM_R (0x1 << 14)
809 #define RT5639_PWR_OM_R_BIT 14
810 #define RT5639_PWR_SM_L (0x1 << 13)
811 #define RT5639_PWR_SM_L_BIT 13
812 #define RT5639_PWR_SM_R (0x1 << 12)
813 #define RT5639_PWR_SM_R_BIT 12
814 #define RT5639_PWR_RM_L (0x1 << 11)
815 #define RT5639_PWR_RM_L_BIT 11
816 #define RT5639_PWR_RM_R (0x1 << 10)
817 #define RT5639_PWR_RM_R_BIT 10
819 /* Power Management for Volume (0x66) */
820 #define RT5639_PWR_SV_L (0x1 << 15)
821 #define RT5639_PWR_SV_L_BIT 15
822 #define RT5639_PWR_SV_R (0x1 << 14)
823 #define RT5639_PWR_SV_R_BIT 14
824 #define RT5639_PWR_OV_L (0x1 << 13)
825 #define RT5639_PWR_OV_L_BIT 13
826 #define RT5639_PWR_OV_R (0x1 << 12)
827 #define RT5639_PWR_OV_R_BIT 12
828 #define RT5639_PWR_HV_L (0x1 << 11)
829 #define RT5639_PWR_HV_L_BIT 11
830 #define RT5639_PWR_HV_R (0x1 << 10)
831 #define RT5639_PWR_HV_R_BIT 10
832 #define RT5639_PWR_IN_L (0x1 << 9)
833 #define RT5639_PWR_IN_L_BIT 9
834 #define RT5639_PWR_IN_R (0x1 << 8)
835 #define RT5639_PWR_IN_R_BIT 8
837 /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71 0x72) */
838 #define RT5639_I2S_MS_MASK (0x1 << 15)
839 #define RT5639_I2S_MS_SFT 15
840 #define RT5639_I2S_MS_M (0x0 << 15)
841 #define RT5639_I2S_MS_S (0x1 << 15)
842 #define RT5639_I2S_IF_MASK (0x7 << 12)
843 #define RT5639_I2S_IF_SFT 12
844 #define RT5639_I2S_O_CP_MASK (0x3 << 10)
845 #define RT5639_I2S_O_CP_SFT 10
846 #define RT5639_I2S_O_CP_OFF (0x0 << 10)
847 #define RT5639_I2S_O_CP_U_LAW (0x1 << 10)
848 #define RT5639_I2S_O_CP_A_LAW (0x2 << 10)
849 #define RT5639_I2S_I_CP_MASK (0x3 << 8)
850 #define RT5639_I2S_I_CP_SFT 8
851 #define RT5639_I2S_I_CP_OFF (0x0 << 8)
852 #define RT5639_I2S_I_CP_U_LAW (0x1 << 8)
853 #define RT5639_I2S_I_CP_A_LAW (0x2 << 8)
854 #define RT5639_I2S_BP_MASK (0x1 << 7)
855 #define RT5639_I2S_BP_SFT 7
856 #define RT5639_I2S_BP_NOR (0x0 << 7)
857 #define RT5639_I2S_BP_INV (0x1 << 7)
858 #define RT5639_I2S_DL_MASK (0x3 << 2)
859 #define RT5639_I2S_DL_SFT 2
860 #define RT5639_I2S_DL_16 (0x0 << 2)
861 #define RT5639_I2S_DL_20 (0x1 << 2)
862 #define RT5639_I2S_DL_24 (0x2 << 2)
863 #define RT5639_I2S_DL_8 (0x3 << 2)
864 #define RT5639_I2S_DF_MASK (0x3)
865 #define RT5639_I2S_DF_SFT 0
866 #define RT5639_I2S_DF_I2S (0x0)
867 #define RT5639_I2S_DF_LEFT (0x1)
868 #define RT5639_I2S_DF_PCM_A (0x2)
869 #define RT5639_I2S_DF_PCM_B (0x3)
871 /* I2S2 Audio Serial Data Port Control (0x71) */
872 #define RT5639_I2S2_SDI_MASK (0x1 << 6)
873 #define RT5639_I2S2_SDI_SFT 6
874 #define RT5639_I2S2_SDI_I2S1 (0x0 << 6)
875 #define RT5639_I2S2_SDI_I2S2 (0x1 << 6)
877 /* ADC/DAC Clock Control 1 (0x73) */
878 #define RT5639_I2S_BCLK_MS1_MASK (0x1 << 15)
879 #define RT5639_I2S_BCLK_MS1_SFT 15
880 #define RT5639_I2S_BCLK_MS1_32 (0x0 << 15)
881 #define RT5639_I2S_BCLK_MS1_64 (0x1 << 15)
882 #define RT5639_I2S_PD1_MASK (0x7 << 12)
883 #define RT5639_I2S_PD1_SFT 12
884 #define RT5639_I2S_PD1_1 (0x0 << 12)
885 #define RT5639_I2S_PD1_2 (0x1 << 12)
886 #define RT5639_I2S_PD1_3 (0x2 << 12)
887 #define RT5639_I2S_PD1_4 (0x3 << 12)
888 #define RT5639_I2S_PD1_6 (0x4 << 12)
889 #define RT5639_I2S_PD1_8 (0x5 << 12)
890 #define RT5639_I2S_PD1_12 (0x6 << 12)
891 #define RT5639_I2S_PD1_16 (0x7 << 12)
892 #define RT5639_I2S_BCLK_MS2_MASK (0x1 << 11)
893 #define RT5639_I2S_BCLK_MS2_SFT 11
894 #define RT5639_I2S_BCLK_MS2_32 (0x0 << 11)
895 #define RT5639_I2S_BCLK_MS2_64 (0x1 << 11)
896 #define RT5639_I2S_PD2_MASK (0x7 << 8)
897 #define RT5639_I2S_PD2_SFT 8
898 #define RT5639_I2S_PD2_1 (0x0 << 8)
899 #define RT5639_I2S_PD2_2 (0x1 << 8)
900 #define RT5639_I2S_PD2_3 (0x2 << 8)
901 #define RT5639_I2S_PD2_4 (0x3 << 8)
902 #define RT5639_I2S_PD2_6 (0x4 << 8)
903 #define RT5639_I2S_PD2_8 (0x5 << 8)
904 #define RT5639_I2S_PD2_12 (0x6 << 8)
905 #define RT5639_I2S_PD2_16 (0x7 << 8)
906 #define RT5639_I2S_BCLK_MS3_MASK (0x1 << 7)
907 #define RT5639_I2S_BCLK_MS3_SFT 7
908 #define RT5639_I2S_BCLK_MS3_32 (0x0 << 7)
909 #define RT5639_I2S_BCLK_MS3_64 (0x1 << 7)
910 #define RT5639_I2S_PD3_MASK (0x7 << 4)
911 #define RT5639_I2S_PD3_SFT 4
912 #define RT5639_I2S_PD3_1 (0x0 << 4)
913 #define RT5639_I2S_PD3_2 (0x1 << 4)
914 #define RT5639_I2S_PD3_3 (0x2 << 4)
915 #define RT5639_I2S_PD3_4 (0x3 << 4)
916 #define RT5639_I2S_PD3_6 (0x4 << 4)
917 #define RT5639_I2S_PD3_8 (0x5 << 4)
918 #define RT5639_I2S_PD3_12 (0x6 << 4)
919 #define RT5639_I2S_PD3_16 (0x7 << 4)
920 #define RT5639_DAC_OSR_MASK (0x3 << 2)
921 #define RT5639_DAC_OSR_SFT 2
922 #define RT5639_DAC_OSR_128 (0x0 << 2)
923 #define RT5639_DAC_OSR_64 (0x1 << 2)
924 #define RT5639_DAC_OSR_32 (0x2 << 2)
925 #define RT5639_DAC_OSR_16 (0x3 << 2)
926 #define RT5639_ADC_OSR_MASK (0x3)
927 #define RT5639_ADC_OSR_SFT 0
928 #define RT5639_ADC_OSR_128 (0x0)
929 #define RT5639_ADC_OSR_64 (0x1)
930 #define RT5639_ADC_OSR_32 (0x2)
931 #define RT5639_ADC_OSR_16 (0x3)
933 /* ADC/DAC Clock Control 2 (0x74) */
934 #define RT5639_DAC_L_OSR_MASK (0x3 << 14)
935 #define RT5639_DAC_L_OSR_SFT 14
936 #define RT5639_DAC_L_OSR_128 (0x0 << 14)
937 #define RT5639_DAC_L_OSR_64 (0x1 << 14)
938 #define RT5639_DAC_L_OSR_32 (0x2 << 14)
939 #define RT5639_DAC_L_OSR_16 (0x3 << 14)
940 #define RT5639_ADC_R_OSR_MASK (0x3 << 12)
941 #define RT5639_ADC_R_OSR_SFT 12
942 #define RT5639_ADC_R_OSR_128 (0x0 << 12)
943 #define RT5639_ADC_R_OSR_64 (0x1 << 12)
944 #define RT5639_ADC_R_OSR_32 (0x2 << 12)
945 #define RT5639_ADC_R_OSR_16 (0x3 << 12)
946 #define RT5639_DAHPF_EN (0x1 << 11)
947 #define RT5639_DAHPF_EN_SFT 11
948 #define RT5639_ADHPF_EN (0x1 << 10)
949 #define RT5639_ADHPF_EN_SFT 10
951 /* Digital Microphone Control (0x75) */
952 #define RT5639_DMIC_1_EN_MASK (0x1 << 15)
953 #define RT5639_DMIC_1_EN_SFT 15
954 #define RT5639_DMIC_1_DIS (0x0 << 15)
955 #define RT5639_DMIC_1_EN (0x1 << 15)
956 #define RT5639_DMIC_2_EN_MASK (0x1 << 14)
957 #define RT5639_DMIC_2_EN_SFT 14
958 #define RT5639_DMIC_2_DIS (0x0 << 14)
959 #define RT5639_DMIC_2_EN (0x1 << 14)
960 #define RT5639_DMIC_1L_LH_MASK (0x1 << 13)
961 #define RT5639_DMIC_1L_LH_SFT 13
962 #define RT5639_DMIC_1L_LH_FALLING (0x0 << 13)
963 #define RT5639_DMIC_1L_LH_RISING (0x1 << 13)
964 #define RT5639_DMIC_1R_LH_MASK (0x1 << 12)
965 #define RT5639_DMIC_1R_LH_SFT 12
966 #define RT5639_DMIC_1R_LH_FALLING (0x0 << 12)
967 #define RT5639_DMIC_1R_LH_RISING (0x1 << 12)
968 #define RT5639_DMIC_1_DP_MASK (0x1 << 11)
969 #define RT5639_DMIC_1_DP_SFT 11
970 #define RT5639_DMIC_1_DP_GPIO3 (0x0 << 11)
971 #define RT5639_DMIC_1_DP_IN1P (0x1 << 11)
972 #define RT5639_DMIC_2_DP_MASK (0x1 << 10)
973 #define RT5639_DMIC_2_DP_SFT 10
974 #define RT5639_DMIC_2_DP_GPIO4 (0x0 << 10)
975 #define RT5639_DMIC_2_DP_IN1N (0x1 << 10)
976 #define RT5639_DMIC_2L_LH_MASK (0x1 << 9)
977 #define RT5639_DMIC_2L_LH_SFT 9
978 #define RT5639_DMIC_2L_LH_FALLING (0x0 << 9)
979 #define RT5639_DMIC_2L_LH_RISING (0x1 << 9)
980 #define RT5639_DMIC_2R_LH_MASK (0x1 << 8)
981 #define RT5639_DMIC_2R_LH_SFT 8
982 #define RT5639_DMIC_2R_LH_FALLING (0x0 << 8)
983 #define RT5639_DMIC_2R_LH_RISING (0x1 << 8)
984 #define RT5639_DMIC_CLK_MASK (0x7 << 5)
985 #define RT5639_DMIC_CLK_SFT 5
987 /* Global Clock Control (0x80) */
988 #define RT5639_SCLK_SRC_MASK (0x3 << 14)
989 #define RT5639_SCLK_SRC_SFT 14
990 #define RT5639_SCLK_SRC_MCLK (0x0 << 14)
991 #define RT5639_SCLK_SRC_PLL1 (0x1 << 14)
992 #define RT5639_SCLK_SRC_RCCLK (0x2 << 14) /* 15MHz */
993 #define RT5639_PLL1_SRC_MASK (0x3 << 12)
994 #define RT5639_PLL1_SRC_SFT 12
995 #define RT5639_PLL1_SRC_MCLK (0x0 << 12)
996 #define RT5639_PLL1_SRC_BCLK1 (0x1 << 12)
997 #define RT5639_PLL1_SRC_BCLK2 (0x2 << 12)
998 #define RT5639_PLL1_SRC_BCLK3 (0x3 << 12)
999 #define RT5639_PLL1_PD_MASK (0x1 << 3)
1000 #define RT5639_PLL1_PD_SFT 3
1001 #define RT5639_PLL1_PD_1 (0x0 << 3)
1002 #define RT5639_PLL1_PD_2 (0x1 << 3)
1004 #define RT5639_PLL_INP_MAX 40000000
1005 #define RT5639_PLL_INP_MIN 256000
1006 /* PLL M/N/K Code Control 1 (0x81) */
1007 #define RT5639_PLL_N_MAX 0x1ff
1008 #define RT5639_PLL_N_MASK (RT5639_PLL_N_MAX << 7)
1009 #define RT5639_PLL_N_SFT 7
1010 #define RT5639_PLL_K_MAX 0x1f
1011 #define RT5639_PLL_K_MASK (RT5639_PLL_K_MAX)
1012 #define RT5639_PLL_K_SFT 0
1014 /* PLL M/N/K Code Control 2 (0x82) */
1015 #define RT5639_PLL_M_MAX 0xf
1016 #define RT5639_PLL_M_MASK (RT5639_PLL_M_MAX << 12)
1017 #define RT5639_PLL_M_SFT 12
1018 #define RT5639_PLL_M_BP (0x1 << 11)
1019 #define RT5639_PLL_M_BP_SFT 11
1021 /* ASRC Control 1 (0x83) */
1022 #define RT5639_STO_T_MASK (0x1 << 15)
1023 #define RT5639_STO_T_SFT 15
1024 #define RT5639_STO_T_SCLK (0x0 << 15)
1025 #define RT5639_STO_T_LRCK1 (0x1 << 15)
1026 #define RT5639_M1_T_MASK (0x1 << 14)
1027 #define RT5639_M1_T_SFT 14
1028 #define RT5639_M1_T_I2S2 (0x0 << 14)
1029 #define RT5639_M1_T_I2S2_D3 (0x1 << 14)
1030 #define RT5639_I2S2_F_MASK (0x1 << 12)
1031 #define RT5639_I2S2_F_SFT 12
1032 #define RT5639_I2S2_F_I2S2_D2 (0x0 << 12)
1033 #define RT5639_I2S2_F_I2S1_TCLK (0x1 << 12)
1034 #define RT5639_DMIC_1_M_MASK (0x1 << 9)
1035 #define RT5639_DMIC_1_M_SFT 9
1036 #define RT5639_DMIC_1_M_NOR (0x0 << 9)
1037 #define RT5639_DMIC_1_M_ASYN (0x1 << 9)
1038 #define RT5639_DMIC_2_M_MASK (0x1 << 8)
1039 #define RT5639_DMIC_2_M_SFT 8
1040 #define RT5639_DMIC_2_M_NOR (0x0 << 8)
1041 #define RT5639_DMIC_2_M_ASYN (0x1 << 8)
1043 /* ASRC Control 2 (0x84) */
1044 #define RT5639_MDA_L_M_MASK (0x1 << 15)
1045 #define RT5639_MDA_L_M_SFT 15
1046 #define RT5639_MDA_L_M_NOR (0x0 << 15)
1047 #define RT5639_MDA_L_M_ASYN (0x1 << 15)
1048 #define RT5639_MDA_R_M_MASK (0x1 << 14)
1049 #define RT5639_MDA_R_M_SFT 14
1050 #define RT5639_MDA_R_M_NOR (0x0 << 14)
1051 #define RT5639_MDA_R_M_ASYN (0x1 << 14)
1052 #define RT5639_MAD_L_M_MASK (0x1 << 13)
1053 #define RT5639_MAD_L_M_SFT 13
1054 #define RT5639_MAD_L_M_NOR (0x0 << 13)
1055 #define RT5639_MAD_L_M_ASYN (0x1 << 13)
1056 #define RT5639_MAD_R_M_MASK (0x1 << 12)
1057 #define RT5639_MAD_R_M_SFT 12
1058 #define RT5639_MAD_R_M_NOR (0x0 << 12)
1059 #define RT5639_MAD_R_M_ASYN (0x1 << 12)
1060 #define RT5639_ADC_M_MASK (0x1 << 11)
1061 #define RT5639_ADC_M_SFT 11
1062 #define RT5639_ADC_M_NOR (0x0 << 11)
1063 #define RT5639_ADC_M_ASYN (0x1 << 11)
1064 #define RT5639_STO_DAC_M_MASK (0x1 << 5)
1065 #define RT5639_STO_DAC_M_SFT 5
1066 #define RT5639_STO_DAC_M_NOR (0x0 << 5)
1067 #define RT5639_STO_DAC_M_ASYN (0x1 << 5)
1068 #define RT5639_I2S1_R_D_MASK (0x1 << 4)
1069 #define RT5639_I2S1_R_D_SFT 4
1070 #define RT5639_I2S1_R_D_DIS (0x0 << 4)
1071 #define RT5639_I2S1_R_D_EN (0x1 << 4)
1072 #define RT5639_I2S2_R_D_MASK (0x1 << 3)
1073 #define RT5639_I2S2_R_D_SFT 3
1074 #define RT5639_I2S2_R_D_DIS (0x0 << 3)
1075 #define RT5639_I2S2_R_D_EN (0x1 << 3)
1076 #define RT5639_PRE_SCLK_MASK (0x3)
1077 #define RT5639_PRE_SCLK_SFT 0
1078 #define RT5639_PRE_SCLK_512 (0x0)
1079 #define RT5639_PRE_SCLK_1024 (0x1)
1080 #define RT5639_PRE_SCLK_2048 (0x2)
1082 /* ASRC Control 3 (0x85) */
1083 #define RT5639_I2S1_RATE_MASK (0xf << 12)
1084 #define RT5639_I2S1_RATE_SFT 12
1085 #define RT5639_I2S2_RATE_MASK (0xf << 8)
1086 #define RT5639_I2S2_RATE_SFT 8
1088 /* ASRC Control 4 (0x89) */
1089 #define RT5639_I2S1_PD_MASK (0x7 << 12)
1090 #define RT5639_I2S1_PD_SFT 12
1091 #define RT5639_I2S2_PD_MASK (0x7 << 8)
1092 #define RT5639_I2S2_PD_SFT 8
1094 /* HPOUT Over Current Detection (0x8b) */
1095 #define RT5639_HP_OVCD_MASK (0x1 << 10)
1096 #define RT5639_HP_OVCD_SFT 10
1097 #define RT5639_HP_OVCD_DIS (0x0 << 10)
1098 #define RT5639_HP_OVCD_EN (0x1 << 10)
1099 #define RT5639_HP_OC_TH_MASK (0x3 << 8)
1100 #define RT5639_HP_OC_TH_SFT 8
1101 #define RT5639_HP_OC_TH_90 (0x0 << 8)
1102 #define RT5639_HP_OC_TH_105 (0x1 << 8)
1103 #define RT5639_HP_OC_TH_120 (0x2 << 8)
1104 #define RT5639_HP_OC_TH_135 (0x3 << 8)
1106 /* Class D Over Current Control (0x8c) */
1107 #define RT5639_CLSD_OC_MASK (0x1 << 9)
1108 #define RT5639_CLSD_OC_SFT 9
1109 #define RT5639_CLSD_OC_PU (0x0 << 9)
1110 #define RT5639_CLSD_OC_PD (0x1 << 9)
1111 #define RT5639_AUTO_PD_MASK (0x1 << 8)
1112 #define RT5639_AUTO_PD_SFT 8
1113 #define RT5639_AUTO_PD_DIS (0x0 << 8)
1114 #define RT5639_AUTO_PD_EN (0x1 << 8)
1115 #define RT5639_CLSD_OC_TH_MASK (0x3f)
1116 #define RT5639_CLSD_OC_TH_SFT 0
1118 /* Class D Output Control (0x8d) */
1119 #define RT5639_CLSD_RATIO_MASK (0xf << 12)
1120 #define RT5639_CLSD_RATIO_SFT 12
1121 #define RT5639_CLSD_OM_MASK (0x1 << 11)
1122 #define RT5639_CLSD_OM_SFT 11
1123 #define RT5639_CLSD_OM_MONO (0x0 << 11)
1124 #define RT5639_CLSD_OM_STO (0x1 << 11)
1125 #define RT5639_CLSD_SCH_MASK (0x1 << 10)
1126 #define RT5639_CLSD_SCH_SFT 10
1127 #define RT5639_CLSD_SCH_L (0x0 << 10)
1128 #define RT5639_CLSD_SCH_S (0x1 << 10)
1130 /* Depop Mode Control 1 (0x8e) */
1131 #define RT5639_SMT_TRIG_MASK (0x1 << 15)
1132 #define RT5639_SMT_TRIG_SFT 15
1133 #define RT5639_SMT_TRIG_DIS (0x0 << 15)
1134 #define RT5639_SMT_TRIG_EN (0x1 << 15)
1135 #define RT5639_HP_L_SMT_MASK (0x1 << 9)
1136 #define RT5639_HP_L_SMT_SFT 9
1137 #define RT5639_HP_L_SMT_DIS (0x0 << 9)
1138 #define RT5639_HP_L_SMT_EN (0x1 << 9)
1139 #define RT5639_HP_R_SMT_MASK (0x1 << 8)
1140 #define RT5639_HP_R_SMT_SFT 8
1141 #define RT5639_HP_R_SMT_DIS (0x0 << 8)
1142 #define RT5639_HP_R_SMT_EN (0x1 << 8)
1143 #define RT5639_HP_CD_PD_MASK (0x1 << 7)
1144 #define RT5639_HP_CD_PD_SFT 7
1145 #define RT5639_HP_CD_PD_DIS (0x0 << 7)
1146 #define RT5639_HP_CD_PD_EN (0x1 << 7)
1147 #define RT5639_RSTN_MASK (0x1 << 6)
1148 #define RT5639_RSTN_SFT 6
1149 #define RT5639_RSTN_DIS (0x0 << 6)
1150 #define RT5639_RSTN_EN (0x1 << 6)
1151 #define RT5639_RSTP_MASK (0x1 << 5)
1152 #define RT5639_RSTP_SFT 5
1153 #define RT5639_RSTP_DIS (0x0 << 5)
1154 #define RT5639_RSTP_EN (0x1 << 5)
1155 #define RT5639_HP_CO_MASK (0x1 << 4)
1156 #define RT5639_HP_CO_SFT 4
1157 #define RT5639_HP_CO_DIS (0x0 << 4)
1158 #define RT5639_HP_CO_EN (0x1 << 4)
1159 #define RT5639_HP_CP_MASK (0x1 << 3)
1160 #define RT5639_HP_CP_SFT 3
1161 #define RT5639_HP_CP_PD (0x0 << 3)
1162 #define RT5639_HP_CP_PU (0x1 << 3)
1163 #define RT5639_HP_SG_MASK (0x1 << 2)
1164 #define RT5639_HP_SG_SFT 2
1165 #define RT5639_HP_SG_DIS (0x0 << 2)
1166 #define RT5639_HP_SG_EN (0x1 << 2)
1167 #define RT5639_HP_DP_MASK (0x1 << 1)
1168 #define RT5639_HP_DP_SFT 1
1169 #define RT5639_HP_DP_PD (0x0 << 1)
1170 #define RT5639_HP_DP_PU (0x1 << 1)
1171 #define RT5639_HP_CB_MASK (0x1)
1172 #define RT5639_HP_CB_SFT 0
1173 #define RT5639_HP_CB_PD (0x0)
1174 #define RT5639_HP_CB_PU (0x1)
1176 /* Depop Mode Control 2 (0x8f) */
1177 #define RT5639_DEPOP_MASK (0x1 << 13)
1178 #define RT5639_DEPOP_SFT 13
1179 #define RT5639_DEPOP_AUTO (0x0 << 13)
1180 #define RT5639_DEPOP_MAN (0x1 << 13)
1181 #define RT5639_RAMP_MASK (0x1 << 12)
1182 #define RT5639_RAMP_SFT 12
1183 #define RT5639_RAMP_DIS (0x0 << 12)
1184 #define RT5639_RAMP_EN (0x1 << 12)
1185 #define RT5639_BPS_MASK (0x1 << 11)
1186 #define RT5639_BPS_SFT 11
1187 #define RT5639_BPS_DIS (0x0 << 11)
1188 #define RT5639_BPS_EN (0x1 << 11)
1189 #define RT5639_FAST_UPDN_MASK (0x1 << 10)
1190 #define RT5639_FAST_UPDN_SFT 10
1191 #define RT5639_FAST_UPDN_DIS (0x0 << 10)
1192 #define RT5639_FAST_UPDN_EN (0x1 << 10)
1193 #define RT5639_MRES_MASK (0x3 << 8)
1194 #define RT5639_MRES_SFT 8
1195 #define RT5639_MRES_15MO (0x0 << 8)
1196 #define RT5639_MRES_25MO (0x1 << 8)
1197 #define RT5639_MRES_35MO (0x2 << 8)
1198 #define RT5639_MRES_45MO (0x3 << 8)
1199 #define RT5639_VLO_MASK (0x1 << 7)
1200 #define RT5639_VLO_SFT 7
1201 #define RT5639_VLO_3V (0x0 << 7)
1202 #define RT5639_VLO_32V (0x1 << 7)
1203 #define RT5639_DIG_DP_MASK (0x1 << 6)
1204 #define RT5639_DIG_DP_SFT 6
1205 #define RT5639_DIG_DP_DIS (0x0 << 6)
1206 #define RT5639_DIG_DP_EN (0x1 << 6)
1207 #define RT5639_DP_TH_MASK (0x3 << 4)
1208 #define RT5639_DP_TH_SFT 4
1210 /* Depop Mode Control 3 (0x90) */
1211 #define RT5639_CP_SYS_MASK (0x7 << 12)
1212 #define RT5639_CP_SYS_SFT 12
1213 #define RT5639_CP_FQ1_MASK (0x7 << 8)
1214 #define RT5639_CP_FQ1_SFT 8
1215 #define RT5639_CP_FQ2_MASK (0x7 << 4)
1216 #define RT5639_CP_FQ2_SFT 4
1217 #define RT5639_CP_FQ3_MASK (0x7)
1218 #define RT5639_CP_FQ3_SFT 0
1219 #define RT5639_CP_FQ_1_5_KHZ 0
1220 #define RT5639_CP_FQ_3_KHZ 1
1221 #define RT5639_CP_FQ_6_KHZ 2
1222 #define RT5639_CP_FQ_12_KHZ 3
1223 #define RT5639_CP_FQ_24_KHZ 4
1224 #define RT5639_CP_FQ_48_KHZ 5
1225 #define RT5639_CP_FQ_96_KHZ 6
1226 #define RT5639_CP_FQ_192_KHZ 7
1228 /* HPOUT charge pump (0x91) */
1229 #define RT5639_OSW_L_MASK (0x1 << 11)
1230 #define RT5639_OSW_L_SFT 11
1231 #define RT5639_OSW_L_DIS (0x0 << 11)
1232 #define RT5639_OSW_L_EN (0x1 << 11)
1233 #define RT5639_OSW_R_MASK (0x1 << 10)
1234 #define RT5639_OSW_R_SFT 10
1235 #define RT5639_OSW_R_DIS (0x0 << 10)
1236 #define RT5639_OSW_R_EN (0x1 << 10)
1237 #define RT5639_PM_HP_MASK (0x3 << 8)
1238 #define RT5639_PM_HP_SFT 8
1239 #define RT5639_PM_HP_LV (0x0 << 8)
1240 #define RT5639_PM_HP_MV (0x1 << 8)
1241 #define RT5639_PM_HP_HV (0x2 << 8)
1242 #define RT5639_IB_HP_MASK (0x3 << 6)
1243 #define RT5639_IB_HP_SFT 6
1244 #define RT5639_IB_HP_125IL (0x0 << 6)
1245 #define RT5639_IB_HP_25IL (0x1 << 6)
1246 #define RT5639_IB_HP_5IL (0x2 << 6)
1247 #define RT5639_IB_HP_1IL (0x3 << 6)
1249 /* PV detection and SPK gain control (0x92) */
1250 #define RT5639_PVDD_DET_MASK (0x1 << 15)
1251 #define RT5639_PVDD_DET_SFT 15
1252 #define RT5639_PVDD_DET_DIS (0x0 << 15)
1253 #define RT5639_PVDD_DET_EN (0x1 << 15)
1254 #define RT5639_SPK_AG_MASK (0x1 << 14)
1255 #define RT5639_SPK_AG_SFT 14
1256 #define RT5639_SPK_AG_DIS (0x0 << 14)
1257 #define RT5639_SPK_AG_EN (0x1 << 14)
1259 /* Micbias Control (0x93) */
1260 #define RT5639_MIC1_BS_MASK (0x1 << 15)
1261 #define RT5639_MIC1_BS_SFT 15
1262 #define RT5639_MIC1_BS_9AV (0x0 << 15)
1263 #define RT5639_MIC1_BS_75AV (0x1 << 15)
1264 #define RT5639_MIC2_BS_MASK (0x1 << 14)
1265 #define RT5639_MIC2_BS_SFT 14
1266 #define RT5639_MIC2_BS_9AV (0x0 << 14)
1267 #define RT5639_MIC2_BS_75AV (0x1 << 14)
1268 #define RT5639_MIC1_CLK_MASK (0x1 << 13)
1269 #define RT5639_MIC1_CLK_SFT 13
1270 #define RT5639_MIC1_CLK_DIS (0x0 << 13)
1271 #define RT5639_MIC1_CLK_EN (0x1 << 13)
1272 #define RT5639_MIC2_CLK_MASK (0x1 << 12)
1273 #define RT5639_MIC2_CLK_SFT 12
1274 #define RT5639_MIC2_CLK_DIS (0x0 << 12)
1275 #define RT5639_MIC2_CLK_EN (0x1 << 12)
1276 #define RT5639_MIC1_OVCD_MASK (0x1 << 11)
1277 #define RT5639_MIC1_OVCD_SFT 11
1278 #define RT5639_MIC1_OVCD_DIS (0x0 << 11)
1279 #define RT5639_MIC1_OVCD_EN (0x1 << 11)
1280 #define RT5639_MIC1_OVTH_MASK (0x3 << 9)
1281 #define RT5639_MIC1_OVTH_SFT 9
1282 #define RT5639_MIC1_OVTH_600UA (0x0 << 9)
1283 #define RT5639_MIC1_OVTH_1500UA (0x1 << 9)
1284 #define RT5639_MIC1_OVTH_2000UA (0x2 << 9)
1285 #define RT5639_MIC2_OVCD_MASK (0x1 << 8)
1286 #define RT5639_MIC2_OVCD_SFT 8
1287 #define RT5639_MIC2_OVCD_DIS (0x0 << 8)
1288 #define RT5639_MIC2_OVCD_EN (0x1 << 8)
1289 #define RT5639_MIC2_OVTH_MASK (0x3 << 6)
1290 #define RT5639_MIC2_OVTH_SFT 6
1291 #define RT5639_MIC2_OVTH_600UA (0x0 << 6)
1292 #define RT5639_MIC2_OVTH_1500UA (0x1 << 6)
1293 #define RT5639_MIC2_OVTH_2000UA (0x2 << 6)
1294 #define RT5639_PWR_MB_MASK (0x1 << 5)
1295 #define RT5639_PWR_MB_SFT 5
1296 #define RT5639_PWR_MB_PD (0x0 << 5)
1297 #define RT5639_PWR_MB_PU (0x1 << 5)
1298 #define RT5639_PWR_CLK25M_MASK (0x1 << 4)
1299 #define RT5639_PWR_CLK25M_SFT 4
1300 #define RT5639_PWR_CLK25M_PD (0x0 << 4)
1301 #define RT5639_PWR_CLK25M_PU (0x1 << 4)
1303 /* EQ Control 1 (0xb0) */
1304 #define RT5639_EQ_SRC_MASK (0x1 << 15)
1305 #define RT5639_EQ_SRC_SFT 15
1306 #define RT5639_EQ_SRC_DAC (0x0 << 15)
1307 #define RT5639_EQ_SRC_ADC (0x1 << 15)
1308 #define RT5639_EQ_UPD (0x1 << 14)
1309 #define RT5639_EQ_UPD_BIT 14
1310 #define RT5639_EQ_CD_MASK (0x1 << 13)
1311 #define RT5639_EQ_CD_SFT 13
1312 #define RT5639_EQ_CD_DIS (0x0 << 13)
1313 #define RT5639_EQ_CD_EN (0x1 << 13)
1314 #define RT5639_EQ_DITH_MASK (0x3 << 8)
1315 #define RT5639_EQ_DITH_SFT 8
1316 #define RT5639_EQ_DITH_NOR (0x0 << 8)
1317 #define RT5639_EQ_DITH_LSB (0x1 << 8)
1318 #define RT5639_EQ_DITH_LSB_1 (0x2 << 8)
1319 #define RT5639_EQ_DITH_LSB_2 (0x3 << 8)
1321 /* EQ Control 2 (0xb1) */
1322 #define RT5639_EQ_HPF1_M_MASK (0x1 << 8)
1323 #define RT5639_EQ_HPF1_M_SFT 8
1324 #define RT5639_EQ_HPF1_M_HI (0x0 << 8)
1325 #define RT5639_EQ_HPF1_M_1ST (0x1 << 8)
1326 #define RT5639_EQ_LPF1_M_MASK (0x1 << 7)
1327 #define RT5639_EQ_LPF1_M_SFT 7
1328 #define RT5639_EQ_LPF1_M_LO (0x0 << 7)
1329 #define RT5639_EQ_LPF1_M_1ST (0x1 << 7)
1330 #define RT5639_EQ_HPF2_MASK (0x1 << 6)
1331 #define RT5639_EQ_HPF2_SFT 6
1332 #define RT5639_EQ_HPF2_DIS (0x0 << 6)
1333 #define RT5639_EQ_HPF2_EN (0x1 << 6)
1334 #define RT5639_EQ_HPF1_MASK (0x1 << 5)
1335 #define RT5639_EQ_HPF1_SFT 5
1336 #define RT5639_EQ_HPF1_DIS (0x0 << 5)
1337 #define RT5639_EQ_HPF1_EN (0x1 << 5)
1338 #define RT5639_EQ_BPF4_MASK (0x1 << 4)
1339 #define RT5639_EQ_BPF4_SFT 4
1340 #define RT5639_EQ_BPF4_DIS (0x0 << 4)
1341 #define RT5639_EQ_BPF4_EN (0x1 << 4)
1342 #define RT5639_EQ_BPF3_MASK (0x1 << 3)
1343 #define RT5639_EQ_BPF3_SFT 3
1344 #define RT5639_EQ_BPF3_DIS (0x0 << 3)
1345 #define RT5639_EQ_BPF3_EN (0x1 << 3)
1346 #define RT5639_EQ_BPF2_MASK (0x1 << 2)
1347 #define RT5639_EQ_BPF2_SFT 2
1348 #define RT5639_EQ_BPF2_DIS (0x0 << 2)
1349 #define RT5639_EQ_BPF2_EN (0x1 << 2)
1350 #define RT5639_EQ_BPF1_MASK (0x1 << 1)
1351 #define RT5639_EQ_BPF1_SFT 1
1352 #define RT5639_EQ_BPF1_DIS (0x0 << 1)
1353 #define RT5639_EQ_BPF1_EN (0x1 << 1)
1354 #define RT5639_EQ_LPF_MASK (0x1)
1355 #define RT5639_EQ_LPF_SFT 0
1356 #define RT5639_EQ_LPF_DIS (0x0)
1357 #define RT5639_EQ_LPF_EN (0x1)
1358 #define RT5639_EQ_CTRL_MASK (0x7f)
1360 /* Memory Test (0xb2) */
1361 #define RT5639_MT_MASK (0x1 << 15)
1362 #define RT5639_MT_SFT 15
1363 #define RT5639_MT_DIS (0x0 << 15)
1364 #define RT5639_MT_EN (0x1 << 15)
1366 /* DRC/AGC Control 1 (0xb4) */
1367 #define RT5639_DRC_AGC_P_MASK (0x1 << 15)
1368 #define RT5639_DRC_AGC_P_SFT 15
1369 #define RT5639_DRC_AGC_P_DAC (0x0 << 15)
1370 #define RT5639_DRC_AGC_P_ADC (0x1 << 15)
1371 #define RT5639_DRC_AGC_MASK (0x1 << 14)
1372 #define RT5639_DRC_AGC_SFT 14
1373 #define RT5639_DRC_AGC_DIS (0x0 << 14)
1374 #define RT5639_DRC_AGC_EN (0x1 << 14)
1375 #define RT5639_DRC_AGC_UPD (0x1 << 13)
1376 #define RT5639_DRC_AGC_UPD_BIT 13
1377 #define RT5639_DRC_AGC_AR_MASK (0x1f << 8)
1378 #define RT5639_DRC_AGC_AR_SFT 8
1379 #define RT5639_DRC_AGC_R_MASK (0x7 << 5)
1380 #define RT5639_DRC_AGC_R_SFT 5
1381 #define RT5639_DRC_AGC_R_48K (0x1 << 5)
1382 #define RT5639_DRC_AGC_R_96K (0x2 << 5)
1383 #define RT5639_DRC_AGC_R_192K (0x3 << 5)
1384 #define RT5639_DRC_AGC_R_441K (0x5 << 5)
1385 #define RT5639_DRC_AGC_R_882K (0x6 << 5)
1386 #define RT5639_DRC_AGC_R_1764K (0x7 << 5)
1387 #define RT5639_DRC_AGC_RC_MASK (0x1f)
1388 #define RT5639_DRC_AGC_RC_SFT 0
1390 /* DRC/AGC Control 2 (0xb5) */
1391 #define RT5639_DRC_AGC_POB_MASK (0x3f << 8)
1392 #define RT5639_DRC_AGC_POB_SFT 8
1393 #define RT5639_DRC_AGC_CP_MASK (0x1 << 7)
1394 #define RT5639_DRC_AGC_CP_SFT 7
1395 #define RT5639_DRC_AGC_CP_DIS (0x0 << 7)
1396 #define RT5639_DRC_AGC_CP_EN (0x1 << 7)
1397 #define RT5639_DRC_AGC_CPR_MASK (0x3 << 5)
1398 #define RT5639_DRC_AGC_CPR_SFT 5
1399 #define RT5639_DRC_AGC_CPR_1_1 (0x0 << 5)
1400 #define RT5639_DRC_AGC_CPR_1_2 (0x1 << 5)
1401 #define RT5639_DRC_AGC_CPR_1_3 (0x2 << 5)
1402 #define RT5639_DRC_AGC_CPR_1_4 (0x3 << 5)
1403 #define RT5639_DRC_AGC_PRB_MASK (0x1f)
1404 #define RT5639_DRC_AGC_PRB_SFT 0
1406 /* DRC/AGC Control 3 (0xb6) */
1407 #define RT5639_DRC_AGC_NGB_MASK (0xf << 12)
1408 #define RT5639_DRC_AGC_NGB_SFT 12
1409 #define RT5639_DRC_AGC_TAR_MASK (0x1f << 7)
1410 #define RT5639_DRC_AGC_TAR_SFT 7
1411 #define RT5639_DRC_AGC_NG_MASK (0x1 << 6)
1412 #define RT5639_DRC_AGC_NG_SFT 6
1413 #define RT5639_DRC_AGC_NG_DIS (0x0 << 6)
1414 #define RT5639_DRC_AGC_NG_EN (0x1 << 6)
1415 #define RT5639_DRC_AGC_NGH_MASK (0x1 << 5)
1416 #define RT5639_DRC_AGC_NGH_SFT 5
1417 #define RT5639_DRC_AGC_NGH_DIS (0x0 << 5)
1418 #define RT5639_DRC_AGC_NGH_EN (0x1 << 5)
1419 #define RT5639_DRC_AGC_NGT_MASK (0x1f)
1420 #define RT5639_DRC_AGC_NGT_SFT 0
1422 /* ANC Control 1 (0xb8) */
1423 #define RT5639_ANC_M_MASK (0x1 << 15)
1424 #define RT5639_ANC_M_SFT 15
1425 #define RT5639_ANC_M_NOR (0x0 << 15)
1426 #define RT5639_ANC_M_REV (0x1 << 15)
1427 #define RT5639_ANC_MASK (0x1 << 14)
1428 #define RT5639_ANC_SFT 14
1429 #define RT5639_ANC_DIS (0x0 << 14)
1430 #define RT5639_ANC_EN (0x1 << 14)
1431 #define RT5639_ANC_MD_MASK (0x3 << 12)
1432 #define RT5639_ANC_MD_SFT 12
1433 #define RT5639_ANC_MD_DIS (0x0 << 12)
1434 #define RT5639_ANC_MD_67MS (0x1 << 12)
1435 #define RT5639_ANC_MD_267MS (0x2 << 12)
1436 #define RT5639_ANC_MD_1067MS (0x3 << 12)
1437 #define RT5639_ANC_SN_MASK (0x1 << 11)
1438 #define RT5639_ANC_SN_SFT 11
1439 #define RT5639_ANC_SN_DIS (0x0 << 11)
1440 #define RT5639_ANC_SN_EN (0x1 << 11)
1441 #define RT5639_ANC_CLK_MASK (0x1 << 10)
1442 #define RT5639_ANC_CLK_SFT 10
1443 #define RT5639_ANC_CLK_ANC (0x0 << 10)
1444 #define RT5639_ANC_CLK_REG (0x1 << 10)
1445 #define RT5639_ANC_ZCD_MASK (0x3 << 8)
1446 #define RT5639_ANC_ZCD_SFT 8
1447 #define RT5639_ANC_ZCD_DIS (0x0 << 8)
1448 #define RT5639_ANC_ZCD_T1 (0x1 << 8)
1449 #define RT5639_ANC_ZCD_T2 (0x2 << 8)
1450 #define RT5639_ANC_ZCD_WT (0x3 << 8)
1451 #define RT5639_ANC_CS_MASK (0x1 << 7)
1452 #define RT5639_ANC_CS_SFT 7
1453 #define RT5639_ANC_CS_DIS (0x0 << 7)
1454 #define RT5639_ANC_CS_EN (0x1 << 7)
1455 #define RT5639_ANC_SW_MASK (0x1 << 6)
1456 #define RT5639_ANC_SW_SFT 6
1457 #define RT5639_ANC_SW_NOR (0x0 << 6)
1458 #define RT5639_ANC_SW_AUTO (0x1 << 6)
1459 #define RT5639_ANC_CO_L_MASK (0x3f)
1460 #define RT5639_ANC_CO_L_SFT 0
1462 /* ANC Control 2 (0xb6) */
1463 #define RT5639_ANC_FG_R_MASK (0xf << 12)
1464 #define RT5639_ANC_FG_R_SFT 12
1465 #define RT5639_ANC_FG_L_MASK (0xf << 8)
1466 #define RT5639_ANC_FG_L_SFT 8
1467 #define RT5639_ANC_CG_R_MASK (0xf << 4)
1468 #define RT5639_ANC_CG_R_SFT 4
1469 #define RT5639_ANC_CG_L_MASK (0xf)
1470 #define RT5639_ANC_CG_L_SFT 0
1472 /* ANC Control 3 (0xb6) */
1473 #define RT5639_ANC_CD_MASK (0x1 << 6)
1474 #define RT5639_ANC_CD_SFT 6
1475 #define RT5639_ANC_CD_BOTH (0x0 << 6)
1476 #define RT5639_ANC_CD_IND (0x1 << 6)
1477 #define RT5639_ANC_CO_R_MASK (0x3f)
1478 #define RT5639_ANC_CO_R_SFT 0
1480 /* Jack Detect Control (0xbb) */
1481 #define RT5639_JD_MASK (0x7 << 13)
1482 #define RT5639_JD_SFT 13
1483 #define RT5639_JD_DIS (0x0 << 13)
1484 #define RT5639_JD_GPIO1 (0x1 << 13)
1485 #define RT5639_JD_JD1_IN4P (0x2 << 13)
1486 #define RT5639_JD_JD2_IN4N (0x3 << 13)
1487 #define RT5639_JD_GPIO2 (0x4 << 13)
1488 #define RT5639_JD_GPIO3 (0x5 << 13)
1489 #define RT5639_JD_GPIO4 (0x6 << 13)
1490 #define RT5639_JD_HP_MASK (0x1 << 11)
1491 #define RT5639_JD_HP_SFT 11
1492 #define RT5639_JD_HP_DIS (0x0 << 11)
1493 #define RT5639_JD_HP_EN (0x1 << 11)
1494 #define RT5639_JD_HP_TRG_MASK (0x1 << 10)
1495 #define RT5639_JD_HP_TRG_SFT 10
1496 #define RT5639_JD_HP_TRG_LO (0x0 << 10)
1497 #define RT5639_JD_HP_TRG_HI (0x1 << 10)
1498 #define RT5639_JD_SPL_MASK (0x1 << 9)
1499 #define RT5639_JD_SPL_SFT 9
1500 #define RT5639_JD_SPL_DIS (0x0 << 9)
1501 #define RT5639_JD_SPL_EN (0x1 << 9)
1502 #define RT5639_JD_SPL_TRG_MASK (0x1 << 8)
1503 #define RT5639_JD_SPL_TRG_SFT 8
1504 #define RT5639_JD_SPL_TRG_LO (0x0 << 8)
1505 #define RT5639_JD_SPL_TRG_HI (0x1 << 8)
1506 #define RT5639_JD_SPR_MASK (0x1 << 7)
1507 #define RT5639_JD_SPR_SFT 7
1508 #define RT5639_JD_SPR_DIS (0x0 << 7)
1509 #define RT5639_JD_SPR_EN (0x1 << 7)
1510 #define RT5639_JD_SPR_TRG_MASK (0x1 << 6)
1511 #define RT5639_JD_SPR_TRG_SFT 6
1512 #define RT5639_JD_SPR_TRG_LO (0x0 << 6)
1513 #define RT5639_JD_SPR_TRG_HI (0x1 << 6)
1514 #define RT5639_JD_MO_MASK (0x1 << 5)
1515 #define RT5639_JD_MO_SFT 5
1516 #define RT5639_JD_MO_DIS (0x0 << 5)
1517 #define RT5639_JD_MO_EN (0x1 << 5)
1518 #define RT5639_JD_MO_TRG_MASK (0x1 << 4)
1519 #define RT5639_JD_MO_TRG_SFT 4
1520 #define RT5639_JD_MO_TRG_LO (0x0 << 4)
1521 #define RT5639_JD_MO_TRG_HI (0x1 << 4)
1522 #define RT5639_JD_LO_MASK (0x1 << 3)
1523 #define RT5639_JD_LO_SFT 3
1524 #define RT5639_JD_LO_DIS (0x0 << 3)
1525 #define RT5639_JD_LO_EN (0x1 << 3)
1526 #define RT5639_JD_LO_TRG_MASK (0x1 << 2)
1527 #define RT5639_JD_LO_TRG_SFT 2
1528 #define RT5639_JD_LO_TRG_LO (0x0 << 2)
1529 #define RT5639_JD_LO_TRG_HI (0x1 << 2)
1530 #define RT5639_JD1_IN4P_MASK (0x1 << 1)
1531 #define RT5639_JD1_IN4P_SFT 1
1532 #define RT5639_JD1_IN4P_DIS (0x0 << 1)
1533 #define RT5639_JD1_IN4P_EN (0x1 << 1)
1534 #define RT5639_JD2_IN4N_MASK (0x1)
1535 #define RT5639_JD2_IN4N_SFT 0
1536 #define RT5639_JD2_IN4N_DIS (0x0)
1537 #define RT5639_JD2_IN4N_EN (0x1)
1539 /* Jack detect for ANC (0xbc) */
1540 #define RT5639_ANC_DET_MASK (0x3 << 4)
1541 #define RT5639_ANC_DET_SFT 4
1542 #define RT5639_ANC_DET_DIS (0x0 << 4)
1543 #define RT5639_ANC_DET_MB1 (0x1 << 4)
1544 #define RT5639_ANC_DET_MB2 (0x2 << 4)
1545 #define RT5639_ANC_DET_JD (0x3 << 4)
1546 #define RT5639_AD_TRG_MASK (0x1 << 3)
1547 #define RT5639_AD_TRG_SFT 3
1548 #define RT5639_AD_TRG_LO (0x0 << 3)
1549 #define RT5639_AD_TRG_HI (0x1 << 3)
1550 #define RT5639_ANCM_DET_MASK (0x3 << 4)
1551 #define RT5639_ANCM_DET_SFT 4
1552 #define RT5639_ANCM_DET_DIS (0x0 << 4)
1553 #define RT5639_ANCM_DET_MB1 (0x1 << 4)
1554 #define RT5639_ANCM_DET_MB2 (0x2 << 4)
1555 #define RT5639_ANCM_DET_JD (0x3 << 4)
1556 #define RT5639_AMD_TRG_MASK (0x1 << 3)
1557 #define RT5639_AMD_TRG_SFT 3
1558 #define RT5639_AMD_TRG_LO (0x0 << 3)
1559 #define RT5639_AMD_TRG_HI (0x1 << 3)
1561 /* IRQ Control 1 (0xbd) */
1562 #define RT5639_IRQ_JD_MASK (0x1 << 15)
1563 #define RT5639_IRQ_JD_SFT 15
1564 #define RT5639_IRQ_JD_BP (0x0 << 15)
1565 #define RT5639_IRQ_JD_NOR (0x1 << 15)
1566 #define RT5639_IRQ_OT_MASK (0x1 << 14)
1567 #define RT5639_IRQ_OT_SFT 14
1568 #define RT5639_IRQ_OT_BP (0x0 << 14)
1569 #define RT5639_IRQ_OT_NOR (0x1 << 14)
1570 #define RT5639_JD_STKY_MASK (0x1 << 13)
1571 #define RT5639_JD_STKY_SFT 13
1572 #define RT5639_JD_STKY_DIS (0x0 << 13)
1573 #define RT5639_JD_STKY_EN (0x1 << 13)
1574 #define RT5639_OT_STKY_MASK (0x1 << 12)
1575 #define RT5639_OT_STKY_SFT 12
1576 #define RT5639_OT_STKY_DIS (0x0 << 12)
1577 #define RT5639_OT_STKY_EN (0x1 << 12)
1578 #define RT5639_JD_P_MASK (0x1 << 11)
1579 #define RT5639_JD_P_SFT 11
1580 #define RT5639_JD_P_NOR (0x0 << 11)
1581 #define RT5639_JD_P_INV (0x1 << 11)
1582 #define RT5639_OT_P_MASK (0x1 << 10)
1583 #define RT5639_OT_P_SFT 10
1584 #define RT5639_OT_P_NOR (0x0 << 10)
1585 #define RT5639_OT_P_INV (0x1 << 10)
1587 /* IRQ Control 2 (0xbe) */
1588 #define RT5639_IRQ_MB1_OC_MASK (0x1 << 15)
1589 #define RT5639_IRQ_MB1_OC_SFT 15
1590 #define RT5639_IRQ_MB1_OC_BP (0x0 << 15)
1591 #define RT5639_IRQ_MB1_OC_NOR (0x1 << 15)
1592 #define RT5639_IRQ_MB2_OC_MASK (0x1 << 14)
1593 #define RT5639_IRQ_MB2_OC_SFT 14
1594 #define RT5639_IRQ_MB2_OC_BP (0x0 << 14)
1595 #define RT5639_IRQ_MB2_OC_NOR (0x1 << 14)
1596 #define RT5639_MB1_OC_STKY_MASK (0x1 << 11)
1597 #define RT5639_MB1_OC_STKY_SFT 11
1598 #define RT5639_MB1_OC_STKY_DIS (0x0 << 11)
1599 #define RT5639_MB1_OC_STKY_EN (0x1 << 11)
1600 #define RT5639_MB2_OC_STKY_MASK (0x1 << 10)
1601 #define RT5639_MB2_OC_STKY_SFT 10
1602 #define RT5639_MB2_OC_STKY_DIS (0x0 << 10)
1603 #define RT5639_MB2_OC_STKY_EN (0x1 << 10)
1604 #define RT5639_MB1_OC_P_MASK (0x1 << 7)
1605 #define RT5639_MB1_OC_P_SFT 7
1606 #define RT5639_MB1_OC_P_NOR (0x0 << 7)
1607 #define RT5639_MB1_OC_P_INV (0x1 << 7)
1608 #define RT5639_MB2_OC_P_MASK (0x1 << 6)
1609 #define RT5639_MB2_OC_P_SFT 6
1610 #define RT5639_MB2_OC_P_NOR (0x0 << 6)
1611 #define RT5639_MB2_OC_P_INV (0x1 << 6)
1612 #define RT5639_MB1_OC_CLR (0x1 << 3)
1613 #define RT5639_MB1_OC_CLR_SFT 3
1614 #define RT5639_MB2_OC_CLR (0x1 << 2)
1615 #define RT5639_MB2_OC_CLR_SFT 2
1617 /* GPIO Control 1 (0xc0) */
1618 #define RT5639_GP1_PIN_MASK (0x1 << 15)
1619 #define RT5639_GP1_PIN_SFT 15
1620 #define RT5639_GP1_PIN_GPIO1 (0x0 << 15)
1621 #define RT5639_GP1_PIN_IRQ (0x1 << 15)
1622 #define RT5639_GP2_PIN_MASK (0x1 << 14)
1623 #define RT5639_GP2_PIN_SFT 14
1624 #define RT5639_GP2_PIN_GPIO2 (0x0 << 14)
1625 #define RT5639_GP2_PIN_DMIC1_SCL (0x1 << 14)
1626 #define RT5639_GP3_PIN_MASK (0x3 << 12)
1627 #define RT5639_GP3_PIN_SFT 12
1628 #define RT5639_GP3_PIN_GPIO3 (0x0 << 12)
1629 #define RT5639_GP3_PIN_DMIC1_SDA (0x1 << 12)
1630 #define RT5639_GP3_PIN_IRQ (0x2 << 12)
1631 #define RT5639_GP4_PIN_MASK (0x1 << 11)
1632 #define RT5639_GP4_PIN_SFT 11
1633 #define RT5639_GP4_PIN_GPIO4 (0x0 << 11)
1634 #define RT5639_GP4_PIN_DMIC2_SDA (0x1 << 11)
1635 #define RT5639_DP_SIG_MASK (0x1 << 10)
1636 #define RT5639_DP_SIG_SFT 10
1637 #define RT5639_DP_SIG_TEST (0x0 << 10)
1638 #define RT5639_DP_SIG_AP (0x1 << 10)
1639 #define RT5639_GPIO_M_MASK (0x1 << 9)
1640 #define RT5639_GPIO_M_SFT 9
1641 #define RT5639_GPIO_M_FLT (0x0 << 9)
1642 #define RT5639_GPIO_M_PH (0x1 << 9)
1644 /* GPIO Control 3 (0xc2) */
1645 #define RT5639_GP4_PF_MASK (0x1 << 11)
1646 #define RT5639_GP4_PF_SFT 11
1647 #define RT5639_GP4_PF_IN (0x0 << 11)
1648 #define RT5639_GP4_PF_OUT (0x1 << 11)
1649 #define RT5639_GP4_OUT_MASK (0x1 << 10)
1650 #define RT5639_GP4_OUT_SFT 10
1651 #define RT5639_GP4_OUT_LO (0x0 << 10)
1652 #define RT5639_GP4_OUT_HI (0x1 << 10)
1653 #define RT5639_GP4_P_MASK (0x1 << 9)
1654 #define RT5639_GP4_P_SFT 9
1655 #define RT5639_GP4_P_NOR (0x0 << 9)
1656 #define RT5639_GP4_P_INV (0x1 << 9)
1657 #define RT5639_GP3_PF_MASK (0x1 << 8)
1658 #define RT5639_GP3_PF_SFT 8
1659 #define RT5639_GP3_PF_IN (0x0 << 8)
1660 #define RT5639_GP3_PF_OUT (0x1 << 8)
1661 #define RT5639_GP3_OUT_MASK (0x1 << 7)
1662 #define RT5639_GP3_OUT_SFT 7
1663 #define RT5639_GP3_OUT_LO (0x0 << 7)
1664 #define RT5639_GP3_OUT_HI (0x1 << 7)
1665 #define RT5639_GP3_P_MASK (0x1 << 6)
1666 #define RT5639_GP3_P_SFT 6
1667 #define RT5639_GP3_P_NOR (0x0 << 6)
1668 #define RT5639_GP3_P_INV (0x1 << 6)
1669 #define RT5639_GP2_PF_MASK (0x1 << 5)
1670 #define RT5639_GP2_PF_SFT 5
1671 #define RT5639_GP2_PF_IN (0x0 << 5)
1672 #define RT5639_GP2_PF_OUT (0x1 << 5)
1673 #define RT5639_GP2_OUT_MASK (0x1 << 4)
1674 #define RT5639_GP2_OUT_SFT 4
1675 #define RT5639_GP2_OUT_LO (0x0 << 4)
1676 #define RT5639_GP2_OUT_HI (0x1 << 4)
1677 #define RT5639_GP2_P_MASK (0x1 << 3)
1678 #define RT5639_GP2_P_SFT 3
1679 #define RT5639_GP2_P_NOR (0x0 << 3)
1680 #define RT5639_GP2_P_INV (0x1 << 3)
1681 #define RT5639_GP1_PF_MASK (0x1 << 2)
1682 #define RT5639_GP1_PF_SFT 2
1683 #define RT5639_GP1_PF_IN (0x0 << 2)
1684 #define RT5639_GP1_PF_OUT (0x1 << 2)
1685 #define RT5639_GP1_OUT_MASK (0x1 << 1)
1686 #define RT5639_GP1_OUT_SFT 1
1687 #define RT5639_GP1_OUT_LO (0x0 << 1)
1688 #define RT5639_GP1_OUT_HI (0x1 << 1)
1689 #define RT5639_GP1_P_MASK (0x1)
1690 #define RT5639_GP1_P_SFT 0
1691 #define RT5639_GP1_P_NOR (0x0)
1692 #define RT5639_GP1_P_INV (0x1)
1694 /* FM34-500 Register Control 1 (0xc4) */
1695 #define RT5639_DSP_ADD_SFT 0
1697 /* FM34-500 Register Control 2 (0xc5) */
1698 #define RT5639_DSP_DAT_SFT 0
1700 /* FM34-500 Register Control 3 (0xc6) */
1701 #define RT5639_DSP_BUSY_MASK (0x1 << 15)
1702 #define RT5639_DSP_BUSY_BIT 15
1703 #define RT5639_DSP_DS_MASK (0x1 << 14)
1704 #define RT5639_DSP_DS_SFT 14
1705 #define RT5639_DSP_DS_FM3010 (0x1 << 14)
1706 #define RT5639_DSP_DS_TEMP (0x1 << 14)
1707 #define RT5639_DSP_CLK_MASK (0x3 << 12)
1708 #define RT5639_DSP_CLK_SFT 12
1709 #define RT5639_DSP_CLK_384K (0x0 << 12)
1710 #define RT5639_DSP_CLK_192K (0x1 << 12)
1711 #define RT5639_DSP_CLK_96K (0x2 << 12)
1712 #define RT5639_DSP_CLK_64K (0x3 << 12)
1713 #define RT5639_DSP_PD_PIN_MASK (0x1 << 11)
1714 #define RT5639_DSP_PD_PIN_SFT 11
1715 #define RT5639_DSP_PD_PIN_LO (0x0 << 11)
1716 #define RT5639_DSP_PD_PIN_HI (0x1 << 11)
1717 #define RT5639_DSP_RST_PIN_MASK (0x1 << 10)
1718 #define RT5639_DSP_RST_PIN_SFT 10
1719 #define RT5639_DSP_RST_PIN_LO (0x0 << 10)
1720 #define RT5639_DSP_RST_PIN_HI (0x1 << 10)
1721 #define RT5639_DSP_R_EN (0x1 << 9)
1722 #define RT5639_DSP_W_EN (0x1 << 8)
1723 #define RT5639_DSP_CMD_MASK (0xff)
1724 #define RT5639_DSP_CMD_PE (0x0d) /* Patch Entry */
1725 #define RT5639_DSP_CMD_MW (0x3b) /* Memory Write */
1726 #define RT5639_DSP_CMD_MR (0x37) /* Memory Read */
1727 #define RT5639_DSP_CMD_RR (0x60) /* Register Read */
1728 #define RT5639_DSP_CMD_RW (0x68) /* Register Write */
1729 #define RT5639_DSP_REG_DATHI (0x26) /* High Data Addr */
1730 #define RT5639_DSP_REG_DATLO (0x25) /* Low Data Addr */
1732 /* Programmable Register Array Control 1 (0xc8) */
1733 #define RT5639_REG_SEQ_MASK (0xf << 12)
1734 #define RT5639_REG_SEQ_SFT 12
1735 #define RT5639_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1736 #define RT5639_SEQ1_ST_SFT 11
1737 #define RT5639_SEQ1_ST_RUN (0x0 << 11)
1738 #define RT5639_SEQ1_ST_FIN (0x1 << 11)
1739 #define RT5639_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1740 #define RT5639_SEQ2_ST_SFT 10
1741 #define RT5639_SEQ2_ST_RUN (0x0 << 10)
1742 #define RT5639_SEQ2_ST_FIN (0x1 << 10)
1743 #define RT5639_REG_LV_MASK (0x1 << 9)
1744 #define RT5639_REG_LV_SFT 9
1745 #define RT5639_REG_LV_MX (0x0 << 9)
1746 #define RT5639_REG_LV_PR (0x1 << 9)
1747 #define RT5639_SEQ_2_PT_MASK (0x1 << 8)
1748 #define RT5639_SEQ_2_PT_BIT 8
1749 #define RT5639_REG_IDX_MASK (0xff)
1750 #define RT5639_REG_IDX_SFT 0
1752 /* Programmable Register Array Control 2 (0xc9) */
1753 #define RT5639_REG_DAT_MASK (0xffff)
1754 #define RT5639_REG_DAT_SFT 0
1756 /* Programmable Register Array Control 3 (0xca) */
1757 #define RT5639_SEQ_DLY_MASK (0xff << 8)
1758 #define RT5639_SEQ_DLY_SFT 8
1759 #define RT5639_PROG_MASK (0x1 << 7)
1760 #define RT5639_PROG_SFT 7
1761 #define RT5639_PROG_DIS (0x0 << 7)
1762 #define RT5639_PROG_EN (0x1 << 7)
1763 #define RT5639_SEQ1_PT_RUN (0x1 << 6)
1764 #define RT5639_SEQ1_PT_RUN_BIT 6
1765 #define RT5639_SEQ2_PT_RUN (0x1 << 5)
1766 #define RT5639_SEQ2_PT_RUN_BIT 5
1768 /* Programmable Register Array Control 4 (0xcb) */
1769 #define RT5639_SEQ1_START_MASK (0xf << 8)
1770 #define RT5639_SEQ1_START_SFT 8
1771 #define RT5639_SEQ1_END_MASK (0xf)
1772 #define RT5639_SEQ1_END_SFT 0
1774 /* Programmable Register Array Control 5 (0xcc) */
1775 #define RT5639_SEQ2_START_MASK (0xf << 8)
1776 #define RT5639_SEQ2_START_SFT 8
1777 #define RT5639_SEQ2_END_MASK (0xf)
1778 #define RT5639_SEQ2_END_SFT 0
1780 /* Scramble Function (0xcd) */
1781 #define RT5639_SCB_KEY_MASK (0xff)
1782 #define RT5639_SCB_KEY_SFT 0
1784 /* Scramble Control (0xce) */
1785 #define RT5639_SCB_SWAP_MASK (0x1 << 15)
1786 #define RT5639_SCB_SWAP_SFT 15
1787 #define RT5639_SCB_SWAP_DIS (0x0 << 15)
1788 #define RT5639_SCB_SWAP_EN (0x1 << 15)
1789 #define RT5639_SCB_MASK (0x1 << 14)
1790 #define RT5639_SCB_SFT 14
1791 #define RT5639_SCB_DIS (0x0 << 14)
1792 #define RT5639_SCB_EN (0x1 << 14)
1794 /* Baseback Control (0xcf) */
1795 #define RT5639_BB_MASK (0x1 << 15)
1796 #define RT5639_BB_SFT 15
1797 #define RT5639_BB_DIS (0x0 << 15)
1798 #define RT5639_BB_EN (0x1 << 15)
1799 #define RT5639_BB_CT_MASK (0x7 << 12)
1800 #define RT5639_BB_CT_SFT 12
1801 #define RT5639_BB_CT_A (0x0 << 12)
1802 #define RT5639_BB_CT_B (0x1 << 12)
1803 #define RT5639_BB_CT_C (0x2 << 12)
1804 #define RT5639_BB_CT_D (0x3 << 12)
1805 #define RT5639_M_BB_L_MASK (0x1 << 9)
1806 #define RT5639_M_BB_L_SFT 9
1807 #define RT5639_M_BB_R_MASK (0x1 << 8)
1808 #define RT5639_M_BB_R_SFT 8
1809 #define RT5639_M_BB_HPF_L_MASK (0x1 << 7)
1810 #define RT5639_M_BB_HPF_L_SFT 7
1811 #define RT5639_M_BB_HPF_R_MASK (0x1 << 6)
1812 #define RT5639_M_BB_HPF_R_SFT 6
1813 #define RT5639_G_BB_BST_MASK (0x3f)
1814 #define RT5639_G_BB_BST_SFT 0
1816 /* MP3 Plus Control 1 (0xd0) */
1817 #define RT5639_M_MP3_L_MASK (0x1 << 15)
1818 #define RT5639_M_MP3_L_SFT 15
1819 #define RT5639_M_MP3_R_MASK (0x1 << 14)
1820 #define RT5639_M_MP3_R_SFT 14
1821 #define RT5639_M_MP3_MASK (0x1 << 13)
1822 #define RT5639_M_MP3_SFT 13
1823 #define RT5639_M_MP3_DIS (0x0 << 13)
1824 #define RT5639_M_MP3_EN (0x1 << 13)
1825 #define RT5639_EG_MP3_MASK (0x1f << 8)
1826 #define RT5639_EG_MP3_SFT 8
1827 #define RT5639_MP3_HLP_MASK (0x1 << 7)
1828 #define RT5639_MP3_HLP_SFT 7
1829 #define RT5639_MP3_HLP_DIS (0x0 << 7)
1830 #define RT5639_MP3_HLP_EN (0x1 << 7)
1831 #define RT5639_M_MP3_ORG_L_MASK (0x1 << 6)
1832 #define RT5639_M_MP3_ORG_L_SFT 6
1833 #define RT5639_M_MP3_ORG_R_MASK (0x1 << 5)
1834 #define RT5639_M_MP3_ORG_R_SFT 5
1836 /* MP3 Plus Control 2 (0xd1) */
1837 #define RT5639_MP3_WT_MASK (0x1 << 13)
1838 #define RT5639_MP3_WT_SFT 13
1839 #define RT5639_MP3_WT_1_4 (0x0 << 13)
1840 #define RT5639_MP3_WT_1_2 (0x1 << 13)
1841 #define RT5639_OG_MP3_MASK (0x1f << 8)
1842 #define RT5639_OG_MP3_SFT 8
1843 #define RT5639_HG_MP3_MASK (0x3f)
1844 #define RT5639_HG_MP3_SFT 0
1846 /* 3D HP Control 1 (0xd2) */
1847 #define RT5639_3D_CF_MASK (0x1 << 15)
1848 #define RT5639_3D_CF_SFT 15
1849 #define RT5639_3D_CF_DIS (0x0 << 15)
1850 #define RT5639_3D_CF_EN (0x1 << 15)
1851 #define RT5639_3D_HP_MASK (0x1 << 14)
1852 #define RT5639_3D_HP_SFT 14
1853 #define RT5639_3D_HP_DIS (0x0 << 14)
1854 #define RT5639_3D_HP_EN (0x1 << 14)
1855 #define RT5639_3D_BT_MASK (0x1 << 13)
1856 #define RT5639_3D_BT_SFT 13
1857 #define RT5639_3D_BT_DIS (0x0 << 13)
1858 #define RT5639_3D_BT_EN (0x1 << 13)
1859 #define RT5639_3D_1F_MIX_MASK (0x3 << 11)
1860 #define RT5639_3D_1F_MIX_SFT 11
1861 #define RT5639_3D_HP_M_MASK (0x1 << 10)
1862 #define RT5639_3D_HP_M_SFT 10
1863 #define RT5639_3D_HP_M_SUR (0x0 << 10)
1864 #define RT5639_3D_HP_M_FRO (0x1 << 10)
1865 #define RT5639_M_3D_HRTF_MASK (0x1 << 9)
1866 #define RT5639_M_3D_HRTF_SFT 9
1867 #define RT5639_M_3D_D2H_MASK (0x1 << 8)
1868 #define RT5639_M_3D_D2H_SFT 8
1869 #define RT5639_M_3D_D2R_MASK (0x1 << 7)
1870 #define RT5639_M_3D_D2R_SFT 7
1871 #define RT5639_M_3D_REVB_MASK (0x1 << 6)
1872 #define RT5639_M_3D_REVB_SFT 6
1874 /* Adjustable high pass filter control 1 (0xd3) */
1875 #define RT5639_2ND_HPF_MASK (0x1 << 15)
1876 #define RT5639_2ND_HPF_SFT 15
1877 #define RT5639_2ND_HPF_DIS (0x0 << 15)
1878 #define RT5639_2ND_HPF_EN (0x1 << 15)
1879 #define RT5639_HPF_CF_L_MASK (0x7 << 12)
1880 #define RT5639_HPF_CF_L_SFT 12
1881 #define RT5639_1ST_HPF_MASK (0x1 << 11)
1882 #define RT5639_1ST_HPF_SFT 11
1883 #define RT5639_1ST_HPF_DIS (0x0 << 11)
1884 #define RT5639_1ST_HPF_EN (0x1 << 11)
1885 #define RT5639_HPF_CF_R_MASK (0x7 << 8)
1886 #define RT5639_HPF_CF_R_SFT 8
1887 #define RT5639_ZD_T_MASK (0x3 << 6)
1888 #define RT5639_ZD_T_SFT 6
1889 #define RT5639_ZD_F_MASK (0x3 << 4)
1890 #define RT5639_ZD_F_SFT 4
1891 #define RT5639_ZD_F_IM (0x0 << 4)
1892 #define RT5639_ZD_F_ZC_IM (0x1 << 4)
1893 #define RT5639_ZD_F_ZC_IOD (0x2 << 4)
1894 #define RT5639_ZD_F_UN (0x3 << 4)
1896 /* HP calibration control and Amp detection (0xd6) */
1897 #define RT5639_SI_DAC_MASK (0x1 << 11)
1898 #define RT5639_SI_DAC_SFT 11
1899 #define RT5639_SI_DAC_AUTO (0x0 << 11)
1900 #define RT5639_SI_DAC_TEST (0x1 << 11)
1901 #define RT5639_DC_CAL_M_MASK (0x1 << 10)
1902 #define RT5639_DC_CAL_M_SFT 10
1903 #define RT5639_DC_CAL_M_CAL (0x0 << 10)
1904 #define RT5639_DC_CAL_M_NOR (0x1 << 10)
1905 #define RT5639_DC_CAL_MASK (0x1 << 9)
1906 #define RT5639_DC_CAL_SFT 9
1907 #define RT5639_DC_CAL_DIS (0x0 << 9)
1908 #define RT5639_DC_CAL_EN (0x1 << 9)
1909 #define RT5639_HPD_RCV_MASK (0x7 << 6)
1910 #define RT5639_HPD_RCV_SFT 6
1911 #define RT5639_HPD_PS_MASK (0x1 << 5)
1912 #define RT5639_HPD_PS_SFT 5
1913 #define RT5639_HPD_PS_DIS (0x0 << 5)
1914 #define RT5639_HPD_PS_EN (0x1 << 5)
1915 #define RT5639_CAL_M_MASK (0x1 << 4)
1916 #define RT5639_CAL_M_SFT 4
1917 #define RT5639_CAL_M_DEP (0x0 << 4)
1918 #define RT5639_CAL_M_CAL (0x1 << 4)
1919 #define RT5639_CAL_MASK (0x1 << 3)
1920 #define RT5639_CAL_SFT 3
1921 #define RT5639_CAL_DIS (0x0 << 3)
1922 #define RT5639_CAL_EN (0x1 << 3)
1923 #define RT5639_CAL_TEST_MASK (0x1 << 2)
1924 #define RT5639_CAL_TEST_SFT 2
1925 #define RT5639_CAL_TEST_DIS (0x0 << 2)
1926 #define RT5639_CAL_TEST_EN (0x1 << 2)
1927 #define RT5639_CAL_P_MASK (0x3)
1928 #define RT5639_CAL_P_SFT 0
1929 #define RT5639_CAL_P_NONE (0x0)
1930 #define RT5639_CAL_P_CAL (0x1)
1931 #define RT5639_CAL_P_DAC_CAL (0x2)
1933 /* Soft volume and zero cross control 1 (0xd9) */
1934 #define RT5639_SV_MASK (0x1 << 15)
1935 #define RT5639_SV_SFT 15
1936 #define RT5639_SV_DIS (0x0 << 15)
1937 #define RT5639_SV_EN (0x1 << 15)
1938 #define RT5639_SPO_SV_MASK (0x1 << 14)
1939 #define RT5639_SPO_SV_SFT 14
1940 #define RT5639_SPO_SV_DIS (0x0 << 14)
1941 #define RT5639_SPO_SV_EN (0x1 << 14)
1942 #define RT5639_OUT_SV_MASK (0x1 << 13)
1943 #define RT5639_OUT_SV_SFT 13
1944 #define RT5639_OUT_SV_DIS (0x0 << 13)
1945 #define RT5639_OUT_SV_EN (0x1 << 13)
1946 #define RT5639_HP_SV_MASK (0x1 << 12)
1947 #define RT5639_HP_SV_SFT 12
1948 #define RT5639_HP_SV_DIS (0x0 << 12)
1949 #define RT5639_HP_SV_EN (0x1 << 12)
1950 #define RT5639_ZCD_DIG_MASK (0x1 << 11)
1951 #define RT5639_ZCD_DIG_SFT 11
1952 #define RT5639_ZCD_DIG_DIS (0x0 << 11)
1953 #define RT5639_ZCD_DIG_EN (0x1 << 11)
1954 #define RT5639_ZCD_MASK (0x1 << 10)
1955 #define RT5639_ZCD_SFT 10
1956 #define RT5639_ZCD_PD (0x0 << 10)
1957 #define RT5639_ZCD_PU (0x1 << 10)
1958 #define RT5639_M_ZCD_MASK (0x3f << 4)
1959 #define RT5639_M_ZCD_SFT 4
1960 #define RT5639_M_ZCD_RM_L (0x1 << 9)
1961 #define RT5639_M_ZCD_RM_R (0x1 << 8)
1962 #define RT5639_M_ZCD_SM_L (0x1 << 7)
1963 #define RT5639_M_ZCD_SM_R (0x1 << 6)
1964 #define RT5639_M_ZCD_OM_L (0x1 << 5)
1965 #define RT5639_M_ZCD_OM_R (0x1 << 4)
1966 #define RT5639_SV_DLY_MASK (0xf)
1967 #define RT5639_SV_DLY_SFT 0
1969 /* Soft volume and zero cross control 2 (0xda) */
1970 #define RT5639_ZCD_HP_MASK (0x1 << 15)
1971 #define RT5639_ZCD_HP_SFT 15
1972 #define RT5639_ZCD_HP_DIS (0x0 << 15)
1973 #define RT5639_ZCD_HP_EN (0x1 << 15)
1976 /* Codec Private Register definition */
1977 /* 3D Speaker Control (0x63) */
1978 #define RT5639_3D_SPK_MASK (0x1 << 15)
1979 #define RT5639_3D_SPK_SFT 15
1980 #define RT5639_3D_SPK_DIS (0x0 << 15)
1981 #define RT5639_3D_SPK_EN (0x1 << 15)
1982 #define RT5639_3D_SPK_M_MASK (0x3 << 13)
1983 #define RT5639_3D_SPK_M_SFT 13
1984 #define RT5639_3D_SPK_CG_MASK (0x1f << 8)
1985 #define RT5639_3D_SPK_CG_SFT 8
1986 #define RT5639_3D_SPK_SG_MASK (0x1f)
1987 #define RT5639_3D_SPK_SG_SFT 0
1989 /* Wind Noise Detection Control 1 (0x6c) */
1990 #define RT5639_WND_MASK (0x1 << 15)
1991 #define RT5639_WND_SFT 15
1992 #define RT5639_WND_DIS (0x0 << 15)
1993 #define RT5639_WND_EN (0x1 << 15)
1995 /* Wind Noise Detection Control 2 (0x6d) */
1996 #define RT5639_WND_FC_NW_MASK (0x3f << 10)
1997 #define RT5639_WND_FC_NW_SFT 10
1998 #define RT5639_WND_FC_WK_MASK (0x3f << 4)
1999 #define RT5639_WND_FC_WK_SFT 4
2001 /* Wind Noise Detection Control 3 (0x6e) */
2002 #define RT5639_HPF_FC_MASK (0x3f << 6)
2003 #define RT5639_HPF_FC_SFT 6
2004 #define RT5639_WND_FC_ST_MASK (0x3f)
2005 #define RT5639_WND_FC_ST_SFT 0
2007 /* Wind Noise Detection Control 4 (0x6f) */
2008 #define RT5639_WND_TH_LO_MASK (0x3ff)
2009 #define RT5639_WND_TH_LO_SFT 0
2011 /* Wind Noise Detection Control 5 (0x70) */
2012 #define RT5639_WND_TH_HI_MASK (0x3ff)
2013 #define RT5639_WND_TH_HI_SFT 0
2015 /* Wind Noise Detection Control 8 (0x73) */
2016 #define RT5639_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2017 #define RT5639_WND_WIND_SFT 13
2018 #define RT5639_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2019 #define RT5639_WND_STRONG_SFT 12
2026 /* Dipole Speaker Interface (0x75) */
2027 #define RT5639_DP_ATT_MASK (0x3 << 14)
2028 #define RT5639_DP_ATT_SFT 14
2029 #define RT5639_DP_SPK_MASK (0x1 << 10)
2030 #define RT5639_DP_SPK_SFT 10
2031 #define RT5639_DP_SPK_DIS (0x0 << 10)
2032 #define RT5639_DP_SPK_EN (0x1 << 10)
2034 /* EQ Pre Volume Control (0xb3) */
2035 #define RT5639_EQ_PRE_VOL_MASK (0xffff)
2036 #define RT5639_EQ_PRE_VOL_SFT 0
2038 /* EQ Post Volume Control (0xb4) */
2039 #define RT5639_EQ_PST_VOL_MASK (0xffff)
2040 #define RT5639_EQ_PST_VOL_SFT 0
2042 /* General Control1 (0xfa) */
2043 #define RT5639_M_MAMIX_L (0x1 << 13)
2044 #define RT5639_M_MAMIX_R (0x1 << 12)
2046 /* General Control2 (0xfb) */
2047 #define RT5639_RXDC_SRC_MASK (0x1 << 7)
2048 #define RT5639_RXDC_SRC_STO (0x0 << 7)
2049 #define RT5639_RXDC_SRC_MONO (0x1 << 7)
2050 #define RT5639_RXDC_SRC_SFT (7)
2051 #define RT5639_RXDP2_SEL_MASK (0x1 << 3)
2052 #define RT5639_RXDP2_SEL_IF2 (0x0 << 3)
2053 #define RT5639_RXDP2_SEL_ADC (0x1 << 3)
2054 #define RT5639_RXDP2_SEL_SFT (3)
2057 /* Vendor ID (0xfd) */
2058 #define RT5639_VER_C 0x2
2059 #define RT5639_VER_D 0x3
2062 /* Volume Rescale */
2063 #define RT5639_VOL_RSCL_MAX 0x27
2064 #define RT5639_VOL_RSCL_RANGE 0x1F
2065 /* Debug String Length */
2066 #define RT5639_REG_DISP_LEN 23
2068 #define RT5639_NO_JACK BIT(0)
2069 #define RT5639_HEADSET_DET BIT(1)
2070 #define RT5639_HEADPHO_DET BIT(2)
2072 int rt5639_headset_detect(struct snd_soc_codec *codec, int jack_insert);
2074 /* System Clock Source */
2078 RT5639_SCLK_S_RCCLK,
2084 RT5639_PLL1_S_BCLK1,
2085 RT5639_PLL1_S_BCLK2,
2086 RT5639_PLL1_S_BCLK3,
2096 #define RT5639_U_IF1 (0x1)
2097 #define RT5639_U_IF2 (0x1 << 1)
2098 #define RT5639_U_IF3 (0x1 << 2)
2118 struct rt5639_pll_code {
2119 bool m_bp; /* Indicates bypass m code or not. */
2125 struct rt5639_priv {
2126 struct snd_soc_codec *codec;
2127 struct delayed_work patch_work;
2132 int lrck[RT5639_AIFS];
2133 int bclk[RT5639_AIFS];
2134 int master[RT5639_AIFS];
2143 int rt5639_conn_mux_path(struct snd_soc_codec *codec,
2144 char *widget_name, char *path_name);
2146 #endif /* __RT5639_H__ */