2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/of_gpio.h>
19 #include <linux/regmap.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/firmware.h>
24 #include <linux/gpio.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
35 #include "rt5677-spi.h"
37 #define RT5677_DEVICE_ID 0x6327
39 #define RT5677_PR_RANGE_BASE (0xff + 1)
40 #define RT5677_PR_SPACING 0x100
42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
44 static const struct regmap_range_cfg rt5677_ranges[] = {
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
57 static const struct reg_default init_list[] = {
58 {RT5677_ASRC_12, 0x0018},
59 {RT5677_PR_BASE + 0x3d, 0x364d},
60 {RT5677_PR_BASE + 0x17, 0x4fc0},
61 {RT5677_PR_BASE + 0x13, 0x0312},
62 {RT5677_PR_BASE + 0x1e, 0x0000},
63 {RT5677_PR_BASE + 0x12, 0x0eaa},
64 {RT5677_PR_BASE + 0x14, 0x018a},
65 {RT5677_PR_BASE + 0x15, 0x0490},
66 {RT5677_PR_BASE + 0x38, 0x0f71},
67 {RT5677_PR_BASE + 0x39, 0x0f71},
69 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
71 static const struct reg_default rt5677_reg[] = {
72 {RT5677_RESET , 0x0000},
73 {RT5677_LOUT1 , 0xa800},
74 {RT5677_IN1 , 0x0000},
75 {RT5677_MICBIAS , 0x0000},
76 {RT5677_SLIMBUS_PARAM , 0x0000},
77 {RT5677_SLIMBUS_RX , 0x0000},
78 {RT5677_SLIMBUS_CTRL , 0x0000},
79 {RT5677_SIDETONE_CTRL , 0x000b},
80 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
81 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
82 {RT5677_DAC4_DIG_VOL , 0xafaf},
83 {RT5677_DAC3_DIG_VOL , 0xafaf},
84 {RT5677_DAC1_DIG_VOL , 0xafaf},
85 {RT5677_DAC2_DIG_VOL , 0xafaf},
86 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
87 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
89 {RT5677_STO1_2_ADC_BST , 0x0000},
90 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_ADC_BST_CTRL2 , 0x0000},
92 {RT5677_STO3_4_ADC_BST , 0x0000},
93 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
94 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
95 {RT5677_STO4_ADC_MIXER , 0xd4c0},
96 {RT5677_STO3_ADC_MIXER , 0xd4c0},
97 {RT5677_STO2_ADC_MIXER , 0xd4c0},
98 {RT5677_STO1_ADC_MIXER , 0xd4c0},
99 {RT5677_MONO_ADC_MIXER , 0xd4d1},
100 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
101 {RT5677_STO1_DAC_MIXER , 0xaaaa},
102 {RT5677_MONO_DAC_MIXER , 0xaaaa},
103 {RT5677_DD1_MIXER , 0xaaaa},
104 {RT5677_DD2_MIXER , 0xaaaa},
105 {RT5677_IF3_DATA , 0x0000},
106 {RT5677_IF4_DATA , 0x0000},
107 {RT5677_PDM_OUT_CTRL , 0x8888},
108 {RT5677_PDM_DATA_CTRL1 , 0x0000},
109 {RT5677_PDM_DATA_CTRL2 , 0x0000},
110 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
111 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
112 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
113 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
114 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
115 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
116 {RT5677_TDM1_CTRL1 , 0x0300},
117 {RT5677_TDM1_CTRL2 , 0x0000},
118 {RT5677_TDM1_CTRL3 , 0x4000},
119 {RT5677_TDM1_CTRL4 , 0x0123},
120 {RT5677_TDM1_CTRL5 , 0x4567},
121 {RT5677_TDM2_CTRL1 , 0x0300},
122 {RT5677_TDM2_CTRL2 , 0x0000},
123 {RT5677_TDM2_CTRL3 , 0x4000},
124 {RT5677_TDM2_CTRL4 , 0x0123},
125 {RT5677_TDM2_CTRL5 , 0x4567},
126 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
127 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
131 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
132 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
133 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
134 {RT5677_DMIC_CTRL1 , 0x1505},
135 {RT5677_DMIC_CTRL2 , 0x0055},
136 {RT5677_HAP_GENE_CTRL1 , 0x0111},
137 {RT5677_HAP_GENE_CTRL2 , 0x0064},
138 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
139 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
140 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
141 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
142 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
143 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
144 {RT5677_HAP_GENE_CTRL9 , 0xf000},
145 {RT5677_HAP_GENE_CTRL10 , 0x0000},
146 {RT5677_PWR_DIG1 , 0x0000},
147 {RT5677_PWR_DIG2 , 0x0000},
148 {RT5677_PWR_ANLG1 , 0x0055},
149 {RT5677_PWR_ANLG2 , 0x0000},
150 {RT5677_PWR_DSP1 , 0x0001},
151 {RT5677_PWR_DSP_ST , 0x0000},
152 {RT5677_PWR_DSP2 , 0x0000},
153 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
154 {RT5677_PRIV_INDEX , 0x0000},
155 {RT5677_PRIV_DATA , 0x0000},
156 {RT5677_I2S4_SDP , 0x8000},
157 {RT5677_I2S1_SDP , 0x8000},
158 {RT5677_I2S2_SDP , 0x8000},
159 {RT5677_I2S3_SDP , 0x8000},
160 {RT5677_CLK_TREE_CTRL1 , 0x1111},
161 {RT5677_CLK_TREE_CTRL2 , 0x1111},
162 {RT5677_CLK_TREE_CTRL3 , 0x0000},
163 {RT5677_PLL1_CTRL1 , 0x0000},
164 {RT5677_PLL1_CTRL2 , 0x0000},
165 {RT5677_PLL2_CTRL1 , 0x0c60},
166 {RT5677_PLL2_CTRL2 , 0x2000},
167 {RT5677_GLB_CLK1 , 0x0000},
168 {RT5677_GLB_CLK2 , 0x0000},
169 {RT5677_ASRC_1 , 0x0000},
170 {RT5677_ASRC_2 , 0x0000},
171 {RT5677_ASRC_3 , 0x0000},
172 {RT5677_ASRC_4 , 0x0000},
173 {RT5677_ASRC_5 , 0x0000},
174 {RT5677_ASRC_6 , 0x0000},
175 {RT5677_ASRC_7 , 0x0000},
176 {RT5677_ASRC_8 , 0x0000},
177 {RT5677_ASRC_9 , 0x0000},
178 {RT5677_ASRC_10 , 0x0000},
179 {RT5677_ASRC_11 , 0x0000},
180 {RT5677_ASRC_12 , 0x0018},
181 {RT5677_ASRC_13 , 0x0000},
182 {RT5677_ASRC_14 , 0x0000},
183 {RT5677_ASRC_15 , 0x0000},
184 {RT5677_ASRC_16 , 0x0000},
185 {RT5677_ASRC_17 , 0x0000},
186 {RT5677_ASRC_18 , 0x0000},
187 {RT5677_ASRC_19 , 0x0000},
188 {RT5677_ASRC_20 , 0x0000},
189 {RT5677_ASRC_21 , 0x000c},
190 {RT5677_ASRC_22 , 0x0000},
191 {RT5677_ASRC_23 , 0x0000},
192 {RT5677_VAD_CTRL1 , 0x2184},
193 {RT5677_VAD_CTRL2 , 0x010a},
194 {RT5677_VAD_CTRL3 , 0x0aea},
195 {RT5677_VAD_CTRL4 , 0x000c},
196 {RT5677_VAD_CTRL5 , 0x0000},
197 {RT5677_DSP_INB_CTRL1 , 0x0000},
198 {RT5677_DSP_INB_CTRL2 , 0x0000},
199 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
200 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
201 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
202 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
203 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
204 {RT5677_ADC_EQ_CTRL1 , 0x6000},
205 {RT5677_ADC_EQ_CTRL2 , 0x0000},
206 {RT5677_EQ_CTRL1 , 0xc000},
207 {RT5677_EQ_CTRL2 , 0x0000},
208 {RT5677_EQ_CTRL3 , 0x0000},
209 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
210 {RT5677_JD_CTRL1 , 0x0000},
211 {RT5677_JD_CTRL2 , 0x0000},
212 {RT5677_JD_CTRL3 , 0x0000},
213 {RT5677_IRQ_CTRL1 , 0x0000},
214 {RT5677_IRQ_CTRL2 , 0x0000},
215 {RT5677_GPIO_ST , 0x0000},
216 {RT5677_GPIO_CTRL1 , 0x0000},
217 {RT5677_GPIO_CTRL2 , 0x0000},
218 {RT5677_GPIO_CTRL3 , 0x0000},
219 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
220 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
221 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
222 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
223 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
224 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
225 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
226 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
227 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
228 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
229 {RT5677_MB_DRC_CTRL1 , 0x0f20},
230 {RT5677_DRC1_CTRL1 , 0x001f},
231 {RT5677_DRC1_CTRL2 , 0x020c},
232 {RT5677_DRC1_CTRL3 , 0x1f00},
233 {RT5677_DRC1_CTRL4 , 0x0000},
234 {RT5677_DRC1_CTRL5 , 0x0000},
235 {RT5677_DRC1_CTRL6 , 0x0029},
236 {RT5677_DRC2_CTRL1 , 0x001f},
237 {RT5677_DRC2_CTRL2 , 0x020c},
238 {RT5677_DRC2_CTRL3 , 0x1f00},
239 {RT5677_DRC2_CTRL4 , 0x0000},
240 {RT5677_DRC2_CTRL5 , 0x0000},
241 {RT5677_DRC2_CTRL6 , 0x0029},
242 {RT5677_DRC1_HL_CTRL1 , 0x8000},
243 {RT5677_DRC1_HL_CTRL2 , 0x0200},
244 {RT5677_DRC2_HL_CTRL1 , 0x8000},
245 {RT5677_DRC2_HL_CTRL2 , 0x0200},
246 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
247 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
248 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
249 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
250 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
251 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
252 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
253 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
254 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
255 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
256 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
257 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
258 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
259 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
260 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
261 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
262 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
263 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
264 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
265 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
266 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
267 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
268 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
269 {RT5677_DIG_MISC , 0x0000},
270 {RT5677_GEN_CTRL1 , 0x0000},
271 {RT5677_GEN_CTRL2 , 0x0000},
272 {RT5677_VENDOR_ID , 0x0000},
273 {RT5677_VENDOR_ID1 , 0x10ec},
274 {RT5677_VENDOR_ID2 , 0x6327},
277 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
281 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
282 if (reg >= rt5677_ranges[i].range_min &&
283 reg <= rt5677_ranges[i].range_max) {
290 case RT5677_SLIMBUS_PARAM:
291 case RT5677_PDM_DATA_CTRL1:
292 case RT5677_PDM_DATA_CTRL2:
293 case RT5677_PDM1_DATA_CTRL4:
294 case RT5677_PDM2_DATA_CTRL4:
295 case RT5677_I2C_MASTER_CTRL1:
296 case RT5677_I2C_MASTER_CTRL7:
297 case RT5677_I2C_MASTER_CTRL8:
298 case RT5677_HAP_GENE_CTRL2:
299 case RT5677_PWR_DSP_ST:
300 case RT5677_PRIV_DATA:
301 case RT5677_PLL1_CTRL2:
302 case RT5677_PLL2_CTRL2:
305 case RT5677_VAD_CTRL5:
306 case RT5677_ADC_EQ_CTRL1:
307 case RT5677_EQ_CTRL1:
308 case RT5677_IRQ_CTRL1:
309 case RT5677_IRQ_CTRL2:
311 case RT5677_DSP_INB1_SRC_CTRL4:
312 case RT5677_DSP_INB2_SRC_CTRL4:
313 case RT5677_DSP_INB3_SRC_CTRL4:
314 case RT5677_DSP_OUTB1_SRC_CTRL4:
315 case RT5677_DSP_OUTB2_SRC_CTRL4:
316 case RT5677_VENDOR_ID:
317 case RT5677_VENDOR_ID1:
318 case RT5677_VENDOR_ID2:
325 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
329 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
330 if (reg >= rt5677_ranges[i].range_min &&
331 reg <= rt5677_ranges[i].range_max) {
341 case RT5677_SLIMBUS_PARAM:
342 case RT5677_SLIMBUS_RX:
343 case RT5677_SLIMBUS_CTRL:
344 case RT5677_SIDETONE_CTRL:
345 case RT5677_ANA_DAC1_2_3_SRC:
346 case RT5677_IF_DSP_DAC3_4_MIXER:
347 case RT5677_DAC4_DIG_VOL:
348 case RT5677_DAC3_DIG_VOL:
349 case RT5677_DAC1_DIG_VOL:
350 case RT5677_DAC2_DIG_VOL:
351 case RT5677_IF_DSP_DAC2_MIXER:
352 case RT5677_STO1_ADC_DIG_VOL:
353 case RT5677_MONO_ADC_DIG_VOL:
354 case RT5677_STO1_2_ADC_BST:
355 case RT5677_STO2_ADC_DIG_VOL:
356 case RT5677_ADC_BST_CTRL2:
357 case RT5677_STO3_4_ADC_BST:
358 case RT5677_STO3_ADC_DIG_VOL:
359 case RT5677_STO4_ADC_DIG_VOL:
360 case RT5677_STO4_ADC_MIXER:
361 case RT5677_STO3_ADC_MIXER:
362 case RT5677_STO2_ADC_MIXER:
363 case RT5677_STO1_ADC_MIXER:
364 case RT5677_MONO_ADC_MIXER:
365 case RT5677_ADC_IF_DSP_DAC1_MIXER:
366 case RT5677_STO1_DAC_MIXER:
367 case RT5677_MONO_DAC_MIXER:
368 case RT5677_DD1_MIXER:
369 case RT5677_DD2_MIXER:
370 case RT5677_IF3_DATA:
371 case RT5677_IF4_DATA:
372 case RT5677_PDM_OUT_CTRL:
373 case RT5677_PDM_DATA_CTRL1:
374 case RT5677_PDM_DATA_CTRL2:
375 case RT5677_PDM1_DATA_CTRL2:
376 case RT5677_PDM1_DATA_CTRL3:
377 case RT5677_PDM1_DATA_CTRL4:
378 case RT5677_PDM2_DATA_CTRL2:
379 case RT5677_PDM2_DATA_CTRL3:
380 case RT5677_PDM2_DATA_CTRL4:
381 case RT5677_TDM1_CTRL1:
382 case RT5677_TDM1_CTRL2:
383 case RT5677_TDM1_CTRL3:
384 case RT5677_TDM1_CTRL4:
385 case RT5677_TDM1_CTRL5:
386 case RT5677_TDM2_CTRL1:
387 case RT5677_TDM2_CTRL2:
388 case RT5677_TDM2_CTRL3:
389 case RT5677_TDM2_CTRL4:
390 case RT5677_TDM2_CTRL5:
391 case RT5677_I2C_MASTER_CTRL1:
392 case RT5677_I2C_MASTER_CTRL2:
393 case RT5677_I2C_MASTER_CTRL3:
394 case RT5677_I2C_MASTER_CTRL4:
395 case RT5677_I2C_MASTER_CTRL5:
396 case RT5677_I2C_MASTER_CTRL6:
397 case RT5677_I2C_MASTER_CTRL7:
398 case RT5677_I2C_MASTER_CTRL8:
399 case RT5677_DMIC_CTRL1:
400 case RT5677_DMIC_CTRL2:
401 case RT5677_HAP_GENE_CTRL1:
402 case RT5677_HAP_GENE_CTRL2:
403 case RT5677_HAP_GENE_CTRL3:
404 case RT5677_HAP_GENE_CTRL4:
405 case RT5677_HAP_GENE_CTRL5:
406 case RT5677_HAP_GENE_CTRL6:
407 case RT5677_HAP_GENE_CTRL7:
408 case RT5677_HAP_GENE_CTRL8:
409 case RT5677_HAP_GENE_CTRL9:
410 case RT5677_HAP_GENE_CTRL10:
411 case RT5677_PWR_DIG1:
412 case RT5677_PWR_DIG2:
413 case RT5677_PWR_ANLG1:
414 case RT5677_PWR_ANLG2:
415 case RT5677_PWR_DSP1:
416 case RT5677_PWR_DSP_ST:
417 case RT5677_PWR_DSP2:
418 case RT5677_ADC_DAC_HPF_CTRL1:
419 case RT5677_PRIV_INDEX:
420 case RT5677_PRIV_DATA:
421 case RT5677_I2S4_SDP:
422 case RT5677_I2S1_SDP:
423 case RT5677_I2S2_SDP:
424 case RT5677_I2S3_SDP:
425 case RT5677_CLK_TREE_CTRL1:
426 case RT5677_CLK_TREE_CTRL2:
427 case RT5677_CLK_TREE_CTRL3:
428 case RT5677_PLL1_CTRL1:
429 case RT5677_PLL1_CTRL2:
430 case RT5677_PLL2_CTRL1:
431 case RT5677_PLL2_CTRL2:
432 case RT5677_GLB_CLK1:
433 case RT5677_GLB_CLK2:
457 case RT5677_VAD_CTRL1:
458 case RT5677_VAD_CTRL2:
459 case RT5677_VAD_CTRL3:
460 case RT5677_VAD_CTRL4:
461 case RT5677_VAD_CTRL5:
462 case RT5677_DSP_INB_CTRL1:
463 case RT5677_DSP_INB_CTRL2:
464 case RT5677_DSP_IN_OUTB_CTRL:
465 case RT5677_DSP_OUTB0_1_DIG_VOL:
466 case RT5677_DSP_OUTB2_3_DIG_VOL:
467 case RT5677_DSP_OUTB4_5_DIG_VOL:
468 case RT5677_DSP_OUTB6_7_DIG_VOL:
469 case RT5677_ADC_EQ_CTRL1:
470 case RT5677_ADC_EQ_CTRL2:
471 case RT5677_EQ_CTRL1:
472 case RT5677_EQ_CTRL2:
473 case RT5677_EQ_CTRL3:
474 case RT5677_SOFT_VOL_ZERO_CROSS1:
475 case RT5677_JD_CTRL1:
476 case RT5677_JD_CTRL2:
477 case RT5677_JD_CTRL3:
478 case RT5677_IRQ_CTRL1:
479 case RT5677_IRQ_CTRL2:
481 case RT5677_GPIO_CTRL1:
482 case RT5677_GPIO_CTRL2:
483 case RT5677_GPIO_CTRL3:
484 case RT5677_STO1_ADC_HI_FILTER1:
485 case RT5677_STO1_ADC_HI_FILTER2:
486 case RT5677_MONO_ADC_HI_FILTER1:
487 case RT5677_MONO_ADC_HI_FILTER2:
488 case RT5677_STO2_ADC_HI_FILTER1:
489 case RT5677_STO2_ADC_HI_FILTER2:
490 case RT5677_STO3_ADC_HI_FILTER1:
491 case RT5677_STO3_ADC_HI_FILTER2:
492 case RT5677_STO4_ADC_HI_FILTER1:
493 case RT5677_STO4_ADC_HI_FILTER2:
494 case RT5677_MB_DRC_CTRL1:
495 case RT5677_DRC1_CTRL1:
496 case RT5677_DRC1_CTRL2:
497 case RT5677_DRC1_CTRL3:
498 case RT5677_DRC1_CTRL4:
499 case RT5677_DRC1_CTRL5:
500 case RT5677_DRC1_CTRL6:
501 case RT5677_DRC2_CTRL1:
502 case RT5677_DRC2_CTRL2:
503 case RT5677_DRC2_CTRL3:
504 case RT5677_DRC2_CTRL4:
505 case RT5677_DRC2_CTRL5:
506 case RT5677_DRC2_CTRL6:
507 case RT5677_DRC1_HL_CTRL1:
508 case RT5677_DRC1_HL_CTRL2:
509 case RT5677_DRC2_HL_CTRL1:
510 case RT5677_DRC2_HL_CTRL2:
511 case RT5677_DSP_INB1_SRC_CTRL1:
512 case RT5677_DSP_INB1_SRC_CTRL2:
513 case RT5677_DSP_INB1_SRC_CTRL3:
514 case RT5677_DSP_INB1_SRC_CTRL4:
515 case RT5677_DSP_INB2_SRC_CTRL1:
516 case RT5677_DSP_INB2_SRC_CTRL2:
517 case RT5677_DSP_INB2_SRC_CTRL3:
518 case RT5677_DSP_INB2_SRC_CTRL4:
519 case RT5677_DSP_INB3_SRC_CTRL1:
520 case RT5677_DSP_INB3_SRC_CTRL2:
521 case RT5677_DSP_INB3_SRC_CTRL3:
522 case RT5677_DSP_INB3_SRC_CTRL4:
523 case RT5677_DSP_OUTB1_SRC_CTRL1:
524 case RT5677_DSP_OUTB1_SRC_CTRL2:
525 case RT5677_DSP_OUTB1_SRC_CTRL3:
526 case RT5677_DSP_OUTB1_SRC_CTRL4:
527 case RT5677_DSP_OUTB2_SRC_CTRL1:
528 case RT5677_DSP_OUTB2_SRC_CTRL2:
529 case RT5677_DSP_OUTB2_SRC_CTRL3:
530 case RT5677_DSP_OUTB2_SRC_CTRL4:
531 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
532 case RT5677_DSP_OUTB_45_MIXER_CTRL:
533 case RT5677_DSP_OUTB_67_MIXER_CTRL:
534 case RT5677_DIG_MISC:
535 case RT5677_GEN_CTRL1:
536 case RT5677_GEN_CTRL2:
537 case RT5677_VENDOR_ID:
538 case RT5677_VENDOR_ID1:
539 case RT5677_VENDOR_ID2:
547 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
548 * @rt5677: Private Data.
549 * @addr: Address index.
550 * @value: Address data.
553 * Returns 0 for success or negative error code.
555 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
556 unsigned int addr, unsigned int value, unsigned int opcode)
558 struct snd_soc_codec *codec = rt5677->codec;
561 mutex_lock(&rt5677->dsp_cmd_lock);
563 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
566 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
570 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
573 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
577 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
580 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
584 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
587 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
591 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
594 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
599 mutex_unlock(&rt5677->dsp_cmd_lock);
605 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
606 * rt5677: Private Data.
607 * @addr: Address index.
608 * @value: Address data.
611 * Returns 0 for success or negative error code.
613 static int rt5677_dsp_mode_i2c_read_addr(
614 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
616 struct snd_soc_codec *codec = rt5677->codec;
618 unsigned int msb, lsb;
620 mutex_lock(&rt5677->dsp_cmd_lock);
622 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
625 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
629 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
632 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
636 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
639 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
643 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
644 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
645 *value = (msb << 16) | lsb;
648 mutex_unlock(&rt5677->dsp_cmd_lock);
654 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
655 * rt5677: Private Data.
656 * @reg: Register index.
657 * @value: Register data.
660 * Returns 0 for success or negative error code.
662 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
663 unsigned int reg, unsigned int value)
665 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
670 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
671 * @codec: SoC audio codec device.
672 * @reg: Register index.
673 * @value: Register data.
676 * Returns 0 for success or negative error code.
678 static int rt5677_dsp_mode_i2c_read(
679 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
681 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
689 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
691 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
695 rt5677->is_dsp_mode = true;
697 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
698 rt5677->is_dsp_mode = false;
702 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
704 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
705 static bool activity;
708 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
711 if (on && !activity) {
714 regcache_cache_only(rt5677->regmap, false);
715 regcache_cache_bypass(rt5677->regmap, true);
717 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
718 regmap_update_bits(rt5677->regmap,
719 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
720 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
721 RT5677_LDO1_SEL_MASK, 0x0);
722 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
723 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
724 switch (rt5677->type) {
726 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
727 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
728 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
729 RT5677_PLL2_PR_SRC_MASK |
730 RT5677_DSP_CLK_SRC_MASK,
731 RT5677_PLL2_PR_SRC_MCLK2 |
732 RT5677_DSP_CLK_SRC_BYPASS);
735 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
736 RT5677_DSP_CLK_SRC_MASK,
737 RT5677_DSP_CLK_SRC_BYPASS);
742 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
743 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
744 rt5677_set_dsp_mode(codec, true);
746 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
749 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
750 release_firmware(rt5677->fw1);
753 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
756 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
757 release_firmware(rt5677->fw2);
760 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
762 regcache_cache_bypass(rt5677->regmap, false);
763 regcache_cache_only(rt5677->regmap, true);
764 } else if (!on && activity) {
767 regcache_cache_only(rt5677->regmap, false);
768 regcache_cache_bypass(rt5677->regmap, true);
770 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
771 rt5677_set_dsp_mode(codec, false);
772 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
774 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
776 regcache_cache_bypass(rt5677->regmap, false);
777 regcache_mark_dirty(rt5677->regmap);
778 regcache_sync(rt5677->regmap);
784 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
785 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
786 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
787 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
788 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
789 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
791 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
792 static unsigned int bst_tlv[] = {
793 TLV_DB_RANGE_HEAD(7),
794 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
795 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
796 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
797 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
798 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
799 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
800 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
803 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
804 struct snd_ctl_elem_value *ucontrol)
806 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
807 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
809 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
814 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
815 struct snd_ctl_elem_value *ucontrol)
817 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
818 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
819 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
821 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
823 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
824 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
829 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
831 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
832 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
833 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
834 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
835 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
836 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
838 /* DAC Digital Volume */
839 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
840 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
841 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
842 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
843 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
844 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
845 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
846 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
848 /* IN1/IN2 Control */
849 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
850 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
852 /* ADC Digital Volume Control */
853 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
854 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
855 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
856 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
857 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
858 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
859 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
860 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
861 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
862 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
864 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
865 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
867 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
868 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
870 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
871 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
873 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
874 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
876 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
877 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
880 /* Sidetone Control */
881 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
882 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
884 /* ADC Boost Volume Control */
885 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
886 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
888 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
889 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
891 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
892 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
894 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
895 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
897 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
898 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
901 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
902 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
906 * set_dmic_clk - Set parameter of dmic.
909 * @kcontrol: The kcontrol of this widget.
912 * Choose dmic clock between 1MHz and 3MHz.
913 * It is better for clock to approximate 3MHz.
915 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
916 struct snd_kcontrol *kcontrol, int event)
918 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
919 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
920 int idx = rl6231_calc_dmic_clk(rt5677->lrck[RT5677_AIF1] << 8);
923 dev_err(codec->dev, "Failed to set DMIC clock\n");
925 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
926 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
930 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
931 struct snd_soc_dapm_widget *sink)
933 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
934 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
937 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
938 val &= RT5677_SCLK_SRC_MASK;
939 if (val == RT5677_SCLK_SRC_PLL1)
945 static int is_using_asrc(struct snd_soc_dapm_widget *source,
946 struct snd_soc_dapm_widget *sink)
948 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
949 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
950 unsigned int reg, shift, val;
952 if (source->reg == RT5677_ASRC_1) {
953 switch (source->shift) {
974 switch (source->shift) {
1000 reg = RT5677_ASRC_3;
1004 reg = RT5677_ASRC_3;
1008 reg = RT5677_ASRC_3;
1016 regmap_read(rt5677->regmap, reg, &val);
1017 val = (val >> shift) & 0xf;
1028 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1029 struct snd_soc_dapm_widget *sink)
1031 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1032 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1034 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1041 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1042 * @codec: SoC audio codec device.
1043 * @filter_mask: mask of filters.
1044 * @clk_src: clock source
1046 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1047 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1048 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1049 * ASRC function will track i2s clock and generate a corresponding system clock
1050 * for codec. This function provides an API to select the clock source for a
1051 * set of filters specified by the mask. And the codec driver will turn on ASRC
1052 * for these filters if ASRC is selected as their clock source.
1054 int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1055 unsigned int filter_mask, unsigned int clk_src)
1057 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1058 unsigned int asrc3_mask = 0, asrc3_value = 0;
1059 unsigned int asrc4_mask = 0, asrc4_value = 0;
1060 unsigned int asrc5_mask = 0, asrc5_value = 0;
1061 unsigned int asrc6_mask = 0, asrc6_value = 0;
1062 unsigned int asrc7_mask = 0, asrc7_value = 0;
1063 unsigned int asrc8_mask = 0, asrc8_value = 0;
1066 case RT5677_CLK_SEL_SYS:
1067 case RT5677_CLK_SEL_I2S1_ASRC:
1068 case RT5677_CLK_SEL_I2S2_ASRC:
1069 case RT5677_CLK_SEL_I2S3_ASRC:
1070 case RT5677_CLK_SEL_I2S4_ASRC:
1071 case RT5677_CLK_SEL_I2S5_ASRC:
1072 case RT5677_CLK_SEL_I2S6_ASRC:
1073 case RT5677_CLK_SEL_SYS2:
1074 case RT5677_CLK_SEL_SYS3:
1075 case RT5677_CLK_SEL_SYS4:
1076 case RT5677_CLK_SEL_SYS5:
1077 case RT5677_CLK_SEL_SYS6:
1078 case RT5677_CLK_SEL_SYS7:
1086 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1087 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1088 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1089 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1092 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1093 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1094 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1095 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1098 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1099 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1100 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1101 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1105 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1109 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1110 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1111 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1112 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1115 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1116 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1117 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1118 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1121 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1122 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1123 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1124 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1127 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1128 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1129 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1130 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1134 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1138 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1139 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1140 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1141 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1144 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1145 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1146 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1147 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1150 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1151 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1152 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1153 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1156 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1157 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1158 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1159 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1163 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1167 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1168 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1169 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1170 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1173 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1174 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1175 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1176 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1180 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1184 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1185 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1186 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1187 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1190 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1191 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1192 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1193 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1197 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1201 if (filter_mask & RT5677_I2S1_SOURCE) {
1202 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1203 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1204 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1207 if (filter_mask & RT5677_I2S2_SOURCE) {
1208 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1209 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1210 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1213 if (filter_mask & RT5677_I2S3_SOURCE) {
1214 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1215 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1216 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1219 if (filter_mask & RT5677_I2S4_SOURCE) {
1220 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1221 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1222 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1226 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1231 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1233 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1234 struct snd_soc_dapm_widget *sink)
1236 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1237 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1238 unsigned int asrc_setting;
1240 switch (source->shift) {
1242 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1243 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1244 RT5677_AD_STO1_CLK_SEL_SFT;
1245 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1246 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1251 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1252 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1253 RT5677_AD_STO2_CLK_SEL_SFT;
1254 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1255 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1260 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1261 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1262 RT5677_AD_STO3_CLK_SEL_SFT;
1263 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1264 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1269 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1270 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1271 RT5677_AD_STO4_CLK_SEL_SFT;
1272 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1273 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1278 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1279 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1280 RT5677_AD_MONOL_CLK_SEL_SFT;
1281 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1282 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1287 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1288 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1289 RT5677_AD_MONOR_CLK_SEL_SFT;
1290 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1291 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1303 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1304 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1305 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1306 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1307 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1310 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1311 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1312 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1313 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1314 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1317 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1318 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1319 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1320 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1321 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1324 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1325 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1326 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1327 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1328 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1331 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1332 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1333 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1334 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1335 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1338 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1339 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1340 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1341 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1342 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1345 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1346 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1347 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1348 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1349 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1352 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1353 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1354 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1355 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1356 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1359 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1360 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1361 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1362 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1363 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1366 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1367 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1368 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1369 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1370 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1373 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1374 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1375 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1376 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1377 RT5677_M_DAC1_L_SFT, 1, 1),
1380 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1381 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1382 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1383 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1384 RT5677_M_DAC1_R_SFT, 1, 1),
1387 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1388 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1389 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1390 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1391 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1392 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1393 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1394 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1395 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1398 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1399 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1400 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1401 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1402 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1403 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1404 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1405 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1406 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1409 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1410 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1411 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1412 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1413 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1414 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1415 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1416 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1417 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1420 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1421 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1422 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1423 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1424 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1425 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1426 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1427 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1428 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1431 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1432 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1433 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1434 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1435 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1436 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1437 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1438 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1439 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1442 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1443 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1444 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1445 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1446 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1447 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1448 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1449 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1450 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1453 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1454 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1455 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1456 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1457 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1458 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1459 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1460 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1461 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1464 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1465 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1466 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1467 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1468 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1469 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1470 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1471 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1472 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1475 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1476 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1477 RT5677_DSP_IB_01_H_SFT, 1, 1),
1478 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1479 RT5677_DSP_IB_23_H_SFT, 1, 1),
1480 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1481 RT5677_DSP_IB_45_H_SFT, 1, 1),
1482 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1483 RT5677_DSP_IB_6_H_SFT, 1, 1),
1484 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1485 RT5677_DSP_IB_7_H_SFT, 1, 1),
1486 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1487 RT5677_DSP_IB_8_H_SFT, 1, 1),
1488 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1489 RT5677_DSP_IB_9_H_SFT, 1, 1),
1492 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1493 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1494 RT5677_DSP_IB_01_L_SFT, 1, 1),
1495 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1496 RT5677_DSP_IB_23_L_SFT, 1, 1),
1497 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1498 RT5677_DSP_IB_45_L_SFT, 1, 1),
1499 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1500 RT5677_DSP_IB_6_L_SFT, 1, 1),
1501 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1502 RT5677_DSP_IB_7_L_SFT, 1, 1),
1503 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1504 RT5677_DSP_IB_8_L_SFT, 1, 1),
1505 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1506 RT5677_DSP_IB_9_L_SFT, 1, 1),
1509 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1510 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1511 RT5677_DSP_IB_01_H_SFT, 1, 1),
1512 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1513 RT5677_DSP_IB_23_H_SFT, 1, 1),
1514 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1515 RT5677_DSP_IB_45_H_SFT, 1, 1),
1516 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1517 RT5677_DSP_IB_6_H_SFT, 1, 1),
1518 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1519 RT5677_DSP_IB_7_H_SFT, 1, 1),
1520 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1521 RT5677_DSP_IB_8_H_SFT, 1, 1),
1522 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1523 RT5677_DSP_IB_9_H_SFT, 1, 1),
1526 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1527 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1528 RT5677_DSP_IB_01_L_SFT, 1, 1),
1529 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1530 RT5677_DSP_IB_23_L_SFT, 1, 1),
1531 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1532 RT5677_DSP_IB_45_L_SFT, 1, 1),
1533 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1534 RT5677_DSP_IB_6_L_SFT, 1, 1),
1535 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1536 RT5677_DSP_IB_7_L_SFT, 1, 1),
1537 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1538 RT5677_DSP_IB_8_L_SFT, 1, 1),
1539 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1540 RT5677_DSP_IB_9_L_SFT, 1, 1),
1543 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1544 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1545 RT5677_DSP_IB_01_H_SFT, 1, 1),
1546 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1547 RT5677_DSP_IB_23_H_SFT, 1, 1),
1548 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1549 RT5677_DSP_IB_45_H_SFT, 1, 1),
1550 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1551 RT5677_DSP_IB_6_H_SFT, 1, 1),
1552 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1553 RT5677_DSP_IB_7_H_SFT, 1, 1),
1554 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1555 RT5677_DSP_IB_8_H_SFT, 1, 1),
1556 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1557 RT5677_DSP_IB_9_H_SFT, 1, 1),
1560 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1561 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1562 RT5677_DSP_IB_01_L_SFT, 1, 1),
1563 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1564 RT5677_DSP_IB_23_L_SFT, 1, 1),
1565 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1566 RT5677_DSP_IB_45_L_SFT, 1, 1),
1567 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1568 RT5677_DSP_IB_6_L_SFT, 1, 1),
1569 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1570 RT5677_DSP_IB_7_L_SFT, 1, 1),
1571 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1572 RT5677_DSP_IB_8_L_SFT, 1, 1),
1573 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1574 RT5677_DSP_IB_9_L_SFT, 1, 1),
1579 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1580 static const char * const rt5677_dac1_src[] = {
1581 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1585 static SOC_ENUM_SINGLE_DECL(
1586 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1587 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1589 static const struct snd_kcontrol_new rt5677_dac1_mux =
1590 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1592 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1593 static const char * const rt5677_adda1_src[] = {
1594 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1597 static SOC_ENUM_SINGLE_DECL(
1598 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1599 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1601 static const struct snd_kcontrol_new rt5677_adda1_mux =
1602 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1605 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1606 static const char * const rt5677_dac2l_src[] = {
1607 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1611 static SOC_ENUM_SINGLE_DECL(
1612 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1613 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1615 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1616 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1618 static const char * const rt5677_dac2r_src[] = {
1619 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1620 "OB 3", "Haptic Generator", "VAD ADC"
1623 static SOC_ENUM_SINGLE_DECL(
1624 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1625 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1627 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1628 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1630 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1631 static const char * const rt5677_dac3l_src[] = {
1632 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1636 static SOC_ENUM_SINGLE_DECL(
1637 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1638 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1640 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1641 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1643 static const char * const rt5677_dac3r_src[] = {
1644 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1648 static SOC_ENUM_SINGLE_DECL(
1649 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1650 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1652 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1653 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1655 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1656 static const char * const rt5677_dac4l_src[] = {
1657 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1661 static SOC_ENUM_SINGLE_DECL(
1662 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1663 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1665 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1666 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1668 static const char * const rt5677_dac4r_src[] = {
1669 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1673 static SOC_ENUM_SINGLE_DECL(
1674 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1675 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1677 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1678 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1680 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1681 static const char * const rt5677_iob_bypass_src[] = {
1682 "Bypass", "Pass SRC"
1685 static SOC_ENUM_SINGLE_DECL(
1686 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1687 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1689 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1690 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1692 static SOC_ENUM_SINGLE_DECL(
1693 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1694 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1696 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1697 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1699 static SOC_ENUM_SINGLE_DECL(
1700 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1701 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1703 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1704 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1706 static SOC_ENUM_SINGLE_DECL(
1707 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1708 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1710 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1711 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1713 static SOC_ENUM_SINGLE_DECL(
1714 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1715 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1717 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1718 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1720 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1721 static const char * const rt5677_stereo_adc2_src[] = {
1722 "DD MIX1", "DMIC", "Stereo DAC MIX"
1725 static SOC_ENUM_SINGLE_DECL(
1726 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1727 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1729 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1730 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1732 static SOC_ENUM_SINGLE_DECL(
1733 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1734 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1736 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1737 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1739 static SOC_ENUM_SINGLE_DECL(
1740 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1741 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1743 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1744 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1746 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1747 static const char * const rt5677_dmic_src[] = {
1748 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1751 static SOC_ENUM_SINGLE_DECL(
1752 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1753 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1755 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1756 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1758 static SOC_ENUM_SINGLE_DECL(
1759 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1760 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1762 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1763 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1765 static SOC_ENUM_SINGLE_DECL(
1766 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1767 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1769 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1770 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1772 static SOC_ENUM_SINGLE_DECL(
1773 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1774 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1776 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1777 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1779 static SOC_ENUM_SINGLE_DECL(
1780 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1781 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1783 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1784 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1786 static SOC_ENUM_SINGLE_DECL(
1787 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1788 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1790 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1791 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1793 /* Stereo2 ADC Source */ /* MX-26 [0] */
1794 static const char * const rt5677_stereo2_adc_lr_src[] = {
1798 static SOC_ENUM_SINGLE_DECL(
1799 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1800 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1802 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1803 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1805 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1806 static const char * const rt5677_stereo_adc1_src[] = {
1807 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1810 static SOC_ENUM_SINGLE_DECL(
1811 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1812 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1814 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1815 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1817 static SOC_ENUM_SINGLE_DECL(
1818 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1819 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1821 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1822 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1824 static SOC_ENUM_SINGLE_DECL(
1825 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1826 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1828 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1829 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1831 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1832 static const char * const rt5677_mono_adc2_l_src[] = {
1833 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1836 static SOC_ENUM_SINGLE_DECL(
1837 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1838 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1840 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1841 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1843 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1844 static const char * const rt5677_mono_adc1_l_src[] = {
1845 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1848 static SOC_ENUM_SINGLE_DECL(
1849 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1850 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1852 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1853 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1855 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1856 static const char * const rt5677_mono_adc2_r_src[] = {
1857 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1860 static SOC_ENUM_SINGLE_DECL(
1861 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1862 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1864 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1865 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1867 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1868 static const char * const rt5677_mono_adc1_r_src[] = {
1869 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1872 static SOC_ENUM_SINGLE_DECL(
1873 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1874 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1876 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1877 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1879 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1880 static const char * const rt5677_stereo4_adc2_src[] = {
1881 "DD MIX1", "DMIC", "DD MIX2"
1884 static SOC_ENUM_SINGLE_DECL(
1885 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1886 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1888 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1889 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1892 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1893 static const char * const rt5677_stereo4_adc1_src[] = {
1894 "DD MIX1", "ADC1/2", "DD MIX2"
1897 static SOC_ENUM_SINGLE_DECL(
1898 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1899 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1901 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1902 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1904 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1905 static const char * const rt5677_inbound01_src[] = {
1906 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1910 static SOC_ENUM_SINGLE_DECL(
1911 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1912 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1914 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1915 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1917 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1918 static const char * const rt5677_inbound23_src[] = {
1919 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1920 "DAC1 FS", "IF4 DAC"
1923 static SOC_ENUM_SINGLE_DECL(
1924 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1925 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1927 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1928 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1930 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1931 static const char * const rt5677_inbound45_src[] = {
1932 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1936 static SOC_ENUM_SINGLE_DECL(
1937 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1938 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1940 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1941 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1943 /* InBound6 Source */ /* MX-A3 [2:0] */
1944 static const char * const rt5677_inbound6_src[] = {
1945 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1946 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1949 static SOC_ENUM_SINGLE_DECL(
1950 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1951 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1953 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1954 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1956 /* InBound7 Source */ /* MX-A4 [14:12] */
1957 static const char * const rt5677_inbound7_src[] = {
1958 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1959 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1962 static SOC_ENUM_SINGLE_DECL(
1963 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1964 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1966 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1967 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1969 /* InBound8 Source */ /* MX-A4 [10:8] */
1970 static const char * const rt5677_inbound8_src[] = {
1971 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1972 "MONO ADC MIX L", "DACL1 FS"
1975 static SOC_ENUM_SINGLE_DECL(
1976 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1977 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1979 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1980 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1982 /* InBound9 Source */ /* MX-A4 [6:4] */
1983 static const char * const rt5677_inbound9_src[] = {
1984 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1985 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1988 static SOC_ENUM_SINGLE_DECL(
1989 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1990 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1992 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1993 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1995 /* VAD Source */ /* MX-9F [6:4] */
1996 static const char * const rt5677_vad_src[] = {
1997 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
2001 static SOC_ENUM_SINGLE_DECL(
2002 rt5677_vad_enum, RT5677_VAD_CTRL4,
2003 RT5677_VAD_SRC_SFT, rt5677_vad_src);
2005 static const struct snd_kcontrol_new rt5677_vad_src_mux =
2006 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
2008 /* Sidetone Source */ /* MX-13 [11:9] */
2009 static const char * const rt5677_sidetone_src[] = {
2010 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
2013 static SOC_ENUM_SINGLE_DECL(
2014 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2015 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2017 static const struct snd_kcontrol_new rt5677_sidetone_mux =
2018 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2020 /* DAC1/2 Source */ /* MX-15 [1:0] */
2021 static const char * const rt5677_dac12_src[] = {
2022 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2025 static SOC_ENUM_SINGLE_DECL(
2026 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2027 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2029 static const struct snd_kcontrol_new rt5677_dac12_mux =
2030 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2032 /* DAC3 Source */ /* MX-15 [5:4] */
2033 static const char * const rt5677_dac3_src[] = {
2034 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2037 static SOC_ENUM_SINGLE_DECL(
2038 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2039 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2041 static const struct snd_kcontrol_new rt5677_dac3_mux =
2042 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2044 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2045 static const char * const rt5677_pdm_src[] = {
2046 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2049 static SOC_ENUM_SINGLE_DECL(
2050 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2051 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2053 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
2054 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
2056 static SOC_ENUM_SINGLE_DECL(
2057 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2058 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2060 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
2061 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
2063 static SOC_ENUM_SINGLE_DECL(
2064 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2065 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2067 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
2068 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
2070 static SOC_ENUM_SINGLE_DECL(
2071 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2072 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2074 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
2075 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
2077 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2078 static const char * const rt5677_if12_adc1_src[] = {
2079 "STO1 ADC MIX", "OB01", "VAD ADC"
2082 static SOC_ENUM_SINGLE_DECL(
2083 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2084 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2086 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
2087 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
2089 static SOC_ENUM_SINGLE_DECL(
2090 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2091 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2093 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
2094 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
2096 static SOC_ENUM_SINGLE_DECL(
2097 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2098 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2100 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2101 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2103 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2104 static const char * const rt5677_if12_adc2_src[] = {
2105 "STO2 ADC MIX", "OB23"
2108 static SOC_ENUM_SINGLE_DECL(
2109 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2110 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2112 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2113 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2115 static SOC_ENUM_SINGLE_DECL(
2116 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2117 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2119 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2120 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2122 static SOC_ENUM_SINGLE_DECL(
2123 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2124 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2126 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2127 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2129 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2130 static const char * const rt5677_if12_adc3_src[] = {
2131 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2134 static SOC_ENUM_SINGLE_DECL(
2135 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2136 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2138 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2139 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2141 static SOC_ENUM_SINGLE_DECL(
2142 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2143 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2145 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2146 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2148 static SOC_ENUM_SINGLE_DECL(
2149 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2150 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2152 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2153 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2155 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2156 static const char * const rt5677_if12_adc4_src[] = {
2157 "STO4 ADC MIX", "OB67", "OB01"
2160 static SOC_ENUM_SINGLE_DECL(
2161 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2162 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2164 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2165 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2167 static SOC_ENUM_SINGLE_DECL(
2168 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2169 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2171 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2172 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2174 static SOC_ENUM_SINGLE_DECL(
2175 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2176 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2178 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2179 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2181 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2182 static const char * const rt5677_if34_adc_src[] = {
2183 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2184 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2187 static SOC_ENUM_SINGLE_DECL(
2188 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2189 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2191 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2192 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2194 static SOC_ENUM_SINGLE_DECL(
2195 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2196 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2198 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2199 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2201 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2202 static const char * const rt5677_if12_adc_swap_src[] = {
2203 "L/R", "R/L", "L/L", "R/R"
2206 static SOC_ENUM_SINGLE_DECL(
2207 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2208 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2210 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2211 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2213 static SOC_ENUM_SINGLE_DECL(
2214 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2215 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2217 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2218 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2220 static SOC_ENUM_SINGLE_DECL(
2221 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2222 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2224 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2225 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2227 static SOC_ENUM_SINGLE_DECL(
2228 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2229 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2231 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2232 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2234 static SOC_ENUM_SINGLE_DECL(
2235 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2236 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2238 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2239 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2241 static SOC_ENUM_SINGLE_DECL(
2242 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2243 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2245 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2246 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2248 static SOC_ENUM_SINGLE_DECL(
2249 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2250 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2252 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2253 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2255 static SOC_ENUM_SINGLE_DECL(
2256 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2257 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2259 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2260 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2262 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2263 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2264 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2265 "3/1/2/4", "3/4/1/2"
2268 static SOC_ENUM_SINGLE_DECL(
2269 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2270 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2272 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2273 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2275 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2276 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2277 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2278 "2/3/1/4", "3/4/1/2"
2281 static SOC_ENUM_SINGLE_DECL(
2282 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2283 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2285 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2286 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2288 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2289 MX-3F[14:12][10:8][6:4][2:0]
2290 MX-43[14:12][10:8][6:4][2:0]
2291 MX-44[14:12][10:8][6:4][2:0] */
2292 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2293 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2296 static SOC_ENUM_SINGLE_DECL(
2297 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2298 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2300 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2301 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2303 static SOC_ENUM_SINGLE_DECL(
2304 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2305 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2307 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2308 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2310 static SOC_ENUM_SINGLE_DECL(
2311 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2312 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2314 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2315 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2317 static SOC_ENUM_SINGLE_DECL(
2318 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2319 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2321 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2322 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2324 static SOC_ENUM_SINGLE_DECL(
2325 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2326 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2328 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2329 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2331 static SOC_ENUM_SINGLE_DECL(
2332 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2333 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2335 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2336 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2338 static SOC_ENUM_SINGLE_DECL(
2339 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2340 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2342 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2343 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2345 static SOC_ENUM_SINGLE_DECL(
2346 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2347 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2349 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2350 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2352 static SOC_ENUM_SINGLE_DECL(
2353 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2354 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2356 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2357 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2359 static SOC_ENUM_SINGLE_DECL(
2360 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2361 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2363 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2364 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2366 static SOC_ENUM_SINGLE_DECL(
2367 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2368 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2370 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2371 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2373 static SOC_ENUM_SINGLE_DECL(
2374 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2375 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2377 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2378 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2380 static SOC_ENUM_SINGLE_DECL(
2381 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2382 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2384 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2385 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2387 static SOC_ENUM_SINGLE_DECL(
2388 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2389 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2391 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2392 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2394 static SOC_ENUM_SINGLE_DECL(
2395 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2396 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2398 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2399 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2401 static SOC_ENUM_SINGLE_DECL(
2402 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2403 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2405 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2406 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2408 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2409 struct snd_kcontrol *kcontrol, int event)
2411 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2412 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2415 case SND_SOC_DAPM_POST_PMU:
2416 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2417 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2420 case SND_SOC_DAPM_PRE_PMD:
2421 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2422 RT5677_PWR_BST1_P, 0);
2432 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2433 struct snd_kcontrol *kcontrol, int event)
2435 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2436 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2439 case SND_SOC_DAPM_POST_PMU:
2440 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2441 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2444 case SND_SOC_DAPM_PRE_PMD:
2445 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2446 RT5677_PWR_BST2_P, 0);
2456 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2457 struct snd_kcontrol *kcontrol, int event)
2459 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2460 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2463 case SND_SOC_DAPM_PRE_PMU:
2464 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2467 case SND_SOC_DAPM_POST_PMU:
2468 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2478 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2479 struct snd_kcontrol *kcontrol, int event)
2481 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2482 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2485 case SND_SOC_DAPM_PRE_PMU:
2486 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2489 case SND_SOC_DAPM_POST_PMU:
2490 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2500 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2501 struct snd_kcontrol *kcontrol, int event)
2503 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2504 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2507 case SND_SOC_DAPM_POST_PMU:
2508 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2509 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2510 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2511 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2514 case SND_SOC_DAPM_PRE_PMD:
2515 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2516 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2517 RT5677_PWR_CLK_MB, 0);
2527 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2528 struct snd_kcontrol *kcontrol, int event)
2530 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2531 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2535 case SND_SOC_DAPM_PRE_PMU:
2536 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2537 if (value & RT5677_IF1_ADC_CTRL_MASK)
2538 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2539 RT5677_IF1_ADC_MODE_MASK,
2540 RT5677_IF1_ADC_MODE_TDM);
2550 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2551 struct snd_kcontrol *kcontrol, int event)
2553 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2554 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2558 case SND_SOC_DAPM_PRE_PMU:
2559 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2560 if (value & RT5677_IF2_ADC_CTRL_MASK)
2561 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2562 RT5677_IF2_ADC_MODE_MASK,
2563 RT5677_IF2_ADC_MODE_TDM);
2573 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2574 struct snd_kcontrol *kcontrol, int event)
2576 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2577 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2580 case SND_SOC_DAPM_POST_PMU:
2581 if (snd_soc_codec_get_bias_level(codec) != SND_SOC_BIAS_ON &&
2582 !rt5677->is_vref_slow) {
2584 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2585 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2586 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2587 rt5677->is_vref_slow = true;
2598 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2599 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2600 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2601 SND_SOC_DAPM_POST_PMU),
2602 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2603 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2604 SND_SOC_DAPM_POST_PMU),
2607 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2608 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2609 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2610 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2611 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2612 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2614 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2616 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2618 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2620 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2622 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2624 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2626 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2628 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2630 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2632 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2634 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2636 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2637 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2638 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2639 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2640 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2642 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2647 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2648 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2649 SND_SOC_DAPM_POST_PMU),
2652 SND_SOC_DAPM_INPUT("DMIC L1"),
2653 SND_SOC_DAPM_INPUT("DMIC R1"),
2654 SND_SOC_DAPM_INPUT("DMIC L2"),
2655 SND_SOC_DAPM_INPUT("DMIC R2"),
2656 SND_SOC_DAPM_INPUT("DMIC L3"),
2657 SND_SOC_DAPM_INPUT("DMIC R3"),
2658 SND_SOC_DAPM_INPUT("DMIC L4"),
2659 SND_SOC_DAPM_INPUT("DMIC R4"),
2661 SND_SOC_DAPM_INPUT("IN1P"),
2662 SND_SOC_DAPM_INPUT("IN1N"),
2663 SND_SOC_DAPM_INPUT("IN2P"),
2664 SND_SOC_DAPM_INPUT("IN2N"),
2666 SND_SOC_DAPM_INPUT("Haptic Generator"),
2668 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2669 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2670 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2671 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2673 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2674 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2675 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2676 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2677 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2678 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2679 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2680 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2682 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2683 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2686 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2687 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2688 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2689 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2690 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2691 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2694 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2696 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2698 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2700 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2701 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2702 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2703 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2704 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2705 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2706 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2707 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2710 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2711 &rt5677_sto1_dmic_mux),
2712 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2713 &rt5677_sto1_adc1_mux),
2714 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2715 &rt5677_sto1_adc2_mux),
2716 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2717 &rt5677_sto2_dmic_mux),
2718 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2719 &rt5677_sto2_adc1_mux),
2720 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2721 &rt5677_sto2_adc2_mux),
2722 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2723 &rt5677_sto2_adc_lr_mux),
2724 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2725 &rt5677_sto3_dmic_mux),
2726 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2727 &rt5677_sto3_adc1_mux),
2728 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2729 &rt5677_sto3_adc2_mux),
2730 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2731 &rt5677_sto4_dmic_mux),
2732 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2733 &rt5677_sto4_adc1_mux),
2734 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2735 &rt5677_sto4_adc2_mux),
2736 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2737 &rt5677_mono_dmic_l_mux),
2738 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2739 &rt5677_mono_dmic_r_mux),
2740 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2741 &rt5677_mono_adc2_l_mux),
2742 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2743 &rt5677_mono_adc1_l_mux),
2744 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2745 &rt5677_mono_adc1_r_mux),
2746 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2747 &rt5677_mono_adc2_r_mux),
2750 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2751 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2752 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2753 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2754 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2755 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2756 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2757 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2758 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2759 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2760 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2761 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2762 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2763 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2764 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2765 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2766 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2767 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2768 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2769 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2770 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2771 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2772 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2773 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2774 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2775 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2776 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2777 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2778 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2779 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2780 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2781 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2784 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2785 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2786 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2787 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2788 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2789 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2791 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2792 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2793 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2794 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2795 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2796 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2797 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2798 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2802 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2803 &rt5677_ib9_src_mux),
2804 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2805 &rt5677_ib8_src_mux),
2806 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2807 &rt5677_ib7_src_mux),
2808 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2809 &rt5677_ib6_src_mux),
2810 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2811 &rt5677_ib45_src_mux),
2812 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5677_ib23_src_mux),
2814 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5677_ib01_src_mux),
2816 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2817 &rt5677_ib45_bypass_src_mux),
2818 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5677_ib23_bypass_src_mux),
2820 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5677_ib01_bypass_src_mux),
2822 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5677_ob23_bypass_src_mux),
2824 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5677_ob01_bypass_src_mux),
2827 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2828 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2830 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2831 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2832 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2833 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2834 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2835 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2837 /* Digital Interface */
2838 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2839 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2840 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2841 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2842 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2843 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2852 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2853 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2854 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2855 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2857 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2858 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2859 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2860 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2877 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2878 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2879 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2886 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2887 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2888 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2889 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2890 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2891 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2892 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2894 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2895 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2896 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2897 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2898 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2902 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2904 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2906 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2907 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2908 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2909 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2913 /* Digital Interface Select */
2914 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2915 &rt5677_if1_adc1_mux),
2916 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2917 &rt5677_if1_adc2_mux),
2918 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2919 &rt5677_if1_adc3_mux),
2920 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2921 &rt5677_if1_adc4_mux),
2922 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2923 &rt5677_if1_adc1_swap_mux),
2924 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2925 &rt5677_if1_adc2_swap_mux),
2926 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2927 &rt5677_if1_adc3_swap_mux),
2928 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2929 &rt5677_if1_adc4_swap_mux),
2930 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2931 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2932 SND_SOC_DAPM_PRE_PMU),
2933 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2934 &rt5677_if2_adc1_mux),
2935 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2936 &rt5677_if2_adc2_mux),
2937 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2938 &rt5677_if2_adc3_mux),
2939 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2940 &rt5677_if2_adc4_mux),
2941 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2942 &rt5677_if2_adc1_swap_mux),
2943 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2944 &rt5677_if2_adc2_swap_mux),
2945 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2946 &rt5677_if2_adc3_swap_mux),
2947 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2948 &rt5677_if2_adc4_swap_mux),
2949 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2950 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2951 SND_SOC_DAPM_PRE_PMU),
2952 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5677_if3_adc_mux),
2954 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5677_if4_adc_mux),
2956 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5677_slb_adc1_mux),
2958 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2959 &rt5677_slb_adc2_mux),
2960 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2961 &rt5677_slb_adc3_mux),
2962 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2963 &rt5677_slb_adc4_mux),
2965 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5677_if1_dac0_tdm_sel_mux),
2967 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5677_if1_dac1_tdm_sel_mux),
2969 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5677_if1_dac2_tdm_sel_mux),
2971 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5677_if1_dac3_tdm_sel_mux),
2973 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5677_if1_dac4_tdm_sel_mux),
2975 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2976 &rt5677_if1_dac5_tdm_sel_mux),
2977 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2978 &rt5677_if1_dac6_tdm_sel_mux),
2979 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2980 &rt5677_if1_dac7_tdm_sel_mux),
2982 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2983 &rt5677_if2_dac0_tdm_sel_mux),
2984 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2985 &rt5677_if2_dac1_tdm_sel_mux),
2986 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2987 &rt5677_if2_dac2_tdm_sel_mux),
2988 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2989 &rt5677_if2_dac3_tdm_sel_mux),
2990 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2991 &rt5677_if2_dac4_tdm_sel_mux),
2992 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2993 &rt5677_if2_dac5_tdm_sel_mux),
2994 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2995 &rt5677_if2_dac6_tdm_sel_mux),
2996 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2997 &rt5677_if2_dac7_tdm_sel_mux),
2999 /* Audio Interface */
3000 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3001 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3002 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3003 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3004 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3005 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3006 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3007 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3008 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3009 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3012 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3013 &rt5677_sidetone_mux),
3014 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3015 RT5677_ST_EN_SFT, 0, NULL, 0),
3018 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3019 &rt5677_vad_src_mux),
3022 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3023 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3024 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3025 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3026 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3027 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3028 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3029 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3030 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3031 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3032 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3033 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3034 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3037 /* DAC mixer before sound effect */
3038 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3039 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3040 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3041 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3042 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3045 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3047 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3049 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3051 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3054 /* DAC2 channel Mux */
3055 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3056 &rt5677_dac2_l_mux),
3057 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3058 &rt5677_dac2_r_mux),
3060 /* DAC3 channel Mux */
3061 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3062 &rt5677_dac3_l_mux),
3063 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3064 &rt5677_dac3_r_mux),
3066 /* DAC4 channel Mux */
3067 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3068 &rt5677_dac4_l_mux),
3069 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3070 &rt5677_dac4_r_mux),
3073 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3074 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
3075 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
3076 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
3077 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
3078 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
3079 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3080 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
3081 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3082 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
3083 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3084 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
3085 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3086 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
3088 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3089 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3090 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3091 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3092 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3093 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3094 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3095 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3096 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3097 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3098 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3099 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3100 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3101 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3102 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3103 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3104 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3105 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3106 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3107 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3110 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3111 RT5677_PWR_DAC1_BIT, 0),
3112 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3113 RT5677_PWR_DAC2_BIT, 0),
3114 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3115 RT5677_PWR_DAC3_BIT, 0),
3118 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3119 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3120 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3121 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3123 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3124 1, &rt5677_pdm1_l_mux),
3125 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3126 1, &rt5677_pdm1_r_mux),
3127 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3128 1, &rt5677_pdm2_l_mux),
3129 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3130 1, &rt5677_pdm2_r_mux),
3132 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3134 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3136 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3139 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3140 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3141 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3142 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3143 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3144 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3147 SND_SOC_DAPM_OUTPUT("LOUT1"),
3148 SND_SOC_DAPM_OUTPUT("LOUT2"),
3149 SND_SOC_DAPM_OUTPUT("LOUT3"),
3150 SND_SOC_DAPM_OUTPUT("PDM1L"),
3151 SND_SOC_DAPM_OUTPUT("PDM1R"),
3152 SND_SOC_DAPM_OUTPUT("PDM2L"),
3153 SND_SOC_DAPM_OUTPUT("PDM2R"),
3155 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3158 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3159 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3160 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3161 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3162 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3163 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3164 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3165 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3166 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3167 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3168 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3170 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3171 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3172 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3173 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3174 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3175 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3176 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3177 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3178 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3179 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3180 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3181 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3182 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3184 { "DMIC1", NULL, "DMIC L1" },
3185 { "DMIC1", NULL, "DMIC R1" },
3186 { "DMIC2", NULL, "DMIC L2" },
3187 { "DMIC2", NULL, "DMIC R2" },
3188 { "DMIC3", NULL, "DMIC L3" },
3189 { "DMIC3", NULL, "DMIC R3" },
3190 { "DMIC4", NULL, "DMIC L4" },
3191 { "DMIC4", NULL, "DMIC R4" },
3193 { "DMIC L1", NULL, "DMIC CLK" },
3194 { "DMIC R1", NULL, "DMIC CLK" },
3195 { "DMIC L2", NULL, "DMIC CLK" },
3196 { "DMIC R2", NULL, "DMIC CLK" },
3197 { "DMIC L3", NULL, "DMIC CLK" },
3198 { "DMIC R3", NULL, "DMIC CLK" },
3199 { "DMIC L4", NULL, "DMIC CLK" },
3200 { "DMIC R4", NULL, "DMIC CLK" },
3202 { "DMIC L1", NULL, "DMIC1 power" },
3203 { "DMIC R1", NULL, "DMIC1 power" },
3204 { "DMIC L3", NULL, "DMIC3 power" },
3205 { "DMIC R3", NULL, "DMIC3 power" },
3206 { "DMIC L4", NULL, "DMIC4 power" },
3207 { "DMIC R4", NULL, "DMIC4 power" },
3209 { "BST1", NULL, "IN1P" },
3210 { "BST1", NULL, "IN1N" },
3211 { "BST2", NULL, "IN2P" },
3212 { "BST2", NULL, "IN2N" },
3214 { "IN1P", NULL, "MICBIAS1" },
3215 { "IN1N", NULL, "MICBIAS1" },
3216 { "IN2P", NULL, "MICBIAS1" },
3217 { "IN2N", NULL, "MICBIAS1" },
3219 { "ADC 1", NULL, "BST1" },
3220 { "ADC 1", NULL, "ADC 1 power" },
3221 { "ADC 1", NULL, "ADC1 clock" },
3222 { "ADC 2", NULL, "BST2" },
3223 { "ADC 2", NULL, "ADC 2 power" },
3224 { "ADC 2", NULL, "ADC2 clock" },
3226 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3227 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3228 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3229 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3231 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3232 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3233 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3234 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3236 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3237 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3238 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3239 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3241 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3242 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3243 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3244 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3246 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3247 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3248 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3249 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3251 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3252 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3253 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3254 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3256 { "ADC 1_2", NULL, "ADC 1" },
3257 { "ADC 1_2", NULL, "ADC 2" },
3259 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3260 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3261 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3263 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3264 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3265 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3267 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3268 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3269 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3271 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3272 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3273 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3275 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3276 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3277 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3279 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3280 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3281 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3283 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3284 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3285 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3287 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3288 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3289 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3291 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3292 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3293 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3295 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3296 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3297 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3299 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3300 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3301 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3303 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3304 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3305 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3307 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3308 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3309 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3310 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3312 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3313 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3314 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3315 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3316 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3318 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3319 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3321 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3322 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3323 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3324 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3326 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3327 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3329 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3330 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3332 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3333 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3334 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3335 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3336 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3338 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3339 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3341 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3342 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3343 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3344 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3346 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3347 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3348 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3349 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3350 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3352 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3353 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3355 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3356 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3357 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3358 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3360 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3361 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3362 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3363 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3364 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3366 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3367 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3369 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3370 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3371 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3372 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3374 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3375 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3376 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3377 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3379 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3380 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3382 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3383 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3384 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3385 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3386 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3388 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3389 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3390 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3392 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3393 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3395 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3396 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3397 { "IF1 ADC3 Mux", "OB45", "OB45" },
3399 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3400 { "IF1 ADC4 Mux", "OB67", "OB67" },
3401 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3403 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3404 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3405 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3406 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3408 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3409 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3410 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3411 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3413 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3414 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3415 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3416 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3418 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3419 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3420 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3421 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3423 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3424 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3425 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3426 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3428 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3429 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3430 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3431 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3432 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3433 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3434 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3435 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3437 { "AIF1TX", NULL, "I2S1" },
3438 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3440 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3441 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3442 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3444 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3445 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3447 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3448 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3449 { "IF2 ADC3 Mux", "OB45", "OB45" },
3451 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3452 { "IF2 ADC4 Mux", "OB67", "OB67" },
3453 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3455 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3456 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3457 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3458 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3460 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3461 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3462 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3463 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3465 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3466 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3467 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3468 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3470 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3471 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3472 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3473 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3475 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3476 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3477 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3478 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3480 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3481 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3482 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3483 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3484 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3485 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3486 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3487 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3489 { "AIF2TX", NULL, "I2S2" },
3490 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3492 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3493 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3494 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3495 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3496 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3497 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3498 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3499 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3501 { "AIF3TX", NULL, "I2S3" },
3502 { "AIF3TX", NULL, "IF3 ADC Mux" },
3504 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3505 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3506 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3507 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3508 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3509 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3510 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3511 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3513 { "AIF4TX", NULL, "I2S4" },
3514 { "AIF4TX", NULL, "IF4 ADC Mux" },
3516 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3517 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3518 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3520 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3521 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3523 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3524 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3525 { "SLB ADC3 Mux", "OB45", "OB45" },
3527 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3528 { "SLB ADC4 Mux", "OB67", "OB67" },
3529 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3531 { "SLBTX", NULL, "SLB" },
3532 { "SLBTX", NULL, "SLB ADC1 Mux" },
3533 { "SLBTX", NULL, "SLB ADC2 Mux" },
3534 { "SLBTX", NULL, "SLB ADC3 Mux" },
3535 { "SLBTX", NULL, "SLB ADC4 Mux" },
3537 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3538 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3539 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3540 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3541 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3543 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3544 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3546 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3547 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3548 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3549 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3550 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3551 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3553 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3554 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3556 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3557 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3558 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3559 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3560 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3562 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3563 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3565 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3566 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3567 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3568 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3569 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3570 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3571 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3572 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3574 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3575 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3576 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3577 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3578 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3579 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3580 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3581 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3583 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3584 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3585 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3586 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3587 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3588 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3590 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3591 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3592 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3593 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3594 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3595 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3596 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3598 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3599 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3600 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3601 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3602 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3603 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3604 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3606 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3607 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3608 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3609 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3610 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3611 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3612 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3614 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3615 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3616 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3617 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3618 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3619 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3620 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3622 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3623 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3624 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3625 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3626 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3627 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3628 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3630 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3631 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3632 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3633 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3634 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3635 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3636 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3638 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3639 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3640 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3641 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3642 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3643 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3644 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3646 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3647 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3648 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3649 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3651 { "OutBound2", NULL, "OB23 Bypass Mux" },
3652 { "OutBound3", NULL, "OB23 Bypass Mux" },
3653 { "OutBound4", NULL, "OB4 MIX" },
3654 { "OutBound5", NULL, "OB5 MIX" },
3655 { "OutBound6", NULL, "OB6 MIX" },
3656 { "OutBound7", NULL, "OB7 MIX" },
3658 { "OB45", NULL, "OutBound4" },
3659 { "OB45", NULL, "OutBound5" },
3660 { "OB67", NULL, "OutBound6" },
3661 { "OB67", NULL, "OutBound7" },
3663 { "IF1 DAC0", NULL, "AIF1RX" },
3664 { "IF1 DAC1", NULL, "AIF1RX" },
3665 { "IF1 DAC2", NULL, "AIF1RX" },
3666 { "IF1 DAC3", NULL, "AIF1RX" },
3667 { "IF1 DAC4", NULL, "AIF1RX" },
3668 { "IF1 DAC5", NULL, "AIF1RX" },
3669 { "IF1 DAC6", NULL, "AIF1RX" },
3670 { "IF1 DAC7", NULL, "AIF1RX" },
3671 { "IF1 DAC0", NULL, "I2S1" },
3672 { "IF1 DAC1", NULL, "I2S1" },
3673 { "IF1 DAC2", NULL, "I2S1" },
3674 { "IF1 DAC3", NULL, "I2S1" },
3675 { "IF1 DAC4", NULL, "I2S1" },
3676 { "IF1 DAC5", NULL, "I2S1" },
3677 { "IF1 DAC6", NULL, "I2S1" },
3678 { "IF1 DAC7", NULL, "I2S1" },
3680 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3681 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3682 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3683 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3684 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3685 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3686 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3687 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3689 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3690 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3691 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3692 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3693 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3694 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3695 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3696 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3698 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3699 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3700 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3701 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3702 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3703 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3704 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3705 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3707 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3708 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3709 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3710 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3711 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3712 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3713 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3714 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3716 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3717 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3718 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3719 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3720 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3721 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3722 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3723 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3725 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3726 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3727 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3728 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3729 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3730 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3731 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3732 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3734 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3735 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3736 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3737 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3738 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3739 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3740 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3741 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3743 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3744 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3745 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3746 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3747 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3748 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3749 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3750 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3752 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3753 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3754 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3755 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3756 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3757 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3758 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3759 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3761 { "IF2 DAC0", NULL, "AIF2RX" },
3762 { "IF2 DAC1", NULL, "AIF2RX" },
3763 { "IF2 DAC2", NULL, "AIF2RX" },
3764 { "IF2 DAC3", NULL, "AIF2RX" },
3765 { "IF2 DAC4", NULL, "AIF2RX" },
3766 { "IF2 DAC5", NULL, "AIF2RX" },
3767 { "IF2 DAC6", NULL, "AIF2RX" },
3768 { "IF2 DAC7", NULL, "AIF2RX" },
3769 { "IF2 DAC0", NULL, "I2S2" },
3770 { "IF2 DAC1", NULL, "I2S2" },
3771 { "IF2 DAC2", NULL, "I2S2" },
3772 { "IF2 DAC3", NULL, "I2S2" },
3773 { "IF2 DAC4", NULL, "I2S2" },
3774 { "IF2 DAC5", NULL, "I2S2" },
3775 { "IF2 DAC6", NULL, "I2S2" },
3776 { "IF2 DAC7", NULL, "I2S2" },
3778 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3779 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3780 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3781 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3782 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3783 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3784 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3785 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3787 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3788 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3789 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3790 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3791 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3792 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3793 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3794 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3796 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3797 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3798 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3799 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3800 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3801 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3802 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3803 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3805 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3806 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3807 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3808 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3809 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3810 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3811 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3812 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3814 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3815 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3816 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3817 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3818 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3819 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3820 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3821 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3823 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3824 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3825 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3826 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3827 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3828 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3829 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3830 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3832 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3833 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3834 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3835 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3836 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3837 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3838 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3839 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3841 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3842 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3843 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3844 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3845 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3846 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3847 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3848 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3850 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3851 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3852 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3853 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3854 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3855 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3856 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3857 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3859 { "IF3 DAC", NULL, "AIF3RX" },
3860 { "IF3 DAC", NULL, "I2S3" },
3862 { "IF4 DAC", NULL, "AIF4RX" },
3863 { "IF4 DAC", NULL, "I2S4" },
3865 { "IF3 DAC L", NULL, "IF3 DAC" },
3866 { "IF3 DAC R", NULL, "IF3 DAC" },
3868 { "IF4 DAC L", NULL, "IF4 DAC" },
3869 { "IF4 DAC R", NULL, "IF4 DAC" },
3871 { "SLB DAC0", NULL, "SLBRX" },
3872 { "SLB DAC1", NULL, "SLBRX" },
3873 { "SLB DAC2", NULL, "SLBRX" },
3874 { "SLB DAC3", NULL, "SLBRX" },
3875 { "SLB DAC4", NULL, "SLBRX" },
3876 { "SLB DAC5", NULL, "SLBRX" },
3877 { "SLB DAC6", NULL, "SLBRX" },
3878 { "SLB DAC7", NULL, "SLBRX" },
3879 { "SLB DAC0", NULL, "SLB" },
3880 { "SLB DAC1", NULL, "SLB" },
3881 { "SLB DAC2", NULL, "SLB" },
3882 { "SLB DAC3", NULL, "SLB" },
3883 { "SLB DAC4", NULL, "SLB" },
3884 { "SLB DAC5", NULL, "SLB" },
3885 { "SLB DAC6", NULL, "SLB" },
3886 { "SLB DAC7", NULL, "SLB" },
3888 { "SLB DAC01", NULL, "SLB DAC0" },
3889 { "SLB DAC01", NULL, "SLB DAC1" },
3890 { "SLB DAC23", NULL, "SLB DAC2" },
3891 { "SLB DAC23", NULL, "SLB DAC3" },
3892 { "SLB DAC45", NULL, "SLB DAC4" },
3893 { "SLB DAC45", NULL, "SLB DAC5" },
3894 { "SLB DAC67", NULL, "SLB DAC6" },
3895 { "SLB DAC67", NULL, "SLB DAC7" },
3897 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3898 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3899 { "ADDA1 Mux", "OB 67", "OB67" },
3901 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3902 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3903 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3904 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3905 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3906 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3908 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3909 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3910 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3911 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3913 { "DAC1 FS", NULL, "DAC1 MIXL" },
3914 { "DAC1 FS", NULL, "DAC1 MIXR" },
3916 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3917 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3918 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3919 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3920 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3921 { "DAC2 L Mux", "OB 2", "OutBound2" },
3923 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3924 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3925 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3926 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3927 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3928 { "DAC2 R Mux", "OB 3", "OutBound3" },
3929 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3930 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3932 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3933 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3934 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3935 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3936 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3937 { "DAC3 L Mux", "OB 4", "OutBound4" },
3939 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3940 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3941 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3942 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3943 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3944 { "DAC3 R Mux", "OB 5", "OutBound5" },
3946 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3947 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3948 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3949 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3950 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3951 { "DAC4 L Mux", "OB 6", "OutBound6" },
3953 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3954 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3955 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3956 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3957 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3958 { "DAC4 R Mux", "OB 7", "OutBound7" },
3960 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3961 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3962 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3963 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3964 { "Sidetone Mux", "ADC1", "ADC 1" },
3965 { "Sidetone Mux", "ADC2", "ADC 2" },
3966 { "Sidetone Mux", NULL, "Sidetone Power" },
3968 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3969 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3970 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3971 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3972 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3973 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3974 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3975 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3976 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3977 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3978 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3980 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3981 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3982 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3983 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3984 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3985 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3986 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3987 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3988 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3989 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3990 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3991 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3993 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3994 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3995 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3996 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3997 { "DD1 MIXL", NULL, "dac mono3 left filter" },
3998 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3999 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4000 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4001 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4002 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4003 { "DD1 MIXR", NULL, "dac mono3 right filter" },
4004 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4006 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4007 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4008 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4009 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4010 { "DD2 MIXL", NULL, "dac mono4 left filter" },
4011 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4012 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4013 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4014 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4015 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4016 { "DD2 MIXR", NULL, "dac mono4 right filter" },
4017 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4019 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4020 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4021 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4022 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4023 { "DD1 MIX", NULL, "DD1 MIXL" },
4024 { "DD1 MIX", NULL, "DD1 MIXR" },
4025 { "DD2 MIX", NULL, "DD2 MIXL" },
4026 { "DD2 MIX", NULL, "DD2 MIXR" },
4028 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4029 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4030 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4031 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4033 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4034 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4035 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4036 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4038 { "DAC 1", NULL, "DAC12 SRC Mux" },
4039 { "DAC 2", NULL, "DAC12 SRC Mux" },
4040 { "DAC 3", NULL, "DAC3 SRC Mux" },
4042 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4043 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4044 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4045 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4046 { "PDM1 L Mux", NULL, "PDM1 Power" },
4047 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4048 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4049 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4050 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4051 { "PDM1 R Mux", NULL, "PDM1 Power" },
4052 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4053 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4054 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4055 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4056 { "PDM2 L Mux", NULL, "PDM2 Power" },
4057 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4058 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4059 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4060 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4061 { "PDM2 R Mux", NULL, "PDM2 Power" },
4063 { "LOUT1 amp", NULL, "DAC 1" },
4064 { "LOUT2 amp", NULL, "DAC 2" },
4065 { "LOUT3 amp", NULL, "DAC 3" },
4067 { "LOUT1 vref", NULL, "LOUT1 amp" },
4068 { "LOUT2 vref", NULL, "LOUT2 amp" },
4069 { "LOUT3 vref", NULL, "LOUT3 amp" },
4071 { "LOUT1", NULL, "LOUT1 vref" },
4072 { "LOUT2", NULL, "LOUT2 vref" },
4073 { "LOUT3", NULL, "LOUT3 vref" },
4075 { "PDM1L", NULL, "PDM1 L Mux" },
4076 { "PDM1R", NULL, "PDM1 R Mux" },
4077 { "PDM2L", NULL, "PDM2 L Mux" },
4078 { "PDM2R", NULL, "PDM2 R Mux" },
4081 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4082 { "DMIC L2", NULL, "DMIC1 power" },
4083 { "DMIC R2", NULL, "DMIC1 power" },
4086 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4087 { "DMIC L2", NULL, "DMIC2 power" },
4088 { "DMIC R2", NULL, "DMIC2 power" },
4091 static int rt5677_hw_params(struct snd_pcm_substream *substream,
4092 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4094 struct snd_soc_codec *codec = dai->codec;
4095 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4096 unsigned int val_len = 0, val_clk, mask_clk;
4097 int pre_div, bclk_ms, frame_size;
4099 rt5677->lrck[dai->id] = params_rate(params);
4100 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4102 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4103 rt5677->sysclk, rt5677->lrck[dai->id]);
4106 frame_size = snd_soc_params_to_frame_size(params);
4107 if (frame_size < 0) {
4108 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4111 bclk_ms = frame_size > 32;
4112 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4114 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4115 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4116 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4117 bclk_ms, pre_div, dai->id);
4119 switch (params_width(params)) {
4123 val_len |= RT5677_I2S_DL_20;
4126 val_len |= RT5677_I2S_DL_24;
4129 val_len |= RT5677_I2S_DL_8;
4137 mask_clk = RT5677_I2S_PD1_MASK;
4138 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4139 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4140 RT5677_I2S_DL_MASK, val_len);
4141 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4145 mask_clk = RT5677_I2S_PD2_MASK;
4146 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4147 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4148 RT5677_I2S_DL_MASK, val_len);
4149 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4153 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4154 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4155 pre_div << RT5677_I2S_PD3_SFT;
4156 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4157 RT5677_I2S_DL_MASK, val_len);
4158 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4162 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4163 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4164 pre_div << RT5677_I2S_PD4_SFT;
4165 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4166 RT5677_I2S_DL_MASK, val_len);
4167 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4177 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4179 struct snd_soc_codec *codec = dai->codec;
4180 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4181 unsigned int reg_val = 0;
4183 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4184 case SND_SOC_DAIFMT_CBM_CFM:
4185 rt5677->master[dai->id] = 1;
4187 case SND_SOC_DAIFMT_CBS_CFS:
4188 reg_val |= RT5677_I2S_MS_S;
4189 rt5677->master[dai->id] = 0;
4195 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4196 case SND_SOC_DAIFMT_NB_NF:
4198 case SND_SOC_DAIFMT_IB_NF:
4199 reg_val |= RT5677_I2S_BP_INV;
4205 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4206 case SND_SOC_DAIFMT_I2S:
4208 case SND_SOC_DAIFMT_LEFT_J:
4209 reg_val |= RT5677_I2S_DF_LEFT;
4211 case SND_SOC_DAIFMT_DSP_A:
4212 reg_val |= RT5677_I2S_DF_PCM_A;
4214 case SND_SOC_DAIFMT_DSP_B:
4215 reg_val |= RT5677_I2S_DF_PCM_B;
4223 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4224 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4225 RT5677_I2S_DF_MASK, reg_val);
4228 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4229 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4230 RT5677_I2S_DF_MASK, reg_val);
4233 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4234 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4235 RT5677_I2S_DF_MASK, reg_val);
4238 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4239 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4240 RT5677_I2S_DF_MASK, reg_val);
4250 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4251 int clk_id, unsigned int freq, int dir)
4253 struct snd_soc_codec *codec = dai->codec;
4254 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4255 unsigned int reg_val = 0;
4257 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4261 case RT5677_SCLK_S_MCLK:
4262 reg_val |= RT5677_SCLK_SRC_MCLK;
4264 case RT5677_SCLK_S_PLL1:
4265 reg_val |= RT5677_SCLK_SRC_PLL1;
4267 case RT5677_SCLK_S_RCCLK:
4268 reg_val |= RT5677_SCLK_SRC_RCCLK;
4271 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4274 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4275 RT5677_SCLK_SRC_MASK, reg_val);
4276 rt5677->sysclk = freq;
4277 rt5677->sysclk_src = clk_id;
4279 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4285 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4286 * @freq_in: external clock provided to codec.
4287 * @freq_out: target clock which codec works on.
4288 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4290 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4292 * Returns 0 for success or negative error code.
4294 static int rt5677_pll_calc(const unsigned int freq_in,
4295 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4297 if (RT5677_PLL_INP_MIN > freq_in)
4300 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4303 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4304 unsigned int freq_in, unsigned int freq_out)
4306 struct snd_soc_codec *codec = dai->codec;
4307 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4308 struct rl6231_pll_code pll_code;
4311 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4312 freq_out == rt5677->pll_out)
4315 if (!freq_in || !freq_out) {
4316 dev_dbg(codec->dev, "PLL disabled\n");
4319 rt5677->pll_out = 0;
4320 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4321 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4326 case RT5677_PLL1_S_MCLK:
4327 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4328 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4330 case RT5677_PLL1_S_BCLK1:
4331 case RT5677_PLL1_S_BCLK2:
4332 case RT5677_PLL1_S_BCLK3:
4333 case RT5677_PLL1_S_BCLK4:
4336 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4337 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4340 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4341 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4344 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4345 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4348 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4349 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4356 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4360 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4362 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4366 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4367 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4368 pll_code.n_code, pll_code.k_code);
4370 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4371 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4372 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4373 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4374 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4376 rt5677->pll_in = freq_in;
4377 rt5677->pll_out = freq_out;
4378 rt5677->pll_src = source;
4383 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4384 unsigned int rx_mask, int slots, int slot_width)
4386 struct snd_soc_codec *codec = dai->codec;
4387 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4388 unsigned int val = 0, slot_width_25 = 0;
4390 if (rx_mask || tx_mask)
4408 switch (slot_width) {
4413 slot_width_25 = 0x8080;
4427 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4429 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4433 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4435 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4445 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4446 enum snd_soc_bias_level level)
4448 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4451 case SND_SOC_BIAS_ON:
4454 case SND_SOC_BIAS_PREPARE:
4455 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
4456 rt5677_set_dsp_vad(codec, false);
4458 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4459 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4461 regmap_update_bits(rt5677->regmap,
4462 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4464 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4465 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4466 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4467 RT5677_PWR_BG | RT5677_PWR_VREF2,
4468 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4469 RT5677_PWR_BG | RT5677_PWR_VREF2);
4470 rt5677->is_vref_slow = false;
4471 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4472 RT5677_PWR_CORE, RT5677_PWR_CORE);
4473 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4478 case SND_SOC_BIAS_STANDBY:
4481 case SND_SOC_BIAS_OFF:
4482 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4483 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4484 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4485 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4486 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4487 regmap_update_bits(rt5677->regmap,
4488 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4490 if (rt5677->dsp_vad_en)
4491 rt5677_set_dsp_vad(codec, true);
4501 #ifdef CONFIG_GPIOLIB
4502 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4504 return container_of(chip, struct rt5677_priv, gpio_chip);
4507 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4509 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4512 case RT5677_GPIO1 ... RT5677_GPIO5:
4513 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4514 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4518 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4519 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4527 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4528 unsigned offset, int value)
4530 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4533 case RT5677_GPIO1 ... RT5677_GPIO5:
4534 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4535 0x3 << (offset * 3 + 1),
4536 (0x2 | !!value) << (offset * 3 + 1));
4540 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4541 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4542 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4552 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4554 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4557 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4561 return (value & (0x1 << offset)) >> offset;
4564 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4566 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4569 case RT5677_GPIO1 ... RT5677_GPIO5:
4570 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4571 0x1 << (offset * 3 + 2), 0x0);
4575 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4576 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4586 /** Configures the gpio as
4591 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4597 case RT5677_GPIO1 ... RT5677_GPIO2:
4598 shift = 2 * (1 - offset);
4599 regmap_update_bits(rt5677->regmap,
4600 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4602 (value & 0x3) << shift);
4605 case RT5677_GPIO3 ... RT5677_GPIO6:
4606 shift = 2 * (9 - offset);
4607 regmap_update_bits(rt5677->regmap,
4608 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4610 (value & 0x3) << shift);
4618 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4620 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4621 struct regmap_irq_chip_data *data = rt5677->irq_data;
4624 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4625 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4626 (rt5677->pdata.jd1_gpio == 2 &&
4627 offset == RT5677_GPIO2) ||
4628 (rt5677->pdata.jd1_gpio == 3 &&
4629 offset == RT5677_GPIO3)) {
4630 irq = RT5677_IRQ_JD1;
4636 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4637 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4638 (rt5677->pdata.jd2_gpio == 2 &&
4639 offset == RT5677_GPIO5) ||
4640 (rt5677->pdata.jd2_gpio == 3 &&
4641 offset == RT5677_GPIO6)) {
4642 irq = RT5677_IRQ_JD2;
4643 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4644 offset == RT5677_GPIO4) ||
4645 (rt5677->pdata.jd3_gpio == 2 &&
4646 offset == RT5677_GPIO5) ||
4647 (rt5677->pdata.jd3_gpio == 3 &&
4648 offset == RT5677_GPIO6)) {
4649 irq = RT5677_IRQ_JD3;
4655 return regmap_irq_get_virq(data, irq);
4658 static struct gpio_chip rt5677_template_chip = {
4660 .owner = THIS_MODULE,
4661 .direction_output = rt5677_gpio_direction_out,
4662 .set = rt5677_gpio_set,
4663 .direction_input = rt5677_gpio_direction_in,
4664 .get = rt5677_gpio_get,
4665 .to_irq = rt5677_to_irq,
4669 static void rt5677_init_gpio(struct i2c_client *i2c)
4671 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4674 rt5677->gpio_chip = rt5677_template_chip;
4675 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4676 rt5677->gpio_chip.dev = &i2c->dev;
4677 rt5677->gpio_chip.base = -1;
4679 ret = gpiochip_add(&rt5677->gpio_chip);
4681 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4684 static void rt5677_free_gpio(struct i2c_client *i2c)
4686 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4688 gpiochip_remove(&rt5677->gpio_chip);
4691 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4696 static void rt5677_init_gpio(struct i2c_client *i2c)
4700 static void rt5677_free_gpio(struct i2c_client *i2c)
4705 static int rt5677_probe(struct snd_soc_codec *codec)
4707 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
4708 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4711 rt5677->codec = codec;
4713 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4714 snd_soc_dapm_add_routes(dapm,
4716 ARRAY_SIZE(rt5677_dmic2_clk_2));
4717 } else { /*use dmic1 clock by default*/
4718 snd_soc_dapm_add_routes(dapm,
4720 ARRAY_SIZE(rt5677_dmic2_clk_1));
4723 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
4725 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4726 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4728 for (i = 0; i < RT5677_GPIO_NUM; i++)
4729 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4731 if (rt5677->irq_data) {
4732 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4734 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4737 if (rt5677->pdata.jd1_gpio)
4738 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4739 RT5677_SEL_GPIO_JD1_MASK,
4740 rt5677->pdata.jd1_gpio <<
4741 RT5677_SEL_GPIO_JD1_SFT);
4743 if (rt5677->pdata.jd2_gpio)
4744 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4745 RT5677_SEL_GPIO_JD2_MASK,
4746 rt5677->pdata.jd2_gpio <<
4747 RT5677_SEL_GPIO_JD2_SFT);
4749 if (rt5677->pdata.jd3_gpio)
4750 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4751 RT5677_SEL_GPIO_JD3_MASK,
4752 rt5677->pdata.jd3_gpio <<
4753 RT5677_SEL_GPIO_JD3_SFT);
4756 mutex_init(&rt5677->dsp_cmd_lock);
4757 mutex_init(&rt5677->dsp_pri_lock);
4762 static int rt5677_remove(struct snd_soc_codec *codec)
4764 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4766 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4767 if (gpio_is_valid(rt5677->pow_ldo2))
4768 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4769 if (gpio_is_valid(rt5677->reset_pin))
4770 gpio_set_value_cansleep(rt5677->reset_pin, 0);
4776 static int rt5677_suspend(struct snd_soc_codec *codec)
4778 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4780 if (!rt5677->dsp_vad_en) {
4781 regcache_cache_only(rt5677->regmap, true);
4782 regcache_mark_dirty(rt5677->regmap);
4784 if (gpio_is_valid(rt5677->pow_ldo2))
4785 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4786 if (gpio_is_valid(rt5677->reset_pin))
4787 gpio_set_value_cansleep(rt5677->reset_pin, 0);
4793 static int rt5677_resume(struct snd_soc_codec *codec)
4795 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4797 if (!rt5677->dsp_vad_en) {
4798 if (gpio_is_valid(rt5677->pow_ldo2))
4799 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4800 if (gpio_is_valid(rt5677->reset_pin))
4801 gpio_set_value_cansleep(rt5677->reset_pin, 1);
4802 if (gpio_is_valid(rt5677->pow_ldo2) ||
4803 gpio_is_valid(rt5677->reset_pin))
4806 regcache_cache_only(rt5677->regmap, false);
4807 regcache_sync(rt5677->regmap);
4813 #define rt5677_suspend NULL
4814 #define rt5677_resume NULL
4817 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4819 struct i2c_client *client = context;
4820 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4822 if (rt5677->is_dsp_mode) {
4824 mutex_lock(&rt5677->dsp_pri_lock);
4825 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4827 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4828 mutex_unlock(&rt5677->dsp_pri_lock);
4830 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4833 regmap_read(rt5677->regmap_physical, reg, val);
4839 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4841 struct i2c_client *client = context;
4842 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4844 if (rt5677->is_dsp_mode) {
4846 mutex_lock(&rt5677->dsp_pri_lock);
4847 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4849 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4851 mutex_unlock(&rt5677->dsp_pri_lock);
4853 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4856 regmap_write(rt5677->regmap_physical, reg, val);
4862 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4863 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4864 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4866 static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4867 .hw_params = rt5677_hw_params,
4868 .set_fmt = rt5677_set_dai_fmt,
4869 .set_sysclk = rt5677_set_dai_sysclk,
4870 .set_pll = rt5677_set_dai_pll,
4871 .set_tdm_slot = rt5677_set_tdm_slot,
4874 static struct snd_soc_dai_driver rt5677_dai[] = {
4876 .name = "rt5677-aif1",
4879 .stream_name = "AIF1 Playback",
4882 .rates = RT5677_STEREO_RATES,
4883 .formats = RT5677_FORMATS,
4886 .stream_name = "AIF1 Capture",
4889 .rates = RT5677_STEREO_RATES,
4890 .formats = RT5677_FORMATS,
4892 .ops = &rt5677_aif_dai_ops,
4895 .name = "rt5677-aif2",
4898 .stream_name = "AIF2 Playback",
4901 .rates = RT5677_STEREO_RATES,
4902 .formats = RT5677_FORMATS,
4905 .stream_name = "AIF2 Capture",
4908 .rates = RT5677_STEREO_RATES,
4909 .formats = RT5677_FORMATS,
4911 .ops = &rt5677_aif_dai_ops,
4914 .name = "rt5677-aif3",
4917 .stream_name = "AIF3 Playback",
4920 .rates = RT5677_STEREO_RATES,
4921 .formats = RT5677_FORMATS,
4924 .stream_name = "AIF3 Capture",
4927 .rates = RT5677_STEREO_RATES,
4928 .formats = RT5677_FORMATS,
4930 .ops = &rt5677_aif_dai_ops,
4933 .name = "rt5677-aif4",
4936 .stream_name = "AIF4 Playback",
4939 .rates = RT5677_STEREO_RATES,
4940 .formats = RT5677_FORMATS,
4943 .stream_name = "AIF4 Capture",
4946 .rates = RT5677_STEREO_RATES,
4947 .formats = RT5677_FORMATS,
4949 .ops = &rt5677_aif_dai_ops,
4952 .name = "rt5677-slimbus",
4955 .stream_name = "SLIMBus Playback",
4958 .rates = RT5677_STEREO_RATES,
4959 .formats = RT5677_FORMATS,
4962 .stream_name = "SLIMBus Capture",
4965 .rates = RT5677_STEREO_RATES,
4966 .formats = RT5677_FORMATS,
4968 .ops = &rt5677_aif_dai_ops,
4972 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4973 .probe = rt5677_probe,
4974 .remove = rt5677_remove,
4975 .suspend = rt5677_suspend,
4976 .resume = rt5677_resume,
4977 .set_bias_level = rt5677_set_bias_level,
4978 .idle_bias_off = true,
4979 .controls = rt5677_snd_controls,
4980 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4981 .dapm_widgets = rt5677_dapm_widgets,
4982 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4983 .dapm_routes = rt5677_dapm_routes,
4984 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4987 static const struct regmap_config rt5677_regmap_physical = {
4992 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4994 .readable_reg = rt5677_readable_register,
4996 .cache_type = REGCACHE_NONE,
4997 .ranges = rt5677_ranges,
4998 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5001 static const struct regmap_config rt5677_regmap = {
5005 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5008 .volatile_reg = rt5677_volatile_register,
5009 .readable_reg = rt5677_readable_register,
5010 .reg_read = rt5677_read,
5011 .reg_write = rt5677_write,
5013 .cache_type = REGCACHE_RBTREE,
5014 .reg_defaults = rt5677_reg,
5015 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5016 .ranges = rt5677_ranges,
5017 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5020 static const struct i2c_device_id rt5677_i2c_id[] = {
5021 { "rt5677", RT5677 },
5022 { "rt5676", RT5676 },
5025 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
5027 static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
5029 rt5677->pdata.in1_diff = of_property_read_bool(np,
5030 "realtek,in1-differential");
5031 rt5677->pdata.in2_diff = of_property_read_bool(np,
5032 "realtek,in2-differential");
5033 rt5677->pdata.lout1_diff = of_property_read_bool(np,
5034 "realtek,lout1-differential");
5035 rt5677->pdata.lout2_diff = of_property_read_bool(np,
5036 "realtek,lout2-differential");
5037 rt5677->pdata.lout3_diff = of_property_read_bool(np,
5038 "realtek,lout3-differential");
5040 rt5677->pow_ldo2 = of_get_named_gpio(np,
5041 "realtek,pow-ldo2-gpio", 0);
5042 rt5677->reset_pin = of_get_named_gpio(np,
5043 "realtek,reset-gpio", 0);
5046 * POW_LDO2 is optional (it may be statically tied on the board).
5047 * -ENOENT means that the property doesn't exist, i.e. there is no
5048 * GPIO, so is not an error. Any other error code means the property
5049 * exists, but could not be parsed.
5051 if (!gpio_is_valid(rt5677->pow_ldo2) &&
5052 (rt5677->pow_ldo2 != -ENOENT))
5053 return rt5677->pow_ldo2;
5054 if (!gpio_is_valid(rt5677->reset_pin) &&
5055 (rt5677->reset_pin != -ENOENT))
5056 return rt5677->reset_pin;
5058 of_property_read_u8_array(np, "realtek,gpio-config",
5059 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5061 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
5062 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
5063 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
5068 static struct regmap_irq rt5677_irqs[] = {
5069 [RT5677_IRQ_JD1] = {
5071 .mask = RT5677_EN_IRQ_GPIO_JD1,
5073 [RT5677_IRQ_JD2] = {
5075 .mask = RT5677_EN_IRQ_GPIO_JD2,
5077 [RT5677_IRQ_JD3] = {
5079 .mask = RT5677_EN_IRQ_GPIO_JD3,
5083 static struct regmap_irq_chip rt5677_irq_chip = {
5085 .irqs = rt5677_irqs,
5086 .num_irqs = ARRAY_SIZE(rt5677_irqs),
5089 .status_base = RT5677_IRQ_CTRL1,
5090 .mask_base = RT5677_IRQ_CTRL1,
5094 static int rt5677_init_irq(struct i2c_client *i2c)
5097 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5099 if (!rt5677->pdata.jd1_gpio &&
5100 !rt5677->pdata.jd2_gpio &&
5101 !rt5677->pdata.jd3_gpio)
5105 dev_err(&i2c->dev, "No interrupt specified\n");
5109 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5110 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5111 &rt5677_irq_chip, &rt5677->irq_data);
5114 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5121 static void rt5677_free_irq(struct i2c_client *i2c)
5123 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5125 if (rt5677->irq_data)
5126 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5129 static int rt5677_i2c_probe(struct i2c_client *i2c,
5130 const struct i2c_device_id *id)
5132 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5133 struct rt5677_priv *rt5677;
5137 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5142 i2c_set_clientdata(i2c, rt5677);
5144 rt5677->type = id->driver_data;
5147 rt5677->pdata = *pdata;
5149 if (i2c->dev.of_node) {
5150 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
5152 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
5157 rt5677->pow_ldo2 = -EINVAL;
5158 rt5677->reset_pin = -EINVAL;
5161 if (gpio_is_valid(rt5677->pow_ldo2)) {
5162 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
5163 GPIOF_OUT_INIT_HIGH,
5166 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
5167 rt5677->pow_ldo2, ret);
5172 if (gpio_is_valid(rt5677->reset_pin)) {
5173 ret = devm_gpio_request_one(&i2c->dev, rt5677->reset_pin,
5174 GPIOF_OUT_INIT_HIGH,
5177 dev_err(&i2c->dev, "Failed to request RESET %d: %d\n",
5178 rt5677->reset_pin, ret);
5183 if (gpio_is_valid(rt5677->pow_ldo2) ||
5184 gpio_is_valid(rt5677->reset_pin)) {
5185 /* Wait a while until I2C bus becomes available. The datasheet
5186 * does not specify the exact we should wait but startup
5187 * sequence mentiones at least a few milliseconds.
5192 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5193 &rt5677_regmap_physical);
5194 if (IS_ERR(rt5677->regmap_physical)) {
5195 ret = PTR_ERR(rt5677->regmap_physical);
5196 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5201 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5202 if (IS_ERR(rt5677->regmap)) {
5203 ret = PTR_ERR(rt5677->regmap);
5204 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5209 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5210 if (val != RT5677_DEVICE_ID) {
5212 "Device with ID register %x is not rt5677\n", val);
5216 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5218 ret = regmap_register_patch(rt5677->regmap, init_list,
5219 ARRAY_SIZE(init_list));
5221 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5223 if (rt5677->pdata.in1_diff)
5224 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5225 RT5677_IN_DF1, RT5677_IN_DF1);
5227 if (rt5677->pdata.in2_diff)
5228 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5229 RT5677_IN_DF2, RT5677_IN_DF2);
5231 if (rt5677->pdata.lout1_diff)
5232 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5233 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5235 if (rt5677->pdata.lout2_diff)
5236 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5237 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5239 if (rt5677->pdata.lout3_diff)
5240 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5241 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5243 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5244 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5245 RT5677_GPIO5_FUNC_MASK,
5246 RT5677_GPIO5_FUNC_DMIC);
5247 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5248 RT5677_GPIO5_DIR_MASK,
5249 RT5677_GPIO5_DIR_OUT);
5252 if (rt5677->pdata.micbias1_vdd_3v3)
5253 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5254 RT5677_MICBIAS1_CTRL_VDD_MASK,
5255 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5257 rt5677_init_gpio(i2c);
5258 rt5677_init_irq(i2c);
5260 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5261 rt5677_dai, ARRAY_SIZE(rt5677_dai));
5264 static int rt5677_i2c_remove(struct i2c_client *i2c)
5266 snd_soc_unregister_codec(&i2c->dev);
5267 rt5677_free_irq(i2c);
5268 rt5677_free_gpio(i2c);
5273 static struct i2c_driver rt5677_i2c_driver = {
5277 .probe = rt5677_i2c_probe,
5278 .remove = rt5677_i2c_remove,
5279 .id_table = rt5677_i2c_id,
5281 module_i2c_driver(rt5677_i2c_driver);
5283 MODULE_DESCRIPTION("ASoC RT5677 driver");
5284 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5285 MODULE_LICENSE("GPL v2");