2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/of_gpio.h>
19 #include <linux/regmap.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/firmware.h>
24 #include <linux/gpio.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/soc-dapm.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
35 #include "rt5677-spi.h"
37 #define RT5677_DEVICE_ID 0x6327
39 #define RT5677_PR_RANGE_BASE (0xff + 1)
40 #define RT5677_PR_SPACING 0x100
42 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
44 static const struct regmap_range_cfg rt5677_ranges[] = {
47 .range_min = RT5677_PR_BASE,
48 .range_max = RT5677_PR_BASE + 0xfd,
49 .selector_reg = RT5677_PRIV_INDEX,
50 .selector_mask = 0xff,
51 .selector_shift = 0x0,
52 .window_start = RT5677_PRIV_DATA,
57 static const struct reg_default init_list[] = {
58 {RT5677_ASRC_12, 0x0018},
59 {RT5677_PR_BASE + 0x3d, 0x364d},
60 {RT5677_PR_BASE + 0x17, 0x4fc0},
61 {RT5677_PR_BASE + 0x13, 0x0312},
62 {RT5677_PR_BASE + 0x1e, 0x0000},
63 {RT5677_PR_BASE + 0x12, 0x0eaa},
64 {RT5677_PR_BASE + 0x14, 0x018a},
66 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
68 static const struct reg_default rt5677_reg[] = {
69 {RT5677_RESET , 0x0000},
70 {RT5677_LOUT1 , 0xa800},
71 {RT5677_IN1 , 0x0000},
72 {RT5677_MICBIAS , 0x0000},
73 {RT5677_SLIMBUS_PARAM , 0x0000},
74 {RT5677_SLIMBUS_RX , 0x0000},
75 {RT5677_SLIMBUS_CTRL , 0x0000},
76 {RT5677_SIDETONE_CTRL , 0x000b},
77 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
78 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
79 {RT5677_DAC4_DIG_VOL , 0xafaf},
80 {RT5677_DAC3_DIG_VOL , 0xafaf},
81 {RT5677_DAC1_DIG_VOL , 0xafaf},
82 {RT5677_DAC2_DIG_VOL , 0xafaf},
83 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
84 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO1_2_ADC_BST , 0x0000},
87 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_ADC_BST_CTRL2 , 0x0000},
89 {RT5677_STO3_4_ADC_BST , 0x0000},
90 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
91 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
92 {RT5677_STO4_ADC_MIXER , 0xd4c0},
93 {RT5677_STO3_ADC_MIXER , 0xd4c0},
94 {RT5677_STO2_ADC_MIXER , 0xd4c0},
95 {RT5677_STO1_ADC_MIXER , 0xd4c0},
96 {RT5677_MONO_ADC_MIXER , 0xd4d1},
97 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
98 {RT5677_STO1_DAC_MIXER , 0xaaaa},
99 {RT5677_MONO_DAC_MIXER , 0xaaaa},
100 {RT5677_DD1_MIXER , 0xaaaa},
101 {RT5677_DD2_MIXER , 0xaaaa},
102 {RT5677_IF3_DATA , 0x0000},
103 {RT5677_IF4_DATA , 0x0000},
104 {RT5677_PDM_OUT_CTRL , 0x8888},
105 {RT5677_PDM_DATA_CTRL1 , 0x0000},
106 {RT5677_PDM_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
108 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
110 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
111 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
113 {RT5677_TDM1_CTRL1 , 0x0300},
114 {RT5677_TDM1_CTRL2 , 0x0000},
115 {RT5677_TDM1_CTRL3 , 0x4000},
116 {RT5677_TDM1_CTRL4 , 0x0123},
117 {RT5677_TDM1_CTRL5 , 0x4567},
118 {RT5677_TDM2_CTRL1 , 0x0300},
119 {RT5677_TDM2_CTRL2 , 0x0000},
120 {RT5677_TDM2_CTRL3 , 0x4000},
121 {RT5677_TDM2_CTRL4 , 0x0123},
122 {RT5677_TDM2_CTRL5 , 0x4567},
123 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
124 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
131 {RT5677_DMIC_CTRL1 , 0x1505},
132 {RT5677_DMIC_CTRL2 , 0x0055},
133 {RT5677_HAP_GENE_CTRL1 , 0x0111},
134 {RT5677_HAP_GENE_CTRL2 , 0x0064},
135 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
136 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
137 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL9 , 0xf000},
142 {RT5677_HAP_GENE_CTRL10 , 0x0000},
143 {RT5677_PWR_DIG1 , 0x0000},
144 {RT5677_PWR_DIG2 , 0x0000},
145 {RT5677_PWR_ANLG1 , 0x0055},
146 {RT5677_PWR_ANLG2 , 0x0000},
147 {RT5677_PWR_DSP1 , 0x0001},
148 {RT5677_PWR_DSP_ST , 0x0000},
149 {RT5677_PWR_DSP2 , 0x0000},
150 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
151 {RT5677_PRIV_INDEX , 0x0000},
152 {RT5677_PRIV_DATA , 0x0000},
153 {RT5677_I2S4_SDP , 0x8000},
154 {RT5677_I2S1_SDP , 0x8000},
155 {RT5677_I2S2_SDP , 0x8000},
156 {RT5677_I2S3_SDP , 0x8000},
157 {RT5677_CLK_TREE_CTRL1 , 0x1111},
158 {RT5677_CLK_TREE_CTRL2 , 0x1111},
159 {RT5677_CLK_TREE_CTRL3 , 0x0000},
160 {RT5677_PLL1_CTRL1 , 0x0000},
161 {RT5677_PLL1_CTRL2 , 0x0000},
162 {RT5677_PLL2_CTRL1 , 0x0c60},
163 {RT5677_PLL2_CTRL2 , 0x2000},
164 {RT5677_GLB_CLK1 , 0x0000},
165 {RT5677_GLB_CLK2 , 0x0000},
166 {RT5677_ASRC_1 , 0x0000},
167 {RT5677_ASRC_2 , 0x0000},
168 {RT5677_ASRC_3 , 0x0000},
169 {RT5677_ASRC_4 , 0x0000},
170 {RT5677_ASRC_5 , 0x0000},
171 {RT5677_ASRC_6 , 0x0000},
172 {RT5677_ASRC_7 , 0x0000},
173 {RT5677_ASRC_8 , 0x0000},
174 {RT5677_ASRC_9 , 0x0000},
175 {RT5677_ASRC_10 , 0x0000},
176 {RT5677_ASRC_11 , 0x0000},
177 {RT5677_ASRC_12 , 0x0018},
178 {RT5677_ASRC_13 , 0x0000},
179 {RT5677_ASRC_14 , 0x0000},
180 {RT5677_ASRC_15 , 0x0000},
181 {RT5677_ASRC_16 , 0x0000},
182 {RT5677_ASRC_17 , 0x0000},
183 {RT5677_ASRC_18 , 0x0000},
184 {RT5677_ASRC_19 , 0x0000},
185 {RT5677_ASRC_20 , 0x0000},
186 {RT5677_ASRC_21 , 0x000c},
187 {RT5677_ASRC_22 , 0x0000},
188 {RT5677_ASRC_23 , 0x0000},
189 {RT5677_VAD_CTRL1 , 0x2184},
190 {RT5677_VAD_CTRL2 , 0x010a},
191 {RT5677_VAD_CTRL3 , 0x0aea},
192 {RT5677_VAD_CTRL4 , 0x000c},
193 {RT5677_VAD_CTRL5 , 0x0000},
194 {RT5677_DSP_INB_CTRL1 , 0x0000},
195 {RT5677_DSP_INB_CTRL2 , 0x0000},
196 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
197 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
198 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
199 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
201 {RT5677_ADC_EQ_CTRL1 , 0x6000},
202 {RT5677_ADC_EQ_CTRL2 , 0x0000},
203 {RT5677_EQ_CTRL1 , 0xc000},
204 {RT5677_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL3 , 0x0000},
206 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
207 {RT5677_JD_CTRL1 , 0x0000},
208 {RT5677_JD_CTRL2 , 0x0000},
209 {RT5677_JD_CTRL3 , 0x0000},
210 {RT5677_IRQ_CTRL1 , 0x0000},
211 {RT5677_IRQ_CTRL2 , 0x0000},
212 {RT5677_GPIO_ST , 0x0000},
213 {RT5677_GPIO_CTRL1 , 0x0000},
214 {RT5677_GPIO_CTRL2 , 0x0000},
215 {RT5677_GPIO_CTRL3 , 0x0000},
216 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
217 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_MB_DRC_CTRL1 , 0x0f20},
227 {RT5677_DRC1_CTRL1 , 0x001f},
228 {RT5677_DRC1_CTRL2 , 0x020c},
229 {RT5677_DRC1_CTRL3 , 0x1f00},
230 {RT5677_DRC1_CTRL4 , 0x0000},
231 {RT5677_DRC1_CTRL5 , 0x0000},
232 {RT5677_DRC1_CTRL6 , 0x0029},
233 {RT5677_DRC2_CTRL1 , 0x001f},
234 {RT5677_DRC2_CTRL2 , 0x020c},
235 {RT5677_DRC2_CTRL3 , 0x1f00},
236 {RT5677_DRC2_CTRL4 , 0x0000},
237 {RT5677_DRC2_CTRL5 , 0x0000},
238 {RT5677_DRC2_CTRL6 , 0x0029},
239 {RT5677_DRC1_HL_CTRL1 , 0x8000},
240 {RT5677_DRC1_HL_CTRL2 , 0x0200},
241 {RT5677_DRC2_HL_CTRL1 , 0x8000},
242 {RT5677_DRC2_HL_CTRL2 , 0x0200},
243 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
244 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
245 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
246 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
247 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
248 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
249 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
250 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
251 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
252 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
253 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
254 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
255 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
260 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
261 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
262 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
263 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
264 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
265 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
266 {RT5677_DIG_MISC , 0x0000},
267 {RT5677_GEN_CTRL1 , 0x0000},
268 {RT5677_GEN_CTRL2 , 0x0000},
269 {RT5677_VENDOR_ID , 0x0000},
270 {RT5677_VENDOR_ID1 , 0x10ec},
271 {RT5677_VENDOR_ID2 , 0x6327},
274 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
278 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
279 if (reg >= rt5677_ranges[i].range_min &&
280 reg <= rt5677_ranges[i].range_max) {
287 case RT5677_SLIMBUS_PARAM:
288 case RT5677_PDM_DATA_CTRL1:
289 case RT5677_PDM_DATA_CTRL2:
290 case RT5677_PDM1_DATA_CTRL4:
291 case RT5677_PDM2_DATA_CTRL4:
292 case RT5677_I2C_MASTER_CTRL1:
293 case RT5677_I2C_MASTER_CTRL7:
294 case RT5677_I2C_MASTER_CTRL8:
295 case RT5677_HAP_GENE_CTRL2:
296 case RT5677_PWR_DSP_ST:
297 case RT5677_PRIV_DATA:
298 case RT5677_PLL1_CTRL2:
299 case RT5677_PLL2_CTRL2:
302 case RT5677_VAD_CTRL5:
303 case RT5677_ADC_EQ_CTRL1:
304 case RT5677_EQ_CTRL1:
305 case RT5677_IRQ_CTRL1:
306 case RT5677_IRQ_CTRL2:
308 case RT5677_DSP_INB1_SRC_CTRL4:
309 case RT5677_DSP_INB2_SRC_CTRL4:
310 case RT5677_DSP_INB3_SRC_CTRL4:
311 case RT5677_DSP_OUTB1_SRC_CTRL4:
312 case RT5677_DSP_OUTB2_SRC_CTRL4:
313 case RT5677_VENDOR_ID:
314 case RT5677_VENDOR_ID1:
315 case RT5677_VENDOR_ID2:
322 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
326 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
327 if (reg >= rt5677_ranges[i].range_min &&
328 reg <= rt5677_ranges[i].range_max) {
338 case RT5677_SLIMBUS_PARAM:
339 case RT5677_SLIMBUS_RX:
340 case RT5677_SLIMBUS_CTRL:
341 case RT5677_SIDETONE_CTRL:
342 case RT5677_ANA_DAC1_2_3_SRC:
343 case RT5677_IF_DSP_DAC3_4_MIXER:
344 case RT5677_DAC4_DIG_VOL:
345 case RT5677_DAC3_DIG_VOL:
346 case RT5677_DAC1_DIG_VOL:
347 case RT5677_DAC2_DIG_VOL:
348 case RT5677_IF_DSP_DAC2_MIXER:
349 case RT5677_STO1_ADC_DIG_VOL:
350 case RT5677_MONO_ADC_DIG_VOL:
351 case RT5677_STO1_2_ADC_BST:
352 case RT5677_STO2_ADC_DIG_VOL:
353 case RT5677_ADC_BST_CTRL2:
354 case RT5677_STO3_4_ADC_BST:
355 case RT5677_STO3_ADC_DIG_VOL:
356 case RT5677_STO4_ADC_DIG_VOL:
357 case RT5677_STO4_ADC_MIXER:
358 case RT5677_STO3_ADC_MIXER:
359 case RT5677_STO2_ADC_MIXER:
360 case RT5677_STO1_ADC_MIXER:
361 case RT5677_MONO_ADC_MIXER:
362 case RT5677_ADC_IF_DSP_DAC1_MIXER:
363 case RT5677_STO1_DAC_MIXER:
364 case RT5677_MONO_DAC_MIXER:
365 case RT5677_DD1_MIXER:
366 case RT5677_DD2_MIXER:
367 case RT5677_IF3_DATA:
368 case RT5677_IF4_DATA:
369 case RT5677_PDM_OUT_CTRL:
370 case RT5677_PDM_DATA_CTRL1:
371 case RT5677_PDM_DATA_CTRL2:
372 case RT5677_PDM1_DATA_CTRL2:
373 case RT5677_PDM1_DATA_CTRL3:
374 case RT5677_PDM1_DATA_CTRL4:
375 case RT5677_PDM2_DATA_CTRL2:
376 case RT5677_PDM2_DATA_CTRL3:
377 case RT5677_PDM2_DATA_CTRL4:
378 case RT5677_TDM1_CTRL1:
379 case RT5677_TDM1_CTRL2:
380 case RT5677_TDM1_CTRL3:
381 case RT5677_TDM1_CTRL4:
382 case RT5677_TDM1_CTRL5:
383 case RT5677_TDM2_CTRL1:
384 case RT5677_TDM2_CTRL2:
385 case RT5677_TDM2_CTRL3:
386 case RT5677_TDM2_CTRL4:
387 case RT5677_TDM2_CTRL5:
388 case RT5677_I2C_MASTER_CTRL1:
389 case RT5677_I2C_MASTER_CTRL2:
390 case RT5677_I2C_MASTER_CTRL3:
391 case RT5677_I2C_MASTER_CTRL4:
392 case RT5677_I2C_MASTER_CTRL5:
393 case RT5677_I2C_MASTER_CTRL6:
394 case RT5677_I2C_MASTER_CTRL7:
395 case RT5677_I2C_MASTER_CTRL8:
396 case RT5677_DMIC_CTRL1:
397 case RT5677_DMIC_CTRL2:
398 case RT5677_HAP_GENE_CTRL1:
399 case RT5677_HAP_GENE_CTRL2:
400 case RT5677_HAP_GENE_CTRL3:
401 case RT5677_HAP_GENE_CTRL4:
402 case RT5677_HAP_GENE_CTRL5:
403 case RT5677_HAP_GENE_CTRL6:
404 case RT5677_HAP_GENE_CTRL7:
405 case RT5677_HAP_GENE_CTRL8:
406 case RT5677_HAP_GENE_CTRL9:
407 case RT5677_HAP_GENE_CTRL10:
408 case RT5677_PWR_DIG1:
409 case RT5677_PWR_DIG2:
410 case RT5677_PWR_ANLG1:
411 case RT5677_PWR_ANLG2:
412 case RT5677_PWR_DSP1:
413 case RT5677_PWR_DSP_ST:
414 case RT5677_PWR_DSP2:
415 case RT5677_ADC_DAC_HPF_CTRL1:
416 case RT5677_PRIV_INDEX:
417 case RT5677_PRIV_DATA:
418 case RT5677_I2S4_SDP:
419 case RT5677_I2S1_SDP:
420 case RT5677_I2S2_SDP:
421 case RT5677_I2S3_SDP:
422 case RT5677_CLK_TREE_CTRL1:
423 case RT5677_CLK_TREE_CTRL2:
424 case RT5677_CLK_TREE_CTRL3:
425 case RT5677_PLL1_CTRL1:
426 case RT5677_PLL1_CTRL2:
427 case RT5677_PLL2_CTRL1:
428 case RT5677_PLL2_CTRL2:
429 case RT5677_GLB_CLK1:
430 case RT5677_GLB_CLK2:
454 case RT5677_VAD_CTRL1:
455 case RT5677_VAD_CTRL2:
456 case RT5677_VAD_CTRL3:
457 case RT5677_VAD_CTRL4:
458 case RT5677_VAD_CTRL5:
459 case RT5677_DSP_INB_CTRL1:
460 case RT5677_DSP_INB_CTRL2:
461 case RT5677_DSP_IN_OUTB_CTRL:
462 case RT5677_DSP_OUTB0_1_DIG_VOL:
463 case RT5677_DSP_OUTB2_3_DIG_VOL:
464 case RT5677_DSP_OUTB4_5_DIG_VOL:
465 case RT5677_DSP_OUTB6_7_DIG_VOL:
466 case RT5677_ADC_EQ_CTRL1:
467 case RT5677_ADC_EQ_CTRL2:
468 case RT5677_EQ_CTRL1:
469 case RT5677_EQ_CTRL2:
470 case RT5677_EQ_CTRL3:
471 case RT5677_SOFT_VOL_ZERO_CROSS1:
472 case RT5677_JD_CTRL1:
473 case RT5677_JD_CTRL2:
474 case RT5677_JD_CTRL3:
475 case RT5677_IRQ_CTRL1:
476 case RT5677_IRQ_CTRL2:
478 case RT5677_GPIO_CTRL1:
479 case RT5677_GPIO_CTRL2:
480 case RT5677_GPIO_CTRL3:
481 case RT5677_STO1_ADC_HI_FILTER1:
482 case RT5677_STO1_ADC_HI_FILTER2:
483 case RT5677_MONO_ADC_HI_FILTER1:
484 case RT5677_MONO_ADC_HI_FILTER2:
485 case RT5677_STO2_ADC_HI_FILTER1:
486 case RT5677_STO2_ADC_HI_FILTER2:
487 case RT5677_STO3_ADC_HI_FILTER1:
488 case RT5677_STO3_ADC_HI_FILTER2:
489 case RT5677_STO4_ADC_HI_FILTER1:
490 case RT5677_STO4_ADC_HI_FILTER2:
491 case RT5677_MB_DRC_CTRL1:
492 case RT5677_DRC1_CTRL1:
493 case RT5677_DRC1_CTRL2:
494 case RT5677_DRC1_CTRL3:
495 case RT5677_DRC1_CTRL4:
496 case RT5677_DRC1_CTRL5:
497 case RT5677_DRC1_CTRL6:
498 case RT5677_DRC2_CTRL1:
499 case RT5677_DRC2_CTRL2:
500 case RT5677_DRC2_CTRL3:
501 case RT5677_DRC2_CTRL4:
502 case RT5677_DRC2_CTRL5:
503 case RT5677_DRC2_CTRL6:
504 case RT5677_DRC1_HL_CTRL1:
505 case RT5677_DRC1_HL_CTRL2:
506 case RT5677_DRC2_HL_CTRL1:
507 case RT5677_DRC2_HL_CTRL2:
508 case RT5677_DSP_INB1_SRC_CTRL1:
509 case RT5677_DSP_INB1_SRC_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL3:
511 case RT5677_DSP_INB1_SRC_CTRL4:
512 case RT5677_DSP_INB2_SRC_CTRL1:
513 case RT5677_DSP_INB2_SRC_CTRL2:
514 case RT5677_DSP_INB2_SRC_CTRL3:
515 case RT5677_DSP_INB2_SRC_CTRL4:
516 case RT5677_DSP_INB3_SRC_CTRL1:
517 case RT5677_DSP_INB3_SRC_CTRL2:
518 case RT5677_DSP_INB3_SRC_CTRL3:
519 case RT5677_DSP_INB3_SRC_CTRL4:
520 case RT5677_DSP_OUTB1_SRC_CTRL1:
521 case RT5677_DSP_OUTB1_SRC_CTRL2:
522 case RT5677_DSP_OUTB1_SRC_CTRL3:
523 case RT5677_DSP_OUTB1_SRC_CTRL4:
524 case RT5677_DSP_OUTB2_SRC_CTRL1:
525 case RT5677_DSP_OUTB2_SRC_CTRL2:
526 case RT5677_DSP_OUTB2_SRC_CTRL3:
527 case RT5677_DSP_OUTB2_SRC_CTRL4:
528 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
529 case RT5677_DSP_OUTB_45_MIXER_CTRL:
530 case RT5677_DSP_OUTB_67_MIXER_CTRL:
531 case RT5677_DIG_MISC:
532 case RT5677_GEN_CTRL1:
533 case RT5677_GEN_CTRL2:
534 case RT5677_VENDOR_ID:
535 case RT5677_VENDOR_ID1:
536 case RT5677_VENDOR_ID2:
544 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
545 * @rt5677: Private Data.
546 * @addr: Address index.
547 * @value: Address data.
550 * Returns 0 for success or negative error code.
552 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
553 unsigned int addr, unsigned int value, unsigned int opcode)
555 struct snd_soc_codec *codec = rt5677->codec;
558 mutex_lock(&rt5677->dsp_cmd_lock);
560 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
563 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
567 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
570 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
574 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
577 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
581 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
584 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
588 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
591 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
596 mutex_unlock(&rt5677->dsp_cmd_lock);
602 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
603 * rt5677: Private Data.
604 * @addr: Address index.
605 * @value: Address data.
608 * Returns 0 for success or negative error code.
610 static int rt5677_dsp_mode_i2c_read_addr(
611 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
613 struct snd_soc_codec *codec = rt5677->codec;
615 unsigned int msb, lsb;
617 mutex_lock(&rt5677->dsp_cmd_lock);
619 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
622 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
626 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
629 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
633 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
636 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
640 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
641 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
642 *value = (msb << 16) | lsb;
645 mutex_unlock(&rt5677->dsp_cmd_lock);
651 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
652 * rt5677: Private Data.
653 * @reg: Register index.
654 * @value: Register data.
657 * Returns 0 for success or negative error code.
659 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
660 unsigned int reg, unsigned int value)
662 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
667 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
668 * @codec: SoC audio codec device.
669 * @reg: Register index.
670 * @value: Register data.
673 * Returns 0 for success or negative error code.
675 static int rt5677_dsp_mode_i2c_read(
676 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
678 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
686 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
688 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
691 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
692 rt5677->is_dsp_mode = true;
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
695 rt5677->is_dsp_mode = false;
699 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
701 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
702 static bool activity;
705 if (on && !activity) {
708 regcache_cache_only(rt5677->regmap, false);
709 regcache_cache_bypass(rt5677->regmap, true);
711 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
712 regmap_update_bits(rt5677->regmap,
713 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
714 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
715 RT5677_LDO1_SEL_MASK, 0x0);
716 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
717 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
718 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
719 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
720 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
721 RT5677_PLL2_PR_SRC_MASK | RT5677_DSP_CLK_SRC_MASK,
722 RT5677_PLL2_PR_SRC_MCLK2 | RT5677_DSP_CLK_SRC_BYPASS);
723 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
724 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
725 rt5677_set_dsp_mode(codec, true);
727 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
730 rt5677_spi_burst_write(0x50000000, rt5677->fw1);
731 release_firmware(rt5677->fw1);
734 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
737 rt5677_spi_burst_write(0x60000000, rt5677->fw2);
738 release_firmware(rt5677->fw2);
741 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
743 regcache_cache_bypass(rt5677->regmap, false);
744 regcache_cache_only(rt5677->regmap, true);
745 } else if (!on && activity) {
748 regcache_cache_only(rt5677->regmap, false);
749 regcache_cache_bypass(rt5677->regmap, true);
751 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
752 rt5677_set_dsp_mode(codec, false);
753 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
755 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
757 regcache_cache_bypass(rt5677->regmap, false);
758 regcache_mark_dirty(rt5677->regmap);
759 regcache_sync(rt5677->regmap);
765 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
766 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
767 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
768 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
769 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
770 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
772 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
773 static unsigned int bst_tlv[] = {
774 TLV_DB_RANGE_HEAD(7),
775 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
776 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
777 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
778 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
779 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
780 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
781 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
784 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
785 struct snd_ctl_elem_value *ucontrol)
787 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
788 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
790 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
795 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
796 struct snd_ctl_elem_value *ucontrol)
798 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
799 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
801 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
803 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
804 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
809 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
811 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
812 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
813 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
814 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
815 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
816 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
818 /* DAC Digital Volume */
819 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
820 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
821 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
822 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
823 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
824 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
825 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
826 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
828 /* IN1/IN2 Control */
829 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
830 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
832 /* ADC Digital Volume Control */
833 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
834 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
835 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
836 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
837 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
838 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
839 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
840 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
841 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
842 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
844 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
845 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
847 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
848 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
850 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
851 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
853 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
854 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
856 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
857 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
860 /* Sidetone Control */
861 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
862 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
864 /* ADC Boost Volume Control */
865 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
866 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
868 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
869 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
871 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
872 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
874 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
875 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
877 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
878 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
881 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
882 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
886 * set_dmic_clk - Set parameter of dmic.
889 * @kcontrol: The kcontrol of this widget.
892 * Choose dmic clock between 1MHz and 3MHz.
893 * It is better for clock to approximate 3MHz.
895 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
896 struct snd_kcontrol *kcontrol, int event)
898 struct snd_soc_codec *codec = w->codec;
899 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
900 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
903 dev_err(codec->dev, "Failed to set DMIC clock\n");
905 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
906 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
910 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
911 struct snd_soc_dapm_widget *sink)
913 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
916 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
917 val &= RT5677_SCLK_SRC_MASK;
918 if (val == RT5677_SCLK_SRC_PLL1)
924 static int is_using_asrc(struct snd_soc_dapm_widget *source,
925 struct snd_soc_dapm_widget *sink)
927 unsigned int reg, shift, val;
929 if (source->reg == RT5677_ASRC_1) {
930 switch (source->shift) {
951 switch (source->shift) {
993 val = (snd_soc_read(source->codec, reg) >> shift) & 0xf;
1003 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1004 struct snd_soc_dapm_widget *sink)
1006 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1007 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1009 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1016 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1017 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1018 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1019 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1020 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1023 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1024 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1025 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1026 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1027 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1030 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1031 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1032 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1033 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1034 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1037 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1038 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1039 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1040 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1041 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1044 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1045 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1046 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1047 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1048 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1051 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1052 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1053 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1054 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1055 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1058 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1059 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1060 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1061 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1062 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1065 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1066 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1067 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1068 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1069 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1072 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1073 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1074 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1075 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1076 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1079 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1080 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1081 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1082 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1083 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1086 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1087 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1088 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1089 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1090 RT5677_M_DAC1_L_SFT, 1, 1),
1093 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1094 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1095 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1096 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1097 RT5677_M_DAC1_R_SFT, 1, 1),
1100 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1101 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1102 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1103 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1104 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1105 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1106 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1107 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1108 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1111 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1112 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1113 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1114 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1115 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1116 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1117 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1118 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1119 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1122 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1123 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1124 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1125 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1126 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1127 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1128 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1129 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1130 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1133 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1134 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1135 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1136 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1137 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1138 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1139 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1140 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1141 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1144 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1145 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1146 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1147 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1148 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1149 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1150 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1151 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1152 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1155 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1156 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1157 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1158 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1159 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1160 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1161 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1162 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1163 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1166 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1167 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1168 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1169 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1170 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1171 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1172 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1173 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1174 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1177 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1178 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1179 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1180 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1181 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1182 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1183 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1184 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1185 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1188 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1189 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1190 RT5677_DSP_IB_01_H_SFT, 1, 1),
1191 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1192 RT5677_DSP_IB_23_H_SFT, 1, 1),
1193 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1194 RT5677_DSP_IB_45_H_SFT, 1, 1),
1195 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1196 RT5677_DSP_IB_6_H_SFT, 1, 1),
1197 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1198 RT5677_DSP_IB_7_H_SFT, 1, 1),
1199 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1200 RT5677_DSP_IB_8_H_SFT, 1, 1),
1201 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1202 RT5677_DSP_IB_9_H_SFT, 1, 1),
1205 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1206 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1207 RT5677_DSP_IB_01_L_SFT, 1, 1),
1208 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1209 RT5677_DSP_IB_23_L_SFT, 1, 1),
1210 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1211 RT5677_DSP_IB_45_L_SFT, 1, 1),
1212 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1213 RT5677_DSP_IB_6_L_SFT, 1, 1),
1214 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1215 RT5677_DSP_IB_7_L_SFT, 1, 1),
1216 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1217 RT5677_DSP_IB_8_L_SFT, 1, 1),
1218 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1219 RT5677_DSP_IB_9_L_SFT, 1, 1),
1222 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1223 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1224 RT5677_DSP_IB_01_H_SFT, 1, 1),
1225 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1226 RT5677_DSP_IB_23_H_SFT, 1, 1),
1227 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1228 RT5677_DSP_IB_45_H_SFT, 1, 1),
1229 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1230 RT5677_DSP_IB_6_H_SFT, 1, 1),
1231 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1232 RT5677_DSP_IB_7_H_SFT, 1, 1),
1233 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1234 RT5677_DSP_IB_8_H_SFT, 1, 1),
1235 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1236 RT5677_DSP_IB_9_H_SFT, 1, 1),
1239 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1240 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1241 RT5677_DSP_IB_01_L_SFT, 1, 1),
1242 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1243 RT5677_DSP_IB_23_L_SFT, 1, 1),
1244 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1245 RT5677_DSP_IB_45_L_SFT, 1, 1),
1246 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1247 RT5677_DSP_IB_6_L_SFT, 1, 1),
1248 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1249 RT5677_DSP_IB_7_L_SFT, 1, 1),
1250 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1251 RT5677_DSP_IB_8_L_SFT, 1, 1),
1252 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1253 RT5677_DSP_IB_9_L_SFT, 1, 1),
1256 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1257 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1258 RT5677_DSP_IB_01_H_SFT, 1, 1),
1259 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1260 RT5677_DSP_IB_23_H_SFT, 1, 1),
1261 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1262 RT5677_DSP_IB_45_H_SFT, 1, 1),
1263 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1264 RT5677_DSP_IB_6_H_SFT, 1, 1),
1265 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1266 RT5677_DSP_IB_7_H_SFT, 1, 1),
1267 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1268 RT5677_DSP_IB_8_H_SFT, 1, 1),
1269 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1270 RT5677_DSP_IB_9_H_SFT, 1, 1),
1273 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1274 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1275 RT5677_DSP_IB_01_L_SFT, 1, 1),
1276 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1277 RT5677_DSP_IB_23_L_SFT, 1, 1),
1278 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1279 RT5677_DSP_IB_45_L_SFT, 1, 1),
1280 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1281 RT5677_DSP_IB_6_L_SFT, 1, 1),
1282 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1283 RT5677_DSP_IB_7_L_SFT, 1, 1),
1284 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1285 RT5677_DSP_IB_8_L_SFT, 1, 1),
1286 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1287 RT5677_DSP_IB_9_L_SFT, 1, 1),
1292 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1293 static const char * const rt5677_dac1_src[] = {
1294 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1298 static SOC_ENUM_SINGLE_DECL(
1299 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1300 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1302 static const struct snd_kcontrol_new rt5677_dac1_mux =
1303 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1305 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1306 static const char * const rt5677_adda1_src[] = {
1307 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1310 static SOC_ENUM_SINGLE_DECL(
1311 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1312 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1314 static const struct snd_kcontrol_new rt5677_adda1_mux =
1315 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1318 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1319 static const char * const rt5677_dac2l_src[] = {
1320 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1324 static SOC_ENUM_SINGLE_DECL(
1325 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1326 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1328 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1329 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1331 static const char * const rt5677_dac2r_src[] = {
1332 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1333 "OB 3", "Haptic Generator", "VAD ADC"
1336 static SOC_ENUM_SINGLE_DECL(
1337 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1338 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1340 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1341 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1343 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1344 static const char * const rt5677_dac3l_src[] = {
1345 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1349 static SOC_ENUM_SINGLE_DECL(
1350 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1351 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1353 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1354 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1356 static const char * const rt5677_dac3r_src[] = {
1357 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1361 static SOC_ENUM_SINGLE_DECL(
1362 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1363 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1365 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1366 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1368 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1369 static const char * const rt5677_dac4l_src[] = {
1370 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1374 static SOC_ENUM_SINGLE_DECL(
1375 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1376 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1378 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1379 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1381 static const char * const rt5677_dac4r_src[] = {
1382 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1386 static SOC_ENUM_SINGLE_DECL(
1387 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1388 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1390 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1391 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1393 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1394 static const char * const rt5677_iob_bypass_src[] = {
1395 "Bypass", "Pass SRC"
1398 static SOC_ENUM_SINGLE_DECL(
1399 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1400 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1402 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1403 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1405 static SOC_ENUM_SINGLE_DECL(
1406 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1407 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1409 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1410 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1412 static SOC_ENUM_SINGLE_DECL(
1413 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1414 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1416 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1417 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1419 static SOC_ENUM_SINGLE_DECL(
1420 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1421 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1423 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1424 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1426 static SOC_ENUM_SINGLE_DECL(
1427 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1428 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1430 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1431 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1433 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1434 static const char * const rt5677_stereo_adc2_src[] = {
1435 "DD MIX1", "DMIC", "Stereo DAC MIX"
1438 static SOC_ENUM_SINGLE_DECL(
1439 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1440 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1442 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1443 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1445 static SOC_ENUM_SINGLE_DECL(
1446 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1447 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1449 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1450 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1452 static SOC_ENUM_SINGLE_DECL(
1453 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1454 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1456 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1457 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1459 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1460 static const char * const rt5677_dmic_src[] = {
1461 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1464 static SOC_ENUM_SINGLE_DECL(
1465 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1466 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1468 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1469 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1471 static SOC_ENUM_SINGLE_DECL(
1472 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1473 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1475 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1476 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1478 static SOC_ENUM_SINGLE_DECL(
1479 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1480 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1482 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1483 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1485 static SOC_ENUM_SINGLE_DECL(
1486 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1487 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1489 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1490 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1492 static SOC_ENUM_SINGLE_DECL(
1493 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1494 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1496 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1497 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1499 static SOC_ENUM_SINGLE_DECL(
1500 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1501 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1503 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1504 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1506 /* Stereo2 ADC Source */ /* MX-26 [0] */
1507 static const char * const rt5677_stereo2_adc_lr_src[] = {
1511 static SOC_ENUM_SINGLE_DECL(
1512 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1513 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1515 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1516 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1518 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1519 static const char * const rt5677_stereo_adc1_src[] = {
1520 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1523 static SOC_ENUM_SINGLE_DECL(
1524 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1525 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1527 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1528 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1530 static SOC_ENUM_SINGLE_DECL(
1531 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1532 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1534 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1535 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1537 static SOC_ENUM_SINGLE_DECL(
1538 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1539 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1541 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1542 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1544 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1545 static const char * const rt5677_mono_adc2_l_src[] = {
1546 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1549 static SOC_ENUM_SINGLE_DECL(
1550 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1551 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1553 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1554 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1556 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1557 static const char * const rt5677_mono_adc1_l_src[] = {
1558 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1561 static SOC_ENUM_SINGLE_DECL(
1562 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1563 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1565 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1566 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1568 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1569 static const char * const rt5677_mono_adc2_r_src[] = {
1570 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1573 static SOC_ENUM_SINGLE_DECL(
1574 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1575 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1577 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1578 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1580 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1581 static const char * const rt5677_mono_adc1_r_src[] = {
1582 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1585 static SOC_ENUM_SINGLE_DECL(
1586 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1587 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1589 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1590 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1592 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1593 static const char * const rt5677_stereo4_adc2_src[] = {
1594 "DD MIX1", "DMIC", "DD MIX2"
1597 static SOC_ENUM_SINGLE_DECL(
1598 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1599 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1601 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1602 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1605 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1606 static const char * const rt5677_stereo4_adc1_src[] = {
1607 "DD MIX1", "ADC1/2", "DD MIX2"
1610 static SOC_ENUM_SINGLE_DECL(
1611 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1612 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1614 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1615 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1617 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1618 static const char * const rt5677_inbound01_src[] = {
1619 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1623 static SOC_ENUM_SINGLE_DECL(
1624 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1625 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1627 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1628 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1630 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1631 static const char * const rt5677_inbound23_src[] = {
1632 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1633 "DAC1 FS", "IF4 DAC"
1636 static SOC_ENUM_SINGLE_DECL(
1637 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1638 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1640 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1641 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1643 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1644 static const char * const rt5677_inbound45_src[] = {
1645 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1649 static SOC_ENUM_SINGLE_DECL(
1650 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1651 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1653 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1654 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1656 /* InBound6 Source */ /* MX-A3 [2:0] */
1657 static const char * const rt5677_inbound6_src[] = {
1658 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1659 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1662 static SOC_ENUM_SINGLE_DECL(
1663 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1664 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1666 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1667 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1669 /* InBound7 Source */ /* MX-A4 [14:12] */
1670 static const char * const rt5677_inbound7_src[] = {
1671 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1672 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1675 static SOC_ENUM_SINGLE_DECL(
1676 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1677 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1679 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1680 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1682 /* InBound8 Source */ /* MX-A4 [10:8] */
1683 static const char * const rt5677_inbound8_src[] = {
1684 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1685 "MONO ADC MIX L", "DACL1 FS"
1688 static SOC_ENUM_SINGLE_DECL(
1689 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1690 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1692 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1693 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1695 /* InBound9 Source */ /* MX-A4 [6:4] */
1696 static const char * const rt5677_inbound9_src[] = {
1697 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1698 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1701 static SOC_ENUM_SINGLE_DECL(
1702 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1703 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1705 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1706 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1708 /* VAD Source */ /* MX-9F [6:4] */
1709 static const char * const rt5677_vad_src[] = {
1710 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1714 static SOC_ENUM_SINGLE_DECL(
1715 rt5677_vad_enum, RT5677_VAD_CTRL4,
1716 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1718 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1719 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1721 /* Sidetone Source */ /* MX-13 [11:9] */
1722 static const char * const rt5677_sidetone_src[] = {
1723 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1726 static SOC_ENUM_SINGLE_DECL(
1727 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1728 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1730 static const struct snd_kcontrol_new rt5677_sidetone_mux =
1731 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1733 /* DAC1/2 Source */ /* MX-15 [1:0] */
1734 static const char * const rt5677_dac12_src[] = {
1735 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1738 static SOC_ENUM_SINGLE_DECL(
1739 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1740 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1742 static const struct snd_kcontrol_new rt5677_dac12_mux =
1743 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1745 /* DAC3 Source */ /* MX-15 [5:4] */
1746 static const char * const rt5677_dac3_src[] = {
1747 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1750 static SOC_ENUM_SINGLE_DECL(
1751 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1752 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1754 static const struct snd_kcontrol_new rt5677_dac3_mux =
1755 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1757 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1758 static const char * const rt5677_pdm_src[] = {
1759 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1762 static SOC_ENUM_SINGLE_DECL(
1763 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1764 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1766 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1767 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
1769 static SOC_ENUM_SINGLE_DECL(
1770 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1771 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1773 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1774 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
1776 static SOC_ENUM_SINGLE_DECL(
1777 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1778 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1780 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1781 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
1783 static SOC_ENUM_SINGLE_DECL(
1784 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1785 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1787 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1788 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
1790 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
1791 static const char * const rt5677_if12_adc1_src[] = {
1792 "STO1 ADC MIX", "OB01", "VAD ADC"
1795 static SOC_ENUM_SINGLE_DECL(
1796 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1797 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1799 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1800 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
1802 static SOC_ENUM_SINGLE_DECL(
1803 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1804 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1806 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1807 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
1809 static SOC_ENUM_SINGLE_DECL(
1810 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1811 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1813 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1814 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
1816 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1817 static const char * const rt5677_if12_adc2_src[] = {
1818 "STO2 ADC MIX", "OB23"
1821 static SOC_ENUM_SINGLE_DECL(
1822 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1823 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1825 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1826 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
1828 static SOC_ENUM_SINGLE_DECL(
1829 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1830 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1832 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1833 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
1835 static SOC_ENUM_SINGLE_DECL(
1836 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1837 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1839 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1840 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
1842 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1843 static const char * const rt5677_if12_adc3_src[] = {
1844 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1847 static SOC_ENUM_SINGLE_DECL(
1848 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1849 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1851 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1852 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
1854 static SOC_ENUM_SINGLE_DECL(
1855 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1856 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1858 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1859 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
1861 static SOC_ENUM_SINGLE_DECL(
1862 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1863 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1865 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1866 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
1868 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1869 static const char * const rt5677_if12_adc4_src[] = {
1870 "STO4 ADC MIX", "OB67", "OB01"
1873 static SOC_ENUM_SINGLE_DECL(
1874 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1875 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1877 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1878 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
1880 static SOC_ENUM_SINGLE_DECL(
1881 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1882 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1884 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1885 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
1887 static SOC_ENUM_SINGLE_DECL(
1888 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1889 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1891 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1892 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
1894 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
1895 static const char * const rt5677_if34_adc_src[] = {
1896 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1897 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1900 static SOC_ENUM_SINGLE_DECL(
1901 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1902 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1904 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1905 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
1907 static SOC_ENUM_SINGLE_DECL(
1908 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1909 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1911 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1912 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
1914 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
1915 static const char * const rt5677_if12_adc_swap_src[] = {
1916 "L/R", "R/L", "L/L", "R/R"
1919 static SOC_ENUM_SINGLE_DECL(
1920 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
1921 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
1923 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
1924 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
1926 static SOC_ENUM_SINGLE_DECL(
1927 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
1928 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1930 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
1931 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
1933 static SOC_ENUM_SINGLE_DECL(
1934 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
1935 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1937 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
1938 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
1940 static SOC_ENUM_SINGLE_DECL(
1941 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
1942 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1944 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
1945 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
1947 static SOC_ENUM_SINGLE_DECL(
1948 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
1949 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1951 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
1952 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
1954 static SOC_ENUM_SINGLE_DECL(
1955 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
1956 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
1958 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
1959 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
1961 static SOC_ENUM_SINGLE_DECL(
1962 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
1963 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
1965 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
1966 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
1968 static SOC_ENUM_SINGLE_DECL(
1969 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
1970 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
1972 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
1973 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
1975 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
1976 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
1977 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1978 "3/1/2/4", "3/4/1/2"
1981 static SOC_ENUM_SINGLE_DECL(
1982 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
1983 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
1985 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
1986 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
1988 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
1989 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
1990 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
1991 "2/3/1/4", "3/4/1/2"
1994 static SOC_ENUM_SINGLE_DECL(
1995 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
1996 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
1998 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
1999 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2001 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2002 MX-3F[14:12][10:8][6:4][2:0]
2003 MX-43[14:12][10:8][6:4][2:0]
2004 MX-44[14:12][10:8][6:4][2:0] */
2005 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2006 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2009 static SOC_ENUM_SINGLE_DECL(
2010 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2011 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2013 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2014 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2016 static SOC_ENUM_SINGLE_DECL(
2017 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2018 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2020 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2021 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2023 static SOC_ENUM_SINGLE_DECL(
2024 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2025 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2027 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2028 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2030 static SOC_ENUM_SINGLE_DECL(
2031 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2032 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2034 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2035 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2037 static SOC_ENUM_SINGLE_DECL(
2038 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2039 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2041 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2042 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2044 static SOC_ENUM_SINGLE_DECL(
2045 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2046 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2048 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2049 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2051 static SOC_ENUM_SINGLE_DECL(
2052 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2053 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2055 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2056 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2058 static SOC_ENUM_SINGLE_DECL(
2059 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2060 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2062 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2063 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2065 static SOC_ENUM_SINGLE_DECL(
2066 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2067 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2069 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2070 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2072 static SOC_ENUM_SINGLE_DECL(
2073 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2074 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2076 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2077 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2079 static SOC_ENUM_SINGLE_DECL(
2080 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2081 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2083 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2084 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2086 static SOC_ENUM_SINGLE_DECL(
2087 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2088 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2090 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2091 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2093 static SOC_ENUM_SINGLE_DECL(
2094 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2095 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2097 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2098 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2100 static SOC_ENUM_SINGLE_DECL(
2101 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2102 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2104 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2105 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2107 static SOC_ENUM_SINGLE_DECL(
2108 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2109 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2111 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2112 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2114 static SOC_ENUM_SINGLE_DECL(
2115 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2116 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2118 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2119 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2121 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2122 struct snd_kcontrol *kcontrol, int event)
2124 struct snd_soc_codec *codec = w->codec;
2125 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2128 case SND_SOC_DAPM_POST_PMU:
2129 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2130 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2133 case SND_SOC_DAPM_PRE_PMD:
2134 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2135 RT5677_PWR_BST1_P, 0);
2145 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2146 struct snd_kcontrol *kcontrol, int event)
2148 struct snd_soc_codec *codec = w->codec;
2149 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2152 case SND_SOC_DAPM_POST_PMU:
2153 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2154 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2157 case SND_SOC_DAPM_PRE_PMD:
2158 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2159 RT5677_PWR_BST2_P, 0);
2169 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2170 struct snd_kcontrol *kcontrol, int event)
2172 struct snd_soc_codec *codec = w->codec;
2173 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2176 case SND_SOC_DAPM_POST_PMU:
2177 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2178 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2187 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2188 struct snd_kcontrol *kcontrol, int event)
2190 struct snd_soc_codec *codec = w->codec;
2191 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2194 case SND_SOC_DAPM_POST_PMU:
2195 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2196 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2205 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2206 struct snd_kcontrol *kcontrol, int event)
2208 struct snd_soc_codec *codec = w->codec;
2209 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2212 case SND_SOC_DAPM_POST_PMU:
2213 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2214 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2215 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2216 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2219 case SND_SOC_DAPM_PRE_PMD:
2220 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2221 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2222 RT5677_PWR_CLK_MB, 0);
2232 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2233 struct snd_kcontrol *kcontrol, int event)
2235 struct snd_soc_codec *codec = w->codec;
2236 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2240 case SND_SOC_DAPM_PRE_PMU:
2241 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2242 if (value & RT5677_IF1_ADC_CTRL_MASK)
2243 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2244 RT5677_IF1_ADC_MODE_MASK,
2245 RT5677_IF1_ADC_MODE_TDM);
2255 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2256 struct snd_kcontrol *kcontrol, int event)
2258 struct snd_soc_codec *codec = w->codec;
2259 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2263 case SND_SOC_DAPM_PRE_PMU:
2264 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2265 if (value & RT5677_IF2_ADC_CTRL_MASK)
2266 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2267 RT5677_IF2_ADC_MODE_MASK,
2268 RT5677_IF2_ADC_MODE_TDM);
2278 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2279 struct snd_kcontrol *kcontrol, int event)
2281 struct snd_soc_codec *codec = w->codec;
2282 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2285 case SND_SOC_DAPM_POST_PMU:
2286 if (codec->dapm.bias_level != SND_SOC_BIAS_ON &&
2287 !rt5677->is_vref_slow) {
2289 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2290 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2291 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2292 rt5677->is_vref_slow = true;
2303 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2304 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2305 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
2306 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2307 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
2310 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2311 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2312 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2313 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2314 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2315 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2317 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2319 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2321 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2323 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2325 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2327 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2329 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2331 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2333 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2335 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2337 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2339 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2340 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2341 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2342 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2343 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2345 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2350 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2351 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2352 SND_SOC_DAPM_POST_PMU),
2355 SND_SOC_DAPM_INPUT("DMIC L1"),
2356 SND_SOC_DAPM_INPUT("DMIC R1"),
2357 SND_SOC_DAPM_INPUT("DMIC L2"),
2358 SND_SOC_DAPM_INPUT("DMIC R2"),
2359 SND_SOC_DAPM_INPUT("DMIC L3"),
2360 SND_SOC_DAPM_INPUT("DMIC R3"),
2361 SND_SOC_DAPM_INPUT("DMIC L4"),
2362 SND_SOC_DAPM_INPUT("DMIC R4"),
2364 SND_SOC_DAPM_INPUT("IN1P"),
2365 SND_SOC_DAPM_INPUT("IN1N"),
2366 SND_SOC_DAPM_INPUT("IN2P"),
2367 SND_SOC_DAPM_INPUT("IN2N"),
2369 SND_SOC_DAPM_INPUT("Haptic Generator"),
2371 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2372 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2373 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2374 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2376 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2377 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2378 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2379 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2380 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2381 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2382 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2383 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2385 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2386 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2389 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2390 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2391 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2392 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2393 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2394 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2397 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2399 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2401 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2403 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2404 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2405 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2406 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2407 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2408 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2409 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2410 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2413 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2414 &rt5677_sto1_dmic_mux),
2415 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2416 &rt5677_sto1_adc1_mux),
2417 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2418 &rt5677_sto1_adc2_mux),
2419 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2420 &rt5677_sto2_dmic_mux),
2421 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2422 &rt5677_sto2_adc1_mux),
2423 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2424 &rt5677_sto2_adc2_mux),
2425 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2426 &rt5677_sto2_adc_lr_mux),
2427 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2428 &rt5677_sto3_dmic_mux),
2429 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2430 &rt5677_sto3_adc1_mux),
2431 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2432 &rt5677_sto3_adc2_mux),
2433 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2434 &rt5677_sto4_dmic_mux),
2435 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2436 &rt5677_sto4_adc1_mux),
2437 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2438 &rt5677_sto4_adc2_mux),
2439 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2440 &rt5677_mono_dmic_l_mux),
2441 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2442 &rt5677_mono_dmic_r_mux),
2443 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2444 &rt5677_mono_adc2_l_mux),
2445 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2446 &rt5677_mono_adc1_l_mux),
2447 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2448 &rt5677_mono_adc1_r_mux),
2449 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2450 &rt5677_mono_adc2_r_mux),
2453 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2454 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2455 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2456 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2457 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2458 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2459 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2460 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2461 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2462 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2463 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2464 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2465 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2466 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2467 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2468 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2469 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2470 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2471 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2472 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2473 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2474 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2475 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2476 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2477 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2478 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2479 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2480 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2481 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2482 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2483 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2484 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2487 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2488 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2489 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2490 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2491 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2492 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2493 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2494 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2495 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2496 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2497 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2498 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2499 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2500 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2501 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2502 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2505 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2506 &rt5677_ib9_src_mux),
2507 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2508 &rt5677_ib8_src_mux),
2509 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2510 &rt5677_ib7_src_mux),
2511 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2512 &rt5677_ib6_src_mux),
2513 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2514 &rt5677_ib45_src_mux),
2515 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2516 &rt5677_ib23_src_mux),
2517 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2518 &rt5677_ib01_src_mux),
2519 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2520 &rt5677_ib45_bypass_src_mux),
2521 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2522 &rt5677_ib23_bypass_src_mux),
2523 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2524 &rt5677_ib01_bypass_src_mux),
2525 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2526 &rt5677_ob23_bypass_src_mux),
2527 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2528 &rt5677_ob01_bypass_src_mux),
2530 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2531 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2533 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2534 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2535 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2536 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2537 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2538 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2540 /* Digital Interface */
2541 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2542 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2543 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2544 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2545 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2546 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2547 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2548 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2549 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2550 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2551 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2552 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2553 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2554 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2555 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2556 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2557 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2558 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2560 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2561 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2562 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2563 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2564 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2565 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2566 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2567 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2568 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2569 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2570 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2571 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2572 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2573 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2574 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2575 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2576 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2577 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2579 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2580 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2581 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2582 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2583 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2584 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2585 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2586 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2588 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2589 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2590 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2591 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2592 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2593 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2594 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2595 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2597 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2598 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2599 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2600 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2601 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2602 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2603 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2604 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2605 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2606 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2607 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2608 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2609 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2610 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2611 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2612 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2613 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2614 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2616 /* Digital Interface Select */
2617 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2618 &rt5677_if1_adc1_mux),
2619 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2620 &rt5677_if1_adc2_mux),
2621 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2622 &rt5677_if1_adc3_mux),
2623 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2624 &rt5677_if1_adc4_mux),
2625 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2626 &rt5677_if1_adc1_swap_mux),
2627 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2628 &rt5677_if1_adc2_swap_mux),
2629 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2630 &rt5677_if1_adc3_swap_mux),
2631 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2632 &rt5677_if1_adc4_swap_mux),
2633 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2634 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2635 SND_SOC_DAPM_PRE_PMU),
2636 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2637 &rt5677_if2_adc1_mux),
2638 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2639 &rt5677_if2_adc2_mux),
2640 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2641 &rt5677_if2_adc3_mux),
2642 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2643 &rt5677_if2_adc4_mux),
2644 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2645 &rt5677_if2_adc1_swap_mux),
2646 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2647 &rt5677_if2_adc2_swap_mux),
2648 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2649 &rt5677_if2_adc3_swap_mux),
2650 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2651 &rt5677_if2_adc4_swap_mux),
2652 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2653 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2654 SND_SOC_DAPM_PRE_PMU),
2655 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2656 &rt5677_if3_adc_mux),
2657 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2658 &rt5677_if4_adc_mux),
2659 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2660 &rt5677_slb_adc1_mux),
2661 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2662 &rt5677_slb_adc2_mux),
2663 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2664 &rt5677_slb_adc3_mux),
2665 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2666 &rt5677_slb_adc4_mux),
2668 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2669 &rt5677_if1_dac0_tdm_sel_mux),
2670 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2671 &rt5677_if1_dac1_tdm_sel_mux),
2672 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2673 &rt5677_if1_dac2_tdm_sel_mux),
2674 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2675 &rt5677_if1_dac3_tdm_sel_mux),
2676 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2677 &rt5677_if1_dac4_tdm_sel_mux),
2678 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2679 &rt5677_if1_dac5_tdm_sel_mux),
2680 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2681 &rt5677_if1_dac6_tdm_sel_mux),
2682 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2683 &rt5677_if1_dac7_tdm_sel_mux),
2685 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2686 &rt5677_if2_dac0_tdm_sel_mux),
2687 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2688 &rt5677_if2_dac1_tdm_sel_mux),
2689 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2690 &rt5677_if2_dac2_tdm_sel_mux),
2691 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2692 &rt5677_if2_dac3_tdm_sel_mux),
2693 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2694 &rt5677_if2_dac4_tdm_sel_mux),
2695 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2696 &rt5677_if2_dac5_tdm_sel_mux),
2697 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2698 &rt5677_if2_dac6_tdm_sel_mux),
2699 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2700 &rt5677_if2_dac7_tdm_sel_mux),
2702 /* Audio Interface */
2703 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2704 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2705 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2706 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2707 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2708 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2709 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
2710 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
2711 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
2712 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
2715 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
2716 &rt5677_sidetone_mux),
2717 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
2718 RT5677_ST_EN_SFT, 0, NULL, 0),
2721 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
2722 &rt5677_vad_src_mux),
2725 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2726 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2727 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2728 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2729 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2730 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2731 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2732 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2733 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2734 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2735 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2736 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2737 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2740 /* DAC mixer before sound effect */
2741 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2742 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2743 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2744 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2745 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2748 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2750 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2752 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2754 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2757 /* DAC2 channel Mux */
2758 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2759 &rt5677_dac2_l_mux),
2760 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2761 &rt5677_dac2_r_mux),
2763 /* DAC3 channel Mux */
2764 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2765 &rt5677_dac3_l_mux),
2766 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2767 &rt5677_dac3_r_mux),
2769 /* DAC4 channel Mux */
2770 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2771 &rt5677_dac4_l_mux),
2772 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2773 &rt5677_dac4_r_mux),
2776 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2777 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2778 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
2779 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2780 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
2781 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2782 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
2783 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
2784 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
2785 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
2786 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
2787 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
2788 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
2789 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
2791 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2792 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2793 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2794 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2795 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2796 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2797 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2798 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2799 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2800 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2801 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2802 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2803 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2804 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2805 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2806 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2807 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2808 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2809 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2810 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2813 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2814 RT5677_PWR_DAC1_BIT, 0),
2815 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2816 RT5677_PWR_DAC2_BIT, 0),
2817 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2818 RT5677_PWR_DAC3_BIT, 0),
2821 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2822 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2823 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2824 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2826 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2827 1, &rt5677_pdm1_l_mux),
2828 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2829 1, &rt5677_pdm1_r_mux),
2830 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2831 1, &rt5677_pdm2_l_mux),
2832 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2833 1, &rt5677_pdm2_r_mux),
2835 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2837 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2839 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2842 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
2843 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2844 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
2845 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2846 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
2847 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
2850 SND_SOC_DAPM_OUTPUT("LOUT1"),
2851 SND_SOC_DAPM_OUTPUT("LOUT2"),
2852 SND_SOC_DAPM_OUTPUT("LOUT3"),
2853 SND_SOC_DAPM_OUTPUT("PDM1L"),
2854 SND_SOC_DAPM_OUTPUT("PDM1R"),
2855 SND_SOC_DAPM_OUTPUT("PDM2L"),
2856 SND_SOC_DAPM_OUTPUT("PDM2R"),
2858 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
2861 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2862 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", can_use_asrc },
2863 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", can_use_asrc },
2864 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", can_use_asrc },
2865 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", can_use_asrc },
2866 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", can_use_asrc },
2867 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", can_use_asrc },
2868 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
2869 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
2870 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
2871 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
2873 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2874 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
2875 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
2876 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
2877 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
2878 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
2879 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
2880 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2881 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
2882 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
2883 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
2884 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2885 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2887 { "DMIC1", NULL, "DMIC L1" },
2888 { "DMIC1", NULL, "DMIC R1" },
2889 { "DMIC2", NULL, "DMIC L2" },
2890 { "DMIC2", NULL, "DMIC R2" },
2891 { "DMIC3", NULL, "DMIC L3" },
2892 { "DMIC3", NULL, "DMIC R3" },
2893 { "DMIC4", NULL, "DMIC L4" },
2894 { "DMIC4", NULL, "DMIC R4" },
2896 { "DMIC L1", NULL, "DMIC CLK" },
2897 { "DMIC R1", NULL, "DMIC CLK" },
2898 { "DMIC L2", NULL, "DMIC CLK" },
2899 { "DMIC R2", NULL, "DMIC CLK" },
2900 { "DMIC L3", NULL, "DMIC CLK" },
2901 { "DMIC R3", NULL, "DMIC CLK" },
2902 { "DMIC L4", NULL, "DMIC CLK" },
2903 { "DMIC R4", NULL, "DMIC CLK" },
2905 { "DMIC L1", NULL, "DMIC1 power" },
2906 { "DMIC R1", NULL, "DMIC1 power" },
2907 { "DMIC L3", NULL, "DMIC3 power" },
2908 { "DMIC R3", NULL, "DMIC3 power" },
2909 { "DMIC L4", NULL, "DMIC4 power" },
2910 { "DMIC R4", NULL, "DMIC4 power" },
2912 { "BST1", NULL, "IN1P" },
2913 { "BST1", NULL, "IN1N" },
2914 { "BST2", NULL, "IN2P" },
2915 { "BST2", NULL, "IN2N" },
2917 { "IN1P", NULL, "MICBIAS1" },
2918 { "IN1N", NULL, "MICBIAS1" },
2919 { "IN2P", NULL, "MICBIAS1" },
2920 { "IN2N", NULL, "MICBIAS1" },
2922 { "ADC 1", NULL, "BST1" },
2923 { "ADC 1", NULL, "ADC 1 power" },
2924 { "ADC 1", NULL, "ADC1 clock" },
2925 { "ADC 2", NULL, "BST2" },
2926 { "ADC 2", NULL, "ADC 2 power" },
2927 { "ADC 2", NULL, "ADC2 clock" },
2929 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2930 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2931 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2932 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2934 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2935 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2936 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2937 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2939 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2940 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2941 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2942 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2944 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2945 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2946 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2947 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2949 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2950 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2951 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2952 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2954 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2955 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2956 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2957 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2959 { "ADC 1_2", NULL, "ADC 1" },
2960 { "ADC 1_2", NULL, "ADC 2" },
2962 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2963 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2964 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2966 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2967 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2968 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2970 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2971 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2972 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2974 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2975 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2976 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2978 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2979 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2980 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2982 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2983 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2984 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2986 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2987 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2988 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2990 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2991 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2992 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2994 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2995 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2996 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2998 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2999 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3000 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3002 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3003 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3004 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3006 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3007 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3008 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3010 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3011 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3012 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3013 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3015 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3016 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3017 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3018 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3019 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3021 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3022 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3024 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3025 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3026 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3027 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3029 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3030 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3032 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3033 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3035 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3036 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3037 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3038 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3039 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3041 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3042 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3044 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3045 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3046 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3047 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3049 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3050 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3051 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3052 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3053 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3055 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3056 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3058 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3059 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3060 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3061 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3063 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3064 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3065 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3066 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3067 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3069 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3070 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3072 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3073 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3074 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3075 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3077 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3078 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3079 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3080 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3082 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3083 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3085 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3086 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3087 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3088 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3089 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3091 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3092 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3093 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3095 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3096 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3098 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3099 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3100 { "IF1 ADC3 Mux", "OB45", "OB45" },
3102 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3103 { "IF1 ADC4 Mux", "OB67", "OB67" },
3104 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3106 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3107 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3108 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3109 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3111 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3112 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3113 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3114 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3116 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3117 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3118 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3119 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3121 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3122 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3123 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3124 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3126 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3127 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3128 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3129 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3131 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3132 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3133 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3134 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3135 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3136 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3137 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3138 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3140 { "AIF1TX", NULL, "I2S1" },
3141 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3143 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3144 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3145 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3147 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3148 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3150 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3151 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3152 { "IF2 ADC3 Mux", "OB45", "OB45" },
3154 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3155 { "IF2 ADC4 Mux", "OB67", "OB67" },
3156 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3158 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3159 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3160 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3161 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3163 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3164 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3165 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3166 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3168 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3169 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3170 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3171 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3173 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3174 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3175 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3176 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3178 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3179 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3180 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3181 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3183 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3184 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3185 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3186 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3187 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3188 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3189 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3190 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3192 { "AIF2TX", NULL, "I2S2" },
3193 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3195 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3196 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3197 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3198 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3199 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3200 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3201 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3202 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3204 { "AIF3TX", NULL, "I2S3" },
3205 { "AIF3TX", NULL, "IF3 ADC Mux" },
3207 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3208 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3209 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3210 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3211 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3212 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3213 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3214 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3216 { "AIF4TX", NULL, "I2S4" },
3217 { "AIF4TX", NULL, "IF4 ADC Mux" },
3219 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3220 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3221 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3223 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3224 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3226 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3227 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3228 { "SLB ADC3 Mux", "OB45", "OB45" },
3230 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3231 { "SLB ADC4 Mux", "OB67", "OB67" },
3232 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3234 { "SLBTX", NULL, "SLB" },
3235 { "SLBTX", NULL, "SLB ADC1 Mux" },
3236 { "SLBTX", NULL, "SLB ADC2 Mux" },
3237 { "SLBTX", NULL, "SLB ADC3 Mux" },
3238 { "SLBTX", NULL, "SLB ADC4 Mux" },
3240 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3241 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3242 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3243 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3244 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3246 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3247 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3249 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3250 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3251 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3252 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3253 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3254 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3256 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3257 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3259 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3260 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3261 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3262 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3263 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3265 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3266 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3268 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
3269 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
3270 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3271 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3272 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3273 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3274 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3275 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3277 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
3278 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
3279 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3280 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3281 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3282 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3283 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3284 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3286 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3287 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3288 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3289 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3290 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3291 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3293 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3294 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3295 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3296 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3297 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3298 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3299 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3301 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3302 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3303 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3304 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3305 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3306 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3307 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3309 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3310 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3311 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3312 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3313 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3314 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3315 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3317 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3318 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3319 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3320 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3321 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3322 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3323 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3325 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3326 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3327 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3328 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3329 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3330 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3331 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3333 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3334 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3335 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3336 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3337 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3338 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3339 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3341 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3342 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3343 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3344 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3345 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3346 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3347 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3349 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3350 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3351 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3352 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3354 { "OutBound2", NULL, "OB23 Bypass Mux" },
3355 { "OutBound3", NULL, "OB23 Bypass Mux" },
3356 { "OutBound4", NULL, "OB4 MIX" },
3357 { "OutBound5", NULL, "OB5 MIX" },
3358 { "OutBound6", NULL, "OB6 MIX" },
3359 { "OutBound7", NULL, "OB7 MIX" },
3361 { "OB45", NULL, "OutBound4" },
3362 { "OB45", NULL, "OutBound5" },
3363 { "OB67", NULL, "OutBound6" },
3364 { "OB67", NULL, "OutBound7" },
3366 { "IF1 DAC0", NULL, "AIF1RX" },
3367 { "IF1 DAC1", NULL, "AIF1RX" },
3368 { "IF1 DAC2", NULL, "AIF1RX" },
3369 { "IF1 DAC3", NULL, "AIF1RX" },
3370 { "IF1 DAC4", NULL, "AIF1RX" },
3371 { "IF1 DAC5", NULL, "AIF1RX" },
3372 { "IF1 DAC6", NULL, "AIF1RX" },
3373 { "IF1 DAC7", NULL, "AIF1RX" },
3374 { "IF1 DAC0", NULL, "I2S1" },
3375 { "IF1 DAC1", NULL, "I2S1" },
3376 { "IF1 DAC2", NULL, "I2S1" },
3377 { "IF1 DAC3", NULL, "I2S1" },
3378 { "IF1 DAC4", NULL, "I2S1" },
3379 { "IF1 DAC5", NULL, "I2S1" },
3380 { "IF1 DAC6", NULL, "I2S1" },
3381 { "IF1 DAC7", NULL, "I2S1" },
3383 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3384 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3385 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3386 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3387 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3388 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3389 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3390 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3392 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3393 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3394 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3395 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3396 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3397 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3398 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3399 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3401 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3402 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3403 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3404 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3405 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3406 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3407 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3408 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3410 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3411 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3412 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3413 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3414 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3415 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3416 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3417 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3419 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3420 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3421 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3422 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3423 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3424 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3425 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3426 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3428 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3429 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3430 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3431 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3432 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3433 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3434 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3435 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3437 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3438 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3439 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3440 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3441 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3442 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3443 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3444 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3446 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3447 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3448 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3449 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3450 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3451 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3452 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3453 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3455 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3456 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3457 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3458 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3459 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3460 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3461 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3462 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3464 { "IF2 DAC0", NULL, "AIF2RX" },
3465 { "IF2 DAC1", NULL, "AIF2RX" },
3466 { "IF2 DAC2", NULL, "AIF2RX" },
3467 { "IF2 DAC3", NULL, "AIF2RX" },
3468 { "IF2 DAC4", NULL, "AIF2RX" },
3469 { "IF2 DAC5", NULL, "AIF2RX" },
3470 { "IF2 DAC6", NULL, "AIF2RX" },
3471 { "IF2 DAC7", NULL, "AIF2RX" },
3472 { "IF2 DAC0", NULL, "I2S2" },
3473 { "IF2 DAC1", NULL, "I2S2" },
3474 { "IF2 DAC2", NULL, "I2S2" },
3475 { "IF2 DAC3", NULL, "I2S2" },
3476 { "IF2 DAC4", NULL, "I2S2" },
3477 { "IF2 DAC5", NULL, "I2S2" },
3478 { "IF2 DAC6", NULL, "I2S2" },
3479 { "IF2 DAC7", NULL, "I2S2" },
3481 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3482 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3483 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3484 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3485 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3486 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3487 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3488 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3490 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3491 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3492 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3493 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3494 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3495 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3496 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3497 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3499 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3500 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3501 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3502 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3503 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3504 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3505 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3506 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3508 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3509 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3510 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3511 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3512 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3513 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3514 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3515 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3517 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3518 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3519 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3520 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3521 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3522 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3523 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3524 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3526 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3527 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3528 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3529 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3530 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3531 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3532 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3533 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3535 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3536 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3537 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3538 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3539 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3540 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3541 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3542 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3544 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3545 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3546 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3547 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3548 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3549 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3550 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3551 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3553 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3554 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3555 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3556 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3557 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3558 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3559 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3560 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3562 { "IF3 DAC", NULL, "AIF3RX" },
3563 { "IF3 DAC", NULL, "I2S3" },
3565 { "IF4 DAC", NULL, "AIF4RX" },
3566 { "IF4 DAC", NULL, "I2S4" },
3568 { "IF3 DAC L", NULL, "IF3 DAC" },
3569 { "IF3 DAC R", NULL, "IF3 DAC" },
3571 { "IF4 DAC L", NULL, "IF4 DAC" },
3572 { "IF4 DAC R", NULL, "IF4 DAC" },
3574 { "SLB DAC0", NULL, "SLBRX" },
3575 { "SLB DAC1", NULL, "SLBRX" },
3576 { "SLB DAC2", NULL, "SLBRX" },
3577 { "SLB DAC3", NULL, "SLBRX" },
3578 { "SLB DAC4", NULL, "SLBRX" },
3579 { "SLB DAC5", NULL, "SLBRX" },
3580 { "SLB DAC6", NULL, "SLBRX" },
3581 { "SLB DAC7", NULL, "SLBRX" },
3582 { "SLB DAC0", NULL, "SLB" },
3583 { "SLB DAC1", NULL, "SLB" },
3584 { "SLB DAC2", NULL, "SLB" },
3585 { "SLB DAC3", NULL, "SLB" },
3586 { "SLB DAC4", NULL, "SLB" },
3587 { "SLB DAC5", NULL, "SLB" },
3588 { "SLB DAC6", NULL, "SLB" },
3589 { "SLB DAC7", NULL, "SLB" },
3591 { "SLB DAC01", NULL, "SLB DAC0" },
3592 { "SLB DAC01", NULL, "SLB DAC1" },
3593 { "SLB DAC23", NULL, "SLB DAC2" },
3594 { "SLB DAC23", NULL, "SLB DAC3" },
3595 { "SLB DAC45", NULL, "SLB DAC4" },
3596 { "SLB DAC45", NULL, "SLB DAC5" },
3597 { "SLB DAC67", NULL, "SLB DAC6" },
3598 { "SLB DAC67", NULL, "SLB DAC7" },
3600 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3601 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3602 { "ADDA1 Mux", "OB 67", "OB67" },
3604 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3605 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3606 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3607 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3608 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3609 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3611 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3612 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3613 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3614 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3616 { "DAC1 FS", NULL, "DAC1 MIXL" },
3617 { "DAC1 FS", NULL, "DAC1 MIXR" },
3619 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
3620 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
3621 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3622 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3623 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3624 { "DAC2 L Mux", "OB 2", "OutBound2" },
3626 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
3627 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
3628 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3629 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3630 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3631 { "DAC2 R Mux", "OB 3", "OutBound3" },
3632 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3633 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3635 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
3636 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
3637 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3638 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3639 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3640 { "DAC3 L Mux", "OB 4", "OutBound4" },
3642 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
3643 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
3644 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3645 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3646 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3647 { "DAC3 R Mux", "OB 5", "OutBound5" },
3649 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
3650 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
3651 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3652 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3653 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3654 { "DAC4 L Mux", "OB 6", "OutBound6" },
3656 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
3657 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
3658 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3659 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3660 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3661 { "DAC4 R Mux", "OB 7", "OutBound7" },
3663 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3664 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3665 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3666 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3667 { "Sidetone Mux", "ADC1", "ADC 1" },
3668 { "Sidetone Mux", "ADC2", "ADC 2" },
3669 { "Sidetone Mux", NULL, "Sidetone Power" },
3671 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3672 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3673 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3674 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3675 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3676 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3677 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3678 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3679 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3680 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3681 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3683 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3684 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3685 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3686 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3687 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3688 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3689 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3690 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3691 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3692 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3693 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3694 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3696 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3697 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3698 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3699 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3700 { "DD1 MIXL", NULL, "dac mono3 left filter" },
3701 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3702 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3703 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3704 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
3705 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
3706 { "DD1 MIXR", NULL, "dac mono3 right filter" },
3707 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3709 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3710 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3711 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
3712 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
3713 { "DD2 MIXL", NULL, "dac mono4 left filter" },
3714 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3715 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
3716 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
3717 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
3718 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
3719 { "DD2 MIXR", NULL, "dac mono4 right filter" },
3720 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3722 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
3723 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
3724 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
3725 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
3726 { "DD1 MIX", NULL, "DD1 MIXL" },
3727 { "DD1 MIX", NULL, "DD1 MIXR" },
3728 { "DD2 MIX", NULL, "DD2 MIXL" },
3729 { "DD2 MIX", NULL, "DD2 MIXR" },
3731 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
3732 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
3733 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
3734 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
3736 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3737 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3738 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
3739 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
3741 { "DAC 1", NULL, "DAC12 SRC Mux" },
3742 { "DAC 2", NULL, "DAC12 SRC Mux" },
3743 { "DAC 3", NULL, "DAC3 SRC Mux" },
3745 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3746 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3747 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
3748 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
3749 { "PDM1 L Mux", NULL, "PDM1 Power" },
3750 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3751 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3752 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
3753 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
3754 { "PDM1 R Mux", NULL, "PDM1 Power" },
3755 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
3756 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
3757 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
3758 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
3759 { "PDM2 L Mux", NULL, "PDM2 Power" },
3760 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
3761 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
3762 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
3763 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
3764 { "PDM2 R Mux", NULL, "PDM2 Power" },
3766 { "LOUT1 amp", NULL, "DAC 1" },
3767 { "LOUT2 amp", NULL, "DAC 2" },
3768 { "LOUT3 amp", NULL, "DAC 3" },
3770 { "LOUT1 vref", NULL, "LOUT1 amp" },
3771 { "LOUT2 vref", NULL, "LOUT2 amp" },
3772 { "LOUT3 vref", NULL, "LOUT3 amp" },
3774 { "LOUT1", NULL, "LOUT1 vref" },
3775 { "LOUT2", NULL, "LOUT2 vref" },
3776 { "LOUT3", NULL, "LOUT3 vref" },
3778 { "PDM1L", NULL, "PDM1 L Mux" },
3779 { "PDM1R", NULL, "PDM1 R Mux" },
3780 { "PDM2L", NULL, "PDM2 L Mux" },
3781 { "PDM2R", NULL, "PDM2 R Mux" },
3784 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
3785 { "DMIC L2", NULL, "DMIC1 power" },
3786 { "DMIC R2", NULL, "DMIC1 power" },
3789 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
3790 { "DMIC L2", NULL, "DMIC2 power" },
3791 { "DMIC R2", NULL, "DMIC2 power" },
3794 static int rt5677_hw_params(struct snd_pcm_substream *substream,
3795 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3797 struct snd_soc_codec *codec = dai->codec;
3798 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3799 unsigned int val_len = 0, val_clk, mask_clk;
3800 int pre_div, bclk_ms, frame_size;
3802 rt5677->lrck[dai->id] = params_rate(params);
3803 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
3805 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
3806 rt5677->sysclk, rt5677->lrck[dai->id]);
3809 frame_size = snd_soc_params_to_frame_size(params);
3810 if (frame_size < 0) {
3811 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3814 bclk_ms = frame_size > 32;
3815 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
3817 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
3818 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
3819 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
3820 bclk_ms, pre_div, dai->id);
3822 switch (params_width(params)) {
3826 val_len |= RT5677_I2S_DL_20;
3829 val_len |= RT5677_I2S_DL_24;
3832 val_len |= RT5677_I2S_DL_8;
3840 mask_clk = RT5677_I2S_PD1_MASK;
3841 val_clk = pre_div << RT5677_I2S_PD1_SFT;
3842 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3843 RT5677_I2S_DL_MASK, val_len);
3844 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3848 mask_clk = RT5677_I2S_PD2_MASK;
3849 val_clk = pre_div << RT5677_I2S_PD2_SFT;
3850 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3851 RT5677_I2S_DL_MASK, val_len);
3852 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3856 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
3857 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
3858 pre_div << RT5677_I2S_PD3_SFT;
3859 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3860 RT5677_I2S_DL_MASK, val_len);
3861 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3865 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
3866 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
3867 pre_div << RT5677_I2S_PD4_SFT;
3868 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3869 RT5677_I2S_DL_MASK, val_len);
3870 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
3880 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3882 struct snd_soc_codec *codec = dai->codec;
3883 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3884 unsigned int reg_val = 0;
3886 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3887 case SND_SOC_DAIFMT_CBM_CFM:
3888 rt5677->master[dai->id] = 1;
3890 case SND_SOC_DAIFMT_CBS_CFS:
3891 reg_val |= RT5677_I2S_MS_S;
3892 rt5677->master[dai->id] = 0;
3898 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3899 case SND_SOC_DAIFMT_NB_NF:
3901 case SND_SOC_DAIFMT_IB_NF:
3902 reg_val |= RT5677_I2S_BP_INV;
3908 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3909 case SND_SOC_DAIFMT_I2S:
3911 case SND_SOC_DAIFMT_LEFT_J:
3912 reg_val |= RT5677_I2S_DF_LEFT;
3914 case SND_SOC_DAIFMT_DSP_A:
3915 reg_val |= RT5677_I2S_DF_PCM_A;
3917 case SND_SOC_DAIFMT_DSP_B:
3918 reg_val |= RT5677_I2S_DF_PCM_B;
3926 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
3927 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3928 RT5677_I2S_DF_MASK, reg_val);
3931 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
3932 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3933 RT5677_I2S_DF_MASK, reg_val);
3936 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
3937 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3938 RT5677_I2S_DF_MASK, reg_val);
3941 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
3942 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
3943 RT5677_I2S_DF_MASK, reg_val);
3953 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
3954 int clk_id, unsigned int freq, int dir)
3956 struct snd_soc_codec *codec = dai->codec;
3957 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3958 unsigned int reg_val = 0;
3960 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
3964 case RT5677_SCLK_S_MCLK:
3965 reg_val |= RT5677_SCLK_SRC_MCLK;
3967 case RT5677_SCLK_S_PLL1:
3968 reg_val |= RT5677_SCLK_SRC_PLL1;
3970 case RT5677_SCLK_S_RCCLK:
3971 reg_val |= RT5677_SCLK_SRC_RCCLK;
3974 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3977 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3978 RT5677_SCLK_SRC_MASK, reg_val);
3979 rt5677->sysclk = freq;
3980 rt5677->sysclk_src = clk_id;
3982 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3988 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3989 * @freq_in: external clock provided to codec.
3990 * @freq_out: target clock which codec works on.
3991 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3993 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3995 * Returns 0 for success or negative error code.
3997 static int rt5677_pll_calc(const unsigned int freq_in,
3998 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4000 if (RT5677_PLL_INP_MIN > freq_in)
4003 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4006 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4007 unsigned int freq_in, unsigned int freq_out)
4009 struct snd_soc_codec *codec = dai->codec;
4010 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4011 struct rl6231_pll_code pll_code;
4014 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4015 freq_out == rt5677->pll_out)
4018 if (!freq_in || !freq_out) {
4019 dev_dbg(codec->dev, "PLL disabled\n");
4022 rt5677->pll_out = 0;
4023 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4024 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4029 case RT5677_PLL1_S_MCLK:
4030 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4031 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4033 case RT5677_PLL1_S_BCLK1:
4034 case RT5677_PLL1_S_BCLK2:
4035 case RT5677_PLL1_S_BCLK3:
4036 case RT5677_PLL1_S_BCLK4:
4039 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4040 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4043 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4044 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4047 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4048 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4051 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4052 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4059 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4063 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4065 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4069 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4070 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4071 pll_code.n_code, pll_code.k_code);
4073 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4074 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4075 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4076 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4077 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4079 rt5677->pll_in = freq_in;
4080 rt5677->pll_out = freq_out;
4081 rt5677->pll_src = source;
4086 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4087 unsigned int rx_mask, int slots, int slot_width)
4089 struct snd_soc_codec *codec = dai->codec;
4090 unsigned int val = 0;
4092 if (rx_mask || tx_mask)
4110 switch (slot_width) {
4127 snd_soc_update_bits(codec, RT5677_TDM1_CTRL1, 0x1f00, val);
4130 snd_soc_update_bits(codec, RT5677_TDM2_CTRL1, 0x1f00, val);
4139 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4140 enum snd_soc_bias_level level)
4142 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4145 case SND_SOC_BIAS_ON:
4148 case SND_SOC_BIAS_PREPARE:
4149 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
4150 rt5677_set_dsp_vad(codec, false);
4152 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4153 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4155 regmap_update_bits(rt5677->regmap,
4156 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4158 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4159 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4160 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4161 RT5677_PWR_BG | RT5677_PWR_VREF2,
4162 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4163 RT5677_PWR_BG | RT5677_PWR_VREF2);
4164 rt5677->is_vref_slow = false;
4165 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4166 RT5677_PWR_CORE, RT5677_PWR_CORE);
4167 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4172 case SND_SOC_BIAS_STANDBY:
4175 case SND_SOC_BIAS_OFF:
4176 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4177 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4178 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4179 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4180 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4181 regmap_update_bits(rt5677->regmap,
4182 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4184 if (rt5677->dsp_vad_en)
4185 rt5677_set_dsp_vad(codec, true);
4191 codec->dapm.bias_level = level;
4196 #ifdef CONFIG_GPIOLIB
4197 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4199 return container_of(chip, struct rt5677_priv, gpio_chip);
4202 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4204 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4207 case RT5677_GPIO1 ... RT5677_GPIO5:
4208 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4209 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4213 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4214 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4222 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4223 unsigned offset, int value)
4225 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4228 case RT5677_GPIO1 ... RT5677_GPIO5:
4229 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4230 0x3 << (offset * 3 + 1),
4231 (0x2 | !!value) << (offset * 3 + 1));
4235 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4236 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4237 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4247 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4249 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4252 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4256 return (value & (0x1 << offset)) >> offset;
4259 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4261 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4264 case RT5677_GPIO1 ... RT5677_GPIO5:
4265 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4266 0x1 << (offset * 3 + 2), 0x0);
4270 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4271 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4281 /** Configures the gpio as
4286 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4292 case RT5677_GPIO1 ... RT5677_GPIO2:
4293 shift = 2 * (1 - offset);
4294 regmap_update_bits(rt5677->regmap,
4295 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4297 (value & 0x3) << shift);
4300 case RT5677_GPIO3 ... RT5677_GPIO6:
4301 shift = 2 * (9 - offset);
4302 regmap_update_bits(rt5677->regmap,
4303 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4305 (value & 0x3) << shift);
4313 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4315 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4316 struct regmap_irq_chip_data *data = rt5677->irq_data;
4319 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4320 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4321 (rt5677->pdata.jd1_gpio == 2 &&
4322 offset == RT5677_GPIO2) ||
4323 (rt5677->pdata.jd1_gpio == 3 &&
4324 offset == RT5677_GPIO3)) {
4325 irq = RT5677_IRQ_JD1;
4331 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4332 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4333 (rt5677->pdata.jd2_gpio == 2 &&
4334 offset == RT5677_GPIO5) ||
4335 (rt5677->pdata.jd2_gpio == 3 &&
4336 offset == RT5677_GPIO6)) {
4337 irq = RT5677_IRQ_JD2;
4338 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4339 offset == RT5677_GPIO4) ||
4340 (rt5677->pdata.jd3_gpio == 2 &&
4341 offset == RT5677_GPIO5) ||
4342 (rt5677->pdata.jd3_gpio == 3 &&
4343 offset == RT5677_GPIO6)) {
4344 irq = RT5677_IRQ_JD3;
4350 return regmap_irq_get_virq(data, irq);
4353 static struct gpio_chip rt5677_template_chip = {
4355 .owner = THIS_MODULE,
4356 .direction_output = rt5677_gpio_direction_out,
4357 .set = rt5677_gpio_set,
4358 .direction_input = rt5677_gpio_direction_in,
4359 .get = rt5677_gpio_get,
4360 .to_irq = rt5677_to_irq,
4364 static void rt5677_init_gpio(struct i2c_client *i2c)
4366 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4369 rt5677->gpio_chip = rt5677_template_chip;
4370 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4371 rt5677->gpio_chip.dev = &i2c->dev;
4372 rt5677->gpio_chip.base = -1;
4374 ret = gpiochip_add(&rt5677->gpio_chip);
4376 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4379 static void rt5677_free_gpio(struct i2c_client *i2c)
4381 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4383 gpiochip_remove(&rt5677->gpio_chip);
4386 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4391 static void rt5677_init_gpio(struct i2c_client *i2c)
4395 static void rt5677_free_gpio(struct i2c_client *i2c)
4400 static int rt5677_probe(struct snd_soc_codec *codec)
4402 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4405 rt5677->codec = codec;
4407 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4408 snd_soc_dapm_add_routes(&codec->dapm,
4410 ARRAY_SIZE(rt5677_dmic2_clk_2));
4411 } else { /*use dmic1 clock by default*/
4412 snd_soc_dapm_add_routes(&codec->dapm,
4414 ARRAY_SIZE(rt5677_dmic2_clk_1));
4417 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
4419 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4420 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4422 for (i = 0; i < RT5677_GPIO_NUM; i++)
4423 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4425 if (rt5677->irq_data) {
4426 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4428 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4431 if (rt5677->pdata.jd1_gpio)
4432 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4433 RT5677_SEL_GPIO_JD1_MASK,
4434 rt5677->pdata.jd1_gpio <<
4435 RT5677_SEL_GPIO_JD1_SFT);
4437 if (rt5677->pdata.jd2_gpio)
4438 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4439 RT5677_SEL_GPIO_JD2_MASK,
4440 rt5677->pdata.jd2_gpio <<
4441 RT5677_SEL_GPIO_JD2_SFT);
4443 if (rt5677->pdata.jd3_gpio)
4444 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4445 RT5677_SEL_GPIO_JD3_MASK,
4446 rt5677->pdata.jd3_gpio <<
4447 RT5677_SEL_GPIO_JD3_SFT);
4450 mutex_init(&rt5677->dsp_cmd_lock);
4451 mutex_init(&rt5677->dsp_pri_lock);
4456 static int rt5677_remove(struct snd_soc_codec *codec)
4458 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4460 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4461 if (gpio_is_valid(rt5677->pow_ldo2))
4462 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4468 static int rt5677_suspend(struct snd_soc_codec *codec)
4470 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4472 if (!rt5677->dsp_vad_en) {
4473 regcache_cache_only(rt5677->regmap, true);
4474 regcache_mark_dirty(rt5677->regmap);
4477 if (gpio_is_valid(rt5677->pow_ldo2))
4478 gpio_set_value_cansleep(rt5677->pow_ldo2, 0);
4483 static int rt5677_resume(struct snd_soc_codec *codec)
4485 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4487 if (gpio_is_valid(rt5677->pow_ldo2)) {
4488 gpio_set_value_cansleep(rt5677->pow_ldo2, 1);
4492 if (!rt5677->dsp_vad_en) {
4493 regcache_cache_only(rt5677->regmap, false);
4494 regcache_sync(rt5677->regmap);
4500 #define rt5677_suspend NULL
4501 #define rt5677_resume NULL
4504 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4506 struct i2c_client *client = context;
4507 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4509 if (rt5677->is_dsp_mode) {
4511 mutex_lock(&rt5677->dsp_pri_lock);
4512 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4514 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4515 mutex_unlock(&rt5677->dsp_pri_lock);
4517 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4520 regmap_read(rt5677->regmap_physical, reg, val);
4526 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4528 struct i2c_client *client = context;
4529 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4531 if (rt5677->is_dsp_mode) {
4533 mutex_lock(&rt5677->dsp_pri_lock);
4534 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4536 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4538 mutex_unlock(&rt5677->dsp_pri_lock);
4540 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4543 regmap_write(rt5677->regmap_physical, reg, val);
4549 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4550 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4551 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4553 static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4554 .hw_params = rt5677_hw_params,
4555 .set_fmt = rt5677_set_dai_fmt,
4556 .set_sysclk = rt5677_set_dai_sysclk,
4557 .set_pll = rt5677_set_dai_pll,
4558 .set_tdm_slot = rt5677_set_tdm_slot,
4561 static struct snd_soc_dai_driver rt5677_dai[] = {
4563 .name = "rt5677-aif1",
4566 .stream_name = "AIF1 Playback",
4569 .rates = RT5677_STEREO_RATES,
4570 .formats = RT5677_FORMATS,
4573 .stream_name = "AIF1 Capture",
4576 .rates = RT5677_STEREO_RATES,
4577 .formats = RT5677_FORMATS,
4579 .ops = &rt5677_aif_dai_ops,
4582 .name = "rt5677-aif2",
4585 .stream_name = "AIF2 Playback",
4588 .rates = RT5677_STEREO_RATES,
4589 .formats = RT5677_FORMATS,
4592 .stream_name = "AIF2 Capture",
4595 .rates = RT5677_STEREO_RATES,
4596 .formats = RT5677_FORMATS,
4598 .ops = &rt5677_aif_dai_ops,
4601 .name = "rt5677-aif3",
4604 .stream_name = "AIF3 Playback",
4607 .rates = RT5677_STEREO_RATES,
4608 .formats = RT5677_FORMATS,
4611 .stream_name = "AIF3 Capture",
4614 .rates = RT5677_STEREO_RATES,
4615 .formats = RT5677_FORMATS,
4617 .ops = &rt5677_aif_dai_ops,
4620 .name = "rt5677-aif4",
4623 .stream_name = "AIF4 Playback",
4626 .rates = RT5677_STEREO_RATES,
4627 .formats = RT5677_FORMATS,
4630 .stream_name = "AIF4 Capture",
4633 .rates = RT5677_STEREO_RATES,
4634 .formats = RT5677_FORMATS,
4636 .ops = &rt5677_aif_dai_ops,
4639 .name = "rt5677-slimbus",
4642 .stream_name = "SLIMBus Playback",
4645 .rates = RT5677_STEREO_RATES,
4646 .formats = RT5677_FORMATS,
4649 .stream_name = "SLIMBus Capture",
4652 .rates = RT5677_STEREO_RATES,
4653 .formats = RT5677_FORMATS,
4655 .ops = &rt5677_aif_dai_ops,
4659 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4660 .probe = rt5677_probe,
4661 .remove = rt5677_remove,
4662 .suspend = rt5677_suspend,
4663 .resume = rt5677_resume,
4664 .set_bias_level = rt5677_set_bias_level,
4665 .idle_bias_off = true,
4666 .controls = rt5677_snd_controls,
4667 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4668 .dapm_widgets = rt5677_dapm_widgets,
4669 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4670 .dapm_routes = rt5677_dapm_routes,
4671 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4674 static const struct regmap_config rt5677_regmap_physical = {
4679 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4681 .readable_reg = rt5677_readable_register,
4683 .cache_type = REGCACHE_NONE,
4684 .ranges = rt5677_ranges,
4685 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4688 static const struct regmap_config rt5677_regmap = {
4692 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4695 .volatile_reg = rt5677_volatile_register,
4696 .readable_reg = rt5677_readable_register,
4697 .reg_read = rt5677_read,
4698 .reg_write = rt5677_write,
4700 .cache_type = REGCACHE_RBTREE,
4701 .reg_defaults = rt5677_reg,
4702 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
4703 .ranges = rt5677_ranges,
4704 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4707 static const struct i2c_device_id rt5677_i2c_id[] = {
4711 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
4713 static int rt5677_parse_dt(struct rt5677_priv *rt5677, struct device_node *np)
4715 rt5677->pdata.in1_diff = of_property_read_bool(np,
4716 "realtek,in1-differential");
4717 rt5677->pdata.in2_diff = of_property_read_bool(np,
4718 "realtek,in2-differential");
4719 rt5677->pdata.lout1_diff = of_property_read_bool(np,
4720 "realtek,lout1-differential");
4721 rt5677->pdata.lout2_diff = of_property_read_bool(np,
4722 "realtek,lout2-differential");
4723 rt5677->pdata.lout3_diff = of_property_read_bool(np,
4724 "realtek,lout3-differential");
4726 rt5677->pow_ldo2 = of_get_named_gpio(np,
4727 "realtek,pow-ldo2-gpio", 0);
4730 * POW_LDO2 is optional (it may be statically tied on the board).
4731 * -ENOENT means that the property doesn't exist, i.e. there is no
4732 * GPIO, so is not an error. Any other error code means the property
4733 * exists, but could not be parsed.
4735 if (!gpio_is_valid(rt5677->pow_ldo2) &&
4736 (rt5677->pow_ldo2 != -ENOENT))
4737 return rt5677->pow_ldo2;
4739 of_property_read_u8_array(np, "realtek,gpio-config",
4740 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
4742 of_property_read_u32(np, "realtek,jd1-gpio", &rt5677->pdata.jd1_gpio);
4743 of_property_read_u32(np, "realtek,jd2-gpio", &rt5677->pdata.jd2_gpio);
4744 of_property_read_u32(np, "realtek,jd3-gpio", &rt5677->pdata.jd3_gpio);
4749 static struct regmap_irq rt5677_irqs[] = {
4750 [RT5677_IRQ_JD1] = {
4752 .mask = RT5677_EN_IRQ_GPIO_JD1,
4754 [RT5677_IRQ_JD2] = {
4756 .mask = RT5677_EN_IRQ_GPIO_JD2,
4758 [RT5677_IRQ_JD3] = {
4760 .mask = RT5677_EN_IRQ_GPIO_JD3,
4764 static struct regmap_irq_chip rt5677_irq_chip = {
4766 .irqs = rt5677_irqs,
4767 .num_irqs = ARRAY_SIZE(rt5677_irqs),
4770 .status_base = RT5677_IRQ_CTRL1,
4771 .mask_base = RT5677_IRQ_CTRL1,
4775 static int rt5677_init_irq(struct i2c_client *i2c)
4778 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4780 if (!rt5677->pdata.jd1_gpio &&
4781 !rt5677->pdata.jd2_gpio &&
4782 !rt5677->pdata.jd3_gpio)
4786 dev_err(&i2c->dev, "No interrupt specified\n");
4790 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
4791 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
4792 &rt5677_irq_chip, &rt5677->irq_data);
4795 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
4802 static void rt5677_free_irq(struct i2c_client *i2c)
4804 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4806 if (rt5677->irq_data)
4807 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
4810 static int rt5677_i2c_probe(struct i2c_client *i2c,
4811 const struct i2c_device_id *id)
4813 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
4814 struct rt5677_priv *rt5677;
4818 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
4823 i2c_set_clientdata(i2c, rt5677);
4826 rt5677->pdata = *pdata;
4828 if (i2c->dev.of_node) {
4829 ret = rt5677_parse_dt(rt5677, i2c->dev.of_node);
4831 dev_err(&i2c->dev, "Failed to parse device tree: %d\n",
4836 rt5677->pow_ldo2 = -EINVAL;
4839 if (gpio_is_valid(rt5677->pow_ldo2)) {
4840 ret = devm_gpio_request_one(&i2c->dev, rt5677->pow_ldo2,
4841 GPIOF_OUT_INIT_HIGH,
4844 dev_err(&i2c->dev, "Failed to request POW_LDO2 %d: %d\n",
4845 rt5677->pow_ldo2, ret);
4848 /* Wait a while until I2C bus becomes available. The datasheet
4849 * does not specify the exact we should wait but startup
4850 * sequence mentiones at least a few milliseconds.
4855 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
4856 &rt5677_regmap_physical);
4857 if (IS_ERR(rt5677->regmap_physical)) {
4858 ret = PTR_ERR(rt5677->regmap_physical);
4859 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4864 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
4865 if (IS_ERR(rt5677->regmap)) {
4866 ret = PTR_ERR(rt5677->regmap);
4867 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4872 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
4873 if (val != RT5677_DEVICE_ID) {
4875 "Device with ID register %x is not rt5677\n", val);
4879 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4881 ret = regmap_register_patch(rt5677->regmap, init_list,
4882 ARRAY_SIZE(init_list));
4884 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4886 if (rt5677->pdata.in1_diff)
4887 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4888 RT5677_IN_DF1, RT5677_IN_DF1);
4890 if (rt5677->pdata.in2_diff)
4891 regmap_update_bits(rt5677->regmap, RT5677_IN1,
4892 RT5677_IN_DF2, RT5677_IN_DF2);
4894 if (rt5677->pdata.lout1_diff)
4895 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4896 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
4898 if (rt5677->pdata.lout2_diff)
4899 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4900 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
4902 if (rt5677->pdata.lout3_diff)
4903 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
4904 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
4906 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4907 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
4908 RT5677_GPIO5_FUNC_MASK,
4909 RT5677_GPIO5_FUNC_DMIC);
4910 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4911 RT5677_GPIO5_DIR_MASK,
4912 RT5677_GPIO5_DIR_OUT);
4915 rt5677_init_gpio(i2c);
4916 rt5677_init_irq(i2c);
4918 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
4919 rt5677_dai, ARRAY_SIZE(rt5677_dai));
4922 static int rt5677_i2c_remove(struct i2c_client *i2c)
4924 snd_soc_unregister_codec(&i2c->dev);
4925 rt5677_free_irq(i2c);
4926 rt5677_free_gpio(i2c);
4931 static struct i2c_driver rt5677_i2c_driver = {
4934 .owner = THIS_MODULE,
4936 .probe = rt5677_i2c_probe,
4937 .remove = rt5677_i2c_remove,
4938 .id_table = rt5677_i2c_id,
4940 module_i2c_driver(rt5677_i2c_driver);
4942 MODULE_DESCRIPTION("ASoC RT5677 driver");
4943 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
4944 MODULE_LICENSE("GPL v2");