2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/regmap.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22 #include <linux/firmware.h>
23 #include <linux/property.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
34 #include "rt5677-spi.h"
36 #define RT5677_DEVICE_ID 0x6327
38 #define RT5677_PR_RANGE_BASE (0xff + 1)
39 #define RT5677_PR_SPACING 0x100
41 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
43 static const struct regmap_range_cfg rt5677_ranges[] = {
46 .range_min = RT5677_PR_BASE,
47 .range_max = RT5677_PR_BASE + 0xfd,
48 .selector_reg = RT5677_PRIV_INDEX,
49 .selector_mask = 0xff,
50 .selector_shift = 0x0,
51 .window_start = RT5677_PRIV_DATA,
56 static const struct reg_sequence init_list[] = {
57 {RT5677_ASRC_12, 0x0018},
58 {RT5677_PR_BASE + 0x3d, 0x364d},
59 {RT5677_PR_BASE + 0x17, 0x4fc0},
60 {RT5677_PR_BASE + 0x13, 0x0312},
61 {RT5677_PR_BASE + 0x1e, 0x0000},
62 {RT5677_PR_BASE + 0x12, 0x0eaa},
63 {RT5677_PR_BASE + 0x14, 0x018a},
64 {RT5677_PR_BASE + 0x15, 0x0490},
65 {RT5677_PR_BASE + 0x38, 0x0f71},
66 {RT5677_PR_BASE + 0x39, 0x0f71},
68 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
70 static const struct reg_default rt5677_reg[] = {
71 {RT5677_RESET , 0x0000},
72 {RT5677_LOUT1 , 0xa800},
73 {RT5677_IN1 , 0x0000},
74 {RT5677_MICBIAS , 0x0000},
75 {RT5677_SLIMBUS_PARAM , 0x0000},
76 {RT5677_SLIMBUS_RX , 0x0000},
77 {RT5677_SLIMBUS_CTRL , 0x0000},
78 {RT5677_SIDETONE_CTRL , 0x000b},
79 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
80 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
81 {RT5677_DAC4_DIG_VOL , 0xafaf},
82 {RT5677_DAC3_DIG_VOL , 0xafaf},
83 {RT5677_DAC1_DIG_VOL , 0xafaf},
84 {RT5677_DAC2_DIG_VOL , 0xafaf},
85 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
86 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_STO1_2_ADC_BST , 0x0000},
89 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
90 {RT5677_ADC_BST_CTRL2 , 0x0000},
91 {RT5677_STO3_4_ADC_BST , 0x0000},
92 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
93 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
94 {RT5677_STO4_ADC_MIXER , 0xd4c0},
95 {RT5677_STO3_ADC_MIXER , 0xd4c0},
96 {RT5677_STO2_ADC_MIXER , 0xd4c0},
97 {RT5677_STO1_ADC_MIXER , 0xd4c0},
98 {RT5677_MONO_ADC_MIXER , 0xd4d1},
99 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
100 {RT5677_STO1_DAC_MIXER , 0xaaaa},
101 {RT5677_MONO_DAC_MIXER , 0xaaaa},
102 {RT5677_DD1_MIXER , 0xaaaa},
103 {RT5677_DD2_MIXER , 0xaaaa},
104 {RT5677_IF3_DATA , 0x0000},
105 {RT5677_IF4_DATA , 0x0000},
106 {RT5677_PDM_OUT_CTRL , 0x8888},
107 {RT5677_PDM_DATA_CTRL1 , 0x0000},
108 {RT5677_PDM_DATA_CTRL2 , 0x0000},
109 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
110 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
111 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
112 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
113 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
114 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
115 {RT5677_TDM1_CTRL1 , 0x0300},
116 {RT5677_TDM1_CTRL2 , 0x0000},
117 {RT5677_TDM1_CTRL3 , 0x4000},
118 {RT5677_TDM1_CTRL4 , 0x0123},
119 {RT5677_TDM1_CTRL5 , 0x4567},
120 {RT5677_TDM2_CTRL1 , 0x0300},
121 {RT5677_TDM2_CTRL2 , 0x0000},
122 {RT5677_TDM2_CTRL3 , 0x4000},
123 {RT5677_TDM2_CTRL4 , 0x0123},
124 {RT5677_TDM2_CTRL5 , 0x4567},
125 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
126 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
127 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
128 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
129 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
130 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
131 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
132 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
133 {RT5677_DMIC_CTRL1 , 0x1505},
134 {RT5677_DMIC_CTRL2 , 0x0055},
135 {RT5677_HAP_GENE_CTRL1 , 0x0111},
136 {RT5677_HAP_GENE_CTRL2 , 0x0064},
137 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
138 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
139 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
140 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
141 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
142 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
143 {RT5677_HAP_GENE_CTRL9 , 0xf000},
144 {RT5677_HAP_GENE_CTRL10 , 0x0000},
145 {RT5677_PWR_DIG1 , 0x0000},
146 {RT5677_PWR_DIG2 , 0x0000},
147 {RT5677_PWR_ANLG1 , 0x0055},
148 {RT5677_PWR_ANLG2 , 0x0000},
149 {RT5677_PWR_DSP1 , 0x0001},
150 {RT5677_PWR_DSP_ST , 0x0000},
151 {RT5677_PWR_DSP2 , 0x0000},
152 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
153 {RT5677_PRIV_INDEX , 0x0000},
154 {RT5677_PRIV_DATA , 0x0000},
155 {RT5677_I2S4_SDP , 0x8000},
156 {RT5677_I2S1_SDP , 0x8000},
157 {RT5677_I2S2_SDP , 0x8000},
158 {RT5677_I2S3_SDP , 0x8000},
159 {RT5677_CLK_TREE_CTRL1 , 0x1111},
160 {RT5677_CLK_TREE_CTRL2 , 0x1111},
161 {RT5677_CLK_TREE_CTRL3 , 0x0000},
162 {RT5677_PLL1_CTRL1 , 0x0000},
163 {RT5677_PLL1_CTRL2 , 0x0000},
164 {RT5677_PLL2_CTRL1 , 0x0c60},
165 {RT5677_PLL2_CTRL2 , 0x2000},
166 {RT5677_GLB_CLK1 , 0x0000},
167 {RT5677_GLB_CLK2 , 0x0000},
168 {RT5677_ASRC_1 , 0x0000},
169 {RT5677_ASRC_2 , 0x0000},
170 {RT5677_ASRC_3 , 0x0000},
171 {RT5677_ASRC_4 , 0x0000},
172 {RT5677_ASRC_5 , 0x0000},
173 {RT5677_ASRC_6 , 0x0000},
174 {RT5677_ASRC_7 , 0x0000},
175 {RT5677_ASRC_8 , 0x0000},
176 {RT5677_ASRC_9 , 0x0000},
177 {RT5677_ASRC_10 , 0x0000},
178 {RT5677_ASRC_11 , 0x0000},
179 {RT5677_ASRC_12 , 0x0018},
180 {RT5677_ASRC_13 , 0x0000},
181 {RT5677_ASRC_14 , 0x0000},
182 {RT5677_ASRC_15 , 0x0000},
183 {RT5677_ASRC_16 , 0x0000},
184 {RT5677_ASRC_17 , 0x0000},
185 {RT5677_ASRC_18 , 0x0000},
186 {RT5677_ASRC_19 , 0x0000},
187 {RT5677_ASRC_20 , 0x0000},
188 {RT5677_ASRC_21 , 0x000c},
189 {RT5677_ASRC_22 , 0x0000},
190 {RT5677_ASRC_23 , 0x0000},
191 {RT5677_VAD_CTRL1 , 0x2184},
192 {RT5677_VAD_CTRL2 , 0x010a},
193 {RT5677_VAD_CTRL3 , 0x0aea},
194 {RT5677_VAD_CTRL4 , 0x000c},
195 {RT5677_VAD_CTRL5 , 0x0000},
196 {RT5677_DSP_INB_CTRL1 , 0x0000},
197 {RT5677_DSP_INB_CTRL2 , 0x0000},
198 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
199 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
200 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
201 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
202 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
203 {RT5677_ADC_EQ_CTRL1 , 0x6000},
204 {RT5677_ADC_EQ_CTRL2 , 0x0000},
205 {RT5677_EQ_CTRL1 , 0xc000},
206 {RT5677_EQ_CTRL2 , 0x0000},
207 {RT5677_EQ_CTRL3 , 0x0000},
208 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
209 {RT5677_JD_CTRL1 , 0x0000},
210 {RT5677_JD_CTRL2 , 0x0000},
211 {RT5677_JD_CTRL3 , 0x0000},
212 {RT5677_IRQ_CTRL1 , 0x0000},
213 {RT5677_IRQ_CTRL2 , 0x0000},
214 {RT5677_GPIO_ST , 0x0000},
215 {RT5677_GPIO_CTRL1 , 0x0000},
216 {RT5677_GPIO_CTRL2 , 0x0000},
217 {RT5677_GPIO_CTRL3 , 0x0000},
218 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
219 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
223 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
224 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
225 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
226 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
227 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
228 {RT5677_MB_DRC_CTRL1 , 0x0f20},
229 {RT5677_DRC1_CTRL1 , 0x001f},
230 {RT5677_DRC1_CTRL2 , 0x020c},
231 {RT5677_DRC1_CTRL3 , 0x1f00},
232 {RT5677_DRC1_CTRL4 , 0x0000},
233 {RT5677_DRC1_CTRL5 , 0x0000},
234 {RT5677_DRC1_CTRL6 , 0x0029},
235 {RT5677_DRC2_CTRL1 , 0x001f},
236 {RT5677_DRC2_CTRL2 , 0x020c},
237 {RT5677_DRC2_CTRL3 , 0x1f00},
238 {RT5677_DRC2_CTRL4 , 0x0000},
239 {RT5677_DRC2_CTRL5 , 0x0000},
240 {RT5677_DRC2_CTRL6 , 0x0029},
241 {RT5677_DRC1_HL_CTRL1 , 0x8000},
242 {RT5677_DRC1_HL_CTRL2 , 0x0200},
243 {RT5677_DRC2_HL_CTRL1 , 0x8000},
244 {RT5677_DRC2_HL_CTRL2 , 0x0200},
245 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
246 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
247 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
248 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
249 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
250 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
251 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
252 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
253 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
254 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
255 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
256 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
257 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
258 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
259 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
260 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
261 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
262 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
263 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
264 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
265 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
266 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
267 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
268 {RT5677_DIG_MISC , 0x0000},
269 {RT5677_GEN_CTRL1 , 0x0000},
270 {RT5677_GEN_CTRL2 , 0x0000},
271 {RT5677_VENDOR_ID , 0x0000},
272 {RT5677_VENDOR_ID1 , 0x10ec},
273 {RT5677_VENDOR_ID2 , 0x6327},
276 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
280 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
281 if (reg >= rt5677_ranges[i].range_min &&
282 reg <= rt5677_ranges[i].range_max) {
289 case RT5677_SLIMBUS_PARAM:
290 case RT5677_PDM_DATA_CTRL1:
291 case RT5677_PDM_DATA_CTRL2:
292 case RT5677_PDM1_DATA_CTRL4:
293 case RT5677_PDM2_DATA_CTRL4:
294 case RT5677_I2C_MASTER_CTRL1:
295 case RT5677_I2C_MASTER_CTRL7:
296 case RT5677_I2C_MASTER_CTRL8:
297 case RT5677_HAP_GENE_CTRL2:
298 case RT5677_PWR_DSP_ST:
299 case RT5677_PRIV_DATA:
300 case RT5677_PLL1_CTRL2:
301 case RT5677_PLL2_CTRL2:
304 case RT5677_VAD_CTRL5:
305 case RT5677_ADC_EQ_CTRL1:
306 case RT5677_EQ_CTRL1:
307 case RT5677_IRQ_CTRL1:
308 case RT5677_IRQ_CTRL2:
310 case RT5677_DSP_INB1_SRC_CTRL4:
311 case RT5677_DSP_INB2_SRC_CTRL4:
312 case RT5677_DSP_INB3_SRC_CTRL4:
313 case RT5677_DSP_OUTB1_SRC_CTRL4:
314 case RT5677_DSP_OUTB2_SRC_CTRL4:
315 case RT5677_VENDOR_ID:
316 case RT5677_VENDOR_ID1:
317 case RT5677_VENDOR_ID2:
324 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
328 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
329 if (reg >= rt5677_ranges[i].range_min &&
330 reg <= rt5677_ranges[i].range_max) {
340 case RT5677_SLIMBUS_PARAM:
341 case RT5677_SLIMBUS_RX:
342 case RT5677_SLIMBUS_CTRL:
343 case RT5677_SIDETONE_CTRL:
344 case RT5677_ANA_DAC1_2_3_SRC:
345 case RT5677_IF_DSP_DAC3_4_MIXER:
346 case RT5677_DAC4_DIG_VOL:
347 case RT5677_DAC3_DIG_VOL:
348 case RT5677_DAC1_DIG_VOL:
349 case RT5677_DAC2_DIG_VOL:
350 case RT5677_IF_DSP_DAC2_MIXER:
351 case RT5677_STO1_ADC_DIG_VOL:
352 case RT5677_MONO_ADC_DIG_VOL:
353 case RT5677_STO1_2_ADC_BST:
354 case RT5677_STO2_ADC_DIG_VOL:
355 case RT5677_ADC_BST_CTRL2:
356 case RT5677_STO3_4_ADC_BST:
357 case RT5677_STO3_ADC_DIG_VOL:
358 case RT5677_STO4_ADC_DIG_VOL:
359 case RT5677_STO4_ADC_MIXER:
360 case RT5677_STO3_ADC_MIXER:
361 case RT5677_STO2_ADC_MIXER:
362 case RT5677_STO1_ADC_MIXER:
363 case RT5677_MONO_ADC_MIXER:
364 case RT5677_ADC_IF_DSP_DAC1_MIXER:
365 case RT5677_STO1_DAC_MIXER:
366 case RT5677_MONO_DAC_MIXER:
367 case RT5677_DD1_MIXER:
368 case RT5677_DD2_MIXER:
369 case RT5677_IF3_DATA:
370 case RT5677_IF4_DATA:
371 case RT5677_PDM_OUT_CTRL:
372 case RT5677_PDM_DATA_CTRL1:
373 case RT5677_PDM_DATA_CTRL2:
374 case RT5677_PDM1_DATA_CTRL2:
375 case RT5677_PDM1_DATA_CTRL3:
376 case RT5677_PDM1_DATA_CTRL4:
377 case RT5677_PDM2_DATA_CTRL2:
378 case RT5677_PDM2_DATA_CTRL3:
379 case RT5677_PDM2_DATA_CTRL4:
380 case RT5677_TDM1_CTRL1:
381 case RT5677_TDM1_CTRL2:
382 case RT5677_TDM1_CTRL3:
383 case RT5677_TDM1_CTRL4:
384 case RT5677_TDM1_CTRL5:
385 case RT5677_TDM2_CTRL1:
386 case RT5677_TDM2_CTRL2:
387 case RT5677_TDM2_CTRL3:
388 case RT5677_TDM2_CTRL4:
389 case RT5677_TDM2_CTRL5:
390 case RT5677_I2C_MASTER_CTRL1:
391 case RT5677_I2C_MASTER_CTRL2:
392 case RT5677_I2C_MASTER_CTRL3:
393 case RT5677_I2C_MASTER_CTRL4:
394 case RT5677_I2C_MASTER_CTRL5:
395 case RT5677_I2C_MASTER_CTRL6:
396 case RT5677_I2C_MASTER_CTRL7:
397 case RT5677_I2C_MASTER_CTRL8:
398 case RT5677_DMIC_CTRL1:
399 case RT5677_DMIC_CTRL2:
400 case RT5677_HAP_GENE_CTRL1:
401 case RT5677_HAP_GENE_CTRL2:
402 case RT5677_HAP_GENE_CTRL3:
403 case RT5677_HAP_GENE_CTRL4:
404 case RT5677_HAP_GENE_CTRL5:
405 case RT5677_HAP_GENE_CTRL6:
406 case RT5677_HAP_GENE_CTRL7:
407 case RT5677_HAP_GENE_CTRL8:
408 case RT5677_HAP_GENE_CTRL9:
409 case RT5677_HAP_GENE_CTRL10:
410 case RT5677_PWR_DIG1:
411 case RT5677_PWR_DIG2:
412 case RT5677_PWR_ANLG1:
413 case RT5677_PWR_ANLG2:
414 case RT5677_PWR_DSP1:
415 case RT5677_PWR_DSP_ST:
416 case RT5677_PWR_DSP2:
417 case RT5677_ADC_DAC_HPF_CTRL1:
418 case RT5677_PRIV_INDEX:
419 case RT5677_PRIV_DATA:
420 case RT5677_I2S4_SDP:
421 case RT5677_I2S1_SDP:
422 case RT5677_I2S2_SDP:
423 case RT5677_I2S3_SDP:
424 case RT5677_CLK_TREE_CTRL1:
425 case RT5677_CLK_TREE_CTRL2:
426 case RT5677_CLK_TREE_CTRL3:
427 case RT5677_PLL1_CTRL1:
428 case RT5677_PLL1_CTRL2:
429 case RT5677_PLL2_CTRL1:
430 case RT5677_PLL2_CTRL2:
431 case RT5677_GLB_CLK1:
432 case RT5677_GLB_CLK2:
456 case RT5677_VAD_CTRL1:
457 case RT5677_VAD_CTRL2:
458 case RT5677_VAD_CTRL3:
459 case RT5677_VAD_CTRL4:
460 case RT5677_VAD_CTRL5:
461 case RT5677_DSP_INB_CTRL1:
462 case RT5677_DSP_INB_CTRL2:
463 case RT5677_DSP_IN_OUTB_CTRL:
464 case RT5677_DSP_OUTB0_1_DIG_VOL:
465 case RT5677_DSP_OUTB2_3_DIG_VOL:
466 case RT5677_DSP_OUTB4_5_DIG_VOL:
467 case RT5677_DSP_OUTB6_7_DIG_VOL:
468 case RT5677_ADC_EQ_CTRL1:
469 case RT5677_ADC_EQ_CTRL2:
470 case RT5677_EQ_CTRL1:
471 case RT5677_EQ_CTRL2:
472 case RT5677_EQ_CTRL3:
473 case RT5677_SOFT_VOL_ZERO_CROSS1:
474 case RT5677_JD_CTRL1:
475 case RT5677_JD_CTRL2:
476 case RT5677_JD_CTRL3:
477 case RT5677_IRQ_CTRL1:
478 case RT5677_IRQ_CTRL2:
480 case RT5677_GPIO_CTRL1:
481 case RT5677_GPIO_CTRL2:
482 case RT5677_GPIO_CTRL3:
483 case RT5677_STO1_ADC_HI_FILTER1:
484 case RT5677_STO1_ADC_HI_FILTER2:
485 case RT5677_MONO_ADC_HI_FILTER1:
486 case RT5677_MONO_ADC_HI_FILTER2:
487 case RT5677_STO2_ADC_HI_FILTER1:
488 case RT5677_STO2_ADC_HI_FILTER2:
489 case RT5677_STO3_ADC_HI_FILTER1:
490 case RT5677_STO3_ADC_HI_FILTER2:
491 case RT5677_STO4_ADC_HI_FILTER1:
492 case RT5677_STO4_ADC_HI_FILTER2:
493 case RT5677_MB_DRC_CTRL1:
494 case RT5677_DRC1_CTRL1:
495 case RT5677_DRC1_CTRL2:
496 case RT5677_DRC1_CTRL3:
497 case RT5677_DRC1_CTRL4:
498 case RT5677_DRC1_CTRL5:
499 case RT5677_DRC1_CTRL6:
500 case RT5677_DRC2_CTRL1:
501 case RT5677_DRC2_CTRL2:
502 case RT5677_DRC2_CTRL3:
503 case RT5677_DRC2_CTRL4:
504 case RT5677_DRC2_CTRL5:
505 case RT5677_DRC2_CTRL6:
506 case RT5677_DRC1_HL_CTRL1:
507 case RT5677_DRC1_HL_CTRL2:
508 case RT5677_DRC2_HL_CTRL1:
509 case RT5677_DRC2_HL_CTRL2:
510 case RT5677_DSP_INB1_SRC_CTRL1:
511 case RT5677_DSP_INB1_SRC_CTRL2:
512 case RT5677_DSP_INB1_SRC_CTRL3:
513 case RT5677_DSP_INB1_SRC_CTRL4:
514 case RT5677_DSP_INB2_SRC_CTRL1:
515 case RT5677_DSP_INB2_SRC_CTRL2:
516 case RT5677_DSP_INB2_SRC_CTRL3:
517 case RT5677_DSP_INB2_SRC_CTRL4:
518 case RT5677_DSP_INB3_SRC_CTRL1:
519 case RT5677_DSP_INB3_SRC_CTRL2:
520 case RT5677_DSP_INB3_SRC_CTRL3:
521 case RT5677_DSP_INB3_SRC_CTRL4:
522 case RT5677_DSP_OUTB1_SRC_CTRL1:
523 case RT5677_DSP_OUTB1_SRC_CTRL2:
524 case RT5677_DSP_OUTB1_SRC_CTRL3:
525 case RT5677_DSP_OUTB1_SRC_CTRL4:
526 case RT5677_DSP_OUTB2_SRC_CTRL1:
527 case RT5677_DSP_OUTB2_SRC_CTRL2:
528 case RT5677_DSP_OUTB2_SRC_CTRL3:
529 case RT5677_DSP_OUTB2_SRC_CTRL4:
530 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
531 case RT5677_DSP_OUTB_45_MIXER_CTRL:
532 case RT5677_DSP_OUTB_67_MIXER_CTRL:
533 case RT5677_DIG_MISC:
534 case RT5677_GEN_CTRL1:
535 case RT5677_GEN_CTRL2:
536 case RT5677_VENDOR_ID:
537 case RT5677_VENDOR_ID1:
538 case RT5677_VENDOR_ID2:
546 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
547 * @rt5677: Private Data.
548 * @addr: Address index.
549 * @value: Address data.
552 * Returns 0 for success or negative error code.
554 static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
555 unsigned int addr, unsigned int value, unsigned int opcode)
557 struct snd_soc_codec *codec = rt5677->codec;
560 mutex_lock(&rt5677->dsp_cmd_lock);
562 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
565 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
569 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
572 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
576 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
579 dev_err(codec->dev, "Failed to set data msb value: %d\n", ret);
583 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
586 dev_err(codec->dev, "Failed to set data lsb value: %d\n", ret);
590 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
593 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
598 mutex_unlock(&rt5677->dsp_cmd_lock);
604 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
605 * rt5677: Private Data.
606 * @addr: Address index.
607 * @value: Address data.
610 * Returns 0 for success or negative error code.
612 static int rt5677_dsp_mode_i2c_read_addr(
613 struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
615 struct snd_soc_codec *codec = rt5677->codec;
617 unsigned int msb, lsb;
619 mutex_lock(&rt5677->dsp_cmd_lock);
621 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
624 dev_err(codec->dev, "Failed to set addr msb value: %d\n", ret);
628 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
631 dev_err(codec->dev, "Failed to set addr lsb value: %d\n", ret);
635 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
638 dev_err(codec->dev, "Failed to set op code value: %d\n", ret);
642 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
643 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
644 *value = (msb << 16) | lsb;
647 mutex_unlock(&rt5677->dsp_cmd_lock);
653 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
654 * rt5677: Private Data.
655 * @reg: Register index.
656 * @value: Register data.
659 * Returns 0 for success or negative error code.
661 static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
662 unsigned int reg, unsigned int value)
664 return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
669 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
670 * @codec: SoC audio codec device.
671 * @reg: Register index.
672 * @value: Register data.
675 * Returns 0 for success or negative error code.
677 static int rt5677_dsp_mode_i2c_read(
678 struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
680 int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
688 static void rt5677_set_dsp_mode(struct snd_soc_codec *codec, bool on)
690 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
693 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2);
694 rt5677->is_dsp_mode = true;
696 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0);
697 rt5677->is_dsp_mode = false;
701 static int rt5677_set_dsp_vad(struct snd_soc_codec *codec, bool on)
703 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
704 static bool activity;
707 if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
710 if (on && !activity) {
713 regcache_cache_only(rt5677->regmap, false);
714 regcache_cache_bypass(rt5677->regmap, true);
716 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1);
717 regmap_update_bits(rt5677->regmap,
718 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0f00);
719 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
720 RT5677_LDO1_SEL_MASK, 0x0);
721 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
722 RT5677_PWR_LDO1, RT5677_PWR_LDO1);
723 switch (rt5677->type) {
725 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
726 RT5677_MCLK_SRC_MASK, RT5677_MCLK2_SRC);
727 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
728 RT5677_PLL2_PR_SRC_MASK |
729 RT5677_DSP_CLK_SRC_MASK,
730 RT5677_PLL2_PR_SRC_MCLK2 |
731 RT5677_DSP_CLK_SRC_BYPASS);
734 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2,
735 RT5677_DSP_CLK_SRC_MASK,
736 RT5677_DSP_CLK_SRC_BYPASS);
741 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff);
742 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd);
743 rt5677_set_dsp_mode(codec, true);
745 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1,
748 rt5677_spi_write_firmware(0x50000000, rt5677->fw1);
749 release_firmware(rt5677->fw1);
752 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2,
755 rt5677_spi_write_firmware(0x60000000, rt5677->fw2);
756 release_firmware(rt5677->fw2);
759 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0);
761 regcache_cache_bypass(rt5677->regmap, false);
762 regcache_cache_only(rt5677->regmap, true);
763 } else if (!on && activity) {
766 regcache_cache_only(rt5677->regmap, false);
767 regcache_cache_bypass(rt5677->regmap, true);
769 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1);
770 rt5677_set_dsp_mode(codec, false);
771 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001);
773 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
775 regcache_cache_bypass(rt5677->regmap, false);
776 regcache_mark_dirty(rt5677->regmap);
777 regcache_sync(rt5677->regmap);
783 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
784 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
785 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
786 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
787 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
788 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
790 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
791 static unsigned int bst_tlv[] = {
792 TLV_DB_RANGE_HEAD(7),
793 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
794 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
795 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
796 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
797 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
798 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
799 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
802 static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
803 struct snd_ctl_elem_value *ucontrol)
805 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
806 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
808 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en;
813 static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
814 struct snd_ctl_elem_value *ucontrol)
816 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
817 struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
818 struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
820 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0];
822 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF)
823 rt5677_set_dsp_vad(codec, rt5677->dsp_vad_en);
828 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
830 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
831 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
832 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
833 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
834 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
835 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
837 /* DAC Digital Volume */
838 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
839 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
840 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
841 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
842 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
843 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
844 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
845 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 87, 0, dac_vol_tlv),
847 /* IN1/IN2 Control */
848 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
849 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
851 /* ADC Digital Volume Control */
852 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
853 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
854 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
855 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
856 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
857 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
858 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
859 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
860 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
861 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
863 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
864 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
866 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
867 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
869 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
870 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
872 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
873 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
875 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
876 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
879 /* Sidetone Control */
880 SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
881 RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),
883 /* ADC Boost Volume Control */
884 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
885 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
887 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
888 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
890 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
891 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
893 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
894 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
896 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
897 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
900 SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
901 rt5677_dsp_vad_get, rt5677_dsp_vad_put),
905 * set_dmic_clk - Set parameter of dmic.
908 * @kcontrol: The kcontrol of this widget.
911 * Choose dmic clock between 1MHz and 3MHz.
912 * It is better for clock to approximate 3MHz.
914 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
915 struct snd_kcontrol *kcontrol, int event)
917 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
918 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
921 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
922 RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
923 idx = rl6231_calc_dmic_clk(rate);
925 dev_err(codec->dev, "Failed to set DMIC clock\n");
927 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
928 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
932 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
933 struct snd_soc_dapm_widget *sink)
935 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
936 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
939 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
940 val &= RT5677_SCLK_SRC_MASK;
941 if (val == RT5677_SCLK_SRC_PLL1)
947 static int is_using_asrc(struct snd_soc_dapm_widget *source,
948 struct snd_soc_dapm_widget *sink)
950 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
951 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
952 unsigned int reg, shift, val;
954 if (source->reg == RT5677_ASRC_1) {
955 switch (source->shift) {
976 switch (source->shift) {
1002 reg = RT5677_ASRC_3;
1006 reg = RT5677_ASRC_3;
1010 reg = RT5677_ASRC_3;
1018 regmap_read(rt5677->regmap, reg, &val);
1019 val = (val >> shift) & 0xf;
1030 static int can_use_asrc(struct snd_soc_dapm_widget *source,
1031 struct snd_soc_dapm_widget *sink)
1033 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1034 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1036 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
1043 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1044 * @codec: SoC audio codec device.
1045 * @filter_mask: mask of filters.
1046 * @clk_src: clock source
1048 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
1049 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1050 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1051 * ASRC function will track i2s clock and generate a corresponding system clock
1052 * for codec. This function provides an API to select the clock source for a
1053 * set of filters specified by the mask. And the codec driver will turn on ASRC
1054 * for these filters if ASRC is selected as their clock source.
1056 int rt5677_sel_asrc_clk_src(struct snd_soc_codec *codec,
1057 unsigned int filter_mask, unsigned int clk_src)
1059 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1060 unsigned int asrc3_mask = 0, asrc3_value = 0;
1061 unsigned int asrc4_mask = 0, asrc4_value = 0;
1062 unsigned int asrc5_mask = 0, asrc5_value = 0;
1063 unsigned int asrc6_mask = 0, asrc6_value = 0;
1064 unsigned int asrc7_mask = 0, asrc7_value = 0;
1065 unsigned int asrc8_mask = 0, asrc8_value = 0;
1068 case RT5677_CLK_SEL_SYS:
1069 case RT5677_CLK_SEL_I2S1_ASRC:
1070 case RT5677_CLK_SEL_I2S2_ASRC:
1071 case RT5677_CLK_SEL_I2S3_ASRC:
1072 case RT5677_CLK_SEL_I2S4_ASRC:
1073 case RT5677_CLK_SEL_I2S5_ASRC:
1074 case RT5677_CLK_SEL_I2S6_ASRC:
1075 case RT5677_CLK_SEL_SYS2:
1076 case RT5677_CLK_SEL_SYS3:
1077 case RT5677_CLK_SEL_SYS4:
1078 case RT5677_CLK_SEL_SYS5:
1079 case RT5677_CLK_SEL_SYS6:
1080 case RT5677_CLK_SEL_SYS7:
1088 if (filter_mask & RT5677_DA_STEREO_FILTER) {
1089 asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
1090 asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
1091 | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
1094 if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
1095 asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
1096 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
1097 | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
1100 if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
1101 asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
1102 asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
1103 | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
1107 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
1111 if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
1112 asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
1113 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
1114 | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
1117 if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
1118 asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
1119 asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
1120 | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
1123 if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
1124 asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
1125 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
1126 | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
1129 if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
1130 asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
1131 asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
1132 | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
1136 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
1140 if (filter_mask & RT5677_AD_STEREO1_FILTER) {
1141 asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
1142 asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
1143 | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
1146 if (filter_mask & RT5677_AD_STEREO2_FILTER) {
1147 asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
1148 asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
1149 | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
1152 if (filter_mask & RT5677_AD_STEREO3_FILTER) {
1153 asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
1154 asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
1155 | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
1158 if (filter_mask & RT5677_AD_STEREO4_FILTER) {
1159 asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
1160 asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
1161 | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
1165 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
1169 if (filter_mask & RT5677_AD_MONO_L_FILTER) {
1170 asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
1171 asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
1172 | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
1175 if (filter_mask & RT5677_AD_MONO_R_FILTER) {
1176 asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
1177 asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
1178 | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
1182 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
1186 if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
1187 asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
1188 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
1189 | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
1192 if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
1193 asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
1194 asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
1195 | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
1199 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
1203 if (filter_mask & RT5677_I2S1_SOURCE) {
1204 asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
1205 asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
1206 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
1209 if (filter_mask & RT5677_I2S2_SOURCE) {
1210 asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
1211 asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
1212 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
1215 if (filter_mask & RT5677_I2S3_SOURCE) {
1216 asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
1217 asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
1218 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
1221 if (filter_mask & RT5677_I2S4_SOURCE) {
1222 asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
1223 asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
1224 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
1228 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
1233 EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);
1235 static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
1236 struct snd_soc_dapm_widget *sink)
1238 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1239 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1240 unsigned int asrc_setting;
1242 switch (source->shift) {
1244 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1245 asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
1246 RT5677_AD_STO1_CLK_SEL_SFT;
1247 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1248 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1253 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1254 asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
1255 RT5677_AD_STO2_CLK_SEL_SFT;
1256 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1257 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1262 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1263 asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
1264 RT5677_AD_STO3_CLK_SEL_SFT;
1265 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1266 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1271 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
1272 asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
1273 RT5677_AD_STO4_CLK_SEL_SFT;
1274 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1275 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1280 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1281 asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
1282 RT5677_AD_MONOL_CLK_SEL_SFT;
1283 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1284 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1289 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
1290 asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
1291 RT5677_AD_MONOR_CLK_SEL_SFT;
1292 if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
1293 asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
1305 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
1306 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1307 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
1308 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1309 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
1312 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
1313 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
1314 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
1315 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
1316 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
1319 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
1320 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1321 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
1322 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1323 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
1326 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
1327 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
1328 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
1329 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
1330 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
1333 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
1334 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1335 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
1336 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1337 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
1340 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
1341 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
1342 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
1343 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
1344 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
1347 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
1348 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1349 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
1350 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1351 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
1354 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
1355 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
1356 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
1357 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
1358 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
1361 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
1362 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1363 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
1364 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1365 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
1368 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
1369 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
1370 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
1371 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
1372 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
1375 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
1376 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1377 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
1378 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1379 RT5677_M_DAC1_L_SFT, 1, 1),
1382 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
1383 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1384 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
1385 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
1386 RT5677_M_DAC1_R_SFT, 1, 1),
1389 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
1390 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
1391 RT5677_M_ST_DAC1_L_SFT, 1, 1),
1392 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1393 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
1394 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
1395 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
1396 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1397 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
1400 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
1401 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
1402 RT5677_M_ST_DAC1_R_SFT, 1, 1),
1403 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
1404 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
1405 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
1406 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
1407 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
1408 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
1411 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
1412 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
1413 RT5677_M_ST_DAC2_L_SFT, 1, 1),
1414 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
1415 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
1416 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1417 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
1418 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1419 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
1422 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
1423 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
1424 RT5677_M_ST_DAC2_R_SFT, 1, 1),
1425 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
1426 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
1427 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
1428 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
1429 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
1430 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
1433 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
1434 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
1435 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
1436 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
1437 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
1438 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1439 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
1440 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1441 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
1444 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
1445 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
1446 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
1447 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
1448 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
1449 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
1450 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
1451 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
1452 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
1455 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
1456 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
1457 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
1458 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
1459 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
1460 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1461 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
1462 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1463 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
1466 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
1467 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
1468 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
1469 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
1470 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
1471 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
1472 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
1473 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
1474 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
1477 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
1478 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1479 RT5677_DSP_IB_01_H_SFT, 1, 1),
1480 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1481 RT5677_DSP_IB_23_H_SFT, 1, 1),
1482 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1483 RT5677_DSP_IB_45_H_SFT, 1, 1),
1484 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1485 RT5677_DSP_IB_6_H_SFT, 1, 1),
1486 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1487 RT5677_DSP_IB_7_H_SFT, 1, 1),
1488 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1489 RT5677_DSP_IB_8_H_SFT, 1, 1),
1490 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1491 RT5677_DSP_IB_9_H_SFT, 1, 1),
1494 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
1495 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1496 RT5677_DSP_IB_01_L_SFT, 1, 1),
1497 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1498 RT5677_DSP_IB_23_L_SFT, 1, 1),
1499 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1500 RT5677_DSP_IB_45_L_SFT, 1, 1),
1501 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1502 RT5677_DSP_IB_6_L_SFT, 1, 1),
1503 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1504 RT5677_DSP_IB_7_L_SFT, 1, 1),
1505 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1506 RT5677_DSP_IB_8_L_SFT, 1, 1),
1507 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
1508 RT5677_DSP_IB_9_L_SFT, 1, 1),
1511 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
1512 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1513 RT5677_DSP_IB_01_H_SFT, 1, 1),
1514 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1515 RT5677_DSP_IB_23_H_SFT, 1, 1),
1516 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1517 RT5677_DSP_IB_45_H_SFT, 1, 1),
1518 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1519 RT5677_DSP_IB_6_H_SFT, 1, 1),
1520 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1521 RT5677_DSP_IB_7_H_SFT, 1, 1),
1522 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1523 RT5677_DSP_IB_8_H_SFT, 1, 1),
1524 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1525 RT5677_DSP_IB_9_H_SFT, 1, 1),
1528 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
1529 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1530 RT5677_DSP_IB_01_L_SFT, 1, 1),
1531 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1532 RT5677_DSP_IB_23_L_SFT, 1, 1),
1533 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1534 RT5677_DSP_IB_45_L_SFT, 1, 1),
1535 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1536 RT5677_DSP_IB_6_L_SFT, 1, 1),
1537 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1538 RT5677_DSP_IB_7_L_SFT, 1, 1),
1539 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1540 RT5677_DSP_IB_8_L_SFT, 1, 1),
1541 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
1542 RT5677_DSP_IB_9_L_SFT, 1, 1),
1545 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
1546 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1547 RT5677_DSP_IB_01_H_SFT, 1, 1),
1548 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1549 RT5677_DSP_IB_23_H_SFT, 1, 1),
1550 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1551 RT5677_DSP_IB_45_H_SFT, 1, 1),
1552 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1553 RT5677_DSP_IB_6_H_SFT, 1, 1),
1554 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1555 RT5677_DSP_IB_7_H_SFT, 1, 1),
1556 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1557 RT5677_DSP_IB_8_H_SFT, 1, 1),
1558 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1559 RT5677_DSP_IB_9_H_SFT, 1, 1),
1562 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
1563 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1564 RT5677_DSP_IB_01_L_SFT, 1, 1),
1565 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1566 RT5677_DSP_IB_23_L_SFT, 1, 1),
1567 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1568 RT5677_DSP_IB_45_L_SFT, 1, 1),
1569 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1570 RT5677_DSP_IB_6_L_SFT, 1, 1),
1571 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1572 RT5677_DSP_IB_7_L_SFT, 1, 1),
1573 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1574 RT5677_DSP_IB_8_L_SFT, 1, 1),
1575 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
1576 RT5677_DSP_IB_9_L_SFT, 1, 1),
1581 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1582 static const char * const rt5677_dac1_src[] = {
1583 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
1587 static SOC_ENUM_SINGLE_DECL(
1588 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1589 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
1591 static const struct snd_kcontrol_new rt5677_dac1_mux =
1592 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
1594 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1595 static const char * const rt5677_adda1_src[] = {
1596 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
1599 static SOC_ENUM_SINGLE_DECL(
1600 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
1601 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
1603 static const struct snd_kcontrol_new rt5677_adda1_mux =
1604 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
1607 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1608 static const char * const rt5677_dac2l_src[] = {
1609 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
1613 static SOC_ENUM_SINGLE_DECL(
1614 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
1615 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
1617 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
1618 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
1620 static const char * const rt5677_dac2r_src[] = {
1621 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
1622 "OB 3", "Haptic Generator", "VAD ADC"
1625 static SOC_ENUM_SINGLE_DECL(
1626 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1627 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1629 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1630 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
1632 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1633 static const char * const rt5677_dac3l_src[] = {
1634 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1638 static SOC_ENUM_SINGLE_DECL(
1639 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1640 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1642 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1643 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1645 static const char * const rt5677_dac3r_src[] = {
1646 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1650 static SOC_ENUM_SINGLE_DECL(
1651 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1652 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1654 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1655 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1657 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1658 static const char * const rt5677_dac4l_src[] = {
1659 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1663 static SOC_ENUM_SINGLE_DECL(
1664 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1665 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1667 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1668 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1670 static const char * const rt5677_dac4r_src[] = {
1671 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1675 static SOC_ENUM_SINGLE_DECL(
1676 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1677 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1679 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1680 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1682 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1683 static const char * const rt5677_iob_bypass_src[] = {
1684 "Bypass", "Pass SRC"
1687 static SOC_ENUM_SINGLE_DECL(
1688 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1689 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1691 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1692 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1694 static SOC_ENUM_SINGLE_DECL(
1695 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1696 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1698 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1699 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1701 static SOC_ENUM_SINGLE_DECL(
1702 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1703 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1705 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1706 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1708 static SOC_ENUM_SINGLE_DECL(
1709 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1710 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1712 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1713 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1715 static SOC_ENUM_SINGLE_DECL(
1716 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1717 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1719 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1720 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1722 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1723 static const char * const rt5677_stereo_adc2_src[] = {
1724 "DD MIX1", "DMIC", "Stereo DAC MIX"
1727 static SOC_ENUM_SINGLE_DECL(
1728 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1729 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1731 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1732 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1734 static SOC_ENUM_SINGLE_DECL(
1735 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1736 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1738 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1739 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1741 static SOC_ENUM_SINGLE_DECL(
1742 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1743 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1745 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1746 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1748 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1749 static const char * const rt5677_dmic_src[] = {
1750 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1753 static SOC_ENUM_SINGLE_DECL(
1754 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1755 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1757 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1758 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1760 static SOC_ENUM_SINGLE_DECL(
1761 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1762 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1764 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1765 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1767 static SOC_ENUM_SINGLE_DECL(
1768 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1769 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1771 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1772 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1774 static SOC_ENUM_SINGLE_DECL(
1775 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1776 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1778 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1779 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1781 static SOC_ENUM_SINGLE_DECL(
1782 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1783 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1785 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1786 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1788 static SOC_ENUM_SINGLE_DECL(
1789 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1790 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1792 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1793 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1795 /* Stereo2 ADC Source */ /* MX-26 [0] */
1796 static const char * const rt5677_stereo2_adc_lr_src[] = {
1800 static SOC_ENUM_SINGLE_DECL(
1801 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1802 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1804 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1805 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1807 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1808 static const char * const rt5677_stereo_adc1_src[] = {
1809 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1812 static SOC_ENUM_SINGLE_DECL(
1813 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1814 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1816 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1817 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1819 static SOC_ENUM_SINGLE_DECL(
1820 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1821 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1823 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1824 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1826 static SOC_ENUM_SINGLE_DECL(
1827 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1828 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1830 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1831 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1833 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1834 static const char * const rt5677_mono_adc2_l_src[] = {
1835 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1838 static SOC_ENUM_SINGLE_DECL(
1839 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1840 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1842 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1843 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1845 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1846 static const char * const rt5677_mono_adc1_l_src[] = {
1847 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1850 static SOC_ENUM_SINGLE_DECL(
1851 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1852 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1854 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1855 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1857 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1858 static const char * const rt5677_mono_adc2_r_src[] = {
1859 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1862 static SOC_ENUM_SINGLE_DECL(
1863 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1864 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1866 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1867 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1869 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1870 static const char * const rt5677_mono_adc1_r_src[] = {
1871 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1874 static SOC_ENUM_SINGLE_DECL(
1875 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1876 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1878 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1879 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1881 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1882 static const char * const rt5677_stereo4_adc2_src[] = {
1883 "DD MIX1", "DMIC", "DD MIX2"
1886 static SOC_ENUM_SINGLE_DECL(
1887 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1888 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1890 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1891 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1894 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1895 static const char * const rt5677_stereo4_adc1_src[] = {
1896 "DD MIX1", "ADC1/2", "DD MIX2"
1899 static SOC_ENUM_SINGLE_DECL(
1900 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1901 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1903 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1904 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1906 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1907 static const char * const rt5677_inbound01_src[] = {
1908 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1912 static SOC_ENUM_SINGLE_DECL(
1913 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1914 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1916 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1917 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1919 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1920 static const char * const rt5677_inbound23_src[] = {
1921 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1922 "DAC1 FS", "IF4 DAC"
1925 static SOC_ENUM_SINGLE_DECL(
1926 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1927 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1929 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1930 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1932 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1933 static const char * const rt5677_inbound45_src[] = {
1934 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1938 static SOC_ENUM_SINGLE_DECL(
1939 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1940 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1942 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1943 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1945 /* InBound6 Source */ /* MX-A3 [2:0] */
1946 static const char * const rt5677_inbound6_src[] = {
1947 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1948 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1951 static SOC_ENUM_SINGLE_DECL(
1952 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1953 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1955 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1956 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1958 /* InBound7 Source */ /* MX-A4 [14:12] */
1959 static const char * const rt5677_inbound7_src[] = {
1960 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1961 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1964 static SOC_ENUM_SINGLE_DECL(
1965 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1966 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1968 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1969 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1971 /* InBound8 Source */ /* MX-A4 [10:8] */
1972 static const char * const rt5677_inbound8_src[] = {
1973 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1974 "MONO ADC MIX L", "DACL1 FS"
1977 static SOC_ENUM_SINGLE_DECL(
1978 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1979 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1981 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1982 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1984 /* InBound9 Source */ /* MX-A4 [6:4] */
1985 static const char * const rt5677_inbound9_src[] = {
1986 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1987 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1990 static SOC_ENUM_SINGLE_DECL(
1991 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1992 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1994 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1995 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1997 /* VAD Source */ /* MX-9F [6:4] */
1998 static const char * const rt5677_vad_src[] = {
1999 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
2003 static SOC_ENUM_SINGLE_DECL(
2004 rt5677_vad_enum, RT5677_VAD_CTRL4,
2005 RT5677_VAD_SRC_SFT, rt5677_vad_src);
2007 static const struct snd_kcontrol_new rt5677_vad_src_mux =
2008 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
2010 /* Sidetone Source */ /* MX-13 [11:9] */
2011 static const char * const rt5677_sidetone_src[] = {
2012 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
2015 static SOC_ENUM_SINGLE_DECL(
2016 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
2017 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
2019 static const struct snd_kcontrol_new rt5677_sidetone_mux =
2020 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
2022 /* DAC1/2 Source */ /* MX-15 [1:0] */
2023 static const char * const rt5677_dac12_src[] = {
2024 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2027 static SOC_ENUM_SINGLE_DECL(
2028 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
2029 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
2031 static const struct snd_kcontrol_new rt5677_dac12_mux =
2032 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
2034 /* DAC3 Source */ /* MX-15 [5:4] */
2035 static const char * const rt5677_dac3_src[] = {
2036 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
2039 static SOC_ENUM_SINGLE_DECL(
2040 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
2041 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
2043 static const struct snd_kcontrol_new rt5677_dac3_mux =
2044 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
2046 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2047 static const char * const rt5677_pdm_src[] = {
2048 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
2051 static SOC_ENUM_SINGLE_DECL(
2052 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
2053 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
2055 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
2056 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
2058 static SOC_ENUM_SINGLE_DECL(
2059 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
2060 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
2062 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
2063 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
2065 static SOC_ENUM_SINGLE_DECL(
2066 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
2067 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
2069 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
2070 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
2072 static SOC_ENUM_SINGLE_DECL(
2073 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
2074 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
2076 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
2077 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
2079 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2080 static const char * const rt5677_if12_adc1_src[] = {
2081 "STO1 ADC MIX", "OB01", "VAD ADC"
2084 static SOC_ENUM_SINGLE_DECL(
2085 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
2086 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
2088 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
2089 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
2091 static SOC_ENUM_SINGLE_DECL(
2092 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
2093 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
2095 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
2096 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
2098 static SOC_ENUM_SINGLE_DECL(
2099 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
2100 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
2102 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
2103 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
2105 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2106 static const char * const rt5677_if12_adc2_src[] = {
2107 "STO2 ADC MIX", "OB23"
2110 static SOC_ENUM_SINGLE_DECL(
2111 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
2112 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
2114 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
2115 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
2117 static SOC_ENUM_SINGLE_DECL(
2118 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
2119 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
2121 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
2122 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
2124 static SOC_ENUM_SINGLE_DECL(
2125 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
2126 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
2128 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
2129 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
2131 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2132 static const char * const rt5677_if12_adc3_src[] = {
2133 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
2136 static SOC_ENUM_SINGLE_DECL(
2137 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
2138 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
2140 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
2141 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
2143 static SOC_ENUM_SINGLE_DECL(
2144 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
2145 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
2147 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
2148 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
2150 static SOC_ENUM_SINGLE_DECL(
2151 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
2152 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
2154 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
2155 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
2157 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2158 static const char * const rt5677_if12_adc4_src[] = {
2159 "STO4 ADC MIX", "OB67", "OB01"
2162 static SOC_ENUM_SINGLE_DECL(
2163 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
2164 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
2166 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
2167 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
2169 static SOC_ENUM_SINGLE_DECL(
2170 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
2171 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
2173 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
2174 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
2176 static SOC_ENUM_SINGLE_DECL(
2177 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
2178 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
2180 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
2181 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
2183 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2184 static const char * const rt5677_if34_adc_src[] = {
2185 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
2186 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
2189 static SOC_ENUM_SINGLE_DECL(
2190 rt5677_if3_adc_enum, RT5677_IF3_DATA,
2191 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
2193 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
2194 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
2196 static SOC_ENUM_SINGLE_DECL(
2197 rt5677_if4_adc_enum, RT5677_IF4_DATA,
2198 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
2200 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
2201 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
2203 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2204 static const char * const rt5677_if12_adc_swap_src[] = {
2205 "L/R", "R/L", "L/L", "R/R"
2208 static SOC_ENUM_SINGLE_DECL(
2209 rt5677_if1_adc1_swap_enum, RT5677_TDM1_CTRL1,
2210 RT5677_IF1_ADC1_SWAP_SFT, rt5677_if12_adc_swap_src);
2212 static const struct snd_kcontrol_new rt5677_if1_adc1_swap_mux =
2213 SOC_DAPM_ENUM("IF1 ADC1 Swap Source", rt5677_if1_adc1_swap_enum);
2215 static SOC_ENUM_SINGLE_DECL(
2216 rt5677_if1_adc2_swap_enum, RT5677_TDM1_CTRL1,
2217 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2219 static const struct snd_kcontrol_new rt5677_if1_adc2_swap_mux =
2220 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if1_adc2_swap_enum);
2222 static SOC_ENUM_SINGLE_DECL(
2223 rt5677_if1_adc3_swap_enum, RT5677_TDM1_CTRL1,
2224 RT5677_IF1_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2226 static const struct snd_kcontrol_new rt5677_if1_adc3_swap_mux =
2227 SOC_DAPM_ENUM("IF1 ADC3 Swap Source", rt5677_if1_adc3_swap_enum);
2229 static SOC_ENUM_SINGLE_DECL(
2230 rt5677_if1_adc4_swap_enum, RT5677_TDM1_CTRL1,
2231 RT5677_IF1_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2233 static const struct snd_kcontrol_new rt5677_if1_adc4_swap_mux =
2234 SOC_DAPM_ENUM("IF1 ADC4 Swap Source", rt5677_if1_adc4_swap_enum);
2236 static SOC_ENUM_SINGLE_DECL(
2237 rt5677_if2_adc1_swap_enum, RT5677_TDM2_CTRL1,
2238 RT5677_IF1_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2240 static const struct snd_kcontrol_new rt5677_if2_adc1_swap_mux =
2241 SOC_DAPM_ENUM("IF1 ADC2 Swap Source", rt5677_if2_adc1_swap_enum);
2243 static SOC_ENUM_SINGLE_DECL(
2244 rt5677_if2_adc2_swap_enum, RT5677_TDM2_CTRL1,
2245 RT5677_IF2_ADC2_SWAP_SFT, rt5677_if12_adc_swap_src);
2247 static const struct snd_kcontrol_new rt5677_if2_adc2_swap_mux =
2248 SOC_DAPM_ENUM("IF2 ADC2 Swap Source", rt5677_if2_adc2_swap_enum);
2250 static SOC_ENUM_SINGLE_DECL(
2251 rt5677_if2_adc3_swap_enum, RT5677_TDM2_CTRL1,
2252 RT5677_IF2_ADC3_SWAP_SFT, rt5677_if12_adc_swap_src);
2254 static const struct snd_kcontrol_new rt5677_if2_adc3_swap_mux =
2255 SOC_DAPM_ENUM("IF2 ADC3 Swap Source", rt5677_if2_adc3_swap_enum);
2257 static SOC_ENUM_SINGLE_DECL(
2258 rt5677_if2_adc4_swap_enum, RT5677_TDM2_CTRL1,
2259 RT5677_IF2_ADC4_SWAP_SFT, rt5677_if12_adc_swap_src);
2261 static const struct snd_kcontrol_new rt5677_if2_adc4_swap_mux =
2262 SOC_DAPM_ENUM("IF2 ADC4 Swap Source", rt5677_if2_adc4_swap_enum);
2264 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2265 static const char * const rt5677_if1_adc_tdm_swap_src[] = {
2266 "1/2/3/4", "2/1/3/4", "2/3/1/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2267 "3/1/2/4", "3/4/1/2"
2270 static SOC_ENUM_SINGLE_DECL(
2271 rt5677_if1_adc_tdm_swap_enum, RT5677_TDM1_CTRL2,
2272 RT5677_IF1_ADC_CTRL_SFT, rt5677_if1_adc_tdm_swap_src);
2274 static const struct snd_kcontrol_new rt5677_if1_adc_tdm_swap_mux =
2275 SOC_DAPM_ENUM("IF1 ADC TDM Swap Source", rt5677_if1_adc_tdm_swap_enum);
2277 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2278 static const char * const rt5677_if2_adc_tdm_swap_src[] = {
2279 "1/2/3/4", "2/1/3/4", "3/1/2/4", "4/1/2/3", "1/3/2/4", "1/4/2/3",
2280 "2/3/1/4", "3/4/1/2"
2283 static SOC_ENUM_SINGLE_DECL(
2284 rt5677_if2_adc_tdm_swap_enum, RT5677_TDM2_CTRL2,
2285 RT5677_IF2_ADC_CTRL_SFT, rt5677_if2_adc_tdm_swap_src);
2287 static const struct snd_kcontrol_new rt5677_if2_adc_tdm_swap_mux =
2288 SOC_DAPM_ENUM("IF2 ADC TDM Swap Source", rt5677_if2_adc_tdm_swap_enum);
2290 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2291 MX-3F[14:12][10:8][6:4][2:0]
2292 MX-43[14:12][10:8][6:4][2:0]
2293 MX-44[14:12][10:8][6:4][2:0] */
2294 static const char * const rt5677_if12_dac_tdm_sel_src[] = {
2295 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
2298 static SOC_ENUM_SINGLE_DECL(
2299 rt5677_if1_dac0_tdm_sel_enum, RT5677_TDM1_CTRL4,
2300 RT5677_IF1_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2302 static const struct snd_kcontrol_new rt5677_if1_dac0_tdm_sel_mux =
2303 SOC_DAPM_ENUM("IF1 DAC0 TDM Source", rt5677_if1_dac0_tdm_sel_enum);
2305 static SOC_ENUM_SINGLE_DECL(
2306 rt5677_if1_dac1_tdm_sel_enum, RT5677_TDM1_CTRL4,
2307 RT5677_IF1_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2309 static const struct snd_kcontrol_new rt5677_if1_dac1_tdm_sel_mux =
2310 SOC_DAPM_ENUM("IF1 DAC1 TDM Source", rt5677_if1_dac1_tdm_sel_enum);
2312 static SOC_ENUM_SINGLE_DECL(
2313 rt5677_if1_dac2_tdm_sel_enum, RT5677_TDM1_CTRL4,
2314 RT5677_IF1_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2316 static const struct snd_kcontrol_new rt5677_if1_dac2_tdm_sel_mux =
2317 SOC_DAPM_ENUM("IF1 DAC2 TDM Source", rt5677_if1_dac2_tdm_sel_enum);
2319 static SOC_ENUM_SINGLE_DECL(
2320 rt5677_if1_dac3_tdm_sel_enum, RT5677_TDM1_CTRL4,
2321 RT5677_IF1_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2323 static const struct snd_kcontrol_new rt5677_if1_dac3_tdm_sel_mux =
2324 SOC_DAPM_ENUM("IF1 DAC3 TDM Source", rt5677_if1_dac3_tdm_sel_enum);
2326 static SOC_ENUM_SINGLE_DECL(
2327 rt5677_if1_dac4_tdm_sel_enum, RT5677_TDM1_CTRL5,
2328 RT5677_IF1_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2330 static const struct snd_kcontrol_new rt5677_if1_dac4_tdm_sel_mux =
2331 SOC_DAPM_ENUM("IF1 DAC4 TDM Source", rt5677_if1_dac4_tdm_sel_enum);
2333 static SOC_ENUM_SINGLE_DECL(
2334 rt5677_if1_dac5_tdm_sel_enum, RT5677_TDM1_CTRL5,
2335 RT5677_IF1_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2337 static const struct snd_kcontrol_new rt5677_if1_dac5_tdm_sel_mux =
2338 SOC_DAPM_ENUM("IF1 DAC5 TDM Source", rt5677_if1_dac5_tdm_sel_enum);
2340 static SOC_ENUM_SINGLE_DECL(
2341 rt5677_if1_dac6_tdm_sel_enum, RT5677_TDM1_CTRL5,
2342 RT5677_IF1_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2344 static const struct snd_kcontrol_new rt5677_if1_dac6_tdm_sel_mux =
2345 SOC_DAPM_ENUM("IF1 DAC6 TDM Source", rt5677_if1_dac6_tdm_sel_enum);
2347 static SOC_ENUM_SINGLE_DECL(
2348 rt5677_if1_dac7_tdm_sel_enum, RT5677_TDM1_CTRL5,
2349 RT5677_IF1_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2351 static const struct snd_kcontrol_new rt5677_if1_dac7_tdm_sel_mux =
2352 SOC_DAPM_ENUM("IF1 DAC7 TDM Source", rt5677_if1_dac7_tdm_sel_enum);
2354 static SOC_ENUM_SINGLE_DECL(
2355 rt5677_if2_dac0_tdm_sel_enum, RT5677_TDM2_CTRL4,
2356 RT5677_IF2_DAC0_SFT, rt5677_if12_dac_tdm_sel_src);
2358 static const struct snd_kcontrol_new rt5677_if2_dac0_tdm_sel_mux =
2359 SOC_DAPM_ENUM("IF2 DAC0 TDM Source", rt5677_if2_dac0_tdm_sel_enum);
2361 static SOC_ENUM_SINGLE_DECL(
2362 rt5677_if2_dac1_tdm_sel_enum, RT5677_TDM2_CTRL4,
2363 RT5677_IF2_DAC1_SFT, rt5677_if12_dac_tdm_sel_src);
2365 static const struct snd_kcontrol_new rt5677_if2_dac1_tdm_sel_mux =
2366 SOC_DAPM_ENUM("IF2 DAC1 TDM Source", rt5677_if2_dac1_tdm_sel_enum);
2368 static SOC_ENUM_SINGLE_DECL(
2369 rt5677_if2_dac2_tdm_sel_enum, RT5677_TDM2_CTRL4,
2370 RT5677_IF2_DAC2_SFT, rt5677_if12_dac_tdm_sel_src);
2372 static const struct snd_kcontrol_new rt5677_if2_dac2_tdm_sel_mux =
2373 SOC_DAPM_ENUM("IF2 DAC2 TDM Source", rt5677_if2_dac2_tdm_sel_enum);
2375 static SOC_ENUM_SINGLE_DECL(
2376 rt5677_if2_dac3_tdm_sel_enum, RT5677_TDM2_CTRL4,
2377 RT5677_IF2_DAC3_SFT, rt5677_if12_dac_tdm_sel_src);
2379 static const struct snd_kcontrol_new rt5677_if2_dac3_tdm_sel_mux =
2380 SOC_DAPM_ENUM("IF2 DAC3 TDM Source", rt5677_if2_dac3_tdm_sel_enum);
2382 static SOC_ENUM_SINGLE_DECL(
2383 rt5677_if2_dac4_tdm_sel_enum, RT5677_TDM2_CTRL5,
2384 RT5677_IF2_DAC4_SFT, rt5677_if12_dac_tdm_sel_src);
2386 static const struct snd_kcontrol_new rt5677_if2_dac4_tdm_sel_mux =
2387 SOC_DAPM_ENUM("IF2 DAC4 TDM Source", rt5677_if2_dac4_tdm_sel_enum);
2389 static SOC_ENUM_SINGLE_DECL(
2390 rt5677_if2_dac5_tdm_sel_enum, RT5677_TDM2_CTRL5,
2391 RT5677_IF2_DAC5_SFT, rt5677_if12_dac_tdm_sel_src);
2393 static const struct snd_kcontrol_new rt5677_if2_dac5_tdm_sel_mux =
2394 SOC_DAPM_ENUM("IF2 DAC5 TDM Source", rt5677_if2_dac5_tdm_sel_enum);
2396 static SOC_ENUM_SINGLE_DECL(
2397 rt5677_if2_dac6_tdm_sel_enum, RT5677_TDM2_CTRL5,
2398 RT5677_IF2_DAC6_SFT, rt5677_if12_dac_tdm_sel_src);
2400 static const struct snd_kcontrol_new rt5677_if2_dac6_tdm_sel_mux =
2401 SOC_DAPM_ENUM("IF2 DAC6 TDM Source", rt5677_if2_dac6_tdm_sel_enum);
2403 static SOC_ENUM_SINGLE_DECL(
2404 rt5677_if2_dac7_tdm_sel_enum, RT5677_TDM2_CTRL5,
2405 RT5677_IF2_DAC7_SFT, rt5677_if12_dac_tdm_sel_src);
2407 static const struct snd_kcontrol_new rt5677_if2_dac7_tdm_sel_mux =
2408 SOC_DAPM_ENUM("IF2 DAC7 TDM Source", rt5677_if2_dac7_tdm_sel_enum);
2410 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
2411 struct snd_kcontrol *kcontrol, int event)
2413 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2414 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2417 case SND_SOC_DAPM_POST_PMU:
2418 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2419 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
2422 case SND_SOC_DAPM_PRE_PMD:
2423 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2424 RT5677_PWR_BST1_P, 0);
2434 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
2435 struct snd_kcontrol *kcontrol, int event)
2437 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2438 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2441 case SND_SOC_DAPM_POST_PMU:
2442 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2443 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
2446 case SND_SOC_DAPM_PRE_PMD:
2447 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2448 RT5677_PWR_BST2_P, 0);
2458 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
2459 struct snd_kcontrol *kcontrol, int event)
2461 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2462 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2465 case SND_SOC_DAPM_PRE_PMU:
2466 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
2469 case SND_SOC_DAPM_POST_PMU:
2470 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
2480 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
2481 struct snd_kcontrol *kcontrol, int event)
2483 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2484 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2487 case SND_SOC_DAPM_PRE_PMU:
2488 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
2491 case SND_SOC_DAPM_POST_PMU:
2492 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
2502 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
2503 struct snd_kcontrol *kcontrol, int event)
2505 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2506 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2509 case SND_SOC_DAPM_POST_PMU:
2510 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2511 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2512 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
2513 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
2516 case SND_SOC_DAPM_PRE_PMD:
2517 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
2518 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
2519 RT5677_PWR_CLK_MB, 0);
2529 static int rt5677_if1_adc_tdm_event(struct snd_soc_dapm_widget *w,
2530 struct snd_kcontrol *kcontrol, int event)
2532 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2533 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2537 case SND_SOC_DAPM_PRE_PMU:
2538 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value);
2539 if (value & RT5677_IF1_ADC_CTRL_MASK)
2540 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1,
2541 RT5677_IF1_ADC_MODE_MASK,
2542 RT5677_IF1_ADC_MODE_TDM);
2552 static int rt5677_if2_adc_tdm_event(struct snd_soc_dapm_widget *w,
2553 struct snd_kcontrol *kcontrol, int event)
2555 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2556 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2560 case SND_SOC_DAPM_PRE_PMU:
2561 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value);
2562 if (value & RT5677_IF2_ADC_CTRL_MASK)
2563 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1,
2564 RT5677_IF2_ADC_MODE_MASK,
2565 RT5677_IF2_ADC_MODE_TDM);
2575 static int rt5677_vref_event(struct snd_soc_dapm_widget *w,
2576 struct snd_kcontrol *kcontrol, int event)
2578 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2579 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2582 case SND_SOC_DAPM_POST_PMU:
2583 if (snd_soc_codec_get_bias_level(codec) != SND_SOC_BIAS_ON &&
2584 !rt5677->is_vref_slow) {
2586 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
2587 RT5677_PWR_FV1 | RT5677_PWR_FV2,
2588 RT5677_PWR_FV1 | RT5677_PWR_FV2);
2589 rt5677->is_vref_slow = true;
2600 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
2601 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2602 0, rt5677_set_pll1_event, SND_SOC_DAPM_PRE_PMU |
2603 SND_SOC_DAPM_POST_PMU),
2604 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2605 0, rt5677_set_pll2_event, SND_SOC_DAPM_PRE_PMU |
2606 SND_SOC_DAPM_POST_PMU),
2609 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5677_ASRC_1, 0, 0, NULL, 0),
2610 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5677_ASRC_1, 1, 0, NULL, 0),
2611 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5677_ASRC_1, 2, 0, NULL, 0),
2612 SND_SOC_DAPM_SUPPLY_S("I2S4 ASRC", 1, RT5677_ASRC_1, 3, 0, NULL, 0),
2613 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5677_ASRC_2, 14, 0, NULL, 0),
2614 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 L ASRC", 1, RT5677_ASRC_2, 13, 0, NULL,
2616 SND_SOC_DAPM_SUPPLY_S("DAC MONO2 R ASRC", 1, RT5677_ASRC_2, 12, 0, NULL,
2618 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 L ASRC", 1, RT5677_ASRC_1, 15, 0, NULL,
2620 SND_SOC_DAPM_SUPPLY_S("DAC MONO3 R ASRC", 1, RT5677_ASRC_1, 14, 0, NULL,
2622 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 L ASRC", 1, RT5677_ASRC_1, 13, 0, NULL,
2624 SND_SOC_DAPM_SUPPLY_S("DAC MONO4 R ASRC", 1, RT5677_ASRC_1, 12, 0, NULL,
2626 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5677_ASRC_2, 11, 0, NULL,
2628 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5677_ASRC_2, 10, 0, NULL,
2630 SND_SOC_DAPM_SUPPLY_S("DMIC STO3 ASRC", 1, RT5677_ASRC_2, 9, 0, NULL,
2632 SND_SOC_DAPM_SUPPLY_S("DMIC STO4 ASRC", 1, RT5677_ASRC_2, 8, 0, NULL,
2634 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5677_ASRC_2, 7, 0, NULL,
2636 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5677_ASRC_2, 6, 0, NULL,
2638 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5677_ASRC_2, 5, 0, NULL, 0),
2639 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5677_ASRC_2, 4, 0, NULL, 0),
2640 SND_SOC_DAPM_SUPPLY_S("ADC STO3 ASRC", 1, RT5677_ASRC_2, 3, 0, NULL, 0),
2641 SND_SOC_DAPM_SUPPLY_S("ADC STO4 ASRC", 1, RT5677_ASRC_2, 2, 0, NULL, 0),
2642 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5677_ASRC_2, 1, 0, NULL,
2644 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5677_ASRC_2, 0, 0, NULL,
2649 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2650 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
2651 SND_SOC_DAPM_POST_PMU),
2654 SND_SOC_DAPM_INPUT("DMIC L1"),
2655 SND_SOC_DAPM_INPUT("DMIC R1"),
2656 SND_SOC_DAPM_INPUT("DMIC L2"),
2657 SND_SOC_DAPM_INPUT("DMIC R2"),
2658 SND_SOC_DAPM_INPUT("DMIC L3"),
2659 SND_SOC_DAPM_INPUT("DMIC R3"),
2660 SND_SOC_DAPM_INPUT("DMIC L4"),
2661 SND_SOC_DAPM_INPUT("DMIC R4"),
2663 SND_SOC_DAPM_INPUT("IN1P"),
2664 SND_SOC_DAPM_INPUT("IN1N"),
2665 SND_SOC_DAPM_INPUT("IN2P"),
2666 SND_SOC_DAPM_INPUT("IN2N"),
2668 SND_SOC_DAPM_INPUT("Haptic Generator"),
2670 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2671 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2672 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2673 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2675 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
2676 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
2677 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
2678 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
2679 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
2680 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
2681 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
2682 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
2684 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2685 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2688 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2689 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
2690 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2691 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
2692 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
2693 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2696 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
2698 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
2700 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
2702 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
2703 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
2704 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
2705 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
2706 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
2707 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
2708 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
2709 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
2712 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2713 &rt5677_sto1_dmic_mux),
2714 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2715 &rt5677_sto1_adc1_mux),
2716 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2717 &rt5677_sto1_adc2_mux),
2718 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2719 &rt5677_sto2_dmic_mux),
2720 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2721 &rt5677_sto2_adc1_mux),
2722 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2723 &rt5677_sto2_adc2_mux),
2724 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2725 &rt5677_sto2_adc_lr_mux),
2726 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
2727 &rt5677_sto3_dmic_mux),
2728 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2729 &rt5677_sto3_adc1_mux),
2730 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2731 &rt5677_sto3_adc2_mux),
2732 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
2733 &rt5677_sto4_dmic_mux),
2734 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2735 &rt5677_sto4_adc1_mux),
2736 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2737 &rt5677_sto4_adc2_mux),
2738 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2739 &rt5677_mono_dmic_l_mux),
2740 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2741 &rt5677_mono_dmic_r_mux),
2742 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
2743 &rt5677_mono_adc2_l_mux),
2744 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
2745 &rt5677_mono_adc1_l_mux),
2746 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
2747 &rt5677_mono_adc1_r_mux),
2748 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
2749 &rt5677_mono_adc2_r_mux),
2752 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
2753 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
2754 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
2755 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
2756 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
2757 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
2758 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
2759 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
2760 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2761 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
2762 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2763 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
2764 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
2765 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
2766 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
2767 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
2768 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
2769 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
2770 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
2771 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
2772 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
2773 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
2774 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
2775 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
2776 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
2777 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2778 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2779 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
2780 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
2781 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2782 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2783 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
2786 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2787 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2788 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2789 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2791 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2792 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2793 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2794 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2795 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2796 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2797 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2798 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2799 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2800 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2801 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2804 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
2805 &rt5677_ib9_src_mux),
2806 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
2807 &rt5677_ib8_src_mux),
2808 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
2809 &rt5677_ib7_src_mux),
2810 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
2811 &rt5677_ib6_src_mux),
2812 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5677_ib45_src_mux),
2814 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5677_ib23_src_mux),
2816 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
2817 &rt5677_ib01_src_mux),
2818 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
2819 &rt5677_ib45_bypass_src_mux),
2820 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5677_ib23_bypass_src_mux),
2822 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5677_ib01_bypass_src_mux),
2824 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5677_ob23_bypass_src_mux),
2826 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
2827 &rt5677_ob01_bypass_src_mux),
2829 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
2830 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
2832 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
2833 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
2834 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
2835 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
2836 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
2837 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
2839 /* Digital Interface */
2840 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
2841 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
2842 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2843 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2851 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2852 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2853 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2854 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2855 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2856 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2857 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2859 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
2860 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2869 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2878 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
2879 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2883 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2884 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2885 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2887 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
2888 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
2889 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2890 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2891 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2892 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2893 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2894 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2896 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
2897 RT5677_PWR_SLB_BIT, 0, NULL, 0),
2898 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2899 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2900 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2901 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2902 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2903 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
2904 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
2905 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
2906 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
2907 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
2908 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
2909 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2912 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2913 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2915 /* Digital Interface Select */
2916 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2917 &rt5677_if1_adc1_mux),
2918 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2919 &rt5677_if1_adc2_mux),
2920 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2921 &rt5677_if1_adc3_mux),
2922 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2923 &rt5677_if1_adc4_mux),
2924 SND_SOC_DAPM_MUX("IF1 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2925 &rt5677_if1_adc1_swap_mux),
2926 SND_SOC_DAPM_MUX("IF1 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2927 &rt5677_if1_adc2_swap_mux),
2928 SND_SOC_DAPM_MUX("IF1 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2929 &rt5677_if1_adc3_swap_mux),
2930 SND_SOC_DAPM_MUX("IF1 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2931 &rt5677_if1_adc4_swap_mux),
2932 SND_SOC_DAPM_MUX_E("IF1 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2933 &rt5677_if1_adc_tdm_swap_mux, rt5677_if1_adc_tdm_event,
2934 SND_SOC_DAPM_PRE_PMU),
2935 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2936 &rt5677_if2_adc1_mux),
2937 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2938 &rt5677_if2_adc2_mux),
2939 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
2940 &rt5677_if2_adc3_mux),
2941 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
2942 &rt5677_if2_adc4_mux),
2943 SND_SOC_DAPM_MUX("IF2 ADC1 Swap Mux", SND_SOC_NOPM, 0, 0,
2944 &rt5677_if2_adc1_swap_mux),
2945 SND_SOC_DAPM_MUX("IF2 ADC2 Swap Mux", SND_SOC_NOPM, 0, 0,
2946 &rt5677_if2_adc2_swap_mux),
2947 SND_SOC_DAPM_MUX("IF2 ADC3 Swap Mux", SND_SOC_NOPM, 0, 0,
2948 &rt5677_if2_adc3_swap_mux),
2949 SND_SOC_DAPM_MUX("IF2 ADC4 Swap Mux", SND_SOC_NOPM, 0, 0,
2950 &rt5677_if2_adc4_swap_mux),
2951 SND_SOC_DAPM_MUX_E("IF2 ADC TDM Swap Mux", SND_SOC_NOPM, 0, 0,
2952 &rt5677_if2_adc_tdm_swap_mux, rt5677_if2_adc_tdm_event,
2953 SND_SOC_DAPM_PRE_PMU),
2954 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5677_if3_adc_mux),
2956 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5677_if4_adc_mux),
2958 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
2959 &rt5677_slb_adc1_mux),
2960 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
2961 &rt5677_slb_adc2_mux),
2962 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
2963 &rt5677_slb_adc3_mux),
2964 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
2965 &rt5677_slb_adc4_mux),
2967 SND_SOC_DAPM_MUX("IF1 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5677_if1_dac0_tdm_sel_mux),
2969 SND_SOC_DAPM_MUX("IF1 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5677_if1_dac1_tdm_sel_mux),
2971 SND_SOC_DAPM_MUX("IF1 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5677_if1_dac2_tdm_sel_mux),
2973 SND_SOC_DAPM_MUX("IF1 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5677_if1_dac3_tdm_sel_mux),
2975 SND_SOC_DAPM_MUX("IF1 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2976 &rt5677_if1_dac4_tdm_sel_mux),
2977 SND_SOC_DAPM_MUX("IF1 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2978 &rt5677_if1_dac5_tdm_sel_mux),
2979 SND_SOC_DAPM_MUX("IF1 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2980 &rt5677_if1_dac6_tdm_sel_mux),
2981 SND_SOC_DAPM_MUX("IF1 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2982 &rt5677_if1_dac7_tdm_sel_mux),
2984 SND_SOC_DAPM_MUX("IF2 DAC0 Mux", SND_SOC_NOPM, 0, 0,
2985 &rt5677_if2_dac0_tdm_sel_mux),
2986 SND_SOC_DAPM_MUX("IF2 DAC1 Mux", SND_SOC_NOPM, 0, 0,
2987 &rt5677_if2_dac1_tdm_sel_mux),
2988 SND_SOC_DAPM_MUX("IF2 DAC2 Mux", SND_SOC_NOPM, 0, 0,
2989 &rt5677_if2_dac2_tdm_sel_mux),
2990 SND_SOC_DAPM_MUX("IF2 DAC3 Mux", SND_SOC_NOPM, 0, 0,
2991 &rt5677_if2_dac3_tdm_sel_mux),
2992 SND_SOC_DAPM_MUX("IF2 DAC4 Mux", SND_SOC_NOPM, 0, 0,
2993 &rt5677_if2_dac4_tdm_sel_mux),
2994 SND_SOC_DAPM_MUX("IF2 DAC5 Mux", SND_SOC_NOPM, 0, 0,
2995 &rt5677_if2_dac5_tdm_sel_mux),
2996 SND_SOC_DAPM_MUX("IF2 DAC6 Mux", SND_SOC_NOPM, 0, 0,
2997 &rt5677_if2_dac6_tdm_sel_mux),
2998 SND_SOC_DAPM_MUX("IF2 DAC7 Mux", SND_SOC_NOPM, 0, 0,
2999 &rt5677_if2_dac7_tdm_sel_mux),
3001 /* Audio Interface */
3002 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
3003 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
3004 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
3005 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
3006 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3007 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
3008 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
3009 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
3010 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
3011 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
3014 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
3015 &rt5677_sidetone_mux),
3016 SND_SOC_DAPM_SUPPLY("Sidetone Power", RT5677_SIDETONE_CTRL,
3017 RT5677_ST_EN_SFT, 0, NULL, 0),
3020 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
3021 &rt5677_vad_src_mux),
3024 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
3025 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
3026 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
3027 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
3028 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
3029 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
3030 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
3031 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
3032 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
3033 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
3034 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
3035 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
3036 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
3039 /* DAC mixer before sound effect */
3040 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3041 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
3042 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3043 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
3044 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
3047 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
3049 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
3051 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
3053 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
3056 /* DAC2 channel Mux */
3057 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
3058 &rt5677_dac2_l_mux),
3059 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
3060 &rt5677_dac2_r_mux),
3062 /* DAC3 channel Mux */
3063 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
3064 &rt5677_dac3_l_mux),
3065 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
3066 &rt5677_dac3_r_mux),
3068 /* DAC4 channel Mux */
3069 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
3070 &rt5677_dac4_l_mux),
3071 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
3072 &rt5677_dac4_r_mux),
3075 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
3076 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
3077 SND_SOC_DAPM_SUPPLY("dac mono2 left filter", RT5677_PWR_DIG2,
3078 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
3079 SND_SOC_DAPM_SUPPLY("dac mono2 right filter", RT5677_PWR_DIG2,
3080 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
3081 SND_SOC_DAPM_SUPPLY("dac mono3 left filter", RT5677_PWR_DIG2,
3082 RT5677_PWR_DAC_M3F_L_BIT, 0, NULL, 0),
3083 SND_SOC_DAPM_SUPPLY("dac mono3 right filter", RT5677_PWR_DIG2,
3084 RT5677_PWR_DAC_M3F_R_BIT, 0, NULL, 0),
3085 SND_SOC_DAPM_SUPPLY("dac mono4 left filter", RT5677_PWR_DIG2,
3086 RT5677_PWR_DAC_M4F_L_BIT, 0, NULL, 0),
3087 SND_SOC_DAPM_SUPPLY("dac mono4 right filter", RT5677_PWR_DIG2,
3088 RT5677_PWR_DAC_M4F_R_BIT, 0, NULL, 0),
3090 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
3091 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
3092 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
3093 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
3094 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3095 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
3096 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3097 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
3098 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
3099 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
3100 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
3101 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
3102 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
3103 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
3104 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
3105 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
3106 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3107 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3108 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3109 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3112 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
3113 RT5677_PWR_DAC1_BIT, 0),
3114 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
3115 RT5677_PWR_DAC2_BIT, 0),
3116 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
3117 RT5677_PWR_DAC3_BIT, 0),
3120 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
3121 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
3122 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
3123 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
3125 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
3126 1, &rt5677_pdm1_l_mux),
3127 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
3128 1, &rt5677_pdm1_r_mux),
3129 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
3130 1, &rt5677_pdm2_l_mux),
3131 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
3132 1, &rt5677_pdm2_r_mux),
3134 SND_SOC_DAPM_PGA_S("LOUT1 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
3136 SND_SOC_DAPM_PGA_S("LOUT2 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
3138 SND_SOC_DAPM_PGA_S("LOUT3 amp", 0, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
3141 SND_SOC_DAPM_PGA_S("LOUT1 vref", 1, SND_SOC_NOPM, 0, 0,
3142 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3143 SND_SOC_DAPM_PGA_S("LOUT2 vref", 1, SND_SOC_NOPM, 0, 0,
3144 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3145 SND_SOC_DAPM_PGA_S("LOUT3 vref", 1, SND_SOC_NOPM, 0, 0,
3146 rt5677_vref_event, SND_SOC_DAPM_POST_PMU),
3149 SND_SOC_DAPM_OUTPUT("LOUT1"),
3150 SND_SOC_DAPM_OUTPUT("LOUT2"),
3151 SND_SOC_DAPM_OUTPUT("LOUT3"),
3152 SND_SOC_DAPM_OUTPUT("PDM1L"),
3153 SND_SOC_DAPM_OUTPUT("PDM1R"),
3154 SND_SOC_DAPM_OUTPUT("PDM2L"),
3155 SND_SOC_DAPM_OUTPUT("PDM2R"),
3157 SND_SOC_DAPM_POST("vref", rt5677_vref_event),
3160 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
3161 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC", rt5677_dmic_use_asrc },
3162 { "Stereo2 DMIC Mux", NULL, "DMIC STO2 ASRC", rt5677_dmic_use_asrc },
3163 { "Stereo3 DMIC Mux", NULL, "DMIC STO3 ASRC", rt5677_dmic_use_asrc },
3164 { "Stereo4 DMIC Mux", NULL, "DMIC STO4 ASRC", rt5677_dmic_use_asrc },
3165 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC", rt5677_dmic_use_asrc },
3166 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC", rt5677_dmic_use_asrc },
3167 { "I2S1", NULL, "I2S1 ASRC", can_use_asrc},
3168 { "I2S2", NULL, "I2S2 ASRC", can_use_asrc},
3169 { "I2S3", NULL, "I2S3 ASRC", can_use_asrc},
3170 { "I2S4", NULL, "I2S4 ASRC", can_use_asrc},
3172 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
3173 { "dac mono2 left filter", NULL, "DAC MONO2 L ASRC", is_using_asrc },
3174 { "dac mono2 right filter", NULL, "DAC MONO2 R ASRC", is_using_asrc },
3175 { "dac mono3 left filter", NULL, "DAC MONO3 L ASRC", is_using_asrc },
3176 { "dac mono3 right filter", NULL, "DAC MONO3 R ASRC", is_using_asrc },
3177 { "dac mono4 left filter", NULL, "DAC MONO4 L ASRC", is_using_asrc },
3178 { "dac mono4 right filter", NULL, "DAC MONO4 R ASRC", is_using_asrc },
3179 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
3180 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
3181 { "adc stereo3 filter", NULL, "ADC STO3 ASRC", is_using_asrc },
3182 { "adc stereo4 filter", NULL, "ADC STO4 ASRC", is_using_asrc },
3183 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
3184 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
3186 { "DMIC1", NULL, "DMIC L1" },
3187 { "DMIC1", NULL, "DMIC R1" },
3188 { "DMIC2", NULL, "DMIC L2" },
3189 { "DMIC2", NULL, "DMIC R2" },
3190 { "DMIC3", NULL, "DMIC L3" },
3191 { "DMIC3", NULL, "DMIC R3" },
3192 { "DMIC4", NULL, "DMIC L4" },
3193 { "DMIC4", NULL, "DMIC R4" },
3195 { "DMIC L1", NULL, "DMIC CLK" },
3196 { "DMIC R1", NULL, "DMIC CLK" },
3197 { "DMIC L2", NULL, "DMIC CLK" },
3198 { "DMIC R2", NULL, "DMIC CLK" },
3199 { "DMIC L3", NULL, "DMIC CLK" },
3200 { "DMIC R3", NULL, "DMIC CLK" },
3201 { "DMIC L4", NULL, "DMIC CLK" },
3202 { "DMIC R4", NULL, "DMIC CLK" },
3204 { "DMIC L1", NULL, "DMIC1 power" },
3205 { "DMIC R1", NULL, "DMIC1 power" },
3206 { "DMIC L3", NULL, "DMIC3 power" },
3207 { "DMIC R3", NULL, "DMIC3 power" },
3208 { "DMIC L4", NULL, "DMIC4 power" },
3209 { "DMIC R4", NULL, "DMIC4 power" },
3211 { "BST1", NULL, "IN1P" },
3212 { "BST1", NULL, "IN1N" },
3213 { "BST2", NULL, "IN2P" },
3214 { "BST2", NULL, "IN2N" },
3216 { "IN1P", NULL, "MICBIAS1" },
3217 { "IN1N", NULL, "MICBIAS1" },
3218 { "IN2P", NULL, "MICBIAS1" },
3219 { "IN2N", NULL, "MICBIAS1" },
3221 { "ADC 1", NULL, "BST1" },
3222 { "ADC 1", NULL, "ADC 1 power" },
3223 { "ADC 1", NULL, "ADC1 clock" },
3224 { "ADC 2", NULL, "BST2" },
3225 { "ADC 2", NULL, "ADC 2 power" },
3226 { "ADC 2", NULL, "ADC2 clock" },
3228 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
3229 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
3230 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
3231 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
3233 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
3234 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
3235 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
3236 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
3238 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
3239 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
3240 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
3241 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
3243 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
3244 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
3245 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
3246 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
3248 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
3249 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
3250 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
3251 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
3253 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
3254 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
3255 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
3256 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
3258 { "ADC 1_2", NULL, "ADC 1" },
3259 { "ADC 1_2", NULL, "ADC 2" },
3261 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3262 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3263 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3265 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3266 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
3267 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3269 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3270 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3271 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3273 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3274 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
3275 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3277 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3278 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3279 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3281 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3282 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3283 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
3285 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
3286 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
3287 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
3289 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
3290 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
3291 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
3293 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
3294 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
3295 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3297 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
3298 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
3299 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
3301 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
3302 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
3303 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3305 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
3306 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
3307 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
3309 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3310 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3311 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
3312 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
3314 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
3315 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
3316 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
3317 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
3318 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3320 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
3321 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
3323 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3324 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3325 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
3326 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
3328 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
3329 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
3331 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
3332 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
3334 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
3335 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
3336 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
3337 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
3338 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
3340 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
3341 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
3343 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3344 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3345 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
3346 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
3348 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
3349 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
3350 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
3351 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
3352 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
3354 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
3355 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
3357 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3358 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3359 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
3360 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
3362 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
3363 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
3364 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
3365 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
3366 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
3368 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
3369 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
3371 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
3372 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
3373 { "Mono ADC MIXL", NULL, "adc mono left filter" },
3374 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
3376 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
3377 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
3378 { "Mono ADC MIXR", NULL, "adc mono right filter" },
3379 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
3381 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
3382 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
3384 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3385 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3386 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3387 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3388 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3390 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3391 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3392 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3394 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3395 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3397 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3398 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3399 { "IF1 ADC3 Mux", "OB45", "OB45" },
3401 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3402 { "IF1 ADC4 Mux", "OB67", "OB67" },
3403 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3405 { "IF1 ADC1 Swap Mux", "L/R", "IF1 ADC1 Mux" },
3406 { "IF1 ADC1 Swap Mux", "R/L", "IF1 ADC1 Mux" },
3407 { "IF1 ADC1 Swap Mux", "L/L", "IF1 ADC1 Mux" },
3408 { "IF1 ADC1 Swap Mux", "R/R", "IF1 ADC1 Mux" },
3410 { "IF1 ADC2 Swap Mux", "L/R", "IF1 ADC2 Mux" },
3411 { "IF1 ADC2 Swap Mux", "R/L", "IF1 ADC2 Mux" },
3412 { "IF1 ADC2 Swap Mux", "L/L", "IF1 ADC2 Mux" },
3413 { "IF1 ADC2 Swap Mux", "R/R", "IF1 ADC2 Mux" },
3415 { "IF1 ADC3 Swap Mux", "L/R", "IF1 ADC3 Mux" },
3416 { "IF1 ADC3 Swap Mux", "R/L", "IF1 ADC3 Mux" },
3417 { "IF1 ADC3 Swap Mux", "L/L", "IF1 ADC3 Mux" },
3418 { "IF1 ADC3 Swap Mux", "R/R", "IF1 ADC3 Mux" },
3420 { "IF1 ADC4 Swap Mux", "L/R", "IF1 ADC4 Mux" },
3421 { "IF1 ADC4 Swap Mux", "R/L", "IF1 ADC4 Mux" },
3422 { "IF1 ADC4 Swap Mux", "L/L", "IF1 ADC4 Mux" },
3423 { "IF1 ADC4 Swap Mux", "R/R", "IF1 ADC4 Mux" },
3425 { "IF1 ADC", NULL, "IF1 ADC1 Swap Mux" },
3426 { "IF1 ADC", NULL, "IF1 ADC2 Swap Mux" },
3427 { "IF1 ADC", NULL, "IF1 ADC3 Swap Mux" },
3428 { "IF1 ADC", NULL, "IF1 ADC4 Swap Mux" },
3430 { "IF1 ADC TDM Swap Mux", "1/2/3/4", "IF1 ADC" },
3431 { "IF1 ADC TDM Swap Mux", "2/1/3/4", "IF1 ADC" },
3432 { "IF1 ADC TDM Swap Mux", "2/3/1/4", "IF1 ADC" },
3433 { "IF1 ADC TDM Swap Mux", "4/1/2/3", "IF1 ADC" },
3434 { "IF1 ADC TDM Swap Mux", "1/3/2/4", "IF1 ADC" },
3435 { "IF1 ADC TDM Swap Mux", "1/4/2/3", "IF1 ADC" },
3436 { "IF1 ADC TDM Swap Mux", "3/1/2/4", "IF1 ADC" },
3437 { "IF1 ADC TDM Swap Mux", "3/4/1/2", "IF1 ADC" },
3439 { "AIF1TX", NULL, "I2S1" },
3440 { "AIF1TX", NULL, "IF1 ADC TDM Swap Mux" },
3442 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3443 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3444 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3446 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3447 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3449 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3450 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3451 { "IF2 ADC3 Mux", "OB45", "OB45" },
3453 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3454 { "IF2 ADC4 Mux", "OB67", "OB67" },
3455 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3457 { "IF2 ADC1 Swap Mux", "L/R", "IF2 ADC1 Mux" },
3458 { "IF2 ADC1 Swap Mux", "R/L", "IF2 ADC1 Mux" },
3459 { "IF2 ADC1 Swap Mux", "L/L", "IF2 ADC1 Mux" },
3460 { "IF2 ADC1 Swap Mux", "R/R", "IF2 ADC1 Mux" },
3462 { "IF2 ADC2 Swap Mux", "L/R", "IF2 ADC2 Mux" },
3463 { "IF2 ADC2 Swap Mux", "R/L", "IF2 ADC2 Mux" },
3464 { "IF2 ADC2 Swap Mux", "L/L", "IF2 ADC2 Mux" },
3465 { "IF2 ADC2 Swap Mux", "R/R", "IF2 ADC2 Mux" },
3467 { "IF2 ADC3 Swap Mux", "L/R", "IF2 ADC3 Mux" },
3468 { "IF2 ADC3 Swap Mux", "R/L", "IF2 ADC3 Mux" },
3469 { "IF2 ADC3 Swap Mux", "L/L", "IF2 ADC3 Mux" },
3470 { "IF2 ADC3 Swap Mux", "R/R", "IF2 ADC3 Mux" },
3472 { "IF2 ADC4 Swap Mux", "L/R", "IF2 ADC4 Mux" },
3473 { "IF2 ADC4 Swap Mux", "R/L", "IF2 ADC4 Mux" },
3474 { "IF2 ADC4 Swap Mux", "L/L", "IF2 ADC4 Mux" },
3475 { "IF2 ADC4 Swap Mux", "R/R", "IF2 ADC4 Mux" },
3477 { "IF2 ADC", NULL, "IF2 ADC1 Swap Mux" },
3478 { "IF2 ADC", NULL, "IF2 ADC2 Swap Mux" },
3479 { "IF2 ADC", NULL, "IF2 ADC3 Swap Mux" },
3480 { "IF2 ADC", NULL, "IF2 ADC4 Swap Mux" },
3482 { "IF2 ADC TDM Swap Mux", "1/2/3/4", "IF2 ADC" },
3483 { "IF2 ADC TDM Swap Mux", "2/1/3/4", "IF2 ADC" },
3484 { "IF2 ADC TDM Swap Mux", "3/1/2/4", "IF2 ADC" },
3485 { "IF2 ADC TDM Swap Mux", "4/1/2/3", "IF2 ADC" },
3486 { "IF2 ADC TDM Swap Mux", "1/3/2/4", "IF2 ADC" },
3487 { "IF2 ADC TDM Swap Mux", "1/4/2/3", "IF2 ADC" },
3488 { "IF2 ADC TDM Swap Mux", "2/3/1/4", "IF2 ADC" },
3489 { "IF2 ADC TDM Swap Mux", "3/4/1/2", "IF2 ADC" },
3491 { "AIF2TX", NULL, "I2S2" },
3492 { "AIF2TX", NULL, "IF2 ADC TDM Swap Mux" },
3494 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3495 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3496 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3497 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3498 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3499 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
3500 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
3501 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3503 { "AIF3TX", NULL, "I2S3" },
3504 { "AIF3TX", NULL, "IF3 ADC Mux" },
3506 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3507 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3508 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3509 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3510 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
3511 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
3512 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
3513 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
3515 { "AIF4TX", NULL, "I2S4" },
3516 { "AIF4TX", NULL, "IF4 ADC Mux" },
3518 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3519 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
3520 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
3522 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3523 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
3525 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3526 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
3527 { "SLB ADC3 Mux", "OB45", "OB45" },
3529 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
3530 { "SLB ADC4 Mux", "OB67", "OB67" },
3531 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
3533 { "SLBTX", NULL, "SLB" },
3534 { "SLBTX", NULL, "SLB ADC1 Mux" },
3535 { "SLBTX", NULL, "SLB ADC2 Mux" },
3536 { "SLBTX", NULL, "SLB ADC3 Mux" },
3537 { "SLBTX", NULL, "SLB ADC4 Mux" },
3539 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
3540 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
3541 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
3542 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3543 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
3545 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
3546 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
3548 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
3549 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
3550 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
3551 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3552 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
3553 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
3555 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
3556 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
3558 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
3559 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
3560 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
3561 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
3562 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
3564 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
3565 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
3567 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3568 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3569 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
3570 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3571 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
3572 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3573 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3574 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3576 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3577 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3578 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
3579 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3580 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
3581 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3582 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3583 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3585 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
3586 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
3587 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
3588 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
3589 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
3590 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
3592 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
3593 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
3594 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
3595 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
3596 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
3597 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
3598 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
3600 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3601 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3602 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3603 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
3604 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
3605 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
3606 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
3608 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3609 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3610 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3611 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
3612 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
3613 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
3614 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
3616 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3617 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3618 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3619 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
3620 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
3621 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
3622 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
3624 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3625 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3626 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3627 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
3628 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
3629 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
3630 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
3632 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3633 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3634 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3635 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
3636 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
3637 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
3638 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
3640 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
3641 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
3642 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
3643 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
3644 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
3645 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
3646 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
3648 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
3649 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
3650 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
3651 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
3653 { "OutBound2", NULL, "OB23 Bypass Mux" },
3654 { "OutBound3", NULL, "OB23 Bypass Mux" },
3655 { "OutBound4", NULL, "OB4 MIX" },
3656 { "OutBound5", NULL, "OB5 MIX" },
3657 { "OutBound6", NULL, "OB6 MIX" },
3658 { "OutBound7", NULL, "OB7 MIX" },
3660 { "OB45", NULL, "OutBound4" },
3661 { "OB45", NULL, "OutBound5" },
3662 { "OB67", NULL, "OutBound6" },
3663 { "OB67", NULL, "OutBound7" },
3665 { "IF1 DAC0", NULL, "AIF1RX" },
3666 { "IF1 DAC1", NULL, "AIF1RX" },
3667 { "IF1 DAC2", NULL, "AIF1RX" },
3668 { "IF1 DAC3", NULL, "AIF1RX" },
3669 { "IF1 DAC4", NULL, "AIF1RX" },
3670 { "IF1 DAC5", NULL, "AIF1RX" },
3671 { "IF1 DAC6", NULL, "AIF1RX" },
3672 { "IF1 DAC7", NULL, "AIF1RX" },
3673 { "IF1 DAC0", NULL, "I2S1" },
3674 { "IF1 DAC1", NULL, "I2S1" },
3675 { "IF1 DAC2", NULL, "I2S1" },
3676 { "IF1 DAC3", NULL, "I2S1" },
3677 { "IF1 DAC4", NULL, "I2S1" },
3678 { "IF1 DAC5", NULL, "I2S1" },
3679 { "IF1 DAC6", NULL, "I2S1" },
3680 { "IF1 DAC7", NULL, "I2S1" },
3682 { "IF1 DAC0 Mux", "Slot0", "IF1 DAC0" },
3683 { "IF1 DAC0 Mux", "Slot1", "IF1 DAC1" },
3684 { "IF1 DAC0 Mux", "Slot2", "IF1 DAC2" },
3685 { "IF1 DAC0 Mux", "Slot3", "IF1 DAC3" },
3686 { "IF1 DAC0 Mux", "Slot4", "IF1 DAC4" },
3687 { "IF1 DAC0 Mux", "Slot5", "IF1 DAC5" },
3688 { "IF1 DAC0 Mux", "Slot6", "IF1 DAC6" },
3689 { "IF1 DAC0 Mux", "Slot7", "IF1 DAC7" },
3691 { "IF1 DAC1 Mux", "Slot0", "IF1 DAC0" },
3692 { "IF1 DAC1 Mux", "Slot1", "IF1 DAC1" },
3693 { "IF1 DAC1 Mux", "Slot2", "IF1 DAC2" },
3694 { "IF1 DAC1 Mux", "Slot3", "IF1 DAC3" },
3695 { "IF1 DAC1 Mux", "Slot4", "IF1 DAC4" },
3696 { "IF1 DAC1 Mux", "Slot5", "IF1 DAC5" },
3697 { "IF1 DAC1 Mux", "Slot6", "IF1 DAC6" },
3698 { "IF1 DAC1 Mux", "Slot7", "IF1 DAC7" },
3700 { "IF1 DAC2 Mux", "Slot0", "IF1 DAC0" },
3701 { "IF1 DAC2 Mux", "Slot1", "IF1 DAC1" },
3702 { "IF1 DAC2 Mux", "Slot2", "IF1 DAC2" },
3703 { "IF1 DAC2 Mux", "Slot3", "IF1 DAC3" },
3704 { "IF1 DAC2 Mux", "Slot4", "IF1 DAC4" },
3705 { "IF1 DAC2 Mux", "Slot5", "IF1 DAC5" },
3706 { "IF1 DAC2 Mux", "Slot6", "IF1 DAC6" },
3707 { "IF1 DAC2 Mux", "Slot7", "IF1 DAC7" },
3709 { "IF1 DAC3 Mux", "Slot0", "IF1 DAC0" },
3710 { "IF1 DAC3 Mux", "Slot1", "IF1 DAC1" },
3711 { "IF1 DAC3 Mux", "Slot2", "IF1 DAC2" },
3712 { "IF1 DAC3 Mux", "Slot3", "IF1 DAC3" },
3713 { "IF1 DAC3 Mux", "Slot4", "IF1 DAC4" },
3714 { "IF1 DAC3 Mux", "Slot5", "IF1 DAC5" },
3715 { "IF1 DAC3 Mux", "Slot6", "IF1 DAC6" },
3716 { "IF1 DAC3 Mux", "Slot7", "IF1 DAC7" },
3718 { "IF1 DAC4 Mux", "Slot0", "IF1 DAC0" },
3719 { "IF1 DAC4 Mux", "Slot1", "IF1 DAC1" },
3720 { "IF1 DAC4 Mux", "Slot2", "IF1 DAC2" },
3721 { "IF1 DAC4 Mux", "Slot3", "IF1 DAC3" },
3722 { "IF1 DAC4 Mux", "Slot4", "IF1 DAC4" },
3723 { "IF1 DAC4 Mux", "Slot5", "IF1 DAC5" },
3724 { "IF1 DAC4 Mux", "Slot6", "IF1 DAC6" },
3725 { "IF1 DAC4 Mux", "Slot7", "IF1 DAC7" },
3727 { "IF1 DAC5 Mux", "Slot0", "IF1 DAC0" },
3728 { "IF1 DAC5 Mux", "Slot1", "IF1 DAC1" },
3729 { "IF1 DAC5 Mux", "Slot2", "IF1 DAC2" },
3730 { "IF1 DAC5 Mux", "Slot3", "IF1 DAC3" },
3731 { "IF1 DAC5 Mux", "Slot4", "IF1 DAC4" },
3732 { "IF1 DAC5 Mux", "Slot5", "IF1 DAC5" },
3733 { "IF1 DAC5 Mux", "Slot6", "IF1 DAC6" },
3734 { "IF1 DAC5 Mux", "Slot7", "IF1 DAC7" },
3736 { "IF1 DAC6 Mux", "Slot0", "IF1 DAC0" },
3737 { "IF1 DAC6 Mux", "Slot1", "IF1 DAC1" },
3738 { "IF1 DAC6 Mux", "Slot2", "IF1 DAC2" },
3739 { "IF1 DAC6 Mux", "Slot3", "IF1 DAC3" },
3740 { "IF1 DAC6 Mux", "Slot4", "IF1 DAC4" },
3741 { "IF1 DAC6 Mux", "Slot5", "IF1 DAC5" },
3742 { "IF1 DAC6 Mux", "Slot6", "IF1 DAC6" },
3743 { "IF1 DAC6 Mux", "Slot7", "IF1 DAC7" },
3745 { "IF1 DAC7 Mux", "Slot0", "IF1 DAC0" },
3746 { "IF1 DAC7 Mux", "Slot1", "IF1 DAC1" },
3747 { "IF1 DAC7 Mux", "Slot2", "IF1 DAC2" },
3748 { "IF1 DAC7 Mux", "Slot3", "IF1 DAC3" },
3749 { "IF1 DAC7 Mux", "Slot4", "IF1 DAC4" },
3750 { "IF1 DAC7 Mux", "Slot5", "IF1 DAC5" },
3751 { "IF1 DAC7 Mux", "Slot6", "IF1 DAC6" },
3752 { "IF1 DAC7 Mux", "Slot7", "IF1 DAC7" },
3754 { "IF1 DAC01", NULL, "IF1 DAC0 Mux" },
3755 { "IF1 DAC01", NULL, "IF1 DAC1 Mux" },
3756 { "IF1 DAC23", NULL, "IF1 DAC2 Mux" },
3757 { "IF1 DAC23", NULL, "IF1 DAC3 Mux" },
3758 { "IF1 DAC45", NULL, "IF1 DAC4 Mux" },
3759 { "IF1 DAC45", NULL, "IF1 DAC5 Mux" },
3760 { "IF1 DAC67", NULL, "IF1 DAC6 Mux" },
3761 { "IF1 DAC67", NULL, "IF1 DAC7 Mux" },
3763 { "IF2 DAC0", NULL, "AIF2RX" },
3764 { "IF2 DAC1", NULL, "AIF2RX" },
3765 { "IF2 DAC2", NULL, "AIF2RX" },
3766 { "IF2 DAC3", NULL, "AIF2RX" },
3767 { "IF2 DAC4", NULL, "AIF2RX" },
3768 { "IF2 DAC5", NULL, "AIF2RX" },
3769 { "IF2 DAC6", NULL, "AIF2RX" },
3770 { "IF2 DAC7", NULL, "AIF2RX" },
3771 { "IF2 DAC0", NULL, "I2S2" },
3772 { "IF2 DAC1", NULL, "I2S2" },
3773 { "IF2 DAC2", NULL, "I2S2" },
3774 { "IF2 DAC3", NULL, "I2S2" },
3775 { "IF2 DAC4", NULL, "I2S2" },
3776 { "IF2 DAC5", NULL, "I2S2" },
3777 { "IF2 DAC6", NULL, "I2S2" },
3778 { "IF2 DAC7", NULL, "I2S2" },
3780 { "IF2 DAC0 Mux", "Slot0", "IF2 DAC0" },
3781 { "IF2 DAC0 Mux", "Slot1", "IF2 DAC1" },
3782 { "IF2 DAC0 Mux", "Slot2", "IF2 DAC2" },
3783 { "IF2 DAC0 Mux", "Slot3", "IF2 DAC3" },
3784 { "IF2 DAC0 Mux", "Slot4", "IF2 DAC4" },
3785 { "IF2 DAC0 Mux", "Slot5", "IF2 DAC5" },
3786 { "IF2 DAC0 Mux", "Slot6", "IF2 DAC6" },
3787 { "IF2 DAC0 Mux", "Slot7", "IF2 DAC7" },
3789 { "IF2 DAC1 Mux", "Slot0", "IF2 DAC0" },
3790 { "IF2 DAC1 Mux", "Slot1", "IF2 DAC1" },
3791 { "IF2 DAC1 Mux", "Slot2", "IF2 DAC2" },
3792 { "IF2 DAC1 Mux", "Slot3", "IF2 DAC3" },
3793 { "IF2 DAC1 Mux", "Slot4", "IF2 DAC4" },
3794 { "IF2 DAC1 Mux", "Slot5", "IF2 DAC5" },
3795 { "IF2 DAC1 Mux", "Slot6", "IF2 DAC6" },
3796 { "IF2 DAC1 Mux", "Slot7", "IF2 DAC7" },
3798 { "IF2 DAC2 Mux", "Slot0", "IF2 DAC0" },
3799 { "IF2 DAC2 Mux", "Slot1", "IF2 DAC1" },
3800 { "IF2 DAC2 Mux", "Slot2", "IF2 DAC2" },
3801 { "IF2 DAC2 Mux", "Slot3", "IF2 DAC3" },
3802 { "IF2 DAC2 Mux", "Slot4", "IF2 DAC4" },
3803 { "IF2 DAC2 Mux", "Slot5", "IF2 DAC5" },
3804 { "IF2 DAC2 Mux", "Slot6", "IF2 DAC6" },
3805 { "IF2 DAC2 Mux", "Slot7", "IF2 DAC7" },
3807 { "IF2 DAC3 Mux", "Slot0", "IF2 DAC0" },
3808 { "IF2 DAC3 Mux", "Slot1", "IF2 DAC1" },
3809 { "IF2 DAC3 Mux", "Slot2", "IF2 DAC2" },
3810 { "IF2 DAC3 Mux", "Slot3", "IF2 DAC3" },
3811 { "IF2 DAC3 Mux", "Slot4", "IF2 DAC4" },
3812 { "IF2 DAC3 Mux", "Slot5", "IF2 DAC5" },
3813 { "IF2 DAC3 Mux", "Slot6", "IF2 DAC6" },
3814 { "IF2 DAC3 Mux", "Slot7", "IF2 DAC7" },
3816 { "IF2 DAC4 Mux", "Slot0", "IF2 DAC0" },
3817 { "IF2 DAC4 Mux", "Slot1", "IF2 DAC1" },
3818 { "IF2 DAC4 Mux", "Slot2", "IF2 DAC2" },
3819 { "IF2 DAC4 Mux", "Slot3", "IF2 DAC3" },
3820 { "IF2 DAC4 Mux", "Slot4", "IF2 DAC4" },
3821 { "IF2 DAC4 Mux", "Slot5", "IF2 DAC5" },
3822 { "IF2 DAC4 Mux", "Slot6", "IF2 DAC6" },
3823 { "IF2 DAC4 Mux", "Slot7", "IF2 DAC7" },
3825 { "IF2 DAC5 Mux", "Slot0", "IF2 DAC0" },
3826 { "IF2 DAC5 Mux", "Slot1", "IF2 DAC1" },
3827 { "IF2 DAC5 Mux", "Slot2", "IF2 DAC2" },
3828 { "IF2 DAC5 Mux", "Slot3", "IF2 DAC3" },
3829 { "IF2 DAC5 Mux", "Slot4", "IF2 DAC4" },
3830 { "IF2 DAC5 Mux", "Slot5", "IF2 DAC5" },
3831 { "IF2 DAC5 Mux", "Slot6", "IF2 DAC6" },
3832 { "IF2 DAC5 Mux", "Slot7", "IF2 DAC7" },
3834 { "IF2 DAC6 Mux", "Slot0", "IF2 DAC0" },
3835 { "IF2 DAC6 Mux", "Slot1", "IF2 DAC1" },
3836 { "IF2 DAC6 Mux", "Slot2", "IF2 DAC2" },
3837 { "IF2 DAC6 Mux", "Slot3", "IF2 DAC3" },
3838 { "IF2 DAC6 Mux", "Slot4", "IF2 DAC4" },
3839 { "IF2 DAC6 Mux", "Slot5", "IF2 DAC5" },
3840 { "IF2 DAC6 Mux", "Slot6", "IF2 DAC6" },
3841 { "IF2 DAC6 Mux", "Slot7", "IF2 DAC7" },
3843 { "IF2 DAC7 Mux", "Slot0", "IF2 DAC0" },
3844 { "IF2 DAC7 Mux", "Slot1", "IF2 DAC1" },
3845 { "IF2 DAC7 Mux", "Slot2", "IF2 DAC2" },
3846 { "IF2 DAC7 Mux", "Slot3", "IF2 DAC3" },
3847 { "IF2 DAC7 Mux", "Slot4", "IF2 DAC4" },
3848 { "IF2 DAC7 Mux", "Slot5", "IF2 DAC5" },
3849 { "IF2 DAC7 Mux", "Slot6", "IF2 DAC6" },
3850 { "IF2 DAC7 Mux", "Slot7", "IF2 DAC7" },
3852 { "IF2 DAC01", NULL, "IF2 DAC0 Mux" },
3853 { "IF2 DAC01", NULL, "IF2 DAC1 Mux" },
3854 { "IF2 DAC23", NULL, "IF2 DAC2 Mux" },
3855 { "IF2 DAC23", NULL, "IF2 DAC3 Mux" },
3856 { "IF2 DAC45", NULL, "IF2 DAC4 Mux" },
3857 { "IF2 DAC45", NULL, "IF2 DAC5 Mux" },
3858 { "IF2 DAC67", NULL, "IF2 DAC6 Mux" },
3859 { "IF2 DAC67", NULL, "IF2 DAC7 Mux" },
3861 { "IF3 DAC", NULL, "AIF3RX" },
3862 { "IF3 DAC", NULL, "I2S3" },
3864 { "IF4 DAC", NULL, "AIF4RX" },
3865 { "IF4 DAC", NULL, "I2S4" },
3867 { "IF3 DAC L", NULL, "IF3 DAC" },
3868 { "IF3 DAC R", NULL, "IF3 DAC" },
3870 { "IF4 DAC L", NULL, "IF4 DAC" },
3871 { "IF4 DAC R", NULL, "IF4 DAC" },
3873 { "SLB DAC0", NULL, "SLBRX" },
3874 { "SLB DAC1", NULL, "SLBRX" },
3875 { "SLB DAC2", NULL, "SLBRX" },
3876 { "SLB DAC3", NULL, "SLBRX" },
3877 { "SLB DAC4", NULL, "SLBRX" },
3878 { "SLB DAC5", NULL, "SLBRX" },
3879 { "SLB DAC6", NULL, "SLBRX" },
3880 { "SLB DAC7", NULL, "SLBRX" },
3881 { "SLB DAC0", NULL, "SLB" },
3882 { "SLB DAC1", NULL, "SLB" },
3883 { "SLB DAC2", NULL, "SLB" },
3884 { "SLB DAC3", NULL, "SLB" },
3885 { "SLB DAC4", NULL, "SLB" },
3886 { "SLB DAC5", NULL, "SLB" },
3887 { "SLB DAC6", NULL, "SLB" },
3888 { "SLB DAC7", NULL, "SLB" },
3890 { "SLB DAC01", NULL, "SLB DAC0" },
3891 { "SLB DAC01", NULL, "SLB DAC1" },
3892 { "SLB DAC23", NULL, "SLB DAC2" },
3893 { "SLB DAC23", NULL, "SLB DAC3" },
3894 { "SLB DAC45", NULL, "SLB DAC4" },
3895 { "SLB DAC45", NULL, "SLB DAC5" },
3896 { "SLB DAC67", NULL, "SLB DAC6" },
3897 { "SLB DAC67", NULL, "SLB DAC7" },
3899 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
3900 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
3901 { "ADDA1 Mux", "OB 67", "OB67" },
3903 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
3904 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
3905 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
3906 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
3907 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
3908 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
3910 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
3911 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
3912 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
3913 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
3915 { "DAC1 FS", NULL, "DAC1 MIXL" },
3916 { "DAC1 FS", NULL, "DAC1 MIXR" },
3918 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2 Mux" },
3919 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2 Mux" },
3920 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
3921 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
3922 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
3923 { "DAC2 L Mux", "OB 2", "OutBound2" },
3925 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3 Mux" },
3926 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3 Mux" },
3927 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
3928 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
3929 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
3930 { "DAC2 R Mux", "OB 3", "OutBound3" },
3931 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
3932 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
3934 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4 Mux" },
3935 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4 Mux" },
3936 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
3937 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
3938 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
3939 { "DAC3 L Mux", "OB 4", "OutBound4" },
3941 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC5 Mux" },
3942 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC5 Mux" },
3943 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
3944 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
3945 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
3946 { "DAC3 R Mux", "OB 5", "OutBound5" },
3948 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6 Mux" },
3949 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6 Mux" },
3950 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
3951 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
3952 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
3953 { "DAC4 L Mux", "OB 6", "OutBound6" },
3955 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7 Mux" },
3956 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7 Mux" },
3957 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
3958 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
3959 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
3960 { "DAC4 R Mux", "OB 7", "OutBound7" },
3962 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
3963 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
3964 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
3965 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
3966 { "Sidetone Mux", "ADC1", "ADC 1" },
3967 { "Sidetone Mux", "ADC2", "ADC 2" },
3968 { "Sidetone Mux", NULL, "Sidetone Power" },
3970 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
3971 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3972 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3973 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
3974 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
3975 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
3976 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3977 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3978 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
3979 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
3980 { "dac stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
3982 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
3983 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
3984 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
3985 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
3986 { "Mono DAC MIXL", NULL, "dac mono2 left filter" },
3987 { "dac mono2 left filter", NULL, "PLL1", is_sys_clk_from_pll },
3988 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
3989 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
3990 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
3991 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
3992 { "Mono DAC MIXR", NULL, "dac mono2 right filter" },
3993 { "dac mono2 right filter", NULL, "PLL1", is_sys_clk_from_pll },
3995 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
3996 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
3997 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
3998 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
3999 { "DD1 MIXL", NULL, "dac mono3 left filter" },
4000 { "dac mono3 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4001 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4002 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4003 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
4004 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
4005 { "DD1 MIXR", NULL, "dac mono3 right filter" },
4006 { "dac mono3 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4008 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
4009 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
4010 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
4011 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
4012 { "DD2 MIXL", NULL, "dac mono4 left filter" },
4013 { "dac mono4 left filter", NULL, "PLL1", is_sys_clk_from_pll },
4014 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
4015 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
4016 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
4017 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
4018 { "DD2 MIXR", NULL, "dac mono4 right filter" },
4019 { "dac mono4 right filter", NULL, "PLL1", is_sys_clk_from_pll },
4021 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
4022 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
4023 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
4024 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
4025 { "DD1 MIX", NULL, "DD1 MIXL" },
4026 { "DD1 MIX", NULL, "DD1 MIXR" },
4027 { "DD2 MIX", NULL, "DD2 MIXL" },
4028 { "DD2 MIX", NULL, "DD2 MIXR" },
4030 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
4031 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
4032 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
4033 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
4035 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
4036 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
4037 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
4038 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
4040 { "DAC 1", NULL, "DAC12 SRC Mux" },
4041 { "DAC 2", NULL, "DAC12 SRC Mux" },
4042 { "DAC 3", NULL, "DAC3 SRC Mux" },
4044 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4045 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4046 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
4047 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
4048 { "PDM1 L Mux", NULL, "PDM1 Power" },
4049 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4050 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4051 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
4052 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
4053 { "PDM1 R Mux", NULL, "PDM1 Power" },
4054 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
4055 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
4056 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
4057 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
4058 { "PDM2 L Mux", NULL, "PDM2 Power" },
4059 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
4060 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
4061 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
4062 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
4063 { "PDM2 R Mux", NULL, "PDM2 Power" },
4065 { "LOUT1 amp", NULL, "DAC 1" },
4066 { "LOUT2 amp", NULL, "DAC 2" },
4067 { "LOUT3 amp", NULL, "DAC 3" },
4069 { "LOUT1 vref", NULL, "LOUT1 amp" },
4070 { "LOUT2 vref", NULL, "LOUT2 amp" },
4071 { "LOUT3 vref", NULL, "LOUT3 amp" },
4073 { "LOUT1", NULL, "LOUT1 vref" },
4074 { "LOUT2", NULL, "LOUT2 vref" },
4075 { "LOUT3", NULL, "LOUT3 vref" },
4077 { "PDM1L", NULL, "PDM1 L Mux" },
4078 { "PDM1R", NULL, "PDM1 R Mux" },
4079 { "PDM2L", NULL, "PDM2 L Mux" },
4080 { "PDM2R", NULL, "PDM2 R Mux" },
4083 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
4084 { "DMIC L2", NULL, "DMIC1 power" },
4085 { "DMIC R2", NULL, "DMIC1 power" },
4088 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
4089 { "DMIC L2", NULL, "DMIC2 power" },
4090 { "DMIC R2", NULL, "DMIC2 power" },
4093 static int rt5677_hw_params(struct snd_pcm_substream *substream,
4094 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4096 struct snd_soc_codec *codec = dai->codec;
4097 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4098 unsigned int val_len = 0, val_clk, mask_clk;
4099 int pre_div, bclk_ms, frame_size;
4101 rt5677->lrck[dai->id] = params_rate(params);
4102 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
4104 dev_err(codec->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n",
4105 rt5677->sysclk, rt5677->lrck[dai->id]);
4108 frame_size = snd_soc_params_to_frame_size(params);
4109 if (frame_size < 0) {
4110 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4113 bclk_ms = frame_size > 32;
4114 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
4116 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
4117 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
4118 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
4119 bclk_ms, pre_div, dai->id);
4121 switch (params_width(params)) {
4125 val_len |= RT5677_I2S_DL_20;
4128 val_len |= RT5677_I2S_DL_24;
4131 val_len |= RT5677_I2S_DL_8;
4139 mask_clk = RT5677_I2S_PD1_MASK;
4140 val_clk = pre_div << RT5677_I2S_PD1_SFT;
4141 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4142 RT5677_I2S_DL_MASK, val_len);
4143 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4147 mask_clk = RT5677_I2S_PD2_MASK;
4148 val_clk = pre_div << RT5677_I2S_PD2_SFT;
4149 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4150 RT5677_I2S_DL_MASK, val_len);
4151 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4155 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
4156 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
4157 pre_div << RT5677_I2S_PD3_SFT;
4158 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4159 RT5677_I2S_DL_MASK, val_len);
4160 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4164 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
4165 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
4166 pre_div << RT5677_I2S_PD4_SFT;
4167 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4168 RT5677_I2S_DL_MASK, val_len);
4169 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
4179 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4181 struct snd_soc_codec *codec = dai->codec;
4182 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4183 unsigned int reg_val = 0;
4185 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4186 case SND_SOC_DAIFMT_CBM_CFM:
4187 rt5677->master[dai->id] = 1;
4189 case SND_SOC_DAIFMT_CBS_CFS:
4190 reg_val |= RT5677_I2S_MS_S;
4191 rt5677->master[dai->id] = 0;
4197 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4198 case SND_SOC_DAIFMT_NB_NF:
4200 case SND_SOC_DAIFMT_IB_NF:
4201 reg_val |= RT5677_I2S_BP_INV;
4207 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4208 case SND_SOC_DAIFMT_I2S:
4210 case SND_SOC_DAIFMT_LEFT_J:
4211 reg_val |= RT5677_I2S_DF_LEFT;
4213 case SND_SOC_DAIFMT_DSP_A:
4214 reg_val |= RT5677_I2S_DF_PCM_A;
4216 case SND_SOC_DAIFMT_DSP_B:
4217 reg_val |= RT5677_I2S_DF_PCM_B;
4225 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
4226 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4227 RT5677_I2S_DF_MASK, reg_val);
4230 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
4231 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4232 RT5677_I2S_DF_MASK, reg_val);
4235 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
4236 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4237 RT5677_I2S_DF_MASK, reg_val);
4240 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
4241 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
4242 RT5677_I2S_DF_MASK, reg_val);
4252 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
4253 int clk_id, unsigned int freq, int dir)
4255 struct snd_soc_codec *codec = dai->codec;
4256 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4257 unsigned int reg_val = 0;
4259 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
4263 case RT5677_SCLK_S_MCLK:
4264 reg_val |= RT5677_SCLK_SRC_MCLK;
4266 case RT5677_SCLK_S_PLL1:
4267 reg_val |= RT5677_SCLK_SRC_PLL1;
4269 case RT5677_SCLK_S_RCCLK:
4270 reg_val |= RT5677_SCLK_SRC_RCCLK;
4273 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4276 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4277 RT5677_SCLK_SRC_MASK, reg_val);
4278 rt5677->sysclk = freq;
4279 rt5677->sysclk_src = clk_id;
4281 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4287 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4288 * @freq_in: external clock provided to codec.
4289 * @freq_out: target clock which codec works on.
4290 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
4292 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
4294 * Returns 0 for success or negative error code.
4296 static int rt5677_pll_calc(const unsigned int freq_in,
4297 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
4299 if (RT5677_PLL_INP_MIN > freq_in)
4302 return rl6231_pll_calc(freq_in, freq_out, pll_code);
4305 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
4306 unsigned int freq_in, unsigned int freq_out)
4308 struct snd_soc_codec *codec = dai->codec;
4309 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4310 struct rl6231_pll_code pll_code;
4313 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
4314 freq_out == rt5677->pll_out)
4317 if (!freq_in || !freq_out) {
4318 dev_dbg(codec->dev, "PLL disabled\n");
4321 rt5677->pll_out = 0;
4322 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4323 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
4328 case RT5677_PLL1_S_MCLK:
4329 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4330 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
4332 case RT5677_PLL1_S_BCLK1:
4333 case RT5677_PLL1_S_BCLK2:
4334 case RT5677_PLL1_S_BCLK3:
4335 case RT5677_PLL1_S_BCLK4:
4338 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4339 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
4342 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4343 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
4346 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4347 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
4350 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
4351 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
4358 dev_err(codec->dev, "Unknown PLL source %d\n", source);
4362 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
4364 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4368 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
4369 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4370 pll_code.n_code, pll_code.k_code);
4372 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
4373 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
4374 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
4375 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
4376 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
4378 rt5677->pll_in = freq_in;
4379 rt5677->pll_out = freq_out;
4380 rt5677->pll_src = source;
4385 static int rt5677_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4386 unsigned int rx_mask, int slots, int slot_width)
4388 struct snd_soc_codec *codec = dai->codec;
4389 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4390 unsigned int val = 0, slot_width_25 = 0;
4392 if (rx_mask || tx_mask)
4410 switch (slot_width) {
4415 slot_width_25 = 0x8080;
4429 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00,
4431 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000,
4435 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00,
4437 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80,
4447 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
4448 enum snd_soc_bias_level level)
4450 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4453 case SND_SOC_BIAS_ON:
4456 case SND_SOC_BIAS_PREPARE:
4457 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) {
4458 rt5677_set_dsp_vad(codec, false);
4460 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4461 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
4463 regmap_update_bits(rt5677->regmap,
4464 RT5677_PR_BASE + RT5677_BIAS_CUR4,
4466 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
4467 RT5677_PWR_FV1 | RT5677_PWR_FV2 |
4468 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4469 RT5677_PWR_BG | RT5677_PWR_VREF2,
4470 RT5677_PWR_VREF1 | RT5677_PWR_MB |
4471 RT5677_PWR_BG | RT5677_PWR_VREF2);
4472 rt5677->is_vref_slow = false;
4473 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
4474 RT5677_PWR_CORE, RT5677_PWR_CORE);
4475 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
4480 case SND_SOC_BIAS_STANDBY:
4483 case SND_SOC_BIAS_OFF:
4484 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
4485 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
4486 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
4487 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
4488 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
4489 regmap_update_bits(rt5677->regmap,
4490 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
4492 if (rt5677->dsp_vad_en)
4493 rt5677_set_dsp_vad(codec, true);
4503 #ifdef CONFIG_GPIOLIB
4504 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
4506 return container_of(chip, struct rt5677_priv, gpio_chip);
4509 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
4511 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4514 case RT5677_GPIO1 ... RT5677_GPIO5:
4515 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4516 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
4520 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4521 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
4529 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
4530 unsigned offset, int value)
4532 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4535 case RT5677_GPIO1 ... RT5677_GPIO5:
4536 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4537 0x3 << (offset * 3 + 1),
4538 (0x2 | !!value) << (offset * 3 + 1));
4542 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4543 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
4544 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
4554 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
4556 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4559 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
4563 return (value & (0x1 << offset)) >> offset;
4566 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
4568 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4571 case RT5677_GPIO1 ... RT5677_GPIO5:
4572 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
4573 0x1 << (offset * 3 + 2), 0x0);
4577 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
4578 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
4588 /** Configures the gpio as
4593 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4599 case RT5677_GPIO1 ... RT5677_GPIO2:
4600 shift = 2 * (1 - offset);
4601 regmap_update_bits(rt5677->regmap,
4602 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL2,
4604 (value & 0x3) << shift);
4607 case RT5677_GPIO3 ... RT5677_GPIO6:
4608 shift = 2 * (9 - offset);
4609 regmap_update_bits(rt5677->regmap,
4610 RT5677_PR_BASE + RT5677_DIG_IN_PIN_ST_CTRL3,
4612 (value & 0x3) << shift);
4620 static int rt5677_to_irq(struct gpio_chip *chip, unsigned offset)
4622 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
4623 struct regmap_irq_chip_data *data = rt5677->irq_data;
4626 if (offset >= RT5677_GPIO1 && offset <= RT5677_GPIO3) {
4627 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) ||
4628 (rt5677->pdata.jd1_gpio == 2 &&
4629 offset == RT5677_GPIO2) ||
4630 (rt5677->pdata.jd1_gpio == 3 &&
4631 offset == RT5677_GPIO3)) {
4632 irq = RT5677_IRQ_JD1;
4638 if (offset >= RT5677_GPIO4 && offset <= RT5677_GPIO6) {
4639 if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) ||
4640 (rt5677->pdata.jd2_gpio == 2 &&
4641 offset == RT5677_GPIO5) ||
4642 (rt5677->pdata.jd2_gpio == 3 &&
4643 offset == RT5677_GPIO6)) {
4644 irq = RT5677_IRQ_JD2;
4645 } else if ((rt5677->pdata.jd3_gpio == 1 &&
4646 offset == RT5677_GPIO4) ||
4647 (rt5677->pdata.jd3_gpio == 2 &&
4648 offset == RT5677_GPIO5) ||
4649 (rt5677->pdata.jd3_gpio == 3 &&
4650 offset == RT5677_GPIO6)) {
4651 irq = RT5677_IRQ_JD3;
4657 return regmap_irq_get_virq(data, irq);
4660 static struct gpio_chip rt5677_template_chip = {
4662 .owner = THIS_MODULE,
4663 .direction_output = rt5677_gpio_direction_out,
4664 .set = rt5677_gpio_set,
4665 .direction_input = rt5677_gpio_direction_in,
4666 .get = rt5677_gpio_get,
4667 .to_irq = rt5677_to_irq,
4671 static void rt5677_init_gpio(struct i2c_client *i2c)
4673 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4676 rt5677->gpio_chip = rt5677_template_chip;
4677 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
4678 rt5677->gpio_chip.dev = &i2c->dev;
4679 rt5677->gpio_chip.base = -1;
4681 ret = gpiochip_add(&rt5677->gpio_chip);
4683 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
4686 static void rt5677_free_gpio(struct i2c_client *i2c)
4688 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
4690 gpiochip_remove(&rt5677->gpio_chip);
4693 static void rt5677_gpio_config(struct rt5677_priv *rt5677, unsigned offset,
4698 static void rt5677_init_gpio(struct i2c_client *i2c)
4702 static void rt5677_free_gpio(struct i2c_client *i2c)
4707 static int rt5677_probe(struct snd_soc_codec *codec)
4709 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
4710 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4713 rt5677->codec = codec;
4715 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
4716 snd_soc_dapm_add_routes(dapm,
4718 ARRAY_SIZE(rt5677_dmic2_clk_2));
4719 } else { /*use dmic1 clock by default*/
4720 snd_soc_dapm_add_routes(dapm,
4722 ARRAY_SIZE(rt5677_dmic2_clk_1));
4725 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
4727 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
4728 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
4730 for (i = 0; i < RT5677_GPIO_NUM; i++)
4731 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]);
4733 if (rt5677->irq_data) {
4734 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000,
4736 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018,
4739 if (rt5677->pdata.jd1_gpio)
4740 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4741 RT5677_SEL_GPIO_JD1_MASK,
4742 rt5677->pdata.jd1_gpio <<
4743 RT5677_SEL_GPIO_JD1_SFT);
4745 if (rt5677->pdata.jd2_gpio)
4746 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4747 RT5677_SEL_GPIO_JD2_MASK,
4748 rt5677->pdata.jd2_gpio <<
4749 RT5677_SEL_GPIO_JD2_SFT);
4751 if (rt5677->pdata.jd3_gpio)
4752 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1,
4753 RT5677_SEL_GPIO_JD3_MASK,
4754 rt5677->pdata.jd3_gpio <<
4755 RT5677_SEL_GPIO_JD3_SFT);
4758 mutex_init(&rt5677->dsp_cmd_lock);
4759 mutex_init(&rt5677->dsp_pri_lock);
4764 static int rt5677_remove(struct snd_soc_codec *codec)
4766 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4768 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4769 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4770 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4776 static int rt5677_suspend(struct snd_soc_codec *codec)
4778 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4780 if (!rt5677->dsp_vad_en) {
4781 regcache_cache_only(rt5677->regmap, true);
4782 regcache_mark_dirty(rt5677->regmap);
4784 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4785 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4791 static int rt5677_resume(struct snd_soc_codec *codec)
4793 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4795 if (!rt5677->dsp_vad_en) {
4796 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4797 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4798 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4801 regcache_cache_only(rt5677->regmap, false);
4802 regcache_sync(rt5677->regmap);
4808 #define rt5677_suspend NULL
4809 #define rt5677_resume NULL
4812 static int rt5677_read(void *context, unsigned int reg, unsigned int *val)
4814 struct i2c_client *client = context;
4815 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4817 if (rt5677->is_dsp_mode) {
4819 mutex_lock(&rt5677->dsp_pri_lock);
4820 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4822 rt5677_dsp_mode_i2c_read(rt5677, RT5677_PRIV_DATA, val);
4823 mutex_unlock(&rt5677->dsp_pri_lock);
4825 rt5677_dsp_mode_i2c_read(rt5677, reg, val);
4828 regmap_read(rt5677->regmap_physical, reg, val);
4834 static int rt5677_write(void *context, unsigned int reg, unsigned int val)
4836 struct i2c_client *client = context;
4837 struct rt5677_priv *rt5677 = i2c_get_clientdata(client);
4839 if (rt5677->is_dsp_mode) {
4841 mutex_lock(&rt5677->dsp_pri_lock);
4842 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_INDEX,
4844 rt5677_dsp_mode_i2c_write(rt5677, RT5677_PRIV_DATA,
4846 mutex_unlock(&rt5677->dsp_pri_lock);
4848 rt5677_dsp_mode_i2c_write(rt5677, reg, val);
4851 regmap_write(rt5677->regmap_physical, reg, val);
4857 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
4858 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4859 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4861 static const struct snd_soc_dai_ops rt5677_aif_dai_ops = {
4862 .hw_params = rt5677_hw_params,
4863 .set_fmt = rt5677_set_dai_fmt,
4864 .set_sysclk = rt5677_set_dai_sysclk,
4865 .set_pll = rt5677_set_dai_pll,
4866 .set_tdm_slot = rt5677_set_tdm_slot,
4869 static struct snd_soc_dai_driver rt5677_dai[] = {
4871 .name = "rt5677-aif1",
4874 .stream_name = "AIF1 Playback",
4877 .rates = RT5677_STEREO_RATES,
4878 .formats = RT5677_FORMATS,
4881 .stream_name = "AIF1 Capture",
4884 .rates = RT5677_STEREO_RATES,
4885 .formats = RT5677_FORMATS,
4887 .ops = &rt5677_aif_dai_ops,
4890 .name = "rt5677-aif2",
4893 .stream_name = "AIF2 Playback",
4896 .rates = RT5677_STEREO_RATES,
4897 .formats = RT5677_FORMATS,
4900 .stream_name = "AIF2 Capture",
4903 .rates = RT5677_STEREO_RATES,
4904 .formats = RT5677_FORMATS,
4906 .ops = &rt5677_aif_dai_ops,
4909 .name = "rt5677-aif3",
4912 .stream_name = "AIF3 Playback",
4915 .rates = RT5677_STEREO_RATES,
4916 .formats = RT5677_FORMATS,
4919 .stream_name = "AIF3 Capture",
4922 .rates = RT5677_STEREO_RATES,
4923 .formats = RT5677_FORMATS,
4925 .ops = &rt5677_aif_dai_ops,
4928 .name = "rt5677-aif4",
4931 .stream_name = "AIF4 Playback",
4934 .rates = RT5677_STEREO_RATES,
4935 .formats = RT5677_FORMATS,
4938 .stream_name = "AIF4 Capture",
4941 .rates = RT5677_STEREO_RATES,
4942 .formats = RT5677_FORMATS,
4944 .ops = &rt5677_aif_dai_ops,
4947 .name = "rt5677-slimbus",
4950 .stream_name = "SLIMBus Playback",
4953 .rates = RT5677_STEREO_RATES,
4954 .formats = RT5677_FORMATS,
4957 .stream_name = "SLIMBus Capture",
4960 .rates = RT5677_STEREO_RATES,
4961 .formats = RT5677_FORMATS,
4963 .ops = &rt5677_aif_dai_ops,
4967 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
4968 .probe = rt5677_probe,
4969 .remove = rt5677_remove,
4970 .suspend = rt5677_suspend,
4971 .resume = rt5677_resume,
4972 .set_bias_level = rt5677_set_bias_level,
4973 .idle_bias_off = true,
4974 .controls = rt5677_snd_controls,
4975 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
4976 .dapm_widgets = rt5677_dapm_widgets,
4977 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
4978 .dapm_routes = rt5677_dapm_routes,
4979 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
4982 static const struct regmap_config rt5677_regmap_physical = {
4987 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
4989 .readable_reg = rt5677_readable_register,
4991 .cache_type = REGCACHE_NONE,
4992 .ranges = rt5677_ranges,
4993 .num_ranges = ARRAY_SIZE(rt5677_ranges),
4996 static const struct regmap_config rt5677_regmap = {
5000 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
5003 .volatile_reg = rt5677_volatile_register,
5004 .readable_reg = rt5677_readable_register,
5005 .reg_read = rt5677_read,
5006 .reg_write = rt5677_write,
5008 .cache_type = REGCACHE_RBTREE,
5009 .reg_defaults = rt5677_reg,
5010 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
5011 .ranges = rt5677_ranges,
5012 .num_ranges = ARRAY_SIZE(rt5677_ranges),
5015 static const struct i2c_device_id rt5677_i2c_id[] = {
5016 { "rt5677", RT5677 },
5017 { "rt5676", RT5676 },
5020 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
5022 static void rt5677_read_device_properties(struct rt5677_priv *rt5677,
5025 rt5677->pdata.in1_diff = device_property_read_bool(dev,
5026 "realtek,in1-differential");
5027 rt5677->pdata.in2_diff = device_property_read_bool(dev,
5028 "realtek,in2-differential");
5029 rt5677->pdata.lout1_diff = device_property_read_bool(dev,
5030 "realtek,lout1-differential");
5031 rt5677->pdata.lout2_diff = device_property_read_bool(dev,
5032 "realtek,lout2-differential");
5033 rt5677->pdata.lout3_diff = device_property_read_bool(dev,
5034 "realtek,lout3-differential");
5036 device_property_read_u8_array(dev, "realtek,gpio-config",
5037 rt5677->pdata.gpio_config, RT5677_GPIO_NUM);
5039 device_property_read_u32(dev, "realtek,jd1-gpio",
5040 &rt5677->pdata.jd1_gpio);
5041 device_property_read_u32(dev, "realtek,jd2-gpio",
5042 &rt5677->pdata.jd2_gpio);
5043 device_property_read_u32(dev, "realtek,jd3-gpio",
5044 &rt5677->pdata.jd3_gpio);
5047 static struct regmap_irq rt5677_irqs[] = {
5048 [RT5677_IRQ_JD1] = {
5050 .mask = RT5677_EN_IRQ_GPIO_JD1,
5052 [RT5677_IRQ_JD2] = {
5054 .mask = RT5677_EN_IRQ_GPIO_JD2,
5056 [RT5677_IRQ_JD3] = {
5058 .mask = RT5677_EN_IRQ_GPIO_JD3,
5062 static struct regmap_irq_chip rt5677_irq_chip = {
5064 .irqs = rt5677_irqs,
5065 .num_irqs = ARRAY_SIZE(rt5677_irqs),
5068 .status_base = RT5677_IRQ_CTRL1,
5069 .mask_base = RT5677_IRQ_CTRL1,
5073 static int rt5677_init_irq(struct i2c_client *i2c)
5076 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5078 if (!rt5677->pdata.jd1_gpio &&
5079 !rt5677->pdata.jd2_gpio &&
5080 !rt5677->pdata.jd3_gpio)
5084 dev_err(&i2c->dev, "No interrupt specified\n");
5088 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq,
5089 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 0,
5090 &rt5677_irq_chip, &rt5677->irq_data);
5093 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret);
5100 static void rt5677_free_irq(struct i2c_client *i2c)
5102 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
5104 if (rt5677->irq_data)
5105 regmap_del_irq_chip(i2c->irq, rt5677->irq_data);
5108 static int rt5677_i2c_probe(struct i2c_client *i2c,
5109 const struct i2c_device_id *id)
5111 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
5112 struct rt5677_priv *rt5677;
5116 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
5121 i2c_set_clientdata(i2c, rt5677);
5123 rt5677->type = id->driver_data;
5126 rt5677->pdata = *pdata;
5128 rt5677_read_device_properties(rt5677, &i2c->dev);
5130 /* pow-ldo2 and reset are optional. The codec pins may be statically
5131 * connected on the board without gpios. If the gpio device property
5132 * isn't specified, devm_gpiod_get_optional returns NULL.
5134 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev,
5135 "realtek,pow-ldo2", GPIOD_OUT_HIGH);
5136 if (IS_ERR(rt5677->pow_ldo2)) {
5137 ret = PTR_ERR(rt5677->pow_ldo2);
5138 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret);
5141 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5142 "realtek,reset", GPIOD_OUT_HIGH);
5143 if (IS_ERR(rt5677->reset_pin)) {
5144 ret = PTR_ERR(rt5677->reset_pin);
5145 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
5149 if (rt5677->pow_ldo2 || rt5677->reset_pin) {
5150 /* Wait a while until I2C bus becomes available. The datasheet
5151 * does not specify the exact we should wait but startup
5152 * sequence mentiones at least a few milliseconds.
5157 rt5677->regmap_physical = devm_regmap_init_i2c(i2c,
5158 &rt5677_regmap_physical);
5159 if (IS_ERR(rt5677->regmap_physical)) {
5160 ret = PTR_ERR(rt5677->regmap_physical);
5161 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5166 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap);
5167 if (IS_ERR(rt5677->regmap)) {
5168 ret = PTR_ERR(rt5677->regmap);
5169 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
5174 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
5175 if (val != RT5677_DEVICE_ID) {
5177 "Device with ID register %#x is not rt5677\n", val);
5181 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
5183 ret = regmap_register_patch(rt5677->regmap, init_list,
5184 ARRAY_SIZE(init_list));
5186 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
5188 if (rt5677->pdata.in1_diff)
5189 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5190 RT5677_IN_DF1, RT5677_IN_DF1);
5192 if (rt5677->pdata.in2_diff)
5193 regmap_update_bits(rt5677->regmap, RT5677_IN1,
5194 RT5677_IN_DF2, RT5677_IN_DF2);
5196 if (rt5677->pdata.lout1_diff)
5197 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5198 RT5677_LOUT1_L_DF, RT5677_LOUT1_L_DF);
5200 if (rt5677->pdata.lout2_diff)
5201 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5202 RT5677_LOUT2_L_DF, RT5677_LOUT2_L_DF);
5204 if (rt5677->pdata.lout3_diff)
5205 regmap_update_bits(rt5677->regmap, RT5677_LOUT1,
5206 RT5677_LOUT3_L_DF, RT5677_LOUT3_L_DF);
5208 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
5209 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
5210 RT5677_GPIO5_FUNC_MASK,
5211 RT5677_GPIO5_FUNC_DMIC);
5212 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
5213 RT5677_GPIO5_DIR_MASK,
5214 RT5677_GPIO5_DIR_OUT);
5217 if (rt5677->pdata.micbias1_vdd_3v3)
5218 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS,
5219 RT5677_MICBIAS1_CTRL_VDD_MASK,
5220 RT5677_MICBIAS1_CTRL_VDD_3_3V);
5222 rt5677_init_gpio(i2c);
5223 rt5677_init_irq(i2c);
5225 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
5226 rt5677_dai, ARRAY_SIZE(rt5677_dai));
5229 static int rt5677_i2c_remove(struct i2c_client *i2c)
5231 snd_soc_unregister_codec(&i2c->dev);
5232 rt5677_free_irq(i2c);
5233 rt5677_free_gpio(i2c);
5238 static struct i2c_driver rt5677_i2c_driver = {
5242 .probe = rt5677_i2c_probe,
5243 .remove = rt5677_i2c_remove,
5244 .id_table = rt5677_i2c_id,
5246 module_i2c_driver(rt5677_i2c_driver);
5248 MODULE_DESCRIPTION("ASoC RT5677 driver");
5249 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
5250 MODULE_LICENSE("GPL v2");