2 * SSM4567 amplifier audio driver
4 * Copyright 2014 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
7 * Based on code copyright/by:
8 * Copyright 2013 Analog Devices Inc.
10 * Licensed under the GPL-2.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/initval.h>
23 #include <sound/tlv.h>
25 #define SSM4567_REG_POWER_CTRL 0x00
26 #define SSM4567_REG_AMP_SNS_CTRL 0x01
27 #define SSM4567_REG_DAC_CTRL 0x02
28 #define SSM4567_REG_DAC_VOLUME 0x03
29 #define SSM4567_REG_SAI_CTRL_1 0x04
30 #define SSM4567_REG_SAI_CTRL_2 0x05
31 #define SSM4567_REG_SAI_PLACEMENT_1 0x06
32 #define SSM4567_REG_SAI_PLACEMENT_2 0x07
33 #define SSM4567_REG_SAI_PLACEMENT_3 0x08
34 #define SSM4567_REG_SAI_PLACEMENT_4 0x09
35 #define SSM4567_REG_SAI_PLACEMENT_5 0x0a
36 #define SSM4567_REG_SAI_PLACEMENT_6 0x0b
37 #define SSM4567_REG_BATTERY_V_OUT 0x0c
38 #define SSM4567_REG_LIMITER_CTRL_1 0x0d
39 #define SSM4567_REG_LIMITER_CTRL_2 0x0e
40 #define SSM4567_REG_LIMITER_CTRL_3 0x0f
41 #define SSM4567_REG_STATUS_1 0x10
42 #define SSM4567_REG_STATUS_2 0x11
43 #define SSM4567_REG_FAULT_CTRL 0x12
44 #define SSM4567_REG_PDM_CTRL 0x13
45 #define SSM4567_REG_MCLK_RATIO 0x14
46 #define SSM4567_REG_BOOST_CTRL_1 0x15
47 #define SSM4567_REG_BOOST_CTRL_2 0x16
48 #define SSM4567_REG_SOFT_RESET 0xff
51 #define SSM4567_POWER_APWDN_EN BIT(7)
52 #define SSM4567_POWER_BSNS_PWDN BIT(6)
53 #define SSM4567_POWER_VSNS_PWDN BIT(5)
54 #define SSM4567_POWER_ISNS_PWDN BIT(4)
55 #define SSM4567_POWER_BOOST_PWDN BIT(3)
56 #define SSM4567_POWER_AMP_PWDN BIT(2)
57 #define SSM4567_POWER_VBAT_ONLY BIT(1)
58 #define SSM4567_POWER_SPWDN BIT(0)
61 #define SSM4567_DAC_HV BIT(7)
62 #define SSM4567_DAC_MUTE BIT(6)
63 #define SSM4567_DAC_HPF BIT(5)
64 #define SSM4567_DAC_LPM BIT(4)
65 #define SSM4567_DAC_FS_MASK 0x7
66 #define SSM4567_DAC_FS_8000_12000 0x0
67 #define SSM4567_DAC_FS_16000_24000 0x1
68 #define SSM4567_DAC_FS_32000_48000 0x2
69 #define SSM4567_DAC_FS_64000_96000 0x3
70 #define SSM4567_DAC_FS_128000_192000 0x4
73 #define SSM4567_SAI_CTRL_1_BCLK BIT(6)
74 #define SSM4567_SAI_CTRL_1_TDM_BLCKS_MASK (0x3 << 4)
75 #define SSM4567_SAI_CTRL_1_TDM_BLCKS_32 (0x0 << 4)
76 #define SSM4567_SAI_CTRL_1_TDM_BLCKS_48 (0x1 << 4)
77 #define SSM4567_SAI_CTRL_1_TDM_BLCKS_64 (0x2 << 4)
78 #define SSM4567_SAI_CTRL_1_FSYNC BIT(3)
79 #define SSM4567_SAI_CTRL_1_LJ BIT(2)
80 #define SSM4567_SAI_CTRL_1_TDM BIT(1)
81 #define SSM4567_SAI_CTRL_1_PDM BIT(0)
84 #define SSM4567_SAI_CTRL_2_AUTO_SLOT BIT(3)
85 #define SSM4567_SAI_CTRL_2_TDM_SLOT_MASK 0x7
86 #define SSM4567_SAI_CTRL_2_TDM_SLOT(x) (x)
89 struct regmap *regmap;
92 static const struct reg_default ssm4567_reg_defaults[] = {
93 { SSM4567_REG_POWER_CTRL, 0x81 },
94 { SSM4567_REG_AMP_SNS_CTRL, 0x09 },
95 { SSM4567_REG_DAC_CTRL, 0x32 },
96 { SSM4567_REG_DAC_VOLUME, 0x40 },
97 { SSM4567_REG_SAI_CTRL_1, 0x00 },
98 { SSM4567_REG_SAI_CTRL_2, 0x08 },
99 { SSM4567_REG_SAI_PLACEMENT_1, 0x01 },
100 { SSM4567_REG_SAI_PLACEMENT_2, 0x20 },
101 { SSM4567_REG_SAI_PLACEMENT_3, 0x32 },
102 { SSM4567_REG_SAI_PLACEMENT_4, 0x07 },
103 { SSM4567_REG_SAI_PLACEMENT_5, 0x07 },
104 { SSM4567_REG_SAI_PLACEMENT_6, 0x07 },
105 { SSM4567_REG_BATTERY_V_OUT, 0x00 },
106 { SSM4567_REG_LIMITER_CTRL_1, 0xa4 },
107 { SSM4567_REG_LIMITER_CTRL_2, 0x73 },
108 { SSM4567_REG_LIMITER_CTRL_3, 0x00 },
109 { SSM4567_REG_STATUS_1, 0x00 },
110 { SSM4567_REG_STATUS_2, 0x00 },
111 { SSM4567_REG_FAULT_CTRL, 0x30 },
112 { SSM4567_REG_PDM_CTRL, 0x40 },
113 { SSM4567_REG_MCLK_RATIO, 0x11 },
114 { SSM4567_REG_BOOST_CTRL_1, 0x03 },
115 { SSM4567_REG_BOOST_CTRL_2, 0x00 },
116 { SSM4567_REG_SOFT_RESET, 0x00 },
120 static bool ssm4567_readable_reg(struct device *dev, unsigned int reg)
123 case SSM4567_REG_POWER_CTRL ... SSM4567_REG_BOOST_CTRL_2:
131 static bool ssm4567_writeable_reg(struct device *dev, unsigned int reg)
134 case SSM4567_REG_POWER_CTRL ... SSM4567_REG_SAI_PLACEMENT_6:
135 case SSM4567_REG_LIMITER_CTRL_1 ... SSM4567_REG_LIMITER_CTRL_3:
136 case SSM4567_REG_FAULT_CTRL ... SSM4567_REG_BOOST_CTRL_2:
137 /* The datasheet states that soft reset register is read-only,
138 * but logically it is write-only. */
139 case SSM4567_REG_SOFT_RESET:
146 static bool ssm4567_volatile_reg(struct device *dev, unsigned int reg)
149 case SSM4567_REG_BATTERY_V_OUT:
150 case SSM4567_REG_STATUS_1 ... SSM4567_REG_STATUS_2:
151 case SSM4567_REG_SOFT_RESET:
158 static const DECLARE_TLV_DB_MINMAX_MUTE(ssm4567_vol_tlv, -7125, 2400);
160 static const struct snd_kcontrol_new ssm4567_snd_controls[] = {
161 SOC_SINGLE_TLV("Master Playback Volume", SSM4567_REG_DAC_VOLUME, 0,
162 0xff, 1, ssm4567_vol_tlv),
163 SOC_SINGLE("DAC Low Power Mode Switch", SSM4567_REG_DAC_CTRL, 4, 1, 0),
164 SOC_SINGLE("DAC High Pass Filter Switch", SSM4567_REG_DAC_CTRL,
168 static const struct snd_kcontrol_new ssm4567_amplifier_boost_control =
169 SOC_DAPM_SINGLE("Switch", SSM4567_REG_POWER_CTRL, 1, 1, 1);
171 static const struct snd_soc_dapm_widget ssm4567_dapm_widgets[] = {
172 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", SSM4567_REG_POWER_CTRL, 2, 1),
173 SND_SOC_DAPM_SWITCH("Amplifier Boost", SSM4567_REG_POWER_CTRL, 3, 1,
174 &ssm4567_amplifier_boost_control),
176 SND_SOC_DAPM_OUTPUT("OUT"),
179 static const struct snd_soc_dapm_route ssm4567_routes[] = {
180 { "OUT", NULL, "Amplifier Boost" },
181 { "Amplifier Boost", "Switch", "DAC" },
182 { "OUT", NULL, "DAC" },
185 static int ssm4567_hw_params(struct snd_pcm_substream *substream,
186 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
188 struct snd_soc_codec *codec = dai->codec;
189 struct ssm4567 *ssm4567 = snd_soc_codec_get_drvdata(codec);
190 unsigned int rate = params_rate(params);
193 if (rate >= 8000 && rate <= 12000)
194 dacfs = SSM4567_DAC_FS_8000_12000;
195 else if (rate >= 16000 && rate <= 24000)
196 dacfs = SSM4567_DAC_FS_16000_24000;
197 else if (rate >= 32000 && rate <= 48000)
198 dacfs = SSM4567_DAC_FS_32000_48000;
199 else if (rate >= 64000 && rate <= 96000)
200 dacfs = SSM4567_DAC_FS_64000_96000;
201 else if (rate >= 128000 && rate <= 192000)
202 dacfs = SSM4567_DAC_FS_128000_192000;
206 return regmap_update_bits(ssm4567->regmap, SSM4567_REG_DAC_CTRL,
207 SSM4567_DAC_FS_MASK, dacfs);
210 static int ssm4567_mute(struct snd_soc_dai *dai, int mute)
212 struct ssm4567 *ssm4567 = snd_soc_codec_get_drvdata(dai->codec);
215 val = mute ? SSM4567_DAC_MUTE : 0;
216 return regmap_update_bits(ssm4567->regmap, SSM4567_REG_DAC_CTRL,
217 SSM4567_DAC_MUTE, val);
220 static int ssm4567_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
221 unsigned int rx_mask, int slots, int width)
223 struct ssm4567 *ssm4567 = snd_soc_dai_get_drvdata(dai);
231 if (rx_mask && rx_mask != tx_mask)
234 slot = __ffs(tx_mask);
235 if (tx_mask != BIT(slot))
240 blcks = SSM4567_SAI_CTRL_1_TDM_BLCKS_32;
243 blcks = SSM4567_SAI_CTRL_1_TDM_BLCKS_48;
246 blcks = SSM4567_SAI_CTRL_1_TDM_BLCKS_64;
252 ret = regmap_update_bits(ssm4567->regmap, SSM4567_REG_SAI_CTRL_2,
253 SSM4567_SAI_CTRL_2_AUTO_SLOT | SSM4567_SAI_CTRL_2_TDM_SLOT_MASK,
254 SSM4567_SAI_CTRL_2_TDM_SLOT(slot));
258 return regmap_update_bits(ssm4567->regmap, SSM4567_REG_SAI_CTRL_1,
259 SSM4567_SAI_CTRL_1_TDM_BLCKS_MASK, blcks);
262 static int ssm4567_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
264 struct ssm4567 *ssm4567 = snd_soc_dai_get_drvdata(dai);
265 unsigned int ctrl1 = 0;
268 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
269 case SND_SOC_DAIFMT_CBS_CFS:
275 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
276 case SND_SOC_DAIFMT_NB_NF:
279 case SND_SOC_DAIFMT_IB_NF:
280 ctrl1 |= SSM4567_SAI_CTRL_1_BCLK;
283 case SND_SOC_DAIFMT_NB_IF:
284 ctrl1 |= SSM4567_SAI_CTRL_1_FSYNC;
287 case SND_SOC_DAIFMT_IB_IF:
288 ctrl1 |= SSM4567_SAI_CTRL_1_BCLK;
295 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
296 case SND_SOC_DAIFMT_I2S:
298 case SND_SOC_DAIFMT_LEFT_J:
299 ctrl1 |= SSM4567_SAI_CTRL_1_LJ;
300 invert_fclk = !invert_fclk;
302 case SND_SOC_DAIFMT_DSP_A:
303 ctrl1 |= SSM4567_SAI_CTRL_1_TDM;
305 case SND_SOC_DAIFMT_DSP_B:
306 ctrl1 |= SSM4567_SAI_CTRL_1_TDM | SSM4567_SAI_CTRL_1_LJ;
308 case SND_SOC_DAIFMT_PDM:
309 ctrl1 |= SSM4567_SAI_CTRL_1_PDM;
316 ctrl1 |= SSM4567_SAI_CTRL_1_FSYNC;
318 return regmap_write(ssm4567->regmap, SSM4567_REG_SAI_CTRL_1, ctrl1);
321 static int ssm4567_set_power(struct ssm4567 *ssm4567, bool enable)
326 ret = regmap_update_bits(ssm4567->regmap,
327 SSM4567_REG_POWER_CTRL,
328 SSM4567_POWER_SPWDN, SSM4567_POWER_SPWDN);
329 regcache_mark_dirty(ssm4567->regmap);
332 regcache_cache_only(ssm4567->regmap, !enable);
335 ret = regmap_update_bits(ssm4567->regmap,
336 SSM4567_REG_POWER_CTRL,
337 SSM4567_POWER_SPWDN, 0x00);
338 regcache_sync(ssm4567->regmap);
344 static int ssm4567_set_bias_level(struct snd_soc_codec *codec,
345 enum snd_soc_bias_level level)
347 struct ssm4567 *ssm4567 = snd_soc_codec_get_drvdata(codec);
351 case SND_SOC_BIAS_ON:
353 case SND_SOC_BIAS_PREPARE:
355 case SND_SOC_BIAS_STANDBY:
356 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
357 ret = ssm4567_set_power(ssm4567, true);
359 case SND_SOC_BIAS_OFF:
360 ret = ssm4567_set_power(ssm4567, false);
367 codec->dapm.bias_level = level;
372 static const struct snd_soc_dai_ops ssm4567_dai_ops = {
373 .hw_params = ssm4567_hw_params,
374 .digital_mute = ssm4567_mute,
375 .set_fmt = ssm4567_set_dai_fmt,
376 .set_tdm_slot = ssm4567_set_tdm_slot,
379 static struct snd_soc_dai_driver ssm4567_dai = {
380 .name = "ssm4567-hifi",
382 .stream_name = "Playback",
385 .rates = SNDRV_PCM_RATE_8000_192000,
386 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
387 SNDRV_PCM_FMTBIT_S32,
389 .ops = &ssm4567_dai_ops,
392 static struct snd_soc_codec_driver ssm4567_codec_driver = {
393 .set_bias_level = ssm4567_set_bias_level,
394 .idle_bias_off = true,
396 .controls = ssm4567_snd_controls,
397 .num_controls = ARRAY_SIZE(ssm4567_snd_controls),
398 .dapm_widgets = ssm4567_dapm_widgets,
399 .num_dapm_widgets = ARRAY_SIZE(ssm4567_dapm_widgets),
400 .dapm_routes = ssm4567_routes,
401 .num_dapm_routes = ARRAY_SIZE(ssm4567_routes),
404 static const struct regmap_config ssm4567_regmap_config = {
408 .max_register = SSM4567_REG_SOFT_RESET,
409 .readable_reg = ssm4567_readable_reg,
410 .writeable_reg = ssm4567_writeable_reg,
411 .volatile_reg = ssm4567_volatile_reg,
413 .cache_type = REGCACHE_RBTREE,
414 .reg_defaults = ssm4567_reg_defaults,
415 .num_reg_defaults = ARRAY_SIZE(ssm4567_reg_defaults),
418 static int ssm4567_i2c_probe(struct i2c_client *i2c,
419 const struct i2c_device_id *id)
421 struct ssm4567 *ssm4567;
424 ssm4567 = devm_kzalloc(&i2c->dev, sizeof(*ssm4567), GFP_KERNEL);
428 i2c_set_clientdata(i2c, ssm4567);
430 ssm4567->regmap = devm_regmap_init_i2c(i2c, &ssm4567_regmap_config);
431 if (IS_ERR(ssm4567->regmap))
432 return PTR_ERR(ssm4567->regmap);
434 ret = regmap_write(ssm4567->regmap, SSM4567_REG_SOFT_RESET, 0x00);
438 ret = ssm4567_set_power(ssm4567, false);
442 return snd_soc_register_codec(&i2c->dev, &ssm4567_codec_driver,
446 static int ssm4567_i2c_remove(struct i2c_client *client)
448 snd_soc_unregister_codec(&client->dev);
452 static const struct i2c_device_id ssm4567_i2c_ids[] = {
456 MODULE_DEVICE_TABLE(i2c, ssm4567_i2c_ids);
458 static struct i2c_driver ssm4567_driver = {
461 .owner = THIS_MODULE,
463 .probe = ssm4567_i2c_probe,
464 .remove = ssm4567_i2c_remove,
465 .id_table = ssm4567_i2c_ids,
467 module_i2c_driver(ssm4567_driver);
469 MODULE_DESCRIPTION("ASoC SSM4567 driver");
470 MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
471 MODULE_LICENSE("GPL");