2 * linux/sound/soc/codecs/tlv320aic3111.c
5 * Copyright (C) 2010 Texas Instruments, Inc.
7 * This package is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
12 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
13 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 * Rev 0.1 ASoC driver support Mistral 14-04-2010
19 * Rev 0.2 Updated based Review Comments Mistral 29-06-2010
21 * Rev 0.3 Updated for Codec Family Compatibility 12-07-2010
25 *****************************************************************************
27 *****************************************************************************
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
34 #include <linux/i2c.h>
35 #include <linux/platform_device.h>
36 #include <linux/cdev.h>
37 #include <linux/of_gpio.h>
38 #include <linux/seq_file.h>
39 #include <linux/spi/spi.h>
40 #include <linux/clk.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48 #include <sound/tlv.h>
50 //#include <mach/gpio.h>
51 #include "tlv320aic3111.h"
54 #define AIC_DBG(x...) printk(KERN_INFO x)
56 #define AIC_DBG(x...) do { } while (0)
61 #define INVALID_GPIO -1
64 #define AIC3110_IS_SHUTDOWN 0
65 #define AIC3110_IS_CAPTURE_ON 1
66 #define AIC3110_IS_PLAYBACK_ON 2
67 #define AIC3110_IS_INITPOWER_ON 4
70 #define AIC3110_POWERDOWN_NULL 0
71 #define AIC3110_POWERDOWN_PLAYBACK 1
72 #define AIC3110_POWERDOWN_CAPTURE 2
73 #define AIC3110_POWERDOWN_PLAYBACK_CAPTURE 3
74 #define JACK_DET_ADLOOP msecs_to_jiffies(200)
79 int aic3111_spk_ctl_gpio = INVALID_GPIO;
80 int aic3111_hp_det_gpio = INVALID_GPIO;
82 static int aic3111_power_speaker (bool on);
84 struct timer_list timer;
92 POWER_STATE_SW_HP = 0,
96 static void aic3111_work(struct work_struct *work);
98 static struct workqueue_struct *aic3111_workq;
99 static DECLARE_DELAYED_WORK(delayed_work, aic3111_work);
100 static int aic3111_current_status = AIC3110_IS_SHUTDOWN, aic3111_work_type = AIC3110_POWERDOWN_NULL;
101 static bool isHSin = true, isSetHW = false;
102 int old_status = SPK;
104 *****************************************************************************
106 *****************************************************************************
108 /* Used to maintain the Register Access control*/
109 static u8 aic3111_reg_ctl;
111 static struct snd_soc_codec *aic3111_codec;
112 struct aic3111_priv *aic3111_privdata;
113 struct i2c_client *aic3111_i2c;
115 /* add a timer for checkout HP or SPK*/
116 static struct timer_list aic3111_timer;
118 /*Used to delay work hpdet switch irq handle*/
119 struct delayed_work aic3111_hpdet_work;
121 #ifdef CONFIG_MINI_DSP
122 extern int aic3111_minidsp_program (struct snd_soc_codec *codec);
123 extern void aic3111_add_minidsp_controls (struct snd_soc_codec *codec);
127 * AIC3111 register cache
128 * We are caching the registers here.
129 * NOTE: In AIC3111, there are 61 pages of 128 registers supported.
130 * The following table contains the page0, page1 and page2 registers values.
133 #ifdef AIC3111_CODEC_SUPPORT
134 static const u8 aic31xx_reg[AIC31xx_CACHEREGNUM] = {
135 /* Page 0 Registers */
136 /* 0 */ 0x00, 0x00, 0x12, 0x00, 0x00, 0x11, 0x04, 0x00, 0x00, 0x00, 0x00,
137 0x01, 0x01, 0x00, 0x80, 0x80,
138 /* 10 */ 0x08, 0x00, 0x01, 0x01, 0x80, 0x80, 0x04, 0x00, 0x01, 0x00, 0x00,
139 0x00, 0x01, 0x00, 0x00, 0x00,
140 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
141 0x00, 0x00, 0x00, 0x00, 0x00,
142 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x55, 0x00, 0x00,
143 0x00, 0x01, 0x01, 0x00, 0x14,
144 /* 40 */ 0x0c, 0x00, 0x00, 0x00, 0x6f, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
145 0xee, 0x10, 0xd8, 0x7e, 0xe3,
146 /* 50 */ 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00,
147 0x00, 0x00, 0x00, 0x00, 0x00,
148 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
149 0x00, 0x00, 0x00, 0x00, 0x00,
150 /* 70 */ 0x00, 0x00, 0x10, 0x32, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
151 0x00, 0x00, 0x00, 0x12, 0x02,
152 /* Page 1 Registers */
153 /* 0 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
154 0x00, 0x00, 0x00, 0x00, 0x00,
155 /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
156 0x00, 0x00, 0x00, 0x00, 0x00,
157 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
158 0x00, 0x00, 0x00, 0x00, 0x00,
159 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
160 0x80, 0x80, 0x00, 0x00, 0x00,
161 /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
162 0x00, 0x00, 0x00, 0x00, 0x00,
163 /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
164 0x00, 0x00, 0x00, 0x00, 0x00,
165 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
166 0x00, 0x00, 0x00, 0x00, 0x00,
167 /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
168 0x00, 0x00, 0x00, 0x00, 0x00,
171 #elif defined(AIC3110_CODEC_SUPPORT)
172 /**************** AIC3110 REG CACHE ******************/
173 static const u8 aic31xx_reg[AIC31xx_CACHEREGNUM] = {
174 /* Page 0 Registers */
175 0x00, 0x00, 0x01, 0x56, 0x00, 0x11, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x80,
176 0x08, 0x00, 0x01, 0x01, 0x80, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
177 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
178 0x00, 0x00, 0x00, 0x02, 0x32, 0x12, 0x03, 0x02, 0x02, 0x11, 0x10, 0x00, 0x01, 0x04, 0x00, 0x14,
179 0x0c, 0x00, 0x00, 0x00, 0x0f, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0xee, 0x10, 0xd8, 0x7e, 0xe3,
180 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
182 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
183 /* Page 1 Registers */
184 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
186 0x06, 0x3e, 0x00, 0x00, 0x7f, 0x7f, 0x7f, 0x7f, 0x02, 0x02, 0x00, 0x00, 0x20, 0x86, 0x00, 0x80,
187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
189 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192 }; /**************************** End of AIC3110 REG CAHE ******************/
194 #elif defined(AIC3100_CODEC_SUPPORT)
195 /******************************* AIC3100 REG CACHE ***********************/
196 static const u8 aic31xx_reg[AIC31xx_CACHEREGNUM] = {
197 /* Page 0 Registers */
198 /* 0 */ 0x00, 0x00, 0x12, 0x00, 0x00, 0x11, 0x04, 0x00, 0x00, 0x00, 0x00,
199 0x01, 0x01, 0x00, 0x80, 0x00,
200 /* 10 */ 0x00, 0x00, 0x01, 0x01, 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
201 0x00, 0x01, 0x00, 0x00, 0x00,
202 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
203 0x00, 0x00, 0x00, 0x00, 0x00,
204 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x55, 0x00, 0x00,
205 0x00, 0x01, 0x01, 0x00, 0x14,
206 /* 40 */ 0x0c, 0x00, 0x00, 0x00, 0x6f, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
207 0xee, 0x10, 0xd8, 0x7e, 0xe3,
208 /* 50 */ 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00,
209 0x00, 0x00, 0x00, 0x00, 0x00,
210 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
211 0x00, 0x00, 0x00, 0x00, 0x00,
212 /* 70 */ 0x00, 0x00, 0x10, 0x32, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
213 0x00, 0x00, 0x00, 0x12, 0x02,
214 /* Page 1 Registers */
215 /* 0 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
216 0x00, 0x00, 0x00, 0x00, 0x00,
217 /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
218 0x00, 0x00, 0x00, 0x00, 0x00,
219 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
220 0x00, 0x00, 0x00, 0x00, 0x00,
221 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
222 0x80, 0x80, 0x00, 0x00, 0x00,
223 /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
224 0x00, 0x00, 0x00, 0x00, 0x00,
225 /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
226 0x00, 0x00, 0x00, 0x00, 0x00,
227 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
228 0x00, 0x00, 0x00, 0x00, 0x00,
229 /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
230 0x00, 0x00, 0x00, 0x00, 0x00,
231 }; /**************************** End of AIC3100 REG CACHE ******************/
233 #else /*#ifdef AIC3120_CODEC_SUPPORT */
234 static const u8 aic31xx_reg[AIC31xx_CACHEREGNUM] = {
235 /* Page 0 Registers */
236 /* 0 */ 0x00, 0x00, 0x12, 0x00, 0x00, 0x11, 0x04, 0x00, 0x00, 0x00, 0x00,
237 0x01, 0x01, 0x00, 0x80, 0x80,
238 /* 10 */ 0x08, 0x00, 0x01, 0x01, 0x80, 0x80, 0x04, 0x00, 0x01, 0x00, 0x00,
239 0x00, 0x01, 0x00, 0x00, 0x00,
240 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
241 0x00, 0x00, 0x00, 0x00, 0x00,
242 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x55, 0x00, 0x00,
243 0x00, 0x01, 0x01, 0x00, 0x14,
244 /* 40 */ 0x0c, 0x00, 0x00, 0x00, 0x6f, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
245 0xee, 0x10, 0xd8, 0x7e, 0xe3,
246 /* 50 */ 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00,
247 0x00, 0x00, 0x00, 0x00, 0x00,
248 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
249 0x00, 0x00, 0x00, 0x00, 0x00,
250 /* 70 */ 0x00, 0x00, 0x10, 0x32, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
251 0x00, 0x00, 0x00, 0x12, 0x02,
252 /* Page 1 Registers */
253 /* 0 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
254 0x00, 0x00, 0x00, 0x00, 0x00,
255 /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
256 0x00, 0x00, 0x00, 0x00, 0x00,
257 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
258 0x00, 0x00, 0x00, 0x00, 0x00,
259 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
260 0x80, 0x80, 0x00, 0x00, 0x00,
261 /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
262 0x00, 0x00, 0x00, 0x00, 0x00,
263 /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
264 0x00, 0x00, 0x00, 0x00, 0x00,
265 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
266 0x00, 0x00, 0x00, 0x00, 0x00,
267 /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
268 0x00, 0x00, 0x00, 0x00, 0x00,
274 *----------------------------------------------------------------------------
275 * Function : aic3111_change_page
276 * Purpose : This function is to switch between page 0 and page 1.
278 *----------------------------------------------------------------------------
280 static int aic3111_change_page (struct snd_soc_codec *codec, u8 new_page)
282 struct aic3111_priv *aic3111 = aic3111_privdata;
285 if (new_page == 2 || new_page > 8) {
286 printk("ERROR::codec do not have page %d !!!!!!\n", new_page);
292 aic3111->page_no = new_page;
294 if (codec->hw_write (codec->control_data, data, 2) != 2)
296 printk ("Error in changing page to %d \n", new_page);
304 *----------------------------------------------------------------------------
305 * Function : aic3111_write_reg_cache
306 * Purpose : This function is to write aic3111 register cache
308 *----------------------------------------------------------------------------
310 static inline void aic3111_write_reg_cache (struct snd_soc_codec *codec, u16 reg, u8 value)
312 u8 *cache = codec->reg_cache;
314 if (reg >= AIC31xx_CACHEREGNUM)
323 *----------------------------------------------------------------------------
324 * Function : aic3111_read
325 * Purpose : This function is to read the aic3111 register space.
327 *----------------------------------------------------------------------------
329 static unsigned int aic3111_read (struct snd_soc_codec *codec, unsigned int reg)
331 struct aic3111_priv *aic3111 = aic3111_privdata;
335 if (page == 2 || page > 8) {
336 printk("aic3111_read::Error page, there's not page %d in codec tlv320aic3111 !!!\n", page);
342 if (aic3111->page_no != page)
344 aic3111_change_page (codec, page);
347 i2c_master_send (codec->control_data, (char *) ®, 1);
348 i2c_master_recv (codec->control_data, &value, 1);
354 *----------------------------------------------------------------------------
355 * Function : aic3111_write
356 * Purpose : This function is to write to the aic3111 register space.
358 *----------------------------------------------------------------------------
360 static int aic3111_write (struct snd_soc_codec *codec, unsigned int reg, unsigned int value)
362 struct aic3111_priv *aic3111 = aic3111_privdata;
365 //printk("enter %s!!!!!!\n",__FUNCTION__);
366 //printk("aic3111_hp_det_gpio =%d!!!!!!\n",gpio_get_value(aic3111_hp_det_gpio));
368 data[AIC3111_REG_OFFSET_INDEX] = reg % 128;
370 if (page == 2 || page > 9) {
371 printk("aic3111_write::Error page, there's not page %d in codec tlv320aic3111 !!!\n", page);
375 if (aic3111->page_no != page)
377 aic3111_change_page (codec, page);
381 * D15..D8 aic3111 register offset
382 * D7...D0 register data
384 data[AIC3111_REG_DATA_INDEX] = value & AIC3111_8BITS_MASK;
385 #if defined(EN_REG_CACHE)
386 if ((page == 0) || (page == 1))
388 aic3111_write_reg_cache (codec, reg, value);
391 if (codec->hw_write (codec->control_data, data, 2) != 2)
393 printk ("Error in i2c write\n");
400 static int aic3111_print_register_cache (struct platform_device *pdev)
402 struct snd_soc_codec *codec = aic3111_codec;
403 u8 *cache = codec->reg_cache;
406 printk ("\n========3110 reg========\n");
407 for (reg = 0; reg < codec->reg_size; reg++)
409 if (reg == 0) printk ("Page 0\n");
410 if (reg == 128) printk ("\nPage 1\n");
411 if (reg%16 == 0 && reg != 0 && reg != 128) printk ("\n");
412 printk("0x%02x, ",aic3111_read(codec,reg));
414 printk ("\n========3110 cache========\n");
415 for (reg = 0; reg < codec->reg_size; reg++)
417 if (reg == 0) printk ("Page 0\n");
418 if (reg == 128) printk ("\nPage 1\n");
419 if (reg%16 == 0 && reg != 0 && reg != 128) printk ("\n");
420 printk ("0x%02x, ",cache[reg]);
422 printk ("\n==========================\n");
426 static void aic3111_soft_reset (void)
428 struct snd_soc_codec *codec = aic3111_codec;
430 AIC_DBG("CODEC::%s\n",__FUNCTION__);
432 //aic3111_write (codec, 1, 0x01);
433 aic3111_write (codec, 63, 0x00);
434 gpio_set_value(aic3111_spk_ctl_gpio, GPIO_LOW);
436 aic3111_write (aic3111_codec, (68), 0x01); //disable DRC
437 aic3111_write (aic3111_codec, (128 + 31), 0xc4);
438 aic3111_write (aic3111_codec, (128 + 36), 0x28); //Left Analog Vol to HPL
439 aic3111_write (aic3111_codec, (128 + 37), 0x28); //Right Analog Vol to HPL
440 aic3111_write (aic3111_codec, (128 + 40), 0x4f); //HPL driver PGA
441 aic3111_write (aic3111_codec, (128 + 41), 0x4f); //HPR driver PGA
442 aic3111_power_speaker(POWER_STATE_OFF);
444 aic3111_write (codec, 1, 0x00);
446 memcpy(codec->reg_cache, aic31xx_reg,
447 sizeof(aic31xx_reg));
455 *----------------------------------------------------------------------------
456 * Function : aic3111_set_bias_level
457 * Purpose : This function is to get triggered when dapm events occurs.
459 *----------------------------------------------------------------------------
461 static int aic3111_set_bias_level(struct snd_soc_codec *codec,
462 enum snd_soc_bias_level level)
464 struct aic3111_priv *aic3111 = aic3111_privdata;
470 AIC_DBG ("CODEC::%s>>>>>>level:%d>>>>master:%d\n", __FUNCTION__, level, aic3111->master);
474 case SND_SOC_BIAS_ON:
475 /* all power is driven by DAPM system */
479 value = aic3111_read(codec, CLK_REG_2);
480 aic3111_write(codec, CLK_REG_2, (value | ENABLE_PLL));
482 /* Switch on NDAC Divider */
483 value = aic3111_read(codec, NDAC_CLK_REG);
484 aic3111_write(codec, NDAC_CLK_REG, value | ENABLE_NDAC);
486 /* Switch on MDAC Divider */
487 value = aic3111_read(codec, MDAC_CLK_REG);
488 aic3111_write(codec, MDAC_CLK_REG, value | ENABLE_MDAC);
490 /* Switch on NADC Divider */
491 value = aic3111_read(codec, NADC_CLK_REG);
492 aic3111_write(codec, NADC_CLK_REG, value | ENABLE_MDAC);
494 /* Switch on MADC Divider */
495 value = aic3111_read(codec, MADC_CLK_REG);
496 aic3111_write(codec, MADC_CLK_REG, value | ENABLE_MDAC);
498 /* Switch on BCLK_N Divider */
499 value = aic3111_read(codec, BCLK_N_VAL);
500 aic3111_write(codec, BCLK_N_VAL, value | ENABLE_BCLK);
503 value = aic3111_read(codec, CLK_REG_2);
504 aic3111_write(codec, CLK_REG_2, (value | ENABLE_PLL));
506 /* Switch on NDAC Divider */
507 value = aic3111_read(codec, NDAC_CLK_REG);
508 aic3111_write(codec, NDAC_CLK_REG, value | ENABLE_NDAC);
510 /* Switch on MDAC Divider */
511 value = aic3111_read(codec, MDAC_CLK_REG);
512 aic3111_write(codec, MDAC_CLK_REG, value | ENABLE_MDAC);
514 /* Switch on NADC Divider */
515 value = aic3111_read(codec, NADC_CLK_REG);
516 aic3111_write(codec, NADC_CLK_REG, value | ENABLE_MDAC);
518 /* Switch on MADC Divider */
519 value = aic3111_read(codec, MADC_CLK_REG);
520 aic3111_write(codec, MADC_CLK_REG, value | ENABLE_MDAC);
522 /* Switch on BCLK_N Divider */
523 value = aic3111_read(codec, BCLK_N_VAL);
524 aic3111_write(codec, BCLK_N_VAL, value | ENABLE_BCLK);
529 case SND_SOC_BIAS_PREPARE:
532 /* Off, with power */
533 case SND_SOC_BIAS_STANDBY:
535 * all power is driven by DAPM system,
536 * so output power is safe if bypass was set
541 value = aic3111_read(codec, CLK_REG_2);
542 aic3111_write(codec, CLK_REG_2, (value & ~ENABLE_PLL));
544 /* Switch off NDAC Divider */
545 value = aic3111_read(codec, NDAC_CLK_REG);
546 aic3111_write(codec, NDAC_CLK_REG, value & ~ENABLE_NDAC);
548 /* Switch off MDAC Divider */
549 value = aic3111_read(codec, MDAC_CLK_REG);
550 aic3111_write(codec, MDAC_CLK_REG, value & ~ENABLE_MDAC);
552 /* Switch off NADC Divider */
553 value = aic3111_read(codec, NADC_CLK_REG);
554 aic3111_write(codec, NADC_CLK_REG, value & ~ENABLE_NDAC);
556 /* Switch off MADC Divider */
557 value = aic3111_read(codec, MADC_CLK_REG);
558 aic3111_write(codec, MADC_CLK_REG, value & ~ENABLE_MDAC);
559 value = aic3111_read(codec, BCLK_N_VAL);
561 /* Switch off BCLK_N Divider */
562 aic3111_write(codec, BCLK_N_VAL, value & ~ENABLE_BCLK);
566 /* Off, without power */
567 case SND_SOC_BIAS_OFF:
568 /* force all power off */
571 codec->dapm.bias_level = level;
575 /* the structure contains the different values for mclk */
576 static const struct aic3111_rate_divs aic3111_divs[] = {
578 * mclk, rate, p_val, pll_j, pll_d, dosr, ndac, mdac, aosr, nadc, madc, blck_N,
579 * codec_speficic_initializations
582 {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
583 //{12288000, 8000, 1, 7, 8643, 768, 5, 3, 128, 5, 18, 24},
584 {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
586 {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
587 {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
589 {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
590 {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
592 {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
593 {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
595 {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
596 {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
598 {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
599 {11289600, 44100, 1, 8, 0, 128, 4, 4, 128, 4, 4, 4},
600 {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
602 {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
603 {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
605 {12000000, 96000, 1, 8, 1920, 64, 2, 8, 64, 2, 8, 2},
606 {24000000, 96000, 2, 8, 1920, 64, 4, 4, 64, 8, 2, 2},
608 {12000000, 192000, 1, 8, 1920, 32, 2, 8, 32, 2, 8, 1},
609 {24000000, 192000, 2, 8, 1920, 32, 4, 4, 32, 4, 4, 1},
613 *----------------------------------------------------------------------------
614 * Function : aic3111_get_divs
615 * Purpose : This function is to get required divisor from the "aic3111_divs"
618 *----------------------------------------------------------------------------
620 static inline int aic3111_get_divs (int mclk, int rate)
624 AIC_DBG("Enter::%s\n",__FUNCTION__);
626 for (i = 0; i < ARRAY_SIZE (aic3111_divs); i++)
628 if ((aic3111_divs[i].rate == rate) && (aic3111_divs[i].mclk == mclk))
634 printk ("Master clock and sample rate is not supported\n");
639 *----------------------------------------------------------------------------
640 * Function : aic3111_hw_params
641 * Purpose : This function is to set the hardware parameters for AIC3111.
642 * The functions set the sample rate and audio serial data word
645 *----------------------------------------------------------------------------
647 static int aic3111_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params,
648 struct snd_soc_dai *codec_dai)
650 struct snd_soc_codec *codec = aic3111_codec;
651 struct aic3111_priv *aic3111 = aic3111_privdata;
658 AIC_DBG("CODEC::%s\n", __FUNCTION__);
660 aic3111_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
662 i = aic3111_get_divs(aic3111->sysclk, params_rate (params));
665 printk ("sampling rate not supported\n");
669 /* We will fix R value to 1 and will make P & J=K.D as varialble */
671 /* Setting P & R values */
672 aic3111_write(codec, CLK_REG_2, ((aic3111_divs[i].p_val << 4) | 0x01));
675 aic3111_write(codec, CLK_REG_3, aic3111_divs[i].pll_j);
677 /* MSB & LSB for D value */
678 aic3111_write(codec, CLK_REG_4, (aic3111_divs[i].pll_d >> 8));
679 aic3111_write(codec, CLK_REG_5, (aic3111_divs[i].pll_d & AIC3111_8BITS_MASK));
681 /* NDAC divider value */
682 aic3111_write(codec, NDAC_CLK_REG, aic3111_divs[i].ndac);
684 /* MDAC divider value */
685 aic3111_write(codec, MDAC_CLK_REG, aic3111_divs[i].mdac);
687 /* DOSR MSB & LSB values */
688 aic3111_write(codec, DAC_OSR_MSB, aic3111_divs[i].dosr >> 8);
689 aic3111_write(codec, DAC_OSR_LSB, aic3111_divs[i].dosr & AIC3111_8BITS_MASK);
691 /* NADC divider value */
692 aic3111_write(codec, NADC_CLK_REG, aic3111_divs[i].nadc);
694 /* MADC divider value */
695 aic3111_write(codec, MADC_CLK_REG, aic3111_divs[i].madc);
698 aic3111_write(codec, ADC_OSR_REG, aic3111_divs[i].aosr);
701 aic3111_write(codec, BCLK_N_VAL, aic3111_divs[i].blck_N);
703 aic3111_set_bias_level(codec, SND_SOC_BIAS_ON);
705 data = aic3111_read(codec, INTERFACE_SET_REG_1);
707 data = data & ~(3 << 4);
709 switch (params_format (params)) {
710 case SNDRV_PCM_FORMAT_S16_LE:
712 case SNDRV_PCM_FORMAT_S20_3LE:
713 data |= (AIC3111_WORD_LEN_20BITS << DATA_LEN_SHIFT);
715 case SNDRV_PCM_FORMAT_S24_LE:
716 data |= (AIC3111_WORD_LEN_24BITS << DATA_LEN_SHIFT);
718 case SNDRV_PCM_FORMAT_S32_LE:
719 data |= (AIC3111_WORD_LEN_32BITS << DATA_LEN_SHIFT);
723 aic3111_write(codec, INTERFACE_SET_REG_1, data);
729 *----------------------------------------------------------------------------
730 * Function : aic3111_mute
731 * Purpose : This function is to mute or unmute the left and right DAC
733 *----------------------------------------------------------------------------
735 static int aic3111_mute (struct snd_soc_dai *codec_dai, int mute)
737 struct snd_soc_codec *codec = codec_dai->codec;
740 AIC_DBG ("CODEC::%s>>>>mute:%d\n", __FUNCTION__, mute);
742 dac_reg = aic3111_read (codec, DAC_MUTE_CTRL_REG) & ~MUTE_ON;
744 ;//aic3111_write (codec, DAC_MUTE_CTRL_REG, dac_reg | MUTE_ON);
746 //aic3111_write (codec, DAC_MUTE_CTRL_REG, dac_reg);
754 *----------------------------------------------------------------------------
755 * Function : aic3111_set_dai_sysclk
756 * Purpose : This function is to set the DAI system clock
758 *----------------------------------------------------------------------------
760 static int aic3111_set_dai_sysclk (struct snd_soc_dai *codec_dai,
761 int clk_id, unsigned int freq, int dir)
763 struct aic3111_priv *aic3111 = aic3111_privdata;
768 AIC_DBG("Enter %s and line %d\n",__FUNCTION__,__LINE__);
771 case AIC3111_FREQ_11289600:
772 case AIC3111_FREQ_12000000:
773 case AIC3111_FREQ_24000000:
774 aic3111->sysclk = freq;
778 printk ("Invalid frequency to set DAI system clock\n");
783 *----------------------------------------------------------------------------
784 * Function : aic3111_set_dai_fmt
785 * Purpose : This function is to set the DAI format
787 *----------------------------------------------------------------------------
789 static int aic3111_set_dai_fmt (struct snd_soc_dai *codec_dai, unsigned int fmt)
791 struct snd_soc_codec *codec = codec_dai->codec;
792 struct aic3111_priv *aic3111 = aic3111_privdata;
798 AIC_DBG("Enter %s and line %d\n",__FUNCTION__,__LINE__);
800 iface_reg = aic3111_read (codec, INTERFACE_SET_REG_1);
801 iface_reg = iface_reg & ~(3 << 6 | 3 << 2); //set I2S mode BCLK and WCLK is input
803 /* set master/slave audio interface */
804 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
805 case SND_SOC_DAIFMT_CBM_CFM:
807 iface_reg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
809 case SND_SOC_DAIFMT_CBS_CFS:
811 iface_reg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
813 case SND_SOC_DAIFMT_CBS_CFM:
815 iface_reg |= BIT_CLK_MASTER;
816 iface_reg &= ~(WORD_CLK_MASTER);
819 printk ("Invalid DAI master/slave interface\n");
823 /* interface format */
824 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
825 case SND_SOC_DAIFMT_I2S:
827 case SND_SOC_DAIFMT_DSP_A:
828 iface_reg |= (AIC3111_DSP_MODE << AUDIO_MODE_SHIFT);
830 case SND_SOC_DAIFMT_RIGHT_J:
831 iface_reg |= (AIC3111_RIGHT_JUSTIFIED_MODE << AUDIO_MODE_SHIFT);
833 case SND_SOC_DAIFMT_LEFT_J:
834 iface_reg |= (AIC3111_LEFT_JUSTIFIED_MODE << AUDIO_MODE_SHIFT);
837 printk ("Invalid DAI interface format\n");
841 aic3111_write (codec, INTERFACE_SET_REG_1, iface_reg);
848 *----------------------------------------------------------------------------
849 * Function : aic3111_power_headphone
851 * parameter: on = 1: power up;
854 *----------------------------------------------------------------------------
856 static int aic3111_power_headphone (bool on)
858 struct snd_soc_codec *codec = aic3111_codec;
860 AIC_DBG("Enter %s and line %d\n",__FUNCTION__,__LINE__);
862 if (on == POWER_STATE_ON) {
863 aic3111_write (codec, (63), 0xd4);
864 // aic3111_write(codec, (128 + 35), 0x88);
865 aic3111_write (codec, (68), 0x01); //disable DRC
866 aic3111_write (codec, (128 + 31), 0xc4);
867 aic3111_write (codec, (128 + 44), 0x00);
868 aic3111_write (codec, (128 + 36), 0x28); //Left Analog Vol to HPL
869 aic3111_write (codec, (128 + 37), 0x28); //Right Analog Vol to HPL
870 // aic3111_write (codec, (128 + 40), 0x06); //HPL driver PGA
871 // aic3111_write (codec, (128 + 41), 0x06); //HPR driver PGA
872 aic3111_write (codec, (128 + 40), 0x4f); //HPL driver PGA
873 aic3111_write (codec, (128 + 41), 0x4f); //HPR driver PGA
875 } else if (on == POWER_STATE_OFF) {
877 aic3111_write (codec, (128 + 31), 0x00);
878 aic3111_write (codec, (128 + 44), 0x00);
879 aic3111_write (codec, (128 + 36), 0xff);
880 aic3111_write (codec, (128 + 37), 0xff);
881 aic3111_write (codec, (128 + 40), 0x02);
882 aic3111_write (codec, (128 + 41), 0x02);
889 *----------------------------------------------------------------------------
890 * Function : aic3111_power_speaker
892 * parameter: on = 1: power up;
895 *----------------------------------------------------------------------------
897 static int aic3111_power_speaker (bool on)
899 struct snd_soc_codec *codec = aic3111_codec;
901 AIC_DBG("Enter %s and line %d\n",__FUNCTION__,__LINE__);
903 if (on == POWER_STATE_ON) {
905 // aic3111_write(codec, (128 + 32), 0x86);
906 aic3111_write(codec, (128 + 32), 0xc6);
907 aic3111_write(codec, (128 + 30), 0x00);
908 // aic3111_write(codec, (128 + 38), 0x08); //set left speaker analog gain to -4.88db
909 aic3111_write(codec, (128 + 38), 0x16); //set left speaker analog gain to -4.88db
910 aic3111_write(codec, (128 + 39), 0x16); //Right Analog Vol to SPR
911 // aic3111_write(codec, (128 + 38), 0x7f); //set left speaker analog gain to -4.88db
912 // aic3111_write(codec, (128 + 39), 0x7f); //Right Analog Vol to SPR
913 aic3111_write(codec, (128 + 42), 0x1d); //set left speaker driver gain to 12db
914 aic3111_write(codec, (128 + 43), 0x1d); //bit3-4 output stage gain
915 // aic3111_write(codec, (128 + 43), 0x00); //bit3-4 output stage gain
916 aic3111_write(codec, (37), 0x98);
919 aic3111_write(codec, (60), 0x02); //select PRB_P2
920 aic3111_write(codec, (68), 0x61); //enable left and right DRC, set DRC threshold to -3db, set DRC hystersis to 1db
921 aic3111_write(codec, (69), 0x00); //set hold time disable
922 aic3111_write(codec, (70), 0x5D); //set attack time to 0.125db per sample period and decay time to 0.000488db per sample
926 aic3111_write(codec, (63), 0xfc);
927 aic3111_write(codec, (128 + 32), 0xc6);
928 aic3111_write(codec, (128 + 30), 0x00);
929 aic3111_write(codec, (128 + 39), 0x08); //set left speaker analog gain to -4.88db
930 aic3111_write(codec, (128 + 38), 0x08); //Right Analog Vol to SPR
931 aic3111_write(codec, (128 + 43), 0x0D); //set left speaker driver gain to 12db
932 aic3111_write(codec, (128 + 42), 0x0D); //bit3-4 output stage gain
933 aic3111_write(codec, (37), 0x99);
936 aic3111_write(codec, (60), 0x02); //select PRB_P2
937 aic3111_write(codec, (68), 0x61); //enable left and right DRC, set DRC threshold to -3db, set DRC hystersis to 1db
938 aic3111_write(codec, (69), 0x00); //set hold time disable
939 aic3111_write(codec, (70), 0x5D); //set attack time to 0.125db per sample period and decay time to 0.000488db per sample
942 } else if (on == POWER_STATE_OFF) {
944 aic3111_write(codec, (68), 0x01); //disable DRC
945 aic3111_write(codec, (128 + 32), 0x06);
946 aic3111_write(codec, (128 + 30), 0x00);
947 aic3111_write(codec, (128 + 38), 0xff);
948 aic3111_write(codec, (128 + 39), 0xff);
949 aic3111_write(codec, (128 + 42), 0x00);
950 aic3111_write(codec, (128 + 43), 0x00);
951 aic3111_write(codec, (37), 0x00);
958 *----------------------------------------------------------------------------
959 * Function : aic3111_HS_switch
960 * Purpose : This function is to initialise the AIC3111 driver
961 * In PLAYBACK, switch between HP and SPK app.
962 * parameter: on = 1: SPK power up & HP power dn;
963 * on = 0: HP power up & SPK power dn;
965 *----------------------------------------------------------------------------
967 static int aic3111_HS_switch (bool on)
969 AIC_DBG("enter %s and line %d\n",__FUNCTION__,__LINE__);
971 if (POWER_STATE_SW_SPK == on) {
973 //aic3111_power_headphone (POWER_STATE_OFF);
974 aic3111_power_speaker (POWER_STATE_ON);
975 } else if (POWER_STATE_SW_HP == on) {
977 aic3111_power_speaker (POWER_STATE_OFF);
978 //aic3111_power_headphone (POWER_STATE_ON);
980 //aic3111_power_speaker (POWER_STATE_ON);
981 //aic3111_power_headphone (POWER_STATE_OFF);
988 *----------------------------------------------------------------------------
989 * Function : aic3111_SPK_HS_powerdown
990 * Purpose : This function is to power down HP and SPK.
992 *----------------------------------------------------------------------------
994 static int aic3111_SPK_HS_powerdown (void)
996 AIC_DBG("enter %s and line %d\n",__FUNCTION__,__LINE__);
998 //aic3111_power_headphone (POWER_STATE_OFF);
999 aic3111_power_speaker (POWER_STATE_OFF);
1000 // aic3111_power_speaker (POWER_STATE_ON);
1006 *----------------------------------------------------------------------------
1007 * Function : aic3111_power_init
1008 * Purpose : pll clock setting
1009 * parameter: on = 1: power up;
1011 * xjq@rock-chips.com
1012 *----------------------------------------------------------------------------
1014 static void aic3111_power_init (void)
1016 struct snd_soc_codec *codec = aic3111_codec;
1018 AIC_DBG("enter %s and line %d\n",__FUNCTION__,__LINE__);
1020 if (!(aic3111_current_status & AIC3110_IS_INITPOWER_ON)) {
1022 AIC_DBG ("CODEC::%s\n", __FUNCTION__);
1024 aic3111_write(codec, (128 + 46), 0x0b);
1025 aic3111_write(codec, (128 + 35), 0x44);
1026 aic3111_write(codec, (4), 0x03);
1027 aic3111_write(codec, (29), 0x01);
1028 aic3111_write(codec, (48), 0xC0);
1029 aic3111_write(codec, (51), 0x14);
1030 aic3111_write(codec, (67), 0x82);
1032 aic3111_current_status |= AIC3110_IS_INITPOWER_ON;
1039 *----------------------------------------------------------------------------
1040 * Function : aic3111_power_playback
1042 * parameter: on = 1: power up;
1044 * xjq@rock-chips.com
1045 *----------------------------------------------------------------------------
1047 static int aic3111_power_playback (bool on)
1049 struct snd_soc_codec *codec = aic3111_codec;
1051 AIC_DBG ("CODEC::%s>>>>>>%d\n", __FUNCTION__, on);
1052 gpio_set_value(aic3111_spk_ctl_gpio, GPIO_LOW);
1053 aic3111_power_init();
1055 if ((on == POWER_STATE_ON) &&
1056 !(aic3111_current_status & AIC3110_IS_PLAYBACK_ON)) {
1058 //gpio_set_value(aic3111_spk_ctl_gpio, GPIO_HIGH);
1060 /****open HPL and HPR*******/
1061 //aic3111_write(codec, (63), 0xfc);
1063 aic3111_write(codec, (65), 0x00); //LDAC VOL
1064 aic3111_write(codec, (66), 0x00); //RDAC VOL
1065 aic3111_write (aic3111_codec, (63), 0xd4);
1066 // aic3111_write(codec, (128 + 35), 0x88);
1068 //aic3111_write (aic3111_codec, (68), 0x01); //disable DRC
1069 //aic3111_write (aic3111_codec, (128 + 31), 0xc4);
1070 aic3111_write (aic3111_codec, (128 + 44), 0x00);
1071 //aic3111_write (aic3111_codec, (128 + 36), 0x28); //Left Analog Vol to HPL
1072 //aic3111_write (aic3111_codec, (128 + 37), 0x28); //Right Analog Vol to HPL
1073 aic3111_write (codec, (128 + 40), 0x06); //HPL driver PGA
1074 aic3111_write (codec, (128 + 41), 0x06); //HPR driver PGA
1075 //aic3111_write (aic3111_codec, (128 + 40), 0x4f); //HPL driver PGA
1076 //aic3111_write (aic3111_codec, (128 + 41), 0x4f); //HPR driver PGA
1077 //printk("HP INIT~~~~~~~~~~~~~~~~~~~~~~~~~`\n");
1078 /***************************/
1080 aic3111_HS_switch(isHSin);
1082 aic3111_write(codec, (65), 0x10); //LDAC VOL to +8db
1083 aic3111_write(codec, (66), 0x10); //RDAC VOL to +8db
1085 aic3111_write(codec, (64), 0x00);
1087 aic3111_current_status |= AIC3110_IS_PLAYBACK_ON;
1089 } else if ((on == POWER_STATE_OFF) &&
1090 (aic3111_current_status & AIC3110_IS_PLAYBACK_ON)) {
1092 aic3111_write(codec, (68), 0x01); //disable DRC
1093 aic3111_write(codec, (64), 0x0c);
1094 aic3111_write(codec, (63), 0x00);
1095 aic3111_write(codec, (65), 0x00); //LDAC VOL
1096 aic3111_write(codec, (66), 0x00); //RDAC VOL
1098 aic3111_SPK_HS_powerdown();
1100 aic3111_current_status &= ~AIC3110_IS_PLAYBACK_ON;
1103 gpio_set_value(aic3111_spk_ctl_gpio, GPIO_HIGH);
1109 *----------------------------------------------------------------------------
1110 * Function : aic3111_power_capture
1112 * parameter: on = 1: power up;
1114 * xjq@rock-chips.com
1115 *----------------------------------------------------------------------------
1117 static int aic3111_power_capture (bool on)
1119 struct snd_soc_codec *codec = aic3111_codec;
1121 AIC_DBG ("CODEC::%s>>>>>>%d\n", __FUNCTION__, on);
1123 aic3111_power_init();
1125 if ((on == POWER_STATE_ON) &&
1126 !(aic3111_current_status & AIC3110_IS_CAPTURE_ON)) {
1127 aic3111_write(codec, (64), 0x0c);
1130 aic3111_write(codec, (61), 0x0b);
1131 aic3111_write(codec, (128 + 47), 0x00); //MIC PGA 0x80:0dB 0x14:10dB 0x28:20dB 0x3c:30dB 0x77:59dB
1132 aic3111_write(codec, (128 + 48), 0x80); //MIC1LP\MIC1LM RIN = 10.
1133 aic3111_write(codec, (128 + 49), 0x20);
1134 aic3111_write(codec, (82), 0x00); //D7=0:0: ADC channel not muted
1135 aic3111_write(codec, (83), 0x1A); //ADC Digital Volume 0 dB
1136 aic3111_write(codec, (81), 0x80); //D7=1:ADC channel is powered up.
1139 /*configure register to creat a filter 20~3.5kHz*/
1141 aic3111_write(codec, (128*4 + 14), 0x7f);
1142 aic3111_write(codec, (128*4 + 15), 0x00);
1143 aic3111_write(codec, (128*4 + 16), 0xc0);
1144 aic3111_write(codec, (128*4 + 17), 0x18);
1145 aic3111_write(codec, (128*4 + 18), 0x00);
1147 aic3111_write(codec, (128*4 + 19), 0x00);
1148 aic3111_write(codec, (128*4 + 20), 0x3f);
1149 aic3111_write(codec, (128*4 + 21), 0x00);
1150 aic3111_write(codec, (128*4 + 22), 0x00);
1151 aic3111_write(codec, (128*4 + 23), 0x00);
1153 aic3111_write(codec, (128*4 + 24), 0x05);
1154 aic3111_write(codec, (128*4 + 25), 0xd2);
1155 aic3111_write(codec, (128*4 + 26), 0x05);
1156 aic3111_write(codec, (128*4 + 27), 0xd2);
1157 aic3111_write(codec, (128*4 + 28), 0x05);
1159 aic3111_write(codec, (128*4 + 29), 0xd2);
1160 aic3111_write(codec, (128*4 + 30), 0x53);
1161 aic3111_write(codec, (128*4 + 31), 0xff);
1162 aic3111_write(codec, (128*4 + 32), 0xc0);
1163 aic3111_write(codec, (128*4 + 33), 0xb5);
1166 aic3111_write(codec, (64), 0x00);
1167 aic3111_current_status |= AIC3110_IS_CAPTURE_ON;
1169 } else if ((on == POWER_STATE_OFF) &&
1170 (aic3111_current_status & AIC3110_IS_CAPTURE_ON)) {
1172 aic3111_write(codec, (61), 0x00);
1173 aic3111_write(codec, (128 + 47), 0x00); //MIC PGA AOL
1174 aic3111_write(codec, (128 + 48), 0x00);
1175 aic3111_write(codec, (128 + 50), 0x00);
1176 aic3111_write(codec, (81), 0x00);
1177 aic3111_write(codec, (82), 0x80);
1178 aic3111_write(codec, (83), 0x00); //ADC VOL
1179 aic3111_write(codec, (86), 0x00);
1181 aic3111_current_status &= ~AIC3110_IS_CAPTURE_ON;
1188 *----------------------------------------------------------------------------
1189 * Function : aic3111_powerdown
1190 * Purpose : This function is to power down codec.
1192 *----------------------------------------------------------------------------
1194 static void aic3111_powerdown (void)
1196 AIC_DBG ("CODEC::%s\n", __FUNCTION__);
1198 if (aic3111_current_status != AIC3110_IS_SHUTDOWN) {
1199 aic3111_soft_reset();//sai
1200 aic3111_current_status = AIC3110_IS_SHUTDOWN;
1205 *----------------------------------------------------------------------------
1206 * Function : aic3111_work
1207 * Purpose : This function is to respond to HPDET handle.
1209 *----------------------------------------------------------------------------
1211 static void aic3111_work (struct work_struct *work)
1213 AIC_DBG("Enter %s and line %d\n",__FUNCTION__,__LINE__);
1215 switch (aic3111_work_type) {
1216 case AIC3110_POWERDOWN_NULL:
1218 case AIC3110_POWERDOWN_PLAYBACK:
1219 aic3111_power_playback(POWER_STATE_OFF);
1221 case AIC3110_POWERDOWN_CAPTURE:
1222 aic3111_power_capture(POWER_STATE_OFF);
1224 case AIC3110_POWERDOWN_PLAYBACK_CAPTURE:
1225 aic3111_powerdown();//sai
1231 aic3111_work_type = AIC3110_POWERDOWN_NULL;
1235 *----------------------------------------------------------------------------
1236 * Function : aic3111_startup
1237 * Purpose : This function is to start up codec.
1239 *----------------------------------------------------------------------------
1241 static int aic3111_startup (struct snd_pcm_substream *substream,
1242 struct snd_soc_dai *dai)
1245 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1246 struct snd_soc_codec *codec = aic3111_codec;
1249 AIC_DBG ("CODEC::%s----substream->stream:%s \n", __FUNCTION__,
1250 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "PLAYBACK":"CAPTURE");
1252 cancel_delayed_work_sync(&delayed_work);
1254 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1256 aic3111_power_playback(POWER_STATE_ON);
1258 } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1260 aic3111_power_capture(POWER_STATE_ON);
1267 *----------------------------------------------------------------------------
1268 * Function : aic3111_startup
1269 * Purpose : This function is to shut down codec.
1271 *----------------------------------------------------------------------------
1273 static void aic3111_shutdown (struct snd_pcm_substream *substream,
1274 struct snd_soc_dai *dai)
1276 struct snd_soc_dai *codec_dai = dai;
1278 AIC_DBG ("CODEC::%s----substream->stream:%s \n", __FUNCTION__,
1279 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "PLAYBACK":"CAPTURE");
1281 if (!codec_dai->capture_active && !codec_dai->playback_active) {
1283 cancel_delayed_work_sync(&delayed_work);
1285 /* If codec is already shutdown, return */
1286 if (aic3111_current_status == AIC3110_IS_SHUTDOWN)
1289 AIC_DBG ("CODEC::Is going to power down aic3111\n");
1291 aic3111_work_type = AIC3110_POWERDOWN_PLAYBACK_CAPTURE;
1293 /* If codec is useless, queue work to close it */
1294 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1295 queue_delayed_work(aic3111_workq, &delayed_work,
1296 msecs_to_jiffies(1000));
1299 queue_delayed_work(aic3111_workq, &delayed_work,
1300 msecs_to_jiffies(3000));
1303 else if (codec_dai->capture_active && !codec_dai->playback_active) {
1305 cancel_delayed_work_sync(&delayed_work);
1307 aic3111_work_type = AIC3110_POWERDOWN_PLAYBACK;
1309 /* Turn off playback and keep record on */
1310 queue_delayed_work(aic3111_workq, &delayed_work,
1311 msecs_to_jiffies(1000));
1313 else if (!codec_dai->capture_active && codec_dai->playback_active) {
1315 cancel_delayed_work_sync(&delayed_work);
1317 aic3111_work_type = AIC3110_POWERDOWN_CAPTURE;
1319 /* Turn off record and keep playback on */
1320 queue_delayed_work(aic3111_workq, &delayed_work,
1321 msecs_to_jiffies(3000));
1326 *----------------------------------------------------------------------------
1327 * Function : aic3111_trigger
1328 * Purpose : This function is to respond to playback trigger.
1330 *----------------------------------------------------------------------------
1332 static int aic3111_trigger(struct snd_pcm_substream *substream,
1334 struct snd_soc_dai *dai)
1336 struct snd_soc_dai *codec_dai = dai;
1340 gpio_set_value(aic3111_spk_ctl_gpio, GPIO_LOW);
1344 AIC_DBG ("CODEC::%s----status = %d substream->stream:%s \n", __FUNCTION__, status,
1345 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "PLAYBACK":"CAPTURE");
1347 if (status == 1 || status == 0) {
1348 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1349 codec_dai->playback_active = status;
1351 codec_dai->capture_active = status;
1358 static struct snd_soc_dai_ops aic3111_dai_ops = {
1359 .hw_params = aic3111_hw_params,
1360 .digital_mute = aic3111_mute,
1361 .set_sysclk = aic3111_set_dai_sysclk,
1362 .set_fmt = aic3111_set_dai_fmt,
1363 .startup = aic3111_startup,
1364 .shutdown = aic3111_shutdown,
1365 .trigger = aic3111_trigger,
1368 static struct snd_soc_dai_driver aic3111_dai[] = {
1370 .name = "AIC3111 HiFi",
1372 .stream_name = "HiFi Playback",
1375 .rates = AIC3111_RATES,
1376 .formats = AIC3111_FORMATS,
1379 .stream_name = "HiFi Capture",
1382 .rates = AIC3111_RATES,
1383 .formats = AIC3111_FORMATS,
1385 .ops = &aic3111_dai_ops,
1389 struct delayed_work aic3111_speaker_delayed_work;
1392 static void aic3111_speaker_delayed_work_func(struct work_struct *work)
1394 struct snd_soc_codec *codec = aic3111_codec;
1396 if (aic3111_current_status & AIC3110_IS_PLAYBACK_ON){
1399 //aic3111_write(codec, (128 + 32), 0xc6);
1400 //printk("reg 128+32 = %x\n"aic3111_read(codec, (128 + 32)));
1402 //gpio_set_value(aic3111_spk_ctl_gpio, GPIO_LOW);
1403 aic3111_power_speaker(POWER_STATE_OFF);
1404 gpio_set_value(aic3111_spk_ctl_gpio, GPIO_HIGH);
1405 //aic3111_power_headphone(POWER_STATE_ON);
1406 //aic3111_write(codec, (128 + 35), 0x88);
1407 printk("now hp sound\n");
1410 //aic3111_power_speaker(POWER_STATE_ON);
1413 //aic3111_power_headphone(POWER_STATE_OFF);
1414 gpio_set_value(aic3111_spk_ctl_gpio, GPIO_LOW);
1415 aic3111_power_speaker(POWER_STATE_ON);
1416 aic3111_write(codec, (128 + 35), 0x44);
1417 aic3111_write(codec, (63), 0xfc);
1418 printk("now spk sound\n");
1422 //printk("----------------------------mma7660_work_func------------------------\n");
1426 /**for check hp or spk****/
1427 static int speaker_timer(unsigned long _data)
1429 struct speaker_data *spk = (struct speaker_data *)_data;
1432 if (gpio_get_value(aic3111_hp_det_gpio) == 0) {
1435 //printk("hp now\n");
1436 if(old_status != new_status)
1438 old_status = new_status;
1439 // printk("new_status = %d,old_status = %d\n",new_status,old_status);
1440 old_status = new_status;
1442 schedule_delayed_work(&aic3111_speaker_delayed_work,msecs_to_jiffies(30));
1444 //printk("HS RUN!!!!!!!!!!\n");
1448 if (gpio_get_value(aic3111_hp_det_gpio) == 1) {
1451 //printk("speak now\n");
1452 if(old_status != new_status)
1454 old_status = new_status;
1455 printk("new_status = %d,old_status = %d\n",new_status,old_status);
1456 old_status = new_status;
1458 schedule_delayed_work(&aic3111_speaker_delayed_work,msecs_to_jiffies(30));
1460 //printk("HS RUN!!!!!!!!!!\n");
1464 mod_timer(&spk->timer, jiffies + msecs_to_jiffies(200));
1469 *----------------------------------------------------------------------------
1470 * Function : aic3111_probe
1471 * Purpose : This is first driver function called by the SoC core driver.
1473 *----------------------------------------------------------------------------
1475 static int aic3111_probe (struct snd_soc_codec *codec)
1477 int ret = 0;//, flags, hp_det_irq;
1479 codec->hw_write = (hw_write_t) i2c_master_send;
1480 codec->control_data = aic3111_i2c;
1481 aic3111_codec = codec;
1484 gpio_set_value(aic3111_hp_det_gpio,1);
1485 struct speaker_data *spk;
1487 spk = kzalloc(sizeof(struct speaker_data), GFP_KERNEL);
1489 printk("Allocate Memory Failed!\n");
1491 //goto exit_gpio_free;
1494 setup_timer(&spk->timer, speaker_timer, (unsigned long)spk);
1495 mod_timer(&spk->timer, jiffies + JACK_DET_ADLOOP);
1496 INIT_DELAYED_WORK(&aic3111_speaker_delayed_work, aic3111_speaker_delayed_work_func);
1498 /*********************/
1499 //pio_set_value(aic3111_spk_ctl_gpio, GPIO_LOW);
1500 //aic3111_power_speaker(POWER_STATE_OFF);
1501 //aic3111_power_headphone(POWER_STATE_ON);
1504 aic3111_workq = create_freezable_workqueue("aic3111");
1505 if (aic3111_workq == NULL) {
1509 /* INIT_DELAYED_WORK (&aic3111_hpdet_work, aic3111_hpdet_work_handle);
1510 if (gpio_request (HP_DET_PIN, "hp_det")) {
1511 gpio_free (HP_DET_PIN);
1512 printk ("CODEC::tlv3110 hp det pin request error\n");
1515 gpio_direction_input (HP_DET_PIN);
1516 gpio_pull_updown (HP_DET_PIN, PullDisable);
1517 hp_det_irq = gpio_to_irq (HP_DET_PIN);
1518 isHSin = gpio_get_value (HP_DET_PIN);
1520 flags = isHSin ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING;
1521 ret = request_irq (hp_det_irq, aic3111_hpdet_isr, flags, "hpdet", codec);
1523 printk ("CODEC::request hp_det_irq error\n");
1527 /* Just Reset codec */
1528 aic3111_soft_reset();
1529 gpio_set_value(aic3111_spk_ctl_gpio, GPIO_LOW);
1531 aic3111_write (aic3111_codec, (68), 0x01); //disable DRC
1532 aic3111_write (aic3111_codec, (128 + 31), 0xc4);
1533 aic3111_write (aic3111_codec, (128 + 36), 0x28); //Left Analog Vol to HPL
1534 aic3111_write (aic3111_codec, (128 + 37), 0x28); //Right Analog Vol to HPL
1535 aic3111_write (aic3111_codec, (128 + 40), 0x4f); //HPL driver PGA
1536 aic3111_write (aic3111_codec, (128 + 41), 0x4f); //HPR driver PGA
1538 aic3111_set_bias_level (codec, SND_SOC_BIAS_STANDBY);
1544 *----------------------------------------------------------------------------
1545 * Function : aic3111_remove
1546 * Purpose : to remove aic3111 soc device
1548 *----------------------------------------------------------------------------
1550 static int aic3111_remove (struct snd_soc_codec *codec)
1552 AIC_DBG ("CODEC::%s\n", __FUNCTION__);
1554 /* Disable HPDET irq */
1555 //disable_irq_nosync (HP_DET_PIN);
1557 /* power down chip */
1558 aic3111_set_bias_level (codec, SND_SOC_BIAS_OFF);
1564 *----------------------------------------------------------------------------
1565 * Function : aic3111_suspend
1566 * Purpose : This function is to suspend the AIC3111 driver.
1568 *----------------------------------------------------------------------------
1570 static int aic3111_suspend (struct snd_soc_codec *codec)
1573 AIC_DBG ("CODEC::%s\n", __FUNCTION__);
1575 aic3111_set_bias_level (codec, SND_SOC_BIAS_STANDBY);
1577 aic3111_soft_reset();//sai
1583 *----------------------------------------------------------------------------
1584 * Function : aic3111_resume
1585 * Purpose : This function is to resume the AIC3111 driver
1587 *----------------------------------------------------------------------------
1589 static int aic3111_resume (struct snd_soc_codec *codec)
1591 //isHSin = gpio_get_value(HP_DET_PIN);
1592 aic3111_set_bias_level (codec, SND_SOC_BIAS_STANDBY);
1593 //aic3111_set_bias_level(codec, codec->suspend_bias_level);
1599 *----------------------------------------------------------------------------
1600 * @struct snd_soc_codec_device |
1601 * This structure is soc audio codec device sturecute which pointer
1602 * to basic functions aic3111_probe(), aic3111_remove(),
1603 * aic3111_suspend() and aic3111_resume()
1604 *----------------------------------------------------------------------------
1606 static struct snd_soc_codec_driver soc_codec_dev_aic3111 = {
1607 .probe = aic3111_probe,
1608 .remove = aic3111_remove,
1609 .suspend = aic3111_suspend,
1610 .resume = aic3111_resume,
1611 .set_bias_level = aic3111_set_bias_level,
1612 .reg_cache_size = ARRAY_SIZE(aic31xx_reg),
1613 .reg_word_size = sizeof(u16),
1614 .reg_cache_default = aic31xx_reg,
1615 .reg_cache_step = 1,
1618 static const struct i2c_device_id tlv320aic3111_i2c_id[] = {
1622 MODULE_DEVICE_TABLE(i2c, tlv320aic3111_i2c_id);
1627 compatible = "aic3111";
1629 spk-ctl-gpio = <&gpio6 GPIO_B5 GPIO_ACTIVE_HIGH>;
1630 hp-det-pio = <&gpio6 GPIO_B6 GPIO_ACTIVE_HIGH>;
1633 static int tlv320aic3111_i2c_probe(struct i2c_client *i2c,
1634 const struct i2c_device_id *id)
1636 struct aic3111_priv *aic3111;
1639 aic3111 = kzalloc(sizeof(struct aic3111_priv), GFP_KERNEL);
1640 if (NULL == aic3111)
1646 aic3111_spk_ctl_gpio= of_get_named_gpio_flags(i2c->dev.of_node, "spk-ctl-gpio", 0, NULL);
1647 if (aic3111_spk_ctl_gpio < 0) {
1648 printk("%s() Can not read property spk-ctl-gpio\n", __FUNCTION__);
1649 aic3111_spk_ctl_gpio = INVALID_GPIO;
1652 aic3111_hp_det_gpio = of_get_named_gpio_flags(i2c->dev.of_node, "hp-det-pio", 0, NULL);
1653 if (aic3111_hp_det_gpio < 0) {
1654 printk("%s() Can not read property hp-det-pio\n", __FUNCTION__);
1655 aic3111_hp_det_gpio = INVALID_GPIO;
1657 #endif //#ifdef CONFIG_OF
1659 i2c_set_clientdata(i2c, aic3111);
1661 aic3111_privdata = aic3111;
1663 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_aic3111,
1664 aic3111_dai, ARRAY_SIZE(aic3111_dai));
1671 static int tlv320aic3111_i2c_remove(struct i2c_client *client)
1673 snd_soc_unregister_codec(&client->dev);
1674 kfree(i2c_get_clientdata(client));
1678 struct i2c_driver tlv320aic3111_i2c_driver = {
1681 .owner = THIS_MODULE,
1683 .probe = tlv320aic3111_i2c_probe,
1684 .remove = tlv320aic3111_i2c_remove,
1685 .id_table = tlv320aic3111_i2c_id,
1688 static int __init tlv320aic3111_init (void)
1690 return i2c_add_driver(&tlv320aic3111_i2c_driver);
1693 static void __exit tlv320aic3111_exit (void)
1695 i2c_del_driver(&tlv320aic3111_i2c_driver);
1698 module_init (tlv320aic3111_init);
1699 module_exit (tlv320aic3111_exit);
1701 MODULE_DESCRIPTION (" ASoC TLV320AIC3111 codec driver ");
1702 MODULE_AUTHOR (" Jaz B John <jazbjohn@mistralsolutions.com> ");
1703 MODULE_LICENSE ("GPL");