2 * linux/sound/soc/codecs/tlv320aic3111.c
5 * Copyright (C) 2010 Texas Instruments, Inc.
7 * This package is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
12 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
13 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 * Rev 0.1 ASoC driver support Mistral 14-04-2010
19 * Rev 0.2 Updated based Review Comments Mistral 29-06-2010
21 * Rev 0.3 Updated for Codec Family Compatibility 12-07-2010
25 *****************************************************************************
27 *****************************************************************************
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
34 #include <linux/i2c.h>
35 #include <linux/platform_device.h>
36 #include <linux/cdev.h>
38 #include <linux/proc_fs.h>
39 #include <linux/seq_file.h>
41 #include <sound/core.h>
42 #include <sound/pcm.h>
43 #include <sound/pcm_params.h>
44 #include <sound/soc.h>
45 #include <sound/soc-dapm.h>
46 #include <sound/initval.h>
48 #include <mach/gpio.h>
49 #include "tlv320aic3111.h"
53 #define AIC_DBG(x...) printk(KERN_INFO x)
55 #define AIC_DBG(x...) do { } while (0)
58 #define HP_DET_PIN RK29_PIN6_PA0
59 //#define AIC3111_DEBUG
61 #define AIC3110_IS_SHUTDOWN 0
62 #define AIC3110_IS_CAPTURE_ON 1
63 #define AIC3110_IS_PLAYBACK_ON 2
64 #define AIC3110_IS_INITPOWER_ON 4
67 #define AIC3110_POWERDOWN_NULL 0
68 #define AIC3110_POWERDOWN_PLAYBACK 1
69 #define AIC3110_POWERDOWN_CAPTURE 2
70 #define AIC3110_POWERDOWN_PLAYBACK_CAPTURE 3
71 #define JACK_DET_ADLOOP msecs_to_jiffies(200)
73 //#define AIC3111_DEBUG
76 static int aic3111_power_speaker (bool on);
78 struct timer_list timer;
86 POWER_STATE_SW_HP = 0,
90 static void aic3111_work(struct work_struct *work);
92 static struct workqueue_struct *aic3111_workq;
93 static DECLARE_DELAYED_WORK(delayed_work, aic3111_work);
94 static int aic3111_current_status = AIC3110_IS_SHUTDOWN, aic3111_work_type = AIC3110_POWERDOWN_NULL;
95 static bool isHSin = true, isSetHW = false;
98 *****************************************************************************
100 *****************************************************************************
102 /* Used to maintain the Register Access control*/
103 static u8 aic3111_reg_ctl;
105 static struct snd_soc_codec *aic3111_codec;
106 struct aic3111_priv *aic3111_privdata;
107 struct i2c_client *aic3111_i2c;
109 /* add a timer for checkout HP or SPK*/
110 static struct timer_list aic3111_timer;
112 /*Used to delay work hpdet switch irq handle*/
113 struct delayed_work aic3111_hpdet_work;
115 #ifdef CONFIG_MINI_DSP
116 extern int aic3111_minidsp_program (struct snd_soc_codec *codec);
117 extern void aic3111_add_minidsp_controls (struct snd_soc_codec *codec);
121 * AIC3111 register cache
122 * We are caching the registers here.
123 * NOTE: In AIC3111, there are 61 pages of 128 registers supported.
124 * The following table contains the page0, page1 and page2 registers values.
127 #ifdef AIC3111_CODEC_SUPPORT
128 static const u8 aic31xx_reg[AIC31xx_CACHEREGNUM] = {
129 /* Page 0 Registers */
130 /* 0 */ 0x00, 0x00, 0x12, 0x00, 0x00, 0x11, 0x04, 0x00, 0x00, 0x00, 0x00,
131 0x01, 0x01, 0x00, 0x80, 0x80,
132 /* 10 */ 0x08, 0x00, 0x01, 0x01, 0x80, 0x80, 0x04, 0x00, 0x01, 0x00, 0x00,
133 0x00, 0x01, 0x00, 0x00, 0x00,
134 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
135 0x00, 0x00, 0x00, 0x00, 0x00,
136 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x55, 0x00, 0x00,
137 0x00, 0x01, 0x01, 0x00, 0x14,
138 /* 40 */ 0x0c, 0x00, 0x00, 0x00, 0x6f, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
139 0xee, 0x10, 0xd8, 0x7e, 0xe3,
140 /* 50 */ 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00,
141 0x00, 0x00, 0x00, 0x00, 0x00,
142 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
143 0x00, 0x00, 0x00, 0x00, 0x00,
144 /* 70 */ 0x00, 0x00, 0x10, 0x32, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
145 0x00, 0x00, 0x00, 0x12, 0x02,
146 /* Page 1 Registers */
147 /* 0 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
148 0x00, 0x00, 0x00, 0x00, 0x00,
149 /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
150 0x00, 0x00, 0x00, 0x00, 0x00,
151 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x00,
153 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
154 0x80, 0x80, 0x00, 0x00, 0x00,
155 /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
156 0x00, 0x00, 0x00, 0x00, 0x00,
157 /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
158 0x00, 0x00, 0x00, 0x00, 0x00,
159 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
160 0x00, 0x00, 0x00, 0x00, 0x00,
161 /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
162 0x00, 0x00, 0x00, 0x00, 0x00,
165 #elif defined(AIC3110_CODEC_SUPPORT)
166 /**************** AIC3110 REG CACHE ******************/
167 static const u8 aic31xx_reg[AIC31xx_CACHEREGNUM] = {
168 /* Page 0 Registers */
169 0x00, 0x00, 0x01, 0x56, 0x00, 0x11, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x80,
170 0x08, 0x00, 0x01, 0x01, 0x80, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
171 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
172 0x00, 0x00, 0x00, 0x02, 0x32, 0x12, 0x03, 0x02, 0x02, 0x11, 0x10, 0x00, 0x01, 0x04, 0x00, 0x14,
173 0x0c, 0x00, 0x00, 0x00, 0x0f, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0xee, 0x10, 0xd8, 0x7e, 0xe3,
174 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
175 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
176 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
177 /* Page 1 Registers */
178 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
179 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
180 0x06, 0x3e, 0x00, 0x00, 0x7f, 0x7f, 0x7f, 0x7f, 0x02, 0x02, 0x00, 0x00, 0x20, 0x86, 0x00, 0x80,
181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
186 }; /**************************** End of AIC3110 REG CAHE ******************/
188 #elif defined(AIC3100_CODEC_SUPPORT)
189 /******************************* AIC3100 REG CACHE ***********************/
190 static const u8 aic31xx_reg[AIC31xx_CACHEREGNUM] = {
191 /* Page 0 Registers */
192 /* 0 */ 0x00, 0x00, 0x12, 0x00, 0x00, 0x11, 0x04, 0x00, 0x00, 0x00, 0x00,
193 0x01, 0x01, 0x00, 0x80, 0x00,
194 /* 10 */ 0x00, 0x00, 0x01, 0x01, 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
195 0x00, 0x01, 0x00, 0x00, 0x00,
196 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
197 0x00, 0x00, 0x00, 0x00, 0x00,
198 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x55, 0x00, 0x00,
199 0x00, 0x01, 0x01, 0x00, 0x14,
200 /* 40 */ 0x0c, 0x00, 0x00, 0x00, 0x6f, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
201 0xee, 0x10, 0xd8, 0x7e, 0xe3,
202 /* 50 */ 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00,
203 0x00, 0x00, 0x00, 0x00, 0x00,
204 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
205 0x00, 0x00, 0x00, 0x00, 0x00,
206 /* 70 */ 0x00, 0x00, 0x10, 0x32, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
207 0x00, 0x00, 0x00, 0x12, 0x02,
208 /* Page 1 Registers */
209 /* 0 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
210 0x00, 0x00, 0x00, 0x00, 0x00,
211 /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
212 0x00, 0x00, 0x00, 0x00, 0x00,
213 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
214 0x00, 0x00, 0x00, 0x00, 0x00,
215 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
216 0x80, 0x80, 0x00, 0x00, 0x00,
217 /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
218 0x00, 0x00, 0x00, 0x00, 0x00,
219 /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
220 0x00, 0x00, 0x00, 0x00, 0x00,
221 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
222 0x00, 0x00, 0x00, 0x00, 0x00,
223 /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
224 0x00, 0x00, 0x00, 0x00, 0x00,
225 }; /**************************** End of AIC3100 REG CACHE ******************/
227 #else /*#ifdef AIC3120_CODEC_SUPPORT */
228 static const u8 aic31xx_reg[AIC31xx_CACHEREGNUM] = {
229 /* Page 0 Registers */
230 /* 0 */ 0x00, 0x00, 0x12, 0x00, 0x00, 0x11, 0x04, 0x00, 0x00, 0x00, 0x00,
231 0x01, 0x01, 0x00, 0x80, 0x80,
232 /* 10 */ 0x08, 0x00, 0x01, 0x01, 0x80, 0x80, 0x04, 0x00, 0x01, 0x00, 0x00,
233 0x00, 0x01, 0x00, 0x00, 0x00,
234 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
235 0x00, 0x00, 0x00, 0x00, 0x00,
236 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x55, 0x55, 0x00, 0x00,
237 0x00, 0x01, 0x01, 0x00, 0x14,
238 /* 40 */ 0x0c, 0x00, 0x00, 0x00, 0x6f, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
239 0xee, 0x10, 0xd8, 0x7e, 0xe3,
240 /* 50 */ 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00,
241 0x00, 0x00, 0x00, 0x00, 0x00,
242 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
243 0x00, 0x00, 0x00, 0x00, 0x00,
244 /* 70 */ 0x00, 0x00, 0x10, 0x32, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
245 0x00, 0x00, 0x00, 0x12, 0x02,
246 /* Page 1 Registers */
247 /* 0 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
248 0x00, 0x00, 0x00, 0x00, 0x00,
249 /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
250 0x00, 0x00, 0x00, 0x00, 0x00,
251 /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
252 0x00, 0x00, 0x00, 0x00, 0x00,
253 /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
254 0x80, 0x80, 0x00, 0x00, 0x00,
255 /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
256 0x00, 0x00, 0x00, 0x00, 0x00,
257 /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
258 0x00, 0x00, 0x00, 0x00, 0x00,
259 /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
260 0x00, 0x00, 0x00, 0x00, 0x00,
261 /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
262 0x00, 0x00, 0x00, 0x00, 0x00,
268 *----------------------------------------------------------------------------
269 * Function : aic3111_change_page
270 * Purpose : This function is to switch between page 0 and page 1.
272 *----------------------------------------------------------------------------
274 static int aic3111_change_page (struct snd_soc_codec *codec, u8 new_page)
276 struct aic3111_priv *aic3111 = aic3111_privdata;
279 if (new_page == 2 || new_page > 8) {
280 printk("ERROR::codec do not have page %d !!!!!!\n", new_page);
286 aic3111->page_no = new_page;
288 if (codec->hw_write (codec->control_data, data, 2) != 2)
290 printk ("Error in changing page to %d \n", new_page);
298 *----------------------------------------------------------------------------
299 * Function : aic3111_write_reg_cache
300 * Purpose : This function is to write aic3111 register cache
302 *----------------------------------------------------------------------------
304 static inline void aic3111_write_reg_cache (struct snd_soc_codec *codec, u16 reg, u8 value)
306 u8 *cache = codec->reg_cache;
308 if (reg >= AIC31xx_CACHEREGNUM)
317 *----------------------------------------------------------------------------
318 * Function : aic3111_read
319 * Purpose : This function is to read the aic3111 register space.
321 *----------------------------------------------------------------------------
323 static unsigned int aic3111_read (struct snd_soc_codec *codec, unsigned int reg)
325 struct aic3111_priv *aic3111 = aic3111_privdata;
329 if (page == 2 || page > 8) {
330 printk("aic3111_read::Error page, there's not page %d in codec tlv320aic3111 !!!\n", page);
336 if (aic3111->page_no != page)
338 aic3111_change_page (codec, page);
341 i2c_master_send (codec->control_data, (char *) ®, 1);
342 i2c_master_recv (codec->control_data, &value, 1);
348 *----------------------------------------------------------------------------
349 * Function : aic3111_write
350 * Purpose : This function is to write to the aic3111 register space.
352 *----------------------------------------------------------------------------
354 static int aic3111_write (struct snd_soc_codec *codec, unsigned int reg, unsigned int value)
356 struct aic3111_priv *aic3111 = aic3111_privdata;
359 //printk("enter %s!!!!!!\n",__FUNCTION__);
360 //printk("RK29_PIN6_PB6 =%d!!!!!!\n",gpio_get_value(RK29_PIN6_PB6));
362 data[AIC3111_REG_OFFSET_INDEX] = reg % 128;
364 if (page == 2 || page > 9) {
365 printk("aic3111_write::Error page, there's not page %d in codec tlv320aic3111 !!!\n", page);
369 if (aic3111->page_no != page)
371 aic3111_change_page (codec, page);
375 * D15..D8 aic3111 register offset
376 * D7...D0 register data
378 data[AIC3111_REG_DATA_INDEX] = value & AIC3111_8BITS_MASK;
379 #if defined(EN_REG_CACHE)
380 if ((page == 0) || (page == 1))
382 aic3111_write_reg_cache (codec, reg, value);
385 if (codec->hw_write (codec->control_data, data, 2) != 2)
387 printk ("Error in i2c write\n");
394 static int aic3111_print_register_cache (struct platform_device *pdev)
396 struct snd_soc_codec *codec = aic3111_codec;
397 u8 *cache = codec->reg_cache;
400 printk ("\n========3110 reg========\n");
401 for (reg = 0; reg < codec->reg_size; reg++)
403 if (reg == 0) printk ("Page 0\n");
404 if (reg == 128) printk ("\nPage 1\n");
405 if (reg%16 == 0 && reg != 0 && reg != 128) printk ("\n");
406 printk("0x%02x, ",aic3111_read(codec,reg));
408 printk ("\n========3110 cache========\n");
409 for (reg = 0; reg < codec->reg_size; reg++)
411 if (reg == 0) printk ("Page 0\n");
412 if (reg == 128) printk ("\nPage 1\n");
413 if (reg%16 == 0 && reg != 0 && reg != 128) printk ("\n");
414 printk ("0x%02x, ",cache[reg]);
416 printk ("\n==========================\n");
420 static void aic3111_soft_reset (void)
422 struct snd_soc_codec *codec = aic3111_codec;
424 AIC_DBG("CODEC::%s\n",__FUNCTION__);
426 //aic3111_write (codec, 1, 0x01);
427 aic3111_write (codec, 63, 0x00);
428 gpio_set_value(RK29_PIN6_PB5, GPIO_LOW);
430 aic3111_write (aic3111_codec, (68), 0x01); //disable DRC
431 aic3111_write (aic3111_codec, (128 + 31), 0xc4);
432 aic3111_write (aic3111_codec, (128 + 36), 0x28); //Left Analog Vol to HPL
433 aic3111_write (aic3111_codec, (128 + 37), 0x28); //Right Analog Vol to HPL
434 aic3111_write (aic3111_codec, (128 + 40), 0x4f); //HPL driver PGA
435 aic3111_write (aic3111_codec, (128 + 41), 0x4f); //HPR driver PGA
436 aic3111_power_speaker(POWER_STATE_OFF);
438 aic3111_write (codec, 1, 0x00);
440 memcpy(codec->reg_cache, aic31xx_reg,
441 sizeof(aic31xx_reg));
449 *----------------------------------------------------------------------------
450 * Function : aic3111_set_bias_level
451 * Purpose : This function is to get triggered when dapm events occurs.
453 *----------------------------------------------------------------------------
455 static int aic3111_set_bias_level(struct snd_soc_codec *codec,
456 enum snd_soc_bias_level level)
458 struct aic3111_priv *aic3111 = aic3111_privdata;
464 AIC_DBG ("CODEC::%s>>>>>>level:%d>>>>master:%d\n", __FUNCTION__, level, aic3111->master);
468 case SND_SOC_BIAS_ON:
469 /* all power is driven by DAPM system */
473 value = aic3111_read(codec, CLK_REG_2);
474 aic3111_write(codec, CLK_REG_2, (value | ENABLE_PLL));
476 /* Switch on NDAC Divider */
477 value = aic3111_read(codec, NDAC_CLK_REG);
478 aic3111_write(codec, NDAC_CLK_REG, value | ENABLE_NDAC);
480 /* Switch on MDAC Divider */
481 value = aic3111_read(codec, MDAC_CLK_REG);
482 aic3111_write(codec, MDAC_CLK_REG, value | ENABLE_MDAC);
484 /* Switch on NADC Divider */
485 value = aic3111_read(codec, NADC_CLK_REG);
486 aic3111_write(codec, NADC_CLK_REG, value | ENABLE_MDAC);
488 /* Switch on MADC Divider */
489 value = aic3111_read(codec, MADC_CLK_REG);
490 aic3111_write(codec, MADC_CLK_REG, value | ENABLE_MDAC);
492 /* Switch on BCLK_N Divider */
493 value = aic3111_read(codec, BCLK_N_VAL);
494 aic3111_write(codec, BCLK_N_VAL, value | ENABLE_BCLK);
497 value = aic3111_read(codec, CLK_REG_2);
498 aic3111_write(codec, CLK_REG_2, (value | ENABLE_PLL));
500 /* Switch on NDAC Divider */
501 value = aic3111_read(codec, NDAC_CLK_REG);
502 aic3111_write(codec, NDAC_CLK_REG, value | ENABLE_NDAC);
504 /* Switch on MDAC Divider */
505 value = aic3111_read(codec, MDAC_CLK_REG);
506 aic3111_write(codec, MDAC_CLK_REG, value | ENABLE_MDAC);
508 /* Switch on NADC Divider */
509 value = aic3111_read(codec, NADC_CLK_REG);
510 aic3111_write(codec, NADC_CLK_REG, value | ENABLE_MDAC);
512 /* Switch on MADC Divider */
513 value = aic3111_read(codec, MADC_CLK_REG);
514 aic3111_write(codec, MADC_CLK_REG, value | ENABLE_MDAC);
516 /* Switch on BCLK_N Divider */
517 value = aic3111_read(codec, BCLK_N_VAL);
518 aic3111_write(codec, BCLK_N_VAL, value | ENABLE_BCLK);
523 case SND_SOC_BIAS_PREPARE:
526 /* Off, with power */
527 case SND_SOC_BIAS_STANDBY:
529 * all power is driven by DAPM system,
530 * so output power is safe if bypass was set
535 value = aic3111_read(codec, CLK_REG_2);
536 aic3111_write(codec, CLK_REG_2, (value & ~ENABLE_PLL));
538 /* Switch off NDAC Divider */
539 value = aic3111_read(codec, NDAC_CLK_REG);
540 aic3111_write(codec, NDAC_CLK_REG, value & ~ENABLE_NDAC);
542 /* Switch off MDAC Divider */
543 value = aic3111_read(codec, MDAC_CLK_REG);
544 aic3111_write(codec, MDAC_CLK_REG, value & ~ENABLE_MDAC);
546 /* Switch off NADC Divider */
547 value = aic3111_read(codec, NADC_CLK_REG);
548 aic3111_write(codec, NADC_CLK_REG, value & ~ENABLE_NDAC);
550 /* Switch off MADC Divider */
551 value = aic3111_read(codec, MADC_CLK_REG);
552 aic3111_write(codec, MADC_CLK_REG, value & ~ENABLE_MDAC);
553 value = aic3111_read(codec, BCLK_N_VAL);
555 /* Switch off BCLK_N Divider */
556 aic3111_write(codec, BCLK_N_VAL, value & ~ENABLE_BCLK);
560 /* Off, without power */
561 case SND_SOC_BIAS_OFF:
562 /* force all power off */
565 codec->dapm.bias_level = level;
569 /* the structure contains the different values for mclk */
570 static const struct aic3111_rate_divs aic3111_divs[] = {
572 * mclk, rate, p_val, pll_j, pll_d, dosr, ndac, mdac, aosr, nadc, madc, blck_N,
573 * codec_speficic_initializations
576 {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
577 //{12288000, 8000, 1, 7, 8643, 768, 5, 3, 128, 5, 18, 24},
578 {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
580 {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
581 {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
583 {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
584 {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
586 {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
587 {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
589 {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
590 {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
592 {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
593 {11289600, 44100, 1, 8, 0, 128, 4, 4, 128, 4, 4, 4},
594 {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
596 {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
597 {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
599 {12000000, 96000, 1, 8, 1920, 64, 2, 8, 64, 2, 8, 2},
600 {24000000, 96000, 2, 8, 1920, 64, 4, 4, 64, 8, 2, 2},
602 {12000000, 192000, 1, 8, 1920, 32, 2, 8, 32, 2, 8, 1},
603 {24000000, 192000, 2, 8, 1920, 32, 4, 4, 32, 4, 4, 1},
607 *----------------------------------------------------------------------------
608 * Function : aic3111_get_divs
609 * Purpose : This function is to get required divisor from the "aic3111_divs"
612 *----------------------------------------------------------------------------
614 static inline int aic3111_get_divs (int mclk, int rate)
618 AIC_DBG("Enter::%s\n",__FUNCTION__);
620 for (i = 0; i < ARRAY_SIZE (aic3111_divs); i++)
622 if ((aic3111_divs[i].rate == rate) && (aic3111_divs[i].mclk == mclk))
628 printk ("Master clock and sample rate is not supported\n");
633 *----------------------------------------------------------------------------
634 * Function : aic3111_hw_params
635 * Purpose : This function is to set the hardware parameters for AIC3111.
636 * The functions set the sample rate and audio serial data word
639 *----------------------------------------------------------------------------
641 static int aic3111_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params,
642 struct snd_soc_dai *codec_dai)
644 struct snd_soc_codec *codec = aic3111_codec;
645 struct aic3111_priv *aic3111 = aic3111_privdata;
652 AIC_DBG("CODEC::%s\n", __FUNCTION__);
654 aic3111_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
656 i = aic3111_get_divs(aic3111->sysclk, params_rate (params));
659 printk ("sampling rate not supported\n");
663 /* We will fix R value to 1 and will make P & J=K.D as varialble */
665 /* Setting P & R values */
666 aic3111_write(codec, CLK_REG_2, ((aic3111_divs[i].p_val << 4) | 0x01));
669 aic3111_write(codec, CLK_REG_3, aic3111_divs[i].pll_j);
671 /* MSB & LSB for D value */
672 aic3111_write(codec, CLK_REG_4, (aic3111_divs[i].pll_d >> 8));
673 aic3111_write(codec, CLK_REG_5, (aic3111_divs[i].pll_d & AIC3111_8BITS_MASK));
675 /* NDAC divider value */
676 aic3111_write(codec, NDAC_CLK_REG, aic3111_divs[i].ndac);
678 /* MDAC divider value */
679 aic3111_write(codec, MDAC_CLK_REG, aic3111_divs[i].mdac);
681 /* DOSR MSB & LSB values */
682 aic3111_write(codec, DAC_OSR_MSB, aic3111_divs[i].dosr >> 8);
683 aic3111_write(codec, DAC_OSR_LSB, aic3111_divs[i].dosr & AIC3111_8BITS_MASK);
685 /* NADC divider value */
686 aic3111_write(codec, NADC_CLK_REG, aic3111_divs[i].nadc);
688 /* MADC divider value */
689 aic3111_write(codec, MADC_CLK_REG, aic3111_divs[i].madc);
692 aic3111_write(codec, ADC_OSR_REG, aic3111_divs[i].aosr);
695 aic3111_write(codec, BCLK_N_VAL, aic3111_divs[i].blck_N);
697 aic3111_set_bias_level(codec, SND_SOC_BIAS_ON);
699 data = aic3111_read(codec, INTERFACE_SET_REG_1);
701 data = data & ~(3 << 4);
703 switch (params_format (params)) {
704 case SNDRV_PCM_FORMAT_S16_LE:
706 case SNDRV_PCM_FORMAT_S20_3LE:
707 data |= (AIC3111_WORD_LEN_20BITS << DATA_LEN_SHIFT);
709 case SNDRV_PCM_FORMAT_S24_LE:
710 data |= (AIC3111_WORD_LEN_24BITS << DATA_LEN_SHIFT);
712 case SNDRV_PCM_FORMAT_S32_LE:
713 data |= (AIC3111_WORD_LEN_32BITS << DATA_LEN_SHIFT);
717 aic3111_write(codec, INTERFACE_SET_REG_1, data);
723 *----------------------------------------------------------------------------
724 * Function : aic3111_mute
725 * Purpose : This function is to mute or unmute the left and right DAC
727 *----------------------------------------------------------------------------
729 static int aic3111_mute (struct snd_soc_dai *codec_dai, int mute)
731 struct snd_soc_codec *codec = codec_dai->codec;
734 AIC_DBG ("CODEC::%s>>>>mute:%d\n", __FUNCTION__, mute);
736 dac_reg = aic3111_read (codec, DAC_MUTE_CTRL_REG) & ~MUTE_ON;
738 ;//aic3111_write (codec, DAC_MUTE_CTRL_REG, dac_reg | MUTE_ON);
740 //aic3111_write (codec, DAC_MUTE_CTRL_REG, dac_reg);
748 *----------------------------------------------------------------------------
749 * Function : aic3111_set_dai_sysclk
750 * Purpose : This function is to set the DAI system clock
752 *----------------------------------------------------------------------------
754 static int aic3111_set_dai_sysclk (struct snd_soc_dai *codec_dai,
755 int clk_id, unsigned int freq, int dir)
757 struct aic3111_priv *aic3111 = aic3111_privdata;
762 AIC_DBG("Enter %s and line %d\n",__FUNCTION__,__LINE__);
765 case AIC3111_FREQ_11289600:
766 case AIC3111_FREQ_12000000:
767 case AIC3111_FREQ_24000000:
768 aic3111->sysclk = freq;
772 printk ("Invalid frequency to set DAI system clock\n");
777 *----------------------------------------------------------------------------
778 * Function : aic3111_set_dai_fmt
779 * Purpose : This function is to set the DAI format
781 *----------------------------------------------------------------------------
783 static int aic3111_set_dai_fmt (struct snd_soc_dai *codec_dai, unsigned int fmt)
785 struct snd_soc_codec *codec = codec_dai->codec;
786 struct aic3111_priv *aic3111 = aic3111_privdata;
792 AIC_DBG("Enter %s and line %d\n",__FUNCTION__,__LINE__);
794 iface_reg = aic3111_read (codec, INTERFACE_SET_REG_1);
795 iface_reg = iface_reg & ~(3 << 6 | 3 << 2); //set I2S mode BCLK and WCLK is input
797 /* set master/slave audio interface */
798 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
799 case SND_SOC_DAIFMT_CBM_CFM:
801 iface_reg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
803 case SND_SOC_DAIFMT_CBS_CFS:
805 iface_reg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
807 case SND_SOC_DAIFMT_CBS_CFM:
809 iface_reg |= BIT_CLK_MASTER;
810 iface_reg &= ~(WORD_CLK_MASTER);
813 printk ("Invalid DAI master/slave interface\n");
817 /* interface format */
818 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
819 case SND_SOC_DAIFMT_I2S:
821 case SND_SOC_DAIFMT_DSP_A:
822 iface_reg |= (AIC3111_DSP_MODE << AUDIO_MODE_SHIFT);
824 case SND_SOC_DAIFMT_RIGHT_J:
825 iface_reg |= (AIC3111_RIGHT_JUSTIFIED_MODE << AUDIO_MODE_SHIFT);
827 case SND_SOC_DAIFMT_LEFT_J:
828 iface_reg |= (AIC3111_LEFT_JUSTIFIED_MODE << AUDIO_MODE_SHIFT);
831 printk ("Invalid DAI interface format\n");
835 aic3111_write (codec, INTERFACE_SET_REG_1, iface_reg);
842 *----------------------------------------------------------------------------
843 * Function : aic3111_power_headphone
845 * parameter: on = 1: power up;
848 *----------------------------------------------------------------------------
850 static int aic3111_power_headphone (bool on)
852 struct snd_soc_codec *codec = aic3111_codec;
854 AIC_DBG("Enter %s and line %d\n",__FUNCTION__,__LINE__);
856 if (on == POWER_STATE_ON) {
857 aic3111_write (codec, (63), 0xd4);
858 // aic3111_write(codec, (128 + 35), 0x88);
859 aic3111_write (codec, (68), 0x01); //disable DRC
860 aic3111_write (codec, (128 + 31), 0xc4);
861 aic3111_write (codec, (128 + 44), 0x00);
862 aic3111_write (codec, (128 + 36), 0x28); //Left Analog Vol to HPL
863 aic3111_write (codec, (128 + 37), 0x28); //Right Analog Vol to HPL
864 // aic3111_write (codec, (128 + 40), 0x06); //HPL driver PGA
865 // aic3111_write (codec, (128 + 41), 0x06); //HPR driver PGA
866 aic3111_write (codec, (128 + 40), 0x4f); //HPL driver PGA
867 aic3111_write (codec, (128 + 41), 0x4f); //HPR driver PGA
869 } else if (on == POWER_STATE_OFF) {
871 aic3111_write (codec, (128 + 31), 0x00);
872 aic3111_write (codec, (128 + 44), 0x00);
873 aic3111_write (codec, (128 + 36), 0xff);
874 aic3111_write (codec, (128 + 37), 0xff);
875 aic3111_write (codec, (128 + 40), 0x02);
876 aic3111_write (codec, (128 + 41), 0x02);
883 *----------------------------------------------------------------------------
884 * Function : aic3111_power_speaker
886 * parameter: on = 1: power up;
889 *----------------------------------------------------------------------------
891 static int aic3111_power_speaker (bool on)
893 struct snd_soc_codec *codec = aic3111_codec;
895 AIC_DBG("Enter %s and line %d\n",__FUNCTION__,__LINE__);
897 if (on == POWER_STATE_ON) {
899 // aic3111_write(codec, (128 + 32), 0x86);
900 aic3111_write(codec, (128 + 32), 0xc6);
901 aic3111_write(codec, (128 + 30), 0x00);
902 // aic3111_write(codec, (128 + 38), 0x08); //set left speaker analog gain to -4.88db
903 aic3111_write(codec, (128 + 38), 0x16); //set left speaker analog gain to -4.88db
904 aic3111_write(codec, (128 + 39), 0x16); //Right Analog Vol to SPR
905 // aic3111_write(codec, (128 + 38), 0x7f); //set left speaker analog gain to -4.88db
906 // aic3111_write(codec, (128 + 39), 0x7f); //Right Analog Vol to SPR
907 aic3111_write(codec, (128 + 42), 0x1d); //set left speaker driver gain to 12db
908 aic3111_write(codec, (128 + 43), 0x1d); //bit3-4 output stage gain
909 // aic3111_write(codec, (128 + 43), 0x00); //bit3-4 output stage gain
910 aic3111_write(codec, (37), 0x98);
913 aic3111_write(codec, (60), 0x02); //select PRB_P2
914 aic3111_write(codec, (68), 0x61); //enable left and right DRC, set DRC threshold to -3db, set DRC hystersis to 1db
915 aic3111_write(codec, (69), 0x00); //set hold time disable
916 aic3111_write(codec, (70), 0x5D); //set attack time to 0.125db per sample period and decay time to 0.000488db per sample
920 aic3111_write(codec, (63), 0xfc);
921 aic3111_write(codec, (128 + 32), 0xc6);
922 aic3111_write(codec, (128 + 30), 0x00);
923 aic3111_write(codec, (128 + 39), 0x08); //set left speaker analog gain to -4.88db
924 aic3111_write(codec, (128 + 38), 0x08); //Right Analog Vol to SPR
925 aic3111_write(codec, (128 + 43), 0x0D); //set left speaker driver gain to 12db
926 aic3111_write(codec, (128 + 42), 0x0D); //bit3-4 output stage gain
927 aic3111_write(codec, (37), 0x99);
930 aic3111_write(codec, (60), 0x02); //select PRB_P2
931 aic3111_write(codec, (68), 0x61); //enable left and right DRC, set DRC threshold to -3db, set DRC hystersis to 1db
932 aic3111_write(codec, (69), 0x00); //set hold time disable
933 aic3111_write(codec, (70), 0x5D); //set attack time to 0.125db per sample period and decay time to 0.000488db per sample
936 } else if (on == POWER_STATE_OFF) {
938 aic3111_write(codec, (68), 0x01); //disable DRC
939 aic3111_write(codec, (128 + 32), 0x06);
940 aic3111_write(codec, (128 + 30), 0x00);
941 aic3111_write(codec, (128 + 38), 0xff);
942 aic3111_write(codec, (128 + 39), 0xff);
943 aic3111_write(codec, (128 + 42), 0x00);
944 aic3111_write(codec, (128 + 43), 0x00);
945 aic3111_write(codec, (37), 0x00);
952 *----------------------------------------------------------------------------
953 * Function : aic3111_HS_switch
954 * Purpose : This function is to initialise the AIC3111 driver
955 * In PLAYBACK, switch between HP and SPK app.
956 * parameter: on = 1: SPK power up & HP power dn;
957 * on = 0: HP power up & SPK power dn;
959 *----------------------------------------------------------------------------
961 static int aic3111_HS_switch (bool on)
963 AIC_DBG("enter %s and line %d\n",__FUNCTION__,__LINE__);
965 if (POWER_STATE_SW_SPK == on) {
967 //aic3111_power_headphone (POWER_STATE_OFF);
968 aic3111_power_speaker (POWER_STATE_ON);
969 } else if (POWER_STATE_SW_HP == on) {
971 aic3111_power_speaker (POWER_STATE_OFF);
972 //aic3111_power_headphone (POWER_STATE_ON);
974 //aic3111_power_speaker (POWER_STATE_ON);
975 //aic3111_power_headphone (POWER_STATE_OFF);
982 *----------------------------------------------------------------------------
983 * Function : aic3111_SPK_HS_powerdown
984 * Purpose : This function is to power down HP and SPK.
986 *----------------------------------------------------------------------------
988 static int aic3111_SPK_HS_powerdown (void)
990 AIC_DBG("enter %s and line %d\n",__FUNCTION__,__LINE__);
992 //aic3111_power_headphone (POWER_STATE_OFF);
993 aic3111_power_speaker (POWER_STATE_OFF);
994 // aic3111_power_speaker (POWER_STATE_ON);
1000 *----------------------------------------------------------------------------
1001 * Function : aic3111_power_init
1002 * Purpose : pll clock setting
1003 * parameter: on = 1: power up;
1005 * xjq@rock-chips.com
1006 *----------------------------------------------------------------------------
1008 static void aic3111_power_init (void)
1010 struct snd_soc_codec *codec = aic3111_codec;
1012 AIC_DBG("enter %s and line %d\n",__FUNCTION__,__LINE__);
1014 if (!(aic3111_current_status & AIC3110_IS_INITPOWER_ON)) {
1016 AIC_DBG ("CODEC::%s\n", __FUNCTION__);
1018 aic3111_write(codec, (128 + 46), 0x0b);
1019 aic3111_write(codec, (128 + 35), 0x44);
1020 aic3111_write(codec, (4), 0x03);
1021 aic3111_write(codec, (29), 0x01);
1022 aic3111_write(codec, (48), 0xC0);
1023 aic3111_write(codec, (51), 0x14);
1024 aic3111_write(codec, (67), 0x82);
1026 aic3111_current_status |= AIC3110_IS_INITPOWER_ON;
1033 *----------------------------------------------------------------------------
1034 * Function : aic3111_power_playback
1036 * parameter: on = 1: power up;
1038 * xjq@rock-chips.com
1039 *----------------------------------------------------------------------------
1041 static int aic3111_power_playback (bool on)
1043 struct snd_soc_codec *codec = aic3111_codec;
1045 AIC_DBG ("CODEC::%s>>>>>>%d\n", __FUNCTION__, on);
1046 gpio_set_value(RK29_PIN6_PB5, GPIO_LOW);
1047 aic3111_power_init();
1049 if ((on == POWER_STATE_ON) &&
1050 !(aic3111_current_status & AIC3110_IS_PLAYBACK_ON)) {
1052 //gpio_set_value(RK29_PIN6_PB5, GPIO_HIGH);
1054 /****open HPL and HPR*******/
1055 //aic3111_write(codec, (63), 0xfc);
1057 aic3111_write(codec, (65), 0x00); //LDAC VOL
1058 aic3111_write(codec, (66), 0x00); //RDAC VOL
1059 aic3111_write (aic3111_codec, (63), 0xd4);
1060 // aic3111_write(codec, (128 + 35), 0x88);
1062 //aic3111_write (aic3111_codec, (68), 0x01); //disable DRC
1063 //aic3111_write (aic3111_codec, (128 + 31), 0xc4);
1064 aic3111_write (aic3111_codec, (128 + 44), 0x00);
1065 //aic3111_write (aic3111_codec, (128 + 36), 0x28); //Left Analog Vol to HPL
1066 //aic3111_write (aic3111_codec, (128 + 37), 0x28); //Right Analog Vol to HPL
1067 aic3111_write (codec, (128 + 40), 0x06); //HPL driver PGA
1068 aic3111_write (codec, (128 + 41), 0x06); //HPR driver PGA
1069 //aic3111_write (aic3111_codec, (128 + 40), 0x4f); //HPL driver PGA
1070 //aic3111_write (aic3111_codec, (128 + 41), 0x4f); //HPR driver PGA
1071 //printk("HP INIT~~~~~~~~~~~~~~~~~~~~~~~~~`\n");
1072 /***************************/
1074 aic3111_HS_switch(isHSin);
1076 aic3111_write(codec, (65), 0x10); //LDAC VOL to +8db
1077 aic3111_write(codec, (66), 0x10); //RDAC VOL to +8db
1079 aic3111_write(codec, (64), 0x00);
1081 aic3111_current_status |= AIC3110_IS_PLAYBACK_ON;
1083 } else if ((on == POWER_STATE_OFF) &&
1084 (aic3111_current_status & AIC3110_IS_PLAYBACK_ON)) {
1086 aic3111_write(codec, (68), 0x01); //disable DRC
1087 aic3111_write(codec, (64), 0x0c);
1088 aic3111_write(codec, (63), 0x00);
1089 aic3111_write(codec, (65), 0x00); //LDAC VOL
1090 aic3111_write(codec, (66), 0x00); //RDAC VOL
1092 aic3111_SPK_HS_powerdown();
1094 aic3111_current_status &= ~AIC3110_IS_PLAYBACK_ON;
1097 gpio_set_value(RK29_PIN6_PB5, GPIO_HIGH);
1103 *----------------------------------------------------------------------------
1104 * Function : aic3111_power_capture
1106 * parameter: on = 1: power up;
1108 * xjq@rock-chips.com
1109 *----------------------------------------------------------------------------
1111 static int aic3111_power_capture (bool on)
1113 struct snd_soc_codec *codec = aic3111_codec;
1115 AIC_DBG ("CODEC::%s>>>>>>%d\n", __FUNCTION__, on);
1117 aic3111_power_init();
1119 if ((on == POWER_STATE_ON) &&
1120 !(aic3111_current_status & AIC3110_IS_CAPTURE_ON)) {
1121 aic3111_write(codec, (64), 0x0c);
1124 aic3111_write(codec, (61), 0x0b);
1125 aic3111_write(codec, (128 + 47), 0x00); //MIC PGA 0x80:0dB 0x14:10dB 0x28:20dB 0x3c:30dB 0x77:59dB
1126 aic3111_write(codec, (128 + 48), 0x80); //MIC1LP\MIC1LM RIN = 10.
1127 aic3111_write(codec, (128 + 49), 0x20);
1128 aic3111_write(codec, (82), 0x00); //D7=0:0: ADC channel not muted
1129 aic3111_write(codec, (83), 0x1A); //ADC Digital Volume 0 dB
1130 aic3111_write(codec, (81), 0x80); //D7=1:ADC channel is powered up.
1133 /*configure register to creat a filter 20~3.5kHz*/
1135 aic3111_write(codec, (128*4 + 14), 0x7f);
1136 aic3111_write(codec, (128*4 + 15), 0x00);
1137 aic3111_write(codec, (128*4 + 16), 0xc0);
1138 aic3111_write(codec, (128*4 + 17), 0x18);
1139 aic3111_write(codec, (128*4 + 18), 0x00);
1141 aic3111_write(codec, (128*4 + 19), 0x00);
1142 aic3111_write(codec, (128*4 + 20), 0x3f);
1143 aic3111_write(codec, (128*4 + 21), 0x00);
1144 aic3111_write(codec, (128*4 + 22), 0x00);
1145 aic3111_write(codec, (128*4 + 23), 0x00);
1147 aic3111_write(codec, (128*4 + 24), 0x05);
1148 aic3111_write(codec, (128*4 + 25), 0xd2);
1149 aic3111_write(codec, (128*4 + 26), 0x05);
1150 aic3111_write(codec, (128*4 + 27), 0xd2);
1151 aic3111_write(codec, (128*4 + 28), 0x05);
1153 aic3111_write(codec, (128*4 + 29), 0xd2);
1154 aic3111_write(codec, (128*4 + 30), 0x53);
1155 aic3111_write(codec, (128*4 + 31), 0xff);
1156 aic3111_write(codec, (128*4 + 32), 0xc0);
1157 aic3111_write(codec, (128*4 + 33), 0xb5);
1160 aic3111_write(codec, (64), 0x00);
1161 aic3111_current_status |= AIC3110_IS_CAPTURE_ON;
1163 } else if ((on == POWER_STATE_OFF) &&
1164 (aic3111_current_status & AIC3110_IS_CAPTURE_ON)) {
1166 aic3111_write(codec, (61), 0x00);
1167 aic3111_write(codec, (128 + 47), 0x00); //MIC PGA AOL
1168 aic3111_write(codec, (128 + 48), 0x00);
1169 aic3111_write(codec, (128 + 50), 0x00);
1170 aic3111_write(codec, (81), 0x00);
1171 aic3111_write(codec, (82), 0x80);
1172 aic3111_write(codec, (83), 0x00); //ADC VOL
1173 aic3111_write(codec, (86), 0x00);
1175 aic3111_current_status &= ~AIC3110_IS_CAPTURE_ON;
1182 *----------------------------------------------------------------------------
1183 * Function : aic3111_powerdown
1184 * Purpose : This function is to power down codec.
1186 *----------------------------------------------------------------------------
1188 static void aic3111_powerdown (void)
1190 AIC_DBG ("CODEC::%s\n", __FUNCTION__);
1192 if (aic3111_current_status != AIC3110_IS_SHUTDOWN) {
1193 aic3111_soft_reset();//sai
1194 aic3111_current_status = AIC3110_IS_SHUTDOWN;
1199 *----------------------------------------------------------------------------
1200 * Function : aic3111_work
1201 * Purpose : This function is to respond to HPDET handle.
1203 *----------------------------------------------------------------------------
1205 static void aic3111_work (struct work_struct *work)
1207 AIC_DBG("Enter %s and line %d\n",__FUNCTION__,__LINE__);
1209 switch (aic3111_work_type) {
1210 case AIC3110_POWERDOWN_NULL:
1212 case AIC3110_POWERDOWN_PLAYBACK:
1213 aic3111_power_playback(POWER_STATE_OFF);
1215 case AIC3110_POWERDOWN_CAPTURE:
1216 aic3111_power_capture(POWER_STATE_OFF);
1218 case AIC3110_POWERDOWN_PLAYBACK_CAPTURE:
1219 aic3111_powerdown();//sai
1225 aic3111_work_type = AIC3110_POWERDOWN_NULL;
1229 *----------------------------------------------------------------------------
1230 * Function : aic3111_startup
1231 * Purpose : This function is to start up codec.
1233 *----------------------------------------------------------------------------
1235 static int aic3111_startup (struct snd_pcm_substream *substream,
1236 struct snd_soc_dai *dai)
1239 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1240 struct snd_soc_codec *codec = aic3111_codec;
1243 AIC_DBG ("CODEC::%s----substream->stream:%s \n", __FUNCTION__,
1244 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "PLAYBACK":"CAPTURE");
1246 cancel_delayed_work_sync(&delayed_work);
1248 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1250 aic3111_power_playback(POWER_STATE_ON);
1252 } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1254 aic3111_power_capture(POWER_STATE_ON);
1261 *----------------------------------------------------------------------------
1262 * Function : aic3111_startup
1263 * Purpose : This function is to shut down codec.
1265 *----------------------------------------------------------------------------
1267 static void aic3111_shutdown (struct snd_pcm_substream *substream,
1268 struct snd_soc_dai *dai)
1270 struct snd_soc_dai *codec_dai = dai;
1272 AIC_DBG ("CODEC::%s----substream->stream:%s \n", __FUNCTION__,
1273 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "PLAYBACK":"CAPTURE");
1275 if (!codec_dai->capture_active && !codec_dai->playback_active) {
1277 cancel_delayed_work_sync(&delayed_work);
1279 /* If codec is already shutdown, return */
1280 if (aic3111_current_status == AIC3110_IS_SHUTDOWN)
1283 AIC_DBG ("CODEC::Is going to power down aic3111\n");
1285 aic3111_work_type = AIC3110_POWERDOWN_PLAYBACK_CAPTURE;
1287 /* If codec is useless, queue work to close it */
1288 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1289 queue_delayed_work(aic3111_workq, &delayed_work,
1290 msecs_to_jiffies(1000));
1293 queue_delayed_work(aic3111_workq, &delayed_work,
1294 msecs_to_jiffies(3000));
1297 else if (codec_dai->capture_active && !codec_dai->playback_active) {
1299 cancel_delayed_work_sync(&delayed_work);
1301 aic3111_work_type = AIC3110_POWERDOWN_PLAYBACK;
1303 /* Turn off playback and keep record on */
1304 queue_delayed_work(aic3111_workq, &delayed_work,
1305 msecs_to_jiffies(1000));
1307 else if (!codec_dai->capture_active && codec_dai->playback_active) {
1309 cancel_delayed_work_sync(&delayed_work);
1311 aic3111_work_type = AIC3110_POWERDOWN_CAPTURE;
1313 /* Turn off record and keep playback on */
1314 queue_delayed_work(aic3111_workq, &delayed_work,
1315 msecs_to_jiffies(3000));
1320 *----------------------------------------------------------------------------
1321 * Function : aic3111_trigger
1322 * Purpose : This function is to respond to playback trigger.
1324 *----------------------------------------------------------------------------
1326 static int aic3111_trigger(struct snd_pcm_substream *substream,
1328 struct snd_soc_dai *dai)
1330 struct snd_soc_dai *codec_dai = dai;
1334 gpio_set_value(RK29_PIN6_PB5, GPIO_LOW);
1338 AIC_DBG ("CODEC::%s----status = %d substream->stream:%s \n", __FUNCTION__, status,
1339 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "PLAYBACK":"CAPTURE");
1341 if (status == 1 || status == 0) {
1342 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1343 codec_dai->playback_active = status;
1345 codec_dai->capture_active = status;
1352 static struct snd_soc_dai_ops aic3111_dai_ops = {
1353 .hw_params = aic3111_hw_params,
1354 .digital_mute = aic3111_mute,
1355 .set_sysclk = aic3111_set_dai_sysclk,
1356 .set_fmt = aic3111_set_dai_fmt,
1357 .startup = aic3111_startup,
1358 .shutdown = aic3111_shutdown,
1359 .trigger = aic3111_trigger,
1362 static struct snd_soc_dai_driver aic3111_dai[] = {
1364 .name = "AIC3111 HiFi",
1366 .stream_name = "HiFi Playback",
1369 .rates = AIC3111_RATES,
1370 .formats = AIC3111_FORMATS,
1373 .stream_name = "HiFi Capture",
1376 .rates = AIC3111_RATES,
1377 .formats = AIC3111_FORMATS,
1379 .ops = &aic3111_dai_ops,
1383 #ifdef AIC3111_DEBUG
1384 static struct class *aic3111_debug_class = NULL;
1385 static int reg_128_39 = 12, reg_128_43 = 0;
1386 static int i=52;j=1,k=0;
1387 static int CheckCommand(const char __user *buffer)
1391 if (*(buffer + 1) == '+') {
1392 if (reg_128_39 < 12) {
1393 if (reg_128_39 % 2 == 0)
1394 printk("write reg 128 + 39 vol + : %ddB -> -%d.5dB\n", (reg_128_39 - 12) / 2, (11 - reg_128_39) / 2);
1396 printk("write reg 128 + 39 vol + : -%d.5dB -> %ddB\n", (12 - reg_128_39) / 2, (reg_128_39 - 11) / 2);
1398 aic3111_write(aic3111_codec, (128 + 39), 0x04 + (12 - reg_128_39));
1400 printk("128 + 39 max vol 0dB\n");
1402 } else if (*(buffer + 1) == '-') {
1403 if (reg_128_39 > 0) {
1404 if (reg_128_39 % 2 == 0)
1405 printk("write reg 128 + 39 vol - : %ddB -> -%d.5dB\n", (reg_128_39 - 12) / 2, (13 - reg_128_39) / 2);
1407 printk("write reg 128 + 39 vol - : -%d.5dB -> %ddB\n", (12 - reg_128_39) / 2, (reg_128_39 - 13) / 2);
1409 aic3111_write(aic3111_codec, (128 + 39), 0x08 + (12 - reg_128_39));
1411 printk("128 + 39 min vol -6dB\n");
1416 if (*(buffer + 1) == '+') {
1417 if (reg_128_43 < 2) {
1418 printk("write reg 128 + 43 vol + : %ddB -> %ddB\n", (reg_128_43) * 6, (reg_128_43 + 1) * 6);
1420 aic3111_write(aic3111_codec, (128 + 43), 0x04 + ((reg_128_43 + 1) << 3));
1422 printk("128 + 43 max vol 12dB\n");
1424 } else if (*(buffer + 1) == '-') {
1425 if (reg_128_43 > 0) {
1426 printk("write reg 128 + 43 vol - : %ddB -> %ddB\n", (reg_128_43) * 6, (reg_128_43 - 1) * 6);
1428 aic3111_write(aic3111_codec, (128 + 43), 0x04 + ((reg_128_43 + 1) << 3));
1430 printk("128 + 43 min vol 0dB\n");
1435 aic3111_write(aic3111_codec, (128 + 39), 0x08 + (12 - reg_128_39));
1436 aic3111_write(aic3111_codec, (128 + 43), 0x04 + ((reg_128_43 + 1) << 3));
1438 if (reg_128_39 % 2 == 0)
1439 printk("reg 128 + 43 vol : %ddB reg 128 + 39 vol : %ddB\n", (reg_128_43) * 6, (reg_128_39 - 12) / 2);
1441 printk("reg 128 + 43 vol : %ddB reg 128 + 39 vol : -%d.5dB\n", (reg_128_43) * 6, (12 - reg_128_39) / 2);
1444 aic3111_power_speaker (POWER_STATE_ON);
1448 aic3111_power_headphone (POWER_STATE_ON);
1452 aic3111_power_speaker (POWER_STATE_OFF);
1456 aic3111_power_headphone (POWER_STATE_OFF);
1461 gpio_set_value(RK29_PIN6_PB5, GPIO_HIGH);
1462 //printk("reg[128+39]=0x%x\n",aic3111_read(aic3111_codec,(128 + 39)));
1463 printk("-db add\n");
1467 gpio_set_value(RK29_PIN6_PB5, GPIO_LOW);
1468 //printk("reg[128+39]=0x%x\n",aic3111_read(aic3111_codec,(128 + 39)));
1469 printk("-db down\n");
1473 printk("PB5 = %d\n",gpio_get_value(RK29_PIN6_PB5));
1478 aic3111_write(aic3111_codec, (66), j);
1479 printk("DAC db add\n");
1480 printk("reg[66]=0x%x\n",aic3111_read(aic3111_codec,66));
1484 aic3111_write(aic3111_codec, (66), j);
1485 printk("DAC db down\n");
1486 printk("reg[66]=0x%x\n",aic3111_read(aic3111_codec,66));
1491 aic3111_write(aic3111_codec, (63), 0xfc);
1492 printk("reg[63]=0x%x\n",aic3111_read(aic3111_codec,66));
1499 aic3111_write(aic3111_codec, (128 + 40), 0x0e);
1500 aic3111_write(aic3111_codec, (128 + 41), 0x0e);
1501 printk("HPR and HPL 1 DB\n",k);
1505 aic3111_write(aic3111_codec, (128 + 40), 0x1e);
1506 aic3111_write(aic3111_codec, (128 + 40), 0x1e);
1507 printk("HPR and HPL 3 DB\n",k);
1511 aic3111_write(aic3111_codec, (128 + 40), 0x2e);
1512 aic3111_write(aic3111_codec, (128 + 40), 0x2e);
1513 printk("HPR and HPL 5 DB\n",k);
1521 aic3111_write(aic3111_codec, (128 + 40), 0x0e);
1522 aic3111_write(aic3111_codec, (128 + 41), 0x0e);
1523 printk("HPR and HPL 1 DB\n",k);
1527 aic3111_write(aic3111_codec, (128 + 40), 0x1e);
1528 aic3111_write(aic3111_codec, (128 + 40), 0x1e);
1529 printk("HPR and HPL 3 DB\n",k);
1533 aic3111_write(aic3111_codec, (128 + 40), 0x2e);
1534 aic3111_write(aic3111_codec, (128 + 40), 0x2e);
1535 printk("HPR and HPL 5 DB\n",k);
1541 printk("Please press '1' '2' 'o' 'l' !\n");
1547 static int aic3111_proc_write(struct file *file, const char __user *buffer,
1548 unsigned long count, void *data)
1550 if (CheckCommand(buffer) != 0) {
1551 printk("Write proc error !\n");
1555 return sizeof(buffer);
1557 static const struct file_operations aic3111_proc_fops = {
1558 .owner = THIS_MODULE,
1559 .write = aic3111_proc_write,
1562 static int aic3111_proc_init(void) {
1564 struct proc_dir_entry *aic3111_proc_entry;
1565 //printk("!!!!!!!!!!!!!!!!!!!!\n");
1566 aic3111_proc_entry = create_proc_entry("driver/aic3111_ts", 0777, NULL);
1568 if (aic3111_proc_entry != NULL) {
1570 aic3111_proc_entry->write_proc = aic3111_proc_write;
1574 printk("create proc error !\n");
1581 struct delayed_work aic3111_speaker_delayed_work;
1584 static void aic3111_speaker_delayed_work_func(struct work_struct *work)
1586 struct snd_soc_codec *codec = aic3111_codec;
1588 if (aic3111_current_status & AIC3110_IS_PLAYBACK_ON){
1591 //aic3111_write(codec, (128 + 32), 0xc6);
1592 //printk("reg 128+32 = %x\n"aic3111_read(codec, (128 + 32)));
1594 //gpio_set_value(RK29_PIN6_PB5, GPIO_LOW);
1595 aic3111_power_speaker(POWER_STATE_OFF);
1596 gpio_set_value(RK29_PIN6_PB5, GPIO_HIGH);
1597 //aic3111_power_headphone(POWER_STATE_ON);
1598 //aic3111_write(codec, (128 + 35), 0x88);
1599 printk("now hp sound\n");
1602 //aic3111_power_speaker(POWER_STATE_ON);
1605 //aic3111_power_headphone(POWER_STATE_OFF);
1606 gpio_set_value(RK29_PIN6_PB5, GPIO_LOW);
1607 aic3111_power_speaker(POWER_STATE_ON);
1608 aic3111_write(codec, (128 + 35), 0x44);
1609 aic3111_write(codec, (63), 0xfc);
1610 printk("now spk sound\n");
1614 //printk("----------------------------mma7660_work_func------------------------\n");
1618 /**for check hp or spk****/
1619 static int speaker_timer(unsigned long _data)
1621 struct speaker_data *spk = (struct speaker_data *)_data;
1624 if (gpio_get_value(RK29_PIN6_PB6) == 0) {
1627 //printk("hp now\n");
1628 if(old_status != new_status)
1630 old_status = new_status;
1631 // printk("new_status = %d,old_status = %d\n",new_status,old_status);
1632 old_status = new_status;
1634 schedule_delayed_work(&aic3111_speaker_delayed_work,msecs_to_jiffies(30));
1636 //printk("HS RUN!!!!!!!!!!\n");
1640 if (gpio_get_value(RK29_PIN6_PB6) == 1) {
1643 //printk("speak now\n");
1644 if(old_status != new_status)
1646 old_status = new_status;
1647 printk("new_status = %d,old_status = %d\n",new_status,old_status);
1648 old_status = new_status;
1650 schedule_delayed_work(&aic3111_speaker_delayed_work,msecs_to_jiffies(30));
1652 //printk("HS RUN!!!!!!!!!!\n");
1656 mod_timer(&spk->timer, jiffies + msecs_to_jiffies(200));
1661 *----------------------------------------------------------------------------
1662 * Function : aic3111_probe
1663 * Purpose : This is first driver function called by the SoC core driver.
1665 *----------------------------------------------------------------------------
1667 static int aic3111_probe (struct snd_soc_codec *codec)
1669 int ret = 0;//, flags, hp_det_irq;
1671 codec->hw_write = (hw_write_t) i2c_master_send;
1672 codec->control_data = aic3111_i2c;
1673 aic3111_codec = codec;
1676 gpio_set_value(RK29_PIN6_PB6,1);
1677 struct speaker_data *spk;
1679 spk = kzalloc(sizeof(struct speaker_data), GFP_KERNEL);
1681 printk("Allocate Memory Failed!\n");
1683 //goto exit_gpio_free;
1686 setup_timer(&spk->timer, speaker_timer, (unsigned long)spk);
1687 mod_timer(&spk->timer, jiffies + JACK_DET_ADLOOP);
1688 INIT_DELAYED_WORK(&aic3111_speaker_delayed_work, aic3111_speaker_delayed_work_func);
1690 /*********************/
1691 //pio_set_value(RK29_PIN6_PB5, GPIO_LOW);
1692 //aic3111_power_speaker(POWER_STATE_OFF);
1693 //aic3111_power_headphone(POWER_STATE_ON);
1696 aic3111_workq = create_freezable_workqueue("aic3111");
1697 if (aic3111_workq == NULL) {
1701 /* INIT_DELAYED_WORK (&aic3111_hpdet_work, aic3111_hpdet_work_handle);
1702 if (gpio_request (HP_DET_PIN, "hp_det")) {
1703 gpio_free (HP_DET_PIN);
1704 printk ("CODEC::tlv3110 hp det pin request error\n");
1707 gpio_direction_input (HP_DET_PIN);
1708 gpio_pull_updown (HP_DET_PIN, PullDisable);
1709 hp_det_irq = gpio_to_irq (HP_DET_PIN);
1710 isHSin = gpio_get_value (HP_DET_PIN);
1712 flags = isHSin ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING;
1713 ret = request_irq (hp_det_irq, aic3111_hpdet_isr, flags, "hpdet", codec);
1715 printk ("CODEC::request hp_det_irq error\n");
1719 /* Just Reset codec */
1720 aic3111_soft_reset();
1721 gpio_set_value(RK29_PIN6_PB5, GPIO_LOW);
1723 aic3111_write (aic3111_codec, (68), 0x01); //disable DRC
1724 aic3111_write (aic3111_codec, (128 + 31), 0xc4);
1725 aic3111_write (aic3111_codec, (128 + 36), 0x28); //Left Analog Vol to HPL
1726 aic3111_write (aic3111_codec, (128 + 37), 0x28); //Right Analog Vol to HPL
1727 aic3111_write (aic3111_codec, (128 + 40), 0x4f); //HPL driver PGA
1728 aic3111_write (aic3111_codec, (128 + 41), 0x4f); //HPR driver PGA
1730 #ifdef AIC3111_DEBUG
1731 aic3111_proc_init();
1734 aic3111_set_bias_level (codec, SND_SOC_BIAS_STANDBY);
1740 *----------------------------------------------------------------------------
1741 * Function : aic3111_remove
1742 * Purpose : to remove aic3111 soc device
1744 *----------------------------------------------------------------------------
1746 static int aic3111_remove (struct snd_soc_codec *codec)
1748 AIC_DBG ("CODEC::%s\n", __FUNCTION__);
1750 /* Disable HPDET irq */
1751 //disable_irq_nosync (HP_DET_PIN);
1753 /* power down chip */
1754 aic3111_set_bias_level (codec, SND_SOC_BIAS_OFF);
1760 *----------------------------------------------------------------------------
1761 * Function : aic3111_suspend
1762 * Purpose : This function is to suspend the AIC3111 driver.
1764 *----------------------------------------------------------------------------
1766 static int aic3111_suspend (struct snd_soc_codec *codec, pm_message_t state)
1769 AIC_DBG ("CODEC::%s\n", __FUNCTION__);
1771 aic3111_set_bias_level (codec, SND_SOC_BIAS_STANDBY);
1773 aic3111_soft_reset();//sai
1779 *----------------------------------------------------------------------------
1780 * Function : aic3111_resume
1781 * Purpose : This function is to resume the AIC3111 driver
1783 *----------------------------------------------------------------------------
1785 static int aic3111_resume (struct snd_soc_codec *codec)
1787 //isHSin = gpio_get_value(HP_DET_PIN);
1788 aic3111_set_bias_level (codec, SND_SOC_BIAS_STANDBY);
1789 //aic3111_set_bias_level(codec, codec->suspend_bias_level);
1795 *----------------------------------------------------------------------------
1796 * @struct snd_soc_codec_device |
1797 * This structure is soc audio codec device sturecute which pointer
1798 * to basic functions aic3111_probe(), aic3111_remove(),
1799 * aic3111_suspend() and aic3111_resume()
1800 *----------------------------------------------------------------------------
1802 static struct snd_soc_codec_driver soc_codec_dev_aic3111 = {
1803 .probe = aic3111_probe,
1804 .remove = aic3111_remove,
1805 .suspend = aic3111_suspend,
1806 .resume = aic3111_resume,
1807 .set_bias_level = aic3111_set_bias_level,
1808 .reg_cache_size = ARRAY_SIZE(aic31xx_reg),
1809 .reg_word_size = sizeof(u16),
1810 .reg_cache_default = aic31xx_reg,
1811 .reg_cache_step = 1,
1814 static const struct i2c_device_id tlv320aic3111_i2c_id[] = {
1818 MODULE_DEVICE_TABLE(i2c, tlv320aic3111_i2c_id);
1820 static int tlv320aic3111_i2c_probe(struct i2c_client *i2c,
1821 const struct i2c_device_id *id)
1823 struct aic3111_priv *aic3111;
1826 aic3111 = kzalloc(sizeof(struct aic3111_priv), GFP_KERNEL);
1827 if (NULL == aic3111)
1832 i2c_set_clientdata(i2c, aic3111);
1834 aic3111_privdata = aic3111;
1836 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_aic3111,
1837 aic3111_dai, ARRAY_SIZE(aic3111_dai));
1844 static __devexit int tlv320aic3111_i2c_remove(struct i2c_client *client)
1846 snd_soc_unregister_codec(&client->dev);
1847 kfree(i2c_get_clientdata(client));
1851 struct i2c_driver tlv320aic3111_i2c_driver = {
1854 .owner = THIS_MODULE,
1856 .probe = tlv320aic3111_i2c_probe,
1857 .remove = __devexit_p(tlv320aic3111_i2c_remove),
1858 .id_table = tlv320aic3111_i2c_id,
1861 static int __init tlv320aic3111_init (void)
1863 return i2c_add_driver(&tlv320aic3111_i2c_driver);
1866 static void __exit tlv320aic3111_exit (void)
1868 i2c_del_driver(&tlv320aic3111_i2c_driver);
1871 module_init (tlv320aic3111_init);
1872 module_exit (tlv320aic3111_exit);
1874 #ifdef CONFIG_PROC_FS
1875 #include <linux/proc_fs.h>
1876 #include <linux/seq_file.h>
1877 static int proc_3110_reg_show (struct seq_file *s, void *v)
1879 struct snd_soc_codec *codec = aic3111_codec;
1881 u8 *cache = codec->reg_cache;
1883 seq_printf (s, "========3110register========\n");
1884 for (reg = 0; reg < 256; reg++) {
1885 if (reg == 0) seq_printf (s, "Page 0\n");
1886 if (reg == 128) seq_printf (s, "\nPage 1\n");
1887 if (reg%8 == 0 && reg != 0 && reg != 128) seq_printf (s, "\n");
1888 seq_printf (s, "[%d]0x%02x, ",reg,aic3111_read (codec, reg));
1890 seq_printf (s, "\n========3110cache========\n");
1891 for (reg = 0; reg < codec->reg_size; reg++) {
1892 if (reg == 0) seq_printf (s, "Page 0\n");
1893 if (reg == 128) seq_printf (s, "\nPage 1\n");
1894 if (reg%16 == 0 && reg != 0 && reg != 128) seq_printf (s, "\n");
1895 seq_printf (s, "0x%02x, ",cache[reg]);
1897 printk ("\n==========================\n");
1901 static int proc_3110_reg_open (struct inode *inode, struct file *file)
1903 return single_open (file, proc_3110_reg_show, NULL);
1906 static const struct file_operations proc_3110_reg_fops = {
1907 .open = proc_3110_reg_open,
1909 .llseek = seq_lseek,
1910 .release = single_release,
1913 static int __init codec_proc_init (void)
1915 proc_create ("aic3110_register", 0, NULL, &proc_3110_reg_fops);
1919 late_initcall (codec_proc_init);
1920 #endif /* CONFIG_PROC_FS */
1922 MODULE_DESCRIPTION (" ASoC TLV320AIC3111 codec driver ");
1923 MODULE_AUTHOR (" Jaz B John <jazbjohn@mistralsolutions.com> ");
1924 MODULE_LICENSE ("GPL");