2 * linux/sound/soc/codecs/tlv320aic3111.h
4 * Copyright (C) 2010 Texas Instruments, Inc.
6 * This package is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
16 * Rev 0.1 ASoC driver support Mistral 14-04-2010
18 * Rev 0.2 Updated based Review Comments Mistral 29-06-2010
20 * Rev 0.3 Updated for Codec Family Compatibility 12-07-2010
23 #ifndef _TLV320AIC3111_H
24 #define _TLV320AIC3111_H
26 /* #define AUDIO_NAME "aic3111"
27 #define AIC3111_VERSION "0.1"
32 ******************AIC31xx CODEC SUPPORT *****************
33 * THE CURRENT CODE-BASE SUPPORTS BUILDING of the CODEC
34 * DRIVER FOR AIC3111, AIC3110, AIC3100 and AIC3120.
35 * PLEASE NOTE THAT FOR EACH OF THE ABOVE CODECS, the
36 * Linux Developer needs to enable a particular flag in
37 * this header file before performing a build of the
39 *********************************************************
42 //#define AIC3111_CODEC_SUPPORT
43 #define AIC3110_CODEC_SUPPORT
44 //#define AIC3100_CODEC_SUPPORT
45 //#define AIC3120_CODEC_SUPPORT
47 /* NOTE THAT AIC3110 and AIC3100 do not support miniDSP */
48 #ifdef AIC3110_CODEC_SUPPORT
49 #undef CONFIG_MINI_DSP
51 #define AUDIO_NAME "aic3110"
52 #define AIC3111_VERSION "0.1"
56 #ifdef AIC3100_CODEC_SUPPORT
57 #undef CONFIG_MINI_DSP
59 #define AUDIO_NAME "aic3100"
60 #define AIC3111_VERSION "0.1"
64 #ifdef AIC3120_CODEC_SUPPORT
65 #undef CONFIG_MINI_DSP
67 #define AUDIO_NAME "aic3120"
68 #define AIC3111_VERSION "0.1"
72 /* The user has a choice to enable or disable miniDSP code
73 * when building for AIC3111 Codec.
75 #ifdef AIC3111_CODEC_SUPPORT
76 /* Macro enables or disables support for miniDSP in the driver */
77 //#define CONFIG_MINI_DSP
78 #undef CONFIG_MINI_DSP
80 #define AUDIO_NAME "aic3111"
81 #define AIC3111_VERSION "0.1"
86 /* Enable slave / master mode for codec */
87 //#define AIC3111_MCBSP_SLAVE
88 #undef AIC3111_MCBSP_SLAVE
90 /* Enable register caching on write */
93 /* Enable headset detection */
94 #define HEADSET_DETECTION
96 /* AIC3111 supported sample rate are 8k to 192k */
97 #define AIC3111_RATES SNDRV_PCM_RATE_8000_192000
99 /* AIC3111 supports the word formats 16bits, 20bits, 24bits and 32 bits */
100 #define AIC3111_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
101 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
103 #define AIC3111_FREQ_12000000 12000000
104 #define AIC3111_FREQ_24000000 24000000
105 #define AIC3111_FREQ_11289600 11289600
107 /* AIC3111 register space */
108 #define AIC31xx_CACHEREGNUM 384
110 /* Audio data word length = 16-bits (default setting) */
111 #define AIC3111_WORD_LEN_16BITS 0x00
112 #define AIC3111_WORD_LEN_20BITS 0x01
113 #define AIC3111_WORD_LEN_24BITS 0x02
114 #define AIC3111_WORD_LEN_32BITS 0x03
115 #define DATA_LEN_SHIFT 4
117 /* sink: name of target widget */
118 #define AIC3111_WIDGET_NAME 0
119 /* control: mixer control name */
120 #define AIC3111_CONTROL_NAME 1
121 /* source: name of source name */
122 #define AIC3111_SOURCE_NAME 2
124 /* D15..D8 aic3111 register offset */
125 #define AIC3111_REG_OFFSET_INDEX 0
126 /* D7...D0 register data */
127 #define AIC3111_REG_DATA_INDEX 1
129 /* Serial data bus uses I2S mode (Default mode) */
130 #define AIC3111_I2S_MODE 0x00
131 #define AIC3111_DSP_MODE 0x01
132 #define AIC3111_RIGHT_JUSTIFIED_MODE 0x02
133 #define AIC3111_LEFT_JUSTIFIED_MODE 0x03
134 #define AUDIO_MODE_SHIFT 6
136 /* number of codec specific register for configuration */
137 #define NO_FEATURE_REGS 2
139 /* 8 bit mask value */
140 #define AIC3111_8BITS_MASK 0xFF
142 #ifndef AIC3120_CODEC_SUPPORT /* for AIC3111, AIC3110 and AIC3100 */
143 /* ****************** Page 0 Registers **************************************/
144 #define PAGE_SELECT 0
151 #define NDAC_CLK_REG 11
152 #define MDAC_CLK_REG 12
153 #define DAC_OSR_MSB 13
154 #define DAC_OSR_LSB 14
155 #define NADC_CLK_REG 18
156 #define MADC_CLK_REG 19
157 #define ADC_OSR_REG 20
158 #define CLK_MUX_REG 25
159 #define CLK_MVAL_REG 26
160 #define INTERFACE_SET_REG_1 27
161 #define DATA_SLOT_OFFSET 28
162 #define INTERFACE_SET_REG_2 29
163 #define BCLK_N_VAL 30
164 #define INTERFACE_SET_REG_3 31
165 #define INTERFACE_SET_REG_4 32
166 #define INTERFACE_SET_REG_5 33
167 #define I2C_BUS_COND 34
169 #define INTL_CRTL_REG_1 48
170 #define INTL_CRTL_REG_2 49
171 #define GPIO_CRTL_REG_1 51
173 #define DAC_PRB_SEL_REG 60
174 #define ADC_PRB_SEL_REG 61
175 #define DAC_CHN_REG 63
176 #define DAC_MUTE_CTRL_REG 64
180 #define HEADSET_DETECT 67
182 #define DRC_CTL_REG_1 68
183 #define DRC_CTL_REG_2 69
184 #define DRC_CTL_REG_3 70
186 #define LEFT_BEEP_GEN 71
187 #define RIGHT_BEEP_GEN 72
188 #define BEEP_LENGTH_MSB 73
189 #define BEEP_LENGTH_MID 74
190 #define BEEP_LENGTH_LSB 75
191 #define BEEP_SINX_MSB 76
192 #define BEEP_SINX_LSB 77
193 #define BEEP_COSX_MSB 78
194 #define BEEP_COSX_LSB 79
197 #define ADC_DIG_MIC 81
201 #define AGC_CTRL_1 86
202 #define AGC_CTRL_2 87
203 #define AGC_CTRL_3 88
204 #define AGC_CTRL_4 89
205 #define AGC_CTRL_5 90
206 #define AGC_CTRL_6 91
207 #define AGC_CTRL_7 92
208 #define AGC_CTRL_8 93
212 #define PIN_VOL_CTRL 116
213 #define PIN_VOL_GAIN 117
216 /******************** Page 1 Registers **************************************/
218 #define HEADPHONE_DRIVER (PAGE_1 + 31)
219 #define CLASSD_SPEAKER_AMP (PAGE_1 + 32)
220 #define HP_POP_CTRL (PAGE_1 + 33)
221 #define PGA_RAMP_CTRL (PAGE_1 + 34)
222 #define DAC_MIX_CTRL (PAGE_1 + 35)
223 #define L_ANLOG_VOL_2_HPL (PAGE_1 + 36)
224 #define R_ANLOG_VOL_2_HPR (PAGE_1 + 37)
225 #define L_ANLOG_VOL_2_SPL (PAGE_1 + 38)
226 #define R_ANLOG_VOL_2_SPR (PAGE_1 + 39)
227 #define HPL_DRIVER (PAGE_1 + 40)
228 #define HPR_DRIVER (PAGE_1 + 41)
229 #define SPL_DRIVER (PAGE_1 + 42)
230 #define SPR_DRIVER (PAGE_1 + 43)
231 #define HP_DRIVER_CTRL (PAGE_1 + 44)
232 #define MICBIAS_CTRL (PAGE_1 + 46)
233 #define MIC_PGA (PAGE_1 + 47)
234 #define MIC_GAIN (PAGE_1 + 48)
235 #define ADC_IP_SEL (PAGE_1 + 49)
236 #define CM_SET (PAGE_1 + 50)
238 #define L_MICPGA_P (PAGE_1 + 52)
239 #define L_MICPGA_N (PAGE_1 + 54)
240 #define R_MICPGA_P (PAGE_1 + 55)
241 #define R_MICPGA_N (PAGE_1 + 57)
243 /****************************************************************************/
244 /****************************************************************************/
245 #define BIT7 (1 << 7)
246 #define BIT6 (1 << 6)
247 #define BIT5 (1 << 5)
248 #define BIT4 (1 << 4)
249 #define BIT3 (1 << 3)
250 #define BIT2 (1 << 2)
251 #define BIT1 (1 << 1)
252 #define BIT0 (1 << 0)
254 #define HP_UNMUTE BIT2
255 #define HPL_UNMUTE BIT3
256 #define ENABLE_DAC_CHN (BIT6 | BIT7)
257 #define ENABLE_ADC_CHN (BIT6 | BIT7)
258 #define BCLK_DIR_CTRL (BIT2 | BIT3)
259 #define CODEC_CLKIN_MASK 0x03
260 #define MCLK_2_CODEC_CLKIN 0x00
261 #define CODEC_MUX_VALUE 0X03
262 /*Bclk_in selection*/
263 #define BDIV_CLKIN_MASK 0x03
264 #define DAC_MOD_CLK_2_BDIV_CLKIN BIT0
265 #define SOFT_RESET 0x01
268 #define BIT_CLK_MASTER BIT3
269 #define WORD_CLK_MASTER BIT2
270 #define HIGH_PLL BIT6
271 #define ENABLE_PLL BIT7
272 #define ENABLE_NDAC BIT7
273 #define ENABLE_MDAC BIT7
274 #define ENABLE_NADC BIT7
275 #define ENABLE_MADC BIT7
276 #define ENABLE_BCLK BIT7
277 #define LDAC_2_LCHN BIT4
278 #define RDAC_2_RCHN BIT2
279 #define RDAC_2_RAMP BIT2
280 #define LDAC_2_LAMP BIT6
281 #define LDAC_CHNL_2_HPL BIT3
282 #define RDAC_CHNL_2_HPR BIT3
283 #define SOFT_STEP_2WCLK BIT0
285 #define DEFAULT_VOL 0x0
286 //#define DEFAULT_VOL 0xAf
287 #define DISABLE_ANALOG BIT3
288 #define LDAC_2_HPL_ROUTEON BIT3
289 #define RDAC_2_HPR_ROUTEON BIT3
290 #define LINEIN_L_2_LMICPGA_10K BIT6
291 #define LINEIN_L_2_LMICPGA_20K BIT7
292 #define LINEIN_L_2_LMICPGA_40K (0x3 << 6)
293 #define LINEIN_R_2_RMICPGA_10K BIT6
294 #define LINEIN_R_2_RMICPGA_20K BIT7
295 #define LINEIN_R_2_RMICPGA_40K (0x3 << 6)
298 /****************************************************************************
299 * DAPM widget related #defines
300 ***************************************************************************
304 #define DACEXTRA_ENUM 2
305 #define DACCONTROL_ENUM 3
306 #define SOFTSTEP_ENUM 4
308 #define MICBIAS_ENUM 6
309 #define DACLEFTIP_ENUM 7
310 #define DACRIGHTIP_ENUM 8
311 #define VOLTAGE_ENUM 9
314 #define MIC1LP_ENUM 12
315 #define MIC1RP_ENUM 13
316 #define MIC1LM_ENUM 14
319 #define MIC1LMM_ENUM 17
323 #define ADCMUTE_ENUM 21
326 #ifdef AIC3120_CODEC_SUPPORT /*for AIC3120 */
327 /* ****************** Page 0 Registers **************************************/
328 #define PAGE_SELECT 0
335 #define NDAC_CLK_REG 11
336 #define MDAC_CLK_REG 12
337 #define DAC_OSR_MSB 13
338 #define DAC_OSR_LSB 14
339 #define NADC_CLK_REG 18
340 #define MADC_CLK_REG 19
341 #define ADC_OSR_REG 20
342 #define CLK_MUX_REG 25
343 #define CLK_MVAL_REG 26
344 #define INTERFACE_SET_REG_1 27
345 #define DATA_SLOT_OFFSET 28
346 #define INTERFACE_SET_REG_2 29
347 #define BCLK_N_VAL 30
348 #define INTERFACE_SET_REG_3 31
349 #define INTERFACE_SET_REG_4 32
350 #define INTERFACE_SET_REG_5 33
351 #define I2C_BUS_COND 34
353 #define INTL_CRTL_REG_1 48
354 #define INTL_CRTL_REG_2 49
355 #define GPIO_CRTL_REG_1 51
357 #define DAC_PRB_SEL_REG 60
358 #define ADC_PRB_SEL_REG 61
359 #define DAC_CHN_REG 63
360 #define DAC_MUTE_CTRL_REG 64
361 #define LDAC_VOL 65 /*Mistral: AIC3120 has mono dac...renamed from LDAC_VOL to DAC_VOL.*/
362 #define DAC_VOL 65 /*Mistral:..DUAL definition for compatibility*/
363 /*Mistral: 3120 is mono..RDAC_VOL is reserved..register removed*/
365 #define HEADSET_DETECT 67
367 #define DRC_CTL_REG_1 68
368 #define DRC_CTL_REG_2 69
369 #define DRC_CTL_REG_3 70
371 /* 3120 does not have beep generation circuits...So removed beep related registers*/
373 #define ADC_DIG_MIC 81
377 #define AGC_CTRL_1 86
378 #define AGC_CTRL_2 87
379 #define AGC_CTRL_3 88
380 #define AGC_CTRL_4 89
381 #define AGC_CTRL_5 90
382 #define AGC_CTRL_6 91
383 #define AGC_CTRL_7 92
384 #define AGC_CTRL_8 93
388 #define PIN_VOL_CTRL 116
389 #define PIN_VOL_GAIN 117
392 /******************** Page 1 Registers **************************************/
394 #define HEADPHONE_DRIVER (PAGE_1 + 31)
395 #define CLASSD_SPEAKER_AMP (PAGE_1 + 32)
396 #define HP_POP_CTRL (PAGE_1 + 33)
397 #define PGA_RAMP_CTRL (PAGE_1 + 34)
398 #define DAC_MIX_CTRL (PAGE_1 + 35)
399 #define L_ANLOG_VOL_2_HPL (PAGE_1 + 36)
400 #define ANALOG_HPOUT_VOL (PAGE_1 + 36)
401 /*Mistral: 3120 DAC is mono.. R_ANALOG_VOL_2_HPR register is removed*/
402 #define L_ANLOG_VOL_2_SPL (PAGE_1 + 38)
403 #define ANALOG_CDOUT_VOL (PAGE_1 + 38) /*Mistral: Dual definition for compatibility*/
404 /*Mistral: 3120 DAC is mono.. R_ANALOG_VOL_2_SPR register is removed*/
405 #define HPL_DRIVER (PAGE_1 + 40) /*Mistral: kept for compatibility*/
406 #define HP_DRIVER (PAGE_1 + 40) /*Mistral: Dual definition for compatibility*/
407 #define HPOUT_DRIVER (PAGE_1 + 40) /*Mistral: Triple definition for compatibility*/
408 /*Mistral: 3120 DAC is mono.. HPR_DRIVER register is removed*/
409 #define SPL_DRIVER (PAGE_1 + 42) /*Mistral: kept for compatibility*/
410 #define SP_DRIVER (PAGE_1 + 42) /*Mistral: Dual Definition for compatibility*/
411 #define CD_OUT_DRIVER (PAGE_1 + 42) /*Mistral: Triple definition for compatibility*/
412 /*Mistral: 3120 DAC is mono.. HPR_DRIVER register is removed*/
413 #define HP_DRIVER_CTRL (PAGE_1 + 44)
414 #define MICBIAS_CTRL (PAGE_1 + 46)
415 #define MIC_PGA (PAGE_1 + 47)
416 #define MIC_GAIN (PAGE_1 + 48)
417 #define ADC_IP_SEL (PAGE_1 + 49)
418 #define CM_SET (PAGE_1 + 50)
420 #define L_MICPGA_P (PAGE_1 + 52)
421 #define L_MICPGA_N (PAGE_1 + 54)
422 #define R_MICPGA_P (PAGE_1 + 55)
423 #define R_MICPGA_N (PAGE_1 + 57)
425 /****************************************************************************/
426 /****************************************************************************/
427 #define BIT7 (1 << 7)
428 #define BIT6 (1 << 6)
429 #define BIT5 (1 << 5)
430 #define BIT4 (1 << 4)
431 #define BIT3 (1 << 3)
432 #define BIT2 (1 << 2)
433 #define BIT1 (1 << 1)
434 #define BIT0 (1 << 0)
436 #define HP_UNMUTE BIT2 /*Mistral: Kept for compatibility*/
437 #define HPL_UNMUTE BIT3
438 #define ENABLE_DAC_CHN BIT7 /*Mistral reg [0][63] only right DAC is present*/
439 #define ENABLE_ADC_CHN (BIT6 | BIT7)
440 #define BCLK_DIR_CTRL (BIT2 | BIT3)
441 #define CODEC_CLKIN_MASK 0x03
442 #define MCLK_2_CODEC_CLKIN 0x00
443 #define CODEC_MUX_VALUE 0X03
444 /*Bclk_in selection*/
445 #define BDIV_CLKIN_MASK 0x03
446 #define DAC_MOD_CLK_2_BDIV_CLKIN BIT0
447 #define SOFT_RESET 0x01
450 #define BIT_CLK_MASTER BIT3
451 #define WORD_CLK_MASTER BIT2
452 #define HIGH_PLL BIT6
453 #define ENABLE_PLL BIT7
454 #define ENABLE_NDAC BIT7
455 #define ENABLE_MDAC BIT7
456 #define ENABLE_NADC BIT7
457 #define ENABLE_MADC BIT7
458 #define ENABLE_BCLK BIT7
459 #define LDAC_2_LCHN BIT4
460 /*Mistral: RDAC_2_LCHN...Removed as its reserved*/
461 #define RDAC_2_RAMP BIT2 /*Mistral: kept for compatibility*/
462 #define LDAC_2_LAMP BIT6
463 #define LDAC_CHNL_2_HPL BIT3
464 #define SOFT_STEP_2WCLK BIT0
466 #define DEFAULT_VOL 0x0
467 #define DISABLE_ANALOG BIT3
468 #define LDAC_2_HPL_ROUTEON BIT3
469 /*#define RDAC_2_HPR_ROUTEON BIT3*/ /*Mistral: NOT present in AIC3120*/
470 #define LINEIN_L_2_LMICPGA_10K BIT6
471 #define LINEIN_L_2_LMICPGA_20K BIT7
472 #define LINEIN_L_2_LMICPGA_40K (0x3 << 6)
473 #define LINEIN_R_2_RMICPGA_10K BIT6
474 #define LINEIN_R_2_RMICPGA_20K BIT7
475 #define LINEIN_R_2_RMICPGA_40K (0x3 << 6)
478 /****************************************************************************
479 * DAPM widget related #defines
480 ***************************************************************************
483 /*#define RMUTE_ENUM 1*/ /*Mistral: NOT Present in AIC3120*/
484 #define DACEXTRA_ENUM 2
485 #define DACCONTROL_ENUM 3
486 #define SOFTSTEP_ENUM 4
487 /*#define BEEP_ENUM 5*/ /*Mistral: not present in AIC3120*/
488 #define MICBIAS_ENUM 6
489 #define DACLEFTIP_ENUM 7
490 #define DACRIGHTIP_ENUM 8
491 #define VOLTAGE_ENUM 9
494 #define MIC1LP_ENUM 12
495 #define MIC1RP_ENUM 13
496 #define MIC1LM_ENUM 14
499 #define MIC1LMM_ENUM 17
503 #define ADCMUTE_ENUM 21
507 /*****************************************************************************
508 * Structures Definitions
509 *****************************************************************************
512 *----------------------------------------------------------------------------
513 * @struct aic3111_setup_data |
514 * i2c specific data setup for AIC3111.
515 * @field unsigned short |i2c_address |
516 * Unsigned short for i2c address.
517 *----------------------------------------------------------------------------
519 struct aic3111_setup_data
521 unsigned short i2c_address;
525 *----------------------------------------------------------------------------
526 * @struct aic3111_priv |
527 * AIC3111 priviate data structure to set the system clock, mode and
529 * @field u32 | sysclk |
531 * @field s32 | master |
532 * master/slave mode setting for AIC3111
533 * @field u8 | page_no |
534 * page number. Here, page 0 and page 1 are used.
535 *----------------------------------------------------------------------------
545 *----------------------------------------------------------------------------
546 * @struct aic3111_configs |
547 * AIC3111 initialization data which has register offset and register
549 * @field u16 | reg_offset |
550 * AIC3111 Register offsets required for initialization..
551 * @field u8 | reg_val |
552 * value to set the AIC3111 register to initialize the AIC3111.
553 *----------------------------------------------------------------------------
555 struct aic3111_configs
562 *----------------------------------------------------------------------------
563 * @struct aic3111_rate_divs |
564 * Setting up the values to get different freqencies
566 * @field u32 | mclk |
568 * @field u32 | rate |
570 * @field u8 | p_val |
572 * @field u32 | pll_j |
574 * @field u32 | pll_d |
576 * @field u32 | dosr |
577 * value to store dosr
578 * @field u32 | ndac |
580 * @field u32 | mdac |
582 * @field u32 | aosr |
584 * @field u32 | nadc |
586 * @field u32 | madc |
588 * @field u32 | blck_N |
590 * @field u32 | aic3111_configs |
591 * configurations for aic3111 register value
592 *----------------------------------------------------------------------------
594 struct aic3111_rate_divs
608 struct aic3111_configs codec_specific_regs[NO_FEATURE_REGS];
612 *----------------------------------------------------------------------------
613 * @struct snd_soc_codec_dai |
614 * It is SoC Codec DAI structure which has DAI capabilities viz.,
615 * playback and capture, DAI runtime information viz. state of DAI
616 * and pop wait state, and DAI private data.
617 *----------------------------------------------------------------------------
619 extern struct snd_soc_dai tlv320aic3111_dai;
621 #endif /* _TLV320AIC3111_H */