sound/soc/codecs/tlv320dac33.c

   1 /*
   2  * ALSA SoC Texas Instruments TLV320DAC33 codec driver
   3  *
   4  * Author:      Peter Ujfalusi <peter.ujfalusi@nokia.com>
   5  *
   6  * Copyright:   (C) 2009 Nokia Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/pm.h>
  29 #include <linux/i2c.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/gpio.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/slab.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/soc.h>
  39 #include <sound/initval.h>
  40 #include <sound/tlv.h>
  41
  42 #include <sound/tlv320dac33-plat.h>
  43 #include "tlv320dac33.h"
  44
  45 /*
  46  * The internal FIFO is 24576 bytes long
  47  * It can be configured to hold 16bit or 24bit samples
  48  * In 16bit configuration the FIFO can hold 6144 stereo samples
  49  * In 24bit configuration the FIFO can hold 4096 stereo samples
  50  */
  51 #define DAC33_FIFO_SIZE_16BIT   6144
  52 #define DAC33_FIFO_SIZE_24BIT   4096
  53 #define DAC33_MODE7_MARGIN      10      /* Safety margin for FIFO in Mode7 */
  54
  55 #define BURST_BASEFREQ_HZ       49152000
  56
  57 #define SAMPLES_TO_US(rate, samples) \
  58         (1000000000 / ((rate * 1000) / samples))
  59
  60 #define US_TO_SAMPLES(rate, us) \
  61         (rate / (1000000 / (us < 1000000 ? us : 1000000)))
  62
  63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
  64         ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
  65
  66 static void dac33_calculate_times(struct snd_pcm_substream *substream);
  67 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
  68
  69 enum dac33_state {
  70         DAC33_IDLE = 0,
  71         DAC33_PREFILL,
  72         DAC33_PLAYBACK,
  73         DAC33_FLUSH,
  74 };
  75
  76 enum dac33_fifo_modes {
  77         DAC33_FIFO_BYPASS = 0,
  78         DAC33_FIFO_MODE1,
  79         DAC33_FIFO_MODE7,
  80         DAC33_FIFO_LAST_MODE,
  81 };
  82
  83 #define DAC33_NUM_SUPPLIES 3
  84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
  85         "AVDD",
  86         "DVDD",
  87         "IOVDD",
  88 };
  89
  90 struct tlv320dac33_priv {
  91         struct mutex mutex;
  92         struct workqueue_struct *dac33_wq;
  93         struct work_struct work;
  94         struct snd_soc_codec *codec;
  95         struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
  96         struct snd_pcm_substream *substream;
  97         int power_gpio;
  98         int chip_power;
  99         int irq;
 100         unsigned int refclk;
 101
 102         unsigned int alarm_threshold;   /* set to be half of LATENCY_TIME_MS */
 103         enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
 104         unsigned int fifo_size;         /* Size of the FIFO in samples */
 105         unsigned int nsample;           /* burst read amount from host */
 106         int mode1_latency;              /* latency caused by the i2c writes in
 107                                          * us */
 108         u8 burst_bclkdiv;               /* BCLK divider value in burst mode */
 109         unsigned int burst_rate;        /* Interface speed in Burst modes */
 110
 111         int keep_bclk;                  /* Keep the BCLK continuously running
 112                                          * in FIFO modes */
 113         spinlock_t lock;
 114         unsigned long long t_stamp1;    /* Time stamp for FIFO modes to */
 115         unsigned long long t_stamp2;    /* calculate the FIFO caused delay */
 116
 117         unsigned int mode1_us_burst;    /* Time to burst read n number of
 118                                          * samples */
 119         unsigned int mode7_us_to_lthr;  /* Time to reach lthr from uthr */
 120
 121         unsigned int uthr;
 122
 123         enum dac33_state state;
 124         enum snd_soc_control_type control_type;
 125         void *control_data;
 126 };
 127
 128 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
 129 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
 130 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
 131 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
 132 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
 133 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
 134 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
 135 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
 136 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
 137 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
 138 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
 139 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
 140 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
 141 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
 142 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
 143 0x00, 0x00,             /* 0x38 - 0x39 */
 144 /* Registers 0x3a - 0x3f are reserved  */
 145             0x00, 0x00, /* 0x3a - 0x3b */
 146 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
 147
 148 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
 149 0x00, 0x80,             /* 0x44 - 0x45 */
 150 /* Registers 0x46 - 0x47 are reserved  */
 151             0x80, 0x80, /* 0x46 - 0x47 */
 152
 153 0x80, 0x00, 0x00,       /* 0x48 - 0x4a */
 154 /* Registers 0x4b - 0x7c are reserved  */
 155                   0x00, /* 0x4b        */
 156 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
 157 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
 158 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
 159 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
 160 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
 161 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
 162 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
 163 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
 164 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
 165 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
 166 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
 167 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
 168 0x00,                   /* 0x7c        */
 169
 170       0xda, 0x33, 0x03, /* 0x7d - 0x7f */
 171 };
 172
 173 /* Register read and write */
 174 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
 175                                                 unsigned reg)
 176 {
 177         u8 *cache = codec->reg_cache;
 178         if (reg >= DAC33_CACHEREGNUM)
 179                 return 0;
 180
 181         return cache[reg];
 182 }
 183
 184 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
 185                                          u8 reg, u8 value)
 186 {
 187         u8 *cache = codec->reg_cache;
 188         if (reg >= DAC33_CACHEREGNUM)
 189                 return;
 190
 191         cache[reg] = value;
 192 }
 193
 194 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
 195                       u8 *value)
 196 {
 197         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 198         int val, ret = 0;
 199
 200         *value = reg & 0xff;
 201
 202         /* If powered off, return the cached value */
 203         if (dac33->chip_power) {
 204                 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
 205                 if (val < 0) {
 206                         dev_err(codec->dev, "Read failed (%d)\n", val);
 207                         value[0] = dac33_read_reg_cache(codec, reg);
 208                         ret = val;
 209                 } else {
 210                         value[0] = val;
 211                         dac33_write_reg_cache(codec, reg, val);
 212                 }
 213         } else {
 214                 value[0] = dac33_read_reg_cache(codec, reg);
 215         }
 216
 217         return ret;
 218 }
 219
 220 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
 221                        unsigned int value)
 222 {
 223         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 224         u8 data[2];
 225         int ret = 0;
 226
 227         /*
 228          * data is
 229          *   D15..D8 dac33 register offset
 230          *   D7...D0 register data
 231          */
 232         data[0] = reg & 0xff;
 233         data[1] = value & 0xff;
 234
 235         dac33_write_reg_cache(codec, data[0], data[1]);
 236         if (dac33->chip_power) {
 237                 ret = codec->hw_write(codec->control_data, data, 2);
 238                 if (ret != 2)
 239                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 240                 else
 241                         ret = 0;
 242         }
 243
 244         return ret;
 245 }
 246
 247 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
 248                        unsigned int value)
 249 {
 250         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 251         int ret;
 252
 253         mutex_lock(&dac33->mutex);
 254         ret = dac33_write(codec, reg, value);
 255         mutex_unlock(&dac33->mutex);
 256
 257         return ret;
 258 }
 259
 260 #define DAC33_I2C_ADDR_AUTOINC  0x80
 261 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
 262                        unsigned int value)
 263 {
 264         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 265         u8 data[3];
 266         int ret = 0;
 267
 268         /*
 269          * data is
 270          *   D23..D16 dac33 register offset
 271          *   D15..D8  register data MSB
 272          *   D7...D0  register data LSB
 273          */
 274         data[0] = reg & 0xff;
 275         data[1] = (value >> 8) & 0xff;
 276         data[2] = value & 0xff;
 277
 278         dac33_write_reg_cache(codec, data[0], data[1]);
 279         dac33_write_reg_cache(codec, data[0] + 1, data[2]);
 280
 281         if (dac33->chip_power) {
 282                 /* We need to set autoincrement mode for 16 bit writes */
 283                 data[0] |= DAC33_I2C_ADDR_AUTOINC;
 284                 ret = codec->hw_write(codec->control_data, data, 3);
 285                 if (ret != 3)
 286                         dev_err(codec->dev, "Write failed (%d)\n", ret);
 287                 else
 288                         ret = 0;
 289         }
 290
 291         return ret;
 292 }
 293
 294 static void dac33_init_chip(struct snd_soc_codec *codec)
 295 {
 296         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 297
 298         if (unlikely(!dac33->chip_power))
 299                 return;
 300
 301         /* 44-46: DAC Control Registers */
 302         /* A : DAC sample rate Fsref/1.5 */
 303         dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
 304         /* B : DAC src=normal, not muted */
 305         dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
 306                                              DAC33_DACSRCL_LEFT);
 307         /* C : (defaults) */
 308         dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
 309
 310         /* 73 : volume soft stepping control,
 311          clock source = internal osc (?) */
 312         dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
 313
 314         /* Restore only selected registers (gains mostly) */
 315         dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
 316                     dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
 317         dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
 318                     dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
 319
 320         dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
 321                     dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
 322         dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
 323                     dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
 324 }
 325
 326 static inline int dac33_read_id(struct snd_soc_codec *codec)
 327 {
 328         int i, ret = 0;
 329         u8 reg;
 330
 331         for (i = 0; i < 3; i++) {
 332                 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, &reg);
 333                 if (ret < 0)
 334                         break;
 335         }
 336
 337         return ret;
 338 }
 339
 340 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
 341 {
 342         u8 reg;
 343
 344         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 345         if (power)
 346                 reg |= DAC33_PDNALLB;
 347         else
 348                 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
 349                          DAC33_DACRPDNB | DAC33_DACLPDNB);
 350         dac33_write(codec, DAC33_PWR_CTRL, reg);
 351 }
 352
 353 static inline void dac33_disable_digital(struct snd_soc_codec *codec)
 354 {
 355         u8 reg;
 356
 357         /* Stop the DAI clock */
 358         reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 359         reg &= ~DAC33_BCLKON;
 360         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg);
 361
 362         /* Power down the Oscillator, and DACs */
 363         reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 364         reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
 365         dac33_write(codec, DAC33_PWR_CTRL, reg);
 366 }
 367
 368 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
 369 {
 370         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 371         int ret = 0;
 372
 373         mutex_lock(&dac33->mutex);
 374
 375         /* Safety check */
 376         if (unlikely(power == dac33->chip_power)) {
 377                 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
 378                         power ? "ON" : "OFF");
 379                 goto exit;
 380         }
 381
 382         if (power) {
 383                 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
 384                                           dac33->supplies);
 385                 if (ret != 0) {
 386                         dev_err(codec->dev,
 387                                 "Failed to enable supplies: %d\n", ret);
 388                                 goto exit;
 389                 }
 390
 391                 if (dac33->power_gpio >= 0)
 392                         gpio_set_value(dac33->power_gpio, 1);
 393
 394                 dac33->chip_power = 1;
 395         } else {
 396                 dac33_soft_power(codec, 0);
 397                 if (dac33->power_gpio >= 0)
 398                         gpio_set_value(dac33->power_gpio, 0);
 399
 400                 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
 401                                              dac33->supplies);
 402                 if (ret != 0) {
 403                         dev_err(codec->dev,
 404                                 "Failed to disable supplies: %d\n", ret);
 405                         goto exit;
 406                 }
 407
 408                 dac33->chip_power = 0;
 409         }
 410
 411 exit:
 412         mutex_unlock(&dac33->mutex);
 413         return ret;
 414 }
 415
 416 static int dac33_playback_event(struct snd_soc_dapm_widget *w,
 417                 struct snd_kcontrol *kcontrol, int event)
 418 {
 419         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
 420
 421         switch (event) {
 422         case SND_SOC_DAPM_PRE_PMU:
 423                 if (likely(dac33->substream)) {
 424                         dac33_calculate_times(dac33->substream);
 425                         dac33_prepare_chip(dac33->substream);
 426                 }
 427                 break;
 428         case SND_SOC_DAPM_POST_PMD:
 429                 dac33_disable_digital(w->codec);
 430                 break;
 431         }
 432         return 0;
 433 }
 434
 435 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
 436                          struct snd_ctl_elem_value *ucontrol)
 437 {
 438         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 439         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 440
 441         ucontrol->value.integer.value[0] = dac33->fifo_mode;
 442
 443         return 0;
 444 }
 445
 446 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
 447                          struct snd_ctl_elem_value *ucontrol)
 448 {
 449         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 450         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 451         int ret = 0;
 452
 453         if (dac33->fifo_mode == ucontrol->value.integer.value[0])
 454                 return 0;
 455         /* Do not allow changes while stream is running*/
 456         if (codec->active)
 457                 return -EPERM;
 458
 459         if (ucontrol->value.integer.value[0] < 0 ||
 460             ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
 461                 ret = -EINVAL;
 462         else
 463                 dac33->fifo_mode = ucontrol->value.integer.value[0];
 464
 465         return ret;
 466 }
 467
 468 /* Codec operation modes */
 469 static const char *dac33_fifo_mode_texts[] = {
 470         "Bypass", "Mode 1", "Mode 7"
 471 };
 472
 473 static const struct soc_enum dac33_fifo_mode_enum =
 474         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
 475                             dac33_fifo_mode_texts);
 476
 477 /* L/R Line Output Gain */
 478 static const char *lr_lineout_gain_texts[] = {
 479         "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
 480         "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
 481 };
 482
 483 static const struct soc_enum l_lineout_gain_enum =
 484         SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
 485                         ARRAY_SIZE(lr_lineout_gain_texts),
 486                         lr_lineout_gain_texts);
 487
 488 static const struct soc_enum r_lineout_gain_enum =
 489         SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
 490                         ARRAY_SIZE(lr_lineout_gain_texts),
 491                         lr_lineout_gain_texts);
 492
 493 /*
 494  * DACL/R digital volume control:
 495  * from 0 dB to -63.5 in 0.5 dB steps
 496  * Need to be inverted later on:
 497  * 0x00 == 0 dB
 498  * 0x7f == -63.5 dB
 499  */
 500 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
 501
 502 static const struct snd_kcontrol_new dac33_snd_controls[] = {
 503         SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
 504                 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
 505                 0, 0x7f, 1, dac_digivol_tlv),
 506         SOC_DOUBLE_R("DAC Digital Playback Switch",
 507                  DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
 508         SOC_DOUBLE_R("Line to Line Out Volume",
 509                  DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
 510         SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
 511         SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
 512 };
 513
 514 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
 515         SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
 516                  dac33_get_fifo_mode, dac33_set_fifo_mode),
 517 };
 518
 519 /* Analog bypass */
 520 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
 521         SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
 522
 523 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
 524         SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
 525
 526 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
 527         SND_SOC_DAPM_OUTPUT("LEFT_LO"),
 528         SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
 529
 530         SND_SOC_DAPM_INPUT("LINEL"),
 531         SND_SOC_DAPM_INPUT("LINER"),
 532
 533         SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0),
 534         SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0),
 535
 536         /* Analog bypass */
 537         SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
 538                                 &dac33_dapm_abypassl_control),
 539         SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
 540                                 &dac33_dapm_abypassr_control),
 541
 542         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier",
 543                          DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
 544         SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier",
 545                          DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
 546
 547         SND_SOC_DAPM_SUPPLY("Left DAC Power",
 548                             DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0),
 549         SND_SOC_DAPM_SUPPLY("Right DAC Power",
 550                             DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0),
 551
 552         SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event),
 553         SND_SOC_DAPM_POST("Post Playback", dac33_playback_event),
 554 };
 555
 556 static const struct snd_soc_dapm_route audio_map[] = {
 557         /* Analog bypass */
 558         {"Analog Left Bypass", "Switch", "LINEL"},
 559         {"Analog Right Bypass", "Switch", "LINER"},
 560
 561         {"Output Left Amplifier", NULL, "DACL"},
 562         {"Output Right Amplifier", NULL, "DACR"},
 563
 564         {"Output Left Amplifier", NULL, "Analog Left Bypass"},
 565         {"Output Right Amplifier", NULL, "Analog Right Bypass"},
 566
 567         {"Output Left Amplifier", NULL, "Left DAC Power"},
 568         {"Output Right Amplifier", NULL, "Right DAC Power"},
 569
 570         /* output */
 571         {"LEFT_LO", NULL, "Output Left Amplifier"},
 572         {"RIGHT_LO", NULL, "Output Right Amplifier"},
 573 };
 574
 575 static int dac33_add_widgets(struct snd_soc_codec *codec)
 576 {
 577         struct snd_soc_dapm_context *dapm = &codec->dapm;
 578
 579         snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets,
 580                                   ARRAY_SIZE(dac33_dapm_widgets));
 581         /* set up audio path interconnects */
 582         snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
 583
 584         return 0;
 585 }
 586
 587 static int dac33_set_bias_level(struct snd_soc_codec *codec,
 588                                 enum snd_soc_bias_level level)
 589 {
 590         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 591         int ret;
 592
 593         switch (level) {
 594         case SND_SOC_BIAS_ON:
 595                 if (!dac33->substream)
 596                         dac33_soft_power(codec, 1);
 597                 break;
 598         case SND_SOC_BIAS_PREPARE:
 599                 break;
 600         case SND_SOC_BIAS_STANDBY:
 601                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
 602                         /* Coming from OFF, switch on the codec */
 603                         ret = dac33_hard_power(codec, 1);
 604                         if (ret != 0)
 605                                 return ret;
 606
 607                         dac33_init_chip(codec);
 608                 }
 609                 break;
 610         case SND_SOC_BIAS_OFF:
 611                 /* Do not power off, when the codec is already off */
 612                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
 613                         return 0;
 614                 ret = dac33_hard_power(codec, 0);
 615                 if (ret != 0)
 616                         return ret;
 617                 break;
 618         }
 619         codec->dapm.bias_level = level;
 620
 621         return 0;
 622 }
 623
 624 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
 625 {
 626         struct snd_soc_codec *codec = dac33->codec;
 627         unsigned int delay;
 628
 629         switch (dac33->fifo_mode) {
 630         case DAC33_FIFO_MODE1:
 631                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 632                         DAC33_THRREG(dac33->nsample));
 633
 634                 /* Take the timestamps */
 635                 spin_lock_irq(&dac33->lock);
 636                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 637                 dac33->t_stamp1 = dac33->t_stamp2;
 638                 spin_unlock_irq(&dac33->lock);
 639
 640                 dac33_write16(codec, DAC33_PREFILL_MSB,
 641                                 DAC33_THRREG(dac33->alarm_threshold));
 642                 /* Enable Alarm Threshold IRQ with a delay */
 643                 delay = SAMPLES_TO_US(dac33->burst_rate,
 644                                      dac33->alarm_threshold) + 1000;
 645                 usleep_range(delay, delay + 500);
 646                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
 647                 break;
 648         case DAC33_FIFO_MODE7:
 649                 /* Take the timestamp */
 650                 spin_lock_irq(&dac33->lock);
 651                 dac33->t_stamp1 = ktime_to_us(ktime_get());
 652                 /* Move back the timestamp with drain time */
 653                 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
 654                 spin_unlock_irq(&dac33->lock);
 655
 656                 dac33_write16(codec, DAC33_PREFILL_MSB,
 657                                 DAC33_THRREG(DAC33_MODE7_MARGIN));
 658
 659                 /* Enable Upper Threshold IRQ */
 660                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
 661                 break;
 662         default:
 663                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 664                                                         dac33->fifo_mode);
 665                 break;
 666         }
 667 }
 668
 669 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
 670 {
 671         struct snd_soc_codec *codec = dac33->codec;
 672
 673         switch (dac33->fifo_mode) {
 674         case DAC33_FIFO_MODE1:
 675                 /* Take the timestamp */
 676                 spin_lock_irq(&dac33->lock);
 677                 dac33->t_stamp2 = ktime_to_us(ktime_get());
 678                 spin_unlock_irq(&dac33->lock);
 679
 680                 dac33_write16(codec, DAC33_NSAMPLE_MSB,
 681                                 DAC33_THRREG(dac33->nsample));
 682                 break;
 683         case DAC33_FIFO_MODE7:
 684                 /* At the moment we are not using interrupts in mode7 */
 685                 break;
 686         default:
 687                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
 688                                                         dac33->fifo_mode);
 689                 break;
 690         }
 691 }
 692
 693 static void dac33_work(struct work_struct *work)
 694 {
 695         struct snd_soc_codec *codec;
 696         struct tlv320dac33_priv *dac33;
 697         u8 reg;
 698
 699         dac33 = container_of(work, struct tlv320dac33_priv, work);
 700         codec = dac33->codec;
 701
 702         mutex_lock(&dac33->mutex);
 703         switch (dac33->state) {
 704         case DAC33_PREFILL:
 705                 dac33->state = DAC33_PLAYBACK;
 706                 dac33_prefill_handler(dac33);
 707                 break;
 708         case DAC33_PLAYBACK:
 709                 dac33_playback_handler(dac33);
 710                 break;
 711         case DAC33_IDLE:
 712                 break;
 713         case DAC33_FLUSH:
 714                 dac33->state = DAC33_IDLE;
 715                 /* Mask all interrupts from dac33 */
 716                 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
 717
 718                 /* flush fifo */
 719                 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 720                 reg |= DAC33_FIFOFLUSH;
 721                 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
 722                 break;
 723         }
 724         mutex_unlock(&dac33->mutex);
 725 }
 726
 727 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
 728 {
 729         struct snd_soc_codec *codec = dev;
 730         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 731
 732         spin_lock(&dac33->lock);
 733         dac33->t_stamp1 = ktime_to_us(ktime_get());
 734         spin_unlock(&dac33->lock);
 735
 736         /* Do not schedule the workqueue in Mode7 */
 737         if (dac33->fifo_mode != DAC33_FIFO_MODE7)
 738                 queue_work(dac33->dac33_wq, &dac33->work);
 739
 740         return IRQ_HANDLED;
 741 }
 742
 743 static void dac33_oscwait(struct snd_soc_codec *codec)
 744 {
 745         int timeout = 60;
 746         u8 reg;
 747
 748         do {
 749                 usleep_range(1000, 2000);
 750                 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
 751         } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
 752         if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
 753                 dev_err(codec->dev,
 754                         "internal oscillator calibration failed\n");
 755 }
 756
 757 static int dac33_startup(struct snd_pcm_substream *substream,
 758                            struct snd_soc_dai *dai)
 759 {
 760         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 761         struct snd_soc_codec *codec = rtd->codec;
 762         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 763
 764         /* Stream started, save the substream pointer */
 765         dac33->substream = substream;
 766
 767         return 0;
 768 }
 769
 770 static void dac33_shutdown(struct snd_pcm_substream *substream,
 771                              struct snd_soc_dai *dai)
 772 {
 773         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 774         struct snd_soc_codec *codec = rtd->codec;
 775         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 776
 777         dac33->substream = NULL;
 778 }
 779
 780 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \
 781         (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample)
 782 static int dac33_hw_params(struct snd_pcm_substream *substream,
 783                            struct snd_pcm_hw_params *params,
 784                            struct snd_soc_dai *dai)
 785 {
 786         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 787         struct snd_soc_codec *codec = rtd->codec;
 788         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 789
 790         /* Check parameters for validity */
 791         switch (params_rate(params)) {
 792         case 44100:
 793         case 48000:
 794                 break;
 795         default:
 796                 dev_err(codec->dev, "unsupported rate %d\n",
 797                         params_rate(params));
 798                 return -EINVAL;
 799         }
 800
 801         switch (params_format(params)) {
 802         case SNDRV_PCM_FORMAT_S16_LE:
 803                 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT;
 804                 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32);
 805                 break;
 806         default:
 807                 dev_err(codec->dev, "unsupported format %d\n",
 808                         params_format(params));
 809                 return -EINVAL;
 810         }
 811
 812         return 0;
 813 }
 814
 815 #define CALC_OSCSET(rate, refclk) ( \
 816         ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
 817 #define CALC_RATIOSET(rate, refclk) ( \
 818         ((((refclk  * 100000) / rate) * 16384) + 50000) / 100000)
 819
 820 /*
 821  * tlv320dac33 is strict on the sequence of the register writes, if the register
 822  * writes happens in different order, than dac33 might end up in unknown state.
 823  * Use the known, working sequence of register writes to initialize the dac33.
 824  */
 825 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
 826 {
 827         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 828         struct snd_soc_codec *codec = rtd->codec;
 829         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
 830         unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
 831         u8 aictrl_a, aictrl_b, fifoctrl_a;
 832
 833         switch (substream->runtime->rate) {
 834         case 44100:
 835         case 48000:
 836                 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
 837                 ratioset = CALC_RATIOSET(substream->runtime->rate,
 838                                          dac33->refclk);
 839                 break;
 840         default:
 841                 dev_err(codec->dev, "unsupported rate %d\n",
 842                         substream->runtime->rate);
 843                 return -EINVAL;
 844         }
 845
 846
 847         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
 848         aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
 849         /* Read FIFO control A, and clear FIFO flush bit */
 850         fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
 851         fifoctrl_a &= ~DAC33_FIFOFLUSH;
 852
 853         fifoctrl_a &= ~DAC33_WIDTH;
 854         switch (substream->runtime->format) {
 855         case SNDRV_PCM_FORMAT_S16_LE:
 856                 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
 857                 fifoctrl_a |= DAC33_WIDTH;
 858                 break;
 859         default:
 860                 dev_err(codec->dev, "unsupported format %d\n",
 861                         substream->runtime->format);
 862                 return -EINVAL;
 863         }
 864
 865         mutex_lock(&dac33->mutex);
 866
 867         if (!dac33->chip_power) {
 868                 /*
 869                  * Chip is not powered yet.
 870                  * Do the init in the dac33_set_bias_level later.
 871                  */
 872                 mutex_unlock(&dac33->mutex);
 873                 return 0;
 874         }
 875
 876         dac33_soft_power(codec, 0);
 877         dac33_soft_power(codec, 1);
 878
 879         reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
 880         dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
 881
 882         /* Write registers 0x08 and 0x09 (MSB, LSB) */
 883         dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
 884
 885         /* calib time: 128 is a nice number ;) */
 886         dac33_write(codec, DAC33_CALIB_TIME, 128);
 887
 888         /* adjustment treshold & step */
 889         dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
 890                                                  DAC33_ADJSTEP(1));
 891
 892         /* div=4 / gain=1 / div */
 893         dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
 894
 895         pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
 896         pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
 897         dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
 898
 899         dac33_oscwait(codec);
 900
 901         if (dac33->fifo_mode) {
 902                 /* Generic for all FIFO modes */
 903                 /* 50-51 : ASRC Control registers */
 904                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
 905                 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
 906
 907                 /* Write registers 0x34 and 0x35 (MSB, LSB) */
 908                 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
 909
 910                 /* Set interrupts to high active */
 911                 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
 912         } else {
 913                 /* FIFO bypass mode */
 914                 /* 50-51 : ASRC Control registers */
 915                 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
 916                 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
 917         }
 918
 919         /* Interrupt behaviour configuration */
 920         switch (dac33->fifo_mode) {
 921         case DAC33_FIFO_MODE1:
 922                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
 923                             DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
 924                 break;
 925         case DAC33_FIFO_MODE7:
 926                 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
 927                         DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
 928                 break;
 929         default:
 930                 /* in FIFO bypass mode, the interrupts are not used */
 931                 break;
 932         }
 933
 934         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
 935
 936         switch (dac33->fifo_mode) {
 937         case DAC33_FIFO_MODE1:
 938                 /*
 939                  * For mode1:
 940                  * Disable the FIFO bypass (Enable the use of FIFO)
 941                  * Select nSample mode
 942                  * BCLK is only running when data is needed by DAC33
 943                  */
 944                 fifoctrl_a &= ~DAC33_FBYPAS;
 945                 fifoctrl_a &= ~DAC33_FAUTO;
 946                 if (dac33->keep_bclk)
 947                         aictrl_b |= DAC33_BCLKON;
 948                 else
 949                         aictrl_b &= ~DAC33_BCLKON;
 950                 break;
 951         case DAC33_FIFO_MODE7:
 952                 /*
 953                  * For mode1:
 954                  * Disable the FIFO bypass (Enable the use of FIFO)
 955                  * Select Threshold mode
 956                  * BCLK is only running when data is needed by DAC33
 957                  */
 958                 fifoctrl_a &= ~DAC33_FBYPAS;
 959                 fifoctrl_a |= DAC33_FAUTO;
 960                 if (dac33->keep_bclk)
 961                         aictrl_b |= DAC33_BCLKON;
 962                 else
 963                         aictrl_b &= ~DAC33_BCLKON;
 964                 break;
 965         default:
 966                 /*
 967                  * For FIFO bypass mode:
 968                  * Enable the FIFO bypass (Disable the FIFO use)
 969                  * Set the BCLK as continous
 970                  */
 971                 fifoctrl_a |= DAC33_FBYPAS;
 972                 aictrl_b |= DAC33_BCLKON;
 973                 break;
 974         }
 975
 976         dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
 977         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
 978         dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
 979
 980         /*
 981          * BCLK divide ratio
 982          * 0: 1.5
 983          * 1: 1
 984          * 2: 2
 985          * ...
 986          * 254: 254
 987          * 255: 255
 988          */
 989         if (dac33->fifo_mode)
 990                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
 991                                                         dac33->burst_bclkdiv);
 992         else
 993                 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
 994
 995         switch (dac33->fifo_mode) {
 996         case DAC33_FIFO_MODE1:
 997                 dac33_write16(codec, DAC33_ATHR_MSB,
 998                               DAC33_THRREG(dac33->alarm_threshold));
 999                 break;
1000         case DAC33_FIFO_MODE7:
1001                 /*
1002                  * Configure the threshold levels, and leave 10 sample space
1003                  * at the bottom, and also at the top of the FIFO
1004                  */
1005                 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1006                 dac33_write16(codec, DAC33_LTHR_MSB,
1007                               DAC33_THRREG(DAC33_MODE7_MARGIN));
1008                 break;
1009         default:
1010                 break;
1011         }
1012
1013         mutex_unlock(&dac33->mutex);
1014
1015         return 0;
1016 }
1017
1018 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1019 {
1020         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1021         struct snd_soc_codec *codec = rtd->codec;
1022         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1023         unsigned int period_size = substream->runtime->period_size;
1024         unsigned int rate = substream->runtime->rate;
1025         unsigned int nsample_limit;
1026
1027         /* In bypass mode we don't need to calculate */
1028         if (!dac33->fifo_mode)
1029                 return;
1030
1031         switch (dac33->fifo_mode) {
1032         case DAC33_FIFO_MODE1:
1033                 /* Number of samples under i2c latency */
1034                 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1035                                                 dac33->mode1_latency);
1036                 nsample_limit = dac33->fifo_size - dac33->alarm_threshold;
1037
1038                 if (period_size <= dac33->alarm_threshold)
1039                         /*
1040                          * Configure nSamaple to number of periods,
1041                          * which covers the latency requironment.
1042                          */
1043                         dac33->nsample = period_size *
1044                                 ((dac33->alarm_threshold / period_size) +
1045                                 (dac33->alarm_threshold % period_size ?
1046                                 1 : 0));
1047                 else if (period_size > nsample_limit)
1048                         dac33->nsample = nsample_limit;
1049                 else
1050                         dac33->nsample = period_size;
1051
1052                 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1053                                                       dac33->nsample);
1054                 dac33->t_stamp1 = 0;
1055                 dac33->t_stamp2 = 0;
1056                 break;
1057         case DAC33_FIFO_MODE7:
1058                 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate,
1059                                                     dac33->burst_rate) + 9;
1060                 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN))
1061                         dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN;
1062                 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10))
1063                         dac33->uthr = (DAC33_MODE7_MARGIN + 10);
1064
1065                 dac33->mode7_us_to_lthr =
1066                                 SAMPLES_TO_US(substream->runtime->rate,
1067                                         dac33->uthr - DAC33_MODE7_MARGIN + 1);
1068                 dac33->t_stamp1 = 0;
1069                 break;
1070         default:
1071                 break;
1072         }
1073
1074 }
1075
1076 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1077                              struct snd_soc_dai *dai)
1078 {
1079         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1080         struct snd_soc_codec *codec = rtd->codec;
1081         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1082         int ret = 0;
1083
1084         switch (cmd) {
1085         case SNDRV_PCM_TRIGGER_START:
1086         case SNDRV_PCM_TRIGGER_RESUME:
1087         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1088                 if (dac33->fifo_mode) {
1089                         dac33->state = DAC33_PREFILL;
1090                         queue_work(dac33->dac33_wq, &dac33->work);
1091                 }
1092                 break;
1093         case SNDRV_PCM_TRIGGER_STOP:
1094         case SNDRV_PCM_TRIGGER_SUSPEND:
1095         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1096                 if (dac33->fifo_mode) {
1097                         dac33->state = DAC33_FLUSH;
1098                         queue_work(dac33->dac33_wq, &dac33->work);
1099                 }
1100                 break;
1101         default:
1102                 ret = -EINVAL;
1103         }
1104
1105         return ret;
1106 }
1107
1108 static snd_pcm_sframes_t dac33_dai_delay(
1109                         struct snd_pcm_substream *substream,
1110                         struct snd_soc_dai *dai)
1111 {
1112         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1113         struct snd_soc_codec *codec = rtd->codec;
1114         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1115         unsigned long long t0, t1, t_now;
1116         unsigned int time_delta, uthr;
1117         int samples_out, samples_in, samples;
1118         snd_pcm_sframes_t delay = 0;
1119
1120         switch (dac33->fifo_mode) {
1121         case DAC33_FIFO_BYPASS:
1122                 break;
1123         case DAC33_FIFO_MODE1:
1124                 spin_lock(&dac33->lock);
1125                 t0 = dac33->t_stamp1;
1126                 t1 = dac33->t_stamp2;
1127                 spin_unlock(&dac33->lock);
1128                 t_now = ktime_to_us(ktime_get());
1129
1130                 /* We have not started to fill the FIFO yet, delay is 0 */
1131                 if (!t1)
1132                         goto out;
1133
1134                 if (t0 > t1) {
1135                         /*
1136                          * Phase 1:
1137                          * After Alarm threshold, and before nSample write
1138                          */
1139                         time_delta = t_now - t0;
1140                         samples_out = time_delta ? US_TO_SAMPLES(
1141                                                 substream->runtime->rate,
1142                                                 time_delta) : 0;
1143
1144                         if (likely(dac33->alarm_threshold > samples_out))
1145                                 delay = dac33->alarm_threshold - samples_out;
1146                         else
1147                                 delay = 0;
1148                 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1149                         /*
1150                          * Phase 2:
1151                          * After nSample write (during burst operation)
1152                          */
1153                         time_delta = t_now - t0;
1154                         samples_out = time_delta ? US_TO_SAMPLES(
1155                                                 substream->runtime->rate,
1156                                                 time_delta) : 0;
1157
1158                         time_delta = t_now - t1;
1159                         samples_in = time_delta ? US_TO_SAMPLES(
1160                                                 dac33->burst_rate,
1161                                                 time_delta) : 0;
1162
1163                         samples = dac33->alarm_threshold;
1164                         samples += (samples_in - samples_out);
1165
1166                         if (likely(samples > 0))
1167                                 delay = samples;
1168                         else
1169                                 delay = 0;
1170                 } else {
1171                         /*
1172                          * Phase 3:
1173                          * After burst operation, before next alarm threshold
1174                          */
1175                         time_delta = t_now - t0;
1176                         samples_out = time_delta ? US_TO_SAMPLES(
1177                                                 substream->runtime->rate,
1178                                                 time_delta) : 0;
1179
1180                         samples_in = dac33->nsample;
1181                         samples = dac33->alarm_threshold;
1182                         samples += (samples_in - samples_out);
1183
1184                         if (likely(samples > 0))
1185                                 delay = samples > dac33->fifo_size ?
1186                                         dac33->fifo_size : samples;
1187                         else
1188                                 delay = 0;
1189                 }
1190                 break;
1191         case DAC33_FIFO_MODE7:
1192                 spin_lock(&dac33->lock);
1193                 t0 = dac33->t_stamp1;
1194                 uthr = dac33->uthr;
1195                 spin_unlock(&dac33->lock);
1196                 t_now = ktime_to_us(ktime_get());
1197
1198                 /* We have not started to fill the FIFO yet, delay is 0 */
1199                 if (!t0)
1200                         goto out;
1201
1202                 if (t_now <= t0) {
1203                         /*
1204                          * Either the timestamps are messed or equal. Report
1205                          * maximum delay
1206                          */
1207                         delay = uthr;
1208                         goto out;
1209                 }
1210
1211                 time_delta = t_now - t0;
1212                 if (time_delta <= dac33->mode7_us_to_lthr) {
1213                         /*
1214                         * Phase 1:
1215                         * After burst (draining phase)
1216                         */
1217                         samples_out = US_TO_SAMPLES(
1218                                         substream->runtime->rate,
1219                                         time_delta);
1220
1221                         if (likely(uthr > samples_out))
1222                                 delay = uthr - samples_out;
1223                         else
1224                                 delay = 0;
1225                 } else {
1226                         /*
1227                         * Phase 2:
1228                         * During burst operation
1229                         */
1230                         time_delta = time_delta - dac33->mode7_us_to_lthr;
1231
1232                         samples_out = US_TO_SAMPLES(
1233                                         substream->runtime->rate,
1234                                         time_delta);
1235                         samples_in = US_TO_SAMPLES(
1236                                         dac33->burst_rate,
1237                                         time_delta);
1238                         delay = DAC33_MODE7_MARGIN + samples_in - samples_out;
1239
1240                         if (unlikely(delay > uthr))
1241                                 delay = uthr;
1242                 }
1243                 break;
1244         default:
1245                 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1246                                                         dac33->fifo_mode);
1247                 break;
1248         }
1249 out:
1250         return delay;
1251 }
1252
1253 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1254                 int clk_id, unsigned int freq, int dir)
1255 {
1256         struct snd_soc_codec *codec = codec_dai->codec;
1257         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1258         u8 ioc_reg, asrcb_reg;
1259
1260         ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1261         asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1262         switch (clk_id) {
1263         case TLV320DAC33_MCLK:
1264                 ioc_reg |= DAC33_REFSEL;
1265                 asrcb_reg |= DAC33_SRCREFSEL;
1266                 break;
1267         case TLV320DAC33_SLEEPCLK:
1268                 ioc_reg &= ~DAC33_REFSEL;
1269                 asrcb_reg &= ~DAC33_SRCREFSEL;
1270                 break;
1271         default:
1272                 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1273                 break;
1274         }
1275         dac33->refclk = freq;
1276
1277         dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1278         dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1279
1280         return 0;
1281 }
1282
1283 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1284                              unsigned int fmt)
1285 {
1286         struct snd_soc_codec *codec = codec_dai->codec;
1287         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1288         u8 aictrl_a, aictrl_b;
1289
1290         aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1291         aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1292         /* set master/slave audio interface */
1293         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1294         case SND_SOC_DAIFMT_CBM_CFM:
1295                 /* Codec Master */
1296                 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1297                 break;
1298         case SND_SOC_DAIFMT_CBS_CFS:
1299                 /* Codec Slave */
1300                 if (dac33->fifo_mode) {
1301                         dev_err(codec->dev, "FIFO mode requires master mode\n");
1302                         return -EINVAL;
1303                 } else
1304                         aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1305                 break;
1306         default:
1307                 return -EINVAL;
1308         }
1309
1310         aictrl_a &= ~DAC33_AFMT_MASK;
1311         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1312         case SND_SOC_DAIFMT_I2S:
1313                 aictrl_a |= DAC33_AFMT_I2S;
1314                 break;
1315         case SND_SOC_DAIFMT_DSP_A:
1316                 aictrl_a |= DAC33_AFMT_DSP;
1317                 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1318                 aictrl_b |= DAC33_DATA_DELAY(0);
1319                 break;
1320         case SND_SOC_DAIFMT_RIGHT_J:
1321                 aictrl_a |= DAC33_AFMT_RIGHT_J;
1322                 break;
1323         case SND_SOC_DAIFMT_LEFT_J:
1324                 aictrl_a |= DAC33_AFMT_LEFT_J;
1325                 break;
1326         default:
1327                 dev_err(codec->dev, "Unsupported format (%u)\n",
1328                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1329                 return -EINVAL;
1330         }
1331
1332         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1333         dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1334
1335         return 0;
1336 }
1337
1338 static int dac33_soc_probe(struct snd_soc_codec *codec)
1339 {
1340         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1341         int ret = 0;
1342
1343         codec->control_data = dac33->control_data;
1344         codec->hw_write = (hw_write_t) i2c_master_send;
1345         codec->dapm.idle_bias_off = 1;
1346         dac33->codec = codec;
1347
1348         /* Read the tlv320dac33 ID registers */
1349         ret = dac33_hard_power(codec, 1);
1350         if (ret != 0) {
1351                 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1352                 goto err_power;
1353         }
1354         ret = dac33_read_id(codec);
1355         dac33_hard_power(codec, 0);
1356
1357         if (ret < 0) {
1358                 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret);
1359                 ret = -ENODEV;
1360                 goto err_power;
1361         }
1362
1363         /* Check if the IRQ number is valid and request it */
1364         if (dac33->irq >= 0) {
1365                 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1366                                   IRQF_TRIGGER_RISING | IRQF_DISABLED,
1367                                   codec->name, codec);
1368                 if (ret < 0) {
1369                         dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1370                                                 dac33->irq, ret);
1371                         dac33->irq = -1;
1372                 }
1373                 if (dac33->irq != -1) {
1374                         /* Setup work queue */
1375                         dac33->dac33_wq =
1376                                 create_singlethread_workqueue("tlv320dac33");
1377                         if (dac33->dac33_wq == NULL) {
1378                                 free_irq(dac33->irq, codec);
1379                                 return -ENOMEM;
1380                         }
1381
1382                         INIT_WORK(&dac33->work, dac33_work);
1383                 }
1384         }
1385
1386         snd_soc_add_controls(codec, dac33_snd_controls,
1387                              ARRAY_SIZE(dac33_snd_controls));
1388         /* Only add the FIFO controls, if we have valid IRQ number */
1389         if (dac33->irq >= 0)
1390                 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1391                                      ARRAY_SIZE(dac33_mode_snd_controls));
1392
1393         dac33_add_widgets(codec);
1394
1395 err_power:
1396         return ret;
1397 }
1398
1399 static int dac33_soc_remove(struct snd_soc_codec *codec)
1400 {
1401         struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1402
1403         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1404
1405         if (dac33->irq >= 0) {
1406                 free_irq(dac33->irq, dac33->codec);
1407                 destroy_workqueue(dac33->dac33_wq);
1408         }
1409         return 0;
1410 }
1411
1412 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
1413 {
1414         dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1415
1416         return 0;
1417 }
1418
1419 static int dac33_soc_resume(struct snd_soc_codec *codec)
1420 {
1421         dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1422
1423         return 0;
1424 }
1425
1426 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1427         .read = dac33_read_reg_cache,
1428         .write = dac33_write_locked,
1429         .set_bias_level = dac33_set_bias_level,
1430         .reg_cache_size = ARRAY_SIZE(dac33_reg),
1431         .reg_word_size = sizeof(u8),
1432         .reg_cache_default = dac33_reg,
1433         .probe = dac33_soc_probe,
1434         .remove = dac33_soc_remove,
1435         .suspend = dac33_soc_suspend,
1436         .resume = dac33_soc_resume,
1437 };
1438
1439 #define DAC33_RATES     (SNDRV_PCM_RATE_44100 | \
1440                          SNDRV_PCM_RATE_48000)
1441 #define DAC33_FORMATS   SNDRV_PCM_FMTBIT_S16_LE
1442
1443 static struct snd_soc_dai_ops dac33_dai_ops = {
1444         .startup        = dac33_startup,
1445         .shutdown       = dac33_shutdown,
1446         .hw_params      = dac33_hw_params,
1447         .trigger        = dac33_pcm_trigger,
1448         .delay          = dac33_dai_delay,
1449         .set_sysclk     = dac33_set_dai_sysclk,
1450         .set_fmt        = dac33_set_dai_fmt,
1451 };
1452
1453 static struct snd_soc_dai_driver dac33_dai = {
1454         .name = "tlv320dac33-hifi",
1455         .playback = {
1456                 .stream_name = "Playback",
1457                 .channels_min = 2,
1458                 .channels_max = 2,
1459                 .rates = DAC33_RATES,
1460                 .formats = DAC33_FORMATS,},
1461         .ops = &dac33_dai_ops,
1462 };
1463
1464 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1465                                      const struct i2c_device_id *id)
1466 {
1467         struct tlv320dac33_platform_data *pdata;
1468         struct tlv320dac33_priv *dac33;
1469         int ret, i;
1470
1471         if (client->dev.platform_data == NULL) {
1472                 dev_err(&client->dev, "Platform data not set\n");
1473                 return -ENODEV;
1474         }
1475         pdata = client->dev.platform_data;
1476
1477         dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1478         if (dac33 == NULL)
1479                 return -ENOMEM;
1480
1481         dac33->control_data = client;
1482         mutex_init(&dac33->mutex);
1483         spin_lock_init(&dac33->lock);
1484
1485         i2c_set_clientdata(client, dac33);
1486
1487         dac33->power_gpio = pdata->power_gpio;
1488         dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1489         dac33->keep_bclk = pdata->keep_bclk;
1490         dac33->mode1_latency = pdata->mode1_latency;
1491         if (!dac33->mode1_latency)
1492                 dac33->mode1_latency = 10000; /* 10ms */
1493         dac33->irq = client->irq;
1494         /* Disable FIFO use by default */
1495         dac33->fifo_mode = DAC33_FIFO_BYPASS;
1496
1497         /* Check if the reset GPIO number is valid and request it */
1498         if (dac33->power_gpio >= 0) {
1499                 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1500                 if (ret < 0) {
1501                         dev_err(&client->dev,
1502                                 "Failed to request reset GPIO (%d)\n",
1503                                 dac33->power_gpio);
1504                         goto err_gpio;
1505                 }
1506                 gpio_direction_output(dac33->power_gpio, 0);
1507         }
1508
1509         for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1510                 dac33->supplies[i].supply = dac33_supply_names[i];
1511
1512         ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1513                                  dac33->supplies);
1514
1515         if (ret != 0) {
1516                 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1517                 goto err_get;
1518         }
1519
1520         ret = snd_soc_register_codec(&client->dev,
1521                         &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1522         if (ret < 0)
1523                 goto err_register;
1524
1525         return ret;
1526 err_register:
1527         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1528 err_get:
1529         if (dac33->power_gpio >= 0)
1530                 gpio_free(dac33->power_gpio);
1531 err_gpio:
1532         kfree(dac33);
1533         return ret;
1534 }
1535
1536 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1537 {
1538         struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1539
1540         if (unlikely(dac33->chip_power))
1541                 dac33_hard_power(dac33->codec, 0);
1542
1543         if (dac33->power_gpio >= 0)
1544                 gpio_free(dac33->power_gpio);
1545
1546         regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1547
1548         snd_soc_unregister_codec(&client->dev);
1549         kfree(dac33);
1550
1551         return 0;
1552 }
1553
1554 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1555         {
1556                 .name = "tlv320dac33",
1557                 .driver_data = 0,
1558         },
1559         { },
1560 };
1561
1562 static struct i2c_driver tlv320dac33_i2c_driver = {
1563         .driver = {
1564                 .name = "tlv320dac33-codec",
1565                 .owner = THIS_MODULE,
1566         },
1567         .probe          = dac33_i2c_probe,
1568         .remove         = __devexit_p(dac33_i2c_remove),
1569         .id_table       = tlv320dac33_i2c_id,
1570 };
1571
1572 static int __init dac33_module_init(void)
1573 {
1574         int r;
1575         r = i2c_add_driver(&tlv320dac33_i2c_driver);
1576         if (r < 0) {
1577                 printk(KERN_ERR "DAC33: driver registration failed\n");
1578                 return r;
1579         }
1580         return 0;
1581 }
1582 module_init(dac33_module_init);
1583
1584 static void __exit dac33_module_exit(void)
1585 {
1586         i2c_del_driver(&tlv320dac33_i2c_driver);
1587 }
1588 module_exit(dac33_module_exit);
1589
1590
1591 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1592 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1593 MODULE_LICENSE("GPL");