2 * wm5100.c -- WM5100 ALSA SoC Audio driver
4 * Copyright 2011 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/gcd.h>
19 #include <linux/gpio.h>
20 #include <linux/i2c.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/regulator/fixed.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <sound/wm5100.h>
36 #define WM5100_NUM_CORE_SUPPLIES 2
37 static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
39 "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
43 #define WM5100_SYNC_SRS 3
49 struct completion lock;
52 /* codec private data */
55 struct regmap *regmap;
56 struct snd_soc_codec *codec;
58 struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
65 bool aif_async[WM5100_AIFS];
66 bool aif_symmetric[WM5100_AIFS];
67 int sr_ref[WM5100_SYNC_SRS];
71 struct snd_soc_jack *jack;
77 struct wm5100_fll fll[2];
79 struct wm5100_pdata pdata;
82 struct gpio_chip gpio_chip;
86 static int wm5100_sr_code[] = {
113 static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
119 static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
121 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
122 int sr_code, sr_free, i;
124 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
125 if (wm5100_sr_code[i] == rate)
127 if (i == ARRAY_SIZE(wm5100_sr_code)) {
128 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
133 if ((wm5100->sysclk % rate) == 0) {
134 /* Is this rate already in use? */
136 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
137 if (!wm5100->sr_ref[i] && sr_free == -1) {
141 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
142 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
146 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
148 dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
149 rate, i, wm5100->sr_ref[i]);
154 dev_err(codec->dev, "All SR slots already in use\n");
158 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
160 wm5100->sr_ref[sr_free]++;
161 snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
162 WM5100_SAMPLE_RATE_1_MASK,
169 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
170 rate, wm5100->sysclk, wm5100->asyncclk);
175 static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
177 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
180 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
181 if (wm5100_sr_code[i] == rate)
183 if (i == ARRAY_SIZE(wm5100_sr_code)) {
184 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
187 sr_code = wm5100_sr_code[i];
189 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
190 if (!wm5100->sr_ref[i])
193 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
194 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
197 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
199 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
200 rate, wm5100->sr_ref[i]);
202 dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
207 static int wm5100_reset(struct wm5100_priv *wm5100)
209 if (wm5100->pdata.reset) {
210 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
211 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
215 return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
219 static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
220 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
221 static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
222 static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
223 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
225 static const char *wm5100_mixer_texts[] = {
300 static int wm5100_mixer_values[] = {
323 0x30, /* AIF3 - check */
358 0xa0, /* ISRC1DEC1 */
362 0xa4, /* ISRC1INT1 */
366 0xa8, /* ISRC2DEC1 */
370 0xac, /* ISRC2INT1 */
376 #define WM5100_MIXER_CONTROLS(name, base) \
377 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
378 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
379 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
380 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
381 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
382 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
383 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
384 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
386 #define WM5100_MUX_ENUM_DECL(name, reg) \
387 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
388 wm5100_mixer_texts, wm5100_mixer_values)
390 #define WM5100_MUX_CTL_DECL(name) \
391 const struct snd_kcontrol_new name##_mux = \
392 SOC_DAPM_VALUE_ENUM("Route", name##_enum)
394 #define WM5100_MIXER_ENUMS(name, base_reg) \
395 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
396 static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
397 static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
398 static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
399 static WM5100_MUX_CTL_DECL(name##_in1); \
400 static WM5100_MUX_CTL_DECL(name##_in2); \
401 static WM5100_MUX_CTL_DECL(name##_in3); \
402 static WM5100_MUX_CTL_DECL(name##_in4)
404 WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
405 WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
406 WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
407 WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
408 WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
409 WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
411 WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
412 WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
413 WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
414 WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
415 WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
416 WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
418 WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
419 WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
421 WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
422 WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
423 WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
424 WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
425 WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
426 WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
427 WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
428 WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
430 WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
431 WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
433 WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
434 WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
436 WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
437 WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
438 WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
439 WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
441 WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
442 WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
444 WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
445 WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
446 WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
447 WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
449 #define WM5100_MUX(name, ctrl) \
450 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
452 #define WM5100_MIXER_WIDGETS(name, name_str) \
453 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
454 WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
455 WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
456 WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
457 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
459 #define WM5100_MIXER_INPUT_ROUTES(name) \
460 { name, "Tone Generator 1", "Tone Generator 1" }, \
461 { name, "Tone Generator 2", "Tone Generator 2" }, \
462 { name, "IN1L", "IN1L PGA" }, \
463 { name, "IN1R", "IN1R PGA" }, \
464 { name, "IN2L", "IN2L PGA" }, \
465 { name, "IN2R", "IN2R PGA" }, \
466 { name, "IN3L", "IN3L PGA" }, \
467 { name, "IN3R", "IN3R PGA" }, \
468 { name, "IN4L", "IN4L PGA" }, \
469 { name, "IN4R", "IN4R PGA" }, \
470 { name, "AIF1RX1", "AIF1RX1" }, \
471 { name, "AIF1RX2", "AIF1RX2" }, \
472 { name, "AIF1RX3", "AIF1RX3" }, \
473 { name, "AIF1RX4", "AIF1RX4" }, \
474 { name, "AIF1RX5", "AIF1RX5" }, \
475 { name, "AIF1RX6", "AIF1RX6" }, \
476 { name, "AIF1RX7", "AIF1RX7" }, \
477 { name, "AIF1RX8", "AIF1RX8" }, \
478 { name, "AIF2RX1", "AIF2RX1" }, \
479 { name, "AIF2RX2", "AIF2RX2" }, \
480 { name, "AIF3RX1", "AIF3RX1" }, \
481 { name, "AIF3RX2", "AIF3RX2" }, \
482 { name, "EQ1", "EQ1" }, \
483 { name, "EQ2", "EQ2" }, \
484 { name, "EQ3", "EQ3" }, \
485 { name, "EQ4", "EQ4" }, \
486 { name, "DRC1L", "DRC1L" }, \
487 { name, "DRC1R", "DRC1R" }, \
488 { name, "LHPF1", "LHPF1" }, \
489 { name, "LHPF2", "LHPF2" }, \
490 { name, "LHPF3", "LHPF3" }, \
491 { name, "LHPF4", "LHPF4" }
493 #define WM5100_MIXER_ROUTES(widget, name) \
494 { widget, NULL, name " Mixer" }, \
495 { name " Mixer", NULL, name " Input 1" }, \
496 { name " Mixer", NULL, name " Input 2" }, \
497 { name " Mixer", NULL, name " Input 3" }, \
498 { name " Mixer", NULL, name " Input 4" }, \
499 WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
500 WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
501 WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
502 WM5100_MIXER_INPUT_ROUTES(name " Input 4")
504 static const char *wm5100_lhpf_mode_text[] = {
505 "Low-pass", "High-pass"
508 static const struct soc_enum wm5100_lhpf1_mode =
509 SOC_ENUM_SINGLE(WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT, 2,
510 wm5100_lhpf_mode_text);
512 static const struct soc_enum wm5100_lhpf2_mode =
513 SOC_ENUM_SINGLE(WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT, 2,
514 wm5100_lhpf_mode_text);
516 static const struct soc_enum wm5100_lhpf3_mode =
517 SOC_ENUM_SINGLE(WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT, 2,
518 wm5100_lhpf_mode_text);
520 static const struct soc_enum wm5100_lhpf4_mode =
521 SOC_ENUM_SINGLE(WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT, 2,
522 wm5100_lhpf_mode_text);
524 static const struct snd_kcontrol_new wm5100_snd_controls[] = {
525 SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
526 WM5100_IN1_OSR_SHIFT, 1, 0),
527 SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
528 WM5100_IN2_OSR_SHIFT, 1, 0),
529 SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
530 WM5100_IN3_OSR_SHIFT, 1, 0),
531 SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
532 WM5100_IN4_OSR_SHIFT, 1, 0),
534 /* Only applicable for analogue inputs */
535 SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
536 WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
537 SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
538 WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
539 SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
540 WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
541 SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
542 WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
544 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
545 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
547 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
548 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
550 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
551 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
553 SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
554 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
557 SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
558 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
559 SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
560 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
561 SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
562 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
563 SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
564 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
566 SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
567 WM5100_OUT1_OSR_SHIFT, 1, 0),
568 SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
569 WM5100_OUT2_OSR_SHIFT, 1, 0),
570 SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
571 WM5100_OUT3_OSR_SHIFT, 1, 0),
572 SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
573 WM5100_OUT4_OSR_SHIFT, 1, 0),
574 SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
575 WM5100_OUT5_OSR_SHIFT, 1, 0),
576 SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
577 WM5100_OUT6_OSR_SHIFT, 1, 0),
579 SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
580 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
582 SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
583 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
585 SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
586 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
588 SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
589 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
591 SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
592 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
594 SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
595 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
598 SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
599 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
600 SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
601 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
602 SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
603 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
604 SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
605 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
606 SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
607 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
608 SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
609 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
611 /* FIXME: Only valid from -12dB to 0dB (52-64) */
612 SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
613 WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
614 SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
615 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
616 SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
617 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
619 SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
620 WM5100_SPK1R_MUTE_SHIFT, 1, 1),
621 SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
622 WM5100_SPK2R_MUTE_SHIFT, 1, 1),
624 SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
626 SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
628 SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
630 SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
632 SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
635 SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
637 SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
639 SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
641 SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
643 SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
646 SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
648 SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
650 SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
652 SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
654 SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
657 SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
659 SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
661 SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
663 SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
665 SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
668 SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
669 SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
670 SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
671 SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
673 WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
674 WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
675 WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
676 WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
677 WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
678 WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
680 WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
681 WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
682 WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
683 WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
684 WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
685 WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
687 WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
688 WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
690 WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
691 WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
692 WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
693 WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
694 WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
695 WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
696 WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
697 WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
699 WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
700 WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
702 WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
703 WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
705 WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
706 WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
707 WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
708 WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
710 WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
711 WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
713 WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
714 WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
715 WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
716 WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
719 static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
720 enum snd_soc_dapm_type event, int subseq)
722 struct snd_soc_codec *codec = container_of(dapm,
723 struct snd_soc_codec, dapm);
724 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
727 /* Wait for the outputs to flag themselves as enabled */
728 if (wm5100->out_ena[0]) {
729 expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
730 for (i = 0; i < 200; i++) {
731 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
733 wm5100->out_ena[0] = false;
738 dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
743 if (wm5100->out_ena[1]) {
744 expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
745 for (i = 0; i < 200; i++) {
746 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
748 wm5100->out_ena[1] = false;
753 dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
759 static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
760 struct snd_kcontrol *kcontrol,
763 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(w->codec);
766 case WM5100_CHANNEL_ENABLES_1:
767 wm5100->out_ena[0] = true;
769 case WM5100_OUTPUT_ENABLES_2:
770 wm5100->out_ena[0] = true;
779 static void wm5100_log_status3(struct wm5100_priv *wm5100, int val)
781 if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
782 dev_crit(wm5100->dev, "Speaker shutdown warning\n");
783 if (val & WM5100_SPK_SHUTDOWN_EINT)
784 dev_crit(wm5100->dev, "Speaker shutdown\n");
785 if (val & WM5100_CLKGEN_ERR_EINT)
786 dev_crit(wm5100->dev, "SYSCLK underclocked\n");
787 if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
788 dev_crit(wm5100->dev, "ASYNCCLK underclocked\n");
791 static void wm5100_log_status4(struct wm5100_priv *wm5100, int val)
793 if (val & WM5100_AIF3_ERR_EINT)
794 dev_err(wm5100->dev, "AIF3 configuration error\n");
795 if (val & WM5100_AIF2_ERR_EINT)
796 dev_err(wm5100->dev, "AIF2 configuration error\n");
797 if (val & WM5100_AIF1_ERR_EINT)
798 dev_err(wm5100->dev, "AIF1 configuration error\n");
799 if (val & WM5100_CTRLIF_ERR_EINT)
800 dev_err(wm5100->dev, "Control interface error\n");
801 if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
802 dev_err(wm5100->dev, "ISRC2 underclocked\n");
803 if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
804 dev_err(wm5100->dev, "ISRC1 underclocked\n");
805 if (val & WM5100_FX_UNDERCLOCKED_EINT)
806 dev_err(wm5100->dev, "FX underclocked\n");
807 if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
808 dev_err(wm5100->dev, "AIF3 underclocked\n");
809 if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
810 dev_err(wm5100->dev, "AIF2 underclocked\n");
811 if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
812 dev_err(wm5100->dev, "AIF1 underclocked\n");
813 if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
814 dev_err(wm5100->dev, "ASRC underclocked\n");
815 if (val & WM5100_DAC_UNDERCLOCKED_EINT)
816 dev_err(wm5100->dev, "DAC underclocked\n");
817 if (val & WM5100_ADC_UNDERCLOCKED_EINT)
818 dev_err(wm5100->dev, "ADC underclocked\n");
819 if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
820 dev_err(wm5100->dev, "Mixer underclocked\n");
823 static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
824 struct snd_kcontrol *kcontrol,
827 struct snd_soc_codec *codec = w->codec;
828 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
831 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
832 ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
833 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
834 WM5100_CLKGEN_ERR_ASYNC_STS;
835 wm5100_log_status3(wm5100, ret);
837 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
838 wm5100_log_status4(wm5100, ret);
843 static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
844 SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
846 SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
849 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20),
850 SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0),
851 SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0),
853 SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
855 SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
857 SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
858 WM5100_CP2_BYPASS_SHIFT, 1, NULL, 0),
860 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
862 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
864 SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
867 SND_SOC_DAPM_INPUT("IN1L"),
868 SND_SOC_DAPM_INPUT("IN1R"),
869 SND_SOC_DAPM_INPUT("IN2L"),
870 SND_SOC_DAPM_INPUT("IN2R"),
871 SND_SOC_DAPM_INPUT("IN3L"),
872 SND_SOC_DAPM_INPUT("IN3R"),
873 SND_SOC_DAPM_INPUT("IN4L"),
874 SND_SOC_DAPM_INPUT("IN4R"),
875 SND_SOC_DAPM_SIGGEN("TONE"),
877 SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
878 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
879 SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
880 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
881 SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
882 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
883 SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
884 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
885 SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
886 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
887 SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
888 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
889 SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
890 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
891 SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
892 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
894 SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
895 WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
896 SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
897 WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
899 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
900 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
901 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
902 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
903 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
904 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
905 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
906 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
907 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
908 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
909 SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
910 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
911 SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
912 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
913 SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
914 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
916 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
917 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
918 SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
919 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
921 SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
922 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
923 SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
924 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
926 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
927 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
928 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
929 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
930 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
931 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
932 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
933 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
934 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
935 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
936 SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
937 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
938 SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
939 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
940 SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
941 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
943 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
944 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
945 SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
946 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
948 SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
949 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
950 SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
951 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
953 SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
954 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
955 SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
956 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
957 SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
958 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
959 SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
960 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
961 SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
962 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
963 SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
964 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
965 SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
966 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
967 SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
968 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
969 SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
970 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
971 SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
972 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
973 SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
974 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
975 SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
976 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
977 SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
978 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
979 SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
980 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
982 SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
983 SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
984 SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
985 SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
987 SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
989 SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
992 SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
994 SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
996 SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
998 SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1001 WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1002 WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1003 WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1004 WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1006 WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1007 WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1009 WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1010 WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1011 WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1012 WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1014 WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1015 WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1016 WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1017 WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1018 WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1019 WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1020 WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1021 WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1023 WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1024 WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1026 WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1027 WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1029 WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1030 WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1031 WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1032 WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1033 WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1034 WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1036 WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1037 WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1038 WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1039 WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1040 WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1041 WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1043 WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1044 WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1046 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1047 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1048 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1049 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1050 SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1051 SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1052 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1053 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1054 SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1055 SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1056 SND_SOC_DAPM_OUTPUT("PWM1"),
1057 SND_SOC_DAPM_OUTPUT("PWM2"),
1060 /* We register a _POST event if we don't have IRQ support so we can
1061 * look at the error status from the CODEC - if we've got the IRQ
1062 * hooked up then we will get prompted to look by an interrupt.
1064 static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1065 SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1068 static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1069 { "CP1", NULL, "CPVDD" },
1070 { "CP2 Active", NULL, "CPVDD" },
1072 { "IN1L", NULL, "SYSCLK" },
1073 { "IN1R", NULL, "SYSCLK" },
1074 { "IN2L", NULL, "SYSCLK" },
1075 { "IN2R", NULL, "SYSCLK" },
1076 { "IN3L", NULL, "SYSCLK" },
1077 { "IN3R", NULL, "SYSCLK" },
1078 { "IN4L", NULL, "SYSCLK" },
1079 { "IN4R", NULL, "SYSCLK" },
1081 { "OUT1L", NULL, "SYSCLK" },
1082 { "OUT1R", NULL, "SYSCLK" },
1083 { "OUT2L", NULL, "SYSCLK" },
1084 { "OUT2R", NULL, "SYSCLK" },
1085 { "OUT3L", NULL, "SYSCLK" },
1086 { "OUT3R", NULL, "SYSCLK" },
1087 { "OUT4L", NULL, "SYSCLK" },
1088 { "OUT4R", NULL, "SYSCLK" },
1089 { "OUT5L", NULL, "SYSCLK" },
1090 { "OUT5R", NULL, "SYSCLK" },
1091 { "OUT6L", NULL, "SYSCLK" },
1092 { "OUT6R", NULL, "SYSCLK" },
1094 { "AIF1RX1", NULL, "SYSCLK" },
1095 { "AIF1RX2", NULL, "SYSCLK" },
1096 { "AIF1RX3", NULL, "SYSCLK" },
1097 { "AIF1RX4", NULL, "SYSCLK" },
1098 { "AIF1RX5", NULL, "SYSCLK" },
1099 { "AIF1RX6", NULL, "SYSCLK" },
1100 { "AIF1RX7", NULL, "SYSCLK" },
1101 { "AIF1RX8", NULL, "SYSCLK" },
1103 { "AIF2RX1", NULL, "SYSCLK" },
1104 { "AIF2RX1", NULL, "DBVDD2" },
1105 { "AIF2RX2", NULL, "SYSCLK" },
1106 { "AIF2RX2", NULL, "DBVDD2" },
1108 { "AIF3RX1", NULL, "SYSCLK" },
1109 { "AIF3RX1", NULL, "DBVDD3" },
1110 { "AIF3RX2", NULL, "SYSCLK" },
1111 { "AIF3RX2", NULL, "DBVDD3" },
1113 { "AIF1TX1", NULL, "SYSCLK" },
1114 { "AIF1TX2", NULL, "SYSCLK" },
1115 { "AIF1TX3", NULL, "SYSCLK" },
1116 { "AIF1TX4", NULL, "SYSCLK" },
1117 { "AIF1TX5", NULL, "SYSCLK" },
1118 { "AIF1TX6", NULL, "SYSCLK" },
1119 { "AIF1TX7", NULL, "SYSCLK" },
1120 { "AIF1TX8", NULL, "SYSCLK" },
1122 { "AIF2TX1", NULL, "SYSCLK" },
1123 { "AIF2TX1", NULL, "DBVDD2" },
1124 { "AIF2TX2", NULL, "SYSCLK" },
1125 { "AIF2TX2", NULL, "DBVDD2" },
1127 { "AIF3TX1", NULL, "SYSCLK" },
1128 { "AIF3TX1", NULL, "DBVDD3" },
1129 { "AIF3TX2", NULL, "SYSCLK" },
1130 { "AIF3TX2", NULL, "DBVDD3" },
1132 { "MICBIAS1", NULL, "CP2" },
1133 { "MICBIAS2", NULL, "CP2" },
1134 { "MICBIAS3", NULL, "CP2" },
1136 { "IN1L PGA", NULL, "CP2" },
1137 { "IN1R PGA", NULL, "CP2" },
1138 { "IN2L PGA", NULL, "CP2" },
1139 { "IN2R PGA", NULL, "CP2" },
1140 { "IN3L PGA", NULL, "CP2" },
1141 { "IN3R PGA", NULL, "CP2" },
1142 { "IN4L PGA", NULL, "CP2" },
1143 { "IN4R PGA", NULL, "CP2" },
1145 { "IN1L PGA", NULL, "CP2 Active" },
1146 { "IN1R PGA", NULL, "CP2 Active" },
1147 { "IN2L PGA", NULL, "CP2 Active" },
1148 { "IN2R PGA", NULL, "CP2 Active" },
1149 { "IN3L PGA", NULL, "CP2 Active" },
1150 { "IN3R PGA", NULL, "CP2 Active" },
1151 { "IN4L PGA", NULL, "CP2 Active" },
1152 { "IN4R PGA", NULL, "CP2 Active" },
1154 { "OUT1L", NULL, "CP1" },
1155 { "OUT1R", NULL, "CP1" },
1156 { "OUT2L", NULL, "CP1" },
1157 { "OUT2R", NULL, "CP1" },
1158 { "OUT3L", NULL, "CP1" },
1159 { "OUT3R", NULL, "CP1" },
1161 { "Tone Generator 1", NULL, "TONE" },
1162 { "Tone Generator 2", NULL, "TONE" },
1164 { "IN1L PGA", NULL, "IN1L" },
1165 { "IN1R PGA", NULL, "IN1R" },
1166 { "IN2L PGA", NULL, "IN2L" },
1167 { "IN2R PGA", NULL, "IN2R" },
1168 { "IN3L PGA", NULL, "IN3L" },
1169 { "IN3R PGA", NULL, "IN3R" },
1170 { "IN4L PGA", NULL, "IN4L" },
1171 { "IN4R PGA", NULL, "IN4R" },
1173 WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1174 WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1175 WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1176 WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1177 WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1178 WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1180 WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1181 WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1182 WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1183 WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1184 WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1185 WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1187 WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1188 WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1190 WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1191 WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1192 WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1193 WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1194 WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1195 WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1196 WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1197 WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1199 WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1200 WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1202 WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1203 WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1205 WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1206 WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1207 WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1208 WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1210 WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1211 WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1213 WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1214 WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1215 WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1216 WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1218 { "HPOUT1L", NULL, "OUT1L" },
1219 { "HPOUT1R", NULL, "OUT1R" },
1220 { "HPOUT2L", NULL, "OUT2L" },
1221 { "HPOUT2R", NULL, "OUT2R" },
1222 { "HPOUT3L", NULL, "OUT3L" },
1223 { "HPOUT3R", NULL, "OUT3R" },
1224 { "SPKOUTL", NULL, "OUT4L" },
1225 { "SPKOUTR", NULL, "OUT4R" },
1226 { "SPKDAT1", NULL, "OUT5L" },
1227 { "SPKDAT1", NULL, "OUT5R" },
1228 { "SPKDAT2", NULL, "OUT6L" },
1229 { "SPKDAT2", NULL, "OUT6R" },
1230 { "PWM1", NULL, "PWM1 Driver" },
1231 { "PWM2", NULL, "PWM2 Driver" },
1234 static const __devinitdata struct reg_default wm5100_reva_patches[] = {
1235 { WM5100_AUDIO_IF_1_10, 0 },
1236 { WM5100_AUDIO_IF_1_11, 1 },
1237 { WM5100_AUDIO_IF_1_12, 2 },
1238 { WM5100_AUDIO_IF_1_13, 3 },
1239 { WM5100_AUDIO_IF_1_14, 4 },
1240 { WM5100_AUDIO_IF_1_15, 5 },
1241 { WM5100_AUDIO_IF_1_16, 6 },
1242 { WM5100_AUDIO_IF_1_17, 7 },
1244 { WM5100_AUDIO_IF_1_18, 0 },
1245 { WM5100_AUDIO_IF_1_19, 1 },
1246 { WM5100_AUDIO_IF_1_20, 2 },
1247 { WM5100_AUDIO_IF_1_21, 3 },
1248 { WM5100_AUDIO_IF_1_22, 4 },
1249 { WM5100_AUDIO_IF_1_23, 5 },
1250 { WM5100_AUDIO_IF_1_24, 6 },
1251 { WM5100_AUDIO_IF_1_25, 7 },
1253 { WM5100_AUDIO_IF_2_10, 0 },
1254 { WM5100_AUDIO_IF_2_11, 1 },
1256 { WM5100_AUDIO_IF_2_18, 0 },
1257 { WM5100_AUDIO_IF_2_19, 1 },
1259 { WM5100_AUDIO_IF_3_10, 0 },
1260 { WM5100_AUDIO_IF_3_11, 1 },
1262 { WM5100_AUDIO_IF_3_18, 0 },
1263 { WM5100_AUDIO_IF_3_19, 1 },
1266 static int wm5100_dai_to_base(struct snd_soc_dai *dai)
1270 return WM5100_AUDIO_IF_1_1 - 1;
1272 return WM5100_AUDIO_IF_2_1 - 1;
1274 return WM5100_AUDIO_IF_3_1 - 1;
1281 static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1283 struct snd_soc_codec *codec = dai->codec;
1284 int lrclk, bclk, mask, base;
1286 base = wm5100_dai_to_base(dai);
1293 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1294 case SND_SOC_DAIFMT_DSP_A:
1297 case SND_SOC_DAIFMT_DSP_B:
1300 case SND_SOC_DAIFMT_I2S:
1303 case SND_SOC_DAIFMT_LEFT_J:
1307 dev_err(codec->dev, "Unsupported DAI format %d\n",
1308 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1312 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1313 case SND_SOC_DAIFMT_CBS_CFS:
1315 case SND_SOC_DAIFMT_CBS_CFM:
1316 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1318 case SND_SOC_DAIFMT_CBM_CFS:
1319 bclk |= WM5100_AIF1_BCLK_MSTR;
1321 case SND_SOC_DAIFMT_CBM_CFM:
1322 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1323 bclk |= WM5100_AIF1_BCLK_MSTR;
1326 dev_err(codec->dev, "Unsupported master mode %d\n",
1327 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1331 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1332 case SND_SOC_DAIFMT_NB_NF:
1334 case SND_SOC_DAIFMT_IB_IF:
1335 bclk |= WM5100_AIF1_BCLK_INV;
1336 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1338 case SND_SOC_DAIFMT_IB_NF:
1339 bclk |= WM5100_AIF1_BCLK_INV;
1341 case SND_SOC_DAIFMT_NB_IF:
1342 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1348 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1349 WM5100_AIF1_BCLK_INV, bclk);
1350 snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1351 WM5100_AIF1TX_LRCLK_INV, lrclk);
1352 snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1353 WM5100_AIF1TX_LRCLK_INV, lrclk);
1354 snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1359 #define WM5100_NUM_BCLK_RATES 19
1361 static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1383 static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1405 static int wm5100_hw_params(struct snd_pcm_substream *substream,
1406 struct snd_pcm_hw_params *params,
1407 struct snd_soc_dai *dai)
1409 struct snd_soc_codec *codec = dai->codec;
1410 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1411 bool async = wm5100->aif_async[dai->id];
1412 int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1415 base = wm5100_dai_to_base(dai);
1419 /* Data sizes if not using TDM */
1420 wl = snd_pcm_format_width(params_format(params));
1423 fl = snd_soc_params_to_frame_size(params);
1427 dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1430 /* Target BCLK rate */
1431 bclk = snd_soc_params_to_bclk(params);
1435 /* Root for BCLK depends on SYS/ASYNCCLK */
1437 aif_rate = wm5100->sysclk;
1438 sr = wm5100_alloc_sr(codec, params_rate(params));
1442 /* If we're in ASYNCCLK set the ASYNC sample rate */
1443 aif_rate = wm5100->asyncclk;
1446 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1447 if (params_rate(params) == wm5100_sr_code[i])
1449 if (i == ARRAY_SIZE(wm5100_sr_code)) {
1450 dev_err(codec->dev, "Invalid rate %dHzn",
1451 params_rate(params));
1455 /* TODO: We should really check for symmetry */
1456 snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1457 WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1461 dev_err(codec->dev, "%s has no rate set\n",
1462 async ? "ASYNCCLK" : "SYSCLK");
1466 dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1467 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1469 if (aif_rate % 4000)
1470 bclk_rates = wm5100_bclk_rates_cd;
1472 bclk_rates = wm5100_bclk_rates_dat;
1474 for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1475 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1477 if (i == WM5100_NUM_BCLK_RATES) {
1479 "No valid BCLK for %dHz found from %dHz %s\n",
1480 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1485 dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1486 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1488 lrclk = bclk_rates[bclk] / params_rate(params);
1489 dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1490 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1491 wm5100->aif_symmetric[dai->id])
1492 snd_soc_update_bits(codec, base + 7,
1493 WM5100_AIF1RX_BCPF_MASK, lrclk);
1495 snd_soc_update_bits(codec, base + 6,
1496 WM5100_AIF1TX_BCPF_MASK, lrclk);
1498 i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1499 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1500 snd_soc_update_bits(codec, base + 9,
1501 WM5100_AIF1RX_WL_MASK |
1502 WM5100_AIF1RX_SLOT_LEN_MASK, i);
1504 snd_soc_update_bits(codec, base + 8,
1505 WM5100_AIF1TX_WL_MASK |
1506 WM5100_AIF1TX_SLOT_LEN_MASK, i);
1508 snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1513 static const struct snd_soc_dai_ops wm5100_dai_ops = {
1514 .set_fmt = wm5100_set_fmt,
1515 .hw_params = wm5100_hw_params,
1518 static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1519 int source, unsigned int freq, int dir)
1521 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1523 int fval, audio_rate, ret, reg;
1526 case WM5100_CLK_SYSCLK:
1527 reg = WM5100_CLOCKING_3;
1528 rate_store = &wm5100->sysclk;
1530 case WM5100_CLK_ASYNCCLK:
1531 reg = WM5100_CLOCKING_7;
1532 rate_store = &wm5100->asyncclk;
1534 case WM5100_CLK_32KHZ:
1535 /* The 32kHz clock is slightly different to the others */
1537 case WM5100_CLKSRC_MCLK1:
1538 case WM5100_CLKSRC_MCLK2:
1539 case WM5100_CLKSRC_SYSCLK:
1540 snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1541 WM5100_CLK_32K_SRC_MASK,
1549 case WM5100_CLK_AIF1:
1550 case WM5100_CLK_AIF2:
1551 case WM5100_CLK_AIF3:
1552 /* Not real clocks, record which clock domain they're in */
1554 case WM5100_CLKSRC_SYSCLK:
1555 wm5100->aif_async[clk_id - 1] = false;
1557 case WM5100_CLKSRC_ASYNCCLK:
1558 wm5100->aif_async[clk_id - 1] = true;
1561 dev_err(codec->dev, "Invalid source %d\n", source);
1566 case WM5100_CLK_OPCLK:
1570 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1571 WM5100_OPCLK_SEL_MASK, 0);
1575 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1576 WM5100_OPCLK_SEL_MASK, 0);
1580 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1581 WM5100_OPCLK_SEL_MASK, 0);
1584 dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1591 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1596 case WM5100_CLKSRC_SYSCLK:
1597 case WM5100_CLKSRC_ASYNCCLK:
1598 dev_err(codec->dev, "Invalid source %d\n", source);
1616 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1639 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1643 snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1644 WM5100_SYSCLK_SRC_MASK,
1645 fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1647 /* If this is SYSCLK then configure the clock rate for the
1648 * internal audio functions to the natural sample rate for
1651 if (clk_id == WM5100_CLK_SYSCLK) {
1652 dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1654 if (0 && *rate_store)
1655 wm5100_free_sr(codec, audio_rate);
1656 ret = wm5100_alloc_sr(codec, audio_rate);
1658 dev_warn(codec->dev, "Primary audio slot is %d\n",
1682 { 0, 64000, 4, 16 },
1683 { 64000, 128000, 3, 8 },
1684 { 128000, 256000, 2, 4 },
1685 { 256000, 1000000, 1, 2 },
1686 { 1000000, 13500000, 0, 1 },
1689 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1692 unsigned int target;
1694 unsigned int fratio, gcd_fll;
1697 /* Fref must be <=13.5MHz */
1699 fll_div->fll_refclk_div = 0;
1700 while ((Fref / div) > 13500000) {
1702 fll_div->fll_refclk_div++;
1705 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1711 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1713 /* Apply the division for our remaining calculations */
1716 /* Fvco should be 90-100MHz; don't check the upper bound */
1718 while (Fout * div < 90000000) {
1721 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1726 target = Fout * div;
1727 fll_div->fll_outdiv = div - 1;
1729 pr_debug("FLL Fvco=%dHz\n", target);
1731 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1732 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1733 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1734 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1735 fratio = fll_fratios[i].ratio;
1739 if (i == ARRAY_SIZE(fll_fratios)) {
1740 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1744 fll_div->n = target / (fratio * Fref);
1746 if (target % Fref == 0) {
1748 fll_div->lambda = 0;
1750 gcd_fll = gcd(target, fratio * Fref);
1752 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1754 fll_div->lambda = (fratio * Fref) / gcd_fll;
1757 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1758 fll_div->n, fll_div->theta, fll_div->lambda);
1759 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1760 fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1761 fll_div->fll_refclk_div);
1766 static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1767 unsigned int Fref, unsigned int Fout)
1769 struct i2c_client *i2c = to_i2c_client(codec->dev);
1770 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1771 struct _fll_div factors;
1772 struct wm5100_fll *fll;
1773 int ret, base, lock, i, timeout;
1777 fll = &wm5100->fll[0];
1778 base = WM5100_FLL1_CONTROL_1 - 1;
1779 lock = WM5100_FLL1_LOCK_STS;
1782 fll = &wm5100->fll[1];
1783 base = WM5100_FLL2_CONTROL_2 - 1;
1784 lock = WM5100_FLL2_LOCK_STS;
1787 dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1792 dev_dbg(codec->dev, "FLL%d disabled", fll_id);
1794 pm_runtime_put(codec->dev);
1796 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1801 case WM5100_FLL_SRC_MCLK1:
1802 case WM5100_FLL_SRC_MCLK2:
1803 case WM5100_FLL_SRC_FLL1:
1804 case WM5100_FLL_SRC_FLL2:
1805 case WM5100_FLL_SRC_AIF1BCLK:
1806 case WM5100_FLL_SRC_AIF2BCLK:
1807 case WM5100_FLL_SRC_AIF3BCLK:
1810 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1814 ret = fll_factors(&factors, Fref, Fout);
1818 /* Disable the FLL while we reconfigure */
1819 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1821 snd_soc_update_bits(codec, base + 2,
1822 WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1823 (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1824 factors.fll_fratio);
1825 snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1827 snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1828 snd_soc_update_bits(codec, base + 6,
1829 WM5100_FLL1_REFCLK_DIV_MASK |
1830 WM5100_FLL1_REFCLK_SRC_MASK,
1831 (factors.fll_refclk_div
1832 << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1833 snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1836 /* Clear any pending completions */
1837 try_wait_for_completion(&fll->lock);
1839 pm_runtime_get_sync(codec->dev);
1841 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1848 snd_soc_update_bits(codec, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
1851 /* Poll for the lock; will use interrupt when we can test */
1852 for (i = 0; i < timeout; i++) {
1854 ret = wait_for_completion_timeout(&fll->lock,
1855 msecs_to_jiffies(25));
1862 ret = snd_soc_read(codec,
1863 WM5100_INTERRUPT_RAW_STATUS_3);
1866 "Failed to read FLL status: %d\n",
1874 dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
1875 pm_runtime_put(codec->dev);
1883 dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
1889 /* Actually go much higher */
1890 #define WM5100_RATES SNDRV_PCM_RATE_8000_192000
1892 #define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1893 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1895 static struct snd_soc_dai_driver wm5100_dai[] = {
1897 .name = "wm5100-aif1",
1899 .stream_name = "AIF1 Playback",
1902 .rates = WM5100_RATES,
1903 .formats = WM5100_FORMATS,
1906 .stream_name = "AIF1 Capture",
1909 .rates = WM5100_RATES,
1910 .formats = WM5100_FORMATS,
1912 .ops = &wm5100_dai_ops,
1915 .name = "wm5100-aif2",
1918 .stream_name = "AIF2 Playback",
1921 .rates = WM5100_RATES,
1922 .formats = WM5100_FORMATS,
1925 .stream_name = "AIF2 Capture",
1928 .rates = WM5100_RATES,
1929 .formats = WM5100_FORMATS,
1931 .ops = &wm5100_dai_ops,
1934 .name = "wm5100-aif3",
1937 .stream_name = "AIF3 Playback",
1940 .rates = WM5100_RATES,
1941 .formats = WM5100_FORMATS,
1944 .stream_name = "AIF3 Capture",
1947 .rates = WM5100_RATES,
1948 .formats = WM5100_FORMATS,
1950 .ops = &wm5100_dai_ops,
1954 static int wm5100_dig_vu[] = {
1955 WM5100_ADC_DIGITAL_VOLUME_1L,
1956 WM5100_ADC_DIGITAL_VOLUME_1R,
1957 WM5100_ADC_DIGITAL_VOLUME_2L,
1958 WM5100_ADC_DIGITAL_VOLUME_2R,
1959 WM5100_ADC_DIGITAL_VOLUME_3L,
1960 WM5100_ADC_DIGITAL_VOLUME_3R,
1961 WM5100_ADC_DIGITAL_VOLUME_4L,
1962 WM5100_ADC_DIGITAL_VOLUME_4R,
1964 WM5100_DAC_DIGITAL_VOLUME_1L,
1965 WM5100_DAC_DIGITAL_VOLUME_1R,
1966 WM5100_DAC_DIGITAL_VOLUME_2L,
1967 WM5100_DAC_DIGITAL_VOLUME_2R,
1968 WM5100_DAC_DIGITAL_VOLUME_3L,
1969 WM5100_DAC_DIGITAL_VOLUME_3R,
1970 WM5100_DAC_DIGITAL_VOLUME_4L,
1971 WM5100_DAC_DIGITAL_VOLUME_4R,
1972 WM5100_DAC_DIGITAL_VOLUME_5L,
1973 WM5100_DAC_DIGITAL_VOLUME_5R,
1974 WM5100_DAC_DIGITAL_VOLUME_6L,
1975 WM5100_DAC_DIGITAL_VOLUME_6R,
1978 static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode)
1980 struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
1982 BUG_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes));
1984 gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
1985 regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1,
1986 WM5100_ACCDET_BIAS_SRC_MASK |
1988 (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
1989 mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
1990 regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL,
1992 mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
1994 wm5100->jack_mode = the_mode;
1996 dev_dbg(wm5100->dev, "Set microphone polarity to %d\n",
2000 static void wm5100_report_headphone(struct wm5100_priv *wm5100)
2002 dev_dbg(wm5100->dev, "Headphone detected\n");
2003 wm5100->jack_detecting = false;
2004 snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
2005 SND_JACK_HEADPHONE);
2007 /* Increase the detection rate a bit for responsiveness. */
2008 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2009 WM5100_ACCDET_RATE_MASK,
2010 7 << WM5100_ACCDET_RATE_SHIFT);
2013 static void wm5100_micd_irq(struct wm5100_priv *wm5100)
2018 ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val);
2020 dev_err(wm5100->dev, "Failed to read micropone status: %d\n",
2025 dev_dbg(wm5100->dev, "Microphone event: %x\n", val);
2027 if (!(val & WM5100_ACCDET_VALID)) {
2028 dev_warn(wm5100->dev, "Microphone detection state invalid\n");
2032 /* No accessory, reset everything and report removal */
2033 if (!(val & WM5100_ACCDET_STS)) {
2034 dev_dbg(wm5100->dev, "Jack removal detected\n");
2035 wm5100->jack_mic = false;
2036 wm5100->jack_detecting = true;
2037 wm5100->jack_flips = 0;
2038 snd_soc_jack_report(wm5100->jack, 0,
2039 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2042 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2043 WM5100_ACCDET_RATE_MASK,
2044 WM5100_ACCDET_RATE_MASK);
2048 /* If the measurement is very high we've got a microphone,
2049 * either we just detected one or if we already reported then
2050 * we've got a button release event.
2053 if (wm5100->jack_detecting) {
2054 dev_dbg(wm5100->dev, "Microphone detected\n");
2055 wm5100->jack_mic = true;
2056 wm5100->jack_detecting = false;
2057 snd_soc_jack_report(wm5100->jack,
2059 SND_JACK_HEADSET | SND_JACK_BTN_0);
2061 /* Increase poll rate to give better responsiveness
2063 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2064 WM5100_ACCDET_RATE_MASK,
2065 5 << WM5100_ACCDET_RATE_SHIFT);
2067 dev_dbg(wm5100->dev, "Mic button up\n");
2068 snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2074 /* If we detected a lower impedence during initial startup
2075 * then we probably have the wrong polarity, flip it. Don't
2076 * do this for the lowest impedences to speed up detection of
2077 * plain headphones and give up if neither polarity looks
2080 if (wm5100->jack_detecting && (val & 0x3f8)) {
2081 wm5100->jack_flips++;
2083 if (wm5100->jack_flips > 1)
2084 wm5100_report_headphone(wm5100);
2086 wm5100_set_detect_mode(wm5100, !wm5100->jack_mode);
2091 /* Don't distinguish between buttons, just report any low
2092 * impedence as BTN_0.
2095 if (wm5100->jack_mic) {
2096 dev_dbg(wm5100->dev, "Mic button detected\n");
2097 snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2099 } else if (wm5100->jack_detecting) {
2100 wm5100_report_headphone(wm5100);
2105 int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
2107 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2110 wm5100->jack = jack;
2111 wm5100->jack_detecting = true;
2112 wm5100->jack_flips = 0;
2114 wm5100_set_detect_mode(wm5100, 0);
2116 /* Slowest detection rate, gives debounce for initial
2118 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2119 WM5100_ACCDET_BIAS_STARTTIME_MASK |
2120 WM5100_ACCDET_RATE_MASK,
2121 (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2122 WM5100_ACCDET_RATE_MASK);
2124 /* We need the charge pump to power MICBIAS */
2125 snd_soc_dapm_force_enable_pin(&codec->dapm, "CP2");
2126 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2127 snd_soc_dapm_sync(&codec->dapm);
2129 /* We start off just enabling microphone detection - even a
2130 * plain headphone will trigger detection.
2132 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2133 WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2135 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2136 WM5100_IM_ACCDET_EINT, 0);
2138 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2139 WM5100_IM_HPDET_EINT |
2140 WM5100_IM_ACCDET_EINT,
2141 WM5100_IM_HPDET_EINT |
2142 WM5100_IM_ACCDET_EINT);
2143 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2144 WM5100_ACCDET_ENA, 0);
2145 wm5100->jack = NULL;
2151 static irqreturn_t wm5100_irq(int irq, void *data)
2153 struct wm5100_priv *wm5100 = data;
2154 irqreturn_t status = IRQ_NONE;
2155 unsigned int irq_val, mask_val;
2158 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val);
2160 dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n",
2165 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK,
2168 dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n",
2173 irq_val &= ~mask_val;
2175 regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val);
2178 status = IRQ_HANDLED;
2180 wm5100_log_status3(wm5100, irq_val);
2182 if (irq_val & WM5100_FLL1_LOCK_EINT) {
2183 dev_dbg(wm5100->dev, "FLL1 locked\n");
2184 complete(&wm5100->fll[0].lock);
2186 if (irq_val & WM5100_FLL2_LOCK_EINT) {
2187 dev_dbg(wm5100->dev, "FLL2 locked\n");
2188 complete(&wm5100->fll[1].lock);
2191 if (irq_val & WM5100_ACCDET_EINT)
2192 wm5100_micd_irq(wm5100);
2194 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val);
2196 dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n",
2201 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK,
2204 dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n",
2209 irq_val &= ~mask_val;
2212 status = IRQ_HANDLED;
2214 regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val);
2216 wm5100_log_status4(wm5100, irq_val);
2221 static irqreturn_t wm5100_edge_irq(int irq, void *data)
2223 irqreturn_t ret = IRQ_NONE;
2227 val = wm5100_irq(irq, data);
2228 if (val != IRQ_NONE)
2230 } while (val != IRQ_NONE);
2235 #ifdef CONFIG_GPIOLIB
2236 static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip)
2238 return container_of(chip, struct wm5100_priv, gpio_chip);
2241 static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2243 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2245 regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2246 WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
2249 static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2250 unsigned offset, int value)
2252 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2255 val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2257 ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2258 WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2259 WM5100_GP1_LVL, val);
2266 static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2268 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2272 ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, ®);
2276 return (reg & WM5100_GP1_LVL) != 0;
2279 static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2281 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2283 return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2284 WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2285 (1 << WM5100_GP1_FN_SHIFT) |
2286 (1 << WM5100_GP1_DIR_SHIFT));
2289 static struct gpio_chip wm5100_template_chip = {
2291 .owner = THIS_MODULE,
2292 .direction_output = wm5100_gpio_direction_out,
2293 .set = wm5100_gpio_set,
2294 .direction_input = wm5100_gpio_direction_in,
2295 .get = wm5100_gpio_get,
2299 static void wm5100_init_gpio(struct i2c_client *i2c)
2301 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2304 wm5100->gpio_chip = wm5100_template_chip;
2305 wm5100->gpio_chip.ngpio = 6;
2306 wm5100->gpio_chip.dev = &i2c->dev;
2308 if (wm5100->pdata.gpio_base)
2309 wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2311 wm5100->gpio_chip.base = -1;
2313 ret = gpiochip_add(&wm5100->gpio_chip);
2315 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
2318 static void wm5100_free_gpio(struct i2c_client *i2c)
2320 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2323 ret = gpiochip_remove(&wm5100->gpio_chip);
2325 dev_err(&i2c->dev, "Failed to remove GPIOs: %d\n", ret);
2328 static void wm5100_init_gpio(struct i2c_client *i2c)
2332 static void wm5100_free_gpio(struct i2c_client *i2c)
2337 static int wm5100_probe(struct snd_soc_codec *codec)
2339 struct i2c_client *i2c = to_i2c_client(codec->dev);
2340 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2343 wm5100->codec = codec;
2344 codec->control_data = wm5100->regmap;
2346 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2348 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2352 for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2353 snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2356 /* Don't debounce interrupts to support use of SYSCLK only */
2357 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2358 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2360 /* TODO: check if we're symmetric */
2363 snd_soc_dapm_new_controls(&codec->dapm,
2364 wm5100_dapm_widgets_noirq,
2365 ARRAY_SIZE(wm5100_dapm_widgets_noirq));
2367 if (wm5100->pdata.hp_pol) {
2368 ret = gpio_request_one(wm5100->pdata.hp_pol,
2369 GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2371 dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2372 wm5100->pdata.hp_pol, ret);
2384 static int wm5100_remove(struct snd_soc_codec *codec)
2386 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2388 if (wm5100->pdata.hp_pol) {
2389 gpio_free(wm5100->pdata.hp_pol);
2395 static int wm5100_soc_volatile(struct snd_soc_codec *codec,
2402 static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2403 .probe = wm5100_probe,
2404 .remove = wm5100_remove,
2406 .set_sysclk = wm5100_set_sysclk,
2407 .set_pll = wm5100_set_fll,
2409 .reg_cache_size = WM5100_MAX_REGISTER,
2410 .volatile_register = wm5100_soc_volatile,
2412 .seq_notifier = wm5100_seq_notifier,
2413 .controls = wm5100_snd_controls,
2414 .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2415 .dapm_widgets = wm5100_dapm_widgets,
2416 .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2417 .dapm_routes = wm5100_dapm_routes,
2418 .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
2421 static const struct regmap_config wm5100_regmap = {
2425 .max_register = WM5100_MAX_REGISTER,
2426 .reg_defaults = wm5100_reg_defaults,
2427 .num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
2428 .volatile_reg = wm5100_volatile_register,
2429 .readable_reg = wm5100_readable_register,
2430 .cache_type = REGCACHE_RBTREE,
2433 static const unsigned int wm5100_mic_ctrl_reg[] = {
2434 WM5100_IN1L_CONTROL,
2435 WM5100_IN2L_CONTROL,
2436 WM5100_IN3L_CONTROL,
2437 WM5100_IN4L_CONTROL,
2440 static __devinit int wm5100_i2c_probe(struct i2c_client *i2c,
2441 const struct i2c_device_id *id)
2443 struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2444 struct wm5100_priv *wm5100;
2446 int ret, i, irq_flags;
2448 wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
2453 wm5100->dev = &i2c->dev;
2455 wm5100->regmap = regmap_init_i2c(i2c, &wm5100_regmap);
2456 if (IS_ERR(wm5100->regmap)) {
2457 ret = PTR_ERR(wm5100->regmap);
2458 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2463 for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2464 init_completion(&wm5100->fll[i].lock);
2467 wm5100->pdata = *pdata;
2469 i2c_set_clientdata(i2c, wm5100);
2471 for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2472 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2474 ret = devm_regulator_bulk_get(&i2c->dev,
2475 ARRAY_SIZE(wm5100->core_supplies),
2476 wm5100->core_supplies);
2478 dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2483 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2484 wm5100->core_supplies);
2486 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2491 if (wm5100->pdata.ldo_ena) {
2492 ret = gpio_request_one(wm5100->pdata.ldo_ena,
2493 GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2495 dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2496 wm5100->pdata.ldo_ena, ret);
2502 if (wm5100->pdata.reset) {
2503 ret = gpio_request_one(wm5100->pdata.reset,
2504 GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2506 dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2507 wm5100->pdata.reset, ret);
2512 ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, ®);
2514 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2523 dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
2528 ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, ®);
2530 dev_err(&i2c->dev, "Failed to read revision register\n");
2533 wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
2535 dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
2537 ret = wm5100_reset(wm5100);
2539 dev_err(&i2c->dev, "Failed to issue reset\n");
2543 switch (wm5100->rev) {
2545 ret = regmap_register_patch(wm5100->regmap,
2546 wm5100_reva_patches,
2547 ARRAY_SIZE(wm5100_reva_patches));
2549 dev_err(&i2c->dev, "Failed to register patches: %d\n",
2559 wm5100_init_gpio(i2c);
2561 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2562 if (!wm5100->pdata.gpio_defaults[i])
2565 regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
2566 wm5100->pdata.gpio_defaults[i]);
2569 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2570 regmap_update_bits(wm5100->regmap, wm5100_mic_ctrl_reg[i],
2571 WM5100_IN1_MODE_MASK |
2572 WM5100_IN1_DMIC_SUP_MASK,
2573 (wm5100->pdata.in_mode[i] <<
2574 WM5100_IN1_MODE_SHIFT) |
2575 (wm5100->pdata.dmic_sup[i] <<
2576 WM5100_IN1_DMIC_SUP_SHIFT));
2580 if (wm5100->pdata.irq_flags)
2581 irq_flags = wm5100->pdata.irq_flags;
2583 irq_flags = IRQF_TRIGGER_LOW;
2585 irq_flags |= IRQF_ONESHOT;
2587 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2588 ret = request_threaded_irq(i2c->irq, NULL,
2589 wm5100_edge_irq, irq_flags,
2592 ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2593 irq_flags, "wm5100",
2597 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2600 /* Enable default interrupts */
2601 regmap_update_bits(wm5100->regmap,
2602 WM5100_INTERRUPT_STATUS_3_MASK,
2603 WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2604 WM5100_IM_SPK_SHUTDOWN_EINT |
2605 WM5100_IM_ASRC2_LOCK_EINT |
2606 WM5100_IM_ASRC1_LOCK_EINT |
2607 WM5100_IM_FLL2_LOCK_EINT |
2608 WM5100_IM_FLL1_LOCK_EINT |
2609 WM5100_CLKGEN_ERR_EINT |
2610 WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2612 regmap_update_bits(wm5100->regmap,
2613 WM5100_INTERRUPT_STATUS_4_MASK,
2614 WM5100_AIF3_ERR_EINT |
2615 WM5100_AIF2_ERR_EINT |
2616 WM5100_AIF1_ERR_EINT |
2617 WM5100_CTRLIF_ERR_EINT |
2618 WM5100_ISRC2_UNDERCLOCKED_EINT |
2619 WM5100_ISRC1_UNDERCLOCKED_EINT |
2620 WM5100_FX_UNDERCLOCKED_EINT |
2621 WM5100_AIF3_UNDERCLOCKED_EINT |
2622 WM5100_AIF2_UNDERCLOCKED_EINT |
2623 WM5100_AIF1_UNDERCLOCKED_EINT |
2624 WM5100_ASRC_UNDERCLOCKED_EINT |
2625 WM5100_DAC_UNDERCLOCKED_EINT |
2626 WM5100_ADC_UNDERCLOCKED_EINT |
2627 WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2631 pm_runtime_set_active(&i2c->dev);
2632 pm_runtime_enable(&i2c->dev);
2633 pm_request_idle(&i2c->dev);
2635 ret = snd_soc_register_codec(&i2c->dev,
2636 &soc_codec_dev_wm5100, wm5100_dai,
2637 ARRAY_SIZE(wm5100_dai));
2639 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
2647 free_irq(i2c->irq, wm5100);
2648 wm5100_free_gpio(i2c);
2649 if (wm5100->pdata.reset) {
2650 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
2651 gpio_free(wm5100->pdata.reset);
2654 if (wm5100->pdata.ldo_ena) {
2655 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2656 gpio_free(wm5100->pdata.ldo_ena);
2659 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2660 wm5100->core_supplies);
2662 regmap_exit(wm5100->regmap);
2667 static __devexit int wm5100_i2c_remove(struct i2c_client *i2c)
2669 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
2671 snd_soc_unregister_codec(&i2c->dev);
2673 free_irq(i2c->irq, wm5100);
2674 wm5100_free_gpio(i2c);
2675 if (wm5100->pdata.reset) {
2676 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
2677 gpio_free(wm5100->pdata.reset);
2679 if (wm5100->pdata.ldo_ena) {
2680 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2681 gpio_free(wm5100->pdata.ldo_ena);
2683 regmap_exit(wm5100->regmap);
2688 #ifdef CONFIG_PM_RUNTIME
2689 static int wm5100_runtime_suspend(struct device *dev)
2691 struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2693 regcache_cache_only(wm5100->regmap, true);
2694 regcache_mark_dirty(wm5100->regmap);
2695 if (wm5100->pdata.ldo_ena)
2696 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2697 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2698 wm5100->core_supplies);
2703 static int wm5100_runtime_resume(struct device *dev)
2705 struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2708 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2709 wm5100->core_supplies);
2711 dev_err(dev, "Failed to enable supplies: %d\n",
2716 if (wm5100->pdata.ldo_ena) {
2717 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 1);
2721 regcache_cache_only(wm5100->regmap, false);
2722 regcache_sync(wm5100->regmap);
2728 static struct dev_pm_ops wm5100_pm = {
2729 SET_RUNTIME_PM_OPS(wm5100_runtime_suspend, wm5100_runtime_resume,
2733 static const struct i2c_device_id wm5100_i2c_id[] = {
2737 MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2739 static struct i2c_driver wm5100_i2c_driver = {
2742 .owner = THIS_MODULE,
2745 .probe = wm5100_i2c_probe,
2746 .remove = __devexit_p(wm5100_i2c_remove),
2747 .id_table = wm5100_i2c_id,
2750 static int __init wm5100_modinit(void)
2752 return i2c_add_driver(&wm5100_i2c_driver);
2754 module_init(wm5100_modinit);
2756 static void __exit wm5100_exit(void)
2758 i2c_del_driver(&wm5100_i2c_driver);
2760 module_exit(wm5100_exit);
2762 MODULE_DESCRIPTION("ASoC WM5100 driver");
2763 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2764 MODULE_LICENSE("GPL");