sound/soc/codecs/wm8900.c

   1 /*
   2  * wm8900.c  --  WM8900 ALSA Soc Audio driver
   3  *
   4  * Copyright 2007, 2008 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * TODO:
  13  *  - Tristating.
  14  *  - TDM.
  15  *  - Jack detect.
  16  *  - FLL source configuration, currently only MCLK is supported.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/platform_device.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/soc.h>
  31 #include <sound/soc-dapm.h>
  32 #include <sound/initval.h>
  33 #include <sound/tlv.h>
  34
  35 #include "wm8900.h"
  36
  37
  38 #if 0
  39 #define WM8900_DBG(x...)        printk(KERN_INFO x)
  40 #else
  41 #define WM8900_DBG(x...)
  42 #endif
  43
  44 /* WM8900 register space */
  45 #define WM8900_REG_RESET        0x0
  46 #define WM8900_REG_ID           0x0
  47 #define WM8900_REG_POWER1       0x1
  48 #define WM8900_REG_POWER2       0x2
  49 #define WM8900_REG_POWER3       0x3
  50 #define WM8900_REG_AUDIO1       0x4
  51 #define WM8900_REG_AUDIO2       0x5
  52 #define WM8900_REG_CLOCKING1    0x6
  53 #define WM8900_REG_CLOCKING2    0x7
  54 #define WM8900_REG_AUDIO3       0x8
  55 #define WM8900_REG_AUDIO4       0x9
  56 #define WM8900_REG_DACCTRL      0xa
  57 #define WM8900_REG_LDAC_DV      0xb
  58 #define WM8900_REG_RDAC_DV      0xc
  59 #define WM8900_REG_SIDETONE     0xd
  60 #define WM8900_REG_ADCCTRL      0xe
  61 #define WM8900_REG_LADC_DV      0xf
  62 #define WM8900_REG_RADC_DV      0x10
  63 #define WM8900_REG_GPIO         0x12
  64 #define WM8900_REG_INCTL        0x15
  65 #define WM8900_REG_LINVOL       0x16
  66 #define WM8900_REG_RINVOL       0x17
  67 #define WM8900_REG_INBOOSTMIX1  0x18
  68 #define WM8900_REG_INBOOSTMIX2  0x19
  69 #define WM8900_REG_ADCPATH      0x1a
  70 #define WM8900_REG_AUXBOOST     0x1b
  71 #define WM8900_REG_ADDCTL       0x1e
  72 #define WM8900_REG_FLLCTL1      0x24
  73 #define WM8900_REG_FLLCTL2      0x25
  74 #define WM8900_REG_FLLCTL3      0x26
  75 #define WM8900_REG_FLLCTL4      0x27
  76 #define WM8900_REG_FLLCTL5      0x28
  77 #define WM8900_REG_FLLCTL6      0x29
  78 #define WM8900_REG_LOUTMIXCTL1  0x2c
  79 #define WM8900_REG_ROUTMIXCTL1  0x2d
  80 #define WM8900_REG_BYPASS1      0x2e
  81 #define WM8900_REG_BYPASS2      0x2f
  82 #define WM8900_REG_AUXOUT_CTL   0x30
  83 #define WM8900_REG_LOUT1CTL     0x33
  84 #define WM8900_REG_ROUT1CTL     0x34
  85 #define WM8900_REG_LOUT2CTL     0x35
  86 #define WM8900_REG_ROUT2CTL     0x36
  87 #define WM8900_REG_HPCTL1       0x3a
  88 #define WM8900_REG_OUTBIASCTL   0x73
  89
  90 #define WM8900_MAXREG           0x80
  91
  92 #define WM8900_REG_ADDCTL_OUT1_DIS    0x80
  93 #define WM8900_REG_ADDCTL_OUT2_DIS    0x40
  94 #define WM8900_REG_ADDCTL_VMID_DIS    0x20
  95 #define WM8900_REG_ADDCTL_BIAS_SRC    0x10
  96 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
  97 #define WM8900_REG_ADDCTL_TEMP_SD     0x02
  98
  99 #define WM8900_REG_GPIO_TEMP_ENA   0x2
 100
 101 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
 102 #define WM8900_REG_POWER1_BIAS_ENA         0x0008
 103 #define WM8900_REG_POWER1_VMID_BUF_ENA     0x0004
 104 #define WM8900_REG_POWER1_FLL_ENA          0x0040
 105
 106 #define WM8900_REG_POWER2_SYSCLK_ENA  0x8000
 107 #define WM8900_REG_POWER2_ADCL_ENA    0x0002
 108 #define WM8900_REG_POWER2_ADCR_ENA    0x0001
 109
 110 #define WM8900_REG_POWER3_DACL_ENA    0x0002
 111 #define WM8900_REG_POWER3_DACR_ENA    0x0001
 112
 113 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
 114 #define WM8900_REG_AUDIO1_LRCLK_INV    0x0080
 115 #define WM8900_REG_AUDIO1_BCLK_INV     0x0100
 116
 117 #define WM8900_REG_CLOCKING1_BCLK_DIR   0x1
 118 #define WM8900_REG_CLOCKING1_MCLK_SRC   0x100
 119 #define WM8900_REG_CLOCKING1_BCLK_MASK  (~0x01e)
 120 #define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
 121
 122 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0x1c
 123 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0xe0
 124
 125 #define WM8900_REG_DACCTRL_MUTE          0x004
 126 #define WM8900_REG_DACCTRL_DAC_SB_FILT   0x100
 127 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
 128
 129 #define WM8900_REG_AUDIO3_ADCLRC_DIR    0x0800
 130
 131 #define WM8900_REG_AUDIO4_DACLRC_DIR    0x0800
 132
 133 #define WM8900_REG_FLLCTL1_OSC_ENA    0x100
 134
 135 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
 136
 137 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
 138 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
 139 #define WM8900_REG_HPCTL1_HP_CLAMP_IP    0x20
 140 #define WM8900_REG_HPCTL1_HP_CLAMP_OP    0x10
 141 #define WM8900_REG_HPCTL1_HP_SHORT       0x08
 142 #define WM8900_REG_HPCTL1_HP_SHORT2      0x04
 143
 144 #define WM8900_LRC_MASK 0xfc00
 145
 146 struct snd_soc_codec_device soc_codec_dev_wm8900;
 147
 148 struct wm8900_priv {
 149         struct snd_soc_codec codec;
 150
 151         u16 reg_cache[WM8900_MAXREG];
 152
 153         u32 fll_in; /* FLL input frequency */
 154         u32 fll_out; /* FLL output frequency */
 155 };
 156
 157 /*
 158  * wm8900 register cache.  We can't read the entire register space and we
 159  * have slow control buses so we cache the registers.
 160  */
 161 static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
 162         0x8900, 0x0000,
 163         0xc000, 0x0000,
 164         0x4050, 0x4000,
 165         0x0008, 0x0000,
 166         0x0040, 0x0040,
 167         0x1004, 0x00c0,
 168         0x00c0, 0x0000,
 169         0x0100, 0x00c0,
 170         0x00c0, 0x0000,
 171         0xb001, 0x0000,
 172         0x0000, 0x0044,
 173         0x004c, 0x004c,
 174         0x0044, 0x0044,
 175         0x0000, 0x0044,
 176         0x0000, 0x0000,
 177         0x0002, 0x0000,
 178         0x0000, 0x0000,
 179         0x0000, 0x0000,
 180         0x0008, 0x0000,
 181         0x0000, 0x0008,
 182         0x0097, 0x0100,
 183         0x0000, 0x0000,
 184         0x0050, 0x0050,
 185         0x0055, 0x0055,
 186         0x0055, 0x0000,
 187         0x0000, 0x0079,
 188         0x0079, 0x0079,
 189         0x0079, 0x0000,
 190         /* Remaining registers all zero */
 191 };
 192
 193 static int wm8900_volatile_register(unsigned int reg)
 194 {
 195         switch (reg) {
 196         case WM8900_REG_ID:
 197         case WM8900_REG_POWER1:
 198                 return 1;
 199         default:
 200                 return 0;
 201         }
 202 }
 203
 204 static void wm8900_reset(struct snd_soc_codec *codec)
 205 {
 206         WM8900_DBG("Enter:%s, %d, codec=0x%8X \n", __FUNCTION__, __LINE__,codec);
 207         snd_soc_write(codec, WM8900_REG_RESET, 0);
 208
 209         memcpy(codec->reg_cache, wm8900_reg_defaults,
 210                sizeof(codec->reg_cache));
 211 }
 212
 213 static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
 214                            struct snd_kcontrol *kcontrol, int event)
 215 {
 216         struct snd_soc_codec *codec = w->codec;
 217         u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
 218
 219         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
 220
 221         switch (event) {
 222         case SND_SOC_DAPM_PRE_PMU:
 223                 /* Clamp headphone outputs */
 224                 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
 225                         WM8900_REG_HPCTL1_HP_CLAMP_OP;
 226                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
 227                 WM8900_DBG("Enter:%s, %d, HPCTL=0x%04X \n", __FUNCTION__, __LINE__, hpctl1);
 228                 break;
 229
 230         case SND_SOC_DAPM_POST_PMU:
 231                 /* Enable the input stage */
 232                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
 233                 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
 234                         WM8900_REG_HPCTL1_HP_SHORT2 |
 235                         WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
 236                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
 237
 238                 msleep(400);
 239
 240                 /* Enable the output stage */
 241                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
 242                 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
 243                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
 244
 245                 /* Remove the shorts */
 246                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
 247                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
 248                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
 249                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
 250                 WM8900_DBG("Enter:%s, %d, HPCTL=0x%04X \n", __FUNCTION__, __LINE__, hpctl1);
 251                 break;
 252
 253         case SND_SOC_DAPM_PRE_PMD:
 254                 /* Short the output */
 255                 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
 256                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
 257
 258                 /* Disable the output stage */
 259                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
 260                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
 261
 262                 /* Clamp the outputs and power down input */
 263                 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
 264                         WM8900_REG_HPCTL1_HP_CLAMP_OP;
 265                 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
 266                 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
 267                 WM8900_DBG("Enter:%s, %d, HPCTL=0x%04X \n", __FUNCTION__, __LINE__, hpctl1);
 268                 break;
 269
 270         case SND_SOC_DAPM_POST_PMD:
 271                 /* Disable everything */
 272                 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
 273                 WM8900_DBG("Enter:%s, %d, HPCTL=0x%04X \n", __FUNCTION__, __LINE__, hpctl1);
 274                 break;
 275
 276         default:
 277                 BUG();
 278         }
 279
 280         return 0;
 281 }
 282
 283 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
 284
 285 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
 286
 287 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
 288
 289 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
 290
 291 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
 292
 293 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
 294
 295 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
 296
 297 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
 298
 299 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
 300
 301 static const struct soc_enum mic_bias_level =
 302 SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
 303
 304 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
 305
 306 static const struct soc_enum dac_mute_rate =
 307 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
 308
 309 static const char *dac_deemphasis_txt[] = {
 310         "Disabled", "32kHz", "44.1kHz", "48kHz"
 311 };
 312
 313 static const struct soc_enum dac_deemphasis =
 314 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
 315
 316 static const char *adc_hpf_cut_txt[] = {
 317         "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
 318 };
 319
 320 static const struct soc_enum adc_hpf_cut =
 321 SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
 322
 323 static const char *lr_txt[] = {
 324         "Left", "Right"
 325 };
 326
 327 static const struct soc_enum aifl_src =
 328 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
 329
 330 static const struct soc_enum aifr_src =
 331 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
 332
 333 static const struct soc_enum dacl_src =
 334 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
 335
 336 static const struct soc_enum dacr_src =
 337 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
 338
 339 static const char *sidetone_txt[] = {
 340         "Disabled", "Left ADC", "Right ADC"
 341 };
 342
 343 static const struct soc_enum dacl_sidetone =
 344 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
 345
 346 static const struct soc_enum dacr_sidetone =
 347 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
 348
 349 static const struct snd_kcontrol_new wm8900_snd_controls[] = {
 350 SOC_ENUM("Mic Bias Level", mic_bias_level),
 351
 352 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
 353                in_pga_tlv),
 354 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
 355 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
 356
 357 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
 358                in_pga_tlv),
 359 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
 360 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
 361
 362 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
 363 SOC_ENUM("DAC Mute Rate", dac_mute_rate),
 364 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
 365 SOC_ENUM("DAC Deemphasis", dac_deemphasis),
 366 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
 367            12, 1, 0),
 368
 369 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
 370 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
 371 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
 372 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
 373                adc_svol_tlv),
 374 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
 375                adc_svol_tlv),
 376 SOC_ENUM("Left Digital Audio Source", aifl_src),
 377 SOC_ENUM("Right Digital Audio Source", aifr_src),
 378
 379 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
 380                dac_boost_tlv),
 381 SOC_ENUM("Left DAC Source", dacl_src),
 382 SOC_ENUM("Right DAC Source", dacr_src),
 383 SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
 384 SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
 385 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
 386
 387 SOC_DOUBLE_R_TLV("Digital Playback Volume",
 388                  WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
 389                  1, 96, 0, dac_tlv),
 390 SOC_DOUBLE_R_TLV("Digital Capture Volume",
 391                  WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
 392
 393 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
 394                out_mix_tlv),
 395 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
 396                out_mix_tlv),
 397 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
 398                out_mix_tlv),
 399 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
 400                out_mix_tlv),
 401
 402 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
 403                out_mix_tlv),
 404 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
 405                out_mix_tlv),
 406 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
 407                out_mix_tlv),
 408 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
 409                out_mix_tlv),
 410
 411 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
 412                in_boost_tlv),
 413 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
 414                in_boost_tlv),
 415 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
 416                in_boost_tlv),
 417 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
 418                in_boost_tlv),
 419 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
 420                in_boost_tlv),
 421 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
 422                in_boost_tlv),
 423
 424 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
 425                0, 63, 0, out_pga_tlv),
 426 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
 427              6, 1, 1),
 428 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
 429              7, 1, 0),
 430
 431 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
 432                  WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
 433                  0, 63, 0, out_pga_tlv),
 434 SOC_DOUBLE_R("LINEOUT2 Switch",
 435              WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
 436 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
 437              WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
 438 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
 439            0, 1, 1),
 440
 441 };
 442
 443 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control[] = {
 444 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0),};
 445
 446 static const struct snd_kcontrol_new wm8900_dapm_routput2_control[] = {
 447 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0),};
 448
 449 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
 450 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
 451 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
 452 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
 453 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
 454 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
 455 };
 456
 457 static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
 458 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
 459 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
 460 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
 461 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
 462 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
 463 };
 464
 465 static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
 466 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
 467 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
 468 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
 469 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
 470 };
 471
 472 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
 473 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
 474 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
 475 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
 476 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
 477 };
 478
 479 static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
 480 SOC_SINGLE("MIC LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
 481 SOC_SINGLE("MIC LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
 482 SOC_SINGLE("MIC LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
 483 };
 484
 485 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
 486 SOC_SINGLE("MIC RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
 487 SOC_SINGLE("MIC RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
 488 SOC_SINGLE("MIC RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
 489 };
 490
 491 static const struct snd_kcontrol_new wm8900_inmix_controls[] = {
 492 SOC_SINGLE("LINPUT PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
 493 SOC_SINGLE("RINPUT PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
 494 };
 495
 496 static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
 497
 498 static const struct soc_enum wm8900_lineout2_lp_mux =
 499 SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
 500
 501 static const struct snd_kcontrol_new wm8900_lineout2_lp =
 502 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
 503
 504 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
 505
 506 /* Externally visible pins */
 507 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
 508 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
 509 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
 510 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
 511 SND_SOC_DAPM_OUTPUT("HP_L"),
 512 SND_SOC_DAPM_OUTPUT("HP_R"),
 513
 514 SND_SOC_DAPM_INPUT("RINPUT1"),
 515 SND_SOC_DAPM_INPUT("LINPUT1"),
 516 SND_SOC_DAPM_INPUT("RINPUT2"),
 517 SND_SOC_DAPM_INPUT("LINPUT2"),
 518 SND_SOC_DAPM_INPUT("RINPUT3"),
 519 SND_SOC_DAPM_INPUT("LINPUT3"),
 520 SND_SOC_DAPM_INPUT("AUX"),
 521
 522 SND_SOC_DAPM_VMID("VMID"),
 523
 524 /* Input */
 525 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
 526                    wm8900_linpga_controls,
 527                    ARRAY_SIZE(wm8900_linpga_controls)),
 528 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
 529                    wm8900_rinpga_controls,
 530                    ARRAY_SIZE(wm8900_rinpga_controls)),
 531
 532 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
 533                    wm8900_linmix_controls,
 534                    ARRAY_SIZE(wm8900_linmix_controls)),
 535 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
 536                    wm8900_rinmix_controls,
 537                    ARRAY_SIZE(wm8900_rinmix_controls)),
 538
 539 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
 540
 541 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
 542 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
 543
 544 /* Output */
 545 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
 546 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
 547
 548 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
 549                    wm8900_hp_event,
 550                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 551                    SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 552
 553 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
 554 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
 555
 556 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
 557 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
 558 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
 559
 560 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
 561                    wm8900_loutmix_controls,
 562                    ARRAY_SIZE(wm8900_loutmix_controls)),
 563 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
 564                    wm8900_routmix_controls,
 565                    ARRAY_SIZE(wm8900_routmix_controls)),
 566 };
 567
 568 /* Target, Path, Source */
 569 static const struct snd_soc_dapm_route audio_map[] = {
 570 /* Inputs */
 571 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
 572 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
 573 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
 574
 575 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
 576 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
 577 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
 578
 579 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
 580 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
 581 {"Left Input Mixer", "AUX Switch", "AUX"},
 582 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
 583
 584 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
 585 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
 586 {"Right Input Mixer", "AUX Switch", "AUX"},
 587 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
 588
 589 {"ADCL", NULL, "Left Input Mixer"},
 590 {"ADCR", NULL, "Right Input Mixer"},
 591
 592 /* Outputs */
 593 {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
 594 {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
 595 {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
 596 {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
 597
 598 {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
 599 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
 600 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
 601 {"LINEOUT2L", NULL, "LINEOUT2 LP"},
 602
 603 {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
 604 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
 605 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
 606 {"LINEOUT2R", NULL, "LINEOUT2 LP"},
 607
 608 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
 609 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
 610 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
 611 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
 612 {"Left Output Mixer", "DACL Switch", "DACL"},
 613
 614 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
 615 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
 616 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
 617 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
 618 {"Right Output Mixer", "DACR Switch", "DACR"},
 619
 620 /* Note that the headphone output stage needs to be connected
 621  * externally to LINEOUT2 via DC blocking capacitors.  Other
 622  * configurations are not supported.
 623  *
 624  * Note also that left and right headphone paths are treated as a
 625  * mono path.
 626  */
 627 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
 628 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
 629 {"HP_L", NULL, "Headphone Amplifier"},
 630 {"HP_R", NULL, "Headphone Amplifier"},
 631 };
 632
 633 static int wm8900_add_widgets(struct snd_soc_codec *codec)
 634 {
 635         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
 636
 637         snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets,
 638                                   ARRAY_SIZE(wm8900_dapm_widgets));
 639         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
 640         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 641         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
 642         snd_soc_dapm_new_widgets(codec);
 643
 644         return 0;
 645 }
 646
 647 static int wm8900_hw_params(struct snd_pcm_substream *substream,
 648         struct snd_pcm_hw_params *params,
 649         struct snd_soc_dai *dai)
 650 {
 651         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 652         struct snd_soc_device *socdev = rtd->socdev;
 653         struct snd_soc_codec *codec = socdev->card->codec;
 654         u16 reg;
 655
 656         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
 657
 658         reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
 659
 660         switch (params_format(params)) {
 661         case SNDRV_PCM_FORMAT_S16_LE:
 662                 break;
 663         case SNDRV_PCM_FORMAT_S20_3LE:
 664                 reg |= 0x20;
 665                 break;
 666         case SNDRV_PCM_FORMAT_S24_LE:
 667                 reg |= 0x40;
 668                 break;
 669         case SNDRV_PCM_FORMAT_S32_LE:
 670                 reg |= 0x60;
 671                 break;
 672         default:
 673                 return -EINVAL;
 674         }
 675
 676         snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
 677
 678         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 679                 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
 680
 681                 if (params_rate(params) <= 24000)
 682                         reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
 683                 else
 684                         reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
 685
 686                 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
 687         }
 688                 snd_soc_write(codec, WM8900_REG_POWER3, 0xEF);
 689
 690                 snd_soc_write(codec, WM8900_REG_LOUTMIXCTL1, 0x150);
 691                 snd_soc_write(codec, WM8900_REG_ROUTMIXCTL1, 0x150);
 692                 snd_soc_write(codec, WM8900_REG_LOUT2CTL, 0x139);
 693                 snd_soc_write(codec, WM8900_REG_ROUT2CTL, 0x139);
 694                 snd_soc_write(codec, WM8900_REG_HPCTL1, 0xC0);
 695         //} else {
 696                 snd_soc_write(codec, WM8900_REG_POWER1, 0x211D);
 697                 snd_soc_write(codec, WM8900_REG_POWER2, 0xC03F);
 698
 699                 //User for asound.conf File
 700                 snd_soc_write(codec, WM8900_REG_LADC_DV, 0x00C1);
 701                 snd_soc_write(codec, WM8900_REG_RADC_DV, 0x01C0);
 702
 703                 snd_soc_write(codec, WM8900_REG_INCTL, 0x0040);
 704
 705                 snd_soc_write(codec, WM8900_REG_LINVOL, 0x0115);
 706                 snd_soc_write(codec, WM8900_REG_RINVOL, 0x0115);
 707                 snd_soc_write(codec, WM8900_REG_INBOOSTMIX1, 0x0042);
 708                 snd_soc_write(codec, WM8900_REG_INBOOSTMIX2, 0x0042);
 709                 snd_soc_write(codec, WM8900_REG_ADCPATH, 0x0055);
 710
 711
 712                 /*
 713                 // MIC to DAC
 714                 snd_soc_write(codec, 0x01, 0x211D);
 715                 snd_soc_write(codec, 0x02, 0xC03C);
 716                 snd_soc_write(codec, 0x03, 0x00EC);
 717                 snd_soc_write(codec, 0x16, 0x0115);
 718                 snd_soc_write(codec, 0x17, 0x0115);
 719                 snd_soc_write(codec, 0x1A, 0x0077);
 720
 721                 snd_soc_write(codec, 0x2E, 0x00DD);
 722                 snd_soc_write(codec, 0x35, 0x011F);
 723                 snd_soc_write(codec, 0x36, 0x011F);
 724                 snd_soc_write(codec, 0x3A, 0x00C0);
 725                 */
 726         //}
 727         WM8900_DBG("<<<<<<<<<<<<<<<<<<<<Exit:%s, %d \n", __FUNCTION__, __LINE__);
 728         return 0;
 729 }
 730
 731 /* FLL divisors */
 732 struct _fll_div {
 733         u16 fll_ratio;
 734         u16 fllclk_div;
 735         u16 fll_slow_lock_ref;
 736         u16 n;
 737         u16 k;
 738 };
 739
 740 /* The size in bits of the FLL divide multiplied by 10
 741  * to allow rounding later */
 742 #define FIXED_FLL_SIZE ((1 << 16) * 10)
 743
 744 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
 745                        unsigned int Fout)
 746 {
 747         u64 Kpart;
 748         unsigned int K, Ndiv, Nmod, target;
 749         unsigned int div;
 750
 751         BUG_ON(!Fout);
 752
 753         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
 754
 755         /* The FLL must run at 90-100MHz which is then scaled down to
 756          * the output value by FLLCLK_DIV. */
 757         target = Fout;
 758         div = 1;
 759         while (target < 90000000) {
 760                 div *= 2;
 761                 target *= 2;
 762         }
 763
 764         if (target > 100000000)
 765                 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
 766                        " Fout=%u\n", target, Fref, Fout);
 767         if (div > 32) {
 768                 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
 769                        "Fref=%u, Fout=%u, target=%u\n",
 770                        div, Fref, Fout, target);
 771                 return -EINVAL;
 772         }
 773
 774         fll_div->fllclk_div = div >> 2;
 775
 776         if (Fref < 48000)
 777                 fll_div->fll_slow_lock_ref = 1;
 778         else
 779                 fll_div->fll_slow_lock_ref = 0;
 780
 781         Ndiv = target / Fref;
 782
 783         if (Fref < 1000000)
 784                 fll_div->fll_ratio = 8;
 785         else
 786                 fll_div->fll_ratio = 1;
 787
 788         fll_div->n = Ndiv / fll_div->fll_ratio;
 789         Nmod = (target / fll_div->fll_ratio) % Fref;
 790
 791         /* Calculate fractional part - scale up so we can round. */
 792         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
 793
 794         do_div(Kpart, Fref);
 795
 796         K = Kpart & 0xFFFFFFFF;
 797
 798         if ((K % 10) >= 5)
 799                 K += 5;
 800
 801         /* Move down to proper range now rounding is done */
 802         fll_div->k = K / 10;
 803
 804         BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
 805         BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
 806
 807         return 0;
 808 }
 809
 810 static int wm8900_set_fll(struct snd_soc_codec *codec,
 811         int fll_id, unsigned int freq_in, unsigned int freq_out)
 812 {
 813         struct wm8900_priv *wm8900 = codec->private_data;
 814         struct _fll_div fll_div;
 815         unsigned int reg;
 816
 817         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
 818
 819         if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
 820                 return 0;
 821
 822         /* The digital side should be disabled during any change. */
 823         reg = snd_soc_read(codec, WM8900_REG_POWER1);
 824         snd_soc_write(codec, WM8900_REG_POWER1,
 825                      reg & (~WM8900_REG_POWER1_FLL_ENA));
 826
 827         /* Disable the FLL? */
 828         if (!freq_in || !freq_out) {
 829                 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
 830                 snd_soc_write(codec, WM8900_REG_CLOCKING1,
 831                              reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
 832
 833                 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
 834                 snd_soc_write(codec, WM8900_REG_FLLCTL1,
 835                              reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
 836
 837                 wm8900->fll_in = freq_in;
 838                 wm8900->fll_out = freq_out;
 839
 840                 return 0;
 841         }
 842
 843         if (fll_factors(&fll_div, freq_in, freq_out) != 0)
 844                 goto reenable;
 845
 846         wm8900->fll_in = freq_in;
 847         wm8900->fll_out = freq_out;
 848
 849         /* The osclilator *MUST* be enabled before we enable the
 850          * digital circuit. */
 851         snd_soc_write(codec, WM8900_REG_FLLCTL1,
 852                      fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
 853
 854         snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
 855         snd_soc_write(codec, WM8900_REG_FLLCTL5,
 856                      (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
 857
 858         if (fll_div.k) {
 859                 snd_soc_write(codec, WM8900_REG_FLLCTL2,
 860                              (fll_div.k >> 8) | 0x100);
 861                 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
 862         } else
 863                 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
 864
 865         if (fll_div.fll_slow_lock_ref)
 866                 snd_soc_write(codec, WM8900_REG_FLLCTL6,
 867                              WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
 868         else
 869                 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
 870
 871         reg = snd_soc_read(codec, WM8900_REG_POWER1);
 872         snd_soc_write(codec, WM8900_REG_POWER1,
 873                      reg | WM8900_REG_POWER1_FLL_ENA);
 874
 875 reenable:
 876         reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
 877         snd_soc_write(codec, WM8900_REG_CLOCKING1,
 878                      reg | WM8900_REG_CLOCKING1_MCLK_SRC);
 879
 880         return 0;
 881 }
 882
 883 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai,
 884                 int pll_id, unsigned int freq_in, unsigned int freq_out)
 885 {
 886         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
 887         return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
 888 }
 889
 890 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 891                                  int div_id, int div)
 892 {
 893         struct snd_soc_codec *codec = codec_dai->codec;
 894         unsigned int reg;
 895         WM8900_DBG("Enter:%s, %d, div_id=%d, div=%d \n", __FUNCTION__, __LINE__, div_id, div);
 896
 897         switch (div_id) {
 898         case WM8900_BCLK_DIV:
 899                 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
 900                 snd_soc_write(codec, WM8900_REG_CLOCKING1,
 901                              div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
 902                 break;
 903         case WM8900_OPCLK_DIV:
 904                 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
 905                 snd_soc_write(codec, WM8900_REG_CLOCKING1,
 906                              div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
 907                 break;
 908         case WM8900_DAC_LRCLK:
 909                 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
 910                 snd_soc_write(codec, WM8900_REG_AUDIO4,
 911                              div | (reg & WM8900_LRC_MASK));
 912                 break;
 913         case WM8900_ADC_LRCLK:
 914                 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
 915                 snd_soc_write(codec, WM8900_REG_AUDIO3,
 916                              div | (reg & WM8900_LRC_MASK));
 917                 break;
 918         case WM8900_DAC_CLKDIV:
 919                 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
 920                 snd_soc_write(codec, WM8900_REG_CLOCKING2,
 921                              div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
 922                 break;
 923         case WM8900_ADC_CLKDIV:
 924                 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
 925                 snd_soc_write(codec, WM8900_REG_CLOCKING2,
 926                              div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
 927                 break;
 928         case WM8900_LRCLK_MODE:
 929                 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
 930                 snd_soc_write(codec, WM8900_REG_DACCTRL,
 931                              div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
 932                 break;
 933         default:
 934                 return -EINVAL;
 935         }
 936
 937         return 0;
 938 }
 939
 940
 941 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
 942                               unsigned int fmt)
 943 {
 944         struct snd_soc_codec *codec = codec_dai->codec;
 945         unsigned int clocking1, aif1, aif3, aif4;
 946
 947         WM8900_DBG("Enter:%s, %d, fmt=0x%08X \n", __FUNCTION__, __LINE__, fmt);
 948
 949         clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
 950         aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
 951         aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
 952         aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
 953
 954         /* set master/slave audio interface */
 955         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 956         case SND_SOC_DAIFMT_CBS_CFS:
 957                 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
 958                 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
 959                 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
 960                 break;
 961         case SND_SOC_DAIFMT_CBS_CFM:
 962                 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
 963                 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
 964                 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
 965                 break;
 966         case SND_SOC_DAIFMT_CBM_CFM:
 967                 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
 968                 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
 969                 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
 970                 break;
 971         case SND_SOC_DAIFMT_CBM_CFS:
 972                 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
 973                 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
 974                 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
 975                 break;
 976         default:
 977                 return -EINVAL;
 978         }
 979
 980         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 981         case SND_SOC_DAIFMT_DSP_A:
 982                 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
 983                 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
 984                 break;
 985         case SND_SOC_DAIFMT_DSP_B:
 986                 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
 987                 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
 988                 break;
 989         case SND_SOC_DAIFMT_I2S:
 990                 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
 991                 aif1 |= 0x10;
 992                 break;
 993         case SND_SOC_DAIFMT_RIGHT_J:
 994                 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
 995                 break;
 996         case SND_SOC_DAIFMT_LEFT_J:
 997                 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
 998                 aif1 |= 0x8;
 999                 break;
1000         default:
1001                 return -EINVAL;
1002         }
1003
1004         /* Clock inversion */
1005         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1006         case SND_SOC_DAIFMT_DSP_A:
1007         case SND_SOC_DAIFMT_DSP_B:
1008                 /* frame inversion not valid for DSP modes */
1009                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1010                 case SND_SOC_DAIFMT_NB_NF:
1011                         aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1012                         break;
1013                 case SND_SOC_DAIFMT_IB_NF:
1014                         aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1015                         break;
1016                 default:
1017                         return -EINVAL;
1018                 }
1019                 break;
1020         case SND_SOC_DAIFMT_I2S:
1021         case SND_SOC_DAIFMT_RIGHT_J:
1022         case SND_SOC_DAIFMT_LEFT_J:
1023                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1024                 case SND_SOC_DAIFMT_NB_NF:
1025                         aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1026                         aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
1027                         break;
1028                 case SND_SOC_DAIFMT_IB_IF:
1029                         aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1030                         aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
1031                         break;
1032                 case SND_SOC_DAIFMT_IB_NF:
1033                         aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1034                         aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
1035                         break;
1036                 case SND_SOC_DAIFMT_NB_IF:
1037                         aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1038                         aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
1039                         break;
1040                 default:
1041                         return -EINVAL;
1042                 }
1043                 break;
1044         default:
1045                 return -EINVAL;
1046         }
1047
1048         snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
1049         snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
1050         snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
1051         snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
1052
1053         return 0;
1054 }
1055
1056 static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1057 {
1058         struct snd_soc_codec *codec = codec_dai->codec;
1059         u16 reg;
1060         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
1061
1062         reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
1063
1064         if (mute)
1065                 reg |= WM8900_REG_DACCTRL_MUTE;
1066         else
1067                 reg &= ~WM8900_REG_DACCTRL_MUTE;
1068
1069         snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
1070
1071         return 0;
1072 }
1073
1074 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1075                       SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1076                       SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1077
1078 #define WM8900_PCM_FORMATS \
1079         (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1080          SNDRV_PCM_FORMAT_S24_LE)
1081
1082 static struct snd_soc_dai_ops wm8900_dai_ops = {
1083         .hw_params      = wm8900_hw_params,
1084         .set_clkdiv     = wm8900_set_dai_clkdiv,
1085         .set_pll        = wm8900_set_dai_pll,
1086         .set_fmt        = wm8900_set_dai_fmt,
1087         .digital_mute   = wm8900_digital_mute,
1088 };
1089
1090 struct snd_soc_dai wm8900_dai = {
1091         .name = "WM8900 HiFi",
1092         .playback = {
1093                 .stream_name = "HiFi Playback",
1094                 .channels_min = 1,
1095                 .channels_max = 2,
1096                 .rates = WM8900_RATES,
1097                 .formats = WM8900_PCM_FORMATS,
1098         },
1099         .capture = {
1100                 .stream_name = "HiFi Capture",
1101                 .channels_min = 1,
1102                 .channels_max = 2,
1103                 .rates = WM8900_RATES,
1104                 .formats = WM8900_PCM_FORMATS,
1105          },
1106         .ops = &wm8900_dai_ops,
1107 };
1108 EXPORT_SYMBOL_GPL(wm8900_dai);
1109
1110 static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1111                                  enum snd_soc_bias_level level)
1112 {
1113         u16 reg;
1114
1115         WM8900_DBG("Enter:%s, %d, level=0x%08X \n", __FUNCTION__, __LINE__, level);
1116
1117         switch (level) {
1118         case SND_SOC_BIAS_ON:
1119                 /* Enable thermal shutdown */
1120                 reg = snd_soc_read(codec, WM8900_REG_GPIO);
1121                 snd_soc_write(codec, WM8900_REG_GPIO,
1122                              reg | WM8900_REG_GPIO_TEMP_ENA);
1123                 reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
1124                 snd_soc_write(codec, WM8900_REG_ADDCTL,
1125                              reg | WM8900_REG_ADDCTL_TEMP_SD);
1126                 break;
1127
1128         case SND_SOC_BIAS_PREPARE:
1129                 break;
1130
1131         case SND_SOC_BIAS_STANDBY:
1132                 /* Charge capacitors if initial power up */
1133                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1134                         /* STARTUP_BIAS_ENA on */
1135                         snd_soc_write(codec, WM8900_REG_POWER1,
1136                                      WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1137
1138                         /* Startup bias mode */
1139                         snd_soc_write(codec, WM8900_REG_ADDCTL,
1140                                      WM8900_REG_ADDCTL_BIAS_SRC |
1141                                      WM8900_REG_ADDCTL_VMID_SOFTST);
1142
1143                         /* VMID 2x50k */
1144                         snd_soc_write(codec, WM8900_REG_POWER1,
1145                                      WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1146
1147                         /* Allow capacitors to charge */
1148                         schedule_timeout_interruptible(msecs_to_jiffies(400));
1149
1150                         /* Enable bias */
1151                         snd_soc_write(codec, WM8900_REG_POWER1,
1152                                      WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1153                                      WM8900_REG_POWER1_BIAS_ENA | 0x1);
1154
1155                         snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1156
1157                         snd_soc_write(codec, WM8900_REG_POWER1,
1158                                      WM8900_REG_POWER1_BIAS_ENA | 0x1);
1159                 }
1160
1161                 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1162                 snd_soc_write(codec, WM8900_REG_POWER1,
1163                              (reg & WM8900_REG_POWER1_FLL_ENA) |
1164                              WM8900_REG_POWER1_BIAS_ENA | 0x1);
1165                 snd_soc_write(codec, WM8900_REG_POWER2,
1166                              WM8900_REG_POWER2_SYSCLK_ENA);
1167                 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1168                 break;
1169
1170         case SND_SOC_BIAS_OFF:
1171                 /* Startup bias enable */
1172                 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1173                 snd_soc_write(codec, WM8900_REG_POWER1,
1174                              reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1175                 snd_soc_write(codec, WM8900_REG_ADDCTL,
1176                              WM8900_REG_ADDCTL_BIAS_SRC |
1177                              WM8900_REG_ADDCTL_VMID_SOFTST);
1178
1179                 /* Discharge caps */
1180                 snd_soc_write(codec, WM8900_REG_POWER1,
1181                              WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1182                 schedule_timeout_interruptible(msecs_to_jiffies(500));
1183
1184                 /* Remove clamp */
1185                 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
1186
1187                 /* Power down */
1188                 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1189                 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1190                 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1191                 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1192
1193                 /* Need to let things settle before stopping the clock
1194                  * to ensure that restart works, see "Stopping the
1195                  * master clock" in the datasheet. */
1196                 schedule_timeout_interruptible(msecs_to_jiffies(1));
1197                 snd_soc_write(codec, WM8900_REG_POWER2,
1198                              WM8900_REG_POWER2_SYSCLK_ENA);
1199                 break;
1200         }
1201
1202
1203         codec->bias_level = level;
1204         return 0;
1205 }
1206
1207 static int wm8900_suspend(struct platform_device *pdev, pm_message_t state)
1208 {
1209         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1210         struct snd_soc_codec *codec = socdev->card->codec;
1211         struct wm8900_priv *wm8900 = codec->private_data;
1212
1213         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
1214
1215         int fll_out = wm8900->fll_out;
1216         int fll_in  = wm8900->fll_in;
1217         int ret;
1218
1219         /* Stop the FLL in an orderly fashion */
1220         ret = wm8900_set_fll(codec, 0, 0, 0);
1221         if (ret != 0) {
1222                 dev_err(&pdev->dev, "Failed to stop FLL\n");
1223                 return ret;
1224         }
1225
1226         wm8900->fll_out = fll_out;
1227         wm8900->fll_in = fll_in;
1228
1229         wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1230
1231         return 0;
1232 }
1233
1234 static int wm8900_resume(struct platform_device *pdev)
1235 {
1236         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1237         struct snd_soc_codec *codec = socdev->card->codec;
1238         struct wm8900_priv *wm8900 = codec->private_data;
1239         u16 *cache;
1240         int i, ret;
1241
1242         cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1243                         GFP_KERNEL);
1244
1245         wm8900_reset(codec);
1246         wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1247
1248         /* Restart the FLL? */
1249         if (wm8900->fll_out) {
1250                 int fll_out = wm8900->fll_out;
1251                 int fll_in  = wm8900->fll_in;
1252
1253                 wm8900->fll_in = 0;
1254                 wm8900->fll_out = 0;
1255
1256                 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1257                 if (ret != 0) {
1258                         dev_err(&pdev->dev, "Failed to restart FLL\n");
1259                         return ret;
1260                 }
1261         }
1262
1263         if (cache) {
1264                 for (i = 0; i < WM8900_MAXREG; i++)
1265                         snd_soc_write(codec, i, cache[i]);
1266                 kfree(cache);
1267         } else
1268                 dev_err(&pdev->dev, "Unable to allocate register cache\n");
1269
1270         return 0;
1271 }
1272
1273 static struct snd_soc_codec *wm8900_codec;
1274
1275 static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1276                                       const struct i2c_device_id *id)
1277 {
1278         struct wm8900_priv *wm8900;
1279         struct snd_soc_codec *codec;
1280         unsigned int reg;
1281         int ret;
1282
1283         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
1284
1285         wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1286         if (wm8900 == NULL)
1287                 return -ENOMEM;
1288
1289         codec = &wm8900->codec;
1290         codec->private_data = wm8900;
1291         codec->reg_cache = &wm8900->reg_cache[0];
1292         codec->reg_cache_size = WM8900_MAXREG;
1293
1294         mutex_init(&codec->mutex);
1295         INIT_LIST_HEAD(&codec->dapm_widgets);
1296         INIT_LIST_HEAD(&codec->dapm_paths);
1297
1298         codec->name = "WM8900";
1299         codec->owner = THIS_MODULE;
1300         codec->dai = &wm8900_dai;
1301         codec->num_dai = 1;
1302         codec->control_data = i2c;
1303         codec->set_bias_level = wm8900_set_bias_level;
1304         codec->volatile_register = wm8900_volatile_register;
1305         codec->dev = &i2c->dev;
1306
1307         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1308         if (ret != 0) {
1309                 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1310                 goto err;
1311         }
1312
1313         reg = snd_soc_read(codec, WM8900_REG_ID);
1314         if (reg != 0x8900) {
1315                 dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg);
1316                 ret = -ENODEV;
1317                 goto err;
1318         }
1319
1320         /* Read back from the chip */
1321         reg = snd_soc_read(codec, WM8900_REG_POWER1);
1322         reg = (reg >> 12) & 0xf;
1323         dev_info(&i2c->dev, "WM8900 revision %d\n", reg);
1324
1325         wm8900_reset(codec);
1326
1327         /* Turn the chip on */
1328         wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1329
1330         /* Latch the volume update bits */
1331         snd_soc_write(codec, WM8900_REG_LINVOL,
1332                       snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
1333         snd_soc_write(codec, WM8900_REG_RINVOL,
1334                       snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
1335         snd_soc_write(codec, WM8900_REG_LOUT1CTL,
1336                       snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1337         snd_soc_write(codec, WM8900_REG_ROUT1CTL,
1338                       snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1339         snd_soc_write(codec, WM8900_REG_LOUT2CTL,
1340                       snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1341         snd_soc_write(codec, WM8900_REG_ROUT2CTL,
1342                       snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1343         snd_soc_write(codec, WM8900_REG_LDAC_DV,
1344                       snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1345         snd_soc_write(codec, WM8900_REG_RDAC_DV,
1346                       snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1347         snd_soc_write(codec, WM8900_REG_LADC_DV,
1348                       snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
1349         snd_soc_write(codec, WM8900_REG_RADC_DV,
1350                       snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
1351
1352
1353         /* For Fzf Test */
1354         #if 1
1355         snd_soc_write(codec, WM8900_REG_LDAC_DV,
1356                       (snd_soc_read(codec, WM8900_REG_LDAC_DV)&0xFF00) | 0xB0);
1357         snd_soc_write(codec, WM8900_REG_RDAC_DV,
1358                       (snd_soc_read(codec, WM8900_REG_RDAC_DV)&0xFF00) | 0xB0);
1359
1360         snd_soc_write(codec, WM8900_REG_AUDIO2,
1361                       (snd_soc_read(codec, WM8900_REG_AUDIO2) | (0<<10)));
1362
1363         #endif
1364         /* Set the DAC and mixer output bias */
1365         snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1366
1367         wm8900_dai.dev = &i2c->dev;
1368
1369         wm8900_codec = codec;
1370
1371         ret = snd_soc_register_codec(codec);
1372         if (ret != 0) {
1373                 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1374                 goto err;
1375         }
1376
1377         ret = snd_soc_register_dai(&wm8900_dai);
1378         if (ret != 0) {
1379                 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1380                 goto err_codec;
1381         }
1382
1383         return ret;
1384
1385 err_codec:
1386         snd_soc_unregister_codec(codec);
1387 err:
1388         kfree(wm8900);
1389         wm8900_codec = NULL;
1390         return ret;
1391 }
1392
1393 static __devexit int wm8900_i2c_remove(struct i2c_client *client)
1394 {
1395         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
1396
1397         snd_soc_unregister_dai(&wm8900_dai);
1398         snd_soc_unregister_codec(wm8900_codec);
1399
1400         wm8900_set_bias_level(wm8900_codec, SND_SOC_BIAS_OFF);
1401
1402         wm8900_dai.dev = NULL;
1403         kfree(wm8900_codec->private_data);
1404         wm8900_codec = NULL;
1405
1406         return 0;
1407 }
1408
1409 #ifdef CONFIG_PM
1410 static int wm8900_i2c_suspend(struct i2c_client *client, pm_message_t msg)
1411 {
1412         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
1413         return snd_soc_suspend_device(&client->dev);
1414 }
1415
1416 static int wm8900_i2c_resume(struct i2c_client *client)
1417 {
1418         return snd_soc_resume_device(&client->dev);
1419 }
1420 #else
1421 #define wm8900_i2c_suspend NULL
1422 #define wm8900_i2c_resume NULL
1423 #endif
1424
1425 static const struct i2c_device_id wm8900_i2c_id[] = {
1426         { "wm8900", 0 },
1427         { }
1428 };
1429 MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1430
1431 static struct i2c_driver wm8900_i2c_driver = {
1432         .driver = {
1433                 .name = "WM8900",
1434                 .owner = THIS_MODULE,
1435         },
1436         .probe = wm8900_i2c_probe,
1437         .remove = __devexit_p(wm8900_i2c_remove),
1438         .suspend = wm8900_i2c_suspend,
1439         .resume = wm8900_i2c_resume,
1440         .id_table = wm8900_i2c_id,
1441 };
1442
1443 static int wm8900_probe(struct platform_device *pdev)
1444 {
1445         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1446         struct snd_soc_codec *codec;
1447         int ret = 0;
1448
1449         WM8900_DBG("Enter:%s, %d \n", __FUNCTION__, __LINE__);
1450
1451         if (!wm8900_codec) {
1452                 dev_err(&pdev->dev, "I2C client not yet instantiated\n");
1453                 return -ENODEV;
1454         }
1455
1456         codec = wm8900_codec;
1457         socdev->card->codec = codec;
1458
1459         /* Register pcms */
1460         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1461         if (ret < 0) {
1462                 dev_err(&pdev->dev, "Failed to register new PCMs\n");
1463                 goto pcm_err;
1464         }
1465
1466         snd_soc_add_controls(codec, wm8900_snd_controls,
1467                                 ARRAY_SIZE(wm8900_snd_controls));
1468         snd_soc_add_controls(codec, wm8900_linpga_controls,
1469                                 ARRAY_SIZE(wm8900_linpga_controls));
1470         snd_soc_add_controls(codec, wm8900_rinpga_controls,
1471                                 ARRAY_SIZE(wm8900_rinpga_controls));
1472         snd_soc_add_controls(codec, wm8900_inmix_controls,
1473                                 ARRAY_SIZE(wm8900_inmix_controls));
1474
1475         wm8900_add_widgets(codec);
1476
1477         ret = snd_soc_init_card(socdev);
1478         if (ret < 0) {
1479                 dev_err(&pdev->dev, "Failed to register card\n");
1480                 goto card_err;
1481         }
1482
1483         return ret;
1484
1485 card_err:
1486         snd_soc_free_pcms(socdev);
1487         snd_soc_dapm_free(socdev);
1488 pcm_err:
1489         return ret;
1490 }
1491
1492 /* power down chip */
1493 static int wm8900_remove(struct platform_device *pdev)
1494 {
1495         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1496
1497         snd_soc_free_pcms(socdev);
1498         snd_soc_dapm_free(socdev);
1499
1500         return 0;
1501 }
1502
1503 struct snd_soc_codec_device soc_codec_dev_wm8900 = {
1504         .probe =        wm8900_probe,
1505         .remove =       wm8900_remove,
1506         .suspend =      wm8900_suspend,
1507         .resume =       wm8900_resume,
1508 };
1509 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900);
1510
1511 static int __init wm8900_modinit(void)
1512 {
1513         return i2c_add_driver(&wm8900_i2c_driver);
1514 }
1515 module_init(wm8900_modinit);
1516
1517 static void __exit wm8900_exit(void)
1518 {
1519         i2c_del_driver(&wm8900_i2c_driver);
1520 }
1521 module_exit(wm8900_exit);
1522
1523 MODULE_DESCRIPTION("ASoC WM8900 driver");
1524 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1525 MODULE_LICENSE("GPL");