2 * wm8900.c -- WM8900 ALSA Soc Audio driver
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 * - FLL source configuration, currently only MCLK is supported.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/spi/spi.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/soc-dapm.h>
34 #include <sound/initval.h>
35 #include <sound/tlv.h>
39 /* WM8900 register space */
40 #define WM8900_REG_RESET 0x0
41 #define WM8900_REG_ID 0x0
42 #define WM8900_REG_POWER1 0x1
43 #define WM8900_REG_POWER2 0x2
44 #define WM8900_REG_POWER3 0x3
45 #define WM8900_REG_AUDIO1 0x4
46 #define WM8900_REG_AUDIO2 0x5
47 #define WM8900_REG_CLOCKING1 0x6
48 #define WM8900_REG_CLOCKING2 0x7
49 #define WM8900_REG_AUDIO3 0x8
50 #define WM8900_REG_AUDIO4 0x9
51 #define WM8900_REG_DACCTRL 0xa
52 #define WM8900_REG_LDAC_DV 0xb
53 #define WM8900_REG_RDAC_DV 0xc
54 #define WM8900_REG_SIDETONE 0xd
55 #define WM8900_REG_ADCCTRL 0xe
56 #define WM8900_REG_LADC_DV 0xf
57 #define WM8900_REG_RADC_DV 0x10
58 #define WM8900_REG_GPIO 0x12
59 #define WM8900_REG_INCTL 0x15
60 #define WM8900_REG_LINVOL 0x16
61 #define WM8900_REG_RINVOL 0x17
62 #define WM8900_REG_INBOOSTMIX1 0x18
63 #define WM8900_REG_INBOOSTMIX2 0x19
64 #define WM8900_REG_ADCPATH 0x1a
65 #define WM8900_REG_AUXBOOST 0x1b
66 #define WM8900_REG_ADDCTL 0x1e
67 #define WM8900_REG_FLLCTL1 0x24
68 #define WM8900_REG_FLLCTL2 0x25
69 #define WM8900_REG_FLLCTL3 0x26
70 #define WM8900_REG_FLLCTL4 0x27
71 #define WM8900_REG_FLLCTL5 0x28
72 #define WM8900_REG_FLLCTL6 0x29
73 #define WM8900_REG_LOUTMIXCTL1 0x2c
74 #define WM8900_REG_ROUTMIXCTL1 0x2d
75 #define WM8900_REG_BYPASS1 0x2e
76 #define WM8900_REG_BYPASS2 0x2f
77 #define WM8900_REG_AUXOUT_CTL 0x30
78 #define WM8900_REG_LOUT1CTL 0x33
79 #define WM8900_REG_ROUT1CTL 0x34
80 #define WM8900_REG_LOUT2CTL 0x35
81 #define WM8900_REG_ROUT2CTL 0x36
82 #define WM8900_REG_HPCTL1 0x3a
83 #define WM8900_REG_OUTBIASCTL 0x73
85 #define WM8900_MAXREG 0x80
87 #define WM8900_REG_ADDCTL_OUT1_DIS 0x80
88 #define WM8900_REG_ADDCTL_OUT2_DIS 0x40
89 #define WM8900_REG_ADDCTL_VMID_DIS 0x20
90 #define WM8900_REG_ADDCTL_BIAS_SRC 0x10
91 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
92 #define WM8900_REG_ADDCTL_TEMP_SD 0x02
94 #define WM8900_REG_GPIO_TEMP_ENA 0x2
96 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
97 #define WM8900_REG_POWER1_BIAS_ENA 0x0008
98 #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
99 #define WM8900_REG_POWER1_FLL_ENA 0x0040
101 #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
102 #define WM8900_REG_POWER2_ADCL_ENA 0x0002
103 #define WM8900_REG_POWER2_ADCR_ENA 0x0001
105 #define WM8900_REG_POWER3_DACL_ENA 0x0002
106 #define WM8900_REG_POWER3_DACR_ENA 0x0001
108 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
109 #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
110 #define WM8900_REG_AUDIO1_BCLK_INV 0x0100
112 #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
113 #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
114 #define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
115 #define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
117 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
118 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
120 #define WM8900_REG_DACCTRL_MUTE 0x004
121 #define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
122 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
124 #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
126 #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
128 #define WM8900_REG_FLLCTL1_OSC_ENA 0x100
130 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
132 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
133 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
134 #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
135 #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
136 #define WM8900_REG_HPCTL1_HP_SHORT 0x08
137 #define WM8900_REG_HPCTL1_HP_SHORT2 0x04
139 #define WM8900_LRC_MASK 0xfc00
142 enum snd_soc_control_type control_type;
143 u16 reg_cache[WM8900_MAXREG];
145 u32 fll_in; /* FLL input frequency */
146 u32 fll_out; /* FLL output frequency */
150 * wm8900 register cache. We can't read the entire register space and we
151 * have slow control buses so we cache the registers.
153 static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
182 /* Remaining registers all zero */
185 static int wm8900_volatile_register(unsigned int reg)
189 case WM8900_REG_POWER1:
196 static void wm8900_reset(struct snd_soc_codec *codec)
198 snd_soc_write(codec, WM8900_REG_RESET, 0);
200 memcpy(codec->reg_cache, wm8900_reg_defaults,
201 sizeof(wm8900_reg_defaults));
204 static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
205 struct snd_kcontrol *kcontrol, int event)
207 struct snd_soc_codec *codec = w->codec;
208 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
211 case SND_SOC_DAPM_PRE_PMU:
212 /* Clamp headphone outputs */
213 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
214 WM8900_REG_HPCTL1_HP_CLAMP_OP;
215 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
218 case SND_SOC_DAPM_POST_PMU:
219 /* Enable the input stage */
220 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
221 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
222 WM8900_REG_HPCTL1_HP_SHORT2 |
223 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
224 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
228 /* Enable the output stage */
229 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
230 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
231 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
233 /* Remove the shorts */
234 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
235 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
236 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
237 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
240 case SND_SOC_DAPM_PRE_PMD:
241 /* Short the output */
242 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
243 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
245 /* Disable the output stage */
246 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
247 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
249 /* Clamp the outputs and power down input */
250 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
251 WM8900_REG_HPCTL1_HP_CLAMP_OP;
252 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
253 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
256 case SND_SOC_DAPM_POST_PMD:
257 /* Disable everything */
258 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
268 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
270 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
272 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
274 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
276 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
278 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
280 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
282 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
284 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
286 static const struct soc_enum mic_bias_level =
287 SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
289 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
291 static const struct soc_enum dac_mute_rate =
292 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
294 static const char *dac_deemphasis_txt[] = {
295 "Disabled", "32kHz", "44.1kHz", "48kHz"
298 static const struct soc_enum dac_deemphasis =
299 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
301 static const char *adc_hpf_cut_txt[] = {
302 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
305 static const struct soc_enum adc_hpf_cut =
306 SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
308 static const char *lr_txt[] = {
312 static const struct soc_enum aifl_src =
313 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
315 static const struct soc_enum aifr_src =
316 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
318 static const struct soc_enum dacl_src =
319 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
321 static const struct soc_enum dacr_src =
322 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
324 static const char *sidetone_txt[] = {
325 "Disabled", "Left ADC", "Right ADC"
328 static const struct soc_enum dacl_sidetone =
329 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
331 static const struct soc_enum dacr_sidetone =
332 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
334 static const struct snd_kcontrol_new wm8900_snd_controls[] = {
335 SOC_ENUM("Mic Bias Level", mic_bias_level),
337 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
339 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
340 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
342 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
344 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
345 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
347 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
348 SOC_ENUM("DAC Mute Rate", dac_mute_rate),
349 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
350 SOC_ENUM("DAC Deemphasis", dac_deemphasis),
351 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
354 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
355 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
356 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
357 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
359 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
361 SOC_ENUM("Left Digital Audio Source", aifl_src),
362 SOC_ENUM("Right Digital Audio Source", aifr_src),
364 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
366 SOC_ENUM("Left DAC Source", dacl_src),
367 SOC_ENUM("Right DAC Source", dacr_src),
368 SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
369 SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
370 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
372 SOC_DOUBLE_R_TLV("Digital Playback Volume",
373 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
375 SOC_DOUBLE_R_TLV("Digital Capture Volume",
376 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
378 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
380 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
382 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
384 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
387 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
389 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
391 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
393 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
396 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
398 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
400 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
402 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
404 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
406 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
409 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
410 0, 63, 0, out_pga_tlv),
411 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
413 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
416 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
417 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
418 0, 63, 0, out_pga_tlv),
419 SOC_DOUBLE_R("LINEOUT2 Switch",
420 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
421 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
422 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
423 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
428 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
429 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
431 static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
432 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
434 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
435 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
436 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
437 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
438 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
439 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
442 static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
443 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
444 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
445 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
446 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
447 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
450 static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
451 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
452 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
453 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
454 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
457 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
458 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
459 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
460 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
461 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
464 static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
465 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
466 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
467 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
470 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
471 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
472 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
473 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
476 static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
478 static const struct soc_enum wm8900_lineout2_lp_mux =
479 SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
481 static const struct snd_kcontrol_new wm8900_lineout2_lp =
482 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
484 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
486 /* Externally visible pins */
487 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
488 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
489 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
490 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
491 SND_SOC_DAPM_OUTPUT("HP_L"),
492 SND_SOC_DAPM_OUTPUT("HP_R"),
494 SND_SOC_DAPM_INPUT("RINPUT1"),
495 SND_SOC_DAPM_INPUT("LINPUT1"),
496 SND_SOC_DAPM_INPUT("RINPUT2"),
497 SND_SOC_DAPM_INPUT("LINPUT2"),
498 SND_SOC_DAPM_INPUT("RINPUT3"),
499 SND_SOC_DAPM_INPUT("LINPUT3"),
500 SND_SOC_DAPM_INPUT("AUX"),
502 SND_SOC_DAPM_VMID("VMID"),
505 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
506 wm8900_linpga_controls,
507 ARRAY_SIZE(wm8900_linpga_controls)),
508 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
509 wm8900_rinpga_controls,
510 ARRAY_SIZE(wm8900_rinpga_controls)),
512 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
513 wm8900_linmix_controls,
514 ARRAY_SIZE(wm8900_linmix_controls)),
515 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
516 wm8900_rinmix_controls,
517 ARRAY_SIZE(wm8900_rinmix_controls)),
519 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
521 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
522 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
525 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
526 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
528 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
530 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
531 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
533 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
534 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
536 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
537 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
538 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
540 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
541 wm8900_loutmix_controls,
542 ARRAY_SIZE(wm8900_loutmix_controls)),
543 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
544 wm8900_routmix_controls,
545 ARRAY_SIZE(wm8900_routmix_controls)),
548 /* Target, Path, Source */
549 static const struct snd_soc_dapm_route audio_map[] = {
551 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
552 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
553 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
555 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
556 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
557 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
559 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
560 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
561 {"Left Input Mixer", "AUX Switch", "AUX"},
562 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
564 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
565 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
566 {"Right Input Mixer", "AUX Switch", "AUX"},
567 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
569 {"ADCL", NULL, "Left Input Mixer"},
570 {"ADCR", NULL, "Right Input Mixer"},
573 {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
574 {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
575 {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
576 {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
578 {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
579 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
580 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
581 {"LINEOUT2L", NULL, "LINEOUT2 LP"},
583 {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
584 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
585 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
586 {"LINEOUT2R", NULL, "LINEOUT2 LP"},
588 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
589 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
590 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
591 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
592 {"Left Output Mixer", "DACL Switch", "DACL"},
594 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
595 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
596 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
597 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
598 {"Right Output Mixer", "DACR Switch", "DACR"},
600 /* Note that the headphone output stage needs to be connected
601 * externally to LINEOUT2 via DC blocking capacitors. Other
602 * configurations are not supported.
604 * Note also that left and right headphone paths are treated as a
607 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
608 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
609 {"HP_L", NULL, "Headphone Amplifier"},
610 {"HP_R", NULL, "Headphone Amplifier"},
613 static int wm8900_add_widgets(struct snd_soc_codec *codec)
615 snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets,
616 ARRAY_SIZE(wm8900_dapm_widgets));
618 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
623 static int wm8900_hw_params(struct snd_pcm_substream *substream,
624 struct snd_pcm_hw_params *params,
625 struct snd_soc_dai *dai)
627 struct snd_soc_pcm_runtime *rtd = substream->private_data;
628 struct snd_soc_codec *codec = rtd->codec;
631 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
633 switch (params_format(params)) {
634 case SNDRV_PCM_FORMAT_S16_LE:
636 case SNDRV_PCM_FORMAT_S20_3LE:
639 case SNDRV_PCM_FORMAT_S24_LE:
642 case SNDRV_PCM_FORMAT_S32_LE:
649 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
651 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
652 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
654 if (params_rate(params) <= 24000)
655 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
657 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
659 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
669 u16 fll_slow_lock_ref;
674 /* The size in bits of the FLL divide multiplied by 10
675 * to allow rounding later */
676 #define FIXED_FLL_SIZE ((1 << 16) * 10)
678 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
682 unsigned int K, Ndiv, Nmod, target;
687 /* The FLL must run at 90-100MHz which is then scaled down to
688 * the output value by FLLCLK_DIV. */
691 while (target < 90000000) {
696 if (target > 100000000)
697 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
698 " Fout=%u\n", target, Fref, Fout);
700 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
701 "Fref=%u, Fout=%u, target=%u\n",
702 div, Fref, Fout, target);
706 fll_div->fllclk_div = div >> 2;
709 fll_div->fll_slow_lock_ref = 1;
711 fll_div->fll_slow_lock_ref = 0;
713 Ndiv = target / Fref;
716 fll_div->fll_ratio = 8;
718 fll_div->fll_ratio = 1;
720 fll_div->n = Ndiv / fll_div->fll_ratio;
721 Nmod = (target / fll_div->fll_ratio) % Fref;
723 /* Calculate fractional part - scale up so we can round. */
724 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
728 K = Kpart & 0xFFFFFFFF;
733 /* Move down to proper range now rounding is done */
736 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
737 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
742 static int wm8900_set_fll(struct snd_soc_codec *codec,
743 int fll_id, unsigned int freq_in, unsigned int freq_out)
745 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
746 struct _fll_div fll_div;
749 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
752 /* The digital side should be disabled during any change. */
753 reg = snd_soc_read(codec, WM8900_REG_POWER1);
754 snd_soc_write(codec, WM8900_REG_POWER1,
755 reg & (~WM8900_REG_POWER1_FLL_ENA));
757 /* Disable the FLL? */
758 if (!freq_in || !freq_out) {
759 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
760 snd_soc_write(codec, WM8900_REG_CLOCKING1,
761 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
763 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
764 snd_soc_write(codec, WM8900_REG_FLLCTL1,
765 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
767 wm8900->fll_in = freq_in;
768 wm8900->fll_out = freq_out;
773 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
776 wm8900->fll_in = freq_in;
777 wm8900->fll_out = freq_out;
779 /* The osclilator *MUST* be enabled before we enable the
780 * digital circuit. */
781 snd_soc_write(codec, WM8900_REG_FLLCTL1,
782 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
784 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
785 snd_soc_write(codec, WM8900_REG_FLLCTL5,
786 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
789 snd_soc_write(codec, WM8900_REG_FLLCTL2,
790 (fll_div.k >> 8) | 0x100);
791 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
793 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
795 if (fll_div.fll_slow_lock_ref)
796 snd_soc_write(codec, WM8900_REG_FLLCTL6,
797 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
799 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
801 reg = snd_soc_read(codec, WM8900_REG_POWER1);
802 snd_soc_write(codec, WM8900_REG_POWER1,
803 reg | WM8900_REG_POWER1_FLL_ENA);
806 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
807 snd_soc_write(codec, WM8900_REG_CLOCKING1,
808 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
813 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
814 int source, unsigned int freq_in, unsigned int freq_out)
816 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
819 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
822 struct snd_soc_codec *codec = codec_dai->codec;
826 case WM8900_BCLK_DIV:
827 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
828 snd_soc_write(codec, WM8900_REG_CLOCKING1,
829 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
831 case WM8900_OPCLK_DIV:
832 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
833 snd_soc_write(codec, WM8900_REG_CLOCKING1,
834 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
836 case WM8900_DAC_LRCLK:
837 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
838 snd_soc_write(codec, WM8900_REG_AUDIO4,
839 div | (reg & WM8900_LRC_MASK));
841 case WM8900_ADC_LRCLK:
842 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
843 snd_soc_write(codec, WM8900_REG_AUDIO3,
844 div | (reg & WM8900_LRC_MASK));
846 case WM8900_DAC_CLKDIV:
847 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
848 snd_soc_write(codec, WM8900_REG_CLOCKING2,
849 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
851 case WM8900_ADC_CLKDIV:
852 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
853 snd_soc_write(codec, WM8900_REG_CLOCKING2,
854 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
856 case WM8900_LRCLK_MODE:
857 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
858 snd_soc_write(codec, WM8900_REG_DACCTRL,
859 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
869 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
872 struct snd_soc_codec *codec = codec_dai->codec;
873 unsigned int clocking1, aif1, aif3, aif4;
875 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
876 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
877 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
878 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
880 /* set master/slave audio interface */
881 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
882 case SND_SOC_DAIFMT_CBS_CFS:
883 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
884 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
885 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
887 case SND_SOC_DAIFMT_CBS_CFM:
888 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
889 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
890 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
892 case SND_SOC_DAIFMT_CBM_CFM:
893 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
894 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
895 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
897 case SND_SOC_DAIFMT_CBM_CFS:
898 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
899 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
900 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
906 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
907 case SND_SOC_DAIFMT_DSP_A:
908 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
909 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
911 case SND_SOC_DAIFMT_DSP_B:
912 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
913 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
915 case SND_SOC_DAIFMT_I2S:
916 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
919 case SND_SOC_DAIFMT_RIGHT_J:
920 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
922 case SND_SOC_DAIFMT_LEFT_J:
923 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
930 /* Clock inversion */
931 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
932 case SND_SOC_DAIFMT_DSP_A:
933 case SND_SOC_DAIFMT_DSP_B:
934 /* frame inversion not valid for DSP modes */
935 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
936 case SND_SOC_DAIFMT_NB_NF:
937 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
939 case SND_SOC_DAIFMT_IB_NF:
940 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
946 case SND_SOC_DAIFMT_I2S:
947 case SND_SOC_DAIFMT_RIGHT_J:
948 case SND_SOC_DAIFMT_LEFT_J:
949 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
950 case SND_SOC_DAIFMT_NB_NF:
951 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
952 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
954 case SND_SOC_DAIFMT_IB_IF:
955 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
956 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
958 case SND_SOC_DAIFMT_IB_NF:
959 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
960 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
962 case SND_SOC_DAIFMT_NB_IF:
963 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
964 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
974 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
975 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
976 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
977 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
982 static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
984 struct snd_soc_codec *codec = codec_dai->codec;
987 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
990 reg |= WM8900_REG_DACCTRL_MUTE;
992 reg &= ~WM8900_REG_DACCTRL_MUTE;
994 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
999 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1000 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1001 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1003 #define WM8900_PCM_FORMATS \
1004 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1005 SNDRV_PCM_FORMAT_S24_LE)
1007 static struct snd_soc_dai_ops wm8900_dai_ops = {
1008 .hw_params = wm8900_hw_params,
1009 .set_clkdiv = wm8900_set_dai_clkdiv,
1010 .set_pll = wm8900_set_dai_pll,
1011 .set_fmt = wm8900_set_dai_fmt,
1012 .digital_mute = wm8900_digital_mute,
1015 static struct snd_soc_dai_driver wm8900_dai = {
1016 .name = "wm8900-hifi",
1018 .stream_name = "HiFi Playback",
1021 .rates = WM8900_RATES,
1022 .formats = WM8900_PCM_FORMATS,
1025 .stream_name = "HiFi Capture",
1028 .rates = WM8900_RATES,
1029 .formats = WM8900_PCM_FORMATS,
1031 .ops = &wm8900_dai_ops,
1034 static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1035 enum snd_soc_bias_level level)
1040 case SND_SOC_BIAS_ON:
1041 /* Enable thermal shutdown */
1042 reg = snd_soc_read(codec, WM8900_REG_GPIO);
1043 snd_soc_write(codec, WM8900_REG_GPIO,
1044 reg | WM8900_REG_GPIO_TEMP_ENA);
1045 reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
1046 snd_soc_write(codec, WM8900_REG_ADDCTL,
1047 reg | WM8900_REG_ADDCTL_TEMP_SD);
1050 case SND_SOC_BIAS_PREPARE:
1053 case SND_SOC_BIAS_STANDBY:
1054 /* Charge capacitors if initial power up */
1055 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1056 /* STARTUP_BIAS_ENA on */
1057 snd_soc_write(codec, WM8900_REG_POWER1,
1058 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1060 /* Startup bias mode */
1061 snd_soc_write(codec, WM8900_REG_ADDCTL,
1062 WM8900_REG_ADDCTL_BIAS_SRC |
1063 WM8900_REG_ADDCTL_VMID_SOFTST);
1066 snd_soc_write(codec, WM8900_REG_POWER1,
1067 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1069 /* Allow capacitors to charge */
1070 schedule_timeout_interruptible(msecs_to_jiffies(400));
1073 snd_soc_write(codec, WM8900_REG_POWER1,
1074 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1075 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1077 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1079 snd_soc_write(codec, WM8900_REG_POWER1,
1080 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1083 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1084 snd_soc_write(codec, WM8900_REG_POWER1,
1085 (reg & WM8900_REG_POWER1_FLL_ENA) |
1086 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1087 snd_soc_write(codec, WM8900_REG_POWER2,
1088 WM8900_REG_POWER2_SYSCLK_ENA);
1089 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1092 case SND_SOC_BIAS_OFF:
1093 /* Startup bias enable */
1094 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1095 snd_soc_write(codec, WM8900_REG_POWER1,
1096 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1097 snd_soc_write(codec, WM8900_REG_ADDCTL,
1098 WM8900_REG_ADDCTL_BIAS_SRC |
1099 WM8900_REG_ADDCTL_VMID_SOFTST);
1101 /* Discharge caps */
1102 snd_soc_write(codec, WM8900_REG_POWER1,
1103 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1104 schedule_timeout_interruptible(msecs_to_jiffies(500));
1107 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
1110 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1111 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1112 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1113 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1115 /* Need to let things settle before stopping the clock
1116 * to ensure that restart works, see "Stopping the
1117 * master clock" in the datasheet. */
1118 schedule_timeout_interruptible(msecs_to_jiffies(1));
1119 snd_soc_write(codec, WM8900_REG_POWER2,
1120 WM8900_REG_POWER2_SYSCLK_ENA);
1123 codec->bias_level = level;
1127 static int wm8900_suspend(struct snd_soc_codec *codec, pm_message_t state)
1129 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1130 int fll_out = wm8900->fll_out;
1131 int fll_in = wm8900->fll_in;
1134 /* Stop the FLL in an orderly fashion */
1135 ret = wm8900_set_fll(codec, 0, 0, 0);
1137 dev_err(codec->dev, "Failed to stop FLL\n");
1141 wm8900->fll_out = fll_out;
1142 wm8900->fll_in = fll_in;
1144 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1149 static int wm8900_resume(struct snd_soc_codec *codec)
1151 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1155 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1158 wm8900_reset(codec);
1159 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1161 /* Restart the FLL? */
1162 if (wm8900->fll_out) {
1163 int fll_out = wm8900->fll_out;
1164 int fll_in = wm8900->fll_in;
1167 wm8900->fll_out = 0;
1169 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1171 dev_err(codec->dev, "Failed to restart FLL\n");
1177 for (i = 0; i < WM8900_MAXREG; i++)
1178 snd_soc_write(codec, i, cache[i]);
1181 dev_err(codec->dev, "Unable to allocate register cache\n");
1186 static int wm8900_probe(struct snd_soc_codec *codec)
1188 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1191 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8900->control_type);
1193 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1197 reg = snd_soc_read(codec, WM8900_REG_ID);
1198 if (reg != 0x8900) {
1199 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1203 /* Read back from the chip */
1204 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1205 reg = (reg >> 12) & 0xf;
1206 dev_info(codec->dev, "WM8900 revision %d\n", reg);
1208 wm8900_reset(codec);
1210 /* Turn the chip on */
1211 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1213 /* Latch the volume update bits */
1214 snd_soc_write(codec, WM8900_REG_LINVOL,
1215 snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
1216 snd_soc_write(codec, WM8900_REG_RINVOL,
1217 snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
1218 snd_soc_write(codec, WM8900_REG_LOUT1CTL,
1219 snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1220 snd_soc_write(codec, WM8900_REG_ROUT1CTL,
1221 snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1222 snd_soc_write(codec, WM8900_REG_LOUT2CTL,
1223 snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1224 snd_soc_write(codec, WM8900_REG_ROUT2CTL,
1225 snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1226 snd_soc_write(codec, WM8900_REG_LDAC_DV,
1227 snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1228 snd_soc_write(codec, WM8900_REG_RDAC_DV,
1229 snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1230 snd_soc_write(codec, WM8900_REG_LADC_DV,
1231 snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
1232 snd_soc_write(codec, WM8900_REG_RADC_DV,
1233 snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
1235 /* Set the DAC and mixer output bias */
1236 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1238 snd_soc_add_controls(codec, wm8900_snd_controls,
1239 ARRAY_SIZE(wm8900_snd_controls));
1240 wm8900_add_widgets(codec);
1245 /* power down chip */
1246 static int wm8900_remove(struct snd_soc_codec *codec)
1248 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1252 static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1253 .probe = wm8900_probe,
1254 .remove = wm8900_remove,
1255 .suspend = wm8900_suspend,
1256 .resume = wm8900_resume,
1257 .set_bias_level = wm8900_set_bias_level,
1258 .volatile_register = wm8900_volatile_register,
1259 .reg_cache_size = sizeof(wm8900_reg_defaults),
1260 .reg_word_size = sizeof(u16),
1261 .reg_cache_default = wm8900_reg_defaults,
1264 #if defined(CONFIG_SPI_MASTER)
1265 static int __devinit wm8900_spi_probe(struct spi_device *spi)
1267 struct wm8900_priv *wm8900;
1270 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1274 wm8900->control_type = SND_SOC_SPI;
1275 spi_set_drvdata(spi, wm8900);
1277 ret = snd_soc_register_codec(&spi->dev,
1278 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1284 static int __devexit wm8900_spi_remove(struct spi_device *spi)
1286 snd_soc_unregister_codec(&spi->dev);
1287 kfree(spi_get_drvdata(spi));
1291 static struct spi_driver wm8900_spi_driver = {
1293 .name = "wm8900-codec",
1294 .bus = &spi_bus_type,
1295 .owner = THIS_MODULE,
1297 .probe = wm8900_spi_probe,
1298 .remove = __devexit_p(wm8900_spi_remove),
1300 #endif /* CONFIG_SPI_MASTER */
1302 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1303 static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1304 const struct i2c_device_id *id)
1306 struct wm8900_priv *wm8900;
1309 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1313 i2c_set_clientdata(i2c, wm8900);
1314 wm8900->control_type = SND_SOC_I2C;
1316 ret = snd_soc_register_codec(&i2c->dev,
1317 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1323 static __devexit int wm8900_i2c_remove(struct i2c_client *client)
1325 snd_soc_unregister_codec(&client->dev);
1326 kfree(i2c_get_clientdata(client));
1330 static const struct i2c_device_id wm8900_i2c_id[] = {
1334 MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1336 static struct i2c_driver wm8900_i2c_driver = {
1338 .name = "wm8900-codec",
1339 .owner = THIS_MODULE,
1341 .probe = wm8900_i2c_probe,
1342 .remove = __devexit_p(wm8900_i2c_remove),
1343 .id_table = wm8900_i2c_id,
1347 static int __init wm8900_modinit(void)
1350 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1351 ret = i2c_add_driver(&wm8900_i2c_driver);
1353 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1357 #if defined(CONFIG_SPI_MASTER)
1358 ret = spi_register_driver(&wm8900_spi_driver);
1360 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1366 module_init(wm8900_modinit);
1368 static void __exit wm8900_exit(void)
1370 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1371 i2c_del_driver(&wm8900_i2c_driver);
1373 #if defined(CONFIG_SPI_MASTER)
1374 spi_unregister_driver(&wm8900_spi_driver);
1377 module_exit(wm8900_exit);
1379 MODULE_DESCRIPTION("ASoC WM8900 driver");
1380 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1381 MODULE_LICENSE("GPL");