sound/soc/codecs/wm8915.c

   1 /*
   2  * wm8915.c - WM8915 audio codec interface
   3  *
   4  * Copyright 2011 Wolfson Microelectronics PLC.
   5  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/completion.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/gcd.h>
  20 #include <linux/gpio.h>
  21 #include <linux/i2c.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/core.h>
  26 #include <sound/jack.h>
  27 #include <sound/pcm.h>
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <sound/initval.h>
  31 #include <sound/tlv.h>
  32 #include <trace/events/asoc.h>
  33
  34 #include <sound/wm8915.h>
  35 #include "wm8915.h"
  36
  37 #define WM8915_AIFS 2
  38
  39 #define HPOUT1L 1
  40 #define HPOUT1R 2
  41 #define HPOUT2L 4
  42 #define HPOUT2R 8
  43
  44 #define WM8915_NUM_SUPPLIES 4
  45 static const char *wm8915_supply_names[WM8915_NUM_SUPPLIES] = {
  46         "DBVDD",
  47         "AVDD1",
  48         "AVDD2",
  49         "CPVDD",
  50 };
  51
  52 struct wm8915_priv {
  53         struct snd_soc_codec *codec;
  54
  55         int ldo1ena;
  56
  57         int sysclk;
  58
  59         int fll_src;
  60         int fll_fref;
  61         int fll_fout;
  62
  63         struct completion fll_lock;
  64
  65         u16 dcs_pending;
  66         struct completion dcs_done;
  67
  68         u16 hpout_ena;
  69         u16 hpout_pending;
  70
  71         struct regulator_bulk_data supplies[WM8915_NUM_SUPPLIES];
  72         struct notifier_block disable_nb[WM8915_NUM_SUPPLIES];
  73
  74         struct wm8915_pdata pdata;
  75
  76         int rx_rate[WM8915_AIFS];
  77
  78         /* Platform dependant ReTune mobile configuration */
  79         int num_retune_mobile_texts;
  80         const char **retune_mobile_texts;
  81         int retune_mobile_cfg[2];
  82         struct soc_enum retune_mobile_enum;
  83
  84         struct snd_soc_jack *jack;
  85         bool detecting;
  86         bool jack_mic;
  87         wm8915_polarity_fn polarity_cb;
  88
  89 #ifdef CONFIG_GPIOLIB
  90         struct gpio_chip gpio_chip;
  91 #endif
  92 };
  93
  94 /* We can't use the same notifier block for more than one supply and
  95  * there's no way I can see to get from a callback to the caller
  96  * except container_of().
  97  */
  98 #define WM8915_REGULATOR_EVENT(n) \
  99 static int wm8915_regulator_event_##n(struct notifier_block *nb, \
 100                                     unsigned long event, void *data)    \
 101 { \
 102         struct wm8915_priv *wm8915 = container_of(nb, struct wm8915_priv, \
 103                                                   disable_nb[n]); \
 104         if (event & REGULATOR_EVENT_DISABLE) { \
 105                 wm8915->codec->cache_sync = 1; \
 106         } \
 107         return 0; \
 108 }
 109
 110 WM8915_REGULATOR_EVENT(0)
 111 WM8915_REGULATOR_EVENT(1)
 112 WM8915_REGULATOR_EVENT(2)
 113 WM8915_REGULATOR_EVENT(3)
 114
 115 static const u16 wm8915_reg[WM8915_MAX_REGISTER] = {
 116         [WM8915_SOFTWARE_RESET] = 0x8915,
 117         [WM8915_POWER_MANAGEMENT_7] = 0x10,
 118         [WM8915_DAC1_HPOUT1_VOLUME] = 0x88,
 119         [WM8915_DAC2_HPOUT2_VOLUME] = 0x88,
 120         [WM8915_DAC1_LEFT_VOLUME] = 0x2c0,
 121         [WM8915_DAC1_RIGHT_VOLUME] = 0x2c0,
 122         [WM8915_DAC2_LEFT_VOLUME] = 0x2c0,
 123         [WM8915_DAC2_RIGHT_VOLUME] = 0x2c0,
 124         [WM8915_OUTPUT1_LEFT_VOLUME] = 0x80,
 125         [WM8915_OUTPUT1_RIGHT_VOLUME] = 0x80,
 126         [WM8915_OUTPUT2_LEFT_VOLUME] = 0x80,
 127         [WM8915_OUTPUT2_RIGHT_VOLUME] = 0x80,
 128         [WM8915_MICBIAS_1] = 0x39,
 129         [WM8915_MICBIAS_2] = 0x39,
 130         [WM8915_LDO_1] = 0x3,
 131         [WM8915_LDO_2] = 0x13,
 132         [WM8915_ACCESSORY_DETECT_MODE_1] = 0x4,
 133         [WM8915_HEADPHONE_DETECT_1] = 0x20,
 134         [WM8915_MIC_DETECT_1] = 0x7600,
 135         [WM8915_MIC_DETECT_2] = 0xbf,
 136         [WM8915_CHARGE_PUMP_1] = 0x1f25,
 137         [WM8915_CHARGE_PUMP_2] = 0xab19,
 138         [WM8915_DC_SERVO_5] = 0x2a2a,
 139         [WM8915_CONTROL_INTERFACE_1] = 0x8004,
 140         [WM8915_CLOCKING_1] = 0x10,
 141         [WM8915_AIF_RATE] = 0x83,
 142         [WM8915_FLL_CONTROL_4] = 0x5dc0,
 143         [WM8915_FLL_CONTROL_5] = 0xc84,
 144         [WM8915_FLL_EFS_2] = 0x2,
 145         [WM8915_AIF1_TX_LRCLK_1] = 0x80,
 146         [WM8915_AIF1_TX_LRCLK_2] = 0x8,
 147         [WM8915_AIF1_RX_LRCLK_1] = 0x80,
 148         [WM8915_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
 149         [WM8915_AIF1RX_DATA_CONFIGURATION] = 0x1818,
 150         [WM8915_AIF1TX_TEST] = 0x7,
 151         [WM8915_AIF2_TX_LRCLK_1] = 0x80,
 152         [WM8915_AIF2_TX_LRCLK_2] = 0x8,
 153         [WM8915_AIF2_RX_LRCLK_1] = 0x80,
 154         [WM8915_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
 155         [WM8915_AIF2RX_DATA_CONFIGURATION] = 0x1818,
 156         [WM8915_AIF2TX_TEST] = 0x1,
 157         [WM8915_DSP1_TX_LEFT_VOLUME] = 0xc0,
 158         [WM8915_DSP1_TX_RIGHT_VOLUME] = 0xc0,
 159         [WM8915_DSP1_RX_LEFT_VOLUME] = 0xc0,
 160         [WM8915_DSP1_RX_RIGHT_VOLUME] = 0xc0,
 161         [WM8915_DSP1_TX_FILTERS] = 0x2000,
 162         [WM8915_DSP1_RX_FILTERS_1] = 0x200,
 163         [WM8915_DSP1_RX_FILTERS_2] = 0x10,
 164         [WM8915_DSP1_DRC_1] = 0x98,
 165         [WM8915_DSP1_DRC_2] = 0x845,
 166         [WM8915_DSP1_RX_EQ_GAINS_1] = 0x6318,
 167         [WM8915_DSP1_RX_EQ_GAINS_2] = 0x6300,
 168         [WM8915_DSP1_RX_EQ_BAND_1_A] = 0xfca,
 169         [WM8915_DSP1_RX_EQ_BAND_1_B] = 0x400,
 170         [WM8915_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
 171         [WM8915_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
 172         [WM8915_DSP1_RX_EQ_BAND_2_B] = 0xf145,
 173         [WM8915_DSP1_RX_EQ_BAND_2_C] = 0xb75,
 174         [WM8915_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
 175         [WM8915_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
 176         [WM8915_DSP1_RX_EQ_BAND_3_B] = 0xf373,
 177         [WM8915_DSP1_RX_EQ_BAND_3_C] = 0xa54,
 178         [WM8915_DSP1_RX_EQ_BAND_3_PG] = 0x558,
 179         [WM8915_DSP1_RX_EQ_BAND_4_A] = 0x168e,
 180         [WM8915_DSP1_RX_EQ_BAND_4_B] = 0xf829,
 181         [WM8915_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
 182         [WM8915_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
 183         [WM8915_DSP1_RX_EQ_BAND_5_A] = 0x564,
 184         [WM8915_DSP1_RX_EQ_BAND_5_B] = 0x559,
 185         [WM8915_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
 186         [WM8915_DSP2_TX_LEFT_VOLUME] = 0xc0,
 187         [WM8915_DSP2_TX_RIGHT_VOLUME] = 0xc0,
 188         [WM8915_DSP2_RX_LEFT_VOLUME] = 0xc0,
 189         [WM8915_DSP2_RX_RIGHT_VOLUME] = 0xc0,
 190         [WM8915_DSP2_TX_FILTERS] = 0x2000,
 191         [WM8915_DSP2_RX_FILTERS_1] = 0x200,
 192         [WM8915_DSP2_RX_FILTERS_2] = 0x10,
 193         [WM8915_DSP2_DRC_1] = 0x98,
 194         [WM8915_DSP2_DRC_2] = 0x845,
 195         [WM8915_DSP2_RX_EQ_GAINS_1] = 0x6318,
 196         [WM8915_DSP2_RX_EQ_GAINS_2] = 0x6300,
 197         [WM8915_DSP2_RX_EQ_BAND_1_A] = 0xfca,
 198         [WM8915_DSP2_RX_EQ_BAND_1_B] = 0x400,
 199         [WM8915_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
 200         [WM8915_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
 201         [WM8915_DSP2_RX_EQ_BAND_2_B] = 0xf145,
 202         [WM8915_DSP2_RX_EQ_BAND_2_C] = 0xb75,
 203         [WM8915_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
 204         [WM8915_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
 205         [WM8915_DSP2_RX_EQ_BAND_3_B] = 0xf373,
 206         [WM8915_DSP2_RX_EQ_BAND_3_C] = 0xa54,
 207         [WM8915_DSP2_RX_EQ_BAND_3_PG] = 0x558,
 208         [WM8915_DSP2_RX_EQ_BAND_4_A] = 0x168e,
 209         [WM8915_DSP2_RX_EQ_BAND_4_B] = 0xf829,
 210         [WM8915_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
 211         [WM8915_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
 212         [WM8915_DSP2_RX_EQ_BAND_5_A] = 0x564,
 213         [WM8915_DSP2_RX_EQ_BAND_5_B] = 0x559,
 214         [WM8915_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
 215         [WM8915_OVERSAMPLING] = 0xd,
 216         [WM8915_SIDETONE] = 0x1040,
 217         [WM8915_GPIO_1] = 0xa101,
 218         [WM8915_GPIO_2] = 0xa101,
 219         [WM8915_GPIO_3] = 0xa101,
 220         [WM8915_GPIO_4] = 0xa101,
 221         [WM8915_GPIO_5] = 0xa101,
 222         [WM8915_PULL_CONTROL_2] = 0x140,
 223         [WM8915_INTERRUPT_STATUS_1_MASK] = 0x1f,
 224         [WM8915_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
 225         [WM8915_RIGHT_PDM_SPEAKER] = 0x1,
 226         [WM8915_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
 227         [WM8915_PDM_SPEAKER_VOLUME] = 0x66,
 228         [WM8915_WRITE_SEQUENCER_0] = 0x1,
 229         [WM8915_WRITE_SEQUENCER_1] = 0x1,
 230         [WM8915_WRITE_SEQUENCER_3] = 0x6,
 231         [WM8915_WRITE_SEQUENCER_4] = 0x40,
 232         [WM8915_WRITE_SEQUENCER_5] = 0x1,
 233         [WM8915_WRITE_SEQUENCER_6] = 0xf,
 234         [WM8915_WRITE_SEQUENCER_7] = 0x6,
 235         [WM8915_WRITE_SEQUENCER_8] = 0x1,
 236         [WM8915_WRITE_SEQUENCER_9] = 0x3,
 237         [WM8915_WRITE_SEQUENCER_10] = 0x104,
 238         [WM8915_WRITE_SEQUENCER_12] = 0x60,
 239         [WM8915_WRITE_SEQUENCER_13] = 0x11,
 240         [WM8915_WRITE_SEQUENCER_14] = 0x401,
 241         [WM8915_WRITE_SEQUENCER_16] = 0x50,
 242         [WM8915_WRITE_SEQUENCER_17] = 0x3,
 243         [WM8915_WRITE_SEQUENCER_18] = 0x100,
 244         [WM8915_WRITE_SEQUENCER_20] = 0x51,
 245         [WM8915_WRITE_SEQUENCER_21] = 0x3,
 246         [WM8915_WRITE_SEQUENCER_22] = 0x104,
 247         [WM8915_WRITE_SEQUENCER_23] = 0xa,
 248         [WM8915_WRITE_SEQUENCER_24] = 0x60,
 249         [WM8915_WRITE_SEQUENCER_25] = 0x3b,
 250         [WM8915_WRITE_SEQUENCER_26] = 0x502,
 251         [WM8915_WRITE_SEQUENCER_27] = 0x100,
 252         [WM8915_WRITE_SEQUENCER_28] = 0x2fff,
 253         [WM8915_WRITE_SEQUENCER_32] = 0x2fff,
 254         [WM8915_WRITE_SEQUENCER_36] = 0x2fff,
 255         [WM8915_WRITE_SEQUENCER_40] = 0x2fff,
 256         [WM8915_WRITE_SEQUENCER_44] = 0x2fff,
 257         [WM8915_WRITE_SEQUENCER_48] = 0x2fff,
 258         [WM8915_WRITE_SEQUENCER_52] = 0x2fff,
 259         [WM8915_WRITE_SEQUENCER_56] = 0x2fff,
 260         [WM8915_WRITE_SEQUENCER_60] = 0x2fff,
 261         [WM8915_WRITE_SEQUENCER_64] = 0x1,
 262         [WM8915_WRITE_SEQUENCER_65] = 0x1,
 263         [WM8915_WRITE_SEQUENCER_67] = 0x6,
 264         [WM8915_WRITE_SEQUENCER_68] = 0x40,
 265         [WM8915_WRITE_SEQUENCER_69] = 0x1,
 266         [WM8915_WRITE_SEQUENCER_70] = 0xf,
 267         [WM8915_WRITE_SEQUENCER_71] = 0x6,
 268         [WM8915_WRITE_SEQUENCER_72] = 0x1,
 269         [WM8915_WRITE_SEQUENCER_73] = 0x3,
 270         [WM8915_WRITE_SEQUENCER_74] = 0x104,
 271         [WM8915_WRITE_SEQUENCER_76] = 0x60,
 272         [WM8915_WRITE_SEQUENCER_77] = 0x11,
 273         [WM8915_WRITE_SEQUENCER_78] = 0x401,
 274         [WM8915_WRITE_SEQUENCER_80] = 0x50,
 275         [WM8915_WRITE_SEQUENCER_81] = 0x3,
 276         [WM8915_WRITE_SEQUENCER_82] = 0x100,
 277         [WM8915_WRITE_SEQUENCER_84] = 0x60,
 278         [WM8915_WRITE_SEQUENCER_85] = 0x3b,
 279         [WM8915_WRITE_SEQUENCER_86] = 0x502,
 280         [WM8915_WRITE_SEQUENCER_87] = 0x100,
 281         [WM8915_WRITE_SEQUENCER_88] = 0x2fff,
 282         [WM8915_WRITE_SEQUENCER_92] = 0x2fff,
 283         [WM8915_WRITE_SEQUENCER_96] = 0x2fff,
 284         [WM8915_WRITE_SEQUENCER_100] = 0x2fff,
 285         [WM8915_WRITE_SEQUENCER_104] = 0x2fff,
 286         [WM8915_WRITE_SEQUENCER_108] = 0x2fff,
 287         [WM8915_WRITE_SEQUENCER_112] = 0x2fff,
 288         [WM8915_WRITE_SEQUENCER_116] = 0x2fff,
 289         [WM8915_WRITE_SEQUENCER_120] = 0x2fff,
 290         [WM8915_WRITE_SEQUENCER_124] = 0x2fff,
 291         [WM8915_WRITE_SEQUENCER_128] = 0x1,
 292         [WM8915_WRITE_SEQUENCER_129] = 0x1,
 293         [WM8915_WRITE_SEQUENCER_131] = 0x6,
 294         [WM8915_WRITE_SEQUENCER_132] = 0x40,
 295         [WM8915_WRITE_SEQUENCER_133] = 0x1,
 296         [WM8915_WRITE_SEQUENCER_134] = 0xf,
 297         [WM8915_WRITE_SEQUENCER_135] = 0x6,
 298         [WM8915_WRITE_SEQUENCER_136] = 0x1,
 299         [WM8915_WRITE_SEQUENCER_137] = 0x3,
 300         [WM8915_WRITE_SEQUENCER_138] = 0x106,
 301         [WM8915_WRITE_SEQUENCER_140] = 0x61,
 302         [WM8915_WRITE_SEQUENCER_141] = 0x11,
 303         [WM8915_WRITE_SEQUENCER_142] = 0x401,
 304         [WM8915_WRITE_SEQUENCER_144] = 0x50,
 305         [WM8915_WRITE_SEQUENCER_145] = 0x3,
 306         [WM8915_WRITE_SEQUENCER_146] = 0x102,
 307         [WM8915_WRITE_SEQUENCER_148] = 0x51,
 308         [WM8915_WRITE_SEQUENCER_149] = 0x3,
 309         [WM8915_WRITE_SEQUENCER_150] = 0x106,
 310         [WM8915_WRITE_SEQUENCER_151] = 0xa,
 311         [WM8915_WRITE_SEQUENCER_152] = 0x61,
 312         [WM8915_WRITE_SEQUENCER_153] = 0x3b,
 313         [WM8915_WRITE_SEQUENCER_154] = 0x502,
 314         [WM8915_WRITE_SEQUENCER_155] = 0x100,
 315         [WM8915_WRITE_SEQUENCER_156] = 0x2fff,
 316         [WM8915_WRITE_SEQUENCER_160] = 0x2fff,
 317         [WM8915_WRITE_SEQUENCER_164] = 0x2fff,
 318         [WM8915_WRITE_SEQUENCER_168] = 0x2fff,
 319         [WM8915_WRITE_SEQUENCER_172] = 0x2fff,
 320         [WM8915_WRITE_SEQUENCER_176] = 0x2fff,
 321         [WM8915_WRITE_SEQUENCER_180] = 0x2fff,
 322         [WM8915_WRITE_SEQUENCER_184] = 0x2fff,
 323         [WM8915_WRITE_SEQUENCER_188] = 0x2fff,
 324         [WM8915_WRITE_SEQUENCER_192] = 0x1,
 325         [WM8915_WRITE_SEQUENCER_193] = 0x1,
 326         [WM8915_WRITE_SEQUENCER_195] = 0x6,
 327         [WM8915_WRITE_SEQUENCER_196] = 0x40,
 328         [WM8915_WRITE_SEQUENCER_197] = 0x1,
 329         [WM8915_WRITE_SEQUENCER_198] = 0xf,
 330         [WM8915_WRITE_SEQUENCER_199] = 0x6,
 331         [WM8915_WRITE_SEQUENCER_200] = 0x1,
 332         [WM8915_WRITE_SEQUENCER_201] = 0x3,
 333         [WM8915_WRITE_SEQUENCER_202] = 0x106,
 334         [WM8915_WRITE_SEQUENCER_204] = 0x61,
 335         [WM8915_WRITE_SEQUENCER_205] = 0x11,
 336         [WM8915_WRITE_SEQUENCER_206] = 0x401,
 337         [WM8915_WRITE_SEQUENCER_208] = 0x50,
 338         [WM8915_WRITE_SEQUENCER_209] = 0x3,
 339         [WM8915_WRITE_SEQUENCER_210] = 0x102,
 340         [WM8915_WRITE_SEQUENCER_212] = 0x61,
 341         [WM8915_WRITE_SEQUENCER_213] = 0x3b,
 342         [WM8915_WRITE_SEQUENCER_214] = 0x502,
 343         [WM8915_WRITE_SEQUENCER_215] = 0x100,
 344         [WM8915_WRITE_SEQUENCER_216] = 0x2fff,
 345         [WM8915_WRITE_SEQUENCER_220] = 0x2fff,
 346         [WM8915_WRITE_SEQUENCER_224] = 0x2fff,
 347         [WM8915_WRITE_SEQUENCER_228] = 0x2fff,
 348         [WM8915_WRITE_SEQUENCER_232] = 0x2fff,
 349         [WM8915_WRITE_SEQUENCER_236] = 0x2fff,
 350         [WM8915_WRITE_SEQUENCER_240] = 0x2fff,
 351         [WM8915_WRITE_SEQUENCER_244] = 0x2fff,
 352         [WM8915_WRITE_SEQUENCER_248] = 0x2fff,
 353         [WM8915_WRITE_SEQUENCER_252] = 0x2fff,
 354         [WM8915_WRITE_SEQUENCER_256] = 0x60,
 355         [WM8915_WRITE_SEQUENCER_258] = 0x601,
 356         [WM8915_WRITE_SEQUENCER_260] = 0x50,
 357         [WM8915_WRITE_SEQUENCER_262] = 0x100,
 358         [WM8915_WRITE_SEQUENCER_264] = 0x1,
 359         [WM8915_WRITE_SEQUENCER_266] = 0x104,
 360         [WM8915_WRITE_SEQUENCER_267] = 0x100,
 361         [WM8915_WRITE_SEQUENCER_268] = 0x2fff,
 362         [WM8915_WRITE_SEQUENCER_272] = 0x2fff,
 363         [WM8915_WRITE_SEQUENCER_276] = 0x2fff,
 364         [WM8915_WRITE_SEQUENCER_280] = 0x2fff,
 365         [WM8915_WRITE_SEQUENCER_284] = 0x2fff,
 366         [WM8915_WRITE_SEQUENCER_288] = 0x2fff,
 367         [WM8915_WRITE_SEQUENCER_292] = 0x2fff,
 368         [WM8915_WRITE_SEQUENCER_296] = 0x2fff,
 369         [WM8915_WRITE_SEQUENCER_300] = 0x2fff,
 370         [WM8915_WRITE_SEQUENCER_304] = 0x2fff,
 371         [WM8915_WRITE_SEQUENCER_308] = 0x2fff,
 372         [WM8915_WRITE_SEQUENCER_312] = 0x2fff,
 373         [WM8915_WRITE_SEQUENCER_316] = 0x2fff,
 374         [WM8915_WRITE_SEQUENCER_320] = 0x61,
 375         [WM8915_WRITE_SEQUENCER_322] = 0x601,
 376         [WM8915_WRITE_SEQUENCER_324] = 0x50,
 377         [WM8915_WRITE_SEQUENCER_326] = 0x102,
 378         [WM8915_WRITE_SEQUENCER_328] = 0x1,
 379         [WM8915_WRITE_SEQUENCER_330] = 0x106,
 380         [WM8915_WRITE_SEQUENCER_331] = 0x100,
 381         [WM8915_WRITE_SEQUENCER_332] = 0x2fff,
 382         [WM8915_WRITE_SEQUENCER_336] = 0x2fff,
 383         [WM8915_WRITE_SEQUENCER_340] = 0x2fff,
 384         [WM8915_WRITE_SEQUENCER_344] = 0x2fff,
 385         [WM8915_WRITE_SEQUENCER_348] = 0x2fff,
 386         [WM8915_WRITE_SEQUENCER_352] = 0x2fff,
 387         [WM8915_WRITE_SEQUENCER_356] = 0x2fff,
 388         [WM8915_WRITE_SEQUENCER_360] = 0x2fff,
 389         [WM8915_WRITE_SEQUENCER_364] = 0x2fff,
 390         [WM8915_WRITE_SEQUENCER_368] = 0x2fff,
 391         [WM8915_WRITE_SEQUENCER_372] = 0x2fff,
 392         [WM8915_WRITE_SEQUENCER_376] = 0x2fff,
 393         [WM8915_WRITE_SEQUENCER_380] = 0x2fff,
 394         [WM8915_WRITE_SEQUENCER_384] = 0x60,
 395         [WM8915_WRITE_SEQUENCER_386] = 0x601,
 396         [WM8915_WRITE_SEQUENCER_388] = 0x61,
 397         [WM8915_WRITE_SEQUENCER_390] = 0x601,
 398         [WM8915_WRITE_SEQUENCER_392] = 0x50,
 399         [WM8915_WRITE_SEQUENCER_394] = 0x300,
 400         [WM8915_WRITE_SEQUENCER_396] = 0x1,
 401         [WM8915_WRITE_SEQUENCER_398] = 0x304,
 402         [WM8915_WRITE_SEQUENCER_400] = 0x40,
 403         [WM8915_WRITE_SEQUENCER_402] = 0xf,
 404         [WM8915_WRITE_SEQUENCER_404] = 0x1,
 405         [WM8915_WRITE_SEQUENCER_407] = 0x100,
 406 };
 407
 408 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
 409 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
 410 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 411 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
 412 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
 413 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
 414 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 415
 416 static const char *sidetone_hpf_text[] = {
 417         "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
 418 };
 419
 420 static const struct soc_enum sidetone_hpf =
 421         SOC_ENUM_SINGLE(WM8915_SIDETONE, 7, 6, sidetone_hpf_text);
 422
 423 static const char *hpf_mode_text[] = {
 424         "HiFi", "Custom", "Voice"
 425 };
 426
 427 static const struct soc_enum dsp1tx_hpf_mode =
 428         SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
 429
 430 static const struct soc_enum dsp2tx_hpf_mode =
 431         SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
 432
 433 static const char *hpf_cutoff_text[] = {
 434         "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
 435 };
 436
 437 static const struct soc_enum dsp1tx_hpf_cutoff =
 438         SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
 439
 440 static const struct soc_enum dsp2tx_hpf_cutoff =
 441         SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
 442
 443 static void wm8915_set_retune_mobile(struct snd_soc_codec *codec, int block)
 444 {
 445         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
 446         struct wm8915_pdata *pdata = &wm8915->pdata;
 447         int base, best, best_val, save, i, cfg, iface;
 448
 449         if (!wm8915->num_retune_mobile_texts)
 450                 return;
 451
 452         switch (block) {
 453         case 0:
 454                 base = WM8915_DSP1_RX_EQ_GAINS_1;
 455                 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
 456                     WM8915_DSP1RX_SRC)
 457                         iface = 1;
 458                 else
 459                         iface = 0;
 460                 break;
 461         case 1:
 462                 base = WM8915_DSP1_RX_EQ_GAINS_2;
 463                 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
 464                     WM8915_DSP2RX_SRC)
 465                         iface = 1;
 466                 else
 467                         iface = 0;
 468                 break;
 469         default:
 470                 return;
 471         }
 472
 473         /* Find the version of the currently selected configuration
 474          * with the nearest sample rate. */
 475         cfg = wm8915->retune_mobile_cfg[block];
 476         best = 0;
 477         best_val = INT_MAX;
 478         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 479                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 480                            wm8915->retune_mobile_texts[cfg]) == 0 &&
 481                     abs(pdata->retune_mobile_cfgs[i].rate
 482                         - wm8915->rx_rate[iface]) < best_val) {
 483                         best = i;
 484                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 485                                        - wm8915->rx_rate[iface]);
 486                 }
 487         }
 488
 489         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 490                 block,
 491                 pdata->retune_mobile_cfgs[best].name,
 492                 pdata->retune_mobile_cfgs[best].rate,
 493                 wm8915->rx_rate[iface]);
 494
 495         /* The EQ will be disabled while reconfiguring it, remember the
 496          * current configuration.
 497          */
 498         save = snd_soc_read(codec, base);
 499         save &= WM8915_DSP1RX_EQ_ENA;
 500
 501         for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
 502                 snd_soc_update_bits(codec, base + i, 0xffff,
 503                                     pdata->retune_mobile_cfgs[best].regs[i]);
 504
 505         snd_soc_update_bits(codec, base, WM8915_DSP1RX_EQ_ENA, save);
 506 }
 507
 508 /* Icky as hell but saves code duplication */
 509 static int wm8915_get_retune_mobile_block(const char *name)
 510 {
 511         if (strcmp(name, "DSP1 EQ Mode") == 0)
 512                 return 0;
 513         if (strcmp(name, "DSP2 EQ Mode") == 0)
 514                 return 1;
 515         return -EINVAL;
 516 }
 517
 518 static int wm8915_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 519                                          struct snd_ctl_elem_value *ucontrol)
 520 {
 521         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 522         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
 523         struct wm8915_pdata *pdata = &wm8915->pdata;
 524         int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
 525         int value = ucontrol->value.integer.value[0];
 526
 527         if (block < 0)
 528                 return block;
 529
 530         if (value >= pdata->num_retune_mobile_cfgs)
 531                 return -EINVAL;
 532
 533         wm8915->retune_mobile_cfg[block] = value;
 534
 535         wm8915_set_retune_mobile(codec, block);
 536
 537         return 0;
 538 }
 539
 540 static int wm8915_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 541                                          struct snd_ctl_elem_value *ucontrol)
 542 {
 543         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 544         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
 545         int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
 546
 547         ucontrol->value.enumerated.item[0] = wm8915->retune_mobile_cfg[block];
 548
 549         return 0;
 550 }
 551
 552 static const struct snd_kcontrol_new wm8915_snd_controls[] = {
 553 SOC_DOUBLE_R_TLV("Capture Volume", WM8915_LEFT_LINE_INPUT_VOLUME,
 554                  WM8915_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
 555 SOC_DOUBLE_R("Capture ZC Switch", WM8915_LEFT_LINE_INPUT_VOLUME,
 556              WM8915_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
 557
 558 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8915_DAC1_MIXER_VOLUMES,
 559                0, 5, 24, 0, sidetone_tlv),
 560 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8915_DAC2_MIXER_VOLUMES,
 561                0, 5, 24, 0, sidetone_tlv),
 562 SOC_SINGLE("Sidetone LPF Switch", WM8915_SIDETONE, 12, 1, 0),
 563 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
 564 SOC_SINGLE("Sidetone HPF Switch", WM8915_SIDETONE, 6, 1, 0),
 565
 566 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8915_DSP1_TX_LEFT_VOLUME,
 567                  WM8915_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 568 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8915_DSP2_TX_LEFT_VOLUME,
 569                  WM8915_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 570
 571 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8915_DSP1_TX_FILTERS,
 572            13, 1, 0),
 573 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8915_DSP1_TX_FILTERS, 12, 11, 1, 0),
 574 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
 575 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
 576
 577 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8915_DSP2_TX_FILTERS,
 578            13, 1, 0),
 579 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8915_DSP2_TX_FILTERS, 12, 11, 1, 0),
 580 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
 581 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
 582
 583 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8915_DSP1_RX_LEFT_VOLUME,
 584                  WM8915_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 585 SOC_SINGLE("DSP1 Playback Switch", WM8915_DSP1_RX_FILTERS_1, 9, 1, 1),
 586
 587 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8915_DSP2_RX_LEFT_VOLUME,
 588                  WM8915_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 589 SOC_SINGLE("DSP2 Playback Switch", WM8915_DSP2_RX_FILTERS_1, 9, 1, 1),
 590
 591 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8915_DAC1_LEFT_VOLUME,
 592                  WM8915_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 593 SOC_DOUBLE_R("DAC1 Switch", WM8915_DAC1_LEFT_VOLUME,
 594              WM8915_DAC1_RIGHT_VOLUME, 9, 1, 1),
 595
 596 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8915_DAC2_LEFT_VOLUME,
 597                  WM8915_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
 598 SOC_DOUBLE_R("DAC2 Switch", WM8915_DAC2_LEFT_VOLUME,
 599              WM8915_DAC2_RIGHT_VOLUME, 9, 1, 1),
 600
 601 SOC_SINGLE("Speaker High Performance Switch", WM8915_OVERSAMPLING, 3, 1, 0),
 602 SOC_SINGLE("DMIC High Performance Switch", WM8915_OVERSAMPLING, 2, 1, 0),
 603 SOC_SINGLE("ADC High Performance Switch", WM8915_OVERSAMPLING, 1, 1, 0),
 604 SOC_SINGLE("DAC High Performance Switch", WM8915_OVERSAMPLING, 0, 1, 0),
 605
 606 SOC_SINGLE("DAC Soft Mute Switch", WM8915_DAC_SOFTMUTE, 1, 1, 0),
 607 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8915_DAC_SOFTMUTE, 0, 1, 0),
 608
 609 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8915_DAC1_HPOUT1_VOLUME, 0, 4,
 610                8, 0, out_digital_tlv),
 611 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8915_DAC2_HPOUT2_VOLUME, 0, 4,
 612                8, 0, out_digital_tlv),
 613
 614 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8915_OUTPUT1_LEFT_VOLUME,
 615                  WM8915_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
 616 SOC_DOUBLE_R("Output 1 ZC Switch",  WM8915_OUTPUT1_LEFT_VOLUME,
 617              WM8915_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
 618
 619 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8915_OUTPUT2_LEFT_VOLUME,
 620                  WM8915_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
 621 SOC_DOUBLE_R("Output 2 ZC Switch",  WM8915_OUTPUT2_LEFT_VOLUME,
 622              WM8915_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
 623
 624 SOC_DOUBLE_TLV("Speaker Volume", WM8915_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
 625                spk_tlv),
 626 SOC_DOUBLE_R("Speaker Switch", WM8915_LEFT_PDM_SPEAKER,
 627              WM8915_RIGHT_PDM_SPEAKER, 3, 1, 1),
 628 SOC_DOUBLE_R("Speaker ZC Switch", WM8915_LEFT_PDM_SPEAKER,
 629              WM8915_RIGHT_PDM_SPEAKER, 2, 1, 0),
 630
 631 SOC_SINGLE("DSP1 EQ Switch", WM8915_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
 632 SOC_SINGLE("DSP2 EQ Switch", WM8915_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
 633 };
 634
 635 static const struct snd_kcontrol_new wm8915_eq_controls[] = {
 636 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
 637                eq_tlv),
 638 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
 639                eq_tlv),
 640 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
 641                eq_tlv),
 642 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
 643                eq_tlv),
 644 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
 645                eq_tlv),
 646
 647 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
 648                eq_tlv),
 649 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
 650                eq_tlv),
 651 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
 652                eq_tlv),
 653 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
 654                eq_tlv),
 655 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
 656                eq_tlv),
 657 };
 658
 659 static int cp_event(struct snd_soc_dapm_widget *w,
 660                     struct snd_kcontrol *kcontrol, int event)
 661 {
 662         switch (event) {
 663         case SND_SOC_DAPM_POST_PMU:
 664                 msleep(5);
 665                 break;
 666         default:
 667                 BUG();
 668                 return -EINVAL;
 669         }
 670
 671         return 0;
 672 }
 673
 674 static int rmv_short_event(struct snd_soc_dapm_widget *w,
 675                            struct snd_kcontrol *kcontrol, int event)
 676 {
 677         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
 678
 679         /* Record which outputs we enabled */
 680         switch (event) {
 681         case SND_SOC_DAPM_PRE_PMD:
 682                 wm8915->hpout_pending &= ~w->shift;
 683                 break;
 684         case SND_SOC_DAPM_PRE_PMU:
 685                 wm8915->hpout_pending |= w->shift;
 686                 break;
 687         default:
 688                 BUG();
 689                 return -EINVAL;
 690         }
 691
 692         return 0;
 693 }
 694
 695 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
 696 {
 697         struct i2c_client *i2c = to_i2c_client(codec->dev);
 698         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
 699         int i, ret;
 700         unsigned long timeout = 200;
 701
 702         snd_soc_write(codec, WM8915_DC_SERVO_2, mask);
 703
 704         /* Use the interrupt if possible */
 705         do {
 706                 if (i2c->irq) {
 707                         timeout = wait_for_completion_timeout(&wm8915->dcs_done,
 708                                                               msecs_to_jiffies(200));
 709                         if (timeout == 0)
 710                                 dev_err(codec->dev, "DC servo timed out\n");
 711
 712                 } else {
 713                         msleep(1);
 714                         if (--i) {
 715                                 timeout = 0;
 716                                 break;
 717                         }
 718                 }
 719
 720                 ret = snd_soc_read(codec, WM8915_DC_SERVO_2);
 721                 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
 722         } while (ret & mask);
 723
 724         if (timeout == 0)
 725                 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
 726         else
 727                 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
 728 }
 729
 730 static void wm8915_seq_notifier(struct snd_soc_dapm_context *dapm,
 731                                 enum snd_soc_dapm_type event, int subseq)
 732 {
 733         struct snd_soc_codec *codec = container_of(dapm,
 734                                                    struct snd_soc_codec, dapm);
 735         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
 736         u16 val, mask;
 737
 738         /* Complete any pending DC servo starts */
 739         if (wm8915->dcs_pending) {
 740                 dev_dbg(codec->dev, "Starting DC servo for %x\n",
 741                         wm8915->dcs_pending);
 742
 743                 /* Trigger a startup sequence */
 744                 wait_for_dc_servo(codec, wm8915->dcs_pending
 745                                          << WM8915_DCS_TRIG_STARTUP_0_SHIFT);
 746
 747                 wm8915->dcs_pending = 0;
 748         }
 749
 750         if (wm8915->hpout_pending != wm8915->hpout_ena) {
 751                 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
 752                         wm8915->hpout_ena, wm8915->hpout_pending);
 753
 754                 val = 0;
 755                 mask = 0;
 756                 if (wm8915->hpout_pending & HPOUT1L) {
 757                         val |= WM8915_HPOUT1L_RMV_SHORT;
 758                         mask |= WM8915_HPOUT1L_RMV_SHORT;
 759                 } else {
 760                         mask |= WM8915_HPOUT1L_RMV_SHORT |
 761                                 WM8915_HPOUT1L_OUTP |
 762                                 WM8915_HPOUT1L_DLY;
 763                 }
 764
 765                 if (wm8915->hpout_pending & HPOUT1R) {
 766                         val |= WM8915_HPOUT1R_RMV_SHORT;
 767                         mask |= WM8915_HPOUT1R_RMV_SHORT;
 768                 } else {
 769                         mask |= WM8915_HPOUT1R_RMV_SHORT |
 770                                 WM8915_HPOUT1R_OUTP |
 771                                 WM8915_HPOUT1R_DLY;
 772                 }
 773
 774                 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_1, mask, val);
 775
 776                 val = 0;
 777                 mask = 0;
 778                 if (wm8915->hpout_pending & HPOUT2L) {
 779                         val |= WM8915_HPOUT2L_RMV_SHORT;
 780                         mask |= WM8915_HPOUT2L_RMV_SHORT;
 781                 } else {
 782                         mask |= WM8915_HPOUT2L_RMV_SHORT |
 783                                 WM8915_HPOUT2L_OUTP |
 784                                 WM8915_HPOUT2L_DLY;
 785                 }
 786
 787                 if (wm8915->hpout_pending & HPOUT2R) {
 788                         val |= WM8915_HPOUT2R_RMV_SHORT;
 789                         mask |= WM8915_HPOUT2R_RMV_SHORT;
 790                 } else {
 791                         mask |= WM8915_HPOUT2R_RMV_SHORT |
 792                                 WM8915_HPOUT2R_OUTP |
 793                                 WM8915_HPOUT2R_DLY;
 794                 }
 795
 796                 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_2, mask, val);
 797
 798                 wm8915->hpout_ena = wm8915->hpout_pending;
 799         }
 800 }
 801
 802 static int dcs_start(struct snd_soc_dapm_widget *w,
 803                      struct snd_kcontrol *kcontrol, int event)
 804 {
 805         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
 806
 807         switch (event) {
 808         case SND_SOC_DAPM_POST_PMU:
 809                 wm8915->dcs_pending |= 1 << w->shift;
 810                 break;
 811         default:
 812                 BUG();
 813                 return -EINVAL;
 814         }
 815
 816         return 0;
 817 }
 818
 819 static const char *sidetone_text[] = {
 820         "IN1", "IN2",
 821 };
 822
 823 static const struct soc_enum left_sidetone_enum =
 824         SOC_ENUM_SINGLE(WM8915_SIDETONE, 0, 2, sidetone_text);
 825
 826 static const struct snd_kcontrol_new left_sidetone =
 827         SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
 828
 829 static const struct soc_enum right_sidetone_enum =
 830         SOC_ENUM_SINGLE(WM8915_SIDETONE, 1, 2, sidetone_text);
 831
 832 static const struct snd_kcontrol_new right_sidetone =
 833         SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
 834
 835 static const char *spk_text[] = {
 836         "DAC1L", "DAC1R", "DAC2L", "DAC2R"
 837 };
 838
 839 static const struct soc_enum spkl_enum =
 840         SOC_ENUM_SINGLE(WM8915_LEFT_PDM_SPEAKER, 0, 4, spk_text);
 841
 842 static const struct snd_kcontrol_new spkl_mux =
 843         SOC_DAPM_ENUM("SPKL", spkl_enum);
 844
 845 static const struct soc_enum spkr_enum =
 846         SOC_ENUM_SINGLE(WM8915_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
 847
 848 static const struct snd_kcontrol_new spkr_mux =
 849         SOC_DAPM_ENUM("SPKR", spkr_enum);
 850
 851 static const char *dsp1rx_text[] = {
 852         "AIF1", "AIF2"
 853 };
 854
 855 static const struct soc_enum dsp1rx_enum =
 856         SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
 857
 858 static const struct snd_kcontrol_new dsp1rx =
 859         SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
 860
 861 static const char *dsp2rx_text[] = {
 862          "AIF2", "AIF1"
 863 };
 864
 865 static const struct soc_enum dsp2rx_enum =
 866         SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
 867
 868 static const struct snd_kcontrol_new dsp2rx =
 869         SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
 870
 871 static const char *aif2tx_text[] = {
 872         "DSP2", "DSP1", "AIF1"
 873 };
 874
 875 static const struct soc_enum aif2tx_enum =
 876         SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
 877
 878 static const struct snd_kcontrol_new aif2tx =
 879         SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
 880
 881 static const char *inmux_text[] = {
 882         "ADC", "DMIC1", "DMIC2"
 883 };
 884
 885 static const struct soc_enum in1_enum =
 886         SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 0, 3, inmux_text);
 887
 888 static const struct snd_kcontrol_new in1_mux =
 889         SOC_DAPM_ENUM("IN1 Mux", in1_enum);
 890
 891 static const struct soc_enum in2_enum =
 892         SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 4, 3, inmux_text);
 893
 894 static const struct snd_kcontrol_new in2_mux =
 895         SOC_DAPM_ENUM("IN2 Mux", in2_enum);
 896
 897 static const struct snd_kcontrol_new dac2r_mix[] = {
 898 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
 899                 5, 1, 0),
 900 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
 901                 4, 1, 0),
 902 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
 903 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
 904 };
 905
 906 static const struct snd_kcontrol_new dac2l_mix[] = {
 907 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
 908                 5, 1, 0),
 909 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
 910                 4, 1, 0),
 911 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
 912 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
 913 };
 914
 915 static const struct snd_kcontrol_new dac1r_mix[] = {
 916 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
 917                 5, 1, 0),
 918 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
 919                 4, 1, 0),
 920 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
 921 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
 922 };
 923
 924 static const struct snd_kcontrol_new dac1l_mix[] = {
 925 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
 926                 5, 1, 0),
 927 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
 928                 4, 1, 0),
 929 SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
 930 SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
 931 };
 932
 933 static const struct snd_kcontrol_new dsp1txl[] = {
 934 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
 935                 1, 1, 0),
 936 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
 937                 0, 1, 0),
 938 };
 939
 940 static const struct snd_kcontrol_new dsp1txr[] = {
 941 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
 942                 1, 1, 0),
 943 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
 944                 0, 1, 0),
 945 };
 946
 947 static const struct snd_kcontrol_new dsp2txl[] = {
 948 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
 949                 1, 1, 0),
 950 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
 951                 0, 1, 0),
 952 };
 953
 954 static const struct snd_kcontrol_new dsp2txr[] = {
 955 SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
 956                 1, 1, 0),
 957 SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
 958                 0, 1, 0),
 959 };
 960
 961
 962 static const struct snd_soc_dapm_widget wm8915_dapm_widgets[] = {
 963 SND_SOC_DAPM_INPUT("IN1LN"),
 964 SND_SOC_DAPM_INPUT("IN1LP"),
 965 SND_SOC_DAPM_INPUT("IN1RN"),
 966 SND_SOC_DAPM_INPUT("IN1RP"),
 967
 968 SND_SOC_DAPM_INPUT("IN2LN"),
 969 SND_SOC_DAPM_INPUT("IN2LP"),
 970 SND_SOC_DAPM_INPUT("IN2RN"),
 971 SND_SOC_DAPM_INPUT("IN2RP"),
 972
 973 SND_SOC_DAPM_INPUT("DMIC1DAT"),
 974 SND_SOC_DAPM_INPUT("DMIC2DAT"),
 975
 976 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8915_AIF_CLOCKING_1, 0, 0, NULL, 0),
 977 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8915_CLOCKING_1, 1, 0, NULL, 0),
 978 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8915_CLOCKING_1, 2, 0, NULL, 0),
 979 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8915_CHARGE_PUMP_1, 15, 0, cp_event,
 980                       SND_SOC_DAPM_POST_PMU),
 981
 982 SND_SOC_DAPM_SUPPLY("LDO2", WM8915_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
 983 SND_SOC_DAPM_MICBIAS("MICB2", WM8915_POWER_MANAGEMENT_1, 9, 0),
 984 SND_SOC_DAPM_MICBIAS("MICB1", WM8915_POWER_MANAGEMENT_1, 8, 0),
 985
 986 SND_SOC_DAPM_PGA("IN1L PGA", WM8915_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
 987 SND_SOC_DAPM_PGA("IN1R PGA", WM8915_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
 988
 989 SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
 990 SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
 991 SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
 992 SND_SOC_DAPM_MUX("IN2R Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
 993
 994 SND_SOC_DAPM_PGA("IN1L", WM8915_POWER_MANAGEMENT_7, 2, 0, NULL, 0),
 995 SND_SOC_DAPM_PGA("IN1R", WM8915_POWER_MANAGEMENT_7, 3, 0, NULL, 0),
 996 SND_SOC_DAPM_PGA("IN2L", WM8915_POWER_MANAGEMENT_7, 6, 0, NULL, 0),
 997 SND_SOC_DAPM_PGA("IN2R", WM8915_POWER_MANAGEMENT_7, 7, 0, NULL, 0),
 998
 999 SND_SOC_DAPM_SUPPLY("DMIC2", WM8915_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1000 SND_SOC_DAPM_SUPPLY("DMIC1", WM8915_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1001
1002 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8915_POWER_MANAGEMENT_3, 5, 0),
1003 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8915_POWER_MANAGEMENT_3, 4, 0),
1004 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8915_POWER_MANAGEMENT_3, 3, 0),
1005 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8915_POWER_MANAGEMENT_3, 2, 0),
1006
1007 SND_SOC_DAPM_ADC("ADCL", NULL, WM8915_POWER_MANAGEMENT_3, 1, 0),
1008 SND_SOC_DAPM_ADC("ADCR", NULL, WM8915_POWER_MANAGEMENT_3, 0, 0),
1009
1010 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1011 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1012
1013 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 11, 0),
1014 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 10, 0),
1015 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 9, 0),
1016 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 8, 0),
1017
1018 SND_SOC_DAPM_MIXER("DSP2TXL", WM8915_POWER_MANAGEMENT_5, 11, 0,
1019                    dsp2txl, ARRAY_SIZE(dsp2txl)),
1020 SND_SOC_DAPM_MIXER("DSP2TXR", WM8915_POWER_MANAGEMENT_5, 10, 0,
1021                    dsp2txr, ARRAY_SIZE(dsp2txr)),
1022 SND_SOC_DAPM_MIXER("DSP1TXL", WM8915_POWER_MANAGEMENT_5, 9, 0,
1023                    dsp1txl, ARRAY_SIZE(dsp1txl)),
1024 SND_SOC_DAPM_MIXER("DSP1TXR", WM8915_POWER_MANAGEMENT_5, 8, 0,
1025                    dsp1txr, ARRAY_SIZE(dsp1txr)),
1026
1027 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1028                    dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1029 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1030                    dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1031 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1032                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1033 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1034                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1035
1036 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8915_POWER_MANAGEMENT_5, 3, 0),
1037 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8915_POWER_MANAGEMENT_5, 2, 0),
1038 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8915_POWER_MANAGEMENT_5, 1, 0),
1039 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8915_POWER_MANAGEMENT_5, 0, 0),
1040
1041 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1,
1042                     WM8915_POWER_MANAGEMENT_4, 9, 0),
1043 SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2,
1044                     WM8915_POWER_MANAGEMENT_4, 8, 0),
1045
1046 SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1,
1047                     WM8915_POWER_MANAGEMENT_6, 9, 0),
1048 SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2,
1049                     WM8915_POWER_MANAGEMENT_6, 8, 0),
1050
1051 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1052                     WM8915_POWER_MANAGEMENT_4, 5, 0),
1053 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1054                     WM8915_POWER_MANAGEMENT_4, 4, 0),
1055 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1056                     WM8915_POWER_MANAGEMENT_4, 3, 0),
1057 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1058                     WM8915_POWER_MANAGEMENT_4, 2, 0),
1059 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1060                     WM8915_POWER_MANAGEMENT_4, 1, 0),
1061 SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1062                     WM8915_POWER_MANAGEMENT_4, 0, 0),
1063
1064 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1065                      WM8915_POWER_MANAGEMENT_6, 5, 0),
1066 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1067                      WM8915_POWER_MANAGEMENT_6, 4, 0),
1068 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1069                      WM8915_POWER_MANAGEMENT_6, 3, 0),
1070 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1071                      WM8915_POWER_MANAGEMENT_6, 2, 0),
1072 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1073                      WM8915_POWER_MANAGEMENT_6, 1, 0),
1074 SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1075                      WM8915_POWER_MANAGEMENT_6, 0, 0),
1076
1077 /* We route as stereo pairs so define some dummy widgets to squash
1078  * things down for now.  RXA = 0,1, RXB = 2,3 and so on */
1079 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1080 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1081 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1082 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1083 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1084
1085 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1086 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1087 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1088
1089 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1090 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1091 SND_SOC_DAPM_PGA("SPKL PGA", WM8915_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1092 SND_SOC_DAPM_PGA("SPKR PGA", WM8915_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1093
1094 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8915_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1095 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8915_ANALOGUE_HP_2, 5, 0, NULL, 0),
1096 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8915_DC_SERVO_1, 2, 0, dcs_start,
1097                    SND_SOC_DAPM_POST_PMU),
1098 SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8915_ANALOGUE_HP_2, 6, 0, NULL, 0),
1099 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1100                    rmv_short_event,
1101                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1102
1103 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8915_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1104 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8915_ANALOGUE_HP_2, 1, 0, NULL, 0),
1105 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8915_DC_SERVO_1, 3, 0, dcs_start,
1106                    SND_SOC_DAPM_POST_PMU),
1107 SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8915_ANALOGUE_HP_2, 2, 0, NULL, 0),
1108 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1109                    rmv_short_event,
1110                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1111
1112 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8915_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1113 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8915_ANALOGUE_HP_1, 5, 0, NULL, 0),
1114 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8915_DC_SERVO_1, 0, 0, dcs_start,
1115                    SND_SOC_DAPM_POST_PMU),
1116 SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8915_ANALOGUE_HP_1, 6, 0, NULL, 0),
1117 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1118                    rmv_short_event,
1119                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1120
1121 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8915_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1122 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8915_ANALOGUE_HP_1, 1, 0, NULL, 0),
1123 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8915_DC_SERVO_1, 1, 0, dcs_start,
1124                    SND_SOC_DAPM_POST_PMU),
1125 SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8915_ANALOGUE_HP_1, 2, 0, NULL, 0),
1126 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1127                    rmv_short_event,
1128                    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1129
1130 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1131 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1132 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1133 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1134 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1135 };
1136
1137 static const struct snd_soc_dapm_route wm8915_dapm_routes[] = {
1138         { "AIFCLK", NULL, "SYSCLK" },
1139         { "SYSDSPCLK", NULL, "SYSCLK" },
1140         { "Charge Pump", NULL, "SYSCLK" },
1141
1142         { "MICB1", NULL, "LDO2" },
1143         { "MICB2", NULL, "LDO2" },
1144
1145         { "IN1L PGA", NULL, "IN2LN" },
1146         { "IN1L PGA", NULL, "IN2LP" },
1147         { "IN1L PGA", NULL, "IN1LN" },
1148         { "IN1L PGA", NULL, "IN1LP" },
1149
1150         { "IN1R PGA", NULL, "IN2RN" },
1151         { "IN1R PGA", NULL, "IN2RP" },
1152         { "IN1R PGA", NULL, "IN1RN" },
1153         { "IN1R PGA", NULL, "IN1RP" },
1154
1155         { "ADCL", NULL, "IN1L PGA" },
1156
1157         { "ADCR", NULL, "IN1R PGA" },
1158
1159         { "DMIC1L", NULL, "DMIC1DAT" },
1160         { "DMIC1R", NULL, "DMIC1DAT" },
1161         { "DMIC2L", NULL, "DMIC2DAT" },
1162         { "DMIC2R", NULL, "DMIC2DAT" },
1163
1164         { "DMIC2L", NULL, "DMIC2" },
1165         { "DMIC2R", NULL, "DMIC2" },
1166         { "DMIC1L", NULL, "DMIC1" },
1167         { "DMIC1R", NULL, "DMIC1" },
1168
1169         { "IN1L Mux", "ADC", "ADCL" },
1170         { "IN1L Mux", "DMIC1", "DMIC1L" },
1171         { "IN1L Mux", "DMIC2", "DMIC2L" },
1172
1173         { "IN1R Mux", "ADC", "ADCR" },
1174         { "IN1R Mux", "DMIC1", "DMIC1R" },
1175         { "IN1R Mux", "DMIC2", "DMIC2R" },
1176
1177         { "IN2L Mux", "ADC", "ADCL" },
1178         { "IN2L Mux", "DMIC1", "DMIC1L" },
1179         { "IN2L Mux", "DMIC2", "DMIC2L" },
1180
1181         { "IN2R Mux", "ADC", "ADCR" },
1182         { "IN2R Mux", "DMIC1", "DMIC1R" },
1183         { "IN2R Mux", "DMIC2", "DMIC2R" },
1184
1185         { "Left Sidetone", "IN1", "IN1L Mux" },
1186         { "Left Sidetone", "IN2", "IN2L Mux" },
1187
1188         { "Right Sidetone", "IN1", "IN1R Mux" },
1189         { "Right Sidetone", "IN2", "IN2R Mux" },
1190
1191         { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1192         { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1193
1194         { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1195         { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1196
1197         { "AIF1TX0", NULL, "DSP1TXL" },
1198         { "AIF1TX1", NULL, "DSP1TXR" },
1199         { "AIF1TX2", NULL, "DSP2TXL" },
1200         { "AIF1TX3", NULL, "DSP2TXR" },
1201         { "AIF1TX4", NULL, "AIF2RX0" },
1202         { "AIF1TX5", NULL, "AIF2RX1" },
1203
1204         { "AIF1RX0", NULL, "AIFCLK" },
1205         { "AIF1RX1", NULL, "AIFCLK" },
1206         { "AIF1RX2", NULL, "AIFCLK" },
1207         { "AIF1RX3", NULL, "AIFCLK" },
1208         { "AIF1RX4", NULL, "AIFCLK" },
1209         { "AIF1RX5", NULL, "AIFCLK" },
1210
1211         { "AIF2RX0", NULL, "AIFCLK" },
1212         { "AIF2RX1", NULL, "AIFCLK" },
1213
1214         { "DSP1RXL", NULL, "SYSDSPCLK" },
1215         { "DSP1RXR", NULL, "SYSDSPCLK" },
1216         { "DSP2RXL", NULL, "SYSDSPCLK" },
1217         { "DSP2RXR", NULL, "SYSDSPCLK" },
1218         { "DSP1TXL", NULL, "SYSDSPCLK" },
1219         { "DSP1TXR", NULL, "SYSDSPCLK" },
1220         { "DSP2TXL", NULL, "SYSDSPCLK" },
1221         { "DSP2TXR", NULL, "SYSDSPCLK" },
1222
1223         { "AIF1RXA", NULL, "AIF1RX0" },
1224         { "AIF1RXA", NULL, "AIF1RX1" },
1225         { "AIF1RXB", NULL, "AIF1RX2" },
1226         { "AIF1RXB", NULL, "AIF1RX3" },
1227         { "AIF1RXC", NULL, "AIF1RX4" },
1228         { "AIF1RXC", NULL, "AIF1RX5" },
1229
1230         { "AIF2RX", NULL, "AIF2RX0" },
1231         { "AIF2RX", NULL, "AIF2RX1" },
1232
1233         { "AIF2TX", "DSP2", "DSP2TX" },
1234         { "AIF2TX", "DSP1", "DSP1RX" },
1235         { "AIF2TX", "AIF1", "AIF1RXC" },
1236
1237         { "DSP1RXL", NULL, "DSP1RX" },
1238         { "DSP1RXR", NULL, "DSP1RX" },
1239         { "DSP2RXL", NULL, "DSP2RX" },
1240         { "DSP2RXR", NULL, "DSP2RX" },
1241
1242         { "DSP2TX", NULL, "DSP2TXL" },
1243         { "DSP2TX", NULL, "DSP2TXR" },
1244
1245         { "DSP1RX", "AIF1", "AIF1RXA" },
1246         { "DSP1RX", "AIF2", "AIF2RX" },
1247
1248         { "DSP2RX", "AIF1", "AIF1RXB" },
1249         { "DSP2RX", "AIF2", "AIF2RX" },
1250
1251         { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1252         { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1253         { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1254         { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1255
1256         { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1257         { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1258         { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1259         { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1260
1261         { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1262         { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1263         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1264         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1265
1266         { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1267         { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1268         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1269         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1270
1271         { "DAC1L", NULL, "DAC1L Mixer" },
1272         { "DAC1R", NULL, "DAC1R Mixer" },
1273         { "DAC2L", NULL, "DAC2L Mixer" },
1274         { "DAC2R", NULL, "DAC2R Mixer" },
1275
1276         { "HPOUT2L PGA", NULL, "Charge Pump" },
1277         { "HPOUT2L PGA", NULL, "DAC2L" },
1278         { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1279         { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1280         { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1281         { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1282
1283         { "HPOUT2R PGA", NULL, "Charge Pump" },
1284         { "HPOUT2R PGA", NULL, "DAC2R" },
1285         { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1286         { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1287         { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1288         { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1289
1290         { "HPOUT1L PGA", NULL, "Charge Pump" },
1291         { "HPOUT1L PGA", NULL, "DAC1L" },
1292         { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1293         { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1294         { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1295         { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1296
1297         { "HPOUT1R PGA", NULL, "Charge Pump" },
1298         { "HPOUT1R PGA", NULL, "DAC1R" },
1299         { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1300         { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1301         { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1302         { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1303
1304         { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1305         { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1306         { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1307         { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1308
1309         { "SPKL", "DAC1L", "DAC1L" },
1310         { "SPKL", "DAC1R", "DAC1R" },
1311         { "SPKL", "DAC2L", "DAC2L" },
1312         { "SPKL", "DAC2R", "DAC2R" },
1313
1314         { "SPKR", "DAC1L", "DAC1L" },
1315         { "SPKR", "DAC1R", "DAC1R" },
1316         { "SPKR", "DAC2L", "DAC2L" },
1317         { "SPKR", "DAC2R", "DAC2R" },
1318
1319         { "SPKL PGA", NULL, "SPKL" },
1320         { "SPKR PGA", NULL, "SPKR" },
1321
1322         { "SPKDAT", NULL, "SPKL PGA" },
1323         { "SPKDAT", NULL, "SPKR PGA" },
1324 };
1325
1326 static int wm8915_readable_register(struct snd_soc_codec *codec,
1327                                     unsigned int reg)
1328 {
1329         /* Due to the sparseness of the register map the compiler
1330          * output from an explicit switch statement ends up being much
1331          * more efficient than a table.
1332          */
1333         switch (reg) {
1334         case WM8915_SOFTWARE_RESET:
1335         case WM8915_POWER_MANAGEMENT_1:
1336         case WM8915_POWER_MANAGEMENT_2:
1337         case WM8915_POWER_MANAGEMENT_3:
1338         case WM8915_POWER_MANAGEMENT_4:
1339         case WM8915_POWER_MANAGEMENT_5:
1340         case WM8915_POWER_MANAGEMENT_6:
1341         case WM8915_POWER_MANAGEMENT_7:
1342         case WM8915_POWER_MANAGEMENT_8:
1343         case WM8915_LEFT_LINE_INPUT_VOLUME:
1344         case WM8915_RIGHT_LINE_INPUT_VOLUME:
1345         case WM8915_LINE_INPUT_CONTROL:
1346         case WM8915_DAC1_HPOUT1_VOLUME:
1347         case WM8915_DAC2_HPOUT2_VOLUME:
1348         case WM8915_DAC1_LEFT_VOLUME:
1349         case WM8915_DAC1_RIGHT_VOLUME:
1350         case WM8915_DAC2_LEFT_VOLUME:
1351         case WM8915_DAC2_RIGHT_VOLUME:
1352         case WM8915_OUTPUT1_LEFT_VOLUME:
1353         case WM8915_OUTPUT1_RIGHT_VOLUME:
1354         case WM8915_OUTPUT2_LEFT_VOLUME:
1355         case WM8915_OUTPUT2_RIGHT_VOLUME:
1356         case WM8915_MICBIAS_1:
1357         case WM8915_MICBIAS_2:
1358         case WM8915_LDO_1:
1359         case WM8915_LDO_2:
1360         case WM8915_ACCESSORY_DETECT_MODE_1:
1361         case WM8915_ACCESSORY_DETECT_MODE_2:
1362         case WM8915_HEADPHONE_DETECT_1:
1363         case WM8915_HEADPHONE_DETECT_2:
1364         case WM8915_MIC_DETECT_1:
1365         case WM8915_MIC_DETECT_2:
1366         case WM8915_MIC_DETECT_3:
1367         case WM8915_CHARGE_PUMP_1:
1368         case WM8915_CHARGE_PUMP_2:
1369         case WM8915_DC_SERVO_1:
1370         case WM8915_DC_SERVO_2:
1371         case WM8915_DC_SERVO_3:
1372         case WM8915_DC_SERVO_5:
1373         case WM8915_DC_SERVO_6:
1374         case WM8915_DC_SERVO_7:
1375         case WM8915_DC_SERVO_READBACK_0:
1376         case WM8915_ANALOGUE_HP_1:
1377         case WM8915_ANALOGUE_HP_2:
1378         case WM8915_CHIP_REVISION:
1379         case WM8915_CONTROL_INTERFACE_1:
1380         case WM8915_WRITE_SEQUENCER_CTRL_1:
1381         case WM8915_WRITE_SEQUENCER_CTRL_2:
1382         case WM8915_AIF_CLOCKING_1:
1383         case WM8915_AIF_CLOCKING_2:
1384         case WM8915_CLOCKING_1:
1385         case WM8915_CLOCKING_2:
1386         case WM8915_AIF_RATE:
1387         case WM8915_FLL_CONTROL_1:
1388         case WM8915_FLL_CONTROL_2:
1389         case WM8915_FLL_CONTROL_3:
1390         case WM8915_FLL_CONTROL_4:
1391         case WM8915_FLL_CONTROL_5:
1392         case WM8915_FLL_CONTROL_6:
1393         case WM8915_FLL_EFS_1:
1394         case WM8915_FLL_EFS_2:
1395         case WM8915_AIF1_CONTROL:
1396         case WM8915_AIF1_BCLK:
1397         case WM8915_AIF1_TX_LRCLK_1:
1398         case WM8915_AIF1_TX_LRCLK_2:
1399         case WM8915_AIF1_RX_LRCLK_1:
1400         case WM8915_AIF1_RX_LRCLK_2:
1401         case WM8915_AIF1TX_DATA_CONFIGURATION_1:
1402         case WM8915_AIF1TX_DATA_CONFIGURATION_2:
1403         case WM8915_AIF1RX_DATA_CONFIGURATION:
1404         case WM8915_AIF1TX_CHANNEL_0_CONFIGURATION:
1405         case WM8915_AIF1TX_CHANNEL_1_CONFIGURATION:
1406         case WM8915_AIF1TX_CHANNEL_2_CONFIGURATION:
1407         case WM8915_AIF1TX_CHANNEL_3_CONFIGURATION:
1408         case WM8915_AIF1TX_CHANNEL_4_CONFIGURATION:
1409         case WM8915_AIF1TX_CHANNEL_5_CONFIGURATION:
1410         case WM8915_AIF1RX_CHANNEL_0_CONFIGURATION:
1411         case WM8915_AIF1RX_CHANNEL_1_CONFIGURATION:
1412         case WM8915_AIF1RX_CHANNEL_2_CONFIGURATION:
1413         case WM8915_AIF1RX_CHANNEL_3_CONFIGURATION:
1414         case WM8915_AIF1RX_CHANNEL_4_CONFIGURATION:
1415         case WM8915_AIF1RX_CHANNEL_5_CONFIGURATION:
1416         case WM8915_AIF1RX_MONO_CONFIGURATION:
1417         case WM8915_AIF1TX_TEST:
1418         case WM8915_AIF2_CONTROL:
1419         case WM8915_AIF2_BCLK:
1420         case WM8915_AIF2_TX_LRCLK_1:
1421         case WM8915_AIF2_TX_LRCLK_2:
1422         case WM8915_AIF2_RX_LRCLK_1:
1423         case WM8915_AIF2_RX_LRCLK_2:
1424         case WM8915_AIF2TX_DATA_CONFIGURATION_1:
1425         case WM8915_AIF2TX_DATA_CONFIGURATION_2:
1426         case WM8915_AIF2RX_DATA_CONFIGURATION:
1427         case WM8915_AIF2TX_CHANNEL_0_CONFIGURATION:
1428         case WM8915_AIF2TX_CHANNEL_1_CONFIGURATION:
1429         case WM8915_AIF2RX_CHANNEL_0_CONFIGURATION:
1430         case WM8915_AIF2RX_CHANNEL_1_CONFIGURATION:
1431         case WM8915_AIF2RX_MONO_CONFIGURATION:
1432         case WM8915_AIF2TX_TEST:
1433         case WM8915_DSP1_TX_LEFT_VOLUME:
1434         case WM8915_DSP1_TX_RIGHT_VOLUME:
1435         case WM8915_DSP1_RX_LEFT_VOLUME:
1436         case WM8915_DSP1_RX_RIGHT_VOLUME:
1437         case WM8915_DSP1_TX_FILTERS:
1438         case WM8915_DSP1_RX_FILTERS_1:
1439         case WM8915_DSP1_RX_FILTERS_2:
1440         case WM8915_DSP1_DRC_1:
1441         case WM8915_DSP1_DRC_2:
1442         case WM8915_DSP1_DRC_3:
1443         case WM8915_DSP1_DRC_4:
1444         case WM8915_DSP1_DRC_5:
1445         case WM8915_DSP1_RX_EQ_GAINS_1:
1446         case WM8915_DSP1_RX_EQ_GAINS_2:
1447         case WM8915_DSP1_RX_EQ_BAND_1_A:
1448         case WM8915_DSP1_RX_EQ_BAND_1_B:
1449         case WM8915_DSP1_RX_EQ_BAND_1_PG:
1450         case WM8915_DSP1_RX_EQ_BAND_2_A:
1451         case WM8915_DSP1_RX_EQ_BAND_2_B:
1452         case WM8915_DSP1_RX_EQ_BAND_2_C:
1453         case WM8915_DSP1_RX_EQ_BAND_2_PG:
1454         case WM8915_DSP1_RX_EQ_BAND_3_A:
1455         case WM8915_DSP1_RX_EQ_BAND_3_B:
1456         case WM8915_DSP1_RX_EQ_BAND_3_C:
1457         case WM8915_DSP1_RX_EQ_BAND_3_PG:
1458         case WM8915_DSP1_RX_EQ_BAND_4_A:
1459         case WM8915_DSP1_RX_EQ_BAND_4_B:
1460         case WM8915_DSP1_RX_EQ_BAND_4_C:
1461         case WM8915_DSP1_RX_EQ_BAND_4_PG:
1462         case WM8915_DSP1_RX_EQ_BAND_5_A:
1463         case WM8915_DSP1_RX_EQ_BAND_5_B:
1464         case WM8915_DSP1_RX_EQ_BAND_5_PG:
1465         case WM8915_DSP2_TX_LEFT_VOLUME:
1466         case WM8915_DSP2_TX_RIGHT_VOLUME:
1467         case WM8915_DSP2_RX_LEFT_VOLUME:
1468         case WM8915_DSP2_RX_RIGHT_VOLUME:
1469         case WM8915_DSP2_TX_FILTERS:
1470         case WM8915_DSP2_RX_FILTERS_1:
1471         case WM8915_DSP2_RX_FILTERS_2:
1472         case WM8915_DSP2_DRC_1:
1473         case WM8915_DSP2_DRC_2:
1474         case WM8915_DSP2_DRC_3:
1475         case WM8915_DSP2_DRC_4:
1476         case WM8915_DSP2_DRC_5:
1477         case WM8915_DSP2_RX_EQ_GAINS_1:
1478         case WM8915_DSP2_RX_EQ_GAINS_2:
1479         case WM8915_DSP2_RX_EQ_BAND_1_A:
1480         case WM8915_DSP2_RX_EQ_BAND_1_B:
1481         case WM8915_DSP2_RX_EQ_BAND_1_PG:
1482         case WM8915_DSP2_RX_EQ_BAND_2_A:
1483         case WM8915_DSP2_RX_EQ_BAND_2_B:
1484         case WM8915_DSP2_RX_EQ_BAND_2_C:
1485         case WM8915_DSP2_RX_EQ_BAND_2_PG:
1486         case WM8915_DSP2_RX_EQ_BAND_3_A:
1487         case WM8915_DSP2_RX_EQ_BAND_3_B:
1488         case WM8915_DSP2_RX_EQ_BAND_3_C:
1489         case WM8915_DSP2_RX_EQ_BAND_3_PG:
1490         case WM8915_DSP2_RX_EQ_BAND_4_A:
1491         case WM8915_DSP2_RX_EQ_BAND_4_B:
1492         case WM8915_DSP2_RX_EQ_BAND_4_C:
1493         case WM8915_DSP2_RX_EQ_BAND_4_PG:
1494         case WM8915_DSP2_RX_EQ_BAND_5_A:
1495         case WM8915_DSP2_RX_EQ_BAND_5_B:
1496         case WM8915_DSP2_RX_EQ_BAND_5_PG:
1497         case WM8915_DAC1_MIXER_VOLUMES:
1498         case WM8915_DAC1_LEFT_MIXER_ROUTING:
1499         case WM8915_DAC1_RIGHT_MIXER_ROUTING:
1500         case WM8915_DAC2_MIXER_VOLUMES:
1501         case WM8915_DAC2_LEFT_MIXER_ROUTING:
1502         case WM8915_DAC2_RIGHT_MIXER_ROUTING:
1503         case WM8915_DSP1_TX_LEFT_MIXER_ROUTING:
1504         case WM8915_DSP1_TX_RIGHT_MIXER_ROUTING:
1505         case WM8915_DSP2_TX_LEFT_MIXER_ROUTING:
1506         case WM8915_DSP2_TX_RIGHT_MIXER_ROUTING:
1507         case WM8915_DSP_TX_MIXER_SELECT:
1508         case WM8915_DAC_SOFTMUTE:
1509         case WM8915_OVERSAMPLING:
1510         case WM8915_SIDETONE:
1511         case WM8915_GPIO_1:
1512         case WM8915_GPIO_2:
1513         case WM8915_GPIO_3:
1514         case WM8915_GPIO_4:
1515         case WM8915_GPIO_5:
1516         case WM8915_PULL_CONTROL_1:
1517         case WM8915_PULL_CONTROL_2:
1518         case WM8915_INTERRUPT_STATUS_1:
1519         case WM8915_INTERRUPT_STATUS_2:
1520         case WM8915_INTERRUPT_RAW_STATUS_2:
1521         case WM8915_INTERRUPT_STATUS_1_MASK:
1522         case WM8915_INTERRUPT_STATUS_2_MASK:
1523         case WM8915_INTERRUPT_CONTROL:
1524         case WM8915_LEFT_PDM_SPEAKER:
1525         case WM8915_RIGHT_PDM_SPEAKER:
1526         case WM8915_PDM_SPEAKER_MUTE_SEQUENCE:
1527         case WM8915_PDM_SPEAKER_VOLUME:
1528                 return 1;
1529         default:
1530                 return 0;
1531         }
1532 }
1533
1534 static int wm8915_volatile_register(struct snd_soc_codec *codec,
1535                                     unsigned int reg)
1536 {
1537         switch (reg) {
1538         case WM8915_SOFTWARE_RESET:
1539         case WM8915_CHIP_REVISION:
1540         case WM8915_LDO_1:
1541         case WM8915_LDO_2:
1542         case WM8915_INTERRUPT_STATUS_1:
1543         case WM8915_INTERRUPT_STATUS_2:
1544         case WM8915_INTERRUPT_RAW_STATUS_2:
1545         case WM8915_DC_SERVO_READBACK_0:
1546         case WM8915_DC_SERVO_2:
1547         case WM8915_DC_SERVO_6:
1548         case WM8915_DC_SERVO_7:
1549         case WM8915_FLL_CONTROL_6:
1550         case WM8915_MIC_DETECT_3:
1551         case WM8915_HEADPHONE_DETECT_1:
1552         case WM8915_HEADPHONE_DETECT_2:
1553                 return 1;
1554         default:
1555                 return 0;
1556         }
1557 }
1558
1559 static int wm8915_reset(struct snd_soc_codec *codec)
1560 {
1561         return snd_soc_write(codec, WM8915_SOFTWARE_RESET, 0x8915);
1562 }
1563
1564 static int wm8915_set_bias_level(struct snd_soc_codec *codec,
1565                                  enum snd_soc_bias_level level)
1566 {
1567         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1568         int ret;
1569
1570         switch (level) {
1571         case SND_SOC_BIAS_ON:
1572                 break;
1573
1574         case SND_SOC_BIAS_PREPARE:
1575                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1576                         snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1577                                             WM8915_BG_ENA, WM8915_BG_ENA);
1578                         msleep(2);
1579                 }
1580                 break;
1581
1582         case SND_SOC_BIAS_STANDBY:
1583                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1584                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
1585                                                     wm8915->supplies);
1586                         if (ret != 0) {
1587                                 dev_err(codec->dev,
1588                                         "Failed to enable supplies: %d\n",
1589                                         ret);
1590                                 return ret;
1591                         }
1592
1593                         if (wm8915->pdata.ldo_ena >= 0) {
1594                                 gpio_set_value_cansleep(wm8915->pdata.ldo_ena,
1595                                                         1);
1596                                 msleep(5);
1597                         }
1598
1599                         codec->cache_only = false;
1600                         snd_soc_cache_sync(codec);
1601                 }
1602
1603                 snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1604                                     WM8915_BG_ENA, 0);
1605                 break;
1606
1607         case SND_SOC_BIAS_OFF:
1608                 codec->cache_only = true;
1609                 if (wm8915->pdata.ldo_ena >= 0)
1610                         gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
1611                 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies),
1612                                        wm8915->supplies);
1613                 break;
1614         }
1615
1616         codec->dapm.bias_level = level;
1617
1618         return 0;
1619 }
1620
1621 static int wm8915_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1622 {
1623         struct snd_soc_codec *codec = dai->codec;
1624         int aifctrl = 0;
1625         int bclk = 0;
1626         int lrclk_tx = 0;
1627         int lrclk_rx = 0;
1628         int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1629
1630         switch (dai->id) {
1631         case 0:
1632                 aifctrl_reg = WM8915_AIF1_CONTROL;
1633                 bclk_reg = WM8915_AIF1_BCLK;
1634                 lrclk_tx_reg = WM8915_AIF1_TX_LRCLK_2;
1635                 lrclk_rx_reg = WM8915_AIF1_RX_LRCLK_2;
1636                 break;
1637         case 1:
1638                 aifctrl_reg = WM8915_AIF2_CONTROL;
1639                 bclk_reg = WM8915_AIF2_BCLK;
1640                 lrclk_tx_reg = WM8915_AIF2_TX_LRCLK_2;
1641                 lrclk_rx_reg = WM8915_AIF2_RX_LRCLK_2;
1642                 break;
1643         default:
1644                 BUG();
1645                 return -EINVAL;
1646         }
1647
1648         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1649         case SND_SOC_DAIFMT_NB_NF:
1650                 break;
1651         case SND_SOC_DAIFMT_IB_NF:
1652                 bclk |= WM8915_AIF1_BCLK_INV;
1653                 break;
1654         case SND_SOC_DAIFMT_NB_IF:
1655                 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1656                 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1657                 break;
1658         case SND_SOC_DAIFMT_IB_IF:
1659                 bclk |= WM8915_AIF1_BCLK_INV;
1660                 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1661                 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1662                 break;
1663         }
1664
1665         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1666         case SND_SOC_DAIFMT_CBS_CFS:
1667                 break;
1668         case SND_SOC_DAIFMT_CBS_CFM:
1669                 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1670                 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1671                 break;
1672         case SND_SOC_DAIFMT_CBM_CFS:
1673                 bclk |= WM8915_AIF1_BCLK_MSTR;
1674                 break;
1675         case SND_SOC_DAIFMT_CBM_CFM:
1676                 bclk |= WM8915_AIF1_BCLK_MSTR;
1677                 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1678                 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1679                 break;
1680         default:
1681                 return -EINVAL;
1682         }
1683
1684         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1685         case SND_SOC_DAIFMT_DSP_A:
1686                 break;
1687         case SND_SOC_DAIFMT_DSP_B:
1688                 aifctrl |= 1;
1689                 break;
1690         case SND_SOC_DAIFMT_I2S:
1691                 aifctrl |= 2;
1692                 break;
1693         case SND_SOC_DAIFMT_LEFT_J:
1694                 aifctrl |= 3;
1695                 break;
1696         default:
1697                 return -EINVAL;
1698         }
1699
1700         snd_soc_update_bits(codec, aifctrl_reg, WM8915_AIF1_FMT_MASK, aifctrl);
1701         snd_soc_update_bits(codec, bclk_reg,
1702                             WM8915_AIF1_BCLK_INV | WM8915_AIF1_BCLK_MSTR,
1703                             bclk);
1704         snd_soc_update_bits(codec, lrclk_tx_reg,
1705                             WM8915_AIF1TX_LRCLK_INV |
1706                             WM8915_AIF1TX_LRCLK_MSTR,
1707                             lrclk_tx);
1708         snd_soc_update_bits(codec, lrclk_rx_reg,
1709                             WM8915_AIF1RX_LRCLK_INV |
1710                             WM8915_AIF1RX_LRCLK_MSTR,
1711                             lrclk_rx);
1712
1713         return 0;
1714 }
1715
1716 static const int bclk_divs[] = {
1717         1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1718 };
1719
1720 static const int dsp_divs[] = {
1721         48000, 32000, 16000, 8000
1722 };
1723
1724 static int wm8915_hw_params(struct snd_pcm_substream *substream,
1725                             struct snd_pcm_hw_params *params,
1726                             struct snd_soc_dai *dai)
1727 {
1728         struct snd_soc_codec *codec = dai->codec;
1729         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1730         int bits, i, bclk_rate, best, cur_val;
1731         int aifdata = 0;
1732         int bclk = 0;
1733         int lrclk = 0;
1734         int dsp = 0;
1735         int aifdata_reg, bclk_reg, lrclk_reg, dsp_shift;
1736
1737         if (!wm8915->sysclk) {
1738                 dev_err(codec->dev, "SYSCLK not configured\n");
1739                 return -EINVAL;
1740         }
1741
1742         switch (dai->id) {
1743         case 0:
1744                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1745                     (snd_soc_read(codec, WM8915_GPIO_1)) & WM8915_GP1_FN_MASK) {
1746                         aifdata_reg = WM8915_AIF1RX_DATA_CONFIGURATION;
1747                         lrclk_reg = WM8915_AIF1_RX_LRCLK_1;
1748                 } else {
1749                         aifdata_reg = WM8915_AIF1TX_DATA_CONFIGURATION_1;
1750                         lrclk_reg = WM8915_AIF1_TX_LRCLK_1;
1751                 }
1752                 bclk_reg = WM8915_AIF1_BCLK;
1753                 dsp_shift = 0;
1754                 break;
1755         case 1:
1756                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1757                     (snd_soc_read(codec, WM8915_GPIO_2)) & WM8915_GP2_FN_MASK) {
1758                         aifdata_reg = WM8915_AIF2RX_DATA_CONFIGURATION;
1759                         lrclk_reg = WM8915_AIF2_RX_LRCLK_1;
1760                 } else {
1761                         aifdata_reg = WM8915_AIF2TX_DATA_CONFIGURATION_1;
1762                         lrclk_reg = WM8915_AIF2_TX_LRCLK_1;
1763                 }
1764                 bclk_reg = WM8915_AIF2_BCLK;
1765                 dsp_shift = WM8915_DSP2_DIV_SHIFT;
1766                 break;
1767         default:
1768                 BUG();
1769                 return -EINVAL;
1770         }
1771
1772         bclk_rate = snd_soc_params_to_bclk(params);
1773         if (bclk_rate < 0) {
1774                 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1775                 return bclk_rate;
1776         }
1777
1778         /* Needs looking at for TDM */
1779         bits = snd_pcm_format_width(params_format(params));
1780         if (bits < 0)
1781                 return bits;
1782         aifdata |= (bits << WM8915_AIF1TX_WL_SHIFT) | bits;
1783
1784         for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1785                 if (dsp_divs[i] == params_rate(params))
1786                         break;
1787         }
1788         if (i == ARRAY_SIZE(dsp_divs)) {
1789                 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1790                         params_rate(params));
1791                 return -EINVAL;
1792         }
1793         dsp |= i << dsp_shift;
1794
1795         /* Pick a divisor for BCLK as close as we can get to ideal */
1796         best = 0;
1797         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1798                 cur_val = (wm8915->sysclk / bclk_divs[i]) - bclk_rate;
1799                 if (cur_val < 0) /* BCLK table is sorted */
1800                         break;
1801                 best = i;
1802         }
1803         bclk_rate = wm8915->sysclk / bclk_divs[best];
1804         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1805                 bclk_divs[best], bclk_rate);
1806         bclk |= best;
1807
1808         lrclk = bclk_rate / params_rate(params);
1809         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1810                 lrclk, bclk_rate / lrclk);
1811
1812         snd_soc_update_bits(codec, aifdata_reg,
1813                             WM8915_AIF1TX_WL_MASK |
1814                             WM8915_AIF1TX_SLOT_LEN_MASK,
1815                             aifdata);
1816         snd_soc_update_bits(codec, bclk_reg, WM8915_AIF1_BCLK_DIV_MASK, bclk);
1817         snd_soc_update_bits(codec, lrclk_reg, WM8915_AIF1RX_RATE_MASK,
1818                             lrclk);
1819         snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_2,
1820                             WM8915_DSP1_DIV_SHIFT << dsp_shift, dsp);
1821
1822         wm8915->rx_rate[dai->id] = params_rate(params);
1823
1824         return 0;
1825 }
1826
1827 static int wm8915_set_sysclk(struct snd_soc_dai *dai,
1828                 int clk_id, unsigned int freq, int dir)
1829 {
1830         struct snd_soc_codec *codec = dai->codec;
1831         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1832         int lfclk = 0;
1833         int ratediv = 0;
1834         int src;
1835         int old;
1836
1837         /* Disable SYSCLK while we reconfigure */
1838         old = snd_soc_read(codec, WM8915_AIF_CLOCKING_1);
1839         snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1840                             WM8915_SYSCLK_ENA, 0);
1841
1842         switch (clk_id) {
1843         case WM8915_SYSCLK_MCLK1:
1844                 wm8915->sysclk = freq;
1845                 src = 0;
1846                 break;
1847         case WM8915_SYSCLK_MCLK2:
1848                 wm8915->sysclk = freq;
1849                 src = 1;
1850                 break;
1851         case WM8915_SYSCLK_FLL:
1852                 wm8915->sysclk = freq;
1853                 src = 2;
1854                 break;
1855         default:
1856                 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1857                 return -EINVAL;
1858         }
1859
1860         switch (wm8915->sysclk) {
1861         case 6144000:
1862                 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1863                                     WM8915_SYSCLK_RATE, 0);
1864                 break;
1865         case 24576000:
1866                 ratediv = WM8915_SYSCLK_DIV;
1867         case 12288000:
1868                 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1869                                     WM8915_SYSCLK_RATE, WM8915_SYSCLK_RATE);
1870                 break;
1871         case 32000:
1872         case 32768:
1873                 lfclk = WM8915_LFCLK_ENA;
1874                 break;
1875         default:
1876                 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1877                          wm8915->sysclk);
1878                 return -EINVAL;
1879         }
1880
1881         snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1882                             WM8915_SYSCLK_SRC_MASK | WM8915_SYSCLK_DIV_MASK,
1883                             src << WM8915_SYSCLK_SRC_SHIFT | ratediv);
1884         snd_soc_update_bits(codec, WM8915_CLOCKING_1, WM8915_LFCLK_ENA, lfclk);
1885         snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1886                             WM8915_SYSCLK_ENA, old);
1887
1888         return 0;
1889 }
1890
1891 struct _fll_div {
1892         u16 fll_fratio;
1893         u16 fll_outdiv;
1894         u16 fll_refclk_div;
1895         u16 fll_loop_gain;
1896         u16 fll_ref_freq;
1897         u16 n;
1898         u16 theta;
1899         u16 lambda;
1900 };
1901
1902 static struct {
1903         unsigned int min;
1904         unsigned int max;
1905         u16 fll_fratio;
1906         int ratio;
1907 } fll_fratios[] = {
1908         {       0,    64000, 4, 16 },
1909         {   64000,   128000, 3,  8 },
1910         {  128000,   256000, 2,  4 },
1911         {  256000,  1000000, 1,  2 },
1912         { 1000000, 13500000, 0,  1 },
1913 };
1914
1915 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1916                        unsigned int Fout)
1917 {
1918         unsigned int target;
1919         unsigned int div;
1920         unsigned int fratio, gcd_fll;
1921         int i;
1922
1923         /* Fref must be <=13.5MHz */
1924         div = 1;
1925         fll_div->fll_refclk_div = 0;
1926         while ((Fref / div) > 13500000) {
1927                 div *= 2;
1928                 fll_div->fll_refclk_div++;
1929
1930                 if (div > 8) {
1931                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1932                                Fref);
1933                         return -EINVAL;
1934                 }
1935         }
1936
1937         pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1938
1939         /* Apply the division for our remaining calculations */
1940         Fref /= div;
1941
1942         if (Fref >= 3000000)
1943                 fll_div->fll_loop_gain = 5;
1944         else
1945                 fll_div->fll_loop_gain = 0;
1946
1947         if (Fref >= 48000)
1948                 fll_div->fll_ref_freq = 0;
1949         else
1950                 fll_div->fll_ref_freq = 1;
1951
1952         /* Fvco should be 90-100MHz; don't check the upper bound */
1953         div = 2;
1954         while (Fout * div < 90000000) {
1955                 div++;
1956                 if (div > 64) {
1957                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1958                                Fout);
1959                         return -EINVAL;
1960                 }
1961         }
1962         target = Fout * div;
1963         fll_div->fll_outdiv = div - 1;
1964
1965         pr_debug("FLL Fvco=%dHz\n", target);
1966
1967         /* Find an appropraite FLL_FRATIO and factor it out of the target */
1968         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1969                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1970                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1971                         fratio = fll_fratios[i].ratio;
1972                         break;
1973                 }
1974         }
1975         if (i == ARRAY_SIZE(fll_fratios)) {
1976                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1977                 return -EINVAL;
1978         }
1979
1980         fll_div->n = target / (fratio * Fref);
1981
1982         if (target % Fref == 0) {
1983                 fll_div->theta = 0;
1984                 fll_div->lambda = 0;
1985         } else {
1986                 gcd_fll = gcd(target, fratio * Fref);
1987
1988                 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1989                         / gcd_fll;
1990                 fll_div->lambda = (fratio * Fref) / gcd_fll;
1991         }
1992
1993         pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1994                  fll_div->n, fll_div->theta, fll_div->lambda);
1995         pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1996                  fll_div->fll_fratio, fll_div->fll_outdiv,
1997                  fll_div->fll_refclk_div);
1998
1999         return 0;
2000 }
2001
2002 static int wm8915_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2003                           unsigned int Fref, unsigned int Fout)
2004 {
2005         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2006         struct _fll_div fll_div;
2007         unsigned long timeout;
2008         int ret, reg;
2009
2010         /* Any change? */
2011         if (source == wm8915->fll_src && Fref == wm8915->fll_fref &&
2012             Fout == wm8915->fll_fout)
2013                 return 0;
2014
2015         if (Fout == 0) {
2016                 dev_dbg(codec->dev, "FLL disabled\n");
2017
2018                 wm8915->fll_fref = 0;
2019                 wm8915->fll_fout = 0;
2020
2021                 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2022                                     WM8915_FLL_ENA, 0);
2023
2024                 return 0;
2025         }
2026
2027         ret = fll_factors(&fll_div, Fref, Fout);
2028         if (ret != 0)
2029                 return ret;
2030
2031         switch (source) {
2032         case WM8915_FLL_MCLK1:
2033                 reg = 0;
2034                 break;
2035         case WM8915_FLL_MCLK2:
2036                 reg = 1;
2037         case WM8915_FLL_DACLRCLK1:
2038                 reg = 2;
2039                 break;
2040         case WM8915_FLL_BCLK1:
2041                 reg = 3;
2042                 break;
2043         default:
2044                 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2045                 return -EINVAL;
2046         }
2047
2048         reg |= fll_div.fll_refclk_div << WM8915_FLL_REFCLK_DIV_SHIFT;
2049         reg |= fll_div.fll_ref_freq << WM8915_FLL_REF_FREQ_SHIFT;
2050
2051         snd_soc_update_bits(codec, WM8915_FLL_CONTROL_5,
2052                             WM8915_FLL_REFCLK_DIV_MASK | WM8915_FLL_REF_FREQ |
2053                             WM8915_FLL_REFCLK_SRC_MASK, reg);
2054
2055         reg = 0;
2056         if (fll_div.theta || fll_div.lambda)
2057                 reg |= WM8915_FLL_EFS_ENA | (3 << WM8915_FLL_LFSR_SEL_SHIFT);
2058         else
2059                 reg |= 1 << WM8915_FLL_LFSR_SEL_SHIFT;
2060         snd_soc_write(codec, WM8915_FLL_EFS_2, reg);
2061
2062         snd_soc_update_bits(codec, WM8915_FLL_CONTROL_2,
2063                             WM8915_FLL_OUTDIV_MASK |
2064                             WM8915_FLL_FRATIO_MASK,
2065                             (fll_div.fll_outdiv << WM8915_FLL_OUTDIV_SHIFT) |
2066                             (fll_div.fll_fratio));
2067
2068         snd_soc_write(codec, WM8915_FLL_CONTROL_3, fll_div.theta);
2069
2070         snd_soc_update_bits(codec, WM8915_FLL_CONTROL_4,
2071                             WM8915_FLL_N_MASK | WM8915_FLL_LOOP_GAIN_MASK,
2072                             (fll_div.n << WM8915_FLL_N_SHIFT) |
2073                             fll_div.fll_loop_gain);
2074
2075         snd_soc_write(codec, WM8915_FLL_EFS_1, fll_div.lambda);
2076
2077         snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2078                             WM8915_FLL_ENA, WM8915_FLL_ENA);
2079
2080         /* The FLL supports live reconfiguration - kick that in case we were
2081          * already enabled.
2082          */
2083         snd_soc_write(codec, WM8915_FLL_CONTROL_6, WM8915_FLL_SWITCH_CLK);
2084
2085         /* Wait for the FLL to lock, using the interrupt if possible */
2086         if (Fref > 1000000)
2087                 timeout = usecs_to_jiffies(300);
2088         else
2089                 timeout = msecs_to_jiffies(2);
2090
2091         wait_for_completion_timeout(&wm8915->fll_lock, timeout);
2092
2093         dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2094
2095         wm8915->fll_fref = Fref;
2096         wm8915->fll_fout = Fout;
2097         wm8915->fll_src = source;
2098
2099         return 0;
2100 }
2101
2102 #ifdef CONFIG_GPIOLIB
2103 static inline struct wm8915_priv *gpio_to_wm8915(struct gpio_chip *chip)
2104 {
2105         return container_of(chip, struct wm8915_priv, gpio_chip);
2106 }
2107
2108 static void wm8915_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2109 {
2110         struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2111         struct snd_soc_codec *codec = wm8915->codec;
2112
2113         snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2114                             WM8915_GP1_LVL, !!value << WM8915_GP1_LVL_SHIFT);
2115 }
2116
2117 static int wm8915_gpio_direction_out(struct gpio_chip *chip,
2118                                      unsigned offset, int value)
2119 {
2120         struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2121         struct snd_soc_codec *codec = wm8915->codec;
2122         int val;
2123
2124         val = (1 << WM8915_GP1_FN_SHIFT) | (!!value << WM8915_GP1_LVL_SHIFT);
2125
2126         return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2127                                    WM8915_GP1_FN_MASK | WM8915_GP1_DIR |
2128                                    WM8915_GP1_LVL, val);
2129 }
2130
2131 static int wm8915_gpio_get(struct gpio_chip *chip, unsigned offset)
2132 {
2133         struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2134         struct snd_soc_codec *codec = wm8915->codec;
2135         int ret;
2136
2137         ret = snd_soc_read(codec, WM8915_GPIO_1 + offset);
2138         if (ret < 0)
2139                 return ret;
2140
2141         return (ret & WM8915_GP1_LVL) != 0;
2142 }
2143
2144 static int wm8915_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2145 {
2146         struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2147         struct snd_soc_codec *codec = wm8915->codec;
2148
2149         return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2150                                    WM8915_GP1_FN_MASK | WM8915_GP1_DIR,
2151                                    (1 << WM8915_GP1_FN_SHIFT) |
2152                                    (1 << WM8915_GP1_DIR_SHIFT));
2153 }
2154
2155 static struct gpio_chip wm8915_template_chip = {
2156         .label                  = "wm8915",
2157         .owner                  = THIS_MODULE,
2158         .direction_output       = wm8915_gpio_direction_out,
2159         .set                    = wm8915_gpio_set,
2160         .direction_input        = wm8915_gpio_direction_in,
2161         .get                    = wm8915_gpio_get,
2162         .can_sleep              = 1,
2163 };
2164
2165 static void wm8915_init_gpio(struct snd_soc_codec *codec)
2166 {
2167         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2168         int ret;
2169
2170         wm8915->gpio_chip = wm8915_template_chip;
2171         wm8915->gpio_chip.ngpio = 5;
2172         wm8915->gpio_chip.dev = codec->dev;
2173
2174         if (wm8915->pdata.gpio_base)
2175                 wm8915->gpio_chip.base = wm8915->pdata.gpio_base;
2176         else
2177                 wm8915->gpio_chip.base = -1;
2178
2179         ret = gpiochip_add(&wm8915->gpio_chip);
2180         if (ret != 0)
2181                 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2182 }
2183
2184 static void wm8915_free_gpio(struct snd_soc_codec *codec)
2185 {
2186         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2187         int ret;
2188
2189         ret = gpiochip_remove(&wm8915->gpio_chip);
2190         if (ret != 0)
2191                 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2192 }
2193 #else
2194 static void wm8915_init_gpio(struct snd_soc_codec *codec)
2195 {
2196 }
2197
2198 static void wm8915_free_gpio(struct snd_soc_codec *codec)
2199 {
2200 }
2201 #endif
2202
2203 /**
2204  * wm8915_detect - Enable default WM8915 jack detection
2205  *
2206  * The WM8915 has advanced accessory detection support for headsets.
2207  * This function provides a default implementation which integrates
2208  * the majority of this functionality with minimal user configuration.
2209  *
2210  * This will detect headset, headphone and short circuit button and
2211  * will also detect inverted microphone ground connections and update
2212  * the polarity of the connections.
2213  */
2214 int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2215                   wm8915_polarity_fn polarity_cb)
2216 {
2217         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2218
2219         wm8915->jack = jack;
2220         wm8915->detecting = true;
2221         wm8915->polarity_cb = polarity_cb;
2222
2223         if (wm8915->polarity_cb)
2224                 wm8915->polarity_cb(codec, 0);
2225
2226         /* Clear discarge to avoid noise during detection */
2227         snd_soc_update_bits(codec, WM8915_MICBIAS_1,
2228                             WM8915_MICB1_DISCH, 0);
2229         snd_soc_update_bits(codec, WM8915_MICBIAS_2,
2230                             WM8915_MICB2_DISCH, 0);
2231
2232         /* LDO2 powers the microphones, SYSCLK clocks detection */
2233         snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2234         snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2235
2236         /* We start off just enabling microphone detection - even a
2237          * plain headphone will trigger detection.
2238          */
2239         snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2240                             WM8915_MICD_ENA, WM8915_MICD_ENA);
2241
2242         /* Slowest detection rate, gives debounce for initial detection */
2243         snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2244                             WM8915_MICD_RATE_MASK,
2245                             WM8915_MICD_RATE_MASK);
2246
2247         /* Enable interrupts and we're off */
2248         snd_soc_update_bits(codec, WM8915_INTERRUPT_STATUS_2_MASK,
2249                             WM8915_IM_MICD_EINT, 0);
2250
2251         return 0;
2252 }
2253 EXPORT_SYMBOL_GPL(wm8915_detect);
2254
2255 static void wm8915_micd(struct snd_soc_codec *codec)
2256 {
2257         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2258         int val, reg;
2259
2260         val = snd_soc_read(codec, WM8915_MIC_DETECT_3);
2261
2262         dev_dbg(codec->dev, "Microphone event: %x\n", val);
2263
2264         if (!(val & WM8915_MICD_VALID)) {
2265                 dev_warn(codec->dev, "Microphone detection state invalid\n");
2266                 return;
2267         }
2268
2269         /* No accessory, reset everything and report removal */
2270         if (!(val & WM8915_MICD_STS)) {
2271                 dev_dbg(codec->dev, "Jack removal detected\n");
2272                 wm8915->jack_mic = false;
2273                 wm8915->detecting = true;
2274                 snd_soc_jack_report(wm8915->jack, 0,
2275                                     SND_JACK_HEADSET | SND_JACK_BTN_0);
2276                 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2277                                     WM8915_MICD_RATE_MASK,
2278                                     WM8915_MICD_RATE_MASK);
2279                 return;
2280         }
2281
2282         /* If the measurement is very high we've got a microphone but
2283          * do a little debounce to account for mechanical issues.
2284          */
2285         if (val & 0x400) {
2286                 dev_dbg(codec->dev, "Microphone detected\n");
2287                 snd_soc_jack_report(wm8915->jack, SND_JACK_HEADSET,
2288                                     SND_JACK_HEADSET | SND_JACK_BTN_0);
2289                 wm8915->jack_mic = true;
2290                 wm8915->detecting = false;
2291
2292                 /* Increase poll rate to give better responsiveness
2293                  * for buttons */
2294                 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2295                                     WM8915_MICD_RATE_MASK,
2296                                     5 << WM8915_MICD_RATE_SHIFT);
2297         }
2298
2299         /* If we detected a lower impedence during initial startup
2300          * then we probably have the wrong polarity, flip it.  Don't
2301          * do this for the lowest impedences to speed up detection of
2302          * plain headphones.
2303          */
2304         if (wm8915->detecting && (val & 0x3f0)) {
2305                 reg = snd_soc_read(codec, WM8915_ACCESSORY_DETECT_MODE_2);
2306                 reg ^= WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2307                         WM8915_MICD_BIAS_SRC;
2308                 snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2309                                     WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2310                                     WM8915_MICD_BIAS_SRC, reg);
2311
2312                 if (wm8915->polarity_cb)
2313                         wm8915->polarity_cb(codec,
2314                                             (reg & WM8915_MICD_SRC) != 0);
2315
2316                 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2317                         (reg & WM8915_MICD_SRC) != 0);
2318
2319                 return;
2320         }
2321
2322         /* Don't distinguish between buttons, just report any low
2323          * impedence as BTN_0.
2324          */
2325         if (val & 0x3fc) {
2326                 if (wm8915->jack_mic) {
2327                         dev_dbg(codec->dev, "Mic button detected\n");
2328                         snd_soc_jack_report(wm8915->jack,
2329                                             SND_JACK_HEADSET | SND_JACK_BTN_0,
2330                                             SND_JACK_HEADSET | SND_JACK_BTN_0);
2331                 } else {
2332                         dev_dbg(codec->dev, "Headphone detected\n");
2333                         snd_soc_jack_report(wm8915->jack,
2334                                             SND_JACK_HEADPHONE,
2335                                             SND_JACK_HEADSET |
2336                                             SND_JACK_BTN_0);
2337
2338                         /* Increase the detection rate a bit for
2339                          * responsiveness.
2340                          */
2341                         snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2342                                             WM8915_MICD_RATE_MASK,
2343                                             7 << WM8915_MICD_RATE_SHIFT);
2344
2345                         wm8915->detecting = false;
2346                 }
2347         }
2348 }
2349
2350 static irqreturn_t wm8915_irq(int irq, void *data)
2351 {
2352         struct snd_soc_codec *codec = data;
2353         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2354         int irq_val;
2355
2356         irq_val = snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2);
2357         if (irq_val < 0) {
2358                 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2359                         irq_val);
2360                 return IRQ_NONE;
2361         }
2362         irq_val &= ~snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2_MASK);
2363
2364         if (irq_val & (WM8915_DCS_DONE_01_EINT | WM8915_DCS_DONE_23_EINT)) {
2365                 dev_dbg(codec->dev, "DC servo IRQ\n");
2366                 complete(&wm8915->dcs_done);
2367         }
2368
2369         if (irq_val & WM8915_FIFOS_ERR_EINT)
2370                 dev_err(codec->dev, "Digital core FIFO error\n");
2371
2372         if (irq_val & WM8915_FLL_LOCK_EINT) {
2373                 dev_dbg(codec->dev, "FLL locked\n");
2374                 complete(&wm8915->fll_lock);
2375         }
2376
2377         if (irq_val & WM8915_MICD_EINT)
2378                 wm8915_micd(codec);
2379
2380         if (irq_val) {
2381                 snd_soc_write(codec, WM8915_INTERRUPT_STATUS_2, irq_val);
2382
2383                 return IRQ_HANDLED;
2384         } else {
2385                 return IRQ_NONE;
2386         }
2387 }
2388
2389 static irqreturn_t wm8915_edge_irq(int irq, void *data)
2390 {
2391         irqreturn_t ret = IRQ_NONE;
2392         irqreturn_t val;
2393
2394         do {
2395                 val = wm8915_irq(irq, data);
2396                 if (val != IRQ_NONE)
2397                         ret = val;
2398         } while (val != IRQ_NONE);
2399
2400         return ret;
2401 }
2402
2403 static void wm8915_retune_mobile_pdata(struct snd_soc_codec *codec)
2404 {
2405         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2406         struct wm8915_pdata *pdata = &wm8915->pdata;
2407
2408         struct snd_kcontrol_new controls[] = {
2409                 SOC_ENUM_EXT("DSP1 EQ Mode",
2410                              wm8915->retune_mobile_enum,
2411                              wm8915_get_retune_mobile_enum,
2412                              wm8915_put_retune_mobile_enum),
2413                 SOC_ENUM_EXT("DSP2 EQ Mode",
2414                              wm8915->retune_mobile_enum,
2415                              wm8915_get_retune_mobile_enum,
2416                              wm8915_put_retune_mobile_enum),
2417         };
2418         int ret, i, j;
2419         const char **t;
2420
2421         /* We need an array of texts for the enum API but the number
2422          * of texts is likely to be less than the number of
2423          * configurations due to the sample rate dependency of the
2424          * configurations. */
2425         wm8915->num_retune_mobile_texts = 0;
2426         wm8915->retune_mobile_texts = NULL;
2427         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2428                 for (j = 0; j < wm8915->num_retune_mobile_texts; j++) {
2429                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2430                                    wm8915->retune_mobile_texts[j]) == 0)
2431                                 break;
2432                 }
2433
2434                 if (j != wm8915->num_retune_mobile_texts)
2435                         continue;
2436
2437                 /* Expand the array... */
2438                 t = krealloc(wm8915->retune_mobile_texts,
2439                              sizeof(char *) *
2440                              (wm8915->num_retune_mobile_texts + 1),
2441                              GFP_KERNEL);
2442                 if (t == NULL)
2443                         continue;
2444
2445                 /* ...store the new entry... */
2446                 t[wm8915->num_retune_mobile_texts] =
2447                         pdata->retune_mobile_cfgs[i].name;
2448
2449                 /* ...and remember the new version. */
2450                 wm8915->num_retune_mobile_texts++;
2451                 wm8915->retune_mobile_texts = t;
2452         }
2453
2454         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2455                 wm8915->num_retune_mobile_texts);
2456
2457         wm8915->retune_mobile_enum.max = wm8915->num_retune_mobile_texts;
2458         wm8915->retune_mobile_enum.texts = wm8915->retune_mobile_texts;
2459
2460         ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2461         if (ret != 0)
2462                 dev_err(codec->dev,
2463                         "Failed to add ReTune Mobile controls: %d\n", ret);
2464 }
2465
2466 static int wm8915_probe(struct snd_soc_codec *codec)
2467 {
2468         int ret;
2469         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2470         struct i2c_client *i2c = to_i2c_client(codec->dev);
2471         struct snd_soc_dapm_context *dapm = &codec->dapm;
2472         int i, irq_flags;
2473
2474         wm8915->codec = codec;
2475
2476         init_completion(&wm8915->dcs_done);
2477         init_completion(&wm8915->fll_lock);
2478
2479         dapm->idle_bias_off = true;
2480         dapm->bias_level = SND_SOC_BIAS_OFF;
2481
2482         ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2483         if (ret != 0) {
2484                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2485                 goto err;
2486         }
2487
2488         for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2489                 wm8915->supplies[i].supply = wm8915_supply_names[i];
2490
2491         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8915->supplies),
2492                                  wm8915->supplies);
2493         if (ret != 0) {
2494                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2495                 goto err;
2496         }
2497
2498         wm8915->disable_nb[0].notifier_call = wm8915_regulator_event_0;
2499         wm8915->disable_nb[1].notifier_call = wm8915_regulator_event_1;
2500         wm8915->disable_nb[2].notifier_call = wm8915_regulator_event_2;
2501         wm8915->disable_nb[3].notifier_call = wm8915_regulator_event_3;
2502
2503         /* This should really be moved into the regulator core */
2504         for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) {
2505                 ret = regulator_register_notifier(wm8915->supplies[i].consumer,
2506                                                   &wm8915->disable_nb[i]);
2507                 if (ret != 0) {
2508                         dev_err(codec->dev,
2509                                 "Failed to register regulator notifier: %d\n",
2510                                 ret);
2511                 }
2512         }
2513
2514         ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
2515                                     wm8915->supplies);
2516         if (ret != 0) {
2517                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2518                 goto err_get;
2519         }
2520
2521         if (wm8915->pdata.ldo_ena >= 0) {
2522                 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 1);
2523                 msleep(5);
2524         }
2525
2526         ret = snd_soc_read(codec, WM8915_SOFTWARE_RESET);
2527         if (ret < 0) {
2528                 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2529                 goto err_enable;
2530         }
2531         if (ret != 0x8915) {
2532                 dev_err(codec->dev, "Device is not a WM8915, ID %x\n", ret);
2533                 ret = -EINVAL;
2534                 goto err_enable;
2535         }
2536
2537         ret = snd_soc_read(codec, WM8915_CHIP_REVISION);
2538         if (ret < 0) {
2539                 dev_err(codec->dev, "Failed to read device revision: %d\n",
2540                         ret);
2541                 goto err_enable;
2542         }
2543
2544         dev_info(codec->dev, "revision %c\n",
2545                  (ret & WM8915_CHIP_REV_MASK) + 'A');
2546
2547         if (wm8915->pdata.ldo_ena >= 0) {
2548                 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2549         } else {
2550                 ret = wm8915_reset(codec);
2551                 if (ret < 0) {
2552                         dev_err(codec->dev, "Failed to issue reset\n");
2553                         goto err_enable;
2554                 }
2555         }
2556
2557         codec->cache_only = true;
2558
2559         /* Apply platform data settings */
2560         snd_soc_update_bits(codec, WM8915_LINE_INPUT_CONTROL,
2561                             WM8915_INL_MODE_MASK | WM8915_INR_MODE_MASK,
2562                             wm8915->pdata.inl_mode << WM8915_INL_MODE_SHIFT |
2563                             wm8915->pdata.inr_mode);
2564
2565         for (i = 0; i < ARRAY_SIZE(wm8915->pdata.gpio_default); i++) {
2566                 if (!wm8915->pdata.gpio_default[i])
2567                         continue;
2568
2569                 snd_soc_write(codec, WM8915_GPIO_1 + i,
2570                               wm8915->pdata.gpio_default[i] & 0xffff);
2571         }
2572
2573         if (wm8915->pdata.spkmute_seq)
2574                 snd_soc_update_bits(codec, WM8915_PDM_SPEAKER_MUTE_SEQUENCE,
2575                                     WM8915_SPK_MUTE_ENDIAN |
2576                                     WM8915_SPK_MUTE_SEQ1_MASK,
2577                                     wm8915->pdata.spkmute_seq);
2578
2579         snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2580                             WM8915_MICD_BIAS_SRC | WM8915_HPOUT1FB_SRC |
2581                             WM8915_MICD_SRC, wm8915->pdata.micdet_def);
2582
2583         /* Latch volume update bits */
2584         snd_soc_update_bits(codec, WM8915_LEFT_LINE_INPUT_VOLUME,
2585                             WM8915_IN1_VU, WM8915_IN1_VU);
2586         snd_soc_update_bits(codec, WM8915_RIGHT_LINE_INPUT_VOLUME,
2587                             WM8915_IN1_VU, WM8915_IN1_VU);
2588
2589         snd_soc_update_bits(codec, WM8915_DAC1_LEFT_VOLUME,
2590                             WM8915_DAC1_VU, WM8915_DAC1_VU);
2591         snd_soc_update_bits(codec, WM8915_DAC1_RIGHT_VOLUME,
2592                             WM8915_DAC1_VU, WM8915_DAC1_VU);
2593         snd_soc_update_bits(codec, WM8915_DAC2_LEFT_VOLUME,
2594                             WM8915_DAC2_VU, WM8915_DAC2_VU);
2595         snd_soc_update_bits(codec, WM8915_DAC2_RIGHT_VOLUME,
2596                             WM8915_DAC2_VU, WM8915_DAC2_VU);
2597
2598         snd_soc_update_bits(codec, WM8915_OUTPUT1_LEFT_VOLUME,
2599                             WM8915_DAC1_VU, WM8915_DAC1_VU);
2600         snd_soc_update_bits(codec, WM8915_OUTPUT1_RIGHT_VOLUME,
2601                             WM8915_DAC1_VU, WM8915_DAC1_VU);
2602         snd_soc_update_bits(codec, WM8915_OUTPUT2_LEFT_VOLUME,
2603                             WM8915_DAC2_VU, WM8915_DAC2_VU);
2604         snd_soc_update_bits(codec, WM8915_OUTPUT2_RIGHT_VOLUME,
2605                             WM8915_DAC2_VU, WM8915_DAC2_VU);
2606
2607         snd_soc_update_bits(codec, WM8915_DSP1_TX_LEFT_VOLUME,
2608                             WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2609         snd_soc_update_bits(codec, WM8915_DSP1_TX_RIGHT_VOLUME,
2610                             WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2611         snd_soc_update_bits(codec, WM8915_DSP2_TX_LEFT_VOLUME,
2612                             WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2613         snd_soc_update_bits(codec, WM8915_DSP2_TX_RIGHT_VOLUME,
2614                             WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2615
2616         snd_soc_update_bits(codec, WM8915_DSP1_RX_LEFT_VOLUME,
2617                             WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2618         snd_soc_update_bits(codec, WM8915_DSP1_RX_RIGHT_VOLUME,
2619                             WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2620         snd_soc_update_bits(codec, WM8915_DSP2_RX_LEFT_VOLUME,
2621                             WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2622         snd_soc_update_bits(codec, WM8915_DSP2_RX_RIGHT_VOLUME,
2623                             WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2624
2625         /* No support currently for the underclocked TDM modes and
2626          * pick a default TDM layout with each channel pair working with
2627          * slots 0 and 1. */
2628         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_0_CONFIGURATION,
2629                             WM8915_AIF1RX_CHAN0_SLOTS_MASK |
2630                             WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2631                             1 << WM8915_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2632         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_1_CONFIGURATION,
2633                             WM8915_AIF1RX_CHAN1_SLOTS_MASK |
2634                             WM8915_AIF1RX_CHAN1_START_SLOT_MASK,
2635                             1 << WM8915_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2636         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_2_CONFIGURATION,
2637                             WM8915_AIF1RX_CHAN2_SLOTS_MASK |
2638                             WM8915_AIF1RX_CHAN2_START_SLOT_MASK,
2639                             1 << WM8915_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2640         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_3_CONFIGURATION,
2641                             WM8915_AIF1RX_CHAN3_SLOTS_MASK |
2642                             WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2643                             1 << WM8915_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2644         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_4_CONFIGURATION,
2645                             WM8915_AIF1RX_CHAN4_SLOTS_MASK |
2646                             WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2647                             1 << WM8915_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2648         snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_5_CONFIGURATION,
2649                             WM8915_AIF1RX_CHAN5_SLOTS_MASK |
2650                             WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2651                             1 << WM8915_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2652
2653         snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_0_CONFIGURATION,
2654                             WM8915_AIF2RX_CHAN0_SLOTS_MASK |
2655                             WM8915_AIF2RX_CHAN0_START_SLOT_MASK,
2656                             1 << WM8915_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2657         snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_1_CONFIGURATION,
2658                             WM8915_AIF2RX_CHAN1_SLOTS_MASK |
2659                             WM8915_AIF2RX_CHAN1_START_SLOT_MASK,
2660                             1 << WM8915_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2661
2662         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_0_CONFIGURATION,
2663                             WM8915_AIF1TX_CHAN0_SLOTS_MASK |
2664                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2665                             1 << WM8915_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2666         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2667                             WM8915_AIF1TX_CHAN1_SLOTS_MASK |
2668                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2669                             1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2670         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_2_CONFIGURATION,
2671                             WM8915_AIF1TX_CHAN2_SLOTS_MASK |
2672                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2673                             1 << WM8915_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2674         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_3_CONFIGURATION,
2675                             WM8915_AIF1TX_CHAN3_SLOTS_MASK |
2676                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2677                             1 << WM8915_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2678         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_4_CONFIGURATION,
2679                             WM8915_AIF1TX_CHAN4_SLOTS_MASK |
2680                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2681                             1 << WM8915_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2682         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_5_CONFIGURATION,
2683                             WM8915_AIF1TX_CHAN5_SLOTS_MASK |
2684                             WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2685                             1 << WM8915_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2686
2687         snd_soc_update_bits(codec, WM8915_AIF2TX_CHANNEL_0_CONFIGURATION,
2688                             WM8915_AIF2TX_CHAN0_SLOTS_MASK |
2689                             WM8915_AIF2TX_CHAN0_START_SLOT_MASK,
2690                             1 << WM8915_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2691         snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2692                             WM8915_AIF2TX_CHAN1_SLOTS_MASK |
2693                             WM8915_AIF2TX_CHAN1_START_SLOT_MASK,
2694                             1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2695
2696         if (wm8915->pdata.num_retune_mobile_cfgs)
2697                 wm8915_retune_mobile_pdata(codec);
2698         else
2699                 snd_soc_add_controls(codec, wm8915_eq_controls,
2700                                      ARRAY_SIZE(wm8915_eq_controls));
2701
2702         /* If the TX LRCLK pins are not in LRCLK mode configure the
2703          * AIFs to source their clocks from the RX LRCLKs.
2704          */
2705         if ((snd_soc_read(codec, WM8915_GPIO_1)))
2706                 snd_soc_update_bits(codec, WM8915_AIF1_TX_LRCLK_2,
2707                                     WM8915_AIF1TX_LRCLK_MODE,
2708                                     WM8915_AIF1TX_LRCLK_MODE);
2709
2710         if ((snd_soc_read(codec, WM8915_GPIO_2)))
2711                 snd_soc_update_bits(codec, WM8915_AIF2_TX_LRCLK_2,
2712                                     WM8915_AIF2TX_LRCLK_MODE,
2713                                     WM8915_AIF2TX_LRCLK_MODE);
2714
2715         regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2716
2717         wm8915_init_gpio(codec);
2718
2719         if (i2c->irq) {
2720                 if (wm8915->pdata.irq_flags)
2721                         irq_flags = wm8915->pdata.irq_flags;
2722                 else
2723                         irq_flags = IRQF_TRIGGER_LOW;
2724
2725                 irq_flags |= IRQF_ONESHOT;
2726
2727                 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2728                         ret = request_threaded_irq(i2c->irq, NULL,
2729                                                    wm8915_edge_irq,
2730                                                    irq_flags, "wm8915", codec);
2731                 else
2732                         ret = request_threaded_irq(i2c->irq, NULL, wm8915_irq,
2733                                                    irq_flags, "wm8915", codec);
2734
2735                 if (ret == 0) {
2736                         /* Unmask the interrupt */
2737                         snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2738                                             WM8915_IM_IRQ, 0);
2739
2740                         /* Enable error reporting and DC servo status */
2741                         snd_soc_update_bits(codec,
2742                                             WM8915_INTERRUPT_STATUS_2_MASK,
2743                                             WM8915_IM_DCS_DONE_23_EINT |
2744                                             WM8915_IM_DCS_DONE_01_EINT |
2745                                             WM8915_IM_FLL_LOCK_EINT |
2746                                             WM8915_IM_FIFOS_ERR_EINT,
2747                                             0);
2748                 } else {
2749                         dev_err(codec->dev, "Failed to request IRQ: %d\n",
2750                                 ret);
2751                 }
2752         }
2753
2754         return 0;
2755
2756 err_enable:
2757         if (wm8915->pdata.ldo_ena >= 0)
2758                 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2759
2760         regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2761 err_get:
2762         regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2763 err:
2764         return ret;
2765 }
2766
2767 static int wm8915_remove(struct snd_soc_codec *codec)
2768 {
2769         struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2770         struct i2c_client *i2c = to_i2c_client(codec->dev);
2771         int i;
2772
2773         snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2774                             WM8915_IM_IRQ, WM8915_IM_IRQ);
2775
2776         if (i2c->irq)
2777                 free_irq(i2c->irq, codec);
2778
2779         wm8915_free_gpio(codec);
2780
2781         for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2782                 regulator_unregister_notifier(wm8915->supplies[i].consumer,
2783                                               &wm8915->disable_nb[i]);
2784         regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2785
2786         return 0;
2787 }
2788
2789 static struct snd_soc_codec_driver soc_codec_dev_wm8915 = {
2790         .probe =        wm8915_probe,
2791         .remove =       wm8915_remove,
2792         .set_bias_level = wm8915_set_bias_level,
2793         .seq_notifier = wm8915_seq_notifier,
2794         .reg_cache_size = WM8915_MAX_REGISTER + 1,
2795         .reg_word_size = sizeof(u16),
2796         .reg_cache_default = wm8915_reg,
2797         .volatile_register = wm8915_volatile_register,
2798         .readable_register = wm8915_readable_register,
2799         .compress_type = SND_SOC_RBTREE_COMPRESSION,
2800         .controls = wm8915_snd_controls,
2801         .num_controls = ARRAY_SIZE(wm8915_snd_controls),
2802         .dapm_widgets = wm8915_dapm_widgets,
2803         .num_dapm_widgets = ARRAY_SIZE(wm8915_dapm_widgets),
2804         .dapm_routes = wm8915_dapm_routes,
2805         .num_dapm_routes = ARRAY_SIZE(wm8915_dapm_routes),
2806         .set_pll = wm8915_set_fll,
2807 };
2808
2809 #define WM8915_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2810                       SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
2811 #define WM8915_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2812                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2813                         SNDRV_PCM_FMTBIT_S32_LE)
2814
2815 static struct snd_soc_dai_ops wm8915_dai_ops = {
2816         .set_fmt = wm8915_set_fmt,
2817         .hw_params = wm8915_hw_params,
2818         .set_sysclk = wm8915_set_sysclk,
2819 };
2820
2821 static struct snd_soc_dai_driver wm8915_dai[] = {
2822         {
2823                 .name = "wm8915-aif1",
2824                 .playback = {
2825                         .stream_name = "AIF1 Playback",
2826                         .channels_min = 1,
2827                         .channels_max = 6,
2828                         .rates = WM8915_RATES,
2829                         .formats = WM8915_FORMATS,
2830                 },
2831                 .capture = {
2832                          .stream_name = "AIF1 Capture",
2833                          .channels_min = 1,
2834                          .channels_max = 6,
2835                          .rates = WM8915_RATES,
2836                          .formats = WM8915_FORMATS,
2837                  },
2838                 .ops = &wm8915_dai_ops,
2839         },
2840         {
2841                 .name = "wm8915-aif2",
2842                 .playback = {
2843                         .stream_name = "AIF2 Playback",
2844                         .channels_min = 1,
2845                         .channels_max = 2,
2846                         .rates = WM8915_RATES,
2847                         .formats = WM8915_FORMATS,
2848                 },
2849                 .capture = {
2850                          .stream_name = "AIF2 Capture",
2851                          .channels_min = 1,
2852                          .channels_max = 2,
2853                          .rates = WM8915_RATES,
2854                          .formats = WM8915_FORMATS,
2855                  },
2856                 .ops = &wm8915_dai_ops,
2857         },
2858 };
2859
2860 static __devinit int wm8915_i2c_probe(struct i2c_client *i2c,
2861                                       const struct i2c_device_id *id)
2862 {
2863         struct wm8915_priv *wm8915;
2864         int ret;
2865
2866         wm8915 = kzalloc(sizeof(struct wm8915_priv), GFP_KERNEL);
2867         if (wm8915 == NULL)
2868                 return -ENOMEM;
2869
2870         i2c_set_clientdata(i2c, wm8915);
2871
2872         if (dev_get_platdata(&i2c->dev))
2873                 memcpy(&wm8915->pdata, dev_get_platdata(&i2c->dev),
2874                        sizeof(wm8915->pdata));
2875
2876         if (wm8915->pdata.ldo_ena > 0) {
2877                 ret = gpio_request_one(wm8915->pdata.ldo_ena,
2878                                        GPIOF_OUT_INIT_LOW, "WM8915 ENA");
2879                 if (ret < 0) {
2880                         dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2881                                 wm8915->pdata.ldo_ena, ret);
2882                         goto err;
2883                 }
2884         }
2885
2886         ret = snd_soc_register_codec(&i2c->dev,
2887                                      &soc_codec_dev_wm8915, wm8915_dai,
2888                                      ARRAY_SIZE(wm8915_dai));
2889         if (ret < 0)
2890                 goto err_gpio;
2891
2892         return ret;
2893
2894 err_gpio:
2895         if (wm8915->pdata.ldo_ena > 0)
2896                 gpio_free(wm8915->pdata.ldo_ena);
2897 err:
2898         kfree(wm8915);
2899
2900         return ret;
2901 }
2902
2903 static __devexit int wm8915_i2c_remove(struct i2c_client *client)
2904 {
2905         struct wm8915_priv *wm8915 = i2c_get_clientdata(client);
2906
2907         snd_soc_unregister_codec(&client->dev);
2908         if (wm8915->pdata.ldo_ena > 0)
2909                 gpio_free(wm8915->pdata.ldo_ena);
2910         kfree(i2c_get_clientdata(client));
2911         return 0;
2912 }
2913
2914 static const struct i2c_device_id wm8915_i2c_id[] = {
2915         { "wm8915", 0 },
2916         { }
2917 };
2918 MODULE_DEVICE_TABLE(i2c, wm8915_i2c_id);
2919
2920 static struct i2c_driver wm8915_i2c_driver = {
2921         .driver = {
2922                 .name = "wm8915",
2923                 .owner = THIS_MODULE,
2924         },
2925         .probe =    wm8915_i2c_probe,
2926         .remove =   __devexit_p(wm8915_i2c_remove),
2927         .id_table = wm8915_i2c_id,
2928 };
2929
2930 static int __init wm8915_modinit(void)
2931 {
2932         int ret;
2933
2934         ret = i2c_add_driver(&wm8915_i2c_driver);
2935         if (ret != 0) {
2936                 printk(KERN_ERR "Failed to register WM8915 I2C driver: %d\n",
2937                        ret);
2938         }
2939
2940         return ret;
2941 }
2942 module_init(wm8915_modinit);
2943
2944 static void __exit wm8915_exit(void)
2945 {
2946         i2c_del_driver(&wm8915_i2c_driver);
2947 }
2948 module_exit(wm8915_exit);
2949
2950 MODULE_DESCRIPTION("ASoC WM8915 driver");
2951 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2952 MODULE_LICENSE("GPL");