2 * wm8955.c -- WM8955 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 #include <sound/wm8955.h>
32 static struct snd_soc_codec *wm8955_codec;
33 struct snd_soc_codec_device soc_codec_dev_wm8955;
35 #define WM8955_NUM_SUPPLIES 4
36 static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
43 /* codec private data */
45 struct snd_soc_codec codec;
46 u16 reg_cache[WM8955_MAX_REGISTER + 1];
48 unsigned int mclk_rate;
53 struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
55 struct wm8955_pdata *pdata;
58 static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = {
61 0x0079, /* R2 - LOUT1 volume */
62 0x0079, /* R3 - ROUT1 volume */
64 0x0008, /* R5 - DAC Control */
66 0x000A, /* R7 - Audio Interface */
67 0x0000, /* R8 - Sample Rate */
69 0x00FF, /* R10 - Left DAC volume */
70 0x00FF, /* R11 - Right DAC volume */
71 0x000F, /* R12 - Bass control */
72 0x000F, /* R13 - Treble control */
74 0x0000, /* R15 - Reset */
82 0x00C1, /* R23 - Additional control (1) */
83 0x0000, /* R24 - Additional control (2) */
84 0x0000, /* R25 - Power Management (1) */
85 0x0000, /* R26 - Power Management (2) */
86 0x0000, /* R27 - Additional Control (3) */
93 0x0050, /* R34 - Left out Mix (1) */
94 0x0050, /* R35 - Left out Mix (2) */
95 0x0050, /* R36 - Right out Mix (1) */
96 0x0050, /* R37 - Right Out Mix (2) */
97 0x0050, /* R38 - Mono out Mix (1) */
98 0x0050, /* R39 - Mono out Mix (2) */
99 0x0079, /* R40 - LOUT2 volume */
100 0x0079, /* R41 - ROUT2 volume */
101 0x0079, /* R42 - MONOOUT volume */
102 0x0000, /* R43 - Clocking / PLL */
103 0x0103, /* R44 - PLL Control 1 */
104 0x0024, /* R45 - PLL Control 2 */
105 0x01BA, /* R46 - PLL Control 3 */
118 0x0000, /* R59 - PLL Control 4 */
121 static int wm8955_reset(struct snd_soc_codec *codec)
123 return snd_soc_write(codec, WM8955_RESET, 0);
132 /* The size in bits of the FLL divide multiplied by 10
133 * to allow rounding later */
134 #define FIXED_FLL_SIZE ((1 << 22) * 10)
136 static int wm8995_pll_factors(struct device *dev,
137 int Fref, int Fout, struct pll_factors *pll)
140 unsigned int K, Ndiv, Nmod, target;
142 dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
144 /* The oscilator should run at should be 90-100MHz, and
145 * there's a divide by 4 plus an optional divide by 2 in the
146 * output path to generate the system clock. The clock table
147 * is sortd so we should always generate a suitable target. */
149 if (target < 90000000) {
156 WARN_ON(target < 90000000 || target > 100000000);
158 dev_dbg(dev, "Fvco=%dHz\n", target);
160 /* Now, calculate N.K */
161 Ndiv = target / Fref;
164 Nmod = target % Fref;
165 dev_dbg(dev, "Nmod=%d\n", Nmod);
167 /* Calculate fractional part - scale up so we can round. */
168 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
172 K = Kpart & 0xFFFFFFFF;
177 /* Move down to proper range now rounding is done */
180 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
185 /* Lookup table specifiying SRATE (table 25 in datasheet); some of the
186 * output frequencies have been rounded to the standard frequencies
187 * they are intended to match where the error is slight. */
194 { 18432000, 8000, 0, 3, },
195 { 18432000, 12000, 0, 9, },
196 { 18432000, 16000, 0, 11, },
197 { 18432000, 24000, 0, 29, },
198 { 18432000, 32000, 0, 13, },
199 { 18432000, 48000, 0, 1, },
200 { 18432000, 96000, 0, 15, },
202 { 16934400, 8018, 0, 19, },
203 { 16934400, 11025, 0, 25, },
204 { 16934400, 22050, 0, 27, },
205 { 16934400, 44100, 0, 17, },
206 { 16934400, 88200, 0, 31, },
208 { 12000000, 8000, 1, 2, },
209 { 12000000, 11025, 1, 25, },
210 { 12000000, 12000, 1, 8, },
211 { 12000000, 16000, 1, 10, },
212 { 12000000, 22050, 1, 27, },
213 { 12000000, 24000, 1, 28, },
214 { 12000000, 32000, 1, 12, },
215 { 12000000, 44100, 1, 17, },
216 { 12000000, 48000, 1, 0, },
217 { 12000000, 88200, 1, 31, },
218 { 12000000, 96000, 1, 14, },
220 { 12288000, 8000, 0, 2, },
221 { 12288000, 12000, 0, 8, },
222 { 12288000, 16000, 0, 10, },
223 { 12288000, 24000, 0, 28, },
224 { 12288000, 32000, 0, 12, },
225 { 12288000, 48000, 0, 0, },
226 { 12288000, 96000, 0, 14, },
228 { 12289600, 8018, 0, 18, },
229 { 12289600, 11025, 0, 24, },
230 { 12289600, 22050, 0, 26, },
231 { 11289600, 44100, 0, 16, },
232 { 11289600, 88200, 0, 31, },
235 static int wm8955_configure_clocking(struct snd_soc_codec *codec)
237 struct wm8955_priv *wm8955 = codec->private_data;
242 struct pll_factors pll;
244 /* If we're not running a sample rate currently just pick one */
248 /* Can we generate an exact output? */
249 for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
250 if (wm8955->fs != clock_cfgs[i].fs)
254 if (wm8955->mclk_rate == clock_cfgs[i].mclk)
258 /* We should never get here with an unsupported sample rate */
260 dev_err(codec->dev, "Sample rate %dHz unsupported\n",
266 if (i == ARRAY_SIZE(clock_cfgs)) {
267 /* If we can't generate the right clock from MCLK then
268 * we should configure the PLL to supply us with an
271 clocking |= WM8955_MCLKSEL;
273 /* Use the last divider configuration we saw for the
275 ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate,
276 clock_cfgs[sr].mclk, &pll);
279 "Unable to generate %dHz from %dHz MCLK\n",
280 wm8955->fs, wm8955->mclk_rate);
284 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1,
285 WM8955_N_MASK | WM8955_K_21_18_MASK,
286 (pll.n << WM8955_N_SHIFT) |
288 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
290 (pll.k >> 9) & WM8955_K_17_9_MASK);
291 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
293 pll.k & WM8955_K_8_0_MASK);
295 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
296 WM8955_KEN, WM8955_KEN);
298 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
302 val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
306 /* Now start the PLL running */
307 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
308 WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
309 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
310 WM8955_PLLEN, WM8955_PLLEN);
313 srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
315 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
316 WM8955_USB | WM8955_SR_MASK, srate);
317 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
318 WM8955_MCLKSEL, clocking);
323 static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
324 struct snd_kcontrol *kcontrol, int event)
326 struct snd_soc_codec *codec = w->codec;
329 /* Always disable the clocks - if we're doing reconfiguration this
330 * avoids misclocking.
332 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
334 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
335 WM8955_PLL_RB | WM8955_PLLEN, 0);
338 case SND_SOC_DAPM_POST_PMD:
340 case SND_SOC_DAPM_PRE_PMU:
341 ret = wm8955_configure_clocking(codec);
351 static int deemph_settings[] = { 0, 32000, 44100, 48000 };
353 static int wm8955_set_deemph(struct snd_soc_codec *codec)
355 struct wm8955_priv *wm8955 = codec->private_data;
358 /* If we're using deemphasis select the nearest available sample
361 if (wm8955->deemph) {
363 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
364 if (abs(deemph_settings[i] - wm8955->fs) <
365 abs(deemph_settings[best] - wm8955->fs))
369 val = best << WM8955_DEEMPH_SHIFT;
374 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
376 return snd_soc_update_bits(codec, WM8955_DAC_CONTROL,
377 WM8955_DEEMPH_MASK, val);
380 static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
381 struct snd_ctl_elem_value *ucontrol)
383 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
384 struct wm8955_priv *wm8955 = codec->private_data;
386 return wm8955->deemph;
389 static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
390 struct snd_ctl_elem_value *ucontrol)
392 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
393 struct wm8955_priv *wm8955 = codec->private_data;
394 int deemph = ucontrol->value.enumerated.item[0];
399 wm8955->deemph = deemph;
401 return wm8955_set_deemph(codec);
404 static const char *bass_mode_text[] = {
405 "Linear", "Adaptive",
408 static const struct soc_enum bass_mode =
409 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 7, 2, bass_mode_text);
411 static const char *bass_cutoff_text[] = {
415 static const struct soc_enum bass_cutoff =
416 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 6, 2, bass_cutoff_text);
418 static const char *treble_cutoff_text[] = {
422 static const struct soc_enum treble_cutoff =
423 SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL, 6, 2, treble_cutoff_text);
425 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
426 static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
427 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
428 static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
429 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
430 static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
432 static const struct snd_kcontrol_new wm8955_snd_controls[] = {
433 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
434 WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
435 SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
437 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
438 wm8955_get_deemph, wm8955_put_deemph),
440 SOC_ENUM("Bass Mode", bass_mode),
441 SOC_ENUM("Bass Cutoff", bass_cutoff),
442 SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
444 SOC_ENUM("Treble Cutoff", treble_cutoff),
445 SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
447 SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
449 SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
452 SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
454 SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
457 /* Not a stereo pair so they line up with the DAPM switches */
458 SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
460 SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
463 SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
464 WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
465 SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
466 WM8955_ROUT1_VOLUME, 7, 1, 0),
468 SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
469 WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
470 SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
471 WM8955_ROUT2_VOLUME, 7, 1, 0),
473 SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
474 SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
477 static const struct snd_kcontrol_new lmixer[] = {
478 SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
479 SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
480 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
481 SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
484 static const struct snd_kcontrol_new rmixer[] = {
485 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
486 SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
487 SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
488 SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
491 static const struct snd_kcontrol_new mmixer[] = {
492 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
493 SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
494 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
495 SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
498 static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
499 SND_SOC_DAPM_INPUT("MONOIN-"),
500 SND_SOC_DAPM_INPUT("MONOIN+"),
501 SND_SOC_DAPM_INPUT("LINEINR"),
502 SND_SOC_DAPM_INPUT("LINEINL"),
504 SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
506 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
507 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
508 SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
510 SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
511 SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
513 SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
514 SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
515 SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
516 SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
517 SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
518 SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
520 /* The names are chosen to make the control names nice */
521 SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
522 lmixer, ARRAY_SIZE(lmixer)),
523 SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
524 rmixer, ARRAY_SIZE(rmixer)),
525 SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
526 mmixer, ARRAY_SIZE(mmixer)),
528 SND_SOC_DAPM_OUTPUT("LOUT1"),
529 SND_SOC_DAPM_OUTPUT("ROUT1"),
530 SND_SOC_DAPM_OUTPUT("LOUT2"),
531 SND_SOC_DAPM_OUTPUT("ROUT2"),
532 SND_SOC_DAPM_OUTPUT("MONOOUT"),
533 SND_SOC_DAPM_OUTPUT("OUT3"),
536 static const struct snd_soc_dapm_route wm8955_intercon[] = {
537 { "DACL", NULL, "SYSCLK" },
538 { "DACR", NULL, "SYSCLK" },
540 { "Mono Input", NULL, "MONOIN-" },
541 { "Mono Input", NULL, "MONOIN+" },
543 { "Left", "Playback Switch", "DACL" },
544 { "Left", "Right Playback Switch", "DACR" },
545 { "Left", "Bypass Switch", "LINEINL" },
546 { "Left", "Mono Switch", "Mono Input" },
548 { "Right", "Playback Switch", "DACR" },
549 { "Right", "Left Playback Switch", "DACL" },
550 { "Right", "Bypass Switch", "LINEINR" },
551 { "Right", "Mono Switch", "Mono Input" },
553 { "Mono", "Left Playback Switch", "DACL" },
554 { "Mono", "Right Playback Switch", "DACR" },
555 { "Mono", "Left Bypass Switch", "LINEINL" },
556 { "Mono", "Right Bypass Switch", "LINEINR" },
558 { "LOUT1 PGA", NULL, "Left" },
559 { "LOUT1", NULL, "TSDEN" },
560 { "LOUT1", NULL, "LOUT1 PGA" },
562 { "ROUT1 PGA", NULL, "Right" },
563 { "ROUT1", NULL, "TSDEN" },
564 { "ROUT1", NULL, "ROUT1 PGA" },
566 { "LOUT2 PGA", NULL, "Left" },
567 { "LOUT2", NULL, "TSDEN" },
568 { "LOUT2", NULL, "LOUT2 PGA" },
570 { "ROUT2 PGA", NULL, "Right" },
571 { "ROUT2", NULL, "TSDEN" },
572 { "ROUT2", NULL, "ROUT2 PGA" },
574 { "MOUT PGA", NULL, "Mono" },
575 { "MONOOUT", NULL, "MOUT PGA" },
577 /* OUT3 not currently implemented */
578 { "OUT3", NULL, "OUT3 PGA" },
581 static int wm8955_add_widgets(struct snd_soc_codec *codec)
583 snd_soc_add_controls(codec, wm8955_snd_controls,
584 ARRAY_SIZE(wm8955_snd_controls));
586 snd_soc_dapm_new_controls(codec, wm8955_dapm_widgets,
587 ARRAY_SIZE(wm8955_dapm_widgets));
589 snd_soc_dapm_add_routes(codec, wm8955_intercon,
590 ARRAY_SIZE(wm8955_intercon));
595 static int wm8955_hw_params(struct snd_pcm_substream *substream,
596 struct snd_pcm_hw_params *params,
597 struct snd_soc_dai *dai)
599 struct snd_soc_codec *codec = dai->codec;
600 struct wm8955_priv *wm8955 = codec->private_data;
604 switch (params_format(params)) {
605 case SNDRV_PCM_FORMAT_S16_LE:
608 case SNDRV_PCM_FORMAT_S20_3LE:
611 case SNDRV_PCM_FORMAT_S24_LE:
614 case SNDRV_PCM_FORMAT_S32_LE:
620 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
623 wm8955->fs = params_rate(params);
624 wm8955_set_deemph(codec);
626 /* If the chip is clocked then disable the clocks and force a
627 * reconfiguration, otherwise DAPM will power up the
628 * clocks for us later. */
629 ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1);
632 if (ret & WM8955_DIGENB) {
633 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
635 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
636 WM8955_PLL_RB | WM8955_PLLEN, 0);
638 wm8955_configure_clocking(codec);
645 static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
646 unsigned int freq, int dir)
648 struct snd_soc_codec *codec = dai->codec;
649 struct wm8955_priv *priv = codec->private_data;
653 case WM8955_CLK_MCLK:
654 if (freq > 15000000) {
655 priv->mclk_rate = freq /= 2;
656 div = WM8955_MCLKDIV2;
658 priv->mclk_rate = freq;
662 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
663 WM8955_MCLKDIV2, div);
670 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
675 static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
677 struct snd_soc_codec *codec = dai->codec;
680 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
681 case SND_SOC_DAIFMT_CBS_CFS:
683 case SND_SOC_DAIFMT_CBM_CFM:
690 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
691 case SND_SOC_DAIFMT_DSP_B:
693 case SND_SOC_DAIFMT_DSP_A:
696 case SND_SOC_DAIFMT_I2S:
699 case SND_SOC_DAIFMT_RIGHT_J:
701 case SND_SOC_DAIFMT_LEFT_J:
708 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
709 case SND_SOC_DAIFMT_DSP_A:
710 case SND_SOC_DAIFMT_DSP_B:
711 /* frame inversion not valid for DSP modes */
712 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
713 case SND_SOC_DAIFMT_NB_NF:
715 case SND_SOC_DAIFMT_IB_NF:
716 aif |= WM8955_BCLKINV;
723 case SND_SOC_DAIFMT_I2S:
724 case SND_SOC_DAIFMT_RIGHT_J:
725 case SND_SOC_DAIFMT_LEFT_J:
726 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
727 case SND_SOC_DAIFMT_NB_NF:
729 case SND_SOC_DAIFMT_IB_IF:
730 aif |= WM8955_BCLKINV | WM8955_LRP;
732 case SND_SOC_DAIFMT_IB_NF:
733 aif |= WM8955_BCLKINV;
735 case SND_SOC_DAIFMT_NB_IF:
746 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
747 WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
754 static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute)
756 struct snd_soc_codec *codec = codec_dai->codec;
764 snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val);
769 static int wm8955_set_bias_level(struct snd_soc_codec *codec,
770 enum snd_soc_bias_level level)
772 struct wm8955_priv *wm8955 = codec->private_data;
776 case SND_SOC_BIAS_ON:
779 case SND_SOC_BIAS_PREPARE:
780 /* VMID resistance 2*50k */
781 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
783 0x1 << WM8955_VMIDSEL_SHIFT);
785 /* Default bias current */
786 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
788 0x2 << WM8955_VSEL_SHIFT);
791 case SND_SOC_BIAS_STANDBY:
792 if (codec->bias_level == SND_SOC_BIAS_OFF) {
793 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
797 "Failed to enable supplies: %d\n",
802 /* Sync back cached values if they're
803 * different from the hardware default.
805 for (i = 0; i < ARRAY_SIZE(wm8955->reg_cache); i++) {
806 if (i == WM8955_RESET)
809 if (wm8955->reg_cache[i] == wm8955_reg[i])
812 snd_soc_write(codec, i, wm8955->reg_cache[i]);
815 /* Enable VREF and VMID */
816 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
820 0x3 << WM8955_VREF_SHIFT);
825 /* High resistance VROI to maintain outputs */
826 snd_soc_update_bits(codec,
827 WM8955_ADDITIONAL_CONTROL_3,
828 WM8955_VROI, WM8955_VROI);
831 /* Maintain VMID with 2*250k */
832 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
834 0x2 << WM8955_VMIDSEL_SHIFT);
836 /* Minimum bias current */
837 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
838 WM8955_VSEL_MASK, 0);
841 case SND_SOC_BIAS_OFF:
842 /* Low resistance VROI to help discharge */
843 snd_soc_update_bits(codec,
844 WM8955_ADDITIONAL_CONTROL_3,
847 /* Turn off VMID and VREF */
848 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
850 WM8955_VMIDSEL_MASK, 0);
852 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
856 codec->bias_level = level;
860 #define WM8955_RATES SNDRV_PCM_RATE_8000_96000
862 #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
863 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
865 static struct snd_soc_dai_ops wm8955_dai_ops = {
866 .set_sysclk = wm8955_set_sysclk,
867 .set_fmt = wm8955_set_fmt,
868 .hw_params = wm8955_hw_params,
869 .digital_mute = wm8955_digital_mute,
872 struct snd_soc_dai wm8955_dai = {
875 .stream_name = "Playback",
878 .rates = WM8955_RATES,
879 .formats = WM8955_FORMATS,
881 .ops = &wm8955_dai_ops,
883 EXPORT_SYMBOL_GPL(wm8955_dai);
886 static int wm8955_suspend(struct platform_device *pdev, pm_message_t state)
888 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
889 struct snd_soc_codec *codec = socdev->card->codec;
891 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
896 static int wm8955_resume(struct platform_device *pdev)
898 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
899 struct snd_soc_codec *codec = socdev->card->codec;
901 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
906 #define wm8955_suspend NULL
907 #define wm8955_resume NULL
910 static int wm8955_probe(struct platform_device *pdev)
912 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
913 struct snd_soc_codec *codec;
916 if (wm8955_codec == NULL) {
917 dev_err(&pdev->dev, "Codec device not registered\n");
921 socdev->card->codec = wm8955_codec;
922 codec = wm8955_codec;
925 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
927 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
931 wm8955_add_widgets(codec);
939 static int wm8955_remove(struct platform_device *pdev)
941 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
943 snd_soc_free_pcms(socdev);
944 snd_soc_dapm_free(socdev);
949 struct snd_soc_codec_device soc_codec_dev_wm8955 = {
950 .probe = wm8955_probe,
951 .remove = wm8955_remove,
952 .suspend = wm8955_suspend,
953 .resume = wm8955_resume,
955 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8955);
957 static int wm8955_register(struct wm8955_priv *wm8955,
958 enum snd_soc_control_type control)
961 struct snd_soc_codec *codec = &wm8955->codec;
965 dev_err(codec->dev, "Another WM8955 is registered\n");
969 mutex_init(&codec->mutex);
970 INIT_LIST_HEAD(&codec->dapm_widgets);
971 INIT_LIST_HEAD(&codec->dapm_paths);
973 codec->private_data = wm8955;
974 codec->name = "WM8955";
975 codec->owner = THIS_MODULE;
976 codec->bias_level = SND_SOC_BIAS_OFF;
977 codec->set_bias_level = wm8955_set_bias_level;
978 codec->dai = &wm8955_dai;
980 codec->reg_cache_size = WM8955_MAX_REGISTER;
981 codec->reg_cache = &wm8955->reg_cache;
983 memcpy(codec->reg_cache, wm8955_reg, sizeof(wm8955_reg));
985 ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
987 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
991 for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
992 wm8955->supplies[i].supply = wm8955_supply_names[i];
994 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies),
997 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1001 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
1004 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1008 ret = wm8955_reset(codec);
1010 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1014 wm8955_dai.dev = codec->dev;
1016 /* Change some default settings - latch VU and enable ZC */
1017 wm8955->reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU;
1018 wm8955->reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU;
1019 wm8955->reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC;
1020 wm8955->reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC;
1021 wm8955->reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC;
1022 wm8955->reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC;
1023 wm8955->reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC;
1025 /* Also enable adaptive bass boost by default */
1026 wm8955->reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB;
1028 /* Set platform data values */
1029 if (wm8955->pdata) {
1030 if (wm8955->pdata->out2_speaker)
1031 wm8955->reg_cache[WM8955_ADDITIONAL_CONTROL_2]
1034 if (wm8955->pdata->monoin_diff)
1035 wm8955->reg_cache[WM8955_MONO_OUT_MIX_1]
1039 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1041 /* Bias level configuration will have done an extra enable */
1042 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
1044 wm8955_codec = codec;
1046 ret = snd_soc_register_codec(codec);
1048 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1052 ret = snd_soc_register_dai(&wm8955_dai);
1054 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1055 snd_soc_unregister_codec(codec);
1062 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
1064 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
1070 static void wm8955_unregister(struct wm8955_priv *wm8955)
1072 wm8955_set_bias_level(&wm8955->codec, SND_SOC_BIAS_OFF);
1073 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
1074 snd_soc_unregister_dai(&wm8955_dai);
1075 snd_soc_unregister_codec(&wm8955->codec);
1077 wm8955_codec = NULL;
1080 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1081 static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
1082 const struct i2c_device_id *id)
1084 struct wm8955_priv *wm8955;
1085 struct snd_soc_codec *codec;
1087 wm8955 = kzalloc(sizeof(struct wm8955_priv), GFP_KERNEL);
1091 codec = &wm8955->codec;
1092 codec->hw_write = (hw_write_t)i2c_master_send;
1094 i2c_set_clientdata(i2c, wm8955);
1095 codec->control_data = i2c;
1096 wm8955->pdata = i2c->dev.platform_data;
1098 codec->dev = &i2c->dev;
1100 return wm8955_register(wm8955, SND_SOC_I2C);
1103 static __devexit int wm8955_i2c_remove(struct i2c_client *client)
1105 struct wm8955_priv *wm8955 = i2c_get_clientdata(client);
1106 wm8955_unregister(wm8955);
1110 static const struct i2c_device_id wm8955_i2c_id[] = {
1114 MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1116 static struct i2c_driver wm8955_i2c_driver = {
1119 .owner = THIS_MODULE,
1121 .probe = wm8955_i2c_probe,
1122 .remove = __devexit_p(wm8955_i2c_remove),
1123 .id_table = wm8955_i2c_id,
1127 static int __init wm8955_modinit(void)
1130 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1131 ret = i2c_add_driver(&wm8955_i2c_driver);
1133 printk(KERN_ERR "Failed to register WM8955 I2C driver: %d\n",
1139 module_init(wm8955_modinit);
1141 static void __exit wm8955_exit(void)
1143 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1144 i2c_del_driver(&wm8955_i2c_driver);
1147 module_exit(wm8955_exit);
1149 MODULE_DESCRIPTION("ASoC WM8955 driver");
1150 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1151 MODULE_LICENSE("GPL");