sound/soc/codecs/wm8985.c

   1 /*
   2  * wm8985.c  --  WM8985 ALSA SoC Audio driver
   3  *
   4  * Copyright 2010 Wolfson Microelectronics plc
   5  *
   6  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * TODO:
  13  *  o Add OUT3/OUT4 mixer controls.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/init.h>
  19 #include <linux/delay.h>
  20 #include <linux/pm.h>
  21 #include <linux/i2c.h>
  22 #include <linux/regmap.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/slab.h>
  26 #include <sound/core.h>
  27 #include <sound/pcm.h>
  28 #include <sound/pcm_params.h>
  29 #include <sound/soc.h>
  30 #include <sound/initval.h>
  31 #include <sound/tlv.h>
  32
  33 #include "wm8985.h"
  34
  35 #define WM8985_NUM_SUPPLIES 4
  36 static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
  37         "DCVDD",
  38         "DBVDD",
  39         "AVDD1",
  40         "AVDD2"
  41 };
  42
  43 static const struct reg_default wm8985_reg_defaults[] = {
  44         { 1,  0x0000 },     /* R1  - Power management 1 */
  45         { 2,  0x0000 },     /* R2  - Power management 2 */
  46         { 3,  0x0000 },     /* R3  - Power management 3 */
  47         { 4,  0x0050 },     /* R4  - Audio Interface */
  48         { 5,  0x0000 },     /* R5  - Companding control */
  49         { 6,  0x0140 },     /* R6  - Clock Gen control */
  50         { 7,  0x0000 },     /* R7  - Additional control */
  51         { 8,  0x0000 },     /* R8  - GPIO Control */
  52         { 9,  0x0000 },     /* R9  - Jack Detect Control 1 */
  53         { 10, 0x0000 },     /* R10 - DAC Control */
  54         { 11, 0x00FF },     /* R11 - Left DAC digital Vol */
  55         { 12, 0x00FF },     /* R12 - Right DAC digital vol */
  56         { 13, 0x0000 },     /* R13 - Jack Detect Control 2 */
  57         { 14, 0x0100 },     /* R14 - ADC Control */
  58         { 15, 0x00FF },     /* R15 - Left ADC Digital Vol */
  59         { 16, 0x00FF },     /* R16 - Right ADC Digital Vol */
  60         { 18, 0x012C },     /* R18 - EQ1 - low shelf */
  61         { 19, 0x002C },     /* R19 - EQ2 - peak 1 */
  62         { 20, 0x002C },     /* R20 - EQ3 - peak 2 */
  63         { 21, 0x002C },     /* R21 - EQ4 - peak 3 */
  64         { 22, 0x002C },     /* R22 - EQ5 - high shelf */
  65         { 24, 0x0032 },     /* R24 - DAC Limiter 1 */
  66         { 25, 0x0000 },     /* R25 - DAC Limiter 2 */
  67         { 27, 0x0000 },     /* R27 - Notch Filter 1 */
  68         { 28, 0x0000 },     /* R28 - Notch Filter 2 */
  69         { 29, 0x0000 },     /* R29 - Notch Filter 3 */
  70         { 30, 0x0000 },     /* R30 - Notch Filter 4 */
  71         { 32, 0x0038 },     /* R32 - ALC control 1 */
  72         { 33, 0x000B },     /* R33 - ALC control 2 */
  73         { 34, 0x0032 },     /* R34 - ALC control 3 */
  74         { 35, 0x0000 },     /* R35 - Noise Gate */
  75         { 36, 0x0008 },     /* R36 - PLL N */
  76         { 37, 0x000C },     /* R37 - PLL K 1 */
  77         { 38, 0x0093 },     /* R38 - PLL K 2 */
  78         { 39, 0x00E9 },     /* R39 - PLL K 3 */
  79         { 41, 0x0000 },     /* R41 - 3D control */
  80         { 42, 0x0000 },     /* R42 - OUT4 to ADC */
  81         { 43, 0x0000 },     /* R43 - Beep control */
  82         { 44, 0x0033 },     /* R44 - Input ctrl */
  83         { 45, 0x0010 },     /* R45 - Left INP PGA gain ctrl */
  84         { 46, 0x0010 },     /* R46 - Right INP PGA gain ctrl */
  85         { 47, 0x0100 },     /* R47 - Left ADC BOOST ctrl */
  86         { 48, 0x0100 },     /* R48 - Right ADC BOOST ctrl */
  87         { 49, 0x0002 },     /* R49 - Output ctrl */
  88         { 50, 0x0001 },     /* R50 - Left mixer ctrl */
  89         { 51, 0x0001 },     /* R51 - Right mixer ctrl */
  90         { 52, 0x0039 },     /* R52 - LOUT1 (HP) volume ctrl */
  91         { 53, 0x0039 },     /* R53 - ROUT1 (HP) volume ctrl */
  92         { 54, 0x0039 },     /* R54 - LOUT2 (SPK) volume ctrl */
  93         { 55, 0x0039 },     /* R55 - ROUT2 (SPK) volume ctrl */
  94         { 56, 0x0001 },     /* R56 - OUT3 mixer ctrl */
  95         { 57, 0x0001 },     /* R57 - OUT4 (MONO) mix ctrl */
  96         { 60, 0x0004 },     /* R60 - OUTPUT ctrl */
  97         { 61, 0x0000 },     /* R61 - BIAS CTRL */
  98 };
  99
 100 static bool wm8985_writeable(struct device *dev, unsigned int reg)
 101 {
 102         switch (reg) {
 103         case WM8985_SOFTWARE_RESET:
 104         case WM8985_POWER_MANAGEMENT_1:
 105         case WM8985_POWER_MANAGEMENT_2:
 106         case WM8985_POWER_MANAGEMENT_3:
 107         case WM8985_AUDIO_INTERFACE:
 108         case WM8985_COMPANDING_CONTROL:
 109         case WM8985_CLOCK_GEN_CONTROL:
 110         case WM8985_ADDITIONAL_CONTROL:
 111         case WM8985_GPIO_CONTROL:
 112         case WM8985_JACK_DETECT_CONTROL_1:
 113         case WM8985_DAC_CONTROL:
 114         case WM8985_LEFT_DAC_DIGITAL_VOL:
 115         case WM8985_RIGHT_DAC_DIGITAL_VOL:
 116         case WM8985_JACK_DETECT_CONTROL_2:
 117         case WM8985_ADC_CONTROL:
 118         case WM8985_LEFT_ADC_DIGITAL_VOL:
 119         case WM8985_RIGHT_ADC_DIGITAL_VOL:
 120         case WM8985_EQ1_LOW_SHELF:
 121         case WM8985_EQ2_PEAK_1:
 122         case WM8985_EQ3_PEAK_2:
 123         case WM8985_EQ4_PEAK_3:
 124         case WM8985_EQ5_HIGH_SHELF:
 125         case WM8985_DAC_LIMITER_1:
 126         case WM8985_DAC_LIMITER_2:
 127         case WM8985_NOTCH_FILTER_1:
 128         case WM8985_NOTCH_FILTER_2:
 129         case WM8985_NOTCH_FILTER_3:
 130         case WM8985_NOTCH_FILTER_4:
 131         case WM8985_ALC_CONTROL_1:
 132         case WM8985_ALC_CONTROL_2:
 133         case WM8985_ALC_CONTROL_3:
 134         case WM8985_NOISE_GATE:
 135         case WM8985_PLL_N:
 136         case WM8985_PLL_K_1:
 137         case WM8985_PLL_K_2:
 138         case WM8985_PLL_K_3:
 139         case WM8985_3D_CONTROL:
 140         case WM8985_OUT4_TO_ADC:
 141         case WM8985_BEEP_CONTROL:
 142         case WM8985_INPUT_CTRL:
 143         case WM8985_LEFT_INP_PGA_GAIN_CTRL:
 144         case WM8985_RIGHT_INP_PGA_GAIN_CTRL:
 145         case WM8985_LEFT_ADC_BOOST_CTRL:
 146         case WM8985_RIGHT_ADC_BOOST_CTRL:
 147         case WM8985_OUTPUT_CTRL0:
 148         case WM8985_LEFT_MIXER_CTRL:
 149         case WM8985_RIGHT_MIXER_CTRL:
 150         case WM8985_LOUT1_HP_VOLUME_CTRL:
 151         case WM8985_ROUT1_HP_VOLUME_CTRL:
 152         case WM8985_LOUT2_SPK_VOLUME_CTRL:
 153         case WM8985_ROUT2_SPK_VOLUME_CTRL:
 154         case WM8985_OUT3_MIXER_CTRL:
 155         case WM8985_OUT4_MONO_MIX_CTRL:
 156         case WM8985_OUTPUT_CTRL1:
 157         case WM8985_BIAS_CTRL:
 158                 return true;
 159         default:
 160                 return false;
 161         }
 162 }
 163
 164 /*
 165  * latch bit 8 of these registers to ensure instant
 166  * volume updates
 167  */
 168 static const int volume_update_regs[] = {
 169         WM8985_LEFT_DAC_DIGITAL_VOL,
 170         WM8985_RIGHT_DAC_DIGITAL_VOL,
 171         WM8985_LEFT_ADC_DIGITAL_VOL,
 172         WM8985_RIGHT_ADC_DIGITAL_VOL,
 173         WM8985_LOUT2_SPK_VOLUME_CTRL,
 174         WM8985_ROUT2_SPK_VOLUME_CTRL,
 175         WM8985_LOUT1_HP_VOLUME_CTRL,
 176         WM8985_ROUT1_HP_VOLUME_CTRL,
 177         WM8985_LEFT_INP_PGA_GAIN_CTRL,
 178         WM8985_RIGHT_INP_PGA_GAIN_CTRL
 179 };
 180
 181 struct wm8985_priv {
 182         struct regmap *regmap;
 183         struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
 184         unsigned int sysclk;
 185         unsigned int bclk;
 186 };
 187
 188 static const struct {
 189         int div;
 190         int ratio;
 191 } fs_ratios[] = {
 192         { 10, 128 },
 193         { 15, 192 },
 194         { 20, 256 },
 195         { 30, 384 },
 196         { 40, 512 },
 197         { 60, 768 },
 198         { 80, 1024 },
 199         { 120, 1536 }
 200 };
 201
 202 static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
 203
 204 static const int bclk_divs[] = {
 205         1, 2, 4, 8, 16, 32
 206 };
 207
 208 static int eqmode_get(struct snd_kcontrol *kcontrol,
 209                       struct snd_ctl_elem_value *ucontrol);
 210 static int eqmode_put(struct snd_kcontrol *kcontrol,
 211                       struct snd_ctl_elem_value *ucontrol);
 212
 213 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
 214 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
 215 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
 216 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
 217 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
 218 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
 219 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
 220 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
 221 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
 222 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
 223 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 224 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
 225 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
 226 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
 227
 228 static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
 229 static SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7, alc_sel_text);
 230
 231 static const char *alc_mode_text[] = { "ALC", "Limiter" };
 232 static SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8, alc_mode_text);
 233
 234 static const char *filter_mode_text[] = { "Audio", "Application" };
 235 static SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
 236                             filter_mode_text);
 237
 238 static const char *eq_bw_text[] = { "Narrow", "Wide" };
 239 static const char *eqmode_text[] = { "Capture", "Playback" };
 240 static SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
 241
 242 static const char *eq1_cutoff_text[] = {
 243         "80Hz", "105Hz", "135Hz", "175Hz"
 244 };
 245 static SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
 246                             eq1_cutoff_text);
 247 static const char *eq2_cutoff_text[] = {
 248         "230Hz", "300Hz", "385Hz", "500Hz"
 249 };
 250 static SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
 251 static SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5, eq2_cutoff_text);
 252 static const char *eq3_cutoff_text[] = {
 253         "650Hz", "850Hz", "1.1kHz", "1.4kHz"
 254 };
 255 static SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
 256 static SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
 257                             eq3_cutoff_text);
 258 static const char *eq4_cutoff_text[] = {
 259         "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
 260 };
 261 static SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
 262 static SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5, eq4_cutoff_text);
 263 static const char *eq5_cutoff_text[] = {
 264         "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
 265 };
 266 static SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
 267                                   eq5_cutoff_text);
 268
 269 static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
 270 static SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
 271
 272 static const char *depth_3d_text[] = {
 273         "Off",
 274         "6.67%",
 275         "13.3%",
 276         "20%",
 277         "26.7%",
 278         "33.3%",
 279         "40%",
 280         "46.6%",
 281         "53.3%",
 282         "60%",
 283         "66.7%",
 284         "73.3%",
 285         "80%",
 286         "86.7%",
 287         "93.3%",
 288         "100%"
 289 };
 290 static SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0, depth_3d_text);
 291
 292 static const struct snd_kcontrol_new wm8985_snd_controls[] = {
 293         SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
 294                 0, 1, 0),
 295
 296         SOC_ENUM("ALC Capture Function", alc_sel),
 297         SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
 298                 3, 7, 0, alc_max_tlv),
 299         SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
 300                 0, 7, 0, alc_min_tlv),
 301         SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
 302                 0, 15, 0, alc_tar_tlv),
 303         SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
 304         SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
 305         SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
 306         SOC_ENUM("ALC Mode", alc_mode),
 307         SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
 308                 3, 1, 0),
 309         SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
 310                 0, 7, 1),
 311
 312         SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
 313                 WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
 314         SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
 315                 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
 316         SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
 317                 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
 318
 319         SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
 320                 WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
 321                 8, 1, 0, pga_boost_tlv),
 322
 323         SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
 324         SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
 325
 326         SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
 327                 WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
 328
 329         SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
 330         SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
 331         SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
 332         SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
 333                 4, 7, 1, lim_thresh_tlv),
 334         SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
 335                 0, 12, 0, lim_boost_tlv),
 336         SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
 337         SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
 338         SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
 339
 340         SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
 341                 WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
 342         SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
 343                 WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
 344         SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
 345                 WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
 346
 347         SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
 348                 WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
 349         SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
 350                 WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
 351         SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
 352                 WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
 353
 354         SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
 355         SOC_ENUM("High Pass Filter Mode", filter_mode),
 356         SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
 357
 358         SOC_DOUBLE_R_TLV("Aux Bypass Volume",
 359                 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
 360                 aux_tlv),
 361
 362         SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
 363                 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
 364                 bypass_tlv),
 365
 366         SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
 367         SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
 368         SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF,  0, 24, 1, eq_tlv),
 369         SOC_ENUM("EQ2 Bandwidth", eq2_bw),
 370         SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
 371         SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
 372         SOC_ENUM("EQ3 Bandwidth", eq3_bw),
 373         SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
 374         SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
 375         SOC_ENUM("EQ4 Bandwidth", eq4_bw),
 376         SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
 377         SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
 378         SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
 379         SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
 380
 381         SOC_ENUM("3D Depth", depth_3d),
 382
 383         SOC_ENUM("Speaker Mode", speaker_mode)
 384 };
 385
 386 static const struct snd_kcontrol_new left_out_mixer[] = {
 387         SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
 388         SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
 389         SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
 390 };
 391
 392 static const struct snd_kcontrol_new right_out_mixer[] = {
 393         SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
 394         SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
 395         SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
 396 };
 397
 398 static const struct snd_kcontrol_new left_input_mixer[] = {
 399         SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
 400         SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
 401         SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
 402 };
 403
 404 static const struct snd_kcontrol_new right_input_mixer[] = {
 405         SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
 406         SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
 407         SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
 408 };
 409
 410 static const struct snd_kcontrol_new left_boost_mixer[] = {
 411         SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
 412                 4, 7, 0, boost_tlv),
 413         SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
 414                 0, 7, 0, boost_tlv)
 415 };
 416
 417 static const struct snd_kcontrol_new right_boost_mixer[] = {
 418         SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
 419                 4, 7, 0, boost_tlv),
 420         SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
 421                 0, 7, 0, boost_tlv)
 422 };
 423
 424 static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
 425         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
 426                 0, 0),
 427         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
 428                 1, 0),
 429         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
 430                 0, 0),
 431         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
 432                 1, 0),
 433
 434         SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
 435                 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
 436         SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
 437                 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
 438
 439         SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
 440                 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
 441         SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
 442                 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
 443
 444         SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
 445                 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
 446         SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
 447                 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
 448
 449         SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
 450                 6, 1, NULL, 0),
 451         SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
 452                 6, 1, NULL, 0),
 453
 454         SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
 455                 7, 0, NULL, 0),
 456         SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
 457                 8, 0, NULL, 0),
 458
 459         SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
 460                 5, 0, NULL, 0),
 461         SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
 462                 6, 0, NULL, 0),
 463
 464         SND_SOC_DAPM_SUPPLY("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0,
 465                             NULL, 0),
 466
 467         SND_SOC_DAPM_INPUT("LIN"),
 468         SND_SOC_DAPM_INPUT("LIP"),
 469         SND_SOC_DAPM_INPUT("RIN"),
 470         SND_SOC_DAPM_INPUT("RIP"),
 471         SND_SOC_DAPM_INPUT("AUXL"),
 472         SND_SOC_DAPM_INPUT("AUXR"),
 473         SND_SOC_DAPM_INPUT("L2"),
 474         SND_SOC_DAPM_INPUT("R2"),
 475         SND_SOC_DAPM_OUTPUT("HPL"),
 476         SND_SOC_DAPM_OUTPUT("HPR"),
 477         SND_SOC_DAPM_OUTPUT("SPKL"),
 478         SND_SOC_DAPM_OUTPUT("SPKR")
 479 };
 480
 481 static const struct snd_soc_dapm_route wm8985_dapm_routes[] = {
 482         { "Right Output Mixer", "PCM Switch", "Right DAC" },
 483         { "Right Output Mixer", "Aux Switch", "AUXR" },
 484         { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
 485
 486         { "Left Output Mixer", "PCM Switch", "Left DAC" },
 487         { "Left Output Mixer", "Aux Switch", "AUXL" },
 488         { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
 489
 490         { "Right Headphone Out", NULL, "Right Output Mixer" },
 491         { "HPR", NULL, "Right Headphone Out" },
 492
 493         { "Left Headphone Out", NULL, "Left Output Mixer" },
 494         { "HPL", NULL, "Left Headphone Out" },
 495
 496         { "Right Speaker Out", NULL, "Right Output Mixer" },
 497         { "SPKR", NULL, "Right Speaker Out" },
 498
 499         { "Left Speaker Out", NULL, "Left Output Mixer" },
 500         { "SPKL", NULL, "Left Speaker Out" },
 501
 502         { "Right ADC", NULL, "Right Boost Mixer" },
 503
 504         { "Right Boost Mixer", "AUXR Volume", "AUXR" },
 505         { "Right Boost Mixer", NULL, "Right Capture PGA" },
 506         { "Right Boost Mixer", "R2 Volume", "R2" },
 507
 508         { "Left ADC", NULL, "Left Boost Mixer" },
 509
 510         { "Left Boost Mixer", "AUXL Volume", "AUXL" },
 511         { "Left Boost Mixer", NULL, "Left Capture PGA" },
 512         { "Left Boost Mixer", "L2 Volume", "L2" },
 513
 514         { "Right Capture PGA", NULL, "Right Input Mixer" },
 515         { "Left Capture PGA", NULL, "Left Input Mixer" },
 516
 517         { "Right Input Mixer", "R2 Switch", "R2" },
 518         { "Right Input Mixer", "MicN Switch", "RIN" },
 519         { "Right Input Mixer", "MicP Switch", "RIP" },
 520
 521         { "Left Input Mixer", "L2 Switch", "L2" },
 522         { "Left Input Mixer", "MicN Switch", "LIN" },
 523         { "Left Input Mixer", "MicP Switch", "LIP" },
 524 };
 525
 526 static int eqmode_get(struct snd_kcontrol *kcontrol,
 527                       struct snd_ctl_elem_value *ucontrol)
 528 {
 529         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 530         unsigned int reg;
 531
 532         reg = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
 533         if (reg & WM8985_EQ3DMODE)
 534                 ucontrol->value.integer.value[0] = 1;
 535         else
 536                 ucontrol->value.integer.value[0] = 0;
 537
 538         return 0;
 539 }
 540
 541 static int eqmode_put(struct snd_kcontrol *kcontrol,
 542                       struct snd_ctl_elem_value *ucontrol)
 543 {
 544         struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 545         unsigned int regpwr2, regpwr3;
 546         unsigned int reg_eq;
 547
 548         if (ucontrol->value.integer.value[0] != 0
 549                         && ucontrol->value.integer.value[0] != 1)
 550                 return -EINVAL;
 551
 552         reg_eq = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
 553         switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
 554         case 0:
 555                 if (!ucontrol->value.integer.value[0])
 556                         return 0;
 557                 break;
 558         case 1:
 559                 if (ucontrol->value.integer.value[0])
 560                         return 0;
 561                 break;
 562         }
 563
 564         regpwr2 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_2);
 565         regpwr3 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_3);
 566         /* disable the DACs and ADCs */
 567         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_2,
 568                             WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
 569         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_3,
 570                             WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
 571         snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
 572                             WM8985_M128ENB_MASK, WM8985_M128ENB);
 573         /* set the desired eqmode */
 574         snd_soc_update_bits(codec, WM8985_EQ1_LOW_SHELF,
 575                             WM8985_EQ3DMODE_MASK,
 576                             ucontrol->value.integer.value[0]
 577                             << WM8985_EQ3DMODE_SHIFT);
 578         /* restore DAC/ADC configuration */
 579         snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, regpwr2);
 580         snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, regpwr3);
 581         return 0;
 582 }
 583
 584 static int wm8985_reset(struct snd_soc_codec *codec)
 585 {
 586         return snd_soc_write(codec, WM8985_SOFTWARE_RESET, 0x0);
 587 }
 588
 589 static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute)
 590 {
 591         struct snd_soc_codec *codec = dai->codec;
 592
 593         return snd_soc_update_bits(codec, WM8985_DAC_CONTROL,
 594                                    WM8985_SOFTMUTE_MASK,
 595                                    !!mute << WM8985_SOFTMUTE_SHIFT);
 596 }
 597
 598 static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 599 {
 600         struct snd_soc_codec *codec;
 601         u16 format, master, bcp, lrp;
 602
 603         codec = dai->codec;
 604
 605         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 606         case SND_SOC_DAIFMT_I2S:
 607                 format = 0x2;
 608                 break;
 609         case SND_SOC_DAIFMT_RIGHT_J:
 610                 format = 0x0;
 611                 break;
 612         case SND_SOC_DAIFMT_LEFT_J:
 613                 format = 0x1;
 614                 break;
 615         case SND_SOC_DAIFMT_DSP_A:
 616         case SND_SOC_DAIFMT_DSP_B:
 617                 format = 0x3;
 618                 break;
 619         default:
 620                 dev_err(dai->dev, "Unknown dai format\n");
 621                 return -EINVAL;
 622         }
 623
 624         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 625                             WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
 626
 627         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 628         case SND_SOC_DAIFMT_CBM_CFM:
 629                 master = 1;
 630                 break;
 631         case SND_SOC_DAIFMT_CBS_CFS:
 632                 master = 0;
 633                 break;
 634         default:
 635                 dev_err(dai->dev, "Unknown master/slave configuration\n");
 636                 return -EINVAL;
 637         }
 638
 639         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 640                             WM8985_MS_MASK, master << WM8985_MS_SHIFT);
 641
 642         /* frame inversion is not valid for dsp modes */
 643         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 644         case SND_SOC_DAIFMT_DSP_A:
 645         case SND_SOC_DAIFMT_DSP_B:
 646                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 647                 case SND_SOC_DAIFMT_IB_IF:
 648                 case SND_SOC_DAIFMT_NB_IF:
 649                         return -EINVAL;
 650                 default:
 651                         break;
 652                 }
 653                 break;
 654         default:
 655                 break;
 656         }
 657
 658         bcp = lrp = 0;
 659         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 660         case SND_SOC_DAIFMT_NB_NF:
 661                 break;
 662         case SND_SOC_DAIFMT_IB_IF:
 663                 bcp = lrp = 1;
 664                 break;
 665         case SND_SOC_DAIFMT_IB_NF:
 666                 bcp = 1;
 667                 break;
 668         case SND_SOC_DAIFMT_NB_IF:
 669                 lrp = 1;
 670                 break;
 671         default:
 672                 dev_err(dai->dev, "Unknown polarity configuration\n");
 673                 return -EINVAL;
 674         }
 675
 676         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 677                             WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
 678         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 679                             WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
 680         return 0;
 681 }
 682
 683 static int wm8985_hw_params(struct snd_pcm_substream *substream,
 684                             struct snd_pcm_hw_params *params,
 685                             struct snd_soc_dai *dai)
 686 {
 687         int i;
 688         struct snd_soc_codec *codec;
 689         struct wm8985_priv *wm8985;
 690         u16 blen, srate_idx;
 691         unsigned int tmp;
 692         int srate_best;
 693
 694         codec = dai->codec;
 695         wm8985 = snd_soc_codec_get_drvdata(codec);
 696
 697         wm8985->bclk = snd_soc_params_to_bclk(params);
 698         if ((int)wm8985->bclk < 0)
 699                 return wm8985->bclk;
 700
 701         switch (params_width(params)) {
 702         case 16:
 703                 blen = 0x0;
 704                 break;
 705         case 20:
 706                 blen = 0x1;
 707                 break;
 708         case 24:
 709                 blen = 0x2;
 710                 break;
 711         case 32:
 712                 blen = 0x3;
 713                 break;
 714         default:
 715                 dev_err(dai->dev, "Unsupported word length %u\n",
 716                         params_width(params));
 717                 return -EINVAL;
 718         }
 719
 720         snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
 721                             WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
 722
 723         /*
 724          * match to the nearest possible sample rate and rely
 725          * on the array index to configure the SR register
 726          */
 727         srate_idx = 0;
 728         srate_best = abs(srates[0] - params_rate(params));
 729         for (i = 1; i < ARRAY_SIZE(srates); ++i) {
 730                 if (abs(srates[i] - params_rate(params)) >= srate_best)
 731                         continue;
 732                 srate_idx = i;
 733                 srate_best = abs(srates[i] - params_rate(params));
 734         }
 735
 736         dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
 737         snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
 738                             WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
 739
 740         dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
 741         dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
 742
 743         for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
 744                 if (wm8985->sysclk / params_rate(params)
 745                                 == fs_ratios[i].ratio)
 746                         break;
 747         }
 748
 749         if (i == ARRAY_SIZE(fs_ratios)) {
 750                 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
 751                         wm8985->sysclk, params_rate(params));
 752                 return -EINVAL;
 753         }
 754
 755         dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
 756         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 757                             WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
 758
 759         /* select the appropriate bclk divider */
 760         tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
 761         for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
 762                 if (wm8985->bclk == tmp / bclk_divs[i])
 763                         break;
 764         }
 765
 766         if (i == ARRAY_SIZE(bclk_divs)) {
 767                 dev_err(dai->dev, "No matching BCLK divider found\n");
 768                 return -EINVAL;
 769         }
 770
 771         dev_dbg(dai->dev, "BCLK div = %d\n", i);
 772         snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 773                             WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
 774         return 0;
 775 }
 776
 777 struct pll_div {
 778         u32 div2:1;
 779         u32 n:4;
 780         u32 k:24;
 781 };
 782
 783 #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
 784 static int pll_factors(struct pll_div *pll_div, unsigned int target,
 785                        unsigned int source)
 786 {
 787         u64 Kpart;
 788         unsigned long int K, Ndiv, Nmod;
 789
 790         pll_div->div2 = 0;
 791         Ndiv = target / source;
 792         if (Ndiv < 6) {
 793                 source >>= 1;
 794                 pll_div->div2 = 1;
 795                 Ndiv = target / source;
 796         }
 797
 798         if (Ndiv < 6 || Ndiv > 12) {
 799                 printk(KERN_ERR "%s: WM8985 N value is not within"
 800                        " the recommended range: %lu\n", __func__, Ndiv);
 801                 return -EINVAL;
 802         }
 803         pll_div->n = Ndiv;
 804
 805         Nmod = target % source;
 806         Kpart = FIXED_PLL_SIZE * (u64)Nmod;
 807
 808         do_div(Kpart, source);
 809
 810         K = Kpart & 0xffffffff;
 811         if ((K % 10) >= 5)
 812                 K += 5;
 813         K /= 10;
 814         pll_div->k = K;
 815
 816         return 0;
 817 }
 818
 819 static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
 820                           int source, unsigned int freq_in,
 821                           unsigned int freq_out)
 822 {
 823         int ret;
 824         struct snd_soc_codec *codec;
 825         struct pll_div pll_div;
 826
 827         codec = dai->codec;
 828         if (!freq_in || !freq_out) {
 829                 /* disable the PLL */
 830                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 831                                     WM8985_PLLEN_MASK, 0);
 832         } else {
 833                 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
 834                 if (ret)
 835                         return ret;
 836
 837                 /* set PLLN and PRESCALE */
 838                 snd_soc_write(codec, WM8985_PLL_N,
 839                               (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
 840                               | pll_div.n);
 841                 /* set PLLK */
 842                 snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff);
 843                 snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
 844                 snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18));
 845                 /* set the source of the clock to be the PLL */
 846                 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 847                                     WM8985_CLKSEL_MASK, WM8985_CLKSEL);
 848                 /* enable the PLL */
 849                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 850                                     WM8985_PLLEN_MASK, WM8985_PLLEN);
 851         }
 852         return 0;
 853 }
 854
 855 static int wm8985_set_sysclk(struct snd_soc_dai *dai,
 856                              int clk_id, unsigned int freq, int dir)
 857 {
 858         struct snd_soc_codec *codec;
 859         struct wm8985_priv *wm8985;
 860
 861         codec = dai->codec;
 862         wm8985 = snd_soc_codec_get_drvdata(codec);
 863
 864         switch (clk_id) {
 865         case WM8985_CLKSRC_MCLK:
 866                 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 867                                     WM8985_CLKSEL_MASK, 0);
 868                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 869                                     WM8985_PLLEN_MASK, 0);
 870                 break;
 871         case WM8985_CLKSRC_PLL:
 872                 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
 873                                     WM8985_CLKSEL_MASK, WM8985_CLKSEL);
 874                 break;
 875         default:
 876                 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
 877                 return -EINVAL;
 878         }
 879
 880         wm8985->sysclk = freq;
 881         return 0;
 882 }
 883
 884 static int wm8985_set_bias_level(struct snd_soc_codec *codec,
 885                                  enum snd_soc_bias_level level)
 886 {
 887         int ret;
 888         struct wm8985_priv *wm8985;
 889
 890         wm8985 = snd_soc_codec_get_drvdata(codec);
 891         switch (level) {
 892         case SND_SOC_BIAS_ON:
 893         case SND_SOC_BIAS_PREPARE:
 894                 /* VMID at 75k */
 895                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 896                                     WM8985_VMIDSEL_MASK,
 897                                     1 << WM8985_VMIDSEL_SHIFT);
 898                 break;
 899         case SND_SOC_BIAS_STANDBY:
 900                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
 901                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
 902                                                     wm8985->supplies);
 903                         if (ret) {
 904                                 dev_err(codec->dev,
 905                                         "Failed to enable supplies: %d\n",
 906                                         ret);
 907                                 return ret;
 908                         }
 909
 910                         regcache_sync(wm8985->regmap);
 911
 912                         /* enable anti-pop features */
 913                         snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
 914                                             WM8985_POBCTRL_MASK,
 915                                             WM8985_POBCTRL);
 916                         /* enable thermal shutdown */
 917                         snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 918                                             WM8985_TSDEN_MASK, WM8985_TSDEN);
 919                         snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 920                                             WM8985_TSOPCTRL_MASK,
 921                                             WM8985_TSOPCTRL);
 922                         /* enable BIASEN */
 923                         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 924                                             WM8985_BIASEN_MASK, WM8985_BIASEN);
 925                         /* VMID at 75k */
 926                         snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 927                                             WM8985_VMIDSEL_MASK,
 928                                             1 << WM8985_VMIDSEL_SHIFT);
 929                         msleep(500);
 930                         /* disable anti-pop features */
 931                         snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
 932                                             WM8985_POBCTRL_MASK, 0);
 933                 }
 934                 /* VMID at 300k */
 935                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 936                                     WM8985_VMIDSEL_MASK,
 937                                     2 << WM8985_VMIDSEL_SHIFT);
 938                 break;
 939         case SND_SOC_BIAS_OFF:
 940                 /* disable thermal shutdown */
 941                 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 942                                     WM8985_TSOPCTRL_MASK, 0);
 943                 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
 944                                     WM8985_TSDEN_MASK, 0);
 945                 /* disable VMIDSEL and BIASEN */
 946                 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
 947                                     WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
 948                                     0);
 949                 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_1, 0);
 950                 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, 0);
 951                 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, 0);
 952
 953                 regcache_mark_dirty(wm8985->regmap);
 954
 955                 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
 956                                        wm8985->supplies);
 957                 break;
 958         }
 959
 960         return 0;
 961 }
 962
 963 static int wm8985_probe(struct snd_soc_codec *codec)
 964 {
 965         size_t i;
 966         struct wm8985_priv *wm8985;
 967         int ret;
 968
 969         wm8985 = snd_soc_codec_get_drvdata(codec);
 970
 971         for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
 972                 wm8985->supplies[i].supply = wm8985_supply_names[i];
 973
 974         ret = devm_regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8985->supplies),
 975                                  wm8985->supplies);
 976         if (ret) {
 977                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
 978                 return ret;
 979         }
 980
 981         ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
 982                                     wm8985->supplies);
 983         if (ret) {
 984                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
 985                 return ret;
 986         }
 987
 988         ret = wm8985_reset(codec);
 989         if (ret < 0) {
 990                 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
 991                 goto err_reg_enable;
 992         }
 993
 994         /* latch volume update bits */
 995         for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
 996                 snd_soc_update_bits(codec, volume_update_regs[i],
 997                                     0x100, 0x100);
 998         /* enable BIASCUT */
 999         snd_soc_update_bits(codec, WM8985_BIAS_CTRL, WM8985_BIASCUT,
1000                             WM8985_BIASCUT);
1001
1002         return 0;
1003
1004 err_reg_enable:
1005         regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
1006         return ret;
1007 }
1008
1009 static const struct snd_soc_dai_ops wm8985_dai_ops = {
1010         .digital_mute = wm8985_dac_mute,
1011         .hw_params = wm8985_hw_params,
1012         .set_fmt = wm8985_set_fmt,
1013         .set_sysclk = wm8985_set_sysclk,
1014         .set_pll = wm8985_set_pll
1015 };
1016
1017 #define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1018                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1019
1020 static struct snd_soc_dai_driver wm8985_dai = {
1021         .name = "wm8985-hifi",
1022         .playback = {
1023                 .stream_name = "Playback",
1024                 .channels_min = 2,
1025                 .channels_max = 2,
1026                 .rates = SNDRV_PCM_RATE_8000_48000,
1027                 .formats = WM8985_FORMATS,
1028         },
1029         .capture = {
1030                 .stream_name = "Capture",
1031                 .channels_min = 2,
1032                 .channels_max = 2,
1033                 .rates = SNDRV_PCM_RATE_8000_48000,
1034                 .formats = WM8985_FORMATS,
1035         },
1036         .ops = &wm8985_dai_ops,
1037         .symmetric_rates = 1
1038 };
1039
1040 static struct snd_soc_codec_driver soc_codec_dev_wm8985 = {
1041         .probe = wm8985_probe,
1042         .set_bias_level = wm8985_set_bias_level,
1043         .suspend_bias_off = true,
1044
1045         .controls = wm8985_snd_controls,
1046         .num_controls = ARRAY_SIZE(wm8985_snd_controls),
1047         .dapm_widgets = wm8985_dapm_widgets,
1048         .num_dapm_widgets = ARRAY_SIZE(wm8985_dapm_widgets),
1049         .dapm_routes = wm8985_dapm_routes,
1050         .num_dapm_routes = ARRAY_SIZE(wm8985_dapm_routes),
1051 };
1052
1053 static const struct regmap_config wm8985_regmap = {
1054         .reg_bits = 7,
1055         .val_bits = 9,
1056
1057         .max_register = WM8985_MAX_REGISTER,
1058         .writeable_reg = wm8985_writeable,
1059
1060         .cache_type = REGCACHE_RBTREE,
1061         .reg_defaults = wm8985_reg_defaults,
1062         .num_reg_defaults = ARRAY_SIZE(wm8985_reg_defaults),
1063 };
1064
1065 #if defined(CONFIG_SPI_MASTER)
1066 static int wm8985_spi_probe(struct spi_device *spi)
1067 {
1068         struct wm8985_priv *wm8985;
1069         int ret;
1070
1071         wm8985 = devm_kzalloc(&spi->dev, sizeof *wm8985, GFP_KERNEL);
1072         if (!wm8985)
1073                 return -ENOMEM;
1074
1075         spi_set_drvdata(spi, wm8985);
1076
1077         wm8985->regmap = devm_regmap_init_spi(spi, &wm8985_regmap);
1078         if (IS_ERR(wm8985->regmap)) {
1079                 ret = PTR_ERR(wm8985->regmap);
1080                 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1081                         ret);
1082                 return ret;
1083         }
1084
1085         ret = snd_soc_register_codec(&spi->dev,
1086                                      &soc_codec_dev_wm8985, &wm8985_dai, 1);
1087         return ret;
1088 }
1089
1090 static int wm8985_spi_remove(struct spi_device *spi)
1091 {
1092         snd_soc_unregister_codec(&spi->dev);
1093         return 0;
1094 }
1095
1096 static struct spi_driver wm8985_spi_driver = {
1097         .driver = {
1098                 .name = "wm8985",
1099         },
1100         .probe = wm8985_spi_probe,
1101         .remove = wm8985_spi_remove
1102 };
1103 #endif
1104
1105 #if IS_ENABLED(CONFIG_I2C)
1106 static int wm8985_i2c_probe(struct i2c_client *i2c,
1107                             const struct i2c_device_id *id)
1108 {
1109         struct wm8985_priv *wm8985;
1110         int ret;
1111
1112         wm8985 = devm_kzalloc(&i2c->dev, sizeof *wm8985, GFP_KERNEL);
1113         if (!wm8985)
1114                 return -ENOMEM;
1115
1116         i2c_set_clientdata(i2c, wm8985);
1117
1118         wm8985->regmap = devm_regmap_init_i2c(i2c, &wm8985_regmap);
1119         if (IS_ERR(wm8985->regmap)) {
1120                 ret = PTR_ERR(wm8985->regmap);
1121                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1122                         ret);
1123                 return ret;
1124         }
1125
1126         ret = snd_soc_register_codec(&i2c->dev,
1127                                      &soc_codec_dev_wm8985, &wm8985_dai, 1);
1128         return ret;
1129 }
1130
1131 static int wm8985_i2c_remove(struct i2c_client *i2c)
1132 {
1133         snd_soc_unregister_codec(&i2c->dev);
1134         return 0;
1135 }
1136
1137 static const struct i2c_device_id wm8985_i2c_id[] = {
1138         { "wm8985", 0 },
1139         { }
1140 };
1141 MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
1142
1143 static struct i2c_driver wm8985_i2c_driver = {
1144         .driver = {
1145                 .name = "wm8985",
1146         },
1147         .probe = wm8985_i2c_probe,
1148         .remove = wm8985_i2c_remove,
1149         .id_table = wm8985_i2c_id
1150 };
1151 #endif
1152
1153 static int __init wm8985_modinit(void)
1154 {
1155         int ret = 0;
1156
1157 #if IS_ENABLED(CONFIG_I2C)
1158         ret = i2c_add_driver(&wm8985_i2c_driver);
1159         if (ret) {
1160                 printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
1161                        ret);
1162         }
1163 #endif
1164 #if defined(CONFIG_SPI_MASTER)
1165         ret = spi_register_driver(&wm8985_spi_driver);
1166         if (ret != 0) {
1167                 printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
1168                        ret);
1169         }
1170 #endif
1171         return ret;
1172 }
1173 module_init(wm8985_modinit);
1174
1175 static void __exit wm8985_exit(void)
1176 {
1177 #if IS_ENABLED(CONFIG_I2C)
1178         i2c_del_driver(&wm8985_i2c_driver);
1179 #endif
1180 #if defined(CONFIG_SPI_MASTER)
1181         spi_unregister_driver(&wm8985_spi_driver);
1182 #endif
1183 }
1184 module_exit(wm8985_exit);
1185
1186 MODULE_DESCRIPTION("ASoC WM8985 driver");
1187 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1188 MODULE_LICENSE("GPL");