sound/soc/codecs/wm8993.c

   1 /*
   2  * wm8993.c -- WM8993 ALSA SoC audio driver
   3  *
   4  * Copyright 2009, 2010 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/pm.h>
  18 #include <linux/i2c.h>
  19 #include <linux/regmap.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/slab.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/tlv.h>
  27 #include <sound/soc.h>
  28 #include <sound/initval.h>
  29 #include <sound/wm8993.h>
  30
  31 #include "wm8993.h"
  32 #include "wm_hubs.h"
  33
  34 #define WM8993_NUM_SUPPLIES 6
  35 static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
  36         "DCVDD",
  37         "DBVDD",
  38         "AVDD1",
  39         "AVDD2",
  40         "CPVDD",
  41         "SPKVDD",
  42 };
  43
  44 static struct reg_default wm8993_reg_defaults[] = {
  45         { 1,   0x0000 },     /* R1   - Power Management (1) */
  46         { 2,   0x6000 },     /* R2   - Power Management (2) */
  47         { 3,   0x0000 },     /* R3   - Power Management (3) */
  48         { 4,   0x4050 },     /* R4   - Audio Interface (1) */
  49         { 5,   0x4000 },     /* R5   - Audio Interface (2) */
  50         { 6,   0x01C8 },     /* R6   - Clocking 1 */
  51         { 7,   0x0000 },     /* R7   - Clocking 2 */
  52         { 8,   0x0000 },     /* R8   - Audio Interface (3) */
  53         { 9,   0x0040 },     /* R9   - Audio Interface (4) */
  54         { 10,  0x0004 },     /* R10  - DAC CTRL */
  55         { 11,  0x00C0 },     /* R11  - Left DAC Digital Volume */
  56         { 12,  0x00C0 },     /* R12  - Right DAC Digital Volume */
  57         { 13,  0x0000 },     /* R13  - Digital Side Tone */
  58         { 14,  0x0300 },     /* R14  - ADC CTRL */
  59         { 15,  0x00C0 },     /* R15  - Left ADC Digital Volume */
  60         { 16,  0x00C0 },     /* R16  - Right ADC Digital Volume */
  61         { 18,  0x0000 },     /* R18  - GPIO CTRL 1 */
  62         { 19,  0x0010 },     /* R19  - GPIO1 */
  63         { 20,  0x0000 },     /* R20  - IRQ_DEBOUNCE */
  64         { 21,  0x8000 },     /* R22  - GPIOCTRL 2 */
  65         { 22,  0x0800 },     /* R23  - GPIO_POL */
  66         { 24,  0x008B },     /* R24  - Left Line Input 1&2 Volume */
  67         { 25,  0x008B },     /* R25  - Left Line Input 3&4 Volume */
  68         { 26,  0x008B },     /* R26  - Right Line Input 1&2 Volume */
  69         { 27,  0x008B },     /* R27  - Right Line Input 3&4 Volume */
  70         { 28,  0x006D },     /* R28  - Left Output Volume */
  71         { 29,  0x006D },     /* R29  - Right Output Volume */
  72         { 30,  0x0066 },     /* R30  - Line Outputs Volume */
  73         { 31,  0x0020 },     /* R31  - HPOUT2 Volume */
  74         { 32,  0x0079 },     /* R32  - Left OPGA Volume */
  75         { 33,  0x0079 },     /* R33  - Right OPGA Volume */
  76         { 34,  0x0003 },     /* R34  - SPKMIXL Attenuation */
  77         { 35,  0x0003 },     /* R35  - SPKMIXR Attenuation */
  78         { 36,  0x0011 },     /* R36  - SPKOUT Mixers */
  79         { 37,  0x0100 },     /* R37  - SPKOUT Boost */
  80         { 38,  0x0079 },     /* R38  - Speaker Volume Left */
  81         { 39,  0x0079 },     /* R39  - Speaker Volume Right */
  82         { 40,  0x0000 },     /* R40  - Input Mixer2 */
  83         { 41,  0x0000 },     /* R41  - Input Mixer3 */
  84         { 42,  0x0000 },     /* R42  - Input Mixer4 */
  85         { 43,  0x0000 },     /* R43  - Input Mixer5 */
  86         { 44,  0x0000 },     /* R44  - Input Mixer6 */
  87         { 45,  0x0000 },     /* R45  - Output Mixer1 */
  88         { 46,  0x0000 },     /* R46  - Output Mixer2 */
  89         { 47,  0x0000 },     /* R47  - Output Mixer3 */
  90         { 48,  0x0000 },     /* R48  - Output Mixer4 */
  91         { 49,  0x0000 },     /* R49  - Output Mixer5 */
  92         { 50,  0x0000 },     /* R50  - Output Mixer6 */
  93         { 51,  0x0000 },     /* R51  - HPOUT2 Mixer */
  94         { 52,  0x0000 },     /* R52  - Line Mixer1 */
  95         { 53,  0x0000 },     /* R53  - Line Mixer2 */
  96         { 54,  0x0000 },     /* R54  - Speaker Mixer */
  97         { 55,  0x0000 },     /* R55  - Additional Control */
  98         { 56,  0x0000 },     /* R56  - AntiPOP1 */
  99         { 57,  0x0000 },     /* R57  - AntiPOP2 */
 100         { 58,  0x0000 },     /* R58  - MICBIAS */
 101         { 60,  0x0000 },     /* R60  - FLL Control 1 */
 102         { 61,  0x0000 },     /* R61  - FLL Control 2 */
 103         { 62,  0x0000 },     /* R62  - FLL Control 3 */
 104         { 63,  0x2EE0 },     /* R63  - FLL Control 4 */
 105         { 64,  0x0002 },     /* R64  - FLL Control 5 */
 106         { 65,  0x2287 },     /* R65  - Clocking 3 */
 107         { 66,  0x025F },     /* R66  - Clocking 4 */
 108         { 67,  0x0000 },     /* R67  - MW Slave Control */
 109         { 69,  0x0002 },     /* R69  - Bus Control 1 */
 110         { 70,  0x0000 },     /* R70  - Write Sequencer 0 */
 111         { 71,  0x0000 },     /* R71  - Write Sequencer 1 */
 112         { 72,  0x0000 },     /* R72  - Write Sequencer 2 */
 113         { 73,  0x0000 },     /* R73  - Write Sequencer 3 */
 114         { 74,  0x0000 },     /* R74  - Write Sequencer 4 */
 115         { 75,  0x0000 },     /* R75  - Write Sequencer 5 */
 116         { 76,  0x1F25 },     /* R76  - Charge Pump 1 */
 117         { 81,  0x0000 },     /* R81  - Class W 0 */
 118         { 85,  0x054A },     /* R85  - DC Servo 1 */
 119         { 87,  0x0000 },     /* R87  - DC Servo 3 */
 120         { 96,  0x0100 },     /* R96  - Analogue HP 0 */
 121         { 98,  0x0000 },     /* R98  - EQ1 */
 122         { 99,  0x000C },     /* R99  - EQ2 */
 123         { 100, 0x000C },     /* R100 - EQ3 */
 124         { 101, 0x000C },     /* R101 - EQ4 */
 125         { 102, 0x000C },     /* R102 - EQ5 */
 126         { 103, 0x000C },     /* R103 - EQ6 */
 127         { 104, 0x0FCA },     /* R104 - EQ7 */
 128         { 105, 0x0400 },     /* R105 - EQ8 */
 129         { 106, 0x00D8 },     /* R106 - EQ9 */
 130         { 107, 0x1EB5 },     /* R107 - EQ10 */
 131         { 108, 0xF145 },     /* R108 - EQ11 */
 132         { 109, 0x0B75 },     /* R109 - EQ12 */
 133         { 110, 0x01C5 },     /* R110 - EQ13 */
 134         { 111, 0x1C58 },     /* R111 - EQ14 */
 135         { 112, 0xF373 },     /* R112 - EQ15 */
 136         { 113, 0x0A54 },     /* R113 - EQ16 */
 137         { 114, 0x0558 },     /* R114 - EQ17 */
 138         { 115, 0x168E },     /* R115 - EQ18 */
 139         { 116, 0xF829 },     /* R116 - EQ19 */
 140         { 117, 0x07AD },     /* R117 - EQ20 */
 141         { 118, 0x1103 },     /* R118 - EQ21 */
 142         { 119, 0x0564 },     /* R119 - EQ22 */
 143         { 120, 0x0559 },     /* R120 - EQ23 */
 144         { 121, 0x4000 },     /* R121 - EQ24 */
 145         { 122, 0x0000 },     /* R122 - Digital Pulls */
 146         { 123, 0x0F08 },     /* R123 - DRC Control 1 */
 147         { 124, 0x0000 },     /* R124 - DRC Control 2 */
 148         { 125, 0x0080 },     /* R125 - DRC Control 3 */
 149         { 126, 0x0000 },     /* R126 - DRC Control 4 */
 150 };
 151
 152 static struct {
 153         int ratio;
 154         int clk_sys_rate;
 155 } clk_sys_rates[] = {
 156         { 64,   0 },
 157         { 128,  1 },
 158         { 192,  2 },
 159         { 256,  3 },
 160         { 384,  4 },
 161         { 512,  5 },
 162         { 768,  6 },
 163         { 1024, 7 },
 164         { 1408, 8 },
 165         { 1536, 9 },
 166 };
 167
 168 static struct {
 169         int rate;
 170         int sample_rate;
 171 } sample_rates[] = {
 172         { 8000,  0  },
 173         { 11025, 1  },
 174         { 12000, 1  },
 175         { 16000, 2  },
 176         { 22050, 3  },
 177         { 24000, 3  },
 178         { 32000, 4  },
 179         { 44100, 5  },
 180         { 48000, 5  },
 181 };
 182
 183 static struct {
 184         int div; /* *10 due to .5s */
 185         int bclk_div;
 186 } bclk_divs[] = {
 187         { 10,  0  },
 188         { 15,  1  },
 189         { 20,  2  },
 190         { 30,  3  },
 191         { 40,  4  },
 192         { 55,  5  },
 193         { 60,  6  },
 194         { 80,  7  },
 195         { 110, 8  },
 196         { 120, 9  },
 197         { 160, 10 },
 198         { 220, 11 },
 199         { 240, 12 },
 200         { 320, 13 },
 201         { 440, 14 },
 202         { 480, 15 },
 203 };
 204
 205 struct wm8993_priv {
 206         struct wm_hubs_data hubs_data;
 207         struct device *dev;
 208         struct regmap *regmap;
 209         struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
 210         struct wm8993_platform_data pdata;
 211         struct completion fll_lock;
 212         int master;
 213         int sysclk_source;
 214         int tdm_slots;
 215         int tdm_width;
 216         unsigned int mclk_rate;
 217         unsigned int sysclk_rate;
 218         unsigned int fs;
 219         unsigned int bclk;
 220         int class_w_users;
 221         unsigned int fll_fref;
 222         unsigned int fll_fout;
 223         int fll_src;
 224 };
 225
 226 static bool wm8993_volatile(struct device *dev, unsigned int reg)
 227 {
 228         switch (reg) {
 229         case WM8993_SOFTWARE_RESET:
 230         case WM8993_GPIO_CTRL_1:
 231         case WM8993_DC_SERVO_0:
 232         case WM8993_DC_SERVO_READBACK_0:
 233         case WM8993_DC_SERVO_READBACK_1:
 234         case WM8993_DC_SERVO_READBACK_2:
 235                 return true;
 236         default:
 237                 return false;
 238         }
 239 }
 240
 241 static bool wm8993_readable(struct device *dev, unsigned int reg)
 242 {
 243         switch (reg) {
 244         case WM8993_SOFTWARE_RESET:
 245         case WM8993_POWER_MANAGEMENT_1:
 246         case WM8993_POWER_MANAGEMENT_2:
 247         case WM8993_POWER_MANAGEMENT_3:
 248         case WM8993_AUDIO_INTERFACE_1:
 249         case WM8993_AUDIO_INTERFACE_2:
 250         case WM8993_CLOCKING_1:
 251         case WM8993_CLOCKING_2:
 252         case WM8993_AUDIO_INTERFACE_3:
 253         case WM8993_AUDIO_INTERFACE_4:
 254         case WM8993_DAC_CTRL:
 255         case WM8993_LEFT_DAC_DIGITAL_VOLUME:
 256         case WM8993_RIGHT_DAC_DIGITAL_VOLUME:
 257         case WM8993_DIGITAL_SIDE_TONE:
 258         case WM8993_ADC_CTRL:
 259         case WM8993_LEFT_ADC_DIGITAL_VOLUME:
 260         case WM8993_RIGHT_ADC_DIGITAL_VOLUME:
 261         case WM8993_GPIO_CTRL_1:
 262         case WM8993_GPIO1:
 263         case WM8993_IRQ_DEBOUNCE:
 264         case WM8993_GPIOCTRL_2:
 265         case WM8993_GPIO_POL:
 266         case WM8993_LEFT_LINE_INPUT_1_2_VOLUME:
 267         case WM8993_LEFT_LINE_INPUT_3_4_VOLUME:
 268         case WM8993_RIGHT_LINE_INPUT_1_2_VOLUME:
 269         case WM8993_RIGHT_LINE_INPUT_3_4_VOLUME:
 270         case WM8993_LEFT_OUTPUT_VOLUME:
 271         case WM8993_RIGHT_OUTPUT_VOLUME:
 272         case WM8993_LINE_OUTPUTS_VOLUME:
 273         case WM8993_HPOUT2_VOLUME:
 274         case WM8993_LEFT_OPGA_VOLUME:
 275         case WM8993_RIGHT_OPGA_VOLUME:
 276         case WM8993_SPKMIXL_ATTENUATION:
 277         case WM8993_SPKMIXR_ATTENUATION:
 278         case WM8993_SPKOUT_MIXERS:
 279         case WM8993_SPKOUT_BOOST:
 280         case WM8993_SPEAKER_VOLUME_LEFT:
 281         case WM8993_SPEAKER_VOLUME_RIGHT:
 282         case WM8993_INPUT_MIXER2:
 283         case WM8993_INPUT_MIXER3:
 284         case WM8993_INPUT_MIXER4:
 285         case WM8993_INPUT_MIXER5:
 286         case WM8993_INPUT_MIXER6:
 287         case WM8993_OUTPUT_MIXER1:
 288         case WM8993_OUTPUT_MIXER2:
 289         case WM8993_OUTPUT_MIXER3:
 290         case WM8993_OUTPUT_MIXER4:
 291         case WM8993_OUTPUT_MIXER5:
 292         case WM8993_OUTPUT_MIXER6:
 293         case WM8993_HPOUT2_MIXER:
 294         case WM8993_LINE_MIXER1:
 295         case WM8993_LINE_MIXER2:
 296         case WM8993_SPEAKER_MIXER:
 297         case WM8993_ADDITIONAL_CONTROL:
 298         case WM8993_ANTIPOP1:
 299         case WM8993_ANTIPOP2:
 300         case WM8993_MICBIAS:
 301         case WM8993_FLL_CONTROL_1:
 302         case WM8993_FLL_CONTROL_2:
 303         case WM8993_FLL_CONTROL_3:
 304         case WM8993_FLL_CONTROL_4:
 305         case WM8993_FLL_CONTROL_5:
 306         case WM8993_CLOCKING_3:
 307         case WM8993_CLOCKING_4:
 308         case WM8993_MW_SLAVE_CONTROL:
 309         case WM8993_BUS_CONTROL_1:
 310         case WM8993_WRITE_SEQUENCER_0:
 311         case WM8993_WRITE_SEQUENCER_1:
 312         case WM8993_WRITE_SEQUENCER_2:
 313         case WM8993_WRITE_SEQUENCER_3:
 314         case WM8993_WRITE_SEQUENCER_4:
 315         case WM8993_WRITE_SEQUENCER_5:
 316         case WM8993_CHARGE_PUMP_1:
 317         case WM8993_CLASS_W_0:
 318         case WM8993_DC_SERVO_0:
 319         case WM8993_DC_SERVO_1:
 320         case WM8993_DC_SERVO_3:
 321         case WM8993_DC_SERVO_READBACK_0:
 322         case WM8993_DC_SERVO_READBACK_1:
 323         case WM8993_DC_SERVO_READBACK_2:
 324         case WM8993_ANALOGUE_HP_0:
 325         case WM8993_EQ1:
 326         case WM8993_EQ2:
 327         case WM8993_EQ3:
 328         case WM8993_EQ4:
 329         case WM8993_EQ5:
 330         case WM8993_EQ6:
 331         case WM8993_EQ7:
 332         case WM8993_EQ8:
 333         case WM8993_EQ9:
 334         case WM8993_EQ10:
 335         case WM8993_EQ11:
 336         case WM8993_EQ12:
 337         case WM8993_EQ13:
 338         case WM8993_EQ14:
 339         case WM8993_EQ15:
 340         case WM8993_EQ16:
 341         case WM8993_EQ17:
 342         case WM8993_EQ18:
 343         case WM8993_EQ19:
 344         case WM8993_EQ20:
 345         case WM8993_EQ21:
 346         case WM8993_EQ22:
 347         case WM8993_EQ23:
 348         case WM8993_EQ24:
 349         case WM8993_DIGITAL_PULLS:
 350         case WM8993_DRC_CONTROL_1:
 351         case WM8993_DRC_CONTROL_2:
 352         case WM8993_DRC_CONTROL_3:
 353         case WM8993_DRC_CONTROL_4:
 354                 return true;
 355         default:
 356                 return false;
 357         }
 358 }
 359
 360 struct _fll_div {
 361         u16 fll_fratio;
 362         u16 fll_outdiv;
 363         u16 fll_clk_ref_div;
 364         u16 n;
 365         u16 k;
 366 };
 367
 368 /* The size in bits of the FLL divide multiplied by 10
 369  * to allow rounding later */
 370 #define FIXED_FLL_SIZE ((1 << 16) * 10)
 371
 372 static struct {
 373         unsigned int min;
 374         unsigned int max;
 375         u16 fll_fratio;
 376         int ratio;
 377 } fll_fratios[] = {
 378         {       0,    64000, 4, 16 },
 379         {   64000,   128000, 3,  8 },
 380         {  128000,   256000, 2,  4 },
 381         {  256000,  1000000, 1,  2 },
 382         { 1000000, 13500000, 0,  1 },
 383 };
 384
 385 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
 386                        unsigned int Fout)
 387 {
 388         u64 Kpart;
 389         unsigned int K, Ndiv, Nmod, target;
 390         unsigned int div;
 391         int i;
 392
 393         /* Fref must be <=13.5MHz */
 394         div = 1;
 395         fll_div->fll_clk_ref_div = 0;
 396         while ((Fref / div) > 13500000) {
 397                 div *= 2;
 398                 fll_div->fll_clk_ref_div++;
 399
 400                 if (div > 8) {
 401                         pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
 402                                Fref);
 403                         return -EINVAL;
 404                 }
 405         }
 406
 407         pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
 408
 409         /* Apply the division for our remaining calculations */
 410         Fref /= div;
 411
 412         /* Fvco should be 90-100MHz; don't check the upper bound */
 413         div = 0;
 414         target = Fout * 2;
 415         while (target < 90000000) {
 416                 div++;
 417                 target *= 2;
 418                 if (div > 7) {
 419                         pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
 420                                Fout);
 421                         return -EINVAL;
 422                 }
 423         }
 424         fll_div->fll_outdiv = div;
 425
 426         pr_debug("Fvco=%dHz\n", target);
 427
 428         /* Find an appropriate FLL_FRATIO and factor it out of the target */
 429         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
 430                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
 431                         fll_div->fll_fratio = fll_fratios[i].fll_fratio;
 432                         target /= fll_fratios[i].ratio;
 433                         break;
 434                 }
 435         }
 436         if (i == ARRAY_SIZE(fll_fratios)) {
 437                 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
 438                 return -EINVAL;
 439         }
 440
 441         /* Now, calculate N.K */
 442         Ndiv = target / Fref;
 443
 444         fll_div->n = Ndiv;
 445         Nmod = target % Fref;
 446         pr_debug("Nmod=%d\n", Nmod);
 447
 448         /* Calculate fractional part - scale up so we can round. */
 449         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
 450
 451         do_div(Kpart, Fref);
 452
 453         K = Kpart & 0xFFFFFFFF;
 454
 455         if ((K % 10) >= 5)
 456                 K += 5;
 457
 458         /* Move down to proper range now rounding is done */
 459         fll_div->k = K / 10;
 460
 461         pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
 462                  fll_div->n, fll_div->k,
 463                  fll_div->fll_fratio, fll_div->fll_outdiv,
 464                  fll_div->fll_clk_ref_div);
 465
 466         return 0;
 467 }
 468
 469 static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
 470                           unsigned int Fref, unsigned int Fout)
 471 {
 472         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
 473         struct i2c_client *i2c = to_i2c_client(codec->dev);
 474         u16 reg1, reg4, reg5;
 475         struct _fll_div fll_div;
 476         unsigned int timeout;
 477         int ret;
 478
 479         /* Any change? */
 480         if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
 481                 return 0;
 482
 483         /* Disable the FLL */
 484         if (Fout == 0) {
 485                 dev_dbg(codec->dev, "FLL disabled\n");
 486                 wm8993->fll_fref = 0;
 487                 wm8993->fll_fout = 0;
 488
 489                 reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
 490                 reg1 &= ~WM8993_FLL_ENA;
 491                 snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
 492
 493                 return 0;
 494         }
 495
 496         ret = fll_factors(&fll_div, Fref, Fout);
 497         if (ret != 0)
 498                 return ret;
 499
 500         reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5);
 501         reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
 502
 503         switch (fll_id) {
 504         case WM8993_FLL_MCLK:
 505                 break;
 506
 507         case WM8993_FLL_LRCLK:
 508                 reg5 |= 1;
 509                 break;
 510
 511         case WM8993_FLL_BCLK:
 512                 reg5 |= 2;
 513                 break;
 514
 515         default:
 516                 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
 517                 return -EINVAL;
 518         }
 519
 520         /* Any FLL configuration change requires that the FLL be
 521          * disabled first. */
 522         reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1);
 523         reg1 &= ~WM8993_FLL_ENA;
 524         snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
 525
 526         /* Apply the configuration */
 527         if (fll_div.k)
 528                 reg1 |= WM8993_FLL_FRAC_MASK;
 529         else
 530                 reg1 &= ~WM8993_FLL_FRAC_MASK;
 531         snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1);
 532
 533         snd_soc_write(codec, WM8993_FLL_CONTROL_2,
 534                       (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
 535                       (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
 536         snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k);
 537
 538         reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4);
 539         reg4 &= ~WM8993_FLL_N_MASK;
 540         reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
 541         snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4);
 542
 543         reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
 544         reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
 545         snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5);
 546
 547         /* If we've got an interrupt wired up make sure we get it */
 548         if (i2c->irq)
 549                 timeout = msecs_to_jiffies(20);
 550         else if (Fref < 1000000)
 551                 timeout = msecs_to_jiffies(3);
 552         else
 553                 timeout = msecs_to_jiffies(1);
 554
 555         try_wait_for_completion(&wm8993->fll_lock);
 556
 557         /* Enable the FLL */
 558         snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
 559
 560         timeout = wait_for_completion_timeout(&wm8993->fll_lock, timeout);
 561         if (i2c->irq && !timeout)
 562                 dev_warn(codec->dev, "Timed out waiting for FLL\n");
 563
 564         dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
 565
 566         wm8993->fll_fref = Fref;
 567         wm8993->fll_fout = Fout;
 568         wm8993->fll_src = source;
 569
 570         return 0;
 571 }
 572
 573 static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
 574                           unsigned int Fref, unsigned int Fout)
 575 {
 576         return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout);
 577 }
 578
 579 static int configure_clock(struct snd_soc_codec *codec)
 580 {
 581         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
 582         unsigned int reg;
 583
 584         /* This should be done on init() for bypass paths */
 585         switch (wm8993->sysclk_source) {
 586         case WM8993_SYSCLK_MCLK:
 587                 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
 588
 589                 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
 590                 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
 591                 if (wm8993->mclk_rate > 13500000) {
 592                         reg |= WM8993_MCLK_DIV;
 593                         wm8993->sysclk_rate = wm8993->mclk_rate / 2;
 594                 } else {
 595                         reg &= ~WM8993_MCLK_DIV;
 596                         wm8993->sysclk_rate = wm8993->mclk_rate;
 597                 }
 598                 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
 599                 break;
 600
 601         case WM8993_SYSCLK_FLL:
 602                 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
 603                         wm8993->fll_fout);
 604
 605                 reg = snd_soc_read(codec, WM8993_CLOCKING_2);
 606                 reg |= WM8993_SYSCLK_SRC;
 607                 if (wm8993->fll_fout > 13500000) {
 608                         reg |= WM8993_MCLK_DIV;
 609                         wm8993->sysclk_rate = wm8993->fll_fout / 2;
 610                 } else {
 611                         reg &= ~WM8993_MCLK_DIV;
 612                         wm8993->sysclk_rate = wm8993->fll_fout;
 613                 }
 614                 snd_soc_write(codec, WM8993_CLOCKING_2, reg);
 615                 break;
 616
 617         default:
 618                 dev_err(codec->dev, "System clock not configured\n");
 619                 return -EINVAL;
 620         }
 621
 622         dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
 623
 624         return 0;
 625 }
 626
 627 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
 628 static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
 629 static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
 630 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
 631 static const unsigned int drc_max_tlv[] = {
 632         TLV_DB_RANGE_HEAD(2),
 633         0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
 634         3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
 635 };
 636 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
 637 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
 638 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 639 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 640 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
 641
 642 static const char *dac_deemph_text[] = {
 643         "None",
 644         "32kHz",
 645         "44.1kHz",
 646         "48kHz",
 647 };
 648
 649 static const struct soc_enum dac_deemph =
 650         SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text);
 651
 652 static const char *adc_hpf_text[] = {
 653         "Hi-Fi",
 654         "Voice 1",
 655         "Voice 2",
 656         "Voice 3",
 657 };
 658
 659 static const struct soc_enum adc_hpf =
 660         SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text);
 661
 662 static const char *drc_path_text[] = {
 663         "ADC",
 664         "DAC"
 665 };
 666
 667 static const struct soc_enum drc_path =
 668         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text);
 669
 670 static const char *drc_r0_text[] = {
 671         "1",
 672         "1/2",
 673         "1/4",
 674         "1/8",
 675         "1/16",
 676         "0",
 677 };
 678
 679 static const struct soc_enum drc_r0 =
 680         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text);
 681
 682 static const char *drc_r1_text[] = {
 683         "1",
 684         "1/2",
 685         "1/4",
 686         "1/8",
 687         "0",
 688 };
 689
 690 static const struct soc_enum drc_r1 =
 691         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text);
 692
 693 static const char *drc_attack_text[] = {
 694         "Reserved",
 695         "181us",
 696         "363us",
 697         "726us",
 698         "1.45ms",
 699         "2.9ms",
 700         "5.8ms",
 701         "11.6ms",
 702         "23.2ms",
 703         "46.4ms",
 704         "92.8ms",
 705         "185.6ms",
 706 };
 707
 708 static const struct soc_enum drc_attack =
 709         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text);
 710
 711 static const char *drc_decay_text[] = {
 712         "186ms",
 713         "372ms",
 714         "743ms",
 715         "1.49s",
 716         "2.97ms",
 717         "5.94ms",
 718         "11.89ms",
 719         "23.78ms",
 720         "47.56ms",
 721 };
 722
 723 static const struct soc_enum drc_decay =
 724         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text);
 725
 726 static const char *drc_ff_text[] = {
 727         "5 samples",
 728         "9 samples",
 729 };
 730
 731 static const struct soc_enum drc_ff =
 732         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text);
 733
 734 static const char *drc_qr_rate_text[] = {
 735         "0.725ms",
 736         "1.45ms",
 737         "5.8ms",
 738 };
 739
 740 static const struct soc_enum drc_qr_rate =
 741         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text);
 742
 743 static const char *drc_smooth_text[] = {
 744         "Low",
 745         "Medium",
 746         "High",
 747 };
 748
 749 static const struct soc_enum drc_smooth =
 750         SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text);
 751
 752 static const struct snd_kcontrol_new wm8993_snd_controls[] = {
 753 SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
 754                5, 9, 12, 0, sidetone_tlv),
 755
 756 SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
 757 SOC_ENUM("DRC Path", drc_path),
 758 SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
 759                2, 60, 1, drc_comp_threash),
 760 SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
 761                11, 30, 1, drc_comp_amp),
 762 SOC_ENUM("DRC R0", drc_r0),
 763 SOC_ENUM("DRC R1", drc_r1),
 764 SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
 765                drc_min_tlv),
 766 SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
 767                drc_max_tlv),
 768 SOC_ENUM("DRC Attack Rate", drc_attack),
 769 SOC_ENUM("DRC Decay Rate", drc_decay),
 770 SOC_ENUM("DRC FF Delay", drc_ff),
 771 SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
 772 SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
 773 SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
 774                drc_qr_tlv),
 775 SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
 776 SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
 777 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
 778 SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
 779 SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
 780                drc_startup_tlv),
 781
 782 SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
 783
 784 SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
 785                  WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
 786 SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
 787 SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
 788
 789 SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
 790                  WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
 791 SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
 792                dac_boost_tlv),
 793 SOC_ENUM("DAC Deemphasis", dac_deemph),
 794
 795 SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
 796                2, 1, 1, wm_hubs_spkmix_tlv),
 797
 798 SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
 799                2, 1, 1, wm_hubs_spkmix_tlv),
 800 };
 801
 802 static const struct snd_kcontrol_new wm8993_eq_controls[] = {
 803 SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
 804 SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
 805 SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
 806 SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
 807 SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
 808 };
 809
 810 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 811                          struct snd_kcontrol *kcontrol, int event)
 812 {
 813         struct snd_soc_codec *codec = w->codec;
 814
 815         switch (event) {
 816         case SND_SOC_DAPM_PRE_PMU:
 817                 return configure_clock(codec);
 818
 819         case SND_SOC_DAPM_POST_PMD:
 820                 break;
 821         }
 822
 823         return 0;
 824 }
 825
 826 /*
 827  * When used with DAC outputs only the WM8993 charge pump supports
 828  * operation in class W mode, providing very low power consumption
 829  * when used with digital sources.  Enable and disable this mode
 830  * automatically depending on the mixer configuration.
 831  *
 832  * Currently the only supported paths are the direct DAC->headphone
 833  * paths (which provide minimum power consumption anyway).
 834  */
 835 static int class_w_put(struct snd_kcontrol *kcontrol,
 836                        struct snd_ctl_elem_value *ucontrol)
 837 {
 838         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
 839         struct snd_soc_dapm_widget *widget = wlist->widgets[0];
 840         struct snd_soc_codec *codec = widget->codec;
 841         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
 842         int ret;
 843
 844         /* Turn it off if we're using the main output mixer */
 845         if (ucontrol->value.integer.value[0] == 0) {
 846                 if (wm8993->class_w_users == 0) {
 847                         dev_dbg(codec->dev, "Disabling Class W\n");
 848                         snd_soc_update_bits(codec, WM8993_CLASS_W_0,
 849                                             WM8993_CP_DYN_FREQ |
 850                                             WM8993_CP_DYN_V,
 851                                             0);
 852                 }
 853                 wm8993->class_w_users++;
 854                 wm8993->hubs_data.class_w = true;
 855         }
 856
 857         /* Implement the change */
 858         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
 859
 860         /* Enable it if we're using the direct DAC path */
 861         if (ucontrol->value.integer.value[0] == 1) {
 862                 if (wm8993->class_w_users == 1) {
 863                         dev_dbg(codec->dev, "Enabling Class W\n");
 864                         snd_soc_update_bits(codec, WM8993_CLASS_W_0,
 865                                             WM8993_CP_DYN_FREQ |
 866                                             WM8993_CP_DYN_V,
 867                                             WM8993_CP_DYN_FREQ |
 868                                             WM8993_CP_DYN_V);
 869                 }
 870                 wm8993->class_w_users--;
 871                 wm8993->hubs_data.class_w = false;
 872         }
 873
 874         dev_dbg(codec->dev, "Indirect DAC use count now %d\n",
 875                 wm8993->class_w_users);
 876
 877         return ret;
 878 }
 879
 880 #define SOC_DAPM_ENUM_W(xname, xenum) \
 881 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 882         .info = snd_soc_info_enum_double, \
 883         .get = snd_soc_dapm_get_enum_double, \
 884         .put = class_w_put, \
 885         .private_value = (unsigned long)&xenum }
 886
 887 static const char *hp_mux_text[] = {
 888         "Mixer",
 889         "DAC",
 890 };
 891
 892 static const struct soc_enum hpl_enum =
 893         SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text);
 894
 895 static const struct snd_kcontrol_new hpl_mux =
 896         SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum);
 897
 898 static const struct soc_enum hpr_enum =
 899         SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text);
 900
 901 static const struct snd_kcontrol_new hpr_mux =
 902         SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum);
 903
 904 static const struct snd_kcontrol_new left_speaker_mixer[] = {
 905 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
 906 SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
 907 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
 908 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
 909 };
 910
 911 static const struct snd_kcontrol_new right_speaker_mixer[] = {
 912 SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
 913 SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
 914 SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
 915 SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
 916 };
 917
 918 static const char *aif_text[] = {
 919         "Left", "Right"
 920 };
 921
 922 static const struct soc_enum aifoutl_enum =
 923         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text);
 924
 925 static const struct snd_kcontrol_new aifoutl_mux =
 926         SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
 927
 928 static const struct soc_enum aifoutr_enum =
 929         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text);
 930
 931 static const struct snd_kcontrol_new aifoutr_mux =
 932         SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
 933
 934 static const struct soc_enum aifinl_enum =
 935         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text);
 936
 937 static const struct snd_kcontrol_new aifinl_mux =
 938         SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
 939
 940 static const struct soc_enum aifinr_enum =
 941         SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text);
 942
 943 static const struct snd_kcontrol_new aifinr_mux =
 944         SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
 945
 946 static const char *sidetone_text[] = {
 947         "None", "Left", "Right"
 948 };
 949
 950 static const struct soc_enum sidetonel_enum =
 951         SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text);
 952
 953 static const struct snd_kcontrol_new sidetonel_mux =
 954         SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
 955
 956 static const struct soc_enum sidetoner_enum =
 957         SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text);
 958
 959 static const struct snd_kcontrol_new sidetoner_mux =
 960         SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
 961
 962 static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
 963 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
 964                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 965 SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
 966 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
 967 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
 968
 969 SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
 970 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
 971
 972 SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
 973 SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
 974
 975 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
 976 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
 977
 978 SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
 979 SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
 980
 981 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
 982 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
 983
 984 SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
 985 SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
 986
 987 SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
 988 SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
 989
 990 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
 991 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
 992
 993 SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
 994                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
 995 SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
 996                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
 997 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
 998 };
 999
1000 static const struct snd_soc_dapm_route routes[] = {
1001         { "MICBIAS1", NULL, "VMID" },
1002         { "MICBIAS2", NULL, "VMID" },
1003
1004         { "ADCL", NULL, "CLK_SYS" },
1005         { "ADCL", NULL, "CLK_DSP" },
1006         { "ADCR", NULL, "CLK_SYS" },
1007         { "ADCR", NULL, "CLK_DSP" },
1008
1009         { "AIFOUTL Mux", "Left", "ADCL" },
1010         { "AIFOUTL Mux", "Right", "ADCR" },
1011         { "AIFOUTR Mux", "Left", "ADCL" },
1012         { "AIFOUTR Mux", "Right", "ADCR" },
1013
1014         { "AIFOUTL", NULL, "AIFOUTL Mux" },
1015         { "AIFOUTR", NULL, "AIFOUTR Mux" },
1016
1017         { "DACL Mux", "Left", "AIFINL" },
1018         { "DACL Mux", "Right", "AIFINR" },
1019         { "DACR Mux", "Left", "AIFINL" },
1020         { "DACR Mux", "Right", "AIFINR" },
1021
1022         { "DACL Sidetone", "Left", "ADCL" },
1023         { "DACL Sidetone", "Right", "ADCR" },
1024         { "DACR Sidetone", "Left", "ADCL" },
1025         { "DACR Sidetone", "Right", "ADCR" },
1026
1027         { "DACL", NULL, "CLK_SYS" },
1028         { "DACL", NULL, "CLK_DSP" },
1029         { "DACL", NULL, "DACL Mux" },
1030         { "DACL", NULL, "DACL Sidetone" },
1031         { "DACR", NULL, "CLK_SYS" },
1032         { "DACR", NULL, "CLK_DSP" },
1033         { "DACR", NULL, "DACR Mux" },
1034         { "DACR", NULL, "DACR Sidetone" },
1035
1036         { "Left Output Mixer", "DAC Switch", "DACL" },
1037
1038         { "Right Output Mixer", "DAC Switch", "DACR" },
1039
1040         { "Left Output PGA", NULL, "CLK_SYS" },
1041
1042         { "Right Output PGA", NULL, "CLK_SYS" },
1043
1044         { "SPKL", "DAC Switch", "DACL" },
1045         { "SPKL", NULL, "CLK_SYS" },
1046
1047         { "SPKR", "DAC Switch", "DACR" },
1048         { "SPKR", NULL, "CLK_SYS" },
1049
1050         { "Left Headphone Mux", "DAC", "DACL" },
1051         { "Right Headphone Mux", "DAC", "DACR" },
1052 };
1053
1054 static int wm8993_set_bias_level(struct snd_soc_codec *codec,
1055                                  enum snd_soc_bias_level level)
1056 {
1057         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1058         int ret;
1059
1060         switch (level) {
1061         case SND_SOC_BIAS_ON:
1062         case SND_SOC_BIAS_PREPARE:
1063                 /* VMID=2*40k */
1064                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1065                                     WM8993_VMID_SEL_MASK, 0x2);
1066                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1067                                     WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
1068                 break;
1069
1070         case SND_SOC_BIAS_STANDBY:
1071                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1072                         ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1073                                                     wm8993->supplies);
1074                         if (ret != 0)
1075                                 return ret;
1076
1077                         regcache_cache_only(wm8993->regmap, false);
1078                         regcache_sync(wm8993->regmap);
1079
1080                         /* Bring up VMID with fast soft start */
1081                         snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1082                                             WM8993_STARTUP_BIAS_ENA |
1083                                             WM8993_VMID_BUF_ENA |
1084                                             WM8993_VMID_RAMP_MASK |
1085                                             WM8993_BIAS_SRC,
1086                                             WM8993_STARTUP_BIAS_ENA |
1087                                             WM8993_VMID_BUF_ENA |
1088                                             WM8993_VMID_RAMP_MASK |
1089                                             WM8993_BIAS_SRC);
1090
1091                         /* If either line output is single ended we
1092                          * need the VMID buffer */
1093                         if (!wm8993->pdata.lineout1_diff ||
1094                             !wm8993->pdata.lineout2_diff)
1095                                 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1096                                                  WM8993_LINEOUT_VMID_BUF_ENA,
1097                                                  WM8993_LINEOUT_VMID_BUF_ENA);
1098
1099                         /* VMID=2*40k */
1100                         snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1101                                             WM8993_VMID_SEL_MASK |
1102                                             WM8993_BIAS_ENA,
1103                                             WM8993_BIAS_ENA | 0x2);
1104                         msleep(32);
1105
1106                         /* Switch to normal bias */
1107                         snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1108                                             WM8993_BIAS_SRC |
1109                                             WM8993_STARTUP_BIAS_ENA, 0);
1110                 }
1111
1112                 /* VMID=2*240k */
1113                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1114                                     WM8993_VMID_SEL_MASK, 0x4);
1115
1116                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2,
1117                                     WM8993_TSHUT_ENA, 0);
1118                 break;
1119
1120         case SND_SOC_BIAS_OFF:
1121                 snd_soc_update_bits(codec, WM8993_ANTIPOP1,
1122                                     WM8993_LINEOUT_VMID_BUF_ENA, 0);
1123
1124                 snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1,
1125                                     WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1126                                     0);
1127
1128                 snd_soc_update_bits(codec, WM8993_ANTIPOP2,
1129                                     WM8993_STARTUP_BIAS_ENA |
1130                                     WM8993_VMID_BUF_ENA |
1131                                     WM8993_VMID_RAMP_MASK |
1132                                     WM8993_BIAS_SRC, 0);
1133
1134                 regcache_cache_only(wm8993->regmap, true);
1135                 regcache_mark_dirty(wm8993->regmap);
1136
1137                 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
1138                                        wm8993->supplies);
1139                 break;
1140         }
1141
1142         codec->dapm.bias_level = level;
1143
1144         return 0;
1145 }
1146
1147 static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1148                              int clk_id, unsigned int freq, int dir)
1149 {
1150         struct snd_soc_codec *codec = codec_dai->codec;
1151         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1152
1153         switch (clk_id) {
1154         case WM8993_SYSCLK_MCLK:
1155                 wm8993->mclk_rate = freq;
1156         case WM8993_SYSCLK_FLL:
1157                 wm8993->sysclk_source = clk_id;
1158                 break;
1159
1160         default:
1161                 return -EINVAL;
1162         }
1163
1164         return 0;
1165 }
1166
1167 static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1168                               unsigned int fmt)
1169 {
1170         struct snd_soc_codec *codec = dai->codec;
1171         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1172         unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1173         unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1174
1175         aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1176                   WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1177         aif4 &= ~WM8993_LRCLK_DIR;
1178
1179         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1180         case SND_SOC_DAIFMT_CBS_CFS:
1181                 wm8993->master = 0;
1182                 break;
1183         case SND_SOC_DAIFMT_CBS_CFM:
1184                 aif4 |= WM8993_LRCLK_DIR;
1185                 wm8993->master = 1;
1186                 break;
1187         case SND_SOC_DAIFMT_CBM_CFS:
1188                 aif1 |= WM8993_BCLK_DIR;
1189                 wm8993->master = 1;
1190                 break;
1191         case SND_SOC_DAIFMT_CBM_CFM:
1192                 aif1 |= WM8993_BCLK_DIR;
1193                 aif4 |= WM8993_LRCLK_DIR;
1194                 wm8993->master = 1;
1195                 break;
1196         default:
1197                 return -EINVAL;
1198         }
1199
1200         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1201         case SND_SOC_DAIFMT_DSP_B:
1202                 aif1 |= WM8993_AIF_LRCLK_INV;
1203         case SND_SOC_DAIFMT_DSP_A:
1204                 aif1 |= 0x18;
1205                 break;
1206         case SND_SOC_DAIFMT_I2S:
1207                 aif1 |= 0x10;
1208                 break;
1209         case SND_SOC_DAIFMT_RIGHT_J:
1210                 break;
1211         case SND_SOC_DAIFMT_LEFT_J:
1212                 aif1 |= 0x8;
1213                 break;
1214         default:
1215                 return -EINVAL;
1216         }
1217
1218         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1219         case SND_SOC_DAIFMT_DSP_A:
1220         case SND_SOC_DAIFMT_DSP_B:
1221                 /* frame inversion not valid for DSP modes */
1222                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1223                 case SND_SOC_DAIFMT_NB_NF:
1224                         break;
1225                 case SND_SOC_DAIFMT_IB_NF:
1226                         aif1 |= WM8993_AIF_BCLK_INV;
1227                         break;
1228                 default:
1229                         return -EINVAL;
1230                 }
1231                 break;
1232
1233         case SND_SOC_DAIFMT_I2S:
1234         case SND_SOC_DAIFMT_RIGHT_J:
1235         case SND_SOC_DAIFMT_LEFT_J:
1236                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1237                 case SND_SOC_DAIFMT_NB_NF:
1238                         break;
1239                 case SND_SOC_DAIFMT_IB_IF:
1240                         aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1241                         break;
1242                 case SND_SOC_DAIFMT_IB_NF:
1243                         aif1 |= WM8993_AIF_BCLK_INV;
1244                         break;
1245                 case SND_SOC_DAIFMT_NB_IF:
1246                         aif1 |= WM8993_AIF_LRCLK_INV;
1247                         break;
1248                 default:
1249                         return -EINVAL;
1250                 }
1251                 break;
1252         default:
1253                 return -EINVAL;
1254         }
1255
1256         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1257         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1258
1259         return 0;
1260 }
1261
1262 static int wm8993_hw_params(struct snd_pcm_substream *substream,
1263                             struct snd_pcm_hw_params *params,
1264                             struct snd_soc_dai *dai)
1265 {
1266         struct snd_soc_codec *codec = dai->codec;
1267         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1268         int ret, i, best, best_val, cur_val;
1269         unsigned int clocking1, clocking3, aif1, aif4;
1270
1271         clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1);
1272         clocking1 &= ~WM8993_BCLK_DIV_MASK;
1273
1274         clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3);
1275         clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1276
1277         aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1);
1278         aif1 &= ~WM8993_AIF_WL_MASK;
1279
1280         aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4);
1281         aif4 &= ~WM8993_LRCLK_RATE_MASK;
1282
1283         /* What BCLK do we need? */
1284         wm8993->fs = params_rate(params);
1285         wm8993->bclk = 2 * wm8993->fs;
1286         if (wm8993->tdm_slots) {
1287                 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1288                         wm8993->tdm_slots, wm8993->tdm_width);
1289                 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1290         } else {
1291                 switch (params_format(params)) {
1292                 case SNDRV_PCM_FORMAT_S16_LE:
1293                         wm8993->bclk *= 16;
1294                         break;
1295                 case SNDRV_PCM_FORMAT_S20_3LE:
1296                         wm8993->bclk *= 20;
1297                         aif1 |= 0x8;
1298                         break;
1299                 case SNDRV_PCM_FORMAT_S24_LE:
1300                         wm8993->bclk *= 24;
1301                         aif1 |= 0x10;
1302                         break;
1303                 case SNDRV_PCM_FORMAT_S32_LE:
1304                         wm8993->bclk *= 32;
1305                         aif1 |= 0x18;
1306                         break;
1307                 default:
1308                         return -EINVAL;
1309                 }
1310         }
1311
1312         dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1313
1314         ret = configure_clock(codec);
1315         if (ret != 0)
1316                 return ret;
1317
1318         /* Select nearest CLK_SYS_RATE */
1319         best = 0;
1320         best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1321                        - wm8993->fs);
1322         for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1323                 cur_val = abs((wm8993->sysclk_rate /
1324                                clk_sys_rates[i].ratio) - wm8993->fs);
1325                 if (cur_val < best_val) {
1326                         best = i;
1327                         best_val = cur_val;
1328                 }
1329         }
1330         dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1331                 clk_sys_rates[best].ratio);
1332         clocking3 |= (clk_sys_rates[best].clk_sys_rate
1333                       << WM8993_CLK_SYS_RATE_SHIFT);
1334
1335         /* SAMPLE_RATE */
1336         best = 0;
1337         best_val = abs(wm8993->fs - sample_rates[0].rate);
1338         for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1339                 /* Closest match */
1340                 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1341                 if (cur_val < best_val) {
1342                         best = i;
1343                         best_val = cur_val;
1344                 }
1345         }
1346         dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1347                 sample_rates[best].rate);
1348         clocking3 |= (sample_rates[best].sample_rate
1349                       << WM8993_SAMPLE_RATE_SHIFT);
1350
1351         /* BCLK_DIV */
1352         best = 0;
1353         best_val = INT_MAX;
1354         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1355                 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1356                         - wm8993->bclk;
1357                 if (cur_val < 0) /* Table is sorted */
1358                         break;
1359                 if (cur_val < best_val) {
1360                         best = i;
1361                         best_val = cur_val;
1362                 }
1363         }
1364         wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1365         dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1366                 bclk_divs[best].div, wm8993->bclk);
1367         clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1368
1369         /* LRCLK is a simple fraction of BCLK */
1370         dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1371         aif4 |= wm8993->bclk / wm8993->fs;
1372
1373         snd_soc_write(codec, WM8993_CLOCKING_1, clocking1);
1374         snd_soc_write(codec, WM8993_CLOCKING_3, clocking3);
1375         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1);
1376         snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4);
1377
1378         /* ReTune Mobile? */
1379         if (wm8993->pdata.num_retune_configs) {
1380                 u16 eq1 = snd_soc_read(codec, WM8993_EQ1);
1381                 struct wm8993_retune_mobile_setting *s;
1382
1383                 best = 0;
1384                 best_val = abs(wm8993->pdata.retune_configs[0].rate
1385                                - wm8993->fs);
1386                 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1387                         cur_val = abs(wm8993->pdata.retune_configs[i].rate
1388                                       - wm8993->fs);
1389                         if (cur_val < best_val) {
1390                                 best_val = cur_val;
1391                                 best = i;
1392                         }
1393                 }
1394                 s = &wm8993->pdata.retune_configs[best];
1395
1396                 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1397                         s->name, s->rate);
1398
1399                 /* Disable EQ while we reconfigure */
1400                 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0);
1401
1402                 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1403                         snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]);
1404
1405                 snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1406         }
1407
1408         return 0;
1409 }
1410
1411 static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1412 {
1413         struct snd_soc_codec *codec = codec_dai->codec;
1414         unsigned int reg;
1415
1416         reg = snd_soc_read(codec, WM8993_DAC_CTRL);
1417
1418         if (mute)
1419                 reg |= WM8993_DAC_MUTE;
1420         else
1421                 reg &= ~WM8993_DAC_MUTE;
1422
1423         snd_soc_write(codec, WM8993_DAC_CTRL, reg);
1424
1425         return 0;
1426 }
1427
1428 static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1429                                unsigned int rx_mask, int slots, int slot_width)
1430 {
1431         struct snd_soc_codec *codec = dai->codec;
1432         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1433         int aif1 = 0;
1434         int aif2 = 0;
1435
1436         /* Don't need to validate anything if we're turning off TDM */
1437         if (slots == 0) {
1438                 wm8993->tdm_slots = 0;
1439                 goto out;
1440         }
1441
1442         /* Note that we allow configurations we can't handle ourselves -
1443          * for example, we can generate clocks for slots 2 and up even if
1444          * we can't use those slots ourselves.
1445          */
1446         aif1 |= WM8993_AIFADC_TDM;
1447         aif2 |= WM8993_AIFDAC_TDM;
1448
1449         switch (rx_mask) {
1450         case 3:
1451                 break;
1452         case 0xc:
1453                 aif1 |= WM8993_AIFADC_TDM_CHAN;
1454                 break;
1455         default:
1456                 return -EINVAL;
1457         }
1458
1459
1460         switch (tx_mask) {
1461         case 3:
1462                 break;
1463         case 0xc:
1464                 aif2 |= WM8993_AIFDAC_TDM_CHAN;
1465                 break;
1466         default:
1467                 return -EINVAL;
1468         }
1469
1470 out:
1471         wm8993->tdm_width = slot_width;
1472         wm8993->tdm_slots = slots / 2;
1473
1474         snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1,
1475                             WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1476         snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2,
1477                             WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1478
1479         return 0;
1480 }
1481
1482 static irqreturn_t wm8993_irq(int irq, void *data)
1483 {
1484         struct wm8993_priv *wm8993 = data;
1485         int mask, val, ret;
1486
1487         ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val);
1488         if (ret != 0) {
1489                 dev_err(wm8993->dev, "Failed to read interrupt status: %d\n",
1490                         ret);
1491                 return IRQ_NONE;
1492         }
1493
1494         ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask);
1495         if (ret != 0) {
1496                 dev_err(wm8993->dev, "Failed to read interrupt mask: %d\n",
1497                         ret);
1498                 return IRQ_NONE;
1499         }
1500
1501         /* The IRQ pin status is visible in the register too */
1502         val &= ~(mask | WM8993_IRQ);
1503         if (!val)
1504                 return IRQ_NONE;
1505
1506         if (val & WM8993_TEMPOK_EINT)
1507                 dev_crit(wm8993->dev, "Thermal warning\n");
1508
1509         if (val & WM8993_FLL_LOCK_EINT) {
1510                 dev_dbg(wm8993->dev, "FLL locked\n");
1511                 complete(&wm8993->fll_lock);
1512         }
1513
1514         ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val);
1515         if (ret != 0)
1516                 dev_err(wm8993->dev, "Failed to ack interrupt: %d\n", ret);
1517
1518         return IRQ_HANDLED;
1519 }
1520
1521 static const struct snd_soc_dai_ops wm8993_ops = {
1522         .set_sysclk = wm8993_set_sysclk,
1523         .set_fmt = wm8993_set_dai_fmt,
1524         .hw_params = wm8993_hw_params,
1525         .digital_mute = wm8993_digital_mute,
1526         .set_pll = wm8993_set_fll,
1527         .set_tdm_slot = wm8993_set_tdm_slot,
1528 };
1529
1530 #define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1531
1532 #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1533                         SNDRV_PCM_FMTBIT_S20_3LE |\
1534                         SNDRV_PCM_FMTBIT_S24_LE |\
1535                         SNDRV_PCM_FMTBIT_S32_LE)
1536
1537 static struct snd_soc_dai_driver wm8993_dai = {
1538         .name = "wm8993-hifi",
1539         .playback = {
1540                 .stream_name = "Playback",
1541                 .channels_min = 1,
1542                 .channels_max = 2,
1543                 .rates = WM8993_RATES,
1544                 .formats = WM8993_FORMATS,
1545                 .sig_bits = 24,
1546         },
1547         .capture = {
1548                  .stream_name = "Capture",
1549                  .channels_min = 1,
1550                  .channels_max = 2,
1551                  .rates = WM8993_RATES,
1552                  .formats = WM8993_FORMATS,
1553                  .sig_bits = 24,
1554          },
1555         .ops = &wm8993_ops,
1556         .symmetric_rates = 1,
1557 };
1558
1559 static int wm8993_probe(struct snd_soc_codec *codec)
1560 {
1561         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1562         struct snd_soc_dapm_context *dapm = &codec->dapm;
1563         int ret;
1564
1565         wm8993->hubs_data.hp_startup_mode = 1;
1566         wm8993->hubs_data.dcs_codes_l = -2;
1567         wm8993->hubs_data.dcs_codes_r = -2;
1568         wm8993->hubs_data.series_startup = 1;
1569
1570         codec->control_data = wm8993->regmap;
1571         ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
1572         if (ret != 0) {
1573                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1574                 return ret;
1575         }
1576
1577         /* By default we're using the output mixers */
1578         wm8993->class_w_users = 2;
1579
1580         /* Latch volume update bits and default ZC on */
1581         snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1582                             WM8993_DAC_VU, WM8993_DAC_VU);
1583         snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1584                             WM8993_ADC_VU, WM8993_ADC_VU);
1585
1586         /* Manualy manage the HPOUT sequencing for independent stereo
1587          * control. */
1588         snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0,
1589                             WM8993_HPOUT1_AUTO_PU, 0);
1590
1591         /* Use automatic clock configuration */
1592         snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1593
1594         wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff,
1595                                       wm8993->pdata.lineout2_diff,
1596                                       wm8993->pdata.lineout1fb,
1597                                       wm8993->pdata.lineout2fb,
1598                                       wm8993->pdata.jd_scthr,
1599                                       wm8993->pdata.jd_thr,
1600                                       wm8993->pdata.micbias1_lvl,
1601                                       wm8993->pdata.micbias2_lvl);
1602
1603         ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1604         if (ret != 0)
1605                 return ret;
1606
1607         snd_soc_add_controls(codec, wm8993_snd_controls,
1608                              ARRAY_SIZE(wm8993_snd_controls));
1609         if (wm8993->pdata.num_retune_configs != 0) {
1610                 dev_dbg(codec->dev, "Using ReTune Mobile\n");
1611         } else {
1612                 dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n");
1613                 snd_soc_add_controls(codec, wm8993_eq_controls,
1614                                      ARRAY_SIZE(wm8993_eq_controls));
1615         }
1616
1617         snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
1618                                   ARRAY_SIZE(wm8993_dapm_widgets));
1619         wm_hubs_add_analogue_controls(codec);
1620
1621         snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1622         wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff,
1623                                     wm8993->pdata.lineout2_diff);
1624
1625         /* If the line outputs are differential then we aren't presenting
1626          * VMID as an output and can disable it.
1627          */
1628         if (wm8993->pdata.lineout1_diff && wm8993->pdata.lineout2_diff)
1629                 codec->dapm.idle_bias_off = 1;
1630
1631         return 0;
1632
1633 }
1634
1635 static int wm8993_remove(struct snd_soc_codec *codec)
1636 {
1637         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1638
1639         wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1640         regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1641         return 0;
1642 }
1643
1644 #ifdef CONFIG_PM
1645 static int wm8993_suspend(struct snd_soc_codec *codec)
1646 {
1647         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1648         int fll_fout = wm8993->fll_fout;
1649         int fll_fref  = wm8993->fll_fref;
1650         int ret;
1651
1652         /* Stop the FLL in an orderly fashion */
1653         ret = _wm8993_set_fll(codec, 0, 0, 0, 0);
1654         if (ret != 0) {
1655                 dev_err(codec->dev, "Failed to stop FLL\n");
1656                 return ret;
1657         }
1658
1659         wm8993->fll_fout = fll_fout;
1660         wm8993->fll_fref = fll_fref;
1661
1662         wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF);
1663
1664         return 0;
1665 }
1666
1667 static int wm8993_resume(struct snd_soc_codec *codec)
1668 {
1669         struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec);
1670         int ret;
1671
1672         wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1673
1674         /* Restart the FLL? */
1675         if (wm8993->fll_fout) {
1676                 int fll_fout = wm8993->fll_fout;
1677                 int fll_fref  = wm8993->fll_fref;
1678
1679                 wm8993->fll_fref = 0;
1680                 wm8993->fll_fout = 0;
1681
1682                 ret = _wm8993_set_fll(codec, 0, wm8993->fll_src,
1683                                      fll_fref, fll_fout);
1684                 if (ret != 0)
1685                         dev_err(codec->dev, "Failed to restart FLL\n");
1686         }
1687
1688         return 0;
1689 }
1690 #else
1691 #define wm8993_suspend NULL
1692 #define wm8993_resume NULL
1693 #endif
1694
1695 /* Tune DC servo configuration */
1696 static struct reg_default wm8993_regmap_patch[] = {
1697         { 0x44, 3 },
1698         { 0x56, 3 },
1699         { 0x44, 0 },
1700 };
1701
1702 static const struct regmap_config wm8993_regmap = {
1703         .reg_bits = 8,
1704         .val_bits = 16,
1705
1706         .max_register = WM8993_MAX_REGISTER,
1707         .volatile_reg = wm8993_volatile,
1708         .readable_reg = wm8993_readable,
1709
1710         .cache_type = REGCACHE_RBTREE,
1711         .reg_defaults = wm8993_reg_defaults,
1712         .num_reg_defaults = ARRAY_SIZE(wm8993_reg_defaults),
1713 };
1714
1715 static struct snd_soc_codec_driver soc_codec_dev_wm8993 = {
1716         .probe =        wm8993_probe,
1717         .remove =       wm8993_remove,
1718         .suspend =      wm8993_suspend,
1719         .resume =       wm8993_resume,
1720         .set_bias_level = wm8993_set_bias_level,
1721 };
1722
1723 static __devinit int wm8993_i2c_probe(struct i2c_client *i2c,
1724                                       const struct i2c_device_id *id)
1725 {
1726         struct wm8993_priv *wm8993;
1727         unsigned int reg;
1728         int ret, i;
1729
1730         wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv),
1731                               GFP_KERNEL);
1732         if (wm8993 == NULL)
1733                 return -ENOMEM;
1734
1735         wm8993->dev = &i2c->dev;
1736         init_completion(&wm8993->fll_lock);
1737
1738         wm8993->regmap = regmap_init_i2c(i2c, &wm8993_regmap);
1739         if (IS_ERR(wm8993->regmap)) {
1740                 ret = PTR_ERR(wm8993->regmap);
1741                 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1742                 return ret;
1743         }
1744
1745         i2c_set_clientdata(i2c, wm8993);
1746
1747         for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1748                 wm8993->supplies[i].supply = wm8993_supply_names[i];
1749
1750         ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8993->supplies),
1751                                  wm8993->supplies);
1752         if (ret != 0) {
1753                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1754                 goto err;
1755         }
1756
1757         ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1758                                     wm8993->supplies);
1759         if (ret != 0) {
1760                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
1761                 goto err_get;
1762         }
1763
1764         ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, &reg);
1765         if (ret != 0) {
1766                 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1767                 goto err_enable;
1768         }
1769
1770         if (reg != 0x8993) {
1771                 dev_err(&i2c->dev, "Invalid ID register value %x\n", reg);
1772                 ret = -EINVAL;
1773                 goto err_enable;
1774         }
1775
1776         ret = regmap_write(wm8993->regmap, WM8993_SOFTWARE_RESET, 0xffff);
1777         if (ret != 0)
1778                 goto err_enable;
1779
1780         ret = regmap_register_patch(wm8993->regmap, wm8993_regmap_patch,
1781                                     ARRAY_SIZE(wm8993_regmap_patch));
1782         if (ret != 0)
1783                 dev_warn(wm8993->dev, "Failed to apply regmap patch: %d\n",
1784                          ret);
1785
1786         if (i2c->irq) {
1787                 /* Put GPIO1 into interrupt mode (only GPIO1 can output IRQ) */
1788                 ret = regmap_update_bits(wm8993->regmap, WM8993_GPIO1,
1789                                          WM8993_GPIO1_PD |
1790                                          WM8993_GPIO1_SEL_MASK, 7);
1791                 if (ret != 0)
1792                         goto err_enable;
1793
1794                 ret = request_threaded_irq(i2c->irq, NULL, wm8993_irq,
1795                                            IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1796                                            "wm8993", wm8993);
1797                 if (ret != 0)
1798                         goto err_enable;
1799
1800         }
1801
1802         regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1803
1804         regcache_cache_only(wm8993->regmap, true);
1805
1806         ret = snd_soc_register_codec(&i2c->dev,
1807                         &soc_codec_dev_wm8993, &wm8993_dai, 1);
1808         if (ret != 0) {
1809                 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1810                 goto err_irq;
1811         }
1812
1813         return 0;
1814
1815 err_irq:
1816         if (i2c->irq)
1817                 free_irq(i2c->irq, wm8993);
1818 err_enable:
1819         regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1820 err_get:
1821         regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1822 err:
1823         regmap_exit(wm8993->regmap);
1824         return ret;
1825 }
1826
1827 static __devexit int wm8993_i2c_remove(struct i2c_client *i2c)
1828 {
1829         struct wm8993_priv *wm8993 = i2c_get_clientdata(i2c);
1830
1831         snd_soc_unregister_codec(&i2c->dev);
1832         if (i2c->irq)
1833                 free_irq(i2c->irq, wm8993);
1834         regmap_exit(wm8993->regmap);
1835         regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1836         regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1837
1838         return 0;
1839 }
1840
1841 static const struct i2c_device_id wm8993_i2c_id[] = {
1842         { "wm8993", 0 },
1843         { }
1844 };
1845 MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1846
1847 static struct i2c_driver wm8993_i2c_driver = {
1848         .driver = {
1849                 .name = "wm8993",
1850                 .owner = THIS_MODULE,
1851         },
1852         .probe =    wm8993_i2c_probe,
1853         .remove =   __devexit_p(wm8993_i2c_remove),
1854         .id_table = wm8993_i2c_id,
1855 };
1856
1857 static int __init wm8993_modinit(void)
1858 {
1859         int ret = 0;
1860         ret = i2c_add_driver(&wm8993_i2c_driver);
1861         if (ret != 0) {
1862                 pr_err("WM8993: Unable to register I2C driver: %d\n",
1863                        ret);
1864         }
1865         return ret;
1866 }
1867 module_init(wm8993_modinit);
1868
1869 static void __exit wm8993_exit(void)
1870 {
1871         i2c_del_driver(&wm8993_i2c_driver);
1872 }
1873 module_exit(wm8993_exit);
1874
1875
1876 MODULE_DESCRIPTION("ASoC WM8993 driver");
1877 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1878 MODULE_LICENSE("GPL");