2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009-12 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/gcd.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/jack.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <trace/events/asoc.h>
34 #include <linux/mfd/wm8994/core.h>
35 #include <linux/mfd/wm8994/registers.h>
36 #include <linux/mfd/wm8994/pdata.h>
37 #include <linux/mfd/wm8994/gpio.h>
42 #define WM1811_JACKDET_MODE_NONE 0x0000
43 #define WM1811_JACKDET_MODE_JACK 0x0100
44 #define WM1811_JACKDET_MODE_MIC 0x0080
45 #define WM1811_JACKDET_MODE_AUDIO 0x0180
47 #define WM8994_NUM_DRC 3
48 #define WM8994_NUM_EQ 3
53 } wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
83 static int wm8994_drc_base[] = {
89 static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
95 static const struct wm8958_micd_rate micdet_rates[] = {
96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
102 static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
109 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
112 struct wm8994 *control = wm8994->wm8994;
113 int best, i, sysclk, val;
115 const struct wm8958_micd_rate *rates;
118 idle = !wm8994->jack_mic;
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
124 sysclk = wm8994->aifclk[0];
126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
129 } else if (wm8994->jackdet) {
130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
144 else if (rates[best].idle != idle)
148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
160 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
177 case WM8994_SYSCLK_MCLK2:
179 rate = wm8994->mclk[1];
182 case WM8994_SYSCLK_FLL1:
184 rate = wm8994->fll[0].out;
187 case WM8994_SYSCLK_FLL2:
189 rate = wm8994->fll[1].out;
196 if (rate >= 13500000) {
198 reg1 |= WM8994_AIF1CLK_DIV;
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
204 wm8994->aifclk[aif] = rate;
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
213 static int configure_clock(struct snd_soc_codec *codec)
215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
228 /* If they're equal it doesn't matter which is used */
229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
242 snd_soc_dapm_sync(&codec->dapm);
244 wm8958_micd_set_rate(codec);
249 static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
252 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8994_SYSCLK_SRC)
261 return strcmp(source->name, clk) == 0;
264 static const char *sidetone_hpf_text[] = {
265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
268 static const struct soc_enum sidetone_hpf =
269 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
271 static const char *adc_hpf_text[] = {
272 "HiFi", "Voice 1", "Voice 2", "Voice 3"
275 static const struct soc_enum aif1adc1_hpf =
276 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
278 static const struct soc_enum aif1adc2_hpf =
279 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
281 static const struct soc_enum aif2adc_hpf =
282 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
284 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
289 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
290 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
292 #define WM8994_DRC_SWITCH(xname, reg, shift) \
293 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
294 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
295 .put = wm8994_put_drc_sw, \
296 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
298 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
299 struct snd_ctl_elem_value *ucontrol)
301 struct soc_mixer_control *mc =
302 (struct soc_mixer_control *)kcontrol->private_value;
303 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
306 /* Can't enable both ADC and DAC paths simultaneously */
307 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
308 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
309 WM8994_AIF1ADC1R_DRC_ENA_MASK;
311 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
313 ret = snd_soc_read(codec, mc->reg);
319 return snd_soc_put_volsw(kcontrol, ucontrol);
322 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
324 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
325 struct wm8994 *control = wm8994->wm8994;
326 struct wm8994_pdata *pdata = &control->pdata;
327 int base = wm8994_drc_base[drc];
328 int cfg = wm8994->drc_cfg[drc];
331 /* Save any enables; the configuration should clear them. */
332 save = snd_soc_read(codec, base);
333 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
334 WM8994_AIF1ADC1R_DRC_ENA;
336 for (i = 0; i < WM8994_DRC_REGS; i++)
337 snd_soc_update_bits(codec, base + i, 0xffff,
338 pdata->drc_cfgs[cfg].regs[i]);
340 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
341 WM8994_AIF1ADC1L_DRC_ENA |
342 WM8994_AIF1ADC1R_DRC_ENA, save);
345 /* Icky as hell but saves code duplication */
346 static int wm8994_get_drc(const char *name)
348 if (strcmp(name, "AIF1DRC1 Mode") == 0)
350 if (strcmp(name, "AIF1DRC2 Mode") == 0)
352 if (strcmp(name, "AIF2DRC Mode") == 0)
357 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
358 struct snd_ctl_elem_value *ucontrol)
360 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
361 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
362 struct wm8994 *control = wm8994->wm8994;
363 struct wm8994_pdata *pdata = &control->pdata;
364 int drc = wm8994_get_drc(kcontrol->id.name);
365 int value = ucontrol->value.integer.value[0];
370 if (value >= pdata->num_drc_cfgs)
373 wm8994->drc_cfg[drc] = value;
375 wm8994_set_drc(codec, drc);
380 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
381 struct snd_ctl_elem_value *ucontrol)
383 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
384 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
385 int drc = wm8994_get_drc(kcontrol->id.name);
389 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
394 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
396 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
397 struct wm8994 *control = wm8994->wm8994;
398 struct wm8994_pdata *pdata = &control->pdata;
399 int base = wm8994_retune_mobile_base[block];
400 int iface, best, best_val, save, i, cfg;
402 if (!pdata || !wm8994->num_retune_mobile_texts)
417 /* Find the version of the currently selected configuration
418 * with the nearest sample rate. */
419 cfg = wm8994->retune_mobile_cfg[block];
422 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
423 if (strcmp(pdata->retune_mobile_cfgs[i].name,
424 wm8994->retune_mobile_texts[cfg]) == 0 &&
425 abs(pdata->retune_mobile_cfgs[i].rate
426 - wm8994->dac_rates[iface]) < best_val) {
428 best_val = abs(pdata->retune_mobile_cfgs[i].rate
429 - wm8994->dac_rates[iface]);
433 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
435 pdata->retune_mobile_cfgs[best].name,
436 pdata->retune_mobile_cfgs[best].rate,
437 wm8994->dac_rates[iface]);
439 /* The EQ will be disabled while reconfiguring it, remember the
440 * current configuration.
442 save = snd_soc_read(codec, base);
443 save &= WM8994_AIF1DAC1_EQ_ENA;
445 for (i = 0; i < WM8994_EQ_REGS; i++)
446 snd_soc_update_bits(codec, base + i, 0xffff,
447 pdata->retune_mobile_cfgs[best].regs[i]);
449 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
452 /* Icky as hell but saves code duplication */
453 static int wm8994_get_retune_mobile_block(const char *name)
455 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
457 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
459 if (strcmp(name, "AIF2 EQ Mode") == 0)
464 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
465 struct snd_ctl_elem_value *ucontrol)
467 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
468 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
469 struct wm8994 *control = wm8994->wm8994;
470 struct wm8994_pdata *pdata = &control->pdata;
471 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
472 int value = ucontrol->value.integer.value[0];
477 if (value >= pdata->num_retune_mobile_cfgs)
480 wm8994->retune_mobile_cfg[block] = value;
482 wm8994_set_retune_mobile(codec, block);
487 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
488 struct snd_ctl_elem_value *ucontrol)
490 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
491 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
492 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
497 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
502 static const char *aif_chan_src_text[] = {
506 static const struct soc_enum aif1adcl_src =
507 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
509 static const struct soc_enum aif1adcr_src =
510 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
512 static const struct soc_enum aif2adcl_src =
513 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
515 static const struct soc_enum aif2adcr_src =
516 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
518 static const struct soc_enum aif1dacl_src =
519 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
521 static const struct soc_enum aif1dacr_src =
522 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
524 static const struct soc_enum aif2dacl_src =
525 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
527 static const struct soc_enum aif2dacr_src =
528 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
530 static const char *osr_text[] = {
531 "Low Power", "High Performance",
534 static const struct soc_enum dac_osr =
535 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
537 static const struct soc_enum adc_osr =
538 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
540 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
541 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
542 WM8994_AIF1_ADC1_RIGHT_VOLUME,
543 1, 119, 0, digital_tlv),
544 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
545 WM8994_AIF1_ADC2_RIGHT_VOLUME,
546 1, 119, 0, digital_tlv),
547 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
548 WM8994_AIF2_ADC_RIGHT_VOLUME,
549 1, 119, 0, digital_tlv),
551 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
552 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
553 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
554 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
556 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
557 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
558 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
559 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
561 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
562 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
563 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
564 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
565 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
566 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
568 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
569 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
571 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
572 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
573 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
575 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
576 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
577 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
579 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
580 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
581 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
583 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
584 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
585 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
587 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
589 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
591 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
593 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
595 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
596 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
598 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
599 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
601 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
602 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
604 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
605 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
607 SOC_ENUM("ADC OSR", adc_osr),
608 SOC_ENUM("DAC OSR", dac_osr),
610 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
611 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
612 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
613 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
615 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
616 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
617 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
618 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
620 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
621 6, 1, 1, wm_hubs_spkmix_tlv),
622 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
623 2, 1, 1, wm_hubs_spkmix_tlv),
625 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
626 6, 1, 1, wm_hubs_spkmix_tlv),
627 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
628 2, 1, 1, wm_hubs_spkmix_tlv),
630 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
631 10, 15, 0, wm8994_3d_tlv),
632 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
634 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
635 10, 15, 0, wm8994_3d_tlv),
636 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
638 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
639 10, 15, 0, wm8994_3d_tlv),
640 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
644 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
645 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
647 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
649 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
651 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
653 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
656 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
658 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
660 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
662 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
664 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
667 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
669 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
671 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
673 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
675 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
679 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
680 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
681 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
682 WM8994_AIF1ADC1R_DRC_ENA),
683 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
684 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
685 WM8994_AIF1ADC2R_DRC_ENA),
686 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
687 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
688 WM8994_AIF2ADCR_DRC_ENA),
691 static const char *wm8958_ng_text[] = {
692 "30ms", "125ms", "250ms", "500ms",
695 static const struct soc_enum wm8958_aif1dac1_ng_hold =
696 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
697 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
699 static const struct soc_enum wm8958_aif1dac2_ng_hold =
700 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
701 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
703 static const struct soc_enum wm8958_aif2dac_ng_hold =
704 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
705 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
707 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
708 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
710 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
711 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
712 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
713 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
714 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
717 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
718 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
719 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
720 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
721 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
724 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
725 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
726 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
727 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
728 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
732 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
733 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
735 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
739 /* We run all mode setting through a function to enforce audio mode */
740 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
742 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
744 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
747 if (wm8994->active_refcount)
748 mode = WM1811_JACKDET_MODE_AUDIO;
750 if (mode == wm8994->jackdet_mode)
753 wm8994->jackdet_mode = mode;
755 /* Always use audio mode to detect while the system is active */
756 if (mode != WM1811_JACKDET_MODE_NONE)
757 mode = WM1811_JACKDET_MODE_AUDIO;
759 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
760 WM1811_JACKDET_MODE_MASK, mode);
763 static void active_reference(struct snd_soc_codec *codec)
765 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
767 mutex_lock(&wm8994->accdet_lock);
769 wm8994->active_refcount++;
771 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
772 wm8994->active_refcount);
774 /* If we're using jack detection go into audio mode */
775 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
777 mutex_unlock(&wm8994->accdet_lock);
780 static void active_dereference(struct snd_soc_codec *codec)
782 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
785 mutex_lock(&wm8994->accdet_lock);
787 wm8994->active_refcount--;
789 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
790 wm8994->active_refcount);
792 if (wm8994->active_refcount == 0) {
793 /* Go into appropriate detection only mode */
794 if (wm8994->jack_mic || wm8994->mic_detecting)
795 mode = WM1811_JACKDET_MODE_MIC;
797 mode = WM1811_JACKDET_MODE_JACK;
799 wm1811_jackdet_set_mode(codec, mode);
802 mutex_unlock(&wm8994->accdet_lock);
805 static int clk_sys_event(struct snd_soc_dapm_widget *w,
806 struct snd_kcontrol *kcontrol, int event)
808 struct snd_soc_codec *codec = w->codec;
809 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
812 case SND_SOC_DAPM_PRE_PMU:
813 return configure_clock(codec);
815 case SND_SOC_DAPM_POST_PMU:
817 * JACKDET won't run until we start the clock and it
818 * only reports deltas, make sure we notify the state
819 * up the stack on startup. Use a *very* generous
820 * timeout for paranoia, there's no urgency and we
821 * don't want false reports.
823 if (wm8994->jackdet && !wm8994->clk_has_run) {
824 schedule_delayed_work(&wm8994->jackdet_bootstrap,
825 msecs_to_jiffies(1000));
826 wm8994->clk_has_run = true;
830 case SND_SOC_DAPM_POST_PMD:
831 configure_clock(codec);
838 static void vmid_reference(struct snd_soc_codec *codec)
840 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
842 pm_runtime_get_sync(codec->dev);
844 wm8994->vmid_refcount++;
846 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
847 wm8994->vmid_refcount);
849 if (wm8994->vmid_refcount == 1) {
850 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
851 WM8994_LINEOUT1_DISCH |
852 WM8994_LINEOUT2_DISCH, 0);
854 wm_hubs_vmid_ena(codec);
856 switch (wm8994->vmid_mode) {
858 WARN_ON(NULL == "Invalid VMID mode");
859 case WM8994_VMID_NORMAL:
860 /* Startup bias, VMID ramp & buffer */
861 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
864 WM8994_STARTUP_BIAS_ENA |
865 WM8994_VMID_BUF_ENA |
866 WM8994_VMID_RAMP_MASK,
868 WM8994_STARTUP_BIAS_ENA |
869 WM8994_VMID_BUF_ENA |
870 (0x2 << WM8994_VMID_RAMP_SHIFT));
872 /* Main bias enable, VMID=2x40k */
873 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
875 WM8994_VMID_SEL_MASK,
876 WM8994_BIAS_ENA | 0x2);
880 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
881 WM8994_VMID_RAMP_MASK |
886 case WM8994_VMID_FORCE:
887 /* Startup bias, slow VMID ramp & buffer */
888 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
891 WM8994_STARTUP_BIAS_ENA |
892 WM8994_VMID_BUF_ENA |
893 WM8994_VMID_RAMP_MASK,
895 WM8994_STARTUP_BIAS_ENA |
896 WM8994_VMID_BUF_ENA |
897 (0x2 << WM8994_VMID_RAMP_SHIFT));
899 /* Main bias enable, VMID=2x40k */
900 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
902 WM8994_VMID_SEL_MASK,
903 WM8994_BIAS_ENA | 0x2);
907 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
908 WM8994_VMID_RAMP_MASK |
916 static void vmid_dereference(struct snd_soc_codec *codec)
918 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
920 wm8994->vmid_refcount--;
922 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
923 wm8994->vmid_refcount);
925 if (wm8994->vmid_refcount == 0) {
926 if (wm8994->hubs.lineout1_se)
927 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
928 WM8994_LINEOUT1N_ENA |
929 WM8994_LINEOUT1P_ENA,
930 WM8994_LINEOUT1N_ENA |
931 WM8994_LINEOUT1P_ENA);
933 if (wm8994->hubs.lineout2_se)
934 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
935 WM8994_LINEOUT2N_ENA |
936 WM8994_LINEOUT2P_ENA,
937 WM8994_LINEOUT2N_ENA |
938 WM8994_LINEOUT2P_ENA);
940 /* Start discharging VMID */
941 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
947 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
948 WM8994_VMID_SEL_MASK, 0);
952 /* Active discharge */
953 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
954 WM8994_LINEOUT1_DISCH |
955 WM8994_LINEOUT2_DISCH,
956 WM8994_LINEOUT1_DISCH |
957 WM8994_LINEOUT2_DISCH);
959 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
960 WM8994_LINEOUT1N_ENA |
961 WM8994_LINEOUT1P_ENA |
962 WM8994_LINEOUT2N_ENA |
963 WM8994_LINEOUT2P_ENA, 0);
965 /* Switch off startup biases */
966 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
968 WM8994_STARTUP_BIAS_ENA |
969 WM8994_VMID_BUF_ENA |
970 WM8994_VMID_RAMP_MASK, 0);
972 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
973 WM8994_VMID_SEL_MASK, 0);
976 pm_runtime_put(codec->dev);
979 static int vmid_event(struct snd_soc_dapm_widget *w,
980 struct snd_kcontrol *kcontrol, int event)
982 struct snd_soc_codec *codec = w->codec;
985 case SND_SOC_DAPM_PRE_PMU:
986 vmid_reference(codec);
989 case SND_SOC_DAPM_POST_PMD:
990 vmid_dereference(codec);
997 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
999 int source = 0; /* GCC flow analysis can't track enable */
1002 /* We also need the same AIF source for L/R and only one path */
1003 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1005 case WM8994_AIF2DACL_TO_DAC1L:
1006 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1007 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1009 case WM8994_AIF1DAC2L_TO_DAC1L:
1010 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1011 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1013 case WM8994_AIF1DAC1L_TO_DAC1L:
1014 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1015 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1018 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1022 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1024 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1028 /* Set the source up */
1029 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1030 WM8994_CP_DYN_SRC_SEL_MASK, source);
1035 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1036 struct snd_kcontrol *kcontrol, int event)
1038 struct snd_soc_codec *codec = w->codec;
1039 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1040 struct wm8994 *control = wm8994->wm8994;
1041 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1047 switch (control->type) {
1050 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1057 case SND_SOC_DAPM_PRE_PMU:
1058 /* Don't enable timeslot 2 if not in use */
1059 if (wm8994->channels[0] <= 2)
1060 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1062 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1063 if ((val & WM8994_AIF1ADCL_SRC) &&
1064 (val & WM8994_AIF1ADCR_SRC))
1065 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1066 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1067 !(val & WM8994_AIF1ADCR_SRC))
1068 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1070 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1071 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1073 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1074 if ((val & WM8994_AIF1DACL_SRC) &&
1075 (val & WM8994_AIF1DACR_SRC))
1076 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1077 else if (!(val & WM8994_AIF1DACL_SRC) &&
1078 !(val & WM8994_AIF1DACR_SRC))
1079 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1081 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1082 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1084 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1086 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1088 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1089 WM8994_AIF1DSPCLK_ENA |
1090 WM8994_SYSDSPCLK_ENA,
1091 WM8994_AIF1DSPCLK_ENA |
1092 WM8994_SYSDSPCLK_ENA);
1093 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1094 WM8994_AIF1ADC1R_ENA |
1095 WM8994_AIF1ADC1L_ENA |
1096 WM8994_AIF1ADC2R_ENA |
1097 WM8994_AIF1ADC2L_ENA);
1098 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1099 WM8994_AIF1DAC1R_ENA |
1100 WM8994_AIF1DAC1L_ENA |
1101 WM8994_AIF1DAC2R_ENA |
1102 WM8994_AIF1DAC2L_ENA);
1105 case SND_SOC_DAPM_POST_PMU:
1106 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1107 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1109 wm8994_vu_bits[i].reg));
1112 case SND_SOC_DAPM_PRE_PMD:
1113 case SND_SOC_DAPM_POST_PMD:
1114 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1116 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1119 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1120 if (val & WM8994_AIF2DSPCLK_ENA)
1121 val = WM8994_SYSDSPCLK_ENA;
1124 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1125 WM8994_SYSDSPCLK_ENA |
1126 WM8994_AIF1DSPCLK_ENA, val);
1133 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1134 struct snd_kcontrol *kcontrol, int event)
1136 struct snd_soc_codec *codec = w->codec;
1143 case SND_SOC_DAPM_PRE_PMU:
1144 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1145 if ((val & WM8994_AIF2ADCL_SRC) &&
1146 (val & WM8994_AIF2ADCR_SRC))
1147 adc = WM8994_AIF2ADCR_ENA;
1148 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1149 !(val & WM8994_AIF2ADCR_SRC))
1150 adc = WM8994_AIF2ADCL_ENA;
1152 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1155 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1156 if ((val & WM8994_AIF2DACL_SRC) &&
1157 (val & WM8994_AIF2DACR_SRC))
1158 dac = WM8994_AIF2DACR_ENA;
1159 else if (!(val & WM8994_AIF2DACL_SRC) &&
1160 !(val & WM8994_AIF2DACR_SRC))
1161 dac = WM8994_AIF2DACL_ENA;
1163 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1165 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1166 WM8994_AIF2ADCL_ENA |
1167 WM8994_AIF2ADCR_ENA, adc);
1168 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1169 WM8994_AIF2DACL_ENA |
1170 WM8994_AIF2DACR_ENA, dac);
1171 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1172 WM8994_AIF2DSPCLK_ENA |
1173 WM8994_SYSDSPCLK_ENA,
1174 WM8994_AIF2DSPCLK_ENA |
1175 WM8994_SYSDSPCLK_ENA);
1176 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1177 WM8994_AIF2ADCL_ENA |
1178 WM8994_AIF2ADCR_ENA,
1179 WM8994_AIF2ADCL_ENA |
1180 WM8994_AIF2ADCR_ENA);
1181 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1182 WM8994_AIF2DACL_ENA |
1183 WM8994_AIF2DACR_ENA,
1184 WM8994_AIF2DACL_ENA |
1185 WM8994_AIF2DACR_ENA);
1188 case SND_SOC_DAPM_POST_PMU:
1189 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1190 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1192 wm8994_vu_bits[i].reg));
1195 case SND_SOC_DAPM_PRE_PMD:
1196 case SND_SOC_DAPM_POST_PMD:
1197 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1198 WM8994_AIF2DACL_ENA |
1199 WM8994_AIF2DACR_ENA, 0);
1200 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1201 WM8994_AIF2ADCL_ENA |
1202 WM8994_AIF2ADCR_ENA, 0);
1204 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1205 if (val & WM8994_AIF1DSPCLK_ENA)
1206 val = WM8994_SYSDSPCLK_ENA;
1209 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1210 WM8994_SYSDSPCLK_ENA |
1211 WM8994_AIF2DSPCLK_ENA, val);
1218 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1219 struct snd_kcontrol *kcontrol, int event)
1221 struct snd_soc_codec *codec = w->codec;
1222 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1225 case SND_SOC_DAPM_PRE_PMU:
1226 wm8994->aif1clk_enable = 1;
1228 case SND_SOC_DAPM_POST_PMD:
1229 wm8994->aif1clk_disable = 1;
1236 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1237 struct snd_kcontrol *kcontrol, int event)
1239 struct snd_soc_codec *codec = w->codec;
1240 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1243 case SND_SOC_DAPM_PRE_PMU:
1244 wm8994->aif2clk_enable = 1;
1246 case SND_SOC_DAPM_POST_PMD:
1247 wm8994->aif2clk_disable = 1;
1254 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1255 struct snd_kcontrol *kcontrol, int event)
1257 struct snd_soc_codec *codec = w->codec;
1258 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1261 case SND_SOC_DAPM_PRE_PMU:
1262 if (wm8994->aif1clk_enable) {
1263 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1264 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1265 WM8994_AIF1CLK_ENA_MASK,
1266 WM8994_AIF1CLK_ENA);
1267 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1268 wm8994->aif1clk_enable = 0;
1270 if (wm8994->aif2clk_enable) {
1271 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1272 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1273 WM8994_AIF2CLK_ENA_MASK,
1274 WM8994_AIF2CLK_ENA);
1275 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1276 wm8994->aif2clk_enable = 0;
1281 /* We may also have postponed startup of DSP, handle that. */
1282 wm8958_aif_ev(w, kcontrol, event);
1287 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1288 struct snd_kcontrol *kcontrol, int event)
1290 struct snd_soc_codec *codec = w->codec;
1291 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1294 case SND_SOC_DAPM_POST_PMD:
1295 if (wm8994->aif1clk_disable) {
1296 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1297 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1298 WM8994_AIF1CLK_ENA_MASK, 0);
1299 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1300 wm8994->aif1clk_disable = 0;
1302 if (wm8994->aif2clk_disable) {
1303 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1304 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1305 WM8994_AIF2CLK_ENA_MASK, 0);
1306 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1307 wm8994->aif2clk_disable = 0;
1315 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1316 struct snd_kcontrol *kcontrol, int event)
1318 late_enable_ev(w, kcontrol, event);
1322 static int micbias_ev(struct snd_soc_dapm_widget *w,
1323 struct snd_kcontrol *kcontrol, int event)
1325 late_enable_ev(w, kcontrol, event);
1329 static int dac_ev(struct snd_soc_dapm_widget *w,
1330 struct snd_kcontrol *kcontrol, int event)
1332 struct snd_soc_codec *codec = w->codec;
1333 unsigned int mask = 1 << w->shift;
1335 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1340 static const char *adc_mux_text[] = {
1345 static const struct soc_enum adc_enum =
1346 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1348 static const struct snd_kcontrol_new adcl_mux =
1349 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1351 static const struct snd_kcontrol_new adcr_mux =
1352 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1354 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1355 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1356 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1357 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1358 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1359 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1362 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1363 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1364 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1365 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1366 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1367 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1370 /* Debugging; dump chip status after DAPM transitions */
1371 static int post_ev(struct snd_soc_dapm_widget *w,
1372 struct snd_kcontrol *kcontrol, int event)
1374 struct snd_soc_codec *codec = w->codec;
1375 dev_dbg(codec->dev, "SRC status: %x\n",
1377 WM8994_RATE_STATUS));
1381 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1382 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1384 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1388 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1389 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1391 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1395 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1396 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1398 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1402 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1403 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1405 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1409 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1410 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1416 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1418 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1422 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1423 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1429 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1431 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1435 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1436 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1437 .info = snd_soc_info_volsw, \
1438 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1439 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1441 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1442 struct snd_ctl_elem_value *ucontrol)
1444 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1445 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1446 struct snd_soc_codec *codec = w->codec;
1449 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1451 wm_hubs_update_class_w(codec);
1456 static const struct snd_kcontrol_new dac1l_mix[] = {
1457 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1463 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1465 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1469 static const struct snd_kcontrol_new dac1r_mix[] = {
1470 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1476 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1478 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1482 static const char *sidetone_text[] = {
1483 "ADC/DMIC1", "DMIC2",
1486 static const struct soc_enum sidetone1_enum =
1487 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1489 static const struct snd_kcontrol_new sidetone1_mux =
1490 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1492 static const struct soc_enum sidetone2_enum =
1493 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1495 static const struct snd_kcontrol_new sidetone2_mux =
1496 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1498 static const char *aif1dac_text[] = {
1499 "AIF1DACDAT", "AIF3DACDAT",
1502 static const char *loopback_text[] = {
1506 static const struct soc_enum aif1_loopback_enum =
1507 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, WM8994_AIF1_LOOPBACK_SHIFT, 2,
1510 static const struct snd_kcontrol_new aif1_loopback =
1511 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1513 static const struct soc_enum aif2_loopback_enum =
1514 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, WM8994_AIF2_LOOPBACK_SHIFT, 2,
1517 static const struct snd_kcontrol_new aif2_loopback =
1518 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1520 static const struct soc_enum aif1dac_enum =
1521 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1523 static const struct snd_kcontrol_new aif1dac_mux =
1524 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1526 static const char *aif2dac_text[] = {
1527 "AIF2DACDAT", "AIF3DACDAT",
1530 static const struct soc_enum aif2dac_enum =
1531 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1533 static const struct snd_kcontrol_new aif2dac_mux =
1534 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1536 static const char *aif2adc_text[] = {
1537 "AIF2ADCDAT", "AIF3DACDAT",
1540 static const struct soc_enum aif2adc_enum =
1541 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1543 static const struct snd_kcontrol_new aif2adc_mux =
1544 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1546 static const char *aif3adc_text[] = {
1547 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1550 static const struct soc_enum wm8994_aif3adc_enum =
1551 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1553 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1554 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1556 static const struct soc_enum wm8958_aif3adc_enum =
1557 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1559 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1560 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1562 static const char *mono_pcm_out_text[] = {
1563 "None", "AIF2ADCL", "AIF2ADCR",
1566 static const struct soc_enum mono_pcm_out_enum =
1567 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1569 static const struct snd_kcontrol_new mono_pcm_out_mux =
1570 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1572 static const char *aif2dac_src_text[] = {
1576 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1577 static const struct soc_enum aif2dacl_src_enum =
1578 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1580 static const struct snd_kcontrol_new aif2dacl_src_mux =
1581 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1583 static const struct soc_enum aif2dacr_src_enum =
1584 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1586 static const struct snd_kcontrol_new aif2dacr_src_mux =
1587 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1589 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1590 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1591 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1592 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1593 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1595 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1596 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1597 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1598 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1599 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1600 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1601 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1602 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1603 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1604 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1606 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1607 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1608 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1609 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1610 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1611 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1612 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1613 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1614 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1615 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1617 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1620 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1621 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1622 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1623 SND_SOC_DAPM_PRE_PMD),
1624 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1625 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1626 SND_SOC_DAPM_PRE_PMD),
1627 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1628 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1629 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1630 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1631 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1632 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1633 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1636 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1637 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1638 dac_ev, SND_SOC_DAPM_PRE_PMU),
1639 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1640 dac_ev, SND_SOC_DAPM_PRE_PMU),
1641 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1642 dac_ev, SND_SOC_DAPM_PRE_PMU),
1643 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1644 dac_ev, SND_SOC_DAPM_PRE_PMU),
1647 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1648 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1649 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1650 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1651 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1654 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1655 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1656 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1657 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1658 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1661 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1662 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1663 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1666 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1667 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1668 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1669 SND_SOC_DAPM_INPUT("Clock"),
1671 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1672 SND_SOC_DAPM_PRE_PMU),
1673 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1674 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1676 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1677 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1678 SND_SOC_DAPM_PRE_PMD),
1680 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1681 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1682 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1684 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1685 0, SND_SOC_NOPM, 9, 0),
1686 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1687 0, SND_SOC_NOPM, 8, 0),
1688 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1689 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1690 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1691 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1692 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1693 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1695 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1696 0, SND_SOC_NOPM, 11, 0),
1697 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1698 0, SND_SOC_NOPM, 10, 0),
1699 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1700 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1701 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1702 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1703 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1704 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1706 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1707 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1708 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1709 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1711 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1712 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1713 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1714 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1716 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1717 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1718 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1719 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1721 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1722 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1724 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1725 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1726 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1727 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1729 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1730 SND_SOC_NOPM, 13, 0),
1731 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1732 SND_SOC_NOPM, 12, 0),
1733 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1734 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1735 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1736 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1737 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1738 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1740 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1741 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1742 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1743 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1745 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1746 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1747 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1749 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1750 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1752 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1754 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1755 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1756 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1757 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1759 /* Power is done with the muxes since the ADC power also controls the
1760 * downsampling chain, the chip will automatically manage the analogue
1761 * specific portions.
1763 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1764 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1766 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1767 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1769 SND_SOC_DAPM_POST("Debug log", post_ev),
1772 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1773 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1776 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1777 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1778 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1779 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1780 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1781 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1784 static const struct snd_soc_dapm_route intercon[] = {
1785 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1786 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1788 { "DSP1CLK", NULL, "CLK_SYS" },
1789 { "DSP2CLK", NULL, "CLK_SYS" },
1790 { "DSPINTCLK", NULL, "CLK_SYS" },
1792 { "AIF1ADC1L", NULL, "AIF1CLK" },
1793 { "AIF1ADC1L", NULL, "DSP1CLK" },
1794 { "AIF1ADC1R", NULL, "AIF1CLK" },
1795 { "AIF1ADC1R", NULL, "DSP1CLK" },
1796 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1798 { "AIF1DAC1L", NULL, "AIF1CLK" },
1799 { "AIF1DAC1L", NULL, "DSP1CLK" },
1800 { "AIF1DAC1R", NULL, "AIF1CLK" },
1801 { "AIF1DAC1R", NULL, "DSP1CLK" },
1802 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1804 { "AIF1ADC2L", NULL, "AIF1CLK" },
1805 { "AIF1ADC2L", NULL, "DSP1CLK" },
1806 { "AIF1ADC2R", NULL, "AIF1CLK" },
1807 { "AIF1ADC2R", NULL, "DSP1CLK" },
1808 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1810 { "AIF1DAC2L", NULL, "AIF1CLK" },
1811 { "AIF1DAC2L", NULL, "DSP1CLK" },
1812 { "AIF1DAC2R", NULL, "AIF1CLK" },
1813 { "AIF1DAC2R", NULL, "DSP1CLK" },
1814 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1816 { "AIF2ADCL", NULL, "AIF2CLK" },
1817 { "AIF2ADCL", NULL, "DSP2CLK" },
1818 { "AIF2ADCR", NULL, "AIF2CLK" },
1819 { "AIF2ADCR", NULL, "DSP2CLK" },
1820 { "AIF2ADCR", NULL, "DSPINTCLK" },
1822 { "AIF2DACL", NULL, "AIF2CLK" },
1823 { "AIF2DACL", NULL, "DSP2CLK" },
1824 { "AIF2DACR", NULL, "AIF2CLK" },
1825 { "AIF2DACR", NULL, "DSP2CLK" },
1826 { "AIF2DACR", NULL, "DSPINTCLK" },
1828 { "DMIC1L", NULL, "DMIC1DAT" },
1829 { "DMIC1L", NULL, "CLK_SYS" },
1830 { "DMIC1R", NULL, "DMIC1DAT" },
1831 { "DMIC1R", NULL, "CLK_SYS" },
1832 { "DMIC2L", NULL, "DMIC2DAT" },
1833 { "DMIC2L", NULL, "CLK_SYS" },
1834 { "DMIC2R", NULL, "DMIC2DAT" },
1835 { "DMIC2R", NULL, "CLK_SYS" },
1837 { "ADCL", NULL, "AIF1CLK" },
1838 { "ADCL", NULL, "DSP1CLK" },
1839 { "ADCL", NULL, "DSPINTCLK" },
1841 { "ADCR", NULL, "AIF1CLK" },
1842 { "ADCR", NULL, "DSP1CLK" },
1843 { "ADCR", NULL, "DSPINTCLK" },
1845 { "ADCL Mux", "ADC", "ADCL" },
1846 { "ADCL Mux", "DMIC", "DMIC1L" },
1847 { "ADCR Mux", "ADC", "ADCR" },
1848 { "ADCR Mux", "DMIC", "DMIC1R" },
1850 { "DAC1L", NULL, "AIF1CLK" },
1851 { "DAC1L", NULL, "DSP1CLK" },
1852 { "DAC1L", NULL, "DSPINTCLK" },
1854 { "DAC1R", NULL, "AIF1CLK" },
1855 { "DAC1R", NULL, "DSP1CLK" },
1856 { "DAC1R", NULL, "DSPINTCLK" },
1858 { "DAC2L", NULL, "AIF2CLK" },
1859 { "DAC2L", NULL, "DSP2CLK" },
1860 { "DAC2L", NULL, "DSPINTCLK" },
1862 { "DAC2R", NULL, "AIF2DACR" },
1863 { "DAC2R", NULL, "AIF2CLK" },
1864 { "DAC2R", NULL, "DSP2CLK" },
1865 { "DAC2R", NULL, "DSPINTCLK" },
1867 { "TOCLK", NULL, "CLK_SYS" },
1869 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1870 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1871 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1873 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1874 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1875 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1878 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1879 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1880 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1882 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1883 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1884 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1886 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1887 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1888 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1890 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1891 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1892 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1894 /* Pin level routing for AIF3 */
1895 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1896 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1897 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1898 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1900 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1901 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1902 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1903 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1904 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1905 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1906 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1909 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1910 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1911 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1912 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1913 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1915 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1916 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1917 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1918 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1919 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1921 /* DAC2/AIF2 outputs */
1922 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1923 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1924 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1925 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1926 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1927 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1929 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1930 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1931 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1932 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1933 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1934 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1936 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1937 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1938 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1939 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1941 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1944 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1945 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1946 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1947 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1948 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1949 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1950 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1951 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1954 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1955 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1956 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1957 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1960 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1961 { "Left Sidetone", "DMIC2", "DMIC2L" },
1962 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1963 { "Right Sidetone", "DMIC2", "DMIC2R" },
1966 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1967 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1969 { "SPKL", "DAC1 Switch", "DAC1L" },
1970 { "SPKL", "DAC2 Switch", "DAC2L" },
1972 { "SPKR", "DAC1 Switch", "DAC1R" },
1973 { "SPKR", "DAC2 Switch", "DAC2R" },
1975 { "Left Headphone Mux", "DAC", "DAC1L" },
1976 { "Right Headphone Mux", "DAC", "DAC1R" },
1979 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1980 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1981 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1982 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1983 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1984 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1985 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1986 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1987 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1990 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1991 { "DAC1L", NULL, "DAC1L Mixer" },
1992 { "DAC1R", NULL, "DAC1R Mixer" },
1993 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1994 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1997 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1998 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1999 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
2000 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2001 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2002 { "MICBIAS1", NULL, "CLK_SYS" },
2003 { "MICBIAS1", NULL, "MICBIAS Supply" },
2004 { "MICBIAS2", NULL, "CLK_SYS" },
2005 { "MICBIAS2", NULL, "MICBIAS Supply" },
2008 static const struct snd_soc_dapm_route wm8994_intercon[] = {
2009 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2010 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2011 { "MICBIAS1", NULL, "VMID" },
2012 { "MICBIAS2", NULL, "VMID" },
2015 static const struct snd_soc_dapm_route wm8958_intercon[] = {
2016 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2017 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2019 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2020 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2021 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2022 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2024 { "AIF3DACDAT", NULL, "AIF3" },
2025 { "AIF3ADCDAT", NULL, "AIF3" },
2027 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2028 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2030 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2033 /* The size in bits of the FLL divide multiplied by 10
2034 * to allow rounding later */
2035 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2046 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2047 int freq_in, int freq_out)
2050 unsigned int K, Ndiv, Nmod, gcd_fll;
2052 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2054 /* Scale the input frequency down to <= 13.5MHz */
2055 fll->clk_ref_div = 0;
2056 while (freq_in > 13500000) {
2060 if (fll->clk_ref_div > 3)
2063 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2065 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2067 while (freq_out * (fll->outdiv + 1) < 90000000) {
2069 if (fll->outdiv > 63)
2072 freq_out *= fll->outdiv + 1;
2073 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2075 if (freq_in > 1000000) {
2076 fll->fll_fratio = 0;
2077 } else if (freq_in > 256000) {
2078 fll->fll_fratio = 1;
2080 } else if (freq_in > 128000) {
2081 fll->fll_fratio = 2;
2083 } else if (freq_in > 64000) {
2084 fll->fll_fratio = 3;
2087 fll->fll_fratio = 4;
2090 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2092 /* Now, calculate N.K */
2093 Ndiv = freq_out / freq_in;
2096 Nmod = freq_out % freq_in;
2097 pr_debug("Nmod=%d\n", Nmod);
2099 switch (control->type) {
2101 /* Calculate fractional part - scale up so we can round. */
2102 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2104 do_div(Kpart, freq_in);
2106 K = Kpart & 0xFFFFFFFF;
2111 /* Move down to proper range now rounding is done */
2115 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2119 gcd_fll = gcd(freq_out, freq_in);
2121 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2122 fll->lambda = freq_in / gcd_fll;
2129 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2130 unsigned int freq_in, unsigned int freq_out)
2132 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2133 struct wm8994 *control = wm8994->wm8994;
2134 int reg_offset, ret;
2136 u16 reg, clk1, aif_reg, aif_src;
2137 unsigned long timeout;
2155 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2156 was_enabled = reg & WM8994_FLL1_ENA;
2160 /* Allow no source specification when stopping */
2163 src = wm8994->fll[id].src;
2165 case WM8994_FLL_SRC_MCLK1:
2166 case WM8994_FLL_SRC_MCLK2:
2167 case WM8994_FLL_SRC_LRCLK:
2168 case WM8994_FLL_SRC_BCLK:
2170 case WM8994_FLL_SRC_INTERNAL:
2172 freq_out = 12000000;
2178 /* Are we changing anything? */
2179 if (wm8994->fll[id].src == src &&
2180 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2183 /* If we're stopping the FLL redo the old config - no
2184 * registers will actually be written but we avoid GCC flow
2185 * analysis bugs spewing warnings.
2188 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2190 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2191 wm8994->fll[id].out);
2195 /* Make sure that we're not providing SYSCLK right now */
2196 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2197 if (clk1 & WM8994_SYSCLK_SRC)
2198 aif_reg = WM8994_AIF2_CLOCKING_1;
2200 aif_reg = WM8994_AIF1_CLOCKING_1;
2201 reg = snd_soc_read(codec, aif_reg);
2203 if ((reg & WM8994_AIF1CLK_ENA) &&
2204 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2205 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2210 /* We always need to disable the FLL while reconfiguring */
2211 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2212 WM8994_FLL1_ENA, 0);
2214 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2215 freq_in == freq_out && freq_out) {
2216 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2217 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2218 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2222 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2223 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2224 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2225 WM8994_FLL1_OUTDIV_MASK |
2226 WM8994_FLL1_FRATIO_MASK, reg);
2228 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2229 WM8994_FLL1_K_MASK, fll.k);
2231 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2233 fll.n << WM8994_FLL1_N_SHIFT);
2236 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2237 WM8958_FLL1_LAMBDA_MASK,
2239 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2240 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2242 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2243 WM8958_FLL1_EFS_ENA, 0);
2246 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2247 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2248 WM8994_FLL1_REFCLK_DIV_MASK |
2249 WM8994_FLL1_REFCLK_SRC_MASK,
2250 ((src == WM8994_FLL_SRC_INTERNAL)
2251 << WM8994_FLL1_FRC_NCO_SHIFT) |
2252 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2255 /* Clear any pending completion from a previous failure */
2256 try_wait_for_completion(&wm8994->fll_locked[id]);
2258 /* Enable (with fractional mode if required) */
2260 /* Enable VMID if we need it */
2262 active_reference(codec);
2264 switch (control->type) {
2266 vmid_reference(codec);
2269 if (control->revision < 1)
2270 vmid_reference(codec);
2277 reg = WM8994_FLL1_ENA;
2280 reg |= WM8994_FLL1_FRAC;
2281 if (src == WM8994_FLL_SRC_INTERNAL)
2282 reg |= WM8994_FLL1_OSC_ENA;
2284 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2285 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2286 WM8994_FLL1_FRAC, reg);
2288 if (wm8994->fll_locked_irq) {
2289 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2290 msecs_to_jiffies(10));
2292 dev_warn(codec->dev,
2293 "Timed out waiting for FLL lock\n");
2299 switch (control->type) {
2301 vmid_dereference(codec);
2304 if (control->revision < 1)
2305 vmid_dereference(codec);
2311 active_dereference(codec);
2316 wm8994->fll[id].in = freq_in;
2317 wm8994->fll[id].out = freq_out;
2318 wm8994->fll[id].src = src;
2320 configure_clock(codec);
2323 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2326 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2327 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2329 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2330 & WM8994_AIF1CLK_RATE_MASK;
2331 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2332 & WM8994_AIF1CLK_RATE_MASK;
2334 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2335 WM8994_AIF1CLK_RATE_MASK, 0x1);
2336 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2337 WM8994_AIF2CLK_RATE_MASK, 0x1);
2338 } else if (wm8994->aifdiv[0]) {
2339 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2340 WM8994_AIF1CLK_RATE_MASK,
2342 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2343 WM8994_AIF2CLK_RATE_MASK,
2346 wm8994->aifdiv[0] = 0;
2347 wm8994->aifdiv[1] = 0;
2353 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2355 struct completion *completion = data;
2357 complete(completion);
2362 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2364 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2365 unsigned int freq_in, unsigned int freq_out)
2367 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2370 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2371 int clk_id, unsigned int freq, int dir)
2373 struct snd_soc_codec *codec = dai->codec;
2374 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2383 /* AIF3 shares clocking with AIF1/2 */
2388 case WM8994_SYSCLK_MCLK1:
2389 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2390 wm8994->mclk[0] = freq;
2391 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2395 case WM8994_SYSCLK_MCLK2:
2396 /* TODO: Set GPIO AF */
2397 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2398 wm8994->mclk[1] = freq;
2399 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2403 case WM8994_SYSCLK_FLL1:
2404 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2405 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2408 case WM8994_SYSCLK_FLL2:
2409 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2410 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2413 case WM8994_SYSCLK_OPCLK:
2414 /* Special case - a division (times 10) is given and
2415 * no effect on main clocking.
2418 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2419 if (opclk_divs[i] == freq)
2421 if (i == ARRAY_SIZE(opclk_divs))
2423 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2424 WM8994_OPCLK_DIV_MASK, i);
2425 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2426 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2428 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2429 WM8994_OPCLK_ENA, 0);
2436 configure_clock(codec);
2439 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2442 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2443 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2445 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2446 & WM8994_AIF1CLK_RATE_MASK;
2447 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2448 & WM8994_AIF1CLK_RATE_MASK;
2450 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2451 WM8994_AIF1CLK_RATE_MASK, 0x1);
2452 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2453 WM8994_AIF2CLK_RATE_MASK, 0x1);
2454 } else if (wm8994->aifdiv[0]) {
2455 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2456 WM8994_AIF1CLK_RATE_MASK,
2458 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2459 WM8994_AIF2CLK_RATE_MASK,
2462 wm8994->aifdiv[0] = 0;
2463 wm8994->aifdiv[1] = 0;
2469 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2470 enum snd_soc_bias_level level)
2472 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2473 struct wm8994 *control = wm8994->wm8994;
2475 wm_hubs_set_bias_level(codec, level);
2478 case SND_SOC_BIAS_ON:
2481 case SND_SOC_BIAS_PREPARE:
2482 /* MICBIAS into regulating mode */
2483 switch (control->type) {
2486 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2487 WM8958_MICB1_MODE, 0);
2488 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2489 WM8958_MICB2_MODE, 0);
2495 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2496 active_reference(codec);
2499 case SND_SOC_BIAS_STANDBY:
2500 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2501 switch (control->type) {
2503 if (control->revision == 0) {
2504 /* Optimise performance for rev A */
2505 snd_soc_update_bits(codec,
2506 WM8958_CHARGE_PUMP_2,
2516 /* Discharge LINEOUT1 & 2 */
2517 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2518 WM8994_LINEOUT1_DISCH |
2519 WM8994_LINEOUT2_DISCH,
2520 WM8994_LINEOUT1_DISCH |
2521 WM8994_LINEOUT2_DISCH);
2524 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2525 active_dereference(codec);
2527 /* MICBIAS into bypass mode on newer devices */
2528 switch (control->type) {
2531 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2534 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2543 case SND_SOC_BIAS_OFF:
2544 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2545 wm8994->cur_fw = NULL;
2549 codec->dapm.bias_level = level;
2554 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2556 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2559 case WM8994_VMID_NORMAL:
2560 if (wm8994->hubs.lineout1_se) {
2561 snd_soc_dapm_disable_pin(&codec->dapm,
2562 "LINEOUT1N Driver");
2563 snd_soc_dapm_disable_pin(&codec->dapm,
2564 "LINEOUT1P Driver");
2566 if (wm8994->hubs.lineout2_se) {
2567 snd_soc_dapm_disable_pin(&codec->dapm,
2568 "LINEOUT2N Driver");
2569 snd_soc_dapm_disable_pin(&codec->dapm,
2570 "LINEOUT2P Driver");
2573 /* Do the sync with the old mode to allow it to clean up */
2574 snd_soc_dapm_sync(&codec->dapm);
2575 wm8994->vmid_mode = mode;
2578 case WM8994_VMID_FORCE:
2579 if (wm8994->hubs.lineout1_se) {
2580 snd_soc_dapm_force_enable_pin(&codec->dapm,
2581 "LINEOUT1N Driver");
2582 snd_soc_dapm_force_enable_pin(&codec->dapm,
2583 "LINEOUT1P Driver");
2585 if (wm8994->hubs.lineout2_se) {
2586 snd_soc_dapm_force_enable_pin(&codec->dapm,
2587 "LINEOUT2N Driver");
2588 snd_soc_dapm_force_enable_pin(&codec->dapm,
2589 "LINEOUT2P Driver");
2592 wm8994->vmid_mode = mode;
2593 snd_soc_dapm_sync(&codec->dapm);
2603 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2605 struct snd_soc_codec *codec = dai->codec;
2606 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2607 struct wm8994 *control = wm8994->wm8994;
2618 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2619 aif1_reg = WM8994_AIF1_CONTROL_1;
2620 dac_reg = WM8994_AIF1DAC_LRCLK;
2621 adc_reg = WM8994_AIF1ADC_LRCLK;
2624 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2625 aif1_reg = WM8994_AIF2_CONTROL_1;
2626 dac_reg = WM8994_AIF1DAC_LRCLK;
2627 adc_reg = WM8994_AIF1ADC_LRCLK;
2633 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2634 case SND_SOC_DAIFMT_CBS_CFS:
2636 case SND_SOC_DAIFMT_CBM_CFM:
2637 ms = WM8994_AIF1_MSTR;
2643 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2644 case SND_SOC_DAIFMT_DSP_B:
2645 aif1 |= WM8994_AIF1_LRCLK_INV;
2646 lrclk |= WM8958_AIF1_LRCLK_INV;
2647 case SND_SOC_DAIFMT_DSP_A:
2650 case SND_SOC_DAIFMT_I2S:
2653 case SND_SOC_DAIFMT_RIGHT_J:
2655 case SND_SOC_DAIFMT_LEFT_J:
2662 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2663 case SND_SOC_DAIFMT_DSP_A:
2664 case SND_SOC_DAIFMT_DSP_B:
2665 /* frame inversion not valid for DSP modes */
2666 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2667 case SND_SOC_DAIFMT_NB_NF:
2669 case SND_SOC_DAIFMT_IB_NF:
2670 aif1 |= WM8994_AIF1_BCLK_INV;
2677 case SND_SOC_DAIFMT_I2S:
2678 case SND_SOC_DAIFMT_RIGHT_J:
2679 case SND_SOC_DAIFMT_LEFT_J:
2680 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2681 case SND_SOC_DAIFMT_NB_NF:
2683 case SND_SOC_DAIFMT_IB_IF:
2684 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2685 lrclk |= WM8958_AIF1_LRCLK_INV;
2687 case SND_SOC_DAIFMT_IB_NF:
2688 aif1 |= WM8994_AIF1_BCLK_INV;
2690 case SND_SOC_DAIFMT_NB_IF:
2691 aif1 |= WM8994_AIF1_LRCLK_INV;
2692 lrclk |= WM8958_AIF1_LRCLK_INV;
2702 /* The AIF2 format configuration needs to be mirrored to AIF3
2703 * on WM8958 if it's in use so just do it all the time. */
2704 switch (control->type) {
2708 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2709 WM8994_AIF1_LRCLK_INV |
2710 WM8958_AIF3_FMT_MASK, aif1);
2717 snd_soc_update_bits(codec, aif1_reg,
2718 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2719 WM8994_AIF1_FMT_MASK,
2721 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2723 snd_soc_update_bits(codec, dac_reg,
2724 WM8958_AIF1_LRCLK_INV, lrclk);
2725 snd_soc_update_bits(codec, adc_reg,
2726 WM8958_AIF1_LRCLK_INV, lrclk);
2747 static int fs_ratios[] = {
2748 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2751 static int bclk_divs[] = {
2752 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2753 640, 880, 960, 1280, 1760, 1920
2756 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2757 struct snd_pcm_hw_params *params,
2758 struct snd_soc_dai *dai)
2760 struct snd_soc_codec *codec = dai->codec;
2761 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2762 struct wm8994 *control = wm8994->wm8994;
2763 struct wm8994_pdata *pdata = &control->pdata;
2774 int id = dai->id - 1;
2776 int i, cur_val, best_val, bclk_rate, best;
2780 aif1_reg = WM8994_AIF1_CONTROL_1;
2781 aif2_reg = WM8994_AIF1_CONTROL_2;
2782 bclk_reg = WM8994_AIF1_BCLK;
2783 rate_reg = WM8994_AIF1_RATE;
2784 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2785 wm8994->lrclk_shared[0]) {
2786 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2788 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2789 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2793 aif1_reg = WM8994_AIF2_CONTROL_1;
2794 aif2_reg = WM8994_AIF2_CONTROL_2;
2795 bclk_reg = WM8994_AIF2_BCLK;
2796 rate_reg = WM8994_AIF2_RATE;
2797 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2798 wm8994->lrclk_shared[1]) {
2799 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2801 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2802 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2809 bclk_rate = params_rate(params);
2810 switch (params_format(params)) {
2811 case SNDRV_PCM_FORMAT_S16_LE:
2814 case SNDRV_PCM_FORMAT_S20_3LE:
2818 case SNDRV_PCM_FORMAT_S24_LE:
2822 case SNDRV_PCM_FORMAT_S32_LE:
2830 wm8994->channels[id] = params_channels(params);
2831 if (pdata->max_channels_clocked[id] &&
2832 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2833 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2834 pdata->max_channels_clocked[id], wm8994->channels[id]);
2835 wm8994->channels[id] = pdata->max_channels_clocked[id];
2838 switch (wm8994->channels[id]) {
2848 /* Try to find an appropriate sample rate; look for an exact match. */
2849 for (i = 0; i < ARRAY_SIZE(srs); i++)
2850 if (srs[i].rate == params_rate(params))
2852 if (i == ARRAY_SIZE(srs))
2854 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2856 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2857 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2858 dai->id, wm8994->aifclk[id], bclk_rate);
2860 if (wm8994->channels[id] == 1 &&
2861 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2862 aif2 |= WM8994_AIF1_MONO;
2864 if (wm8994->aifclk[id] == 0) {
2865 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2869 /* AIFCLK/fs ratio; look for a close match in either direction */
2871 best_val = abs((fs_ratios[0] * params_rate(params))
2872 - wm8994->aifclk[id]);
2873 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2874 cur_val = abs((fs_ratios[i] * params_rate(params))
2875 - wm8994->aifclk[id]);
2876 if (cur_val >= best_val)
2881 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2882 dai->id, fs_ratios[best]);
2885 /* We may not get quite the right frequency if using
2886 * approximate clocks so look for the closest match that is
2887 * higher than the target (we need to ensure that there enough
2888 * BCLKs to clock out the samples).
2891 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2892 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2893 if (cur_val < 0) /* BCLK table is sorted */
2897 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2898 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2899 bclk_divs[best], bclk_rate);
2900 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2902 lrclk = bclk_rate / params_rate(params);
2904 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2908 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2909 lrclk, bclk_rate / lrclk);
2911 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2912 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2913 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2914 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2916 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2917 WM8994_AIF1CLK_RATE_MASK, rate_val);
2919 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2922 wm8994->dac_rates[0] = params_rate(params);
2923 wm8994_set_retune_mobile(codec, 0);
2924 wm8994_set_retune_mobile(codec, 1);
2927 wm8994->dac_rates[1] = params_rate(params);
2928 wm8994_set_retune_mobile(codec, 2);
2936 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2937 struct snd_pcm_hw_params *params,
2938 struct snd_soc_dai *dai)
2940 struct snd_soc_codec *codec = dai->codec;
2941 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2942 struct wm8994 *control = wm8994->wm8994;
2948 switch (control->type) {
2951 aif1_reg = WM8958_AIF3_CONTROL_1;
2961 switch (params_format(params)) {
2962 case SNDRV_PCM_FORMAT_S16_LE:
2964 case SNDRV_PCM_FORMAT_S20_3LE:
2967 case SNDRV_PCM_FORMAT_S24_LE:
2970 case SNDRV_PCM_FORMAT_S32_LE:
2977 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2980 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2982 struct snd_soc_codec *codec = codec_dai->codec;
2986 switch (codec_dai->id) {
2988 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2991 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2998 reg = WM8994_AIF1DAC1_MUTE;
3002 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3007 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3009 struct snd_soc_codec *codec = codec_dai->codec;
3012 switch (codec_dai->id) {
3014 reg = WM8994_AIF1_MASTER_SLAVE;
3015 mask = WM8994_AIF1_TRI;
3018 reg = WM8994_AIF2_MASTER_SLAVE;
3019 mask = WM8994_AIF2_TRI;
3030 return snd_soc_update_bits(codec, reg, mask, val);
3033 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3035 struct snd_soc_codec *codec = dai->codec;
3037 /* Disable the pulls on the AIF if we're using it to save power. */
3038 snd_soc_update_bits(codec, WM8994_GPIO_3,
3039 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3040 snd_soc_update_bits(codec, WM8994_GPIO_4,
3041 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3042 snd_soc_update_bits(codec, WM8994_GPIO_5,
3043 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3048 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3050 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3051 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3053 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3054 .set_sysclk = wm8994_set_dai_sysclk,
3055 .set_fmt = wm8994_set_dai_fmt,
3056 .hw_params = wm8994_hw_params,
3057 .digital_mute = wm8994_aif_mute,
3058 .set_pll = wm8994_set_fll,
3059 .set_tristate = wm8994_set_tristate,
3062 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3063 .set_sysclk = wm8994_set_dai_sysclk,
3064 .set_fmt = wm8994_set_dai_fmt,
3065 .hw_params = wm8994_hw_params,
3066 .digital_mute = wm8994_aif_mute,
3067 .set_pll = wm8994_set_fll,
3068 .set_tristate = wm8994_set_tristate,
3071 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3072 .hw_params = wm8994_aif3_hw_params,
3075 static struct snd_soc_dai_driver wm8994_dai[] = {
3077 .name = "wm8994-aif1",
3080 .stream_name = "AIF1 Playback",
3083 .rates = WM8994_RATES,
3084 .formats = WM8994_FORMATS,
3088 .stream_name = "AIF1 Capture",
3091 .rates = WM8994_RATES,
3092 .formats = WM8994_FORMATS,
3095 .ops = &wm8994_aif1_dai_ops,
3098 .name = "wm8994-aif2",
3101 .stream_name = "AIF2 Playback",
3104 .rates = WM8994_RATES,
3105 .formats = WM8994_FORMATS,
3109 .stream_name = "AIF2 Capture",
3112 .rates = WM8994_RATES,
3113 .formats = WM8994_FORMATS,
3116 .probe = wm8994_aif2_probe,
3117 .ops = &wm8994_aif2_dai_ops,
3120 .name = "wm8994-aif3",
3123 .stream_name = "AIF3 Playback",
3126 .rates = WM8994_RATES,
3127 .formats = WM8994_FORMATS,
3131 .stream_name = "AIF3 Capture",
3134 .rates = WM8994_RATES,
3135 .formats = WM8994_FORMATS,
3138 .ops = &wm8994_aif3_dai_ops,
3143 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3145 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3148 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3149 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3150 sizeof(struct wm8994_fll_config));
3151 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3153 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3157 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3162 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3164 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3167 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3168 if (!wm8994->fll_suspend[i].out)
3171 ret = _wm8994_set_fll(codec, i + 1,
3172 wm8994->fll_suspend[i].src,
3173 wm8994->fll_suspend[i].in,
3174 wm8994->fll_suspend[i].out);
3176 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3183 #define wm8994_codec_suspend NULL
3184 #define wm8994_codec_resume NULL
3187 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3189 struct snd_soc_codec *codec = wm8994->hubs.codec;
3190 struct wm8994 *control = wm8994->wm8994;
3191 struct wm8994_pdata *pdata = &control->pdata;
3192 struct snd_kcontrol_new controls[] = {
3193 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3194 wm8994->retune_mobile_enum,
3195 wm8994_get_retune_mobile_enum,
3196 wm8994_put_retune_mobile_enum),
3197 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3198 wm8994->retune_mobile_enum,
3199 wm8994_get_retune_mobile_enum,
3200 wm8994_put_retune_mobile_enum),
3201 SOC_ENUM_EXT("AIF2 EQ Mode",
3202 wm8994->retune_mobile_enum,
3203 wm8994_get_retune_mobile_enum,
3204 wm8994_put_retune_mobile_enum),
3209 /* We need an array of texts for the enum API but the number
3210 * of texts is likely to be less than the number of
3211 * configurations due to the sample rate dependency of the
3212 * configurations. */
3213 wm8994->num_retune_mobile_texts = 0;
3214 wm8994->retune_mobile_texts = NULL;
3215 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3216 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3217 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3218 wm8994->retune_mobile_texts[j]) == 0)
3222 if (j != wm8994->num_retune_mobile_texts)
3225 /* Expand the array... */
3226 t = krealloc(wm8994->retune_mobile_texts,
3228 (wm8994->num_retune_mobile_texts + 1),
3233 /* ...store the new entry... */
3234 t[wm8994->num_retune_mobile_texts] =
3235 pdata->retune_mobile_cfgs[i].name;
3237 /* ...and remember the new version. */
3238 wm8994->num_retune_mobile_texts++;
3239 wm8994->retune_mobile_texts = t;
3242 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3243 wm8994->num_retune_mobile_texts);
3245 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3246 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3248 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3249 ARRAY_SIZE(controls));
3251 dev_err(wm8994->hubs.codec->dev,
3252 "Failed to add ReTune Mobile controls: %d\n", ret);
3255 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3257 struct snd_soc_codec *codec = wm8994->hubs.codec;
3258 struct wm8994 *control = wm8994->wm8994;
3259 struct wm8994_pdata *pdata = &control->pdata;
3265 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3266 pdata->lineout2_diff,
3273 pdata->micbias1_lvl,
3274 pdata->micbias2_lvl);
3276 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3278 if (pdata->num_drc_cfgs) {
3279 struct snd_kcontrol_new controls[] = {
3280 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3281 wm8994_get_drc_enum, wm8994_put_drc_enum),
3282 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3283 wm8994_get_drc_enum, wm8994_put_drc_enum),
3284 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3285 wm8994_get_drc_enum, wm8994_put_drc_enum),
3288 /* We need an array of texts for the enum API */
3289 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3290 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3291 if (!wm8994->drc_texts) {
3292 dev_err(wm8994->hubs.codec->dev,
3293 "Failed to allocate %d DRC config texts\n",
3294 pdata->num_drc_cfgs);
3298 for (i = 0; i < pdata->num_drc_cfgs; i++)
3299 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3301 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3302 wm8994->drc_enum.texts = wm8994->drc_texts;
3304 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3305 ARRAY_SIZE(controls));
3306 for (i = 0; i < WM8994_NUM_DRC; i++)
3307 wm8994_set_drc(codec, i);
3309 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3310 wm8994_drc_controls,
3311 ARRAY_SIZE(wm8994_drc_controls));
3315 dev_err(wm8994->hubs.codec->dev,
3316 "Failed to add DRC mode controls: %d\n", ret);
3319 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3320 pdata->num_retune_mobile_cfgs);
3322 if (pdata->num_retune_mobile_cfgs)
3323 wm8994_handle_retune_mobile_pdata(wm8994);
3325 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3326 ARRAY_SIZE(wm8994_eq_controls));
3328 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3329 if (pdata->micbias[i]) {
3330 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3331 pdata->micbias[i] & 0xffff);
3337 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3339 * @codec: WM8994 codec
3340 * @jack: jack to report detection events on
3341 * @micbias: microphone bias to detect on
3343 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3344 * being used to bring out signals to the processor then only platform
3345 * data configuration is needed for WM8994 and processor GPIOs should
3346 * be configured using snd_soc_jack_add_gpios() instead.
3348 * Configuration of detection levels is available via the micbias1_lvl
3349 * and micbias2_lvl platform data members.
3351 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3354 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3355 struct wm8994_micdet *micdet;
3356 struct wm8994 *control = wm8994->wm8994;
3359 if (control->type != WM8994) {
3360 dev_warn(codec->dev, "Not a WM8994\n");
3366 micdet = &wm8994->micdet[0];
3368 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3371 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3375 micdet = &wm8994->micdet[1];
3377 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3380 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3384 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3389 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3392 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3395 /* Store the configuration */
3396 micdet->jack = jack;
3397 micdet->detecting = true;
3399 /* If either of the jacks is set up then enable detection */
3400 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3401 reg = WM8994_MICD_ENA;
3405 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3407 /* enable MICDET and MICSHRT deboune */
3408 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3409 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3410 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3411 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3413 snd_soc_dapm_sync(&codec->dapm);
3417 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3419 static void wm8994_mic_work(struct work_struct *work)
3421 struct wm8994_priv *priv = container_of(work,
3424 struct regmap *regmap = priv->wm8994->regmap;
3425 struct device *dev = priv->wm8994->dev;
3430 pm_runtime_get_sync(dev);
3432 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®);
3434 dev_err(dev, "Failed to read microphone status: %d\n",
3436 pm_runtime_put(dev);
3440 dev_dbg(dev, "Microphone status: %x\n", reg);
3443 if (reg & WM8994_MIC1_DET_STS) {
3444 if (priv->micdet[0].detecting)
3445 report = SND_JACK_HEADSET;
3447 if (reg & WM8994_MIC1_SHRT_STS) {
3448 if (priv->micdet[0].detecting)
3449 report = SND_JACK_HEADPHONE;
3451 report |= SND_JACK_BTN_0;
3454 priv->micdet[0].detecting = false;
3456 priv->micdet[0].detecting = true;
3458 snd_soc_jack_report(priv->micdet[0].jack, report,
3459 SND_JACK_HEADSET | SND_JACK_BTN_0);
3462 if (reg & WM8994_MIC2_DET_STS) {
3463 if (priv->micdet[1].detecting)
3464 report = SND_JACK_HEADSET;
3466 if (reg & WM8994_MIC2_SHRT_STS) {
3467 if (priv->micdet[1].detecting)
3468 report = SND_JACK_HEADPHONE;
3470 report |= SND_JACK_BTN_0;
3473 priv->micdet[1].detecting = false;
3475 priv->micdet[1].detecting = true;
3477 snd_soc_jack_report(priv->micdet[1].jack, report,
3478 SND_JACK_HEADSET | SND_JACK_BTN_0);
3480 pm_runtime_put(dev);
3483 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3485 struct wm8994_priv *priv = data;
3486 struct snd_soc_codec *codec = priv->hubs.codec;
3488 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3489 trace_snd_soc_jack_irq(dev_name(codec->dev));
3492 pm_wakeup_event(codec->dev, 300);
3494 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3499 static void wm1811_micd_stop(struct snd_soc_codec *codec)
3501 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3503 if (!wm8994->jackdet)
3506 mutex_lock(&wm8994->accdet_lock);
3508 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3510 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3512 mutex_unlock(&wm8994->accdet_lock);
3514 if (wm8994->wm8994->pdata.jd_ext_cap)
3515 snd_soc_dapm_disable_pin(&codec->dapm,
3519 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3521 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3526 report |= SND_JACK_BTN_0;
3529 report |= SND_JACK_BTN_1;
3532 report |= SND_JACK_BTN_2;
3535 report |= SND_JACK_BTN_3;
3538 report |= SND_JACK_BTN_4;
3541 report |= SND_JACK_BTN_5;
3543 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3547 static void wm8958_open_circuit_work(struct work_struct *work)
3549 struct wm8994_priv *wm8994 = container_of(work,
3551 open_circuit_work.work);
3552 struct device *dev = wm8994->wm8994->dev;
3554 wm1811_micd_stop(wm8994->hubs.codec);
3556 mutex_lock(&wm8994->accdet_lock);
3558 dev_dbg(dev, "Reporting open circuit\n");
3560 wm8994->jack_mic = false;
3561 wm8994->mic_detecting = true;
3563 wm8958_micd_set_rate(wm8994->hubs.codec);
3565 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3569 mutex_unlock(&wm8994->accdet_lock);
3572 static void wm8958_mic_id(void *data, u16 status)
3574 struct snd_soc_codec *codec = data;
3575 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3577 /* Either nothing present or just starting detection */
3578 if (!(status & WM8958_MICD_STS)) {
3579 /* If nothing present then clear our statuses */
3580 dev_dbg(codec->dev, "Detected open circuit\n");
3582 schedule_delayed_work(&wm8994->open_circuit_work,
3583 msecs_to_jiffies(2500));
3587 /* If the measurement is showing a high impedence we've got a
3590 if (status & 0x600) {
3591 dev_dbg(codec->dev, "Detected microphone\n");
3593 wm8994->mic_detecting = false;
3594 wm8994->jack_mic = true;
3596 wm8958_micd_set_rate(codec);
3598 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3603 if (status & 0xfc) {
3604 dev_dbg(codec->dev, "Detected headphone\n");
3605 wm8994->mic_detecting = false;
3607 wm8958_micd_set_rate(codec);
3609 /* If we have jackdet that will detect removal */
3610 wm1811_micd_stop(codec);
3612 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3617 /* Deferred mic detection to allow for extra settling time */
3618 static void wm1811_mic_work(struct work_struct *work)
3620 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3622 struct wm8994 *control = wm8994->wm8994;
3623 struct snd_soc_codec *codec = wm8994->hubs.codec;
3625 pm_runtime_get_sync(codec->dev);
3627 /* If required for an external cap force MICBIAS on */
3628 if (control->pdata.jd_ext_cap) {
3629 snd_soc_dapm_force_enable_pin(&codec->dapm,
3631 snd_soc_dapm_sync(&codec->dapm);
3634 mutex_lock(&wm8994->accdet_lock);
3636 dev_dbg(codec->dev, "Starting mic detection\n");
3638 /* Use a user-supplied callback if we have one */
3639 if (wm8994->micd_cb) {
3640 wm8994->micd_cb(wm8994->micd_cb_data);
3643 * Start off measument of microphone impedence to find out
3644 * what's actually there.
3646 wm8994->mic_detecting = true;
3647 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3649 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3650 WM8958_MICD_ENA, WM8958_MICD_ENA);
3653 mutex_unlock(&wm8994->accdet_lock);
3655 pm_runtime_put(codec->dev);
3658 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3660 struct wm8994_priv *wm8994 = data;
3661 struct wm8994 *control = wm8994->wm8994;
3662 struct snd_soc_codec *codec = wm8994->hubs.codec;
3666 pm_runtime_get_sync(codec->dev);
3668 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3670 mutex_lock(&wm8994->accdet_lock);
3672 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3674 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3675 mutex_unlock(&wm8994->accdet_lock);
3676 pm_runtime_put(codec->dev);
3680 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3682 present = reg & WM1811_JACKDET_LVL;
3685 dev_dbg(codec->dev, "Jack detected\n");
3687 wm8958_micd_set_rate(codec);
3689 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3690 WM8958_MICB2_DISCH, 0);
3692 /* Disable debounce while inserted */
3693 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3694 WM1811_JACKDET_DB, 0);
3696 delay = control->pdata.micdet_delay;
3697 schedule_delayed_work(&wm8994->mic_work,
3698 msecs_to_jiffies(delay));
3700 dev_dbg(codec->dev, "Jack not detected\n");
3702 cancel_delayed_work_sync(&wm8994->mic_work);
3704 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3705 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3707 /* Enable debounce while removed */
3708 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3709 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3711 wm8994->mic_detecting = false;
3712 wm8994->jack_mic = false;
3713 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3714 WM8958_MICD_ENA, 0);
3715 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3718 mutex_unlock(&wm8994->accdet_lock);
3720 /* Turn off MICBIAS if it was on for an external cap */
3721 if (control->pdata.jd_ext_cap && !present)
3722 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3725 snd_soc_jack_report(wm8994->micdet[0].jack,
3726 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3728 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3729 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3732 /* Since we only report deltas force an update, ensures we
3733 * avoid bootstrapping issues with the core. */
3734 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3736 pm_runtime_put(codec->dev);
3740 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3742 struct wm8994_priv *wm8994 = container_of(work,
3744 jackdet_bootstrap.work);
3745 wm1811_jackdet_irq(0, wm8994);
3749 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3751 * @codec: WM8958 codec
3752 * @jack: jack to report detection events on
3754 * Enable microphone detection functionality for the WM8958. By
3755 * default simple detection which supports the detection of up to 6
3756 * buttons plus video and microphone functionality is supported.
3758 * The WM8958 has an advanced jack detection facility which is able to
3759 * support complex accessory detection, especially when used in
3760 * conjunction with external circuitry. In order to provide maximum
3761 * flexiblity a callback is provided which allows a completely custom
3762 * detection algorithm.
3764 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3765 wm1811_micdet_cb det_cb, void *det_cb_data,
3766 wm1811_mic_id_cb id_cb, void *id_cb_data)
3768 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3769 struct wm8994 *control = wm8994->wm8994;
3772 switch (control->type) {
3781 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3782 snd_soc_dapm_sync(&codec->dapm);
3784 wm8994->micdet[0].jack = jack;
3787 wm8994->micd_cb = det_cb;
3788 wm8994->micd_cb_data = det_cb_data;
3790 wm8994->mic_detecting = true;
3791 wm8994->jack_mic = false;
3795 wm8994->mic_id_cb = id_cb;
3796 wm8994->mic_id_cb_data = id_cb_data;
3798 wm8994->mic_id_cb = wm8958_mic_id;
3799 wm8994->mic_id_cb_data = codec;
3802 wm8958_micd_set_rate(codec);
3804 /* Detect microphones and short circuits by default */
3805 if (control->pdata.micd_lvl_sel)
3806 micd_lvl_sel = control->pdata.micd_lvl_sel;
3808 micd_lvl_sel = 0x41;
3810 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3811 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3812 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3814 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3815 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3817 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3820 * If we can use jack detection start off with that,
3821 * otherwise jump straight to microphone detection.
3823 if (wm8994->jackdet) {
3824 /* Disable debounce for the initial detect */
3825 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3826 WM1811_JACKDET_DB, 0);
3828 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3830 WM8958_MICB2_DISCH);
3831 snd_soc_update_bits(codec, WM8994_LDO_1,
3832 WM8994_LDO1_DISCH, 0);
3833 wm1811_jackdet_set_mode(codec,
3834 WM1811_JACKDET_MODE_JACK);
3836 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3837 WM8958_MICD_ENA, WM8958_MICD_ENA);
3841 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3842 WM8958_MICD_ENA, 0);
3843 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3844 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3845 snd_soc_dapm_sync(&codec->dapm);
3850 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3852 static void wm8958_mic_work(struct work_struct *work)
3854 struct wm8994_priv *wm8994 = container_of(work,
3856 mic_complete_work.work);
3857 struct snd_soc_codec *codec = wm8994->hubs.codec;
3859 dev_crit(codec->dev, "MIC WORK %x\n", wm8994->mic_status);
3861 pm_runtime_get_sync(codec->dev);
3863 mutex_lock(&wm8994->accdet_lock);
3865 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3867 mutex_unlock(&wm8994->accdet_lock);
3869 pm_runtime_put(codec->dev);
3871 dev_crit(codec->dev, "MIC WORK %x DONE\n", wm8994->mic_status);
3874 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3876 struct wm8994_priv *wm8994 = data;
3877 struct snd_soc_codec *codec = wm8994->hubs.codec;
3878 int reg, count, ret, id_delay;
3881 * Jack detection may have detected a removal simulataneously
3882 * with an update of the MICDET status; if so it will have
3883 * stopped detection and we can ignore this interrupt.
3885 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3888 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3889 cancel_delayed_work_sync(&wm8994->open_circuit_work);
3891 pm_runtime_get_sync(codec->dev);
3893 /* We may occasionally read a detection without an impedence
3894 * range being provided - if that happens loop again.
3898 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3901 "Failed to read mic detect status: %d\n",
3903 pm_runtime_put(codec->dev);
3907 if (!(reg & WM8958_MICD_VALID)) {
3908 dev_dbg(codec->dev, "Mic detect data not valid\n");
3912 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3919 dev_warn(codec->dev, "No impedance range reported for jack\n");
3921 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3922 trace_snd_soc_jack_irq(dev_name(codec->dev));
3925 /* Avoid a transient report when the accessory is being removed */
3926 if (wm8994->jackdet) {
3927 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3929 dev_err(codec->dev, "Failed to read jack status: %d\n",
3931 } else if (!(ret & WM1811_JACKDET_LVL)) {
3932 dev_dbg(codec->dev, "Ignoring removed jack\n");
3935 } else if (!(reg & WM8958_MICD_STS)) {
3936 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3937 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3939 wm8994->mic_detecting = true;
3943 wm8994->mic_status = reg;
3944 id_delay = wm8994->wm8994->pdata.mic_id_delay;
3946 if (wm8994->mic_detecting)
3947 schedule_delayed_work(&wm8994->mic_complete_work,
3948 msecs_to_jiffies(id_delay));
3950 wm8958_button_det(codec, reg);
3953 pm_runtime_put(codec->dev);
3957 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3959 struct snd_soc_codec *codec = data;
3961 dev_err(codec->dev, "FIFO error\n");
3966 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3968 struct snd_soc_codec *codec = data;
3970 dev_err(codec->dev, "Thermal warning\n");
3975 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3977 struct snd_soc_codec *codec = data;
3979 dev_crit(codec->dev, "Thermal shutdown\n");
3984 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3986 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3987 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3988 struct snd_soc_dapm_context *dapm = &codec->dapm;
3992 wm8994->hubs.codec = codec;
3993 codec->control_data = control->regmap;
3995 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3997 mutex_init(&wm8994->accdet_lock);
3998 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3999 wm1811_jackdet_bootstrap);
4000 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4001 wm8958_open_circuit_work);
4003 switch (control->type) {
4005 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4008 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4014 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4016 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4017 init_completion(&wm8994->fll_locked[i]);
4019 wm8994->micdet_irq = control->pdata.micdet_irq;
4021 pm_runtime_enable(codec->dev);
4022 pm_runtime_idle(codec->dev);
4024 /* By default use idle_bias_off, will override for WM8994 */
4025 codec->dapm.idle_bias_off = 1;
4027 /* Set revision-specific configuration */
4028 switch (control->type) {
4030 /* Single ended line outputs should have VMID on. */
4031 if (!control->pdata.lineout1_diff ||
4032 !control->pdata.lineout2_diff)
4033 codec->dapm.idle_bias_off = 0;
4035 switch (control->revision) {
4038 wm8994->hubs.dcs_codes_l = -5;
4039 wm8994->hubs.dcs_codes_r = -5;
4040 wm8994->hubs.hp_startup_mode = 1;
4041 wm8994->hubs.dcs_readback_mode = 1;
4042 wm8994->hubs.series_startup = 1;
4045 wm8994->hubs.dcs_readback_mode = 2;
4051 wm8994->hubs.dcs_readback_mode = 1;
4052 wm8994->hubs.hp_startup_mode = 1;
4054 switch (control->revision) {
4058 wm8994->fll_byp = true;
4064 wm8994->hubs.dcs_readback_mode = 2;
4065 wm8994->hubs.no_series_update = 1;
4066 wm8994->hubs.hp_startup_mode = 1;
4067 wm8994->hubs.no_cache_dac_hp_direct = true;
4068 wm8994->fll_byp = true;
4070 wm8994->hubs.dcs_codes_l = -9;
4071 wm8994->hubs.dcs_codes_r = -7;
4073 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4074 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4081 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4082 wm8994_fifo_error, "FIFO error", codec);
4083 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4084 wm8994_temp_warn, "Thermal warning", codec);
4085 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4086 wm8994_temp_shut, "Thermal shutdown", codec);
4088 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4089 wm_hubs_dcs_done, "DC servo done",
4092 wm8994->hubs.dcs_done_irq = true;
4094 switch (control->type) {
4096 if (wm8994->micdet_irq) {
4097 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4099 IRQF_TRIGGER_RISING,
4103 dev_warn(codec->dev,
4104 "Failed to request Mic1 detect IRQ: %d\n",
4108 ret = wm8994_request_irq(wm8994->wm8994,
4109 WM8994_IRQ_MIC1_SHRT,
4110 wm8994_mic_irq, "Mic 1 short",
4113 dev_warn(codec->dev,
4114 "Failed to request Mic1 short IRQ: %d\n",
4117 ret = wm8994_request_irq(wm8994->wm8994,
4118 WM8994_IRQ_MIC2_DET,
4119 wm8994_mic_irq, "Mic 2 detect",
4122 dev_warn(codec->dev,
4123 "Failed to request Mic2 detect IRQ: %d\n",
4126 ret = wm8994_request_irq(wm8994->wm8994,
4127 WM8994_IRQ_MIC2_SHRT,
4128 wm8994_mic_irq, "Mic 2 short",
4131 dev_warn(codec->dev,
4132 "Failed to request Mic2 short IRQ: %d\n",
4138 if (wm8994->micdet_irq) {
4139 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4141 IRQF_TRIGGER_RISING,
4145 dev_warn(codec->dev,
4146 "Failed to request Mic detect IRQ: %d\n",
4149 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4150 wm8958_mic_irq, "Mic detect",
4155 switch (control->type) {
4157 if (control->cust_id > 1 || control->revision > 1) {
4158 ret = wm8994_request_irq(wm8994->wm8994,
4160 wm1811_jackdet_irq, "JACKDET",
4163 wm8994->jackdet = true;
4170 wm8994->fll_locked_irq = true;
4171 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4172 ret = wm8994_request_irq(wm8994->wm8994,
4173 WM8994_IRQ_FLL1_LOCK + i,
4174 wm8994_fll_locked_irq, "FLL lock",
4175 &wm8994->fll_locked[i]);
4177 wm8994->fll_locked_irq = false;
4180 /* Make sure we can read from the GPIOs if they're inputs */
4181 pm_runtime_get_sync(codec->dev);
4183 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4184 * configured on init - if a system wants to do this dynamically
4185 * at runtime we can deal with that then.
4187 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®);
4189 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4192 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4193 wm8994->lrclk_shared[0] = 1;
4194 wm8994_dai[0].symmetric_rates = 1;
4196 wm8994->lrclk_shared[0] = 0;
4199 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®);
4201 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4204 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4205 wm8994->lrclk_shared[1] = 1;
4206 wm8994_dai[1].symmetric_rates = 1;
4208 wm8994->lrclk_shared[1] = 0;
4211 pm_runtime_put(codec->dev);
4213 /* Latch volume update bits */
4214 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4215 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4216 wm8994_vu_bits[i].mask,
4217 wm8994_vu_bits[i].mask);
4219 /* Set the low bit of the 3D stereo depth so TLV matches */
4220 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4221 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4222 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4223 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4224 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4225 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4226 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4227 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4228 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4230 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4231 * use this; it only affects behaviour on idle TDM clock
4233 switch (control->type) {
4236 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4237 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4243 /* Put MICBIAS into bypass mode by default on newer devices */
4244 switch (control->type) {
4247 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4248 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4249 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4250 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4256 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4257 wm_hubs_update_class_w(codec);
4259 wm8994_handle_pdata(wm8994);
4261 wm_hubs_add_analogue_controls(codec);
4262 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4263 ARRAY_SIZE(wm8994_snd_controls));
4264 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4265 ARRAY_SIZE(wm8994_dapm_widgets));
4267 switch (control->type) {
4269 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4270 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4271 if (control->revision < 4) {
4272 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4273 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4274 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4275 ARRAY_SIZE(wm8994_adc_revd_widgets));
4276 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4277 ARRAY_SIZE(wm8994_dac_revd_widgets));
4279 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4280 ARRAY_SIZE(wm8994_lateclk_widgets));
4281 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4282 ARRAY_SIZE(wm8994_adc_widgets));
4283 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4284 ARRAY_SIZE(wm8994_dac_widgets));
4288 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4289 ARRAY_SIZE(wm8958_snd_controls));
4290 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4291 ARRAY_SIZE(wm8958_dapm_widgets));
4292 if (control->revision < 1) {
4293 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4294 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4295 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4296 ARRAY_SIZE(wm8994_adc_revd_widgets));
4297 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4298 ARRAY_SIZE(wm8994_dac_revd_widgets));
4300 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4301 ARRAY_SIZE(wm8994_lateclk_widgets));
4302 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4303 ARRAY_SIZE(wm8994_adc_widgets));
4304 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4305 ARRAY_SIZE(wm8994_dac_widgets));
4310 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4311 ARRAY_SIZE(wm8958_snd_controls));
4312 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4313 ARRAY_SIZE(wm8958_dapm_widgets));
4314 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4315 ARRAY_SIZE(wm8994_lateclk_widgets));
4316 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4317 ARRAY_SIZE(wm8994_adc_widgets));
4318 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4319 ARRAY_SIZE(wm8994_dac_widgets));
4323 wm_hubs_add_analogue_routes(codec, 0, 0);
4324 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4326 switch (control->type) {
4328 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4329 ARRAY_SIZE(wm8994_intercon));
4331 if (control->revision < 4) {
4332 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4333 ARRAY_SIZE(wm8994_revd_intercon));
4334 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4335 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4337 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4338 ARRAY_SIZE(wm8994_lateclk_intercon));
4342 if (control->revision < 1) {
4343 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4344 ARRAY_SIZE(wm8994_intercon));
4345 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4346 ARRAY_SIZE(wm8994_revd_intercon));
4347 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4348 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4350 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4351 ARRAY_SIZE(wm8994_lateclk_intercon));
4352 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4353 ARRAY_SIZE(wm8958_intercon));
4356 wm8958_dsp2_init(codec);
4359 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4360 ARRAY_SIZE(wm8994_lateclk_intercon));
4361 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4362 ARRAY_SIZE(wm8958_intercon));
4369 if (wm8994->jackdet)
4370 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4371 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4372 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4373 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4374 if (wm8994->micdet_irq)
4375 free_irq(wm8994->micdet_irq, wm8994);
4376 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4377 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4378 &wm8994->fll_locked[i]);
4379 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4381 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4382 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4383 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4388 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4390 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4391 struct wm8994 *control = wm8994->wm8994;
4394 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4396 pm_runtime_disable(codec->dev);
4398 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4399 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4400 &wm8994->fll_locked[i]);
4402 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4404 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4405 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4406 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4408 if (wm8994->jackdet)
4409 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4411 switch (control->type) {
4413 if (wm8994->micdet_irq)
4414 free_irq(wm8994->micdet_irq, wm8994);
4415 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4417 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4419 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4425 if (wm8994->micdet_irq)
4426 free_irq(wm8994->micdet_irq, wm8994);
4429 release_firmware(wm8994->mbc);
4430 release_firmware(wm8994->mbc_vss);
4431 release_firmware(wm8994->enh_eq);
4432 kfree(wm8994->retune_mobile_texts);
4436 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4437 .probe = wm8994_codec_probe,
4438 .remove = wm8994_codec_remove,
4439 .suspend = wm8994_codec_suspend,
4440 .resume = wm8994_codec_resume,
4441 .set_bias_level = wm8994_set_bias_level,
4444 static int wm8994_probe(struct platform_device *pdev)
4446 struct wm8994_priv *wm8994;
4448 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4452 platform_set_drvdata(pdev, wm8994);
4454 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4456 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4457 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4460 static int wm8994_remove(struct platform_device *pdev)
4462 snd_soc_unregister_codec(&pdev->dev);
4466 #ifdef CONFIG_PM_SLEEP
4467 static int wm8994_suspend(struct device *dev)
4469 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4471 /* Drop down to power saving mode when system is suspended */
4472 if (wm8994->jackdet && !wm8994->active_refcount)
4473 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4474 WM1811_JACKDET_MODE_MASK,
4475 wm8994->jackdet_mode);
4480 static int wm8994_resume(struct device *dev)
4482 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4484 if (wm8994->jackdet && wm8994->jackdet_mode)
4485 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4486 WM1811_JACKDET_MODE_MASK,
4487 WM1811_JACKDET_MODE_AUDIO);
4493 static const struct dev_pm_ops wm8994_pm_ops = {
4494 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4497 static struct platform_driver wm8994_codec_driver = {
4499 .name = "wm8994-codec",
4500 .owner = THIS_MODULE,
4501 .pm = &wm8994_pm_ops,
4503 .probe = wm8994_probe,
4504 .remove = wm8994_remove,
4507 module_platform_driver(wm8994_codec_driver);
4509 MODULE_DESCRIPTION("ASoC WM8994 driver");
4510 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4511 MODULE_LICENSE("GPL");
4512 MODULE_ALIAS("platform:wm8994-codec");