sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c -- WM8994 ALSA SoC audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  * Copyright 2005 Openedhand Ltd.
   6  *
   7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/platform_device.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/tlv.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29
  30 #include <mach/iomux.h>
  31 #include <mach/gpio.h>
  32
  33 #include "wm8994.h"
  34 #include <linux/miscdevice.h>
  35 #include <linux/circ_buf.h>
  36 #include <mach/spi_fpga.h>
  37
  38
  39 #if 1
  40 #define DBG(x...) printk(KERN_INFO x)
  41 #else
  42 #define DBG(x...) do { } while (0)
  43 #endif
  44
  45 #define WM8994_DELAY 50
  46
  47 struct i2c_client *wm8994_client;
  48 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate);
  49 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate);
  50
  51 enum wm8994_codec_mode
  52 {
  53   wm8994_AP_to_headset,
  54   wm8994_AP_to_speakers,
  55   wm8994_recorder,
  56   wm8994_recorder_and_AP_to_headset,
  57   wm8994_recorder_and_AP_to_speakers,
  58   wm8994_FM_to_headset,
  59   wm8994_FM_to_headset_and_record,
  60   wm8994_FM_to_speakers,
  61   wm8994_FM_to_speakers_and_record,
  62   wm8994_handsetMIC_to_baseband_to_headset,
  63   wm8994_handsetMIC_to_baseband_to_headset_and_record,
  64   wm8994_mainMIC_to_baseband_to_earpiece,
  65   wm8994_mainMIC_to_baseband_to_earpiece_and_record,
  66   wm8994_mainMIC_to_baseband_to_speakers,
  67   wm8994_mainMIC_to_baseband_to_speakers_and_record,
  68   wm8994_BT_baseband,
  69   wm8994_BT_baseband_and_record,
  70 ///PCM BB BEGIN
  71   wm8994_handsetMIC_to_PCMbaseband_to_headset,
  72   wm8994_handsetMIC_to_PCMbaseband_to_headset_and_record,
  73   wm8994_mainMIC_to_PCMbaseband_to_earpiece,
  74   wm8994_mainMIC_to_PCMbaseband_to_earpiece_and_record,
  75   wm8994_mainMIC_to_PCMbaseband_to_speakers,
  76   wm8994_mainMIC_to_PCMbaseband_to_speakers_and_record,
  77   wm8994_BT_PCMbaseband,
  78   wm8994_BT_PCMbaseband_and_record,
  79 ///PCM BB END
  80   null
  81 };
  82
  83 unsigned char wm8994_mode=null;
  84
  85 /* For voice device route set, add by phc  */
  86 enum VoiceDeviceSwitch
  87 {
  88         SPEAKER_INCALL,
  89         SPEAKER_NORMAL,
  90
  91         HEADSET_INCALL,
  92         HEADSET_NORMAL,
  93
  94         EARPIECE_INCALL,
  95         EARPIECE_NORMAL,
  96
  97         BLUETOOTH_SCO_INCALL,
  98         BLUETOOTH_SCO_NORMAL,
  99
 100         BLUETOOTH_A2DP_INCALL,
 101         BLUETOOTH_A2DP_NORMAL,
 102
 103         MIC_CAPTURE,
 104
 105         ALL_OPEN,
 106         ALL_CLOSED
 107 };
 108 /*
 109  * wm8994 register cache
 110  * We can't read the WM8994 register space when we
 111  * are using 2 wire for device control, so we cache them instead.
 112  */
 113 static const u16 wm8994_reg[] = {
 114         0x0097, 0x0097, 0x0079, 0x0079,  /*  0 */
 115         0x0000, 0x0008, 0x0000, 0x000a,  /*  4 */
 116         0x0000, 0x0000, 0x00ff, 0x00ff,  /*  8 */
 117         0x000f, 0x000f, 0x0000, 0x0000,  /* 12 */
 118         0x0000, 0x007b, 0x0000, 0x0032,  /* 16 */
 119         0x0000, 0x00c3, 0x00c3, 0x00c0,  /* 20 */
 120         0x0000, 0x0000, 0x0000, 0x0000,  /* 24 */
 121         0x0000, 0x0000, 0x0000, 0x0000,  /* 28 */
 122         0x0000, 0x0000, 0x0050, 0x0050,  /* 32 */
 123         0x0050, 0x0050, 0x0050, 0x0050,  /* 36 */
 124         0x0079, 0x0079, 0x0079,          /* 40 */
 125 };
 126
 127 /* codec private data */
 128 struct wm8994_priv {
 129         unsigned int sysclk;
 130         struct snd_soc_codec codec;
 131         struct snd_pcm_hw_constraint_list *sysclk_constraints;
 132         u16 reg_cache[WM8994_NUM_REG];
 133 };
 134
 135 static int wm8994_read(unsigned short reg,unsigned short *value)
 136 {
 137         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values;
 138
 139         if (reg_recv_data(wm8994_client,&regs,&values,400000) >= 0)
 140         {
 141                 *value=((values>>8)& 0x00FF)|((values<<8)&0xFF00);
 142                 return 0;
 143         }
 144
 145         printk("%s---line->%d:Codec read error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,*value);
 146
 147         return -EIO;
 148 }
 149
 150
 151 static int wm8994_write(unsigned short reg,unsigned short value)
 152 {
 153         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values=((value>>8)&0x00FF)|((value<<8)&0xFF00);
 154
 155         if (reg_send_data(wm8994_client,&regs,&values,400000)>=0)
 156                 return 0;
 157
 158         printk("%s---line->%d:Codec write error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,value);
 159
 160         return -EIO;
 161 }
 162
 163 #define wm8994_reset()  wm8994_write(WM8994_RESET, 0)
 164
 165 void  AP_to_headset(void)
 166 {
 167
 168         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 169
 170         wm8994_mode=wm8994_AP_to_headset;
 171         wm8994_reset();
 172         mdelay(WM8994_DELAY);
 173
 174         wm8994_write(0x01,  0x0003);
 175         mdelay(WM8994_DELAY);
 176
 177 //MCLK=12MHz
 178 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 179
 180         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 181         wm8994_write(0x220, 0x0000);
 182         wm8994_write(0x221, 0x0700);
 183         wm8994_write(0x222, 0x3126);
 184         wm8994_write(0x223, 0x0100);
 185 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 186         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 187         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 188         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 189         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 190 #endif
 191         wm8994_write(0x210, 0x0083); // SR=48KHz
 192
 193         wm8994_write(0x220, 0x0004);
 194         mdelay(WM8994_DELAY);
 195         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 196         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 197         wm8994_write(0x300, 0x4010);  // i2s 16 bits
 198
 199         wm8994_write(0x01,  0x0303);
 200         wm8994_write(0x05,  0x0303);
 201         wm8994_write(0x2D,  0x0100);
 202         wm8994_write(0x2E,  0x0100);
 203         wm8994_write(0x4C,  0x9F25);
 204         wm8994_write(0x60,  0x00EE);
 205         wm8994_write(0x208, 0x000A);
 206         wm8994_write(0x420, 0x0000);
 207         wm8994_write(0x601, 0x0001);
 208         wm8994_write(0x602, 0x0001);
 209
 210         wm8994_write(0x610, 0x0190);  //DAC1 Left Volume bit0~7
 211         wm8994_write(0x611, 0x0190);  //DAC1 Right Volume bit0~7
 212         wm8994_write(0x03,  0x0300);
 213         wm8994_write(0x22,  0x0000);
 214         wm8994_write(0x23,  0x0100);
 215         wm8994_write(0x36,  0x0003);
 216 }
 217
 218 void  AP_to_speakers(void)
 219 {
 220
 221         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 222
 223         wm8994_mode=wm8994_AP_to_speakers;
 224         wm8994_reset();
 225         mdelay(WM8994_DELAY);
 226
 227
 228         wm8994_write(0x01,  0x0003);
 229         mdelay(WM8994_DELAY);
 230
 231 //MCLK=12MHz
 232 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 233
 234         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 235         wm8994_write(0x220, 0x0000);
 236         wm8994_write(0x221, 0x0700);
 237         wm8994_write(0x222, 0x3126);
 238         wm8994_write(0x223, 0x0100);
 239 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 240         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 241         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 242         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 243         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 244 #endif
 245         wm8994_write(0x210, 0x0083); // SR=48KHz
 246
 247         wm8994_write(0x220, 0x0004);
 248         mdelay(WM8994_DELAY);
 249         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 250         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 251         wm8994_write(0x300, 0xC010);  // i2s 16 bits
 252
 253         wm8994_write(0x01,  0x3003);
 254         wm8994_write(0x05,  0x0303);
 255         wm8994_write(0x2D,  0x0100);
 256         wm8994_write(0x2E,  0x0100);
 257         wm8994_write(0x4C,  0x9F25);
 258         wm8994_write(0x60,  0x00EE);
 259         wm8994_write(0x208, 0x000A);
 260         wm8994_write(0x420, 0x0000);
 261
 262         wm8994_write(0x601, 0x0001);
 263         wm8994_write(0x602, 0x0001);
 264
 265         wm8994_write(0x610, 0x01c0);  //DAC1 Left Volume bit0~7
 266         wm8994_write(0x611, 0x01c0);  //DAC1 Right Volume bit0~7
 267         wm8994_write(0x03,  0x0300);
 268         wm8994_write(0x22,  0x0000);
 269         wm8994_write(0x23,  0x0100);
 270         wm8994_write(0x36,  0x0003);
 271         mdelay(WM8994_DELAY);
 272
 273 }
 274
 275 void  recorder(void)
 276 {
 277
 278         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 279
 280         wm8994_mode=wm8994_recorder;
 281         wm8994_reset();
 282         mdelay(WM8994_DELAY);
 283
 284         wm8994_write(0x01,   0x0013);
 285         mdelay(WM8994_DELAY);
 286 //MCLK=12MHz
 287 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 288
 289         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 290         wm8994_write(0x220, 0x0000);
 291         wm8994_write(0x221, 0x0700);
 292         wm8994_write(0x222, 0x3126);
 293         wm8994_write(0x223, 0x0100);
 294 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 295         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 296         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 297         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 298         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 299 #endif
 300         wm8994_write(0x210, 0x0083); // SR=48KHz
 301
 302         wm8994_write(0x220, 0x0004);
 303         mdelay(WM8994_DELAY);
 304         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 305         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 306
 307         wm8994_write(0x02,   0x6110);
 308         wm8994_write(0x04,   0x0303);
 309         wm8994_write(0x1A,   0x015F);  //volume
 310
 311         wm8994_write(0x28,   0x0003);
 312         wm8994_write(0x2A,   0x0020);
 313         wm8994_write(0x200,  0x0011);
 314         wm8994_write(0x208,  0x000A);
 315         wm8994_write(0x300,  0xC050);
 316         wm8994_write(0x606,  0x0002);
 317         wm8994_write(0x607,  0x0002);
 318         wm8994_write(0x620,  0x0000);
 319
 320 }
 321 void  recorder_and_AP_to_headset(void)
 322 {
 323
 324         DBG("%s--%d\n",__FUNCTION__,__LINE__);
 325
 326         wm8994_mode=wm8994_recorder_and_AP_to_headset;
 327         wm8994_reset();
 328         mdelay(WM8994_DELAY);
 329
 330         wm8994_write(0x01,  0x0013);
 331         mdelay(WM8994_DELAY);
 332
 333 //MCLK=12MHz
 334 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 335
 336         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 337         wm8994_write(0x220, 0x0000);
 338         wm8994_write(0x221, 0x0700);
 339         wm8994_write(0x222, 0x3126);
 340         wm8994_write(0x223, 0x0100);
 341 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 342         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 343         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 344         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 345         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 346 #endif
 347         wm8994_write(0x210, 0x0083); // SR=48KHz
 348
 349         wm8994_write(0x220, 0x0004);
 350         mdelay(WM8994_DELAY);
 351         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 352         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 353
 354         wm8994_write(0x02,  0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
 355         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 356         wm8994_write(0x1A,  0x014B); // IN1_VU=1, IN1R_ZC=1, IN1R_VOL=0_1011
 357         wm8994_write(0x28,  0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
 358         wm8994_write(0x2A,  0x0020); // IN1R_TO_MIXINR=1
 359         wm8994_write(0x200, 0x0011); // AIF1CLK_ENA=1
 360         wm8994_write(0x208, 0x000A); // DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 361         wm8994_write(0x300, 0xC010); // AIF1ADCL_SRC=1, AIF1ADCR_SRC=1, AIF1_WL=10, AIF1_FMT=10
 362         wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
 363         wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
 364         wm8994_write(0x620, 0x0000);
 365
 366         wm8994_write(0x700, 0xA101);
 367
 368         wm8994_write(0x01,  0x0313);
 369         wm8994_write(0x05,  0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
 370         wm8994_write(0x2D,  0x0100); // DAC1L_TO_HPOUT1L=1
 371         wm8994_write(0x2E,  0x0100); // DAC1R_TO_HPOUT1R=1
 372         wm8994_write(0x4C,  0x9F25); // CP_ENA=1
 373         wm8994_write(0x60,  0x00EE); // HPOUT1L_RMV_SHORT=1, HPOUT1L_OUTP=1, HPOUT1L_DLY=1, HPOUT1R_RMV_SHORT=1, HPOUT1R_OUTP=1, HPOUT1R_DLY=1
 374         wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
 375         wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
 376         wm8994_write(0x610, 0x01C0); // DAC1_VU=1, DAC1L_VOL=1100_0000
 377         wm8994_write(0x611, 0x01C0); // DAC1_VU=1, DAC1R_VOL=1100_0000
 378
 379         wm8994_write(0x420, 0x0000);
 380 }
 381
 382 void  recorder_and_AP_to_speakers(void)
 383 {
 384
 385         DBG("%s--%d\n",__FUNCTION__,__LINE__);
 386
 387         wm8994_mode=wm8994_recorder_and_AP_to_speakers;
 388         wm8994_reset();
 389         mdelay(WM8994_DELAY);
 390
 391         wm8994_write(0x01,  0x0013);
 392         mdelay(WM8994_DELAY);
 393
 394 //MCLK=12MHz
 395 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 396
 397         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 398         wm8994_write(0x220, 0x0000);
 399         wm8994_write(0x221, 0x0700);
 400         wm8994_write(0x222, 0x3126);
 401         wm8994_write(0x223, 0x0100);
 402 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 403         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 404         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 405         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 406         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 407 #endif
 408         wm8994_write(0x210, 0x0083); // SR=48KHz
 409
 410         wm8994_write(0x220, 0x0004);
 411         mdelay(WM8994_DELAY);
 412         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 413         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 414
 415         wm8994_write(0x02,  0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
 416         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 417         wm8994_write(0x1A,  0x014B); // IN1_VU=1, IN1R_ZC=1, IN1R_VOL=0_1011
 418         wm8994_write(0x28,  0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
 419         wm8994_write(0x2A,  0x0020); // IN1R_TO_MIXINR=1
 420         wm8994_write(0x200, 0x0011); // AIF1CLK_ENA=1
 421         wm8994_write(0x208, 0x000A); // DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 422         wm8994_write(0x300, 0xC010); // AIF1ADCL_SRC=1, AIF1ADCR_SRC=1, AIF1_WL=10, AIF1_FMT=10
 423         wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
 424         wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
 425         wm8994_write(0x620, 0x0000);
 426
 427         wm8994_write(0x700, 0xA101);
 428
 429         wm8994_write(0x01,  0x3013);
 430         wm8994_write(0x03,  0x0330); // SPKRVOL_ENA=1, SPKLVOL_ENA=1, MIXOUTL_ENA=1, MIXOUTR_ENA=1
 431         wm8994_write(0x05,  0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
 432         wm8994_write(0x22,  0x0000);
 433         wm8994_write(0x23,  0x0100); // SPKOUT_CLASSAB=1
 434
 435         wm8994_write(0x2D,  0x0001); // DAC1L_TO_MIXOUTL=1
 436         wm8994_write(0x2E,  0x0001); // DAC1R_TO_MIXOUTR=1
 437         wm8994_write(0x36,  0x000C); // MIXOUTL_TO_SPKMIXL=1, MIXOUTR_TO_SPKMIXR=1
 438         wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
 439         wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
 440         wm8994_write(0x610, 0x01C0); // DAC1_VU=1, DAC1L_VOL=1100_0000
 441         wm8994_write(0x611, 0x01C0); // DAC1_VU=1, DAC1R_VOL=1100_0000
 442
 443         wm8994_write(0x420, 0x0000);
 444
 445 }
 446
 447 void  FM_to_headset(void)
 448 {
 449
 450         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 451
 452         wm8994_mode=wm8994_FM_to_headset;
 453         wm8994_reset();
 454         mdelay(WM8994_DELAY);
 455
 456         wm8994_write(0x01,  0x0323);
 457         wm8994_write(0x02,  0x03A0);
 458         wm8994_write(0x03,  0x0030);
 459         wm8994_write(0x19,  0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 460         wm8994_write(0x1B,  0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 461
 462         wm8994_write(0x28,  0x0044);
 463         wm8994_write(0x29,  0x0100);
 464         wm8994_write(0x2A,  0x0100);
 465         wm8994_write(0x2D,  0x0040);
 466         wm8994_write(0x2E,  0x0040);
 467         wm8994_write(0x4C,  0x9F25);
 468         wm8994_write(0x60,  0x00EE);
 469         wm8994_write(0x220, 0x0003);
 470         wm8994_write(0x221, 0x0700);
 471         wm8994_write(0x224, 0x0CC0);
 472         wm8994_write(0x200, 0x0011);
 473         wm8994_write(0x1C,  0x01F9);  //LEFT OUTPUT VOLUME
 474         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 475 }
 476
 477 void  FM_to_headset_and_record(void)
 478 {
 479
 480         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 481
 482         wm8994_mode=wm8994_FM_to_headset_and_record;
 483         wm8994_reset();
 484         mdelay(WM8994_DELAY);
 485
 486         wm8994_write(0x01,   0x0003);
 487         mdelay(WM8994_DELAY);
 488         wm8994_write(0x221,  0x1900);  //8~13BIT div
 489
 490 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 491         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 492         wm8994_write(0x303,  0x0040);  // master  0x0050 lrck 7.94kHz bclk 510KHz
 493 #endif
 494
 495         wm8994_write(0x220,  0x0004);
 496         mdelay(WM8994_DELAY);
 497         wm8994_write(0x220,  0x0005);
 498
 499         wm8994_write(0x01,   0x0323);
 500         wm8994_write(0x02,   0x03A0);
 501         wm8994_write(0x03,   0x0030);
 502         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 503         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 504
 505         wm8994_write(0x28,   0x0044);
 506         wm8994_write(0x29,   0x0100);
 507         wm8994_write(0x2A,   0x0100);
 508         wm8994_write(0x2D,   0x0040);
 509         wm8994_write(0x2E,   0x0040);
 510         wm8994_write(0x4C,   0x9F25);
 511         wm8994_write(0x60,   0x00EE);
 512         wm8994_write(0x200,  0x0011);
 513         wm8994_write(0x1C,   0x01F9);  //LEFT OUTPUT VOLUME
 514         wm8994_write(0x1D,   0x01F9);  //RIGHT OUTPUT VOLUME
 515         wm8994_write(0x04,   0x0303);
 516         wm8994_write(0x208,  0x000A);
 517         wm8994_write(0x300,  0x4050);
 518         wm8994_write(0x606,  0x0002);
 519         wm8994_write(0x607,  0x0002);
 520         wm8994_write(0x620,  0x0000);
 521 }
 522
 523 void  FM_to_speakers(void)
 524 {
 525
 526         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 527
 528         wm8994_mode=wm8994_FM_to_speakers;
 529         wm8994_reset();
 530         mdelay(WM8994_DELAY);
 531
 532         wm8994_write(0x01,   0x3023);
 533         wm8994_write(0x02,   0x03A0);
 534         wm8994_write(0x03,   0x0330);
 535         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 536         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 537
 538         wm8994_write(0x22,   0x0000);
 539         wm8994_write(0x23,   0x0000);
 540         wm8994_write(0x36,   0x000C);
 541
 542         wm8994_write(0x28,   0x0044);
 543         wm8994_write(0x29,   0x0100);
 544         wm8994_write(0x2A,   0x0100);
 545         wm8994_write(0x2D,   0x0040);
 546         wm8994_write(0x2E,   0x0040);
 547
 548         wm8994_write(0x220,  0x0003);
 549         wm8994_write(0x221,  0x0700);
 550         wm8994_write(0x224,  0x0CC0);
 551
 552         wm8994_write(0x200,  0x0011);
 553         wm8994_write(0x20,   0x01F9);
 554         wm8994_write(0x21,   0x01F9);
 555 }
 556
 557 void  FM_to_speakers_and_record(void)
 558 {
 559
 560         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 561
 562         wm8994_mode=wm8994_FM_to_speakers_and_record;
 563         wm8994_reset();
 564         mdelay(WM8994_DELAY);
 565
 566         wm8994_write(0x01,   0x0003);
 567         mdelay(WM8994_DELAY);
 568
 569 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 570         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 571         wm8994_write(0x303,  0x0090);  //
 572 #endif
 573
 574         wm8994_write(0x220,  0x0006);
 575         mdelay(WM8994_DELAY);
 576
 577         wm8994_write(0x01,   0x3023);
 578         wm8994_write(0x02,   0x03A0);
 579         wm8994_write(0x03,   0x0330);
 580         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 581         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 582
 583         wm8994_write(0x22,   0x0000);
 584         wm8994_write(0x23,   0x0000);
 585         wm8994_write(0x36,   0x000C);
 586
 587         wm8994_write(0x28,   0x0044);
 588         wm8994_write(0x29,   0x0100);
 589         wm8994_write(0x2A,   0x0100);
 590         wm8994_write(0x2D,   0x0040);
 591         wm8994_write(0x2E,   0x0040);
 592
 593         wm8994_write(0x220,  0x0003);
 594         wm8994_write(0x221,  0x0700);
 595         wm8994_write(0x224,  0x0CC0);
 596
 597         wm8994_write(0x200,  0x0011);
 598         wm8994_write(0x20,   0x01F9);
 599         wm8994_write(0x21,   0x01F9);
 600         wm8994_write(0x04,   0x0303);
 601         wm8994_write(0x208,  0x000A);
 602         wm8994_write(0x300,  0x4050);
 603         wm8994_write(0x606,  0x0002);
 604         wm8994_write(0x607,  0x0002);
 605         wm8994_write(0x620,  0x0000);
 606 }
 607
 608 void  handsetMIC_to_baseband_to_headset(void)
 609 {
 610
 611         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 612
 613         wm8994_mode=wm8994_handsetMIC_to_baseband_to_headset;
 614         wm8994_reset();
 615         mdelay(WM8994_DELAY);
 616
 617         wm8994_write(0x01,  0x0323);
 618         wm8994_write(0x02,  0x6040);
 619         wm8994_write(0x03,  0x3030);
 620         wm8994_write(0x18,  0x014B);  //mic volume
 621         wm8994_write(0x1E,  0x0006);
 622         wm8994_write(0x28,  0x0030);
 623         wm8994_write(0x2D,  0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 624         wm8994_write(0x2E,  0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 625         wm8994_write(0x34,  0x0002);
 626         wm8994_write(0x4C,  0x9F25);
 627         wm8994_write(0x60,  0x00EE);
 628         wm8994_write(0x220, 0x0003);
 629         wm8994_write(0x221, 0x0700);
 630         wm8994_write(0x224, 0x0CC0);
 631
 632 //Note: free-running start first, then open AIF1 clock setting
 633         wm8994_write(0x200, 0x0011);
 634 //Note: 0x1C/0x1D=0x01FF-->bypass volume no gain/attenuation
 635         wm8994_write(0x1C,  0x01FF);  //LEFT OUTPUT VOLUME
 636         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 637
 638 }
 639
 640 void  handsetMIC_to_baseband_to_headset_and_record(void)
 641 {
 642
 643         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 644
 645         wm8994_mode=wm8994_handsetMIC_to_baseband_to_headset_and_record;
 646         wm8994_reset();
 647         mdelay(WM8994_DELAY);
 648
 649         wm8994_write(0x01,  0x0323);
 650         wm8994_write(0x02,  0x62C0);
 651         wm8994_write(0x03,  0x3030);
 652         wm8994_write(0x04,  0x0303);
 653         wm8994_write(0x18,  0x014B);  //volume
 654         wm8994_write(0x19,  0x014B);  //volume
 655         wm8994_write(0x1C,  0x01FF);  //LEFT OUTPUT VOLUME
 656         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 657         wm8994_write(0x1E,  0x0006);
 658         wm8994_write(0x28,  0x00B0);  //IN2LP_TO_IN2L
 659         wm8994_write(0x29,  0x0120);
 660         wm8994_write(0x2D,  0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 661         wm8994_write(0x2E,  0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 662         wm8994_write(0x34,  0x0002);
 663         wm8994_write(0x4C,  0x9F25);
 664         wm8994_write(0x60,  0x00EE);
 665         wm8994_write(0x200, 0x0001);
 666         wm8994_write(0x208, 0x000A);
 667         wm8994_write(0x300, 0x0050);
 668
 669 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 670         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 671         wm8994_write(0x303, 0x0090);  // master lrck 16k
 672 #endif
 673
 674         wm8994_write(0x606, 0x0002);
 675         wm8994_write(0x607, 0x0002);
 676         wm8994_write(0x620, 0x0000);
 677
 678         wm8994_write(0x1C, 0x01F9);
 679         wm8994_write(0x1D, 0x01F9);
 680 }
 681
 682 void  mainMIC_to_baseband_to_earpiece(void)
 683 {
 684
 685         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 686
 687         wm8994_mode=wm8994_mainMIC_to_baseband_to_earpiece;
 688         wm8994_reset();
 689         mdelay(WM8994_DELAY);
 690
 691         wm8994_write(0x01, 0x0813);
 692         wm8994_write(0x02, 0x6210);
 693         wm8994_write(0x03, 0x30A0);
 694         wm8994_write(0x1A, 0x015F);  //main mic volume
 695         wm8994_write(0x1E, 0x0006);
 696         wm8994_write(0x1F, 0x0000);
 697         wm8994_write(0x28, 0x0003);
 698         wm8994_write(0x2B, 0x0005);  //VRX_MIXINL_VOL
 699         wm8994_write(0x2D, 0x0040);
 700         wm8994_write(0x33, 0x0010);
 701         wm8994_write(0x34, 0x0004);
 702 }
 703
 704 void  mainMIC_to_baseband_to_earpiece_and_record(void)
 705 {
 706
 707         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 708
 709         wm8994_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
 710         wm8994_reset();
 711         mdelay(WM8994_DELAY);
 712
 713         wm8994_write(0x01  ,0x0813);
 714         wm8994_write(0x02  ,0x6310);
 715         wm8994_write(0x03  ,0x30A0);
 716         wm8994_write(0x04  ,0x0303);
 717         wm8994_write(0x1A  ,0x014F);
 718         wm8994_write(0x1E  ,0x0006);
 719         wm8994_write(0x1F  ,0x0000);
 720         wm8994_write(0x28  ,0x0003);  //MAINMIC_TO_IN1R  //
 721         wm8994_write(0x2A  ,0x0020);  //IN1R_TO_MIXINR   //
 722         wm8994_write(0x2B  ,0x0005);  //VRX_MIXINL_VOL bit 0~2
 723         wm8994_write(0x2C  ,0x0005);  //VRX_MIXINR_VOL
 724         wm8994_write(0x2D  ,0x0040);  //MIXINL_TO_MIXOUTL
 725         wm8994_write(0x33  ,0x0010);  //MIXOUTLVOL_TO_HPOUT2
 726         wm8994_write(0x34  ,0x0004);  //IN1R_TO_LINEOUT1 //
 727         wm8994_write(0x200 ,0x0001);
 728         wm8994_write(0x208 ,0x000A);
 729         wm8994_write(0x300 ,0xC050);
 730
 731 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 732         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 733         wm8994_write(0x303, 0x0090);  // master lrck 16k
 734 #endif
 735
 736         wm8994_write(0x606 ,0x0002);
 737         wm8994_write(0x607 ,0x0002);
 738         wm8994_write(0x620 ,0x0000);
 739 }
 740
 741 void  mainMIC_to_baseband_to_speakers(void)
 742 {
 743
 744         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 745
 746         wm8994_mode=wm8994_mainMIC_to_baseband_to_speakers;
 747         wm8994_reset();
 748         mdelay(WM8994_DELAY);
 749
 750 #if 1
 751         wm8994_write(0x01 ,0x3013);
 752         wm8994_write(0x02 ,0x6210);
 753         wm8994_write(0x03 ,0x3330);
 754         wm8994_write(0x1A ,0x015F);
 755         wm8994_write(0x1E ,0x0006);
 756         wm8994_write(0x22 ,0x0000);
 757         wm8994_write(0x23 ,0x0100);
 758         wm8994_write(0x26 ,0x017F);  //Speaker Volume Left bit 0~5
 759         wm8994_write(0x27 ,0x017F);  //Speaker Volume Right bit 0~5
 760         wm8994_write(0x28 ,0x0003);
 761         wm8994_write(0x2D ,0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 762         wm8994_write(0x2E ,0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 763         wm8994_write(0x34 ,0x0004);
 764         wm8994_write(0x36 ,0x000C);
 765 #endif
 766 }
 767
 768 void  mainMIC_to_baseband_to_speakers_with_music(void)
 769 {
 770
 771         DBG("%s--%d:: with music \n",__FUNCTION__,__LINE__);
 772
 773         wm8994_mode=wm8994_mainMIC_to_baseband_to_speakers;
 774         wm8994_reset();
 775         mdelay(WM8994_DELAY);
 776
 777         wm8994_write(0x01,  0x3013);
 778         mdelay(WM8994_DELAY);
 779
 780 //MCLK=12MHz
 781 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 782
 783         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 784         wm8994_write(0x220, 0x0000);
 785         wm8994_write(0x221, 0x0700);
 786         wm8994_write(0x222, 0x3126);
 787         wm8994_write(0x223, 0x0100);
 788 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 789         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 790         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 791         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 792         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 793 #endif
 794         wm8994_write(0x210, 0x0083); // SR=48KHz
 795
 796         wm8994_write(0x220, 0x0004);
 797         mdelay(WM8994_DELAY);
 798         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 799         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 800         wm8994_write(0x300, 0xC010);  // i2s 16 bits
 801
 802         wm8994_write(0x01,  0x3013);
 803         wm8994_write(0x02,  0x6210);
 804         wm8994_write(0x03,  0x3330);
 805         wm8994_write(0x05,  0x0303);
 806         wm8994_write(0x1A,  0x015F);
 807         wm8994_write(0x1E,  0x0006);
 808         wm8994_write(0x22,  0x0000);
 809         wm8994_write(0x23,  0x0100);
 810         wm8994_write(0x26,  0x017F);  //Speaker Volume Left bit 0~5
 811         wm8994_write(0x27,  0x017F);  //Speaker Volume Right bit 0~5
 812         wm8994_write(0x28,  0x0003);
 813         wm8994_write(0x2D,  0x0003);  //bit 1 IN2LP_TO_MIXOUTL
 814         wm8994_write(0x2E,  0x0003);  //bit 1 IN2RP_TO_MIXOUTR
 815         wm8994_write(0x4C,  0x9F25);
 816         wm8994_write(0x60,  0x00EE);
 817         wm8994_write(0x34,  0x0004);
 818         wm8994_write(0x36,  0x000C);
 819
 820         wm8994_write(0x208, 0x000A);
 821         wm8994_write(0x420, 0x0000);
 822
 823         wm8994_write(0x601, 0x0001);
 824         wm8994_write(0x602, 0x0001);
 825
 826         wm8994_write(0x610, 0x01c0);  //DAC1 Left Volume bit0~7
 827         wm8994_write(0x611, 0x01c0);  //DAC1 Right Volume bit0~7
 828 }
 829
 830 void  mainMIC_to_baseband_to_speakers_and_record(void)
 831 {
 832
 833         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 834
 835         wm8994_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
 836         wm8994_reset();
 837         mdelay(WM8994_DELAY);
 838
 839         wm8994_write(0x01, 0x3013);
 840         wm8994_write(0x02, 0x6330);
 841         wm8994_write(0x03, 0x3330);
 842         wm8994_write(0x04, 0x0303);
 843         wm8994_write(0x1A, 0x014B);
 844         wm8994_write(0x1B, 0x014B);
 845         wm8994_write(0x1E, 0x0006);
 846         wm8994_write(0x22, 0x0000);
 847         wm8994_write(0x23, 0x0100);
 848         wm8994_write(0x28, 0x0007);
 849         wm8994_write(0x2A, 0x0120);
 850         wm8994_write(0x2D, 0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 851         wm8994_write(0x2E, 0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 852         wm8994_write(0x34, 0x0004);
 853         wm8994_write(0x36, 0x000C);
 854         wm8994_write(0x200, 0x0001);
 855         wm8994_write(0x208, 0x000A);
 856         wm8994_write(0x300, 0xC050);
 857
 858 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 859         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 860         wm8994_write(0x303, 0x0090);  // master lrck 16k
 861 #endif
 862
 863         wm8994_write(0x606, 0x0002);
 864         wm8994_write(0x607, 0x0002);
 865         wm8994_write(0x620, 0x0000);
 866
 867 }
 868
 869 void  BT_baseband(void)
 870 {
 871
 872         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 873
 874         wm8994_mode=wm8994_BT_baseband;
 875         wm8994_reset();
 876         mdelay(WM8994_DELAY);
 877
 878         wm8994_write(0x01,  0x0003);
 879         mdelay(WM8994_DELAY);
 880         wm8994_write(0x221, 0x0700);
 881         wm8994_write(0x222, 0x3127);
 882         wm8994_write(0x223, 0x0100);
 883         wm8994_write(0x220, 0x0004);
 884         mdelay(WM8994_DELAY);
 885         wm8994_write(0x220, 0x0005);
 886
 887         wm8994_write(0x01,  0x0003);
 888         wm8994_write(0x03,  0x30F0);
 889         wm8994_write(0x05,  0x3003);
 890         wm8994_write(0x2D,  0x0001);
 891         wm8994_write(0x2E,  0x0001);
 892
 893         wm8994_write(0x200, 0x0001);
 894         wm8994_write(0x204, 0x0001);
 895         wm8994_write(0x208, 0x0007);
 896         wm8994_write(0x520, 0x0000);
 897         wm8994_write(0x601, 0x0004);
 898         wm8994_write(0x602, 0x0004);
 899         wm8994_write(0x610, 0x01C0);
 900         wm8994_write(0x611, 0x01C0);
 901         wm8994_write(0x613, 0x01C0);
 902
 903         wm8994_write(0x702, 0xC100);
 904         wm8994_write(0x703, 0xC100);
 905         wm8994_write(0x704, 0xC100);
 906         wm8994_write(0x706, 0x4100);
 907
 908         wm8994_write(0x204, 0x0011);  // AIF2 MCLK=FLL                            //MASTER
 909         wm8994_write(0x211, 0x0039);  //LRCK=8KHZ,Rate=MCLK/1536                         //MASTER
 910         wm8994_write(0x310, 0xC118);  //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
 911
 912         wm8994_write(0x313, 0x00F0);
 913         wm8994_write(0x314, 0x0020);
 914         wm8994_write(0x315, 0x0020);
 915         wm8994_write(0x2B,  0x0005);
 916         wm8994_write(0x2C,  0x0005);
 917         wm8994_write(0x02,  0x6300);
 918         wm8994_write(0x04,  0x3003);
 919
 920         wm8994_write(0x1E,  0x0006);  //LINEOUT1N_MUTE(001Eh);
 921         wm8994_write(0x34,  0x0001);  //LINEOUT1_MODE=1;LINEOUT_VMID_BUF_ENA=1;
 922
 923         wm8994_write(0x603, 0x018C);
 924         wm8994_write(0x604, 0x0010);
 925         wm8994_write(0x605, 0x0010);
 926         wm8994_write(0x621, 0x0001);
 927         wm8994_write(0x317, 0x0003);
 928
 929 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 930         wm8994_write(0x312, 0x4000);  //set 0x312 PCM2 as Master
 931         wm8994_write(0x313, 0x0090);  //master   0x0090 lrck2 8kHz bclk2 1MH
 932         wm8994_write(0x315, 0x007D);  //master   0x007D lrck2 8kHz bclk2 1MH
 933 #endif
 934 }
 935
 936 void  BT_baseband_and_record(void)
 937 {
 938
 939         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 940
 941         wm8994_mode=wm8994_BT_baseband_and_record;
 942         wm8994_reset();
 943         mdelay(WM8994_DELAY);
 944
 945         wm8994_write(0x01, 0x0003);
 946         wm8994_write(0x02, 0x63A0);
 947         wm8994_write(0x03, 0x30A0);
 948         wm8994_write(0x04, 0x3303);
 949         wm8994_write(0x05, 0x3002);
 950         wm8994_write(0x06, 0x000A);
 951         wm8994_write(0x19, 0x014B);
 952         wm8994_write(0x1B, 0x014B);
 953         wm8994_write(0x1E, 0x0006);
 954         wm8994_write(0x28, 0x00CC);
 955         wm8994_write(0x29, 0x0100);
 956         wm8994_write(0x2A, 0x0100);
 957         wm8994_write(0x2D, 0x0001);
 958         wm8994_write(0x34, 0x0001);
 959         wm8994_write(0x200, 0x0001);
 960         wm8994_write(0x204, 0x0001);
 961         wm8994_write(0x208, 0x000F);
 962
 963 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 964         wm8994_write(0x312, 0x7000);
 965         wm8994_write(0x313, 0x0090);  //master   0x0090 lrck2 8kHz bclk2 1MH
 966         wm8994_write(0x315, 0x007D);  //master   0x007D lrck2 8kHz bclk2 1MH
 967
 968         wm8994_write(0x302, 0x4000);
 969         wm8994_write(0x303, 0x0090);  //master
 970 #endif
 971
 972         wm8994_write(0x440, 0x0018);
 973         wm8994_write(0x450, 0x0018);
 974         wm8994_write(0x480, 0x0000);
 975         wm8994_write(0x481, 0x0000);
 976         wm8994_write(0x4A0, 0x0000);
 977         wm8994_write(0x4A1, 0x0000);
 978         wm8994_write(0x520, 0x0000);
 979         wm8994_write(0x540, 0x0018);
 980         wm8994_write(0x580, 0x0000);
 981         wm8994_write(0x581, 0x0000);
 982         wm8994_write(0x601, 0x0004);
 983         wm8994_write(0x603, 0x000C);
 984         wm8994_write(0x604, 0x0010);
 985         wm8994_write(0x605, 0x0010);
 986         wm8994_write(0x606, 0x0003);
 987         wm8994_write(0x607, 0x0003);
 988         wm8994_write(0x610, 0x01C0);
 989         wm8994_write(0x612, 0x01C0);
 990         wm8994_write(0x613, 0x01C0);
 991         wm8994_write(0x620, 0x0000);
 992         wm8994_write(0x704, 0xA100);
 993         wm8994_write(0x707, 0xA100);
 994         wm8994_write(0x708, 0x2100);
 995         wm8994_write(0x709, 0x2100);
 996         wm8994_write(0x70A, 0x2100);
 997 }
 998
 999
1000 ///PCM BB BEGIN//
1001
1002 void  handsetMIC_to_PCMbaseband_to_headset(void)
1003 {
1004
1005         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1006
1007         wm8994_mode=wm8994_handsetMIC_to_PCMbaseband_to_headset;
1008         wm8994_reset();
1009         mdelay(WM8994_DELAY);
1010
1011         wm8994_write(0x01,  0x0003);
1012         mdelay(WM8994_DELAY);
1013         wm8994_write(0x221, 0x0700);
1014         wm8994_write(0x222, 0x3127);
1015         wm8994_write(0x223, 0x0100);
1016         wm8994_write(0x220, 0x0004);
1017         mdelay(WM8994_DELAY);
1018         wm8994_write(0x220, 0x0005);
1019
1020         wm8994_write(0x01,  0x0303);  // sysclk = fll (bit4 =1)   0x0011
1021         wm8994_write(0x02,  0x0240);
1022         wm8994_write(0x03,  0x0030);
1023         wm8994_write(0x04,  0x3003);
1024         wm8994_write(0x05,  0x3003);  // i2s 16 bits
1025         wm8994_write(0x18,  0x010B);
1026         wm8994_write(0x28,  0x0030);
1027         wm8994_write(0x29,  0x0020);
1028         wm8994_write(0x2D,  0x0100);
1029         wm8994_write(0x2E,  0x0100);
1030         wm8994_write(0x4C,  0x9F25);
1031         wm8994_write(0x60,  0x00EE);
1032         wm8994_write(0x200, 0x0001);
1033         wm8994_write(0x204, 0x0001);
1034         wm8994_write(0x208, 0x0007);
1035         wm8994_write(0x520, 0x0000);
1036         wm8994_write(0x601, 0x0004);
1037         wm8994_write(0x602, 0x0004);
1038
1039         wm8994_write(0x610, 0x01C0);
1040         wm8994_write(0x611, 0x01C0);
1041         wm8994_write(0x612, 0x01C0);
1042         wm8994_write(0x613, 0x01C0);
1043
1044         wm8994_write(0x702, 0xC100);
1045         wm8994_write(0x703, 0xC100);
1046         wm8994_write(0x704, 0xC100);
1047         wm8994_write(0x706, 0x4100);
1048         wm8994_write(0x204, 0x0011);
1049         wm8994_write(0x211, 0x0009);
1050         wm8994_write(0x310, 0x4118);
1051         wm8994_write(0x313, 0x00F0);
1052         wm8994_write(0x314, 0x0020);
1053         wm8994_write(0x315, 0x0020);
1054
1055         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1056         wm8994_write(0x604, 0x0010);
1057         wm8994_write(0x605, 0x0010);
1058         wm8994_write(0x621, 0x0001);
1059 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1060         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1061 #endif
1062 }
1063
1064 void  handsetMIC_to_PCMbaseband_to_headset_and_record(void)
1065 {
1066
1067         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1068
1069         wm8994_mode=wm8994_handsetMIC_to_PCMbaseband_to_headset_and_record;
1070         wm8994_reset();
1071         mdelay(WM8994_DELAY);
1072
1073         wm8994_write(0x01,  0x0003);
1074         mdelay(WM8994_DELAY);
1075         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1076         wm8994_write(0x222, 0x3127);
1077         wm8994_write(0x223, 0x0100);
1078         wm8994_write(0x220, 0x0004);
1079         mdelay(WM8994_DELAY);
1080         wm8994_write(0x220, 0x0005);
1081
1082         wm8994_write(0x01,  0x0303);
1083         wm8994_write(0x02,  0x0240);
1084         wm8994_write(0x03,  0x0030);
1085         wm8994_write(0x04,  0x3003);
1086         wm8994_write(0x05,  0x3003);
1087         wm8994_write(0x18,  0x010B);  // 0x011F=+30dB for MIC
1088         wm8994_write(0x28,  0x0030);
1089         wm8994_write(0x29,  0x0020);
1090         wm8994_write(0x2D,  0x0100);
1091         wm8994_write(0x2E,  0x0100);
1092         wm8994_write(0x4C,  0x9F25);
1093         wm8994_write(0x60,  0x00EE);
1094         wm8994_write(0x200, 0x0001);
1095         wm8994_write(0x204, 0x0001);
1096         wm8994_write(0x208, 0x0007);
1097         wm8994_write(0x520, 0x0000);
1098         wm8994_write(0x601, 0x0004);
1099         wm8994_write(0x602, 0x0004);
1100
1101         wm8994_write(0x610, 0x01C0);
1102         wm8994_write(0x611, 0x01C0);
1103         wm8994_write(0x612, 0x01C0);
1104         wm8994_write(0x613, 0x01C0);
1105
1106         wm8994_write(0x700, 0x8141);  //SYNC issue, AIF1 ADCLRC1 from LRCK1
1107         wm8994_write(0x702, 0xC100);
1108         wm8994_write(0x703, 0xC100);
1109         wm8994_write(0x704, 0xC100);
1110         wm8994_write(0x706, 0x4100);
1111         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1112         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1113         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1114         wm8994_write(0x313, 0x00F0);
1115         wm8994_write(0x314, 0x0020);
1116         wm8994_write(0x315, 0x0020);
1117
1118         wm8994_write(0x603, 0x000C);  //Rev.D ADCL SideTone
1119         wm8994_write(0x604, 0x0010);
1120         wm8994_write(0x605, 0x0010);
1121         wm8994_write(0x621, 0x0000);
1122 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1123         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1124 #endif
1125 ////AIF1
1126         wm8994_write(0x04,   0x3303);
1127         wm8994_write(0x200,  0x0001);
1128         wm8994_write(0x208,  0x000F);
1129         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1130         wm8994_write(0x300,  0x0118);  //DSP/PCM 16bits, R ADC = L ADC
1131         wm8994_write(0x606,  0x0003);
1132         wm8994_write(0x607,  0x0003);
1133
1134 ////AIF1 Master Clock(SR=8KHz)
1135         wm8994_write(0x200,  0x0011);
1136 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1137         wm8994_write(0x302,  0x4000);
1138 #endif
1139         wm8994_write(0x303,  0x00F0);
1140         wm8994_write(0x304,  0x0020);
1141         wm8994_write(0x305,  0x0020);
1142
1143 ////AIF1 DAC1 HP
1144         wm8994_write(0x05,   0x3303);
1145         wm8994_write(0x420,  0x0000);
1146         wm8994_write(0x601,  0x0001);
1147         wm8994_write(0x602,  0x0001);
1148         wm8994_write(0x700,  0x8140);  //SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1149 }
1150
1151 void  mainMIC_to_PCMbaseband_to_earpiece(void)
1152 {
1153
1154         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1155
1156         wm8994_mode=wm8994_mainMIC_to_PCMbaseband_to_earpiece;
1157         wm8994_reset();
1158         mdelay(WM8994_DELAY);
1159
1160         wm8994_write(0x01,  0x0013);
1161         mdelay(WM8994_DELAY);
1162         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1163         wm8994_write(0x222, 0x3127);
1164         wm8994_write(0x223, 0x0100);
1165         wm8994_write(0x220, 0x0004);
1166         mdelay(WM8994_DELAY);
1167         wm8994_write(0x220, 0x0005);
1168
1169         wm8994_write(0x01,  0x0813);
1170         wm8994_write(0x02,  0x0110);
1171         wm8994_write(0x03,  0x00F0);
1172         wm8994_write(0x04,  0x3003);
1173         wm8994_write(0x05,  0x3003);
1174         wm8994_write(0x1A,  0x010B);
1175         wm8994_write(0x1F,  0x0000);
1176         wm8994_write(0x28,  0x0003);
1177         wm8994_write(0x2A,  0x0020);
1178         wm8994_write(0x2D,  0x0001);
1179         wm8994_write(0x2E,  0x0001);
1180         wm8994_write(0x33,  0x0018);
1181         wm8994_write(0x200, 0x0001);
1182         wm8994_write(0x204, 0x0001);
1183         wm8994_write(0x208, 0x0007);
1184         wm8994_write(0x520, 0x0000);
1185         wm8994_write(0x601, 0x0004);
1186         wm8994_write(0x602, 0x0004);
1187
1188         wm8994_write(0x610, 0x01C0);
1189         wm8994_write(0x611, 0x01C0);
1190         wm8994_write(0x612, 0x01C0);
1191         wm8994_write(0x613, 0x01C0);
1192
1193         wm8994_write(0x700, 0x8141);
1194         wm8994_write(0x702, 0xC100);
1195         wm8994_write(0x703, 0xC100);
1196         wm8994_write(0x704, 0xC100);
1197         wm8994_write(0x706, 0x4100);
1198         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1199         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1200         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1201         wm8994_write(0x313, 0x00F0);
1202         wm8994_write(0x314, 0x0020);
1203         wm8994_write(0x315, 0x0020);
1204
1205         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1206         wm8994_write(0x604, 0x0010);
1207         wm8994_write(0x605, 0x0010);
1208         wm8994_write(0x621, 0x0001);
1209
1210 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1211         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1212 #endif
1213 }
1214
1215 void  mainMIC_to_PCMbaseband_to_earpiece_and_record(void)
1216 {
1217
1218         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1219
1220         wm8994_mode=wm8994_mainMIC_to_PCMbaseband_to_earpiece_and_record;
1221         wm8994_reset();
1222         mdelay(WM8994_DELAY);
1223
1224         wm8994_write(0x01,  0x0013);
1225         mdelay(WM8994_DELAY);
1226         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1227         wm8994_write(0x222, 0x3127);
1228         wm8994_write(0x223, 0x0100);
1229         wm8994_write(0x220, 0x0004);
1230         mdelay(WM8994_DELAY);
1231         wm8994_write(0x220, 0x0005);
1232
1233         wm8994_write(0x01,  0x0813);
1234         wm8994_write(0x02,  0x0110);
1235         wm8994_write(0x03,  0x00F0);
1236         wm8994_write(0x04,  0x3003);
1237         wm8994_write(0x05,  0x3003);
1238         wm8994_write(0x1A,  0x010B);
1239         wm8994_write(0x1F,  0x0000);
1240         wm8994_write(0x28,  0x0003);
1241         wm8994_write(0x2A,  0x0020);
1242         wm8994_write(0x2D,  0x0001);
1243         wm8994_write(0x2E,  0x0001);
1244         wm8994_write(0x33,  0x0018);
1245         wm8994_write(0x200, 0x0001);
1246         wm8994_write(0x204, 0x0001);
1247         wm8994_write(0x208, 0x0007);
1248         wm8994_write(0x520, 0x0000);
1249         wm8994_write(0x601, 0x0004);
1250         wm8994_write(0x602, 0x0004);
1251
1252         wm8994_write(0x610, 0x01C0);
1253         wm8994_write(0x611, 0x01C0);
1254         wm8994_write(0x612, 0x01C0);
1255         wm8994_write(0x613, 0x01C0);
1256
1257         wm8994_write(0x702, 0xC100);
1258         wm8994_write(0x703, 0xC100);
1259         wm8994_write(0x704, 0xC100);
1260         wm8994_write(0x706, 0x4100);
1261         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1262         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1263         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1264         wm8994_write(0x313, 0x00F0);
1265         wm8994_write(0x314, 0x0020);
1266         wm8994_write(0x315, 0x0020);
1267
1268         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1269         wm8994_write(0x604, 0x0010);
1270         wm8994_write(0x605, 0x0010);
1271         wm8994_write(0x621, 0x0001);
1272
1273 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1274         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1275 #endif
1276
1277 ////AIF1
1278         wm8994_write(0x04,   0x3303);
1279         wm8994_write(0x200,  0x0001);
1280         wm8994_write(0x208,  0x000F);
1281         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1282         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1283         wm8994_write(0x606,  0x0003);
1284         wm8994_write(0x607,  0x0003);
1285
1286 ////AIF1 Master Clock(SR=8KHz)
1287         wm8994_write(0x200,  0x0011);
1288 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1289         wm8994_write(0x302,  0x4000);
1290 #endif
1291         wm8994_write(0x303,  0x00F0);
1292         wm8994_write(0x304,  0x0020);
1293         wm8994_write(0x305,  0x0020);
1294
1295 ////AIF1 DAC1 HP
1296         wm8994_write(0x05,   0x3303);
1297         wm8994_write(0x420,  0x0000);
1298         wm8994_write(0x601,  0x0001);
1299         wm8994_write(0x602,  0x0001);
1300         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1301 }
1302
1303 void  mainMIC_to_PCMbaseband_to_speakers(void)
1304 {
1305
1306         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1307
1308         wm8994_mode=wm8994_mainMIC_to_PCMbaseband_to_speakers;
1309         wm8994_reset();
1310         mdelay(WM8994_DELAY);
1311
1312         wm8994_write(0x01,  0x0013);
1313         mdelay(WM8994_DELAY);
1314         wm8994_write(0x221, 0x0700);  //MCLK=12MHz   //FLL1 CONTRLO(2)
1315         wm8994_write(0x222, 0x3127);  //FLL1 CONTRLO(3)
1316         wm8994_write(0x223, 0x0100);  //FLL1 CONTRLO(4)
1317         wm8994_write(0x220, 0x0004);  //FLL1 CONTRLO(1)
1318         mdelay(WM8994_DELAY);
1319         wm8994_write(0x220, 0x0005);  //FLL1 CONTRLO(1)
1320
1321         wm8994_write(0x01,  0x3013);
1322         wm8994_write(0x02,  0x0110);
1323         wm8994_write(0x03,  0x0330);
1324         wm8994_write(0x04,  0x3003);
1325         wm8994_write(0x05,  0x3003);
1326         wm8994_write(0x1A,  0x011F);
1327         wm8994_write(0x22,  0x0000);
1328         wm8994_write(0x23,  0x0000);
1329         wm8994_write(0x28,  0x0003);
1330         wm8994_write(0x2A,  0x0020);
1331         wm8994_write(0x2D,  0x0001);
1332         wm8994_write(0x2E,  0x0001);
1333         wm8994_write(0x36,  0x000C);  //MIXOUTL_TO_SPKMIXL  MIXOUTR_TO_SPKMIXR
1334         wm8994_write(0x200, 0x0001);  //AIF1 CLOCKING(1)
1335         wm8994_write(0x204, 0x0001);  //AIF2 CLOCKING(1)
1336         wm8994_write(0x208, 0x0007);  //CLOCKING(1)
1337         wm8994_write(0x520, 0x0000);  //AIF2 DAC FILTERS(1)
1338         wm8994_write(0x601, 0x0004);  //AIF2DACL_DAC1L
1339         wm8994_write(0x602, 0x0004);  //AIF2DACR_DAC1R
1340
1341         wm8994_write(0x610, 0x01C0);  //DAC1L_VOLUME
1342         wm8994_write(0x611, 0x01C0);  //DAC1R_VOLUME
1343         wm8994_write(0x612, 0x01C0);  //DAC2L_VOLUME
1344         wm8994_write(0x613, 0x01C0);  //DAC2R_VOLUME
1345
1346         wm8994_write(0x702, 0xC100);  //GPIO3
1347         wm8994_write(0x703, 0xC100);  //GPIO4
1348         wm8994_write(0x704, 0xC100);  //GPIO5
1349         wm8994_write(0x706, 0x4100);  //GPIO7
1350         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1351         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1352         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1353         wm8994_write(0x313, 0x00F0);  //AIF2BCLK
1354         wm8994_write(0x314, 0x0020);  //AIF2ADCLRCK
1355         wm8994_write(0x315, 0x0020);  //AIF2DACLRCLK
1356
1357         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1358         wm8994_write(0x604, 0x0010);  //ADC2_TO_DAC2L
1359         wm8994_write(0x605, 0x0010);  //ADC2_TO_DAC2R
1360         wm8994_write(0x621, 0x0001);
1361
1362 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1363         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1364 #endif
1365 }
1366
1367 void  mainMIC_to_PCMbaseband_to_speakers_and_record(void)
1368 {
1369
1370         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1371
1372         wm8994_mode=wm8994_mainMIC_to_PCMbaseband_to_speakers_and_record;
1373         wm8994_reset();
1374         mdelay(WM8994_DELAY);
1375
1376         wm8994_write(0x01,  0x0013);
1377         mdelay(WM8994_DELAY);
1378         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1379         wm8994_write(0x222, 0x3127);
1380         wm8994_write(0x223, 0x0100);
1381         wm8994_write(0x220, 0x0004);
1382         mdelay(WM8994_DELAY);
1383         wm8994_write(0x220, 0x0005);
1384
1385         wm8994_write(0x01,  0x3013);
1386         wm8994_write(0x02,  0x0110);
1387         wm8994_write(0x03,  0x0330);
1388         wm8994_write(0x04,  0x3003);
1389         wm8994_write(0x05,  0x3003);
1390         wm8994_write(0x1A,  0x010B);
1391         wm8994_write(0x22,  0x0000);
1392         wm8994_write(0x23,  0x0000);
1393         wm8994_write(0x28,  0x0003);
1394         wm8994_write(0x2A,  0x0020);
1395         wm8994_write(0x2D,  0x0001);
1396         wm8994_write(0x2E,  0x0001);
1397         wm8994_write(0x36,  0x000C);
1398         wm8994_write(0x200, 0x0001);
1399         wm8994_write(0x204, 0x0001);
1400         wm8994_write(0x208, 0x0007);
1401         wm8994_write(0x520, 0x0000);
1402         wm8994_write(0x601, 0x0004);
1403         wm8994_write(0x602, 0x0004);
1404
1405         wm8994_write(0x610, 0x01C0);
1406         wm8994_write(0x611, 0x01C0);
1407         wm8994_write(0x612, 0x01C0);
1408         wm8994_write(0x613, 0x01C0);
1409
1410         wm8994_write(0x700, 0x8141);
1411         wm8994_write(0x702, 0xC100);
1412         wm8994_write(0x703, 0xC100);
1413         wm8994_write(0x704, 0xC100);
1414         wm8994_write(0x706, 0x4100);
1415         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1416         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1417         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1418         wm8994_write(0x313, 0x00F0);
1419         wm8994_write(0x314, 0x0020);
1420         wm8994_write(0x315, 0x0020);
1421
1422         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1423         wm8994_write(0x604, 0x0010);
1424         wm8994_write(0x605, 0x0010);
1425         wm8994_write(0x621, 0x0001);
1426 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1427         wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1428 #endif
1429
1430 ////AIF1
1431         wm8994_write(0x04,   0x3303);
1432         wm8994_write(0x200,  0x0001);
1433         wm8994_write(0x208,  0x000F);
1434         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1435         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1436         wm8994_write(0x606,  0x0003);
1437         wm8994_write(0x607,  0x0003);
1438
1439 ////AIF1 Master Clock(SR=8KHz)
1440         wm8994_write(0x200,  0x0011);
1441 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1442         wm8994_write(0x302,  0x4000);
1443 #endif
1444         wm8994_write(0x303,  0x00F0);
1445         wm8994_write(0x304,  0x0020);
1446         wm8994_write(0x305,  0x0020);
1447
1448 ////AIF1 DAC1 HP
1449         wm8994_write(0x05,   0x3303);
1450         wm8994_write(0x420,  0x0000);
1451         wm8994_write(0x601,  0x0001);
1452         wm8994_write(0x602,  0x0001);
1453         wm8994_write(0x700,  0x8140);  //SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1454 }
1455
1456 void  BT_PCMbaseband(void)
1457 {
1458
1459         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1460
1461         wm8994_mode=wm8994_BT_PCMbaseband;
1462         wm8994_reset();
1463         mdelay(WM8994_DELAY);
1464
1465         wm8994_write(0x01  ,0x0003);
1466         mdelay (WM8994_DELAY);
1467
1468         wm8994_write(0x200 ,0x0001);
1469         wm8994_write(0x221 ,0x0700);  //MCLK=12MHz
1470         wm8994_write(0x222 ,0x3127);
1471         wm8994_write(0x223 ,0x0100);
1472         wm8994_write(0x220 ,0x0004);
1473         mdelay (WM8994_DELAY);
1474         wm8994_write(0x220 ,0x0005);
1475
1476         wm8994_write(0x02  ,0x0000);
1477         wm8994_write(0x200 ,0x0011);  // AIF1 MCLK=FLL1
1478         wm8994_write(0x210 ,0x0009);  // LRCK=8KHz, Rate=MCLK/1536
1479         wm8994_write(0x300 ,0x4018);  // DSP/PCM 16bits
1480
1481         wm8994_write(0x204 ,0x0011);  // AIF2 MCLK=FLL1
1482         wm8994_write(0x211 ,0x0009);  // LRCK=8KHz, Rate=MCLK/1536
1483         wm8994_write(0x310 ,0x4118);  // DSP/PCM 16bits
1484         wm8994_write(0x208 ,0x000F);
1485
1486 /////AIF1
1487         wm8994_write(0x700 ,0x8101);
1488 /////AIF2
1489         wm8994_write(0x702 ,0xC100);
1490         wm8994_write(0x703 ,0xC100);
1491         wm8994_write(0x704 ,0xC100);
1492         wm8994_write(0x706 ,0x4100);
1493 /////AIF3
1494         wm8994_write(0x707 ,0xA100);
1495         wm8994_write(0x708 ,0xA100);
1496         wm8994_write(0x709 ,0xA100);
1497         wm8994_write(0x70A ,0xA100);
1498
1499         wm8994_write(0x06 ,0x0001);
1500
1501         wm8994_write(0x02 ,0x0300);
1502         wm8994_write(0x03 ,0x0030);
1503         wm8994_write(0x04 ,0x3301);  //ADCL off
1504         wm8994_write(0x05 ,0x3301);  //DACL off
1505
1506         wm8994_write(0x2A ,0x0005);
1507
1508         wm8994_write(0x313 ,0x00F0);
1509         wm8994_write(0x314 ,0x0020);
1510         wm8994_write(0x315 ,0x0020);
1511
1512         wm8994_write(0x2E  ,0x0001);
1513         wm8994_write(0x420 ,0x0000);
1514         wm8994_write(0x520 ,0x0000);
1515         wm8994_write(0x602 ,0x0001);
1516         wm8994_write(0x604 ,0x0001);
1517         wm8994_write(0x605 ,0x0001);
1518         wm8994_write(0x607 ,0x0002);
1519         wm8994_write(0x611 ,0x01C0);
1520         wm8994_write(0x612 ,0x01C0);
1521         wm8994_write(0x613 ,0x01C0);
1522
1523 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1524         wm8994_write(0x312 ,0x4000);
1525 #endif
1526
1527         wm8994_write(0x606 ,0x0001);
1528         wm8994_write(0x607 ,0x0003);  //R channel for data mix/CPU record data
1529
1530 ////////////HP output test
1531         wm8994_write(0x01  ,0x0303);
1532         wm8994_write(0x4C  ,0x9F25);
1533         wm8994_write(0x60  ,0x00EE);
1534 ///////////end HP test
1535 }
1536
1537 void  BT_PCMbaseband_and_record(void)
1538 {
1539
1540         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1541
1542         wm8994_mode=wm8994_BT_PCMbaseband_and_record;
1543         wm8994_reset();
1544         mdelay(WM8994_DELAY);
1545
1546         wm8994_write(0x01  ,0x0003);
1547         mdelay (WM8994_DELAY);
1548
1549         wm8994_write(0x200 ,0x0001);
1550         wm8994_write(0x221 ,0x0700);  //MCLK=12MHz
1551         wm8994_write(0x222 ,0x3127);
1552         wm8994_write(0x223 ,0x0100);
1553         wm8994_write(0x220 ,0x0004);
1554         mdelay (WM8994_DELAY);
1555         wm8994_write(0x220 ,0x0005);
1556
1557         wm8994_write(0x02  ,0x0000);
1558         wm8994_write(0x200 ,0x0011);  // AIF1 MCLK=FLL1
1559         wm8994_write(0x210 ,0x0009);  // LRCK=8KHz, Rate=MCLK/1536
1560         wm8994_write(0x300 ,0x4018);  // DSP/PCM 16bits
1561
1562         wm8994_write(0x204 ,0x0011);  // AIF2 MCLK=FLL1
1563         wm8994_write(0x211 ,0x0009);  // LRCK=8KHz, Rate=MCLK/1536
1564         wm8994_write(0x310 ,0x4118);  // DSP/PCM 16bits
1565         wm8994_write(0x208 ,0x000F);
1566
1567 /////AIF1
1568         wm8994_write(0x700 ,0x8101);
1569 /////AIF2
1570         wm8994_write(0x702 ,0xC100);
1571         wm8994_write(0x703 ,0xC100);
1572         wm8994_write(0x704 ,0xC100);
1573         wm8994_write(0x706 ,0x4100);
1574 /////AIF3
1575         wm8994_write(0x707 ,0xA100);
1576         wm8994_write(0x708 ,0xA100);
1577         wm8994_write(0x709 ,0xA100);
1578         wm8994_write(0x70A ,0xA100);
1579
1580         wm8994_write(0x06  ,0x0001);
1581
1582         wm8994_write(0x02  ,0x0300);
1583         wm8994_write(0x03  ,0x0030);
1584         wm8994_write(0x04  ,0x3301);  //ADCL off
1585         wm8994_write(0x05  ,0x3301);  //DACL off
1586
1587         wm8994_write(0x2A  ,0x0005);
1588
1589         wm8994_write(0x313 ,0x00F0);
1590         wm8994_write(0x314 ,0x0020);
1591         wm8994_write(0x315 ,0x0020);
1592
1593         wm8994_write(0x2E  ,0x0001);
1594         wm8994_write(0x420 ,0x0000);
1595         wm8994_write(0x520 ,0x0000);
1596         wm8994_write(0x602 ,0x0001);
1597         wm8994_write(0x604 ,0x0001);
1598         wm8994_write(0x605 ,0x0001);
1599         wm8994_write(0x607 ,0x0002);
1600         wm8994_write(0x611 ,0x01C0);
1601         wm8994_write(0x612 ,0x01C0);
1602         wm8994_write(0x613 ,0x01C0);
1603
1604 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1605         wm8994_write(0x312 ,0x4000);
1606 #endif
1607
1608         wm8994_write(0x606 ,0x0001);
1609         wm8994_write(0x607 ,0x0003);  //R channel for data mix/CPU record data
1610
1611 ////////////HP output test
1612         wm8994_write(0x01  ,0x0303);
1613         wm8994_write(0x4C  ,0x9F25);
1614         wm8994_write(0x60  ,0x00EE);
1615 ///////////end HP test
1616 }
1617
1618
1619 typedef void (wm8994_codec_fnc_t) (void);
1620
1621 wm8994_codec_fnc_t *wm8994_codec_sequence[] = {
1622         AP_to_headset,
1623         AP_to_speakers,
1624         recorder,
1625         recorder_and_AP_to_headset,
1626         recorder_and_AP_to_speakers,
1627         FM_to_headset,
1628         FM_to_headset_and_record,
1629         FM_to_speakers,
1630         FM_to_speakers_and_record,
1631         handsetMIC_to_baseband_to_headset,
1632         handsetMIC_to_baseband_to_headset_and_record,
1633         mainMIC_to_baseband_to_earpiece,
1634         mainMIC_to_baseband_to_earpiece_and_record,
1635         mainMIC_to_baseband_to_speakers,
1636         mainMIC_to_baseband_to_speakers_and_record,
1637         BT_baseband,
1638         BT_baseband_and_record,
1639 ///PCM BB BEGIN
1640         handsetMIC_to_PCMbaseband_to_headset,
1641         handsetMIC_to_PCMbaseband_to_headset_and_record,
1642         mainMIC_to_PCMbaseband_to_earpiece,
1643         mainMIC_to_PCMbaseband_to_earpiece_and_record,
1644         mainMIC_to_PCMbaseband_to_speakers,
1645         mainMIC_to_PCMbaseband_to_speakers_and_record,
1646         BT_PCMbaseband,
1647         BT_PCMbaseband_and_record
1648 ///PCM BB END
1649 };
1650
1651 /*************set wm8994 volume****************/
1652
1653 unsigned char handset_maxvol=0x3f,VRX_maxvol=0x07,speaker_maxvol=0x3f,AP_maxvol=0xff,recorder_maxvol=0x1f,FM_maxvol=0x1f;
1654
1655 void wm8994_codec_set_volume(unsigned char mode,unsigned char volume)
1656 {
1657         unsigned short lvol=0,rvol=0;
1658
1659         if(wm8994_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record||
1660         wm8994_mode==wm8994_handsetMIC_to_baseband_to_headset)
1661         {
1662                 wm8994_read(0x001c, &lvol);
1663                 wm8994_read(0x001d, &rvol);
1664                 wm8994_write(0x001c ,(0x0100|(lvol&0xffc0))|(0x003f&(handset_maxvol*volume/7)));//bit 0~5  -57dB~6dB
1665                 wm8994_write(0x001d ,(0x0100|(rvol&0xffc0))|(0x003f&(handset_maxvol*volume/7)));//bit 0~5 / -57dB~6dB
1666         }
1667         else if(wm8994_mode==wm8994_BT_baseband_and_record||wm8994_mode==wm8994_BT_baseband||
1668         wm8994_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record||
1669         wm8994_mode==wm8994_mainMIC_to_baseband_to_earpiece)
1670         {
1671                 wm8994_read(0x002b, &lvol);
1672                 wm8994_write(0x002b ,(0x0100|(lvol&0xfff8))|(0x0007&(VRX_maxvol*volume/7))); //bit 0~2 / -12dB~6dB
1673         }
1674         else if(wm8994_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record||
1675         wm8994_mode==wm8994_mainMIC_to_baseband_to_speakers)
1676         {
1677                 wm8994_read(0x0026, &lvol);
1678                 wm8994_write(0x0026 ,(0x0100|(lvol&0xffc0))|(0x003f&(speaker_maxvol*volume/7))); //bit0~5 / -57dB~6dB
1679         }
1680         else if(wm8994_mode==wm8994_AP_to_headset||wm8994_mode==wm8994_AP_to_speakers)
1681         {
1682                 wm8994_read(0x0610, &lvol);
1683                 wm8994_read(0x0611, &rvol);
1684                 wm8994_write(0x0610 ,(0x0100|(lvol&0xff00))|(0x00ff&(AP_maxvol*volume/7))); //bit 0~7 / -71.625dB~0dB
1685                 wm8994_write(0x0611 ,(0x0100|(rvol&0xff00))|(0x00ff&(AP_maxvol*volume/7))); //bit 0~7 / -71.625dB~0dB
1686         }
1687         else if(wm8994_mode==wm8994_recorder)
1688         {
1689                 wm8994_read(0x001a, &lvol);
1690                 wm8994_write(0x001a ,(0x0100|(lvol&0xffe0))|(0x001f&(recorder_maxvol*volume/7))); //bit 0~4 / -16.5dB~30dB
1691         }
1692         else if(wm8994_mode==wm8994_FM_to_headset||wm8994_mode==wm8994_FM_to_headset_and_record||
1693         wm8994_mode==wm8994_FM_to_speakers||wm8994_mode==wm8994_FM_to_speakers_and_record)
1694         {
1695                 wm8994_read(0x0019, &lvol);
1696                 wm8994_read(0x001b, &rvol);
1697                 wm8994_write(0x0019 ,(0x0100|(lvol&0xffe0))|(0x001f&(FM_maxvol*volume/7))); //bit 0~4 / -16.5dB~30dB
1698                 wm8994_write(0x001b ,(0x0100|(rvol&0xffe0))|(0x001f&(FM_maxvol*volume/7))); //bit 0~4 / -16.5dB~30dB
1699         }
1700 }
1701
1702
1703 #define SOC_DOUBLE_SWITCH_WM8994CODEC(xname, route) \
1704 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
1705         .info = snd_soc_info_route, \
1706         .get = snd_soc_get_route, .put = snd_soc_put_route, \
1707         .private_value = route }
1708
1709 int snd_soc_info_route(struct snd_kcontrol *kcontrol,
1710         struct snd_ctl_elem_info *uinfo)
1711 {
1712         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1713
1714         uinfo->count = 1;
1715         uinfo->value.integer.min = 0;
1716         uinfo->value.integer.max = 0;
1717         return 0;
1718 }
1719
1720 int snd_soc_get_route(struct snd_kcontrol *kcontrol,
1721         struct snd_ctl_elem_value *ucontrol)
1722 {
1723         return 0;
1724 }
1725
1726 int snd_soc_put_route(struct snd_kcontrol *kcontrol,
1727         struct snd_ctl_elem_value *ucontrol)
1728 {
1729
1730         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1731         int route = kcontrol->private_value & 0xff;
1732
1733         switch(route)
1734         {
1735                 /* Speaker*/
1736                 case SPEAKER_NORMAL: //AP-> 8994Codec -> Speaker
1737                     AP_to_speakers();
1738                     break;
1739                 case SPEAKER_INCALL: //BB-> 8994Codec -> Speaker
1740                     mainMIC_to_baseband_to_speakers();
1741                     break;
1742
1743                 /* Headset */
1744                 case HEADSET_NORMAL:    //AP-> 8994Codec -> Headset
1745                     AP_to_headset();
1746                     break;
1747                 case HEADSET_INCALL:    //AP-> 8994Codec -> Headset
1748                     handsetMIC_to_baseband_to_headset();
1749                     break;
1750
1751                 /* Earpiece*/
1752                 case EARPIECE_INCALL:   //:BB-> 8994Codec -> EARPIECE
1753                     mainMIC_to_baseband_to_earpiece();
1754                     break;
1755
1756                 /* BLUETOOTH_SCO*/
1757                 case BLUETOOTH_SCO_INCALL:      //BB-> 8994Codec -> BLUETOOTH_SCO
1758                     BT_baseband();
1759                     break;
1760
1761                 /* BLUETOOTH_A2DP*/
1762                 case BLUETOOTH_A2DP_NORMAL:     //AP-> 8994Codec -> BLUETOOTH_A2DP
1763                     break;
1764
1765                 case MIC_CAPTURE:
1766                     if(wm8994_mode==wm8994_AP_to_headset)
1767                         recorder_and_AP_to_headset();
1768                     else if(wm8994_mode==wm8994_AP_to_speakers)
1769                         recorder_and_AP_to_speakers();
1770                     else
1771                         recorder_and_AP_to_speakers();
1772
1773                         printk("%s--%d--: wm8994 with null mode\n",__FUNCTION__,__LINE__);
1774
1775                     break;
1776
1777                 default:
1778                     //codec_daout_route();
1779                     break;
1780         }
1781         return 0;
1782 }
1783
1784 /*
1785  * WM8994 Controls
1786  */
1787
1788 static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
1789 static const struct soc_enum bass_boost =
1790         SOC_ENUM_SINGLE(WM8994_BASS, 7, 2, bass_boost_txt);
1791
1792 static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
1793 static const struct soc_enum bass_filter =
1794         SOC_ENUM_SINGLE(WM8994_BASS, 6, 2, bass_filter_txt);
1795
1796 static const char *treble_txt[] = {"8kHz", "4kHz"};
1797 static const struct soc_enum treble =
1798         SOC_ENUM_SINGLE(WM8994_TREBLE, 6, 2, treble_txt);
1799
1800 static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
1801 static const struct soc_enum stereo_3d_lc =
1802         SOC_ENUM_SINGLE(WM8994_3D, 5, 2, stereo_3d_lc_txt);
1803
1804 static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
1805 static const struct soc_enum stereo_3d_uc =
1806         SOC_ENUM_SINGLE(WM8994_3D, 6, 2, stereo_3d_uc_txt);
1807
1808 static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
1809 static const struct soc_enum stereo_3d_func =
1810         SOC_ENUM_SINGLE(WM8994_3D, 7, 2, stereo_3d_func_txt);
1811
1812 static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
1813 static const struct soc_enum alc_func =
1814         SOC_ENUM_SINGLE(WM8994_ALC1, 7, 4, alc_func_txt);
1815
1816 static const char *ng_type_txt[] = {"Constant PGA Gain",
1817                                     "Mute ADC Output"};
1818 static const struct soc_enum ng_type =
1819         SOC_ENUM_SINGLE(WM8994_NGATE, 1, 2, ng_type_txt);
1820
1821 static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
1822 static const struct soc_enum deemph =
1823         SOC_ENUM_SINGLE(WM8994_ADCDAC, 1, 4, deemph_txt);
1824
1825 static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
1826                                    "L + R Invert"};
1827 static const struct soc_enum adcpol =
1828         SOC_ENUM_SINGLE(WM8994_ADCDAC, 5, 4, adcpol_txt);
1829
1830 static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
1831 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
1832 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
1833 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1834 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1835
1836 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
1837
1838 /* 鍠囧彮 */
1839 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker incall Switch", SPEAKER_INCALL),
1840 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker normal Switch", SPEAKER_NORMAL),
1841 /* 鍚瓛 */
1842 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece incall Switch", EARPIECE_INCALL),
1843 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece normal Switch", EARPIECE_NORMAL),
1844 /* 鑰虫満 */
1845 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset incall Switch", HEADSET_INCALL),
1846 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset normal Switch", HEADSET_NORMAL),
1847 /* 钃濈墮SCO */
1848 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth incall Switch", BLUETOOTH_SCO_INCALL),
1849 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth normal Switch", BLUETOOTH_SCO_NORMAL),
1850 /* 钃濈墮A2DP */
1851 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP incall Switch", BLUETOOTH_A2DP_INCALL),
1852 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP normal Switch", BLUETOOTH_A2DP_NORMAL),
1853 /* 鑰抽害 */
1854 SOC_DOUBLE_SWITCH_WM8994CODEC("Capture Switch", MIC_CAPTURE),
1855
1856 };
1857
1858 /*
1859  * DAPM Controls
1860  */
1861
1862 static int wm8994_lrc_control(struct snd_soc_dapm_widget *w,
1863                               struct snd_kcontrol *kcontrol, int event)
1864 {
1865         return 0;
1866 }
1867
1868 static const char *wm8994_line_texts[] = {
1869         "Line 1", "Line 2", "PGA", "Differential"};
1870
1871 static const unsigned int wm8994_line_values[] = {
1872         0, 1, 3, 4};
1873
1874 static const struct soc_enum wm8994_lline_enum =
1875         SOC_VALUE_ENUM_SINGLE(WM8994_LOUTM1, 0, 7,
1876                               ARRAY_SIZE(wm8994_line_texts),
1877                               wm8994_line_texts,
1878                               wm8994_line_values);
1879 static const struct snd_kcontrol_new wm8994_left_line_controls =
1880         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
1881
1882 static const struct soc_enum wm8994_rline_enum =
1883         SOC_VALUE_ENUM_SINGLE(WM8994_ROUTM1, 0, 7,
1884                               ARRAY_SIZE(wm8994_line_texts),
1885                               wm8994_line_texts,
1886                               wm8994_line_values);
1887 static const struct snd_kcontrol_new wm8994_right_line_controls =
1888         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
1889
1890 /* Left Mixer */
1891 static const struct snd_kcontrol_new wm8994_left_mixer_controls[] = {
1892         SOC_DAPM_SINGLE("Playback Switch", WM8994_LOUTM1, 8, 1, 0),
1893         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_LOUTM1, 7, 1, 0),
1894         SOC_DAPM_SINGLE("Right Playback Switch", WM8994_LOUTM2, 8, 1, 0),
1895         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_LOUTM2, 7, 1, 0),
1896 };
1897
1898 /* Right Mixer */
1899 static const struct snd_kcontrol_new wm8994_right_mixer_controls[] = {
1900         SOC_DAPM_SINGLE("Left Playback Switch", WM8994_ROUTM1, 8, 1, 0),
1901         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_ROUTM1, 7, 1, 0),
1902         SOC_DAPM_SINGLE("Playback Switch", WM8994_ROUTM2, 8, 1, 0),
1903         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_ROUTM2, 7, 1, 0),
1904 };
1905
1906 static const char *wm8994_pga_sel[] = {"Line 1", "Line 2", "Differential"};
1907 static const unsigned int wm8994_pga_val[] = { 0, 1, 3 };
1908
1909 /* Left PGA Mux */
1910 static const struct soc_enum wm8994_lpga_enum =
1911         SOC_VALUE_ENUM_SINGLE(WM8994_LADCIN, 6, 3,
1912                               ARRAY_SIZE(wm8994_pga_sel),
1913                               wm8994_pga_sel,
1914                               wm8994_pga_val);
1915 static const struct snd_kcontrol_new wm8994_left_pga_controls =
1916         SOC_DAPM_VALUE_ENUM("Route", wm8994_lpga_enum);
1917
1918 /* Right PGA Mux */
1919 static const struct soc_enum wm8994_rpga_enum =
1920         SOC_VALUE_ENUM_SINGLE(WM8994_RADCIN, 6, 3,
1921                               ARRAY_SIZE(wm8994_pga_sel),
1922                               wm8994_pga_sel,
1923                               wm8994_pga_val);
1924 static const struct snd_kcontrol_new wm8994_right_pga_controls =
1925         SOC_DAPM_VALUE_ENUM("Route", wm8994_rpga_enum);
1926
1927 /* Differential Mux */
1928 static const char *wm8994_diff_sel[] = {"Line 1", "Line 2"};
1929 static const struct soc_enum diffmux =
1930         SOC_ENUM_SINGLE(WM8994_ADCIN, 8, 2, wm8994_diff_sel);
1931 static const struct snd_kcontrol_new wm8994_diffmux_controls =
1932         SOC_DAPM_ENUM("Route", diffmux);
1933
1934 /* Mono ADC Mux */
1935 static const char *wm8994_mono_mux[] = {"Stereo", "Mono (Left)",
1936         "Mono (Right)", "Digital Mono"};
1937 static const struct soc_enum monomux =
1938         SOC_ENUM_SINGLE(WM8994_ADCIN, 6, 4, wm8994_mono_mux);
1939 static const struct snd_kcontrol_new wm8994_monomux_controls =
1940         SOC_DAPM_ENUM("Route", monomux);
1941
1942 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1943         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8994_PWR1, 1, 0),
1944
1945         SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
1946                 &wm8994_diffmux_controls),
1947         SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
1948                 &wm8994_monomux_controls),
1949         SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
1950                 &wm8994_monomux_controls),
1951
1952         SND_SOC_DAPM_MUX("Left PGA Mux", WM8994_PWR1, 5, 0,
1953                 &wm8994_left_pga_controls),
1954         SND_SOC_DAPM_MUX("Right PGA Mux", WM8994_PWR1, 4, 0,
1955                 &wm8994_right_pga_controls),
1956
1957         SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
1958                 &wm8994_left_line_controls),
1959         SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
1960                 &wm8994_right_line_controls),
1961
1962         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8994_PWR1, 2, 0),
1963         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8994_PWR1, 3, 0),
1964
1965         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8994_PWR2, 7, 0),
1966         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8994_PWR2, 8, 0),
1967
1968         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
1969                 &wm8994_left_mixer_controls[0],
1970                 ARRAY_SIZE(wm8994_left_mixer_controls)),
1971         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
1972                 &wm8994_right_mixer_controls[0],
1973                 ARRAY_SIZE(wm8994_right_mixer_controls)),
1974
1975         SND_SOC_DAPM_PGA("Right Out 2", WM8994_PWR2, 3, 0, NULL, 0),
1976         SND_SOC_DAPM_PGA("Left Out 2", WM8994_PWR2, 4, 0, NULL, 0),
1977         SND_SOC_DAPM_PGA("Right Out 1", WM8994_PWR2, 5, 0, NULL, 0),
1978         SND_SOC_DAPM_PGA("Left Out 1", WM8994_PWR2, 6, 0, NULL, 0),
1979
1980         SND_SOC_DAPM_POST("LRC control", wm8994_lrc_control),
1981
1982         SND_SOC_DAPM_OUTPUT("LOUT1"),
1983         SND_SOC_DAPM_OUTPUT("ROUT1"),
1984         SND_SOC_DAPM_OUTPUT("LOUT2"),
1985         SND_SOC_DAPM_OUTPUT("ROUT2"),
1986         SND_SOC_DAPM_OUTPUT("VREF"),
1987
1988         SND_SOC_DAPM_INPUT("LINPUT1"),
1989         SND_SOC_DAPM_INPUT("LINPUT2"),
1990         SND_SOC_DAPM_INPUT("RINPUT1"),
1991         SND_SOC_DAPM_INPUT("RINPUT2"),
1992 };
1993
1994 static const struct snd_soc_dapm_route audio_map[] = {
1995
1996         { "Left Line Mux", "Line 1", "LINPUT1" },
1997         { "Left Line Mux", "Line 2", "LINPUT2" },
1998         { "Left Line Mux", "PGA", "Left PGA Mux" },
1999         { "Left Line Mux", "Differential", "Differential Mux" },
2000
2001         { "Right Line Mux", "Line 1", "RINPUT1" },
2002         { "Right Line Mux", "Line 2", "RINPUT2" },
2003         { "Right Line Mux", "PGA", "Right PGA Mux" },
2004         { "Right Line Mux", "Differential", "Differential Mux" },
2005
2006         { "Left PGA Mux", "Line 1", "LINPUT1" },
2007         { "Left PGA Mux", "Line 2", "LINPUT2" },
2008         { "Left PGA Mux", "Differential", "Differential Mux" },
2009
2010         { "Right PGA Mux", "Line 1", "RINPUT1" },
2011         { "Right PGA Mux", "Line 2", "RINPUT2" },
2012         { "Right PGA Mux", "Differential", "Differential Mux" },
2013
2014         { "Differential Mux", "Line 1", "LINPUT1" },
2015         { "Differential Mux", "Line 1", "RINPUT1" },
2016         { "Differential Mux", "Line 2", "LINPUT2" },
2017         { "Differential Mux", "Line 2", "RINPUT2" },
2018
2019         { "Left ADC Mux", "Stereo", "Left PGA Mux" },
2020         { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
2021         { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
2022
2023         { "Right ADC Mux", "Stereo", "Right PGA Mux" },
2024         { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
2025         { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
2026
2027         { "Left ADC", NULL, "Left ADC Mux" },
2028         { "Right ADC", NULL, "Right ADC Mux" },
2029
2030         { "Left Line Mux", "Line 1", "LINPUT1" },
2031         { "Left Line Mux", "Line 2", "LINPUT2" },
2032         { "Left Line Mux", "PGA", "Left PGA Mux" },
2033         { "Left Line Mux", "Differential", "Differential Mux" },
2034
2035         { "Right Line Mux", "Line 1", "RINPUT1" },
2036         { "Right Line Mux", "Line 2", "RINPUT2" },
2037         { "Right Line Mux", "PGA", "Right PGA Mux" },
2038         { "Right Line Mux", "Differential", "Differential Mux" },
2039
2040         { "Left Mixer", "Playback Switch", "Left DAC" },
2041         { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
2042         { "Left Mixer", "Right Playback Switch", "Right DAC" },
2043         { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
2044
2045         { "Right Mixer", "Left Playback Switch", "Left DAC" },
2046         { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
2047         { "Right Mixer", "Playback Switch", "Right DAC" },
2048         { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
2049
2050         { "Left Out 1", NULL, "Left Mixer" },
2051         { "LOUT1", NULL, "Left Out 1" },
2052         { "Right Out 1", NULL, "Right Mixer" },
2053         { "ROUT1", NULL, "Right Out 1" },
2054
2055         { "Left Out 2", NULL, "Left Mixer" },
2056         { "LOUT2", NULL, "Left Out 2" },
2057         { "Right Out 2", NULL, "Right Mixer" },
2058         { "ROUT2", NULL, "Right Out 2" },
2059 };
2060
2061 struct _coeff_div {
2062         u32 mclk;
2063         u32 rate;
2064         u16 fs;
2065         u8 sr:5;
2066         u8 usb:1;
2067 };
2068
2069 /* codec hifi mclk clock divider coefficients */
2070 static const struct _coeff_div coeff_div[] = {
2071         /* 8k */
2072         {12288000, 8000, 1536, 0x6, 0x0},
2073         {11289600, 8000, 1408, 0x16, 0x0},
2074         {18432000, 8000, 2304, 0x7, 0x0},
2075         {16934400, 8000, 2112, 0x17, 0x0},
2076         {12000000, 8000, 1500, 0x6, 0x1},
2077
2078         /* 11.025k */
2079         {11289600, 11025, 1024, 0x18, 0x0},
2080         {16934400, 11025, 1536, 0x19, 0x0},
2081         {12000000, 11025, 1088, 0x19, 0x1},
2082
2083         /* 16k */
2084         {12288000, 16000, 768, 0xa, 0x0},
2085         {18432000, 16000, 1152, 0xb, 0x0},
2086         {12000000, 16000, 750, 0xa, 0x1},
2087
2088         /* 22.05k */
2089         {11289600, 22050, 512, 0x1a, 0x0},
2090         {16934400, 22050, 768, 0x1b, 0x0},
2091         {12000000, 22050, 544, 0x1b, 0x1},
2092
2093         /* 32k */
2094         {12288000, 32000, 384, 0xc, 0x0},
2095         {18432000, 32000, 576, 0xd, 0x0},
2096         {12000000, 32000, 375, 0xa, 0x1},
2097
2098         /* 44.1k */
2099         {11289600, 44100, 256, 0x10, 0x0},
2100         {16934400, 44100, 384, 0x11, 0x0},
2101         {12000000, 44100, 272, 0x11, 0x1},
2102
2103         /* 48k */
2104         {12288000, 48000, 256, 0x0, 0x0},
2105         {18432000, 48000, 384, 0x1, 0x0},
2106         {12000000, 48000, 250, 0x0, 0x1},
2107
2108         /* 88.2k */
2109         {11289600, 88200, 128, 0x1e, 0x0},
2110         {16934400, 88200, 192, 0x1f, 0x0},
2111         {12000000, 88200, 136, 0x1f, 0x1},
2112
2113         /* 96k */
2114         {12288000, 96000, 128, 0xe, 0x0},
2115         {18432000, 96000, 192, 0xf, 0x0},
2116         {12000000, 96000, 125, 0xe, 0x1},
2117 };
2118
2119
2120 static inline int get_coeff(int mclk, int rate)
2121 {
2122         int i;
2123
2124         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
2125                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
2126                         return i;
2127         }
2128
2129         return -EINVAL;
2130 }
2131
2132 /* The set of rates we can generate from the above for each SYSCLK */
2133
2134 static unsigned int rates_12288[] = {
2135         8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
2136 };
2137
2138 static struct snd_pcm_hw_constraint_list constraints_12288 = {
2139         .count  = ARRAY_SIZE(rates_12288),
2140         .list   = rates_12288,
2141 };
2142
2143 static unsigned int rates_112896[] = {
2144         8000, 11025, 22050, 44100,
2145 };
2146
2147 static struct snd_pcm_hw_constraint_list constraints_112896 = {
2148         .count  = ARRAY_SIZE(rates_112896),
2149         .list   = rates_112896,
2150 };
2151
2152 static unsigned int rates_12[] = {
2153         8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
2154         48000, 88235, 96000,
2155 };
2156
2157 static struct snd_pcm_hw_constraint_list constraints_12 = {
2158         .count  = ARRAY_SIZE(rates_12),
2159         .list   = rates_12,
2160 };
2161
2162 /*
2163  * Note that this should be called from init rather than from hw_params.
2164  */
2165 static int wm8994_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2166                 int clk_id, unsigned int freq, int dir)
2167 {
2168         struct snd_soc_codec *codec = codec_dai->codec;
2169         struct wm8994_priv *wm8994 = codec->private_data;
2170
2171         DBG("%s----%d\n",__FUNCTION__,__LINE__);
2172
2173         switch (freq) {
2174         case 11289600:
2175         case 18432000:
2176         case 22579200:
2177         case 36864000:
2178                 wm8994->sysclk_constraints = &constraints_112896;
2179                 wm8994->sysclk = freq;
2180                 return 0;
2181
2182         case 12288000:
2183         case 16934400:
2184         case 24576000:
2185         case 33868800:
2186                 wm8994->sysclk_constraints = &constraints_12288;
2187                 wm8994->sysclk = freq;
2188                 return 0;
2189
2190         case 12000000:
2191         case 24000000:
2192                 wm8994->sysclk_constraints = &constraints_12;
2193                 wm8994->sysclk = freq;
2194                 return 0;
2195         }
2196         return -EINVAL;
2197 }
2198
2199 static int wm8994_set_dai_fmt(struct snd_soc_dai *codec_dai,
2200                 unsigned int fmt)
2201 {
2202         return 0;
2203 }
2204
2205 static int wm8994_pcm_startup(struct snd_pcm_substream *substream,
2206                               struct snd_soc_dai *dai)
2207 {
2208         struct snd_soc_codec *codec = dai->codec;
2209         struct wm8994_priv *wm8994 = codec->private_data;
2210
2211         /* The set of sample rates that can be supported depends on the
2212          * MCLK supplied to the CODEC - enforce this.
2213          */
2214
2215         if (!wm8994->sysclk) {
2216                 dev_err(codec->dev,
2217                         "No MCLK configured, call set_sysclk() on init\n");
2218                 return -EINVAL;
2219         }
2220
2221         snd_pcm_hw_constraint_list(substream->runtime, 0,
2222                                    SNDRV_PCM_HW_PARAM_RATE,
2223                                    wm8994->sysclk_constraints);
2224
2225         return 0;
2226 }
2227
2228 static int wm8994_pcm_hw_params(struct snd_pcm_substream *substream,
2229                                 struct snd_pcm_hw_params *params,
2230                                 struct snd_soc_dai *dai)
2231 {
2232         struct snd_soc_pcm_runtime *rtd = substream->private_data;
2233         struct snd_soc_device *socdev = rtd->socdev;
2234         struct snd_soc_codec *codec = socdev->card->codec;
2235         struct wm8994_priv *wm8994 = codec->private_data;
2236         int coeff;
2237
2238         coeff = get_coeff(wm8994->sysclk, params_rate(params));
2239         if (coeff < 0) {
2240                 coeff = get_coeff(wm8994->sysclk / 2, params_rate(params));
2241         }
2242         if (coeff < 0) {
2243                 dev_err(codec->dev,
2244                         "Unable to configure sample rate %dHz with %dHz MCLK\n",
2245                         params_rate(params), wm8994->sysclk);
2246                 return coeff;
2247         }
2248         params_format(params);
2249
2250         return 0;
2251 }
2252
2253 static int wm8994_mute(struct snd_soc_dai *dai, int mute)
2254 {
2255         return 0;
2256 }
2257
2258 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2259                                  enum snd_soc_bias_level level)
2260 {
2261
2262         codec->bias_level = level;
2263         return 0;
2264 }
2265
2266 #define WM8994_RATES SNDRV_PCM_RATE_48000
2267
2268 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2269         SNDRV_PCM_FMTBIT_S24_LE)
2270
2271 static struct snd_soc_dai_ops wm8994_ops = {
2272         .startup = wm8994_pcm_startup,
2273         .hw_params = wm8994_pcm_hw_params,
2274         .set_fmt = wm8994_set_dai_fmt,
2275         .set_sysclk = wm8994_set_dai_sysclk,
2276         .digital_mute = wm8994_mute,
2277 };
2278
2279 struct snd_soc_dai wm8994_dai = {
2280         .name = "WM8994",
2281         .playback = {
2282                 .stream_name = "Playback",
2283                 .channels_min = 1,
2284                 .channels_max = 2,
2285                 .rates = WM8994_RATES,
2286                 .formats = WM8994_FORMATS,
2287         },
2288         .capture = {
2289                 .stream_name = "Capture",
2290                 .channels_min = 2,
2291                 .channels_max = 2,
2292                 .rates = WM8994_RATES,
2293                 .formats = WM8994_FORMATS,
2294          },
2295         .ops = &wm8994_ops,
2296         .symmetric_rates = 1,
2297 };
2298 EXPORT_SYMBOL_GPL(wm8994_dai);
2299
2300 static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
2301 {
2302         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2303         struct snd_soc_codec *codec = socdev->card->codec;
2304
2305         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2306         wm8994_reset();
2307         mdelay(WM8994_DELAY);
2308         return 0;
2309 }
2310
2311 static int wm8994_resume(struct platform_device *pdev)
2312 {
2313         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2314         struct snd_soc_codec *codec = socdev->card->codec;
2315         int i;
2316         u8 data[2];
2317         u16 *cache = codec->reg_cache;
2318         wm8994_codec_fnc_t **wm8994_fnc_ptr=wm8994_codec_sequence;
2319
2320         /* Sync reg_cache with the hardware */
2321         for (i = 0; i < WM8994_NUM_REG; i++) {
2322                 if (i == WM8994_RESET)
2323                         continue;
2324                 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
2325                 data[1] = cache[i] & 0x00ff;
2326                 codec->hw_write(codec->control_data, data, 2);
2327         }
2328
2329         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2330         if(wm8994_mode<=wm8994_AP_to_speakers)
2331         {
2332                 wm8994_fnc_ptr+=wm8994_mode;
2333                 (*wm8994_fnc_ptr)() ;
2334         }
2335         else if(wm8994_mode>wm8994_BT_PCMbaseband_and_record)
2336         {
2337                 printk("%s--%d--: Wm8994 resume with null mode\n",__FUNCTION__,__LINE__);
2338         }
2339         else
2340         {
2341                 wm8994_fnc_ptr+=wm8994_mode;
2342                 (*wm8994_fnc_ptr)() ;
2343                 printk("%s--%d--: Wm8994 resume with error mode\n",__FUNCTION__,__LINE__);
2344         }
2345
2346         return 0;
2347 }
2348
2349 static struct snd_soc_codec *wm8994_codec;
2350
2351 static int wm8994_probe(struct platform_device *pdev)
2352 {
2353         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2354         struct snd_soc_codec *codec;
2355         int ret = 0;
2356
2357         if (wm8994_codec == NULL) {
2358                 dev_err(&pdev->dev, "Codec device not registered\n");
2359                 return -ENODEV;
2360         }
2361
2362         socdev->card->codec = wm8994_codec;
2363         codec = wm8994_codec;
2364
2365         /* register pcms */
2366         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2367         if (ret < 0) {
2368                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
2369                 goto pcm_err;
2370         }
2371
2372         snd_soc_add_controls(codec, wm8994_snd_controls,
2373                                 ARRAY_SIZE(wm8994_snd_controls));
2374         snd_soc_dapm_new_controls(codec, wm8994_dapm_widgets,
2375                                   ARRAY_SIZE(wm8994_dapm_widgets));
2376         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
2377         snd_soc_dapm_new_widgets(codec);
2378
2379         ret = snd_soc_init_card(socdev);
2380         if (ret < 0) {
2381                 dev_err(codec->dev, "failed to register card: %d\n", ret);
2382                 goto card_err;
2383         }
2384
2385         return ret;
2386
2387 card_err:
2388         snd_soc_free_pcms(socdev);
2389         snd_soc_dapm_free(socdev);
2390 pcm_err:
2391         return ret;
2392 }
2393
2394 static int wm8994_remove(struct platform_device *pdev)
2395 {
2396         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2397
2398         snd_soc_free_pcms(socdev);
2399         snd_soc_dapm_free(socdev);
2400
2401         return 0;
2402 }
2403
2404 struct snd_soc_codec_device soc_codec_dev_wm8994 = {
2405         .probe =        wm8994_probe,
2406         .remove =       wm8994_remove,
2407         .suspend =      wm8994_suspend,
2408         .resume =       wm8994_resume,
2409 };
2410 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
2411
2412 static int wm8994_register(struct wm8994_priv *wm8994,
2413                            enum snd_soc_control_type control)
2414 {
2415         struct snd_soc_codec *codec = &wm8994->codec;
2416         int ret;
2417         u16 reg;
2418
2419         if (wm8994_codec) {
2420                 dev_err(codec->dev, "Another WM8994 is registered\n");
2421                 ret = -EINVAL;
2422                 goto err;
2423         }
2424
2425         mutex_init(&codec->mutex);
2426         INIT_LIST_HEAD(&codec->dapm_widgets);
2427         INIT_LIST_HEAD(&codec->dapm_paths);
2428
2429         codec->private_data = wm8994;
2430         codec->name = "WM8994";
2431         codec->owner = THIS_MODULE;
2432         codec->dai = &wm8994_dai;
2433         codec->num_dai = 1;
2434         codec->reg_cache_size = ARRAY_SIZE(wm8994->reg_cache);
2435         codec->reg_cache = &wm8994->reg_cache;
2436         codec->bias_level = SND_SOC_BIAS_OFF;
2437         codec->set_bias_level = wm8994_set_bias_level;
2438
2439         memcpy(codec->reg_cache, wm8994_reg,
2440                sizeof(wm8994_reg));
2441
2442         ret = snd_soc_codec_set_cache_io(codec, 7, 9, control);
2443         if (ret < 0) {
2444                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2445                 goto err;
2446         }
2447
2448         ret = 0;//wm8994_reset(); cjq
2449         if (ret < 0) {
2450                 dev_err(codec->dev, "Failed to issue reset\n");
2451                 goto err;
2452         }
2453                 /*disable speaker */
2454                 gpio_request(RK2818_PIN_PF7, "WM8994");
2455                 rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_GPIO1_A3B7);
2456                 gpio_direction_output(RK2818_PIN_PF7,GPIO_HIGH);
2457
2458
2459         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_STANDBY);
2460
2461         wm8994_dai.dev = codec->dev;
2462
2463         wm8994_codec = codec;
2464
2465         ret = snd_soc_register_codec(codec);
2466         if (ret != 0) {
2467                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2468                 goto err;
2469         }
2470
2471         ret = snd_soc_register_dai(&wm8994_dai);
2472         if (ret != 0) {
2473                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
2474                 snd_soc_unregister_codec(codec);
2475                 goto err_codec;
2476         }
2477         return 0;
2478
2479 err_codec:
2480         snd_soc_unregister_codec(codec);
2481 err:
2482         kfree(wm8994);
2483         return ret;
2484 }
2485
2486 static void wm8994_unregister(struct wm8994_priv *wm8994)
2487 {
2488         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_OFF);
2489         snd_soc_unregister_dai(&wm8994_dai);
2490         snd_soc_unregister_codec(&wm8994->codec);
2491         kfree(wm8994);
2492         wm8994_codec = NULL;
2493 }
2494
2495 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2496 static int wm8994_i2c_probe(struct i2c_client *i2c,
2497                             const struct i2c_device_id *id)
2498 {
2499         struct wm8994_priv *wm8994;
2500         struct snd_soc_codec *codec;
2501         wm8994_client=i2c;
2502         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2503         if (wm8994 == NULL)
2504                 return -ENOMEM;
2505
2506         codec = &wm8994->codec;
2507
2508         i2c_set_clientdata(i2c, wm8994);
2509         codec->control_data = i2c;
2510
2511         codec->dev = &i2c->dev;
2512
2513         return wm8994_register(wm8994, SND_SOC_I2C);
2514 }
2515
2516 static int wm8994_i2c_remove(struct i2c_client *client)
2517 {
2518         struct wm8994_priv *wm8994 = i2c_get_clientdata(client);
2519         wm8994_unregister(wm8994);
2520         return 0;
2521 }
2522
2523 #ifdef CONFIG_PM
2524 static int wm8994_i2c_suspend(struct i2c_client *client, pm_message_t msg)
2525 {
2526         return snd_soc_suspend_device(&client->dev);
2527 }
2528
2529 static int wm8994_i2c_resume(struct i2c_client *client)
2530 {
2531         return snd_soc_resume_device(&client->dev);
2532 }
2533 #else
2534 #define wm8994_i2c_suspend NULL
2535 #define wm8994_i2c_resume NULL
2536 #endif
2537
2538 static const struct i2c_device_id wm8994_i2c_id[] = {
2539         { "wm8994", 0 },
2540         { }
2541 };
2542 MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
2543
2544 static struct i2c_driver wm8994_i2c_driver = {
2545         .driver = {
2546                 .name = "WM8994",
2547                 .owner = THIS_MODULE,
2548         },
2549         .probe = wm8994_i2c_probe,
2550         .remove = wm8994_i2c_remove,
2551         .suspend = wm8994_i2c_suspend,
2552         .resume = wm8994_i2c_resume,
2553         .id_table = wm8994_i2c_id,
2554 };
2555
2556 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate)
2557 {
2558         int ret;
2559         struct i2c_adapter *adap = client->adapter;
2560         struct i2c_msg msg;
2561         char tx_buf[4];
2562
2563         memcpy(tx_buf, reg, 2);
2564         memcpy(tx_buf+2, data, 2);
2565         msg.addr = client->addr;
2566         msg.buf = tx_buf;
2567         msg.len = 4;
2568         msg.flags = client->flags;
2569         msg.scl_rate = scl_rate;
2570         msg.read_type = I2C_NORMAL;
2571
2572         ret = i2c_transfer(adap, &msg, 1);
2573
2574         return ret;
2575 }
2576
2577 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate)
2578 {
2579         int ret;
2580         struct i2c_adapter *adap = client->adapter;
2581         struct i2c_msg msgs[2];
2582
2583         msgs[0].addr = client->addr;
2584         msgs[0].buf = (char *)reg;
2585         msgs[0].flags = client->flags;
2586         msgs[0].len = 2;
2587         msgs[0].scl_rate = scl_rate;
2588         msgs[0].read_type = I2C_NO_STOP;
2589
2590         msgs[1].addr = client->addr;
2591         msgs[1].buf = (char *)buf;
2592         msgs[1].flags = client->flags | I2C_M_RD;
2593         msgs[1].len = 2;
2594         msgs[1].scl_rate = scl_rate;
2595         msgs[1].read_type = I2C_NO_STOP;
2596
2597         ret = i2c_transfer(adap, msgs, 2);
2598
2599         return ret;
2600 }
2601
2602 #endif
2603
2604 #if defined(CONFIG_SPI_MASTER)
2605 static int __devinit wm8994_spi_probe(struct spi_device *spi)
2606 {
2607         struct wm8994_priv *wm8994;
2608         struct snd_soc_codec *codec;
2609
2610         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2611         if (wm8994 == NULL)
2612                 return -ENOMEM;
2613
2614         codec = &wm8994->codec;
2615         codec->control_data = spi;
2616         codec->dev = &spi->dev;
2617
2618         dev_set_drvdata(&spi->dev, wm8994);
2619
2620         return wm8994_register(wm8994, SND_SOC_SPI);
2621 }
2622
2623 static int __devexit wm8994_spi_remove(struct spi_device *spi)
2624 {
2625         struct wm8994_priv *wm8994 = dev_get_drvdata(&spi->dev);
2626
2627         wm8994_unregister(wm8994);
2628
2629         return 0;
2630 }
2631
2632 #ifdef CONFIG_PM
2633 static int wm8994_spi_suspend(struct spi_device *spi, pm_message_t msg)
2634 {
2635         return snd_soc_suspend_device(&spi->dev);
2636 }
2637
2638 static int wm8994_spi_resume(struct spi_device *spi)
2639 {
2640         return snd_soc_resume_device(&spi->dev);
2641 }
2642 #else
2643 #define wm8994_spi_suspend NULL
2644 #define wm8994_spi_resume NULL
2645 #endif
2646
2647 static struct spi_driver wm8994_spi_driver = {
2648         .driver = {
2649                 .name   = "wm8994",
2650                 .bus    = &spi_bus_type,
2651                 .owner  = THIS_MODULE,
2652         },
2653         .probe          = wm8994_spi_probe,
2654         .remove         = __devexit_p(wm8994_spi_remove),
2655         .suspend        = wm8994_spi_suspend,
2656         .resume         = wm8994_spi_resume,
2657 };
2658 #endif
2659
2660 static int __init wm8994_modinit(void)
2661 {
2662         int ret;
2663
2664 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2665         ret = i2c_add_driver(&wm8994_i2c_driver);
2666         if (ret != 0)
2667                 pr_err("WM8994: Unable to register I2C driver: %d\n", ret);
2668 #endif
2669 #if defined(CONFIG_SPI_MASTER)
2670         ret = spi_register_driver(&wm8994_spi_driver);
2671         if (ret != 0)
2672                 pr_err("WM8994: Unable to register SPI driver: %d\n", ret);
2673 #endif
2674         return ret;
2675 }
2676 module_init(wm8994_modinit);
2677
2678 static void __exit wm8994_exit(void)
2679 {
2680 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2681         i2c_del_driver(&wm8994_i2c_driver);
2682 #endif
2683 #if defined(CONFIG_SPI_MASTER)
2684         spi_unregister_driver(&wm8994_spi_driver);
2685 #endif
2686 }
2687 module_exit(wm8994_exit);
2688
2689
2690 MODULE_DESCRIPTION("ASoC WM8994 driver");
2691 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2692 MODULE_LICENSE("GPL");