sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c -- WM8994 ALSA SoC audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  * Copyright 2005 Openedhand Ltd.
   6  *
   7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/platform_device.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/tlv.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29
  30 #include <mach/iomux.h>
  31 #include <mach/gpio.h>
  32
  33 #include "wm8994.h"
  34 #include <linux/miscdevice.h>
  35 #include <linux/circ_buf.h>
  36 //#include <mach/spi_fpga.h>
  37
  38 #define WM8994_PROC
  39 #ifdef WM8994_PROC
  40 #include <linux/proc_fs.h>
  41 #include <linux/seq_file.h>
  42 #include <linux/vmalloc.h>
  43 #endif
  44
  45 #define CONFIG_SND_BB_NORMAL_INPUT
  46 #define CONFIG_SND_INSIDE_EARPIECE
  47 /* If digital BB is used,open this define. */
  48 //#define PCM_BB
  49
  50 /* Define what kind of digital BB is used. */
  51 #ifdef PCM_BB
  52 #define TD688_MODE
  53 //#define MU301_MODE
  54 //#define CHONGY_MODE
  55 //#define THINKWILL_M800_MODE
  56 #endif //PCM_BB
  57
  58 #if 1
  59 #define DBG(x...) printk(KERN_INFO x)
  60 #else
  61 #define DBG(x...) do { } while (0)
  62 #endif
  63
  64 #define wm8994_mic_VCC 0x0010
  65 #define WM8994_DELAY 50
  66
  67 struct i2c_client *wm8994_client;
  68 bool first_incall = false, isWM8994SetChannel = true, isSetChannelErr = false;
  69 struct workqueue_struct *wm8994_workqueue;
  70 struct work_struct wm8994_work;
  71 struct timer_list wm8994_timer;
  72 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate);
  73 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate);
  74 void wm8994_set_volume(unsigned char wm8994_mode,unsigned char volume,unsigned char max_volume);
  75 void wm8994_set_channel_vol(void);
  76 //extern bool isHSKey_MIC(void);
  77
  78 enum wm8994_codec_mode
  79 {
  80   wm8994_AP_to_headset,
  81   wm8994_AP_to_speakers,
  82   wm8994_AP_to_speakers_and_headset,
  83   wm8994_recorder_and_AP_to_headset,
  84   wm8994_recorder_and_AP_to_speakers,
  85   wm8994_FM_to_headset,
  86   wm8994_FM_to_headset_and_record,
  87   wm8994_FM_to_speakers,
  88   wm8994_FM_to_speakers_and_record,
  89   wm8994_handsetMIC_to_baseband_to_headset,
  90   wm8994_mainMIC_to_baseband_to_headset,
  91   wm8994_handsetMIC_to_baseband_to_headset_and_record,
  92   wm8994_mainMIC_to_baseband_to_earpiece,
  93   wm8994_mainMIC_to_baseband_to_earpiece_and_record,
  94   wm8994_mainMIC_to_baseband_to_speakers,
  95   wm8994_mainMIC_to_baseband_to_speakers_and_record,
  96   wm8994_BT_baseband,
  97   wm8994_BT_baseband_and_record,
  98   null
  99 };
 100
 101 /* wm8994_current_mode:save current wm8994 mode */
 102 unsigned char wm8994_current_mode=null;
 103
 104 enum stream_type_wm8994
 105 {
 106         VOICE_CALL      =0,
 107         BLUETOOTH_SCO   =6,
 108 };
 109
 110 /* For voice device route set, add by phc  */
 111 enum VoiceDeviceSwitch
 112 {
 113         SPEAKER_INCALL,
 114         SPEAKER_NORMAL,
 115
 116         HEADSET_INCALL,
 117         HEADSET_NORMAL,
 118
 119         EARPIECE_INCALL,
 120         EARPIECE_NORMAL,
 121
 122         BLUETOOTH_SCO_INCALL,
 123         BLUETOOTH_SCO_NORMAL,
 124
 125         BLUETOOTH_A2DP_INCALL,
 126         BLUETOOTH_A2DP_NORMAL,
 127
 128         MIC_CAPTURE,
 129
 130         EARPIECE_RINGTONE,
 131         SPEAKER_RINGTONE,
 132         HEADSET_RINGTONE,
 133
 134         ALL_OPEN,
 135         ALL_CLOSED
 136 };
 137
 138 #ifdef WM8994_PROC
 139 char wm8994_current_route = SPEAKER_NORMAL;
 140 char debug_write_read = 0;
 141 #endif
 142
 143 #define WM_EN_PIN RK29_PIN5_PA1
 144 #define call_maxvol 5
 145 #define BT_call_maxvol 15
 146
 147 /* call_vol:  save all kinds of system volume value. */
 148 unsigned char call_vol = 5, BT_call_vol = 15;
 149 int vol;
 150 unsigned short headset_vol_table[6]     ={0x012D,0x0133,0x0136,0x0139,0x013B,0x013D};
 151 unsigned short speakers_vol_table[6]    ={0x012D,0x0133,0x0136,0x0139,0x013B,0x013D};
 152 #ifdef CONFIG_RAHO_CTA
 153 unsigned short earpiece_vol_table[6]    ={0x0127,0x012D,0x0130,0x0135,0x0137,0x0135};//for cta
 154 #else
 155 unsigned short earpiece_vol_table[6]    ={0x0127,0x012D,0x0130,0x0135,0x0139,0x013D};//normal
 156 #endif
 157 unsigned short BT_vol_table[16]         ={0x01DB,0x01DC,0x01DD,0x01DE,0x01DF,0x01E0,
 158                                         0x01E1,0x01E2,0x01E3,0x01E4,0x01E5,0x01E6,
 159                                         0x01E7,0x01E8,0x01E9,0x01EA};
 160
 161 int speaker_incall_vol = 0,//CONFIG_WM8994_SPEAKER_INCALL_VOL
 162 speaker_incall_mic_vol = -9,//CONFIG_WM8994_SPEAKER_INCALL_MIC_VOL
 163 speaker_normal_vol = 6,//CONFIG_WM8994_SPEAKER_NORMAL_VOL,
 164 earpiece_incall_vol = 0,//CONFIG_WM8994_EARPIECE_INCALL_VOL
 165 headset_incall_vol = 6,//CONFIG_WM8994_HEADSET_INCALL_VOL
 166 headset_incall_mic_vol = -6,//CONFIG_WM8994_HEADSET_INCALL_MIC_VOL
 167 headset_normal_vol = 6,//CONFIG_WM8994_HEADSET_NORMAL_VOL,
 168 BT_incall_vol = 0,//CONFIG_WM8994_BT_INCALL_VOL,
 169 BT_incall_mic_vol = 0,//CONFIG_WM8994_BT_INCALL_MIC_VOL,
 170 recorder_vol = 50,//CONFIG_WM8994_RECORDER_VOL,
 171 bank_vol[6] = {0,0,-3,3,-6,3};
 172
 173 /*
 174  * wm8994 register cache
 175  * We can't read the WM8994 register space when we
 176  * are using 2 wire for device control, so we cache them instead.
 177  */
 178 static const u16 wm8994_reg[] = {
 179         0x0097, 0x0097, 0x0079, 0x0079,  /*  0 */
 180         0x0000, 0x0008, 0x0000, 0x000a,  /*  4 */
 181         0x0000, 0x0000, 0x00ff, 0x00ff,  /*  8 */
 182         0x000f, 0x000f, 0x0000, 0x0000,  /* 12 */
 183         0x0000, 0x007b, 0x0000, 0x0032,  /* 16 */
 184         0x0000, 0x00c3, 0x00c3, 0x00c0,  /* 20 */
 185         0x0000, 0x0000, 0x0000, 0x0000,  /* 24 */
 186         0x0000, 0x0000, 0x0000, 0x0000,  /* 28 */
 187         0x0000, 0x0000, 0x0050, 0x0050,  /* 32 */
 188         0x0050, 0x0050, 0x0050, 0x0050,  /* 36 */
 189         0x0079, 0x0079, 0x0079,          /* 40 */
 190 };
 191
 192 /* codec private data */
 193 struct wm8994_priv {
 194         unsigned int sysclk;
 195         struct snd_soc_codec codec;
 196         struct snd_pcm_hw_constraint_list *sysclk_constraints;
 197         u16 reg_cache[WM8994_NUM_REG];
 198 };
 199
 200 bool wm8994_set_status(void)
 201 {
 202         return isWM8994SetChannel;
 203 }
 204
 205 EXPORT_SYMBOL_GPL(wm8994_set_status);
 206
 207 static int wm8994_read(unsigned short reg,unsigned short *value)
 208 {
 209         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values;
 210         char i = 2;
 211
 212         if(isSetChannelErr)return -EIO;
 213
 214         while(i > 0)
 215         {
 216                 i--;
 217                 if (reg_recv_data(wm8994_client,&regs,&values,400000) > 0)
 218                 {
 219                         *value=((values>>8)& 0x00FF)|((values<<8)&0xFF00);
 220                 #ifdef WM8994_PROC
 221                         if(debug_write_read != 0)
 222                                 DBG("%s:0x%04x = 0x%04x",__FUNCTION__,reg,*value);
 223                 #endif
 224                         return 0;
 225                 }
 226         }
 227         isSetChannelErr = true;
 228
 229         printk("%s---line->%d:Codec read error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,*value);
 230
 231         return -EIO;
 232 }
 233
 234 static int wm8994_write(unsigned short reg,unsigned short value)
 235 {
 236         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values=((value>>8)&0x00FF)|((value<<8)&0xFF00);
 237         char i = 2;
 238
 239         if(isSetChannelErr)return -EIO;
 240 #ifdef WM8994_PROC
 241         if(debug_write_read != 0)
 242                 DBG("%s:0x%04x = 0x%04x\n",__FUNCTION__,reg,value);
 243 #endif
 244         while(i > 0)
 245         {
 246                 i--;
 247                 if (reg_send_data(wm8994_client,&regs,&values,400000) > 0)
 248                 {
 249                         if (reg == 0x302)
 250                         {
 251                                 wm8994_read(0x406, &values);
 252                                 wm8994_write(0x406, values);
 253                                 wm8994_read(reg, &values);
 254
 255                                 DBG("read 0x302 = 0x%x write 0x302 = 0x%x \n", values, value);
 256
 257                                 if (values != value)
 258                                         isSetChannelErr = true;
 259                         }
 260                         return 0;
 261                 }
 262         }
 263         isSetChannelErr = true;
 264
 265         printk("%s---line->%d:Codec write error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,value);
 266
 267         return -EIO;
 268 }
 269
 270 void wm8994_work_handler(struct work_struct *work)
 271 {
 272         DBG("Enter::wm8994 work handler\n");
 273         if(wm8994_current_mode==wm8994_BT_baseband){
 274                 wm8994_write(0x602, 0x0001);
 275         }else{
 276                 wm8994_write(0x601, 0x0001);
 277                 wm8994_write(0x602, 0x0001);
 278         }
 279 }
 280
 281 static void wm8994_codec_timer(unsigned long data)
 282 {
 283         DBG("Enter::wm8994 timer\n");
 284         if(first_incall){
 285                 DBG("first_incall set 0x601 0x602\n");
 286                 queue_work(wm8994_workqueue, &wm8994_work);
 287                 first_incall = false;
 288         }
 289 }
 290
 291 static void wm8994_codec_first_incall(void)
 292 {
 293         if(wm8994_current_mode==wm8994_AP_to_speakers_and_headset||
 294         wm8994_current_mode==wm8994_recorder_and_AP_to_headset||
 295         wm8994_current_mode==wm8994_recorder_and_AP_to_speakers){
 296                 first_incall = true;
 297                 wm8994_timer.expires  = jiffies + msecs_to_jiffies(1500);//1s
 298                 add_timer(&wm8994_timer);
 299         }
 300 }
 301
 302 static void wm8994_set_all_mute(void)
 303 {
 304         int i;
 305
 306         if(call_vol < 0)
 307                 return;
 308
 309         for (i = call_vol; i >= 0; i--)
 310                 wm8994_set_volume(null,i,call_maxvol);
 311
 312 }
 313
 314 static void wm8994_set_level_volume(void)
 315 {
 316         int i;
 317
 318         for (i = 0; i <= call_vol; i++)
 319                 wm8994_set_volume(wm8994_current_mode,i,call_maxvol);
 320
 321 }
 322
 323 #define wm8994_reset()  wm8994_set_all_mute();\
 324                                                 wm8994_write(WM8994_RESET, 0)
 325
 326
 327 void AP_to_headset(void)
 328 {
 329         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 330
 331         if(wm8994_current_mode==wm8994_AP_to_headset)return;
 332         wm8994_current_mode=wm8994_AP_to_headset;
 333         wm8994_reset();
 334         msleep(WM8994_DELAY);
 335
 336         wm8994_write(0x700, 0xA101);
 337         wm8994_write(0x01,  0x0023);
 338         wm8994_write(0x200, 0x0000);
 339         mdelay(WM8994_DELAY);
 340
 341         wm8994_write(0x220, 0x0000);
 342         wm8994_write(0x221, 0x0700);
 343         wm8994_write(0x222, 0x3126);
 344         wm8994_write(0x223, 0x0100);
 345
 346         wm8994_write(0x220, 0x0004);
 347         msleep(10);
 348         wm8994_write(0x220, 0x0005);
 349         msleep(5);
 350
 351         wm8994_write(0x200, 0x0010);
 352         wm8994_write(0x208, 0x0008); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 353         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 354         wm8994_write(0x210, 0x0083); // SR=48KHz
 355 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 356         wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
 357         wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
 358         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 359         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 360         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 361         wm8994_write(0x300, 0x4010); // i2s 16 bits
 362 #endif
 363         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
 364
 365         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1/ q
 366         wm8994_write(0x05,  0x0303);
 367         wm8994_write(0x2D,  0x0100);
 368         wm8994_write(0x2E,  0x0100);
 369
 370         wm8994_write(0x4C,  0x9F25);
 371         msleep(5);
 372         wm8994_write(0x01,  0x0323);
 373         msleep(50);
 374         wm8994_write(0x60,  0x0022);
 375         wm8994_write(0x60,  0x00FF);
 376
 377         wm8994_write(0x420, 0x0000);
 378         wm8994_write(0x601, 0x0001);
 379         wm8994_write(0x602, 0x0001);
 380
 381         wm8994_write(0x610, 0x01A0);  //DAC1 Left Volume bit0~7
 382         wm8994_write(0x611, 0x01A0);  //DAC1 Right Volume bit0~7
 383         wm8994_write(0x03,  0x3030);
 384         wm8994_write(0x22,  0x0000);
 385         wm8994_write(0x23,  0x0100);
 386         wm8994_write(0x36,  0x0003);
 387         wm8994_write(0x1C,  0x017F);  //HPOUT1L Volume
 388         wm8994_write(0x1D,  0x017F);  //HPOUT1R Volume
 389 }
 390
 391 void AP_to_speakers(void)
 392 {
 393         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 394
 395         if(wm8994_current_mode==wm8994_AP_to_speakers)return;
 396         wm8994_current_mode=wm8994_AP_to_speakers;
 397 //      wm8994_reset();
 398         wm8994_write(0,0);
 399         msleep(WM8994_DELAY);
 400
 401 //      wm8994_write(0x700, 0xA101);
 402 //      wm8994_write(0x39,  0x006C);
 403         wm8994_write(0x01,  0x0023);
 404         wm8994_write(0x200, 0x0000);
 405         mdelay(WM8994_DELAY);
 406
 407         wm8994_write(0x220, 0x0000);
 408         wm8994_write(0x221, 0x0700);
 409         wm8994_write(0x222, 0x3126);
 410         wm8994_write(0x223, 0x0100);
 411
 412         wm8994_write(0x220, 0x0004);
 413         msleep(10);
 414         wm8994_write(0x220, 0x0005);
 415         msleep(5);
 416
 417         wm8994_write(0x200, 0x0010);
 418         wm8994_write(0x208, 0x0008); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 419         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 420         wm8994_write(0x210, 0x0083); // SR=48KHz
 421 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 422         wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
 423         wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
 424         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 425         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 426         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 427         wm8994_write(0x300, 0xC010); // i2s 16 bits
 428 #endif
 429         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
 430
 431         wm8994_write(0x01,  0x3023);
 432         wm8994_write(0x03,  0x0330);
 433         wm8994_write(0x05,  0x0303);
 434         wm8994_write(0x22,  0x0000);
 435         wm8994_write(0x23,  0x0100);
 436         wm8994_write(0x2D,  0x0001);
 437         wm8994_write(0x2E,  0x0000);
 438         wm8994_write(0x36,  0x000C);
 439         wm8994_write(0x4C,  0x9F25);
 440         wm8994_write(0x60,  0x00EE);
 441         wm8994_write(0x420, 0x0000);
 442
 443         wm8994_write(0x601, 0x0001);
 444         wm8994_write(0x602, 0x0001);
 445
 446         wm8994_write(0x610, 0x01c0);  //DAC1 Left Volume bit0~7
 447         wm8994_write(0x611, 0x01c0);  //DAC1 Right Volume bit0~7
 448
 449         wm8994_write(0x26,  0x017F);  //Speaker Left Output Volume
 450         wm8994_write(0x27,  0x017F);  //Speaker Right Output Volume
 451 }
 452
 453 void AP_to_speakers_and_headset(void)
 454 {
 455         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 456         if(wm8994_current_mode==wm8994_AP_to_speakers_and_headset)return;
 457         wm8994_current_mode=wm8994_AP_to_speakers_and_headset;
 458         wm8994_reset();
 459         mdelay(WM8994_DELAY);
 460
 461         wm8994_write(0x700, 0xA101);
 462         wm8994_write(0x39,  0x006C);
 463         wm8994_write(0x01,  0x0023);
 464         wm8994_write(0x200, 0x0000);
 465         mdelay(WM8994_DELAY);
 466
 467         wm8994_write(0x220, 0x0000);
 468         wm8994_write(0x221, 0x0700);
 469         wm8994_write(0x222, 0x3126);
 470         wm8994_write(0x223, 0x0100);
 471
 472         wm8994_write(0x220, 0x0004);
 473         msleep(10);
 474         wm8994_write(0x220, 0x0005);
 475         msleep(5);
 476
 477         wm8994_write(0x200, 0x0010);
 478         wm8994_write(0x208, 0x0008); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 479         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 480         wm8994_write(0x210, 0x0083); // SR=48KHz
 481 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 482         wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
 483         wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
 484         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 485         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 486         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 487         wm8994_write(0x300, 0xC010); // i2s 16 bits
 488 #endif
 489         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
 490
 491         wm8994_write(0x610, 0x0100);  //DAC1 Left Volume bit0~7
 492         wm8994_write(0x611, 0x0100);  //DAC1 Right Volume bit0~7
 493
 494 //      wm8994_write(0x24,  0x0011);
 495         wm8994_set_channel_vol();
 496         //wm8994_write(0x25,  0x003F);
 497
 498         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 499         wm8994_write(0x05,  0x0303);
 500         wm8994_write(0x2D,  0x0100);
 501         wm8994_write(0x2E,  0x0100);
 502
 503         wm8994_write(0x4C,  0x9F25);
 504         mdelay(5);
 505         wm8994_write(0x01,  0x3303);
 506         mdelay(50);
 507         wm8994_write(0x60,  0x0022);
 508         wm8994_write(0x60,  0x00EE);
 509
 510         wm8994_write(0x420, 0x0000);
 511
 512         wm8994_write(0x601, 0x0001);
 513         wm8994_write(0x602, 0x0001);
 514
 515         wm8994_write(0x03,  0x3330);
 516         wm8994_write(0x22,  0x0000);
 517         wm8994_write(0x23,  0x0100);
 518         wm8994_write(0x36,  0x0003);
 519         wm8994_write(0x01,  0x3323);
 520
 521         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
 522         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
 523 }
 524
 525 void recorder_and_AP_to_headset(void)
 526 {
 527         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 528
 529         if(wm8994_current_mode==wm8994_recorder_and_AP_to_headset)return;
 530         wm8994_current_mode=wm8994_recorder_and_AP_to_headset;
 531         wm8994_reset();
 532         msleep(WM8994_DELAY);
 533
 534         wm8994_write(0x700, 0xA101);
 535         wm8994_write(0x01,  0x0023);
 536         wm8994_write(0x200, 0x0000);
 537         mdelay(WM8994_DELAY);
 538
 539         wm8994_write(0x220, 0x0000);
 540         wm8994_write(0x221, 0x0700);
 541         wm8994_write(0x222, 0x3126);
 542         wm8994_write(0x223, 0x0100);
 543
 544         wm8994_write(0x220, 0x0004);
 545         msleep(10);
 546         wm8994_write(0x220, 0x0005);
 547         msleep(5);
 548
 549         wm8994_write(0x200, 0x0010);
 550         wm8994_write(0x208, 0x0008); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 551         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 552         wm8994_write(0x210, 0x0083); // SR=48KHz
 553 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 554         wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
 555         wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
 556         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 557         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 558         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 559         wm8994_write(0x300, 0xC050); // i2s 16 bits
 560 #endif
 561         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
 562
 563         wm8994_write(0x610, 0x0100); // DAC1_VU=1, DAC1L_VOL=1100_0000
 564         wm8994_write(0x611, 0x0100); // DAC1_VU=1, DAC1R_VOL=1100_0000
 565
 566         wm8994_set_channel_vol();
 567         //wm8994_write(0x25,  0x003F);
 568         wm8994_write(0x28,  0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
 569         wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
 570         wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
 571         wm8994_write(0x620, 0x0000);
 572
 573         wm8994_write(0x402, 0x01FF); // AIF1ADC1L_VOL [7:0]
 574         wm8994_write(0x403, 0x01FF); // AIF1ADC1R_VOL [7:0]
 575         wm8994_write(0x440, 0x01BF);
 576         wm8994_write(0x450, 0x01BF);
 577         wm8994_write(0x2D,  0x0100); // DAC1L_TO_HPOUT1L=1
 578         wm8994_write(0x2E,  0x0100); // DAC1R_TO_HPOUT1R=1
 579
 580         wm8994_write(0x4C,  0x9F25);
 581         mdelay(5);
 582         wm8994_write(0x01,  0x3303);
 583         mdelay(50);
 584         wm8994_write(0x60,  0x0022);
 585         wm8994_write(0x60,  0x00FF);
 586
 587         wm8994_write(0x02,  0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
 588         wm8994_write(0x03,  0x3030);
 589         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 590         wm8994_write(0x05,  0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
 591         wm8994_write(0x420, 0x0000);
 592
 593         wm8994_write(0x01,  0x0333);
 594
 595         wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
 596         wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
 597         wm8994_write(0x610, 0x01A0); // DAC1_VU=1, DAC1L_VOL=1100_0000
 598         wm8994_write(0x611, 0x01A0); // DAC1_VU=1, DAC1R_VOL=1100_0000
 599 }
 600
 601 void recorder_and_AP_to_speakers(void)
 602 {
 603         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 604
 605         if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers)return;
 606         wm8994_current_mode=wm8994_recorder_and_AP_to_speakers;
 607         wm8994_reset();
 608         msleep(WM8994_DELAY);
 609
 610         wm8994_write(0x700, 0xA101);
 611         wm8994_write(0x39,  0x006C);
 612         wm8994_write(0x01,  0x0023);
 613         wm8994_write(0x200, 0x0000);
 614         mdelay(WM8994_DELAY);
 615
 616         wm8994_write(0x220, 0x0000);
 617         wm8994_write(0x221, 0x0700);
 618         wm8994_write(0x222, 0x3126);
 619         wm8994_write(0x223, 0x0100);
 620
 621         wm8994_write(0x220, 0x0004);
 622         msleep(10);
 623         wm8994_write(0x220, 0x0005);
 624         msleep(5);
 625
 626         wm8994_write(0x200, 0x0010);
 627         wm8994_write(0x208, 0x0008); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 628         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 629         wm8994_write(0x210, 0x0083); // SR=48KHz
 630 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 631         wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
 632         wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
 633         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 634         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 635         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 636         wm8994_write(0x300, 0xC050); // i2s 16 bits
 637 #endif
 638         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
 639
 640         wm8994_write(0x610, 0x0100); // DAC1_VU=1, DAC1L_VOL=1100_0000
 641         wm8994_write(0x611, 0x0100); // DAC1_VU=1, DAC1R_VOL=1100_0000
 642         wm8994_set_channel_vol();
 643 //      wm8994_write(0x24,  0x001f);
 644         //wm8994_write(0x25,  0x003F);
 645
 646         wm8994_write(0x02,  0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
 647         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 648         wm8994_write(0x28,  0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
 649
 650         wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
 651         wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
 652         wm8994_write(0x620, 0x0000);
 653
 654         wm8994_write(0x402, 0x01FF); // AIF1ADC1L_VOL [7:0]
 655         wm8994_write(0x403, 0x01FF); // AIF1ADC1R_VOL [7:0]
 656
 657         wm8994_write(0x03,  0x0330); // SPKRVOL_ENA=1, SPKLVOL_ENA=1, MIXOUTL_ENA=1, MIXOUTR_ENA=1
 658         wm8994_write(0x05,  0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
 659         wm8994_write(0x22,  0x0000);
 660         wm8994_write(0x23,  0x0100); // SPKOUT_CLASSAB=1
 661
 662         wm8994_write(0x2D,  0x0001); // DAC1L_TO_MIXOUTL=1
 663         wm8994_write(0x2E,  0x0001); // DAC1R_TO_MIXOUTR=1
 664         wm8994_write(0x4C,  0x9F25);
 665         wm8994_write(0x60,  0x00EE);
 666         wm8994_write(0x36,  0x000C); // MIXOUTL_TO_SPKMIXL=1, MIXOUTR_TO_SPKMIXR=1
 667         wm8994_write(0x440, 0x01BF);
 668         wm8994_write(0x450, 0x01BF);
 669         wm8994_write(0x610, 0x01C0); // DAC1_VU=1, DAC1L_VOL=1100_0000
 670         wm8994_write(0x611, 0x01C0); // DAC1_VU=1, DAC1R_VOL=1100_0000
 671         wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
 672         wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
 673         wm8994_write(0x420, 0x0000);
 674         wm8994_write(0x01,  0x3003);
 675         msleep(20);
 676         wm8994_write(0x01,  0x3033);
 677 }
 678
 679 void FM_to_headset(void)
 680 {
 681         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 682
 683         if(wm8994_current_mode == wm8994_FM_to_headset)return;
 684         wm8994_current_mode = wm8994_FM_to_headset;
 685         wm8994_reset();
 686         msleep(WM8994_DELAY);
 687
 688         wm8994_write(0x01,  0x0303);
 689         wm8994_write(0x02,  0x03A0);
 690         wm8994_write(0x03,  0x0030);
 691         wm8994_write(0x19,  0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 692         wm8994_write(0x1B,  0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 693
 694         wm8994_write(0x28,  0x0044);
 695         wm8994_write(0x29,  0x0100);
 696         wm8994_write(0x2A,  0x0100);
 697         wm8994_write(0x2D,  0x0040);
 698         wm8994_write(0x2E,  0x0040);
 699         wm8994_write(0x4C,  0x9F25);
 700         wm8994_write(0x60,  0x00EE);
 701         wm8994_write(0x220, 0x0003);
 702         wm8994_write(0x221, 0x0700);
 703         wm8994_write(0x224, 0x0CC0);
 704         wm8994_write(0x200, 0x0011);
 705         wm8994_write(0x1C,  0x01F9);  //LEFT OUTPUT VOLUME
 706         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 707 }
 708
 709 void FM_to_headset_and_record(void)
 710 {
 711         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 712
 713         if(wm8994_current_mode == wm8994_FM_to_headset_and_record)return;
 714         wm8994_current_mode = wm8994_FM_to_headset_and_record;
 715         wm8994_reset();
 716         msleep(WM8994_DELAY);
 717
 718         wm8994_write(0x01,   0x0003);
 719         msleep(WM8994_DELAY);
 720         wm8994_write(0x221,  0x1900);  //8~13BIT div
 721
 722 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 723         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 724         wm8994_write(0x303,  0x0040);  // master  0x0050 lrck 7.94kHz bclk 510KHz
 725 #endif
 726
 727         wm8994_write(0x220,  0x0004);
 728         msleep(WM8994_DELAY);
 729         wm8994_write(0x220,  0x0005);
 730
 731         wm8994_write(0x01,   0x0323);
 732         wm8994_write(0x02,   0x03A0);
 733         wm8994_write(0x03,   0x0030);
 734         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 735         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 736
 737         wm8994_write(0x28,   0x0044);
 738         wm8994_write(0x29,   0x0100);
 739         wm8994_write(0x2A,   0x0100);
 740         wm8994_write(0x2D,   0x0040);
 741         wm8994_write(0x2E,   0x0040);
 742         wm8994_write(0x4C,   0x9F25);
 743         wm8994_write(0x60,   0x00EE);
 744         wm8994_write(0x200,  0x0011);
 745         wm8994_write(0x1C,   0x01F9);  //LEFT OUTPUT VOLUME
 746         wm8994_write(0x1D,   0x01F9);  //RIGHT OUTPUT VOLUME
 747         wm8994_write(0x04,   0x0303);
 748         wm8994_write(0x208,  0x000A);
 749         wm8994_write(0x300,  0x4050);
 750         wm8994_write(0x606,  0x0002);
 751         wm8994_write(0x607,  0x0002);
 752         wm8994_write(0x620,  0x0000);
 753 }
 754
 755 void FM_to_speakers(void)
 756 {
 757         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 758
 759         if(wm8994_current_mode == wm8994_FM_to_speakers)return;
 760         wm8994_current_mode = wm8994_FM_to_speakers;
 761         wm8994_reset();
 762         msleep(WM8994_DELAY);
 763
 764         wm8994_write(0x01,   0x3003);
 765         wm8994_write(0x02,   0x03A0);
 766         wm8994_write(0x03,   0x0330);
 767         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 768         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 769
 770         wm8994_write(0x22,   0x0000);
 771         wm8994_write(0x23,   0x0000);
 772         wm8994_write(0x36,   0x000C);
 773
 774         wm8994_write(0x28,   0x0044);
 775         wm8994_write(0x29,   0x0100);
 776         wm8994_write(0x2A,   0x0100);
 777         wm8994_write(0x2D,   0x0040);
 778         wm8994_write(0x2E,   0x0040);
 779
 780         wm8994_write(0x220,  0x0003);
 781         wm8994_write(0x221,  0x0700);
 782         wm8994_write(0x224,  0x0CC0);
 783
 784         wm8994_write(0x200,  0x0011);
 785         wm8994_write(0x20,   0x01F9);
 786         wm8994_write(0x21,   0x01F9);
 787 }
 788
 789 void FM_to_speakers_and_record(void)
 790 {
 791         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 792
 793         if(wm8994_current_mode == wm8994_FM_to_speakers_and_record)return;
 794         wm8994_current_mode = wm8994_FM_to_speakers_and_record;
 795         wm8994_reset();
 796         msleep(WM8994_DELAY);
 797
 798         wm8994_write(0x01,   0x0003);
 799         msleep(WM8994_DELAY);
 800
 801 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 802         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 803         wm8994_write(0x303,  0x0090);  //
 804 #endif
 805
 806         wm8994_write(0x220,  0x0006);
 807         msleep(WM8994_DELAY);
 808
 809         wm8994_write(0x01,   0x3023);
 810         wm8994_write(0x02,   0x03A0);
 811         wm8994_write(0x03,   0x0330);
 812         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 813         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 814
 815         wm8994_write(0x22,   0x0000);
 816         wm8994_write(0x23,   0x0000);
 817         wm8994_write(0x36,   0x000C);
 818
 819         wm8994_write(0x28,   0x0044);
 820         wm8994_write(0x29,   0x0100);
 821         wm8994_write(0x2A,   0x0100);
 822         wm8994_write(0x2D,   0x0040);
 823         wm8994_write(0x2E,   0x0040);
 824
 825         wm8994_write(0x220,  0x0003);
 826         wm8994_write(0x221,  0x0700);
 827         wm8994_write(0x224,  0x0CC0);
 828
 829         wm8994_write(0x200,  0x0011);
 830         wm8994_write(0x20,   0x01F9);
 831         wm8994_write(0x21,   0x01F9);
 832         wm8994_write(0x04,   0x0303);
 833         wm8994_write(0x208,  0x000A);
 834         wm8994_write(0x300,  0x4050);
 835         wm8994_write(0x606,  0x0002);
 836         wm8994_write(0x607,  0x0002);
 837         wm8994_write(0x620,  0x0000);
 838 }
 839 #ifndef PCM_BB
 840 void handsetMIC_to_baseband_to_headset(void)
 841 {
 842         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 843
 844         if(wm8994_current_mode == wm8994_handsetMIC_to_baseband_to_headset)return;
 845
 846         wm8994_codec_first_incall();
 847         wm8994_current_mode = wm8994_handsetMIC_to_baseband_to_headset;
 848         wm8994_reset();
 849         msleep(WM8994_DELAY);
 850
 851         wm8994_set_volume(wm8994_current_mode,0,call_maxvol);
 852
 853         wm8994_write(0x700, 0xA101);
 854         wm8994_write(0x01,  0x0023);
 855         wm8994_write(0x200, 0x0000);
 856         mdelay(WM8994_DELAY);
 857
 858         wm8994_write(0x220, 0x0000);
 859         wm8994_write(0x221, 0x0700);
 860         wm8994_write(0x222, 0x3126);
 861         wm8994_write(0x223, 0x0100);
 862
 863         wm8994_write(0x220, 0x0004);
 864         msleep(10);
 865         wm8994_write(0x220, 0x0005);
 866         msleep(5);
 867
 868         wm8994_write(0x200, 0x0010);
 869         wm8994_write(0x208, 0x0008); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 870         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 871         wm8994_write(0x210, 0x0083); // SR=48KHz
 872 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 873         wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
 874         wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
 875         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 876         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 877         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 878         wm8994_write(0x300, 0xC010); // i2s 16 bits
 879 #endif
 880         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
 881
 882         wm8994_write(0x01,  0x0023);
 883         mdelay(WM8994_DELAY);
 884         wm8994_write(0xFF,  0x0000);
 885         mdelay(5);
 886         wm8994_write(0x4C,  0x9F25);
 887         mdelay(5);
 888         wm8994_write(0x01,  0x0323);
 889         wm8994_write(0x60,  0x0022);
 890         wm8994_write(0x60,  0x00EE);
 891         mdelay(5);
 892         wm8994_write(0x54,  0x0033);
 893
 894         wm8994_write(0x610, 0x0100);  //DAC1 Left Volume bit0~7
 895         wm8994_write(0x611, 0x0100);  //DAC1 Right Volume bit0~7
 896
 897         wm8994_set_channel_vol();
 898         msleep(50);
 899         wm8994_write(0x22,  0x0000);
 900         wm8994_write(0x23,  0x0100);
 901
 902         wm8994_write(0x02,  0x6240);
 903         wm8994_write(0x28,  0x0030);  //IN1LN_TO_IN1L IN1LP_TO_IN1L
 904 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
 905         wm8994_write(0x2D,  0x0041);  //bit 1 MIXINL_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
 906         wm8994_write(0x2E,  0x0081);  //bit 1 MIXINL_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
 907 #endif
 908 #ifdef CONFIG_SND_BB_NORMAL_INPUT
 909         wm8994_write(0x2D,  0x0003);  //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
 910         wm8994_write(0x2E,  0x0003);  //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
 911 #endif
 912         wm8994_write(0x34,  0x0002);  //IN1L_TO_LINEOUT1P
 913         wm8994_write(0x36,  0x0003);
 914
 915         wm8994_write(0x4C,  0x9F25);
 916         mdelay(5);
 917         wm8994_write(0x01,  0x0303);
 918         mdelay(50);
 919         wm8994_write(0x60,  0x0022);
 920         wm8994_write(0x60,  0x00EE);
 921
 922         wm8994_write(0x03,  0x3030);
 923         wm8994_write(0x04,  0x0300); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1
 924         wm8994_write(0x05,  0x0303);
 925         wm8994_write(0x420, 0x0000);
 926
 927         wm8994_write(0x01,  0x0323);
 928         if(!first_incall){
 929                 wm8994_write(0x601, 0x0001);
 930                 wm8994_write(0x602, 0x0001);
 931         }
 932         wm8994_write(0x610, 0x01A0);  //DAC1 Left Volume bit0~7
 933         wm8994_write(0x611, 0x01A0);  //DAC1 Right Volume bit0~7
 934
 935         wm8994_set_level_volume();
 936 }
 937
 938 void mainMIC_to_baseband_to_headset(void)
 939 {
 940         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 941
 942         if(wm8994_current_mode == wm8994_mainMIC_to_baseband_to_headset)return;
 943         wm8994_codec_first_incall();
 944         wm8994_current_mode = wm8994_mainMIC_to_baseband_to_headset;
 945         wm8994_reset();
 946         msleep(WM8994_DELAY);
 947
 948         wm8994_write(0x700, 0xA101);
 949         wm8994_write(0x01,  0x0023);
 950         wm8994_write(0x200, 0x0000);
 951         mdelay(WM8994_DELAY);
 952
 953         wm8994_write(0x220, 0x0000);
 954         wm8994_write(0x221, 0x0700);
 955         wm8994_write(0x222, 0x3126);
 956         wm8994_write(0x223, 0x0100);
 957
 958         wm8994_write(0x220, 0x0004);
 959         msleep(10);
 960         wm8994_write(0x220, 0x0005);
 961         msleep(5);
 962
 963         wm8994_write(0x200, 0x0010);
 964         wm8994_write(0x208, 0x0008); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 965         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 966         wm8994_write(0x210, 0x0083); // SR=48KHz
 967 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
 968         wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
 969         wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
 970         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 971         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 972         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 973         wm8994_write(0x300, 0xC010); // i2s 16 bits
 974 #endif
 975         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
 976
 977         wm8994_write(0x39,  0x006C);
 978         wm8994_write(0x01,  0x0023);
 979         mdelay(WM8994_DELAY);
 980         wm8994_write(0xFF,  0x0000);
 981         mdelay(5);
 982         wm8994_write(0x4C,  0x9F25);
 983         mdelay(5);
 984         wm8994_write(0x01,  0x0323);
 985         wm8994_write(0x60,  0x0022);
 986         wm8994_write(0x60,  0x00EE);
 987         mdelay(5);
 988         wm8994_write(0x54,  0x0033);
 989
 990         wm8994_write(0x610, 0x0100);  //DAC1 Left Volume bit0~7
 991         wm8994_write(0x611, 0x0100);  //DAC1 Right Volume bit0~7
 992
 993         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 994         wm8994_set_channel_vol();
 995         msleep(50);
 996         wm8994_write(0x22,  0x0000);
 997         wm8994_write(0x23,  0x0100);
 998
 999         wm8994_write(0x02,  0x6210);
1000         wm8994_write(0x28,  0x0003);  //IN1LN_TO_IN1L IN1LP_TO_IN1L
1001 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
1002         wm8994_write(0x2D,  0x0041);  //bit 1 MIXINL_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
1003         wm8994_write(0x2E,  0x0081);  //bit 1 MIXINL_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
1004 #endif
1005 #ifdef CONFIG_SND_BB_NORMAL_INPUT
1006         wm8994_write(0x2D,  0x0003);  //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
1007         wm8994_write(0x2E,  0x0003);  //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
1008 #endif
1009         wm8994_write(0x34,  0x0004);  //IN1L_TO_LINEOUT1P
1010         wm8994_write(0x36,  0x0003);
1011
1012         wm8994_write(0x4C,  0x9F25);
1013         mdelay(5);
1014         wm8994_write(0x01,  0x0303);
1015         mdelay(50);
1016         wm8994_write(0x60,  0x0022);
1017         wm8994_write(0x60,  0x00EE);
1018
1019         wm8994_write(0x03,  0x3030);
1020         wm8994_write(0x04,  0x0300); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1
1021         wm8994_write(0x05,  0x0303);
1022         wm8994_write(0x420, 0x0000);
1023
1024         wm8994_write(0x01,  0x0333);
1025         if(!first_incall){
1026                 wm8994_write(0x601, 0x0001);
1027                 wm8994_write(0x602, 0x0001);
1028         }
1029         wm8994_write(0x610, 0x01A0);  //DAC1 Left Volume bit0~7
1030         wm8994_write(0x611, 0x01A0);  //DAC1 Right Volume bit0~7
1031 }
1032
1033 void handsetMIC_to_baseband_to_headset_and_record(void)
1034 {
1035         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1036
1037         if(wm8994_current_mode == wm8994_handsetMIC_to_baseband_to_headset_and_record)return;
1038         wm8994_current_mode = wm8994_handsetMIC_to_baseband_to_headset_and_record;
1039         wm8994_reset();
1040         msleep(WM8994_DELAY);
1041
1042         wm8994_write(0x01,  0x0303);
1043         wm8994_write(0x02,  0x62C0);
1044         wm8994_write(0x03,  0x3030);
1045         wm8994_write(0x04,  0x0303);
1046         wm8994_write(0x18,  0x014B);  //volume
1047         wm8994_write(0x19,  0x014B);  //volume
1048         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1049         wm8994_write(0x1E,  0x0006);
1050         wm8994_write(0x28,  0x00B0);  //IN2LP_TO_IN2L
1051         wm8994_write(0x29,  0x0120);
1052         wm8994_write(0x2D,  0x0002);  //bit 1 IN2LP_TO_MIXOUTL
1053         wm8994_write(0x2E,  0x0002);  //bit 1 IN2RP_TO_MIXOUTR
1054         wm8994_write(0x34,  0x0002);
1055         wm8994_write(0x4C,  0x9F25);
1056         wm8994_write(0x60,  0x00EE);
1057         wm8994_write(0x200, 0x0001);
1058         wm8994_write(0x208, 0x000A);
1059         wm8994_write(0x300, 0x0050);
1060
1061 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
1062         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
1063         wm8994_write(0x303, 0x0090);  // master lrck 16k
1064 #endif
1065
1066         wm8994_write(0x606, 0x0002);
1067         wm8994_write(0x607, 0x0002);
1068         wm8994_write(0x620, 0x0000);
1069 }
1070
1071 void mainMIC_to_baseband_to_earpiece(void)
1072 {
1073         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1074
1075         if(wm8994_current_mode == wm8994_mainMIC_to_baseband_to_earpiece)return;
1076
1077         wm8994_codec_first_incall();
1078         wm8994_current_mode = wm8994_mainMIC_to_baseband_to_earpiece;
1079         wm8994_reset();
1080         msleep(WM8994_DELAY);
1081
1082         wm8994_write(0x700, 0xA101);
1083         wm8994_write(0x01,  0x0023);
1084         wm8994_write(0x200, 0x0000);
1085         mdelay(WM8994_DELAY);
1086
1087         wm8994_write(0x220, 0x0000);
1088         wm8994_write(0x221, 0x0700);
1089         wm8994_write(0x222, 0x3126);
1090         wm8994_write(0x223, 0x0100);
1091
1092         wm8994_write(0x220, 0x0004);
1093         msleep(10);
1094         wm8994_write(0x220, 0x0005);
1095         msleep(5);
1096
1097         wm8994_write(0x200, 0x0010);
1098         wm8994_write(0x208, 0x0008); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
1099         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
1100         wm8994_write(0x210, 0x0083); // SR=48KHz
1101 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
1102         wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
1103         wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
1104         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
1105         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
1106         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
1107         wm8994_write(0x300, 0x4010); // i2s 16 bits
1108 #endif
1109         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
1110
1111         wm8994_write(0x01,  0x0833); //HPOUT2_ENA=1, VMID_SEL=01, BIAS_ENA=1
1112         wm8994_write(0x4C,  0x9F25);
1113
1114         wm8994_write(0x02,  0x6250); //bit4 IN1R_ENV bit6 IN1L_ENV
1115         wm8994_write(0x03,  0x30F0);
1116         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
1117         wm8994_write(0x05,  0x0303);
1118         wm8994_write(0x1F,  0x0000);
1119
1120 #if defined(CONFIG_SND_INSIDE_EARPIECE)||defined(CONFIG_SND_OUTSIDE_EARPIECE)
1121         wm8994_set_channel_vol();
1122 #ifdef CONFIG_SND_INSIDE_EARPIECE
1123         wm8994_write(0x28,  0x0003); //IN1RP_TO_IN1R IN1RN_TO_IN1R
1124         wm8994_write(0x34,  0x0004); //IN1R_TO_LINEOUT1P
1125 #endif
1126 #ifdef CONFIG_SND_OUTSIDE_EARPIECE
1127         wm8994_write(0x28,  0x0030); //IN1LP_TO_IN1L IN1LN_TO_IN1L
1128         wm8994_write(0x34,  0x0002); //IN1L_TO_LINEOUT1P
1129 #endif
1130 #endif
1131 #ifdef CONFIG_SND_BB_NORMAL_INPUT
1132         wm8994_write(0x2D,  0x0003);  //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
1133         wm8994_write(0x2E,  0x0003);  //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
1134 #endif
1135 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
1136         wm8994_write(0x2B,  0x0007);  //VRX_MIXINL_VOL
1137         wm8994_write(0x2D,  0x0041);  //bit 1 MIXINL_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
1138         wm8994_write(0x2E,  0x0081);  //bit 1 MIXINL_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
1139 #endif
1140
1141         if(!first_incall){
1142                 wm8994_write(0x601, 0x0001); //AIF1DAC1L_TO_DAC1L=1
1143                 wm8994_write(0x602, 0x0001); //AIF1DAC1R_TO_DAC1R=1
1144         }
1145         wm8994_write(0x610, 0x01C0); //DAC1_VU=1, DAC1L_VOL=1100_0000
1146         wm8994_write(0x611, 0x01C0); //DAC1_VU=1, DAC1R_VOL=1100_0000
1147
1148         wm8994_write(0x420, 0x0000);
1149
1150         wm8994_set_level_volume();
1151 }
1152
1153 void mainMIC_to_baseband_to_earpiece_and_record(void)
1154 {
1155         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1156
1157         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)return;
1158         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
1159         wm8994_reset();
1160         msleep(WM8994_DELAY);
1161
1162         wm8994_write(0x01  ,0x0803|wm8994_mic_VCC);
1163         wm8994_write(0x02  ,0x6310);
1164         wm8994_write(0x03  ,0x30A0);
1165         wm8994_write(0x04  ,0x0303);
1166         wm8994_write(0x1A  ,0x014F);
1167         wm8994_write(0x1E  ,0x0006);
1168         wm8994_write(0x1F  ,0x0000);
1169         wm8994_write(0x28  ,0x0003);  //MAINMIC_TO_IN1R
1170         wm8994_write(0x2A  ,0x0020);  //IN1R_TO_MIXINR
1171         wm8994_write(0x2B  ,0x0005);  //VRX_MIXINL_VOL bit 0~2
1172         wm8994_write(0x2C  ,0x0005);  //VRX_MIXINR_VOL
1173         wm8994_write(0x2D  ,0x0040);  //MIXINL_TO_MIXOUTL
1174         wm8994_write(0x33  ,0x0010);  //MIXOUTLVOL_TO_HPOUT2
1175         wm8994_write(0x34  ,0x0004);  //IN1R_TO_LINEOUT1
1176         wm8994_write(0x200 ,0x0001);
1177         wm8994_write(0x208 ,0x000A);
1178         wm8994_write(0x300 ,0xC050);
1179         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1180
1181 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
1182         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
1183         wm8994_write(0x303, 0x0090);  // master lrck 16k
1184 #endif
1185
1186         wm8994_write(0x606 ,0x0002);
1187         wm8994_write(0x607 ,0x0002);
1188         wm8994_write(0x620 ,0x0000);
1189 }
1190
1191 void mainMIC_to_baseband_to_speakers(void)
1192 {
1193         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1194
1195         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers)return;
1196
1197         wm8994_codec_first_incall();
1198         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers;
1199         wm8994_reset();
1200         msleep(WM8994_DELAY);
1201         wm8994_set_volume(wm8994_current_mode,0,call_maxvol);
1202
1203         wm8994_write(0x700, 0xA101);
1204         wm8994_write(0x39,  0x006C);
1205         wm8994_write(0x01,  0x0023);
1206         wm8994_write(0x200, 0x0000);
1207         mdelay(WM8994_DELAY);
1208
1209         wm8994_write(0x220, 0x0000);
1210         wm8994_write(0x221, 0x0700);
1211         wm8994_write(0x222, 0x3126);
1212         wm8994_write(0x223, 0x0100);
1213
1214         wm8994_write(0x220, 0x0004);
1215         msleep(10);
1216         wm8994_write(0x220, 0x0005);
1217         msleep(5);
1218
1219         wm8994_write(0x200, 0x0010);
1220         wm8994_write(0x208, 0x0008); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
1221         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
1222         wm8994_write(0x210, 0x0083); // SR=48KHz
1223 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
1224         wm8994_write(0x302, 0x3000); // AIF1_MSTR=1
1225         wm8994_write(0x302, 0x7000); // AIF1_MSTR=1
1226         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
1227         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
1228         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
1229         wm8994_write(0x300, 0xC010); // i2s 16 bits
1230 #endif
1231         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
1232
1233         wm8994_write(0x610, 0x0100);
1234         wm8994_write(0x611, 0x0100);
1235
1236 //      wm8994_write(0x24,  0x0011);
1237         wm8994_set_channel_vol();
1238
1239         wm8994_write(0x02,  0x6210);
1240         wm8994_write(0x03,  0x1330);
1241         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
1242         wm8994_write(0x05,  0x0303);
1243         wm8994_write(0x22,  0x0000);
1244         wm8994_write(0x23,  0x0100);
1245         wm8994_write(0x28,  0x0003);  //IN1LN_TO_IN1L IN1LP_TO_IN1L
1246         wm8994_write(0x29,  0x0030);
1247 #ifdef CONFIG_SND_BB_NORMAL_INPUT
1248         wm8994_write(0x2D,  0x0003);  //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
1249         wm8994_write(0x2E,  0x0003);  //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
1250 #endif
1251 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
1252         wm8994_write(0x2B,  0x0005);  //VRX_MIXINL_VOL
1253         wm8994_write(0x2D,  0x0041);  //bit 1 MIXINL_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
1254         wm8994_write(0x2E,  0x0081);  //bit 1 MIXINL_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
1255 #endif
1256         wm8994_write(0x34,  0x000C);  //IN1L_TO_LINEOUT1P
1257
1258         wm8994_write(0x4C,  0x9F25);
1259         mdelay(5);
1260         wm8994_write(0x01,  0x3003);
1261         mdelay(50);
1262         wm8994_write(0x60,  0x0022);
1263         wm8994_write(0x36,  0x000C);
1264         wm8994_write(0x60,  0x00EE);
1265         wm8994_write(0x420, 0x0000);
1266         if(!first_incall){
1267                 wm8994_write(0x601, 0x0001);
1268                 wm8994_write(0x602, 0x0001);
1269         }
1270         wm8994_write(0x01,  0x3033);
1271         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1272         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1273
1274         wm8994_set_level_volume();
1275 }
1276
1277 void mainMIC_to_baseband_to_speakers_and_record(void)
1278 {
1279         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1280
1281         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record)return;
1282         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
1283         wm8994_reset();
1284         msleep(WM8994_DELAY);
1285
1286         wm8994_write(0x01, 0x3023|wm8994_mic_VCC);
1287         wm8994_write(0x02, 0x6330);
1288         wm8994_write(0x03, 0x3330);
1289         wm8994_write(0x04, 0x0303);
1290         wm8994_write(0x1A, 0x014B);
1291         wm8994_write(0x1B, 0x014B);
1292         wm8994_write(0x1E, 0x0006);
1293         wm8994_write(0x22, 0x0000);
1294         wm8994_write(0x23, 0x0100);
1295         wm8994_write(0x28, 0x0007);
1296         wm8994_write(0x2A, 0x0120);
1297         wm8994_write(0x2D, 0x0002);  //bit 1 IN2LP_TO_MIXOUTL
1298         wm8994_write(0x2E, 0x0002);  //bit 1 IN2RP_TO_MIXOUTR
1299         wm8994_write(0x34, 0x0004);
1300         wm8994_write(0x36, 0x000C);
1301         wm8994_write(0x200, 0x0001);
1302         wm8994_write(0x208, 0x000A);
1303         wm8994_write(0x300, 0xC050);
1304         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1305
1306 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
1307         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
1308         wm8994_write(0x303, 0x0090);  // master lrck 16k
1309 #endif
1310
1311         wm8994_write(0x606, 0x0002);
1312         wm8994_write(0x607, 0x0002);
1313         wm8994_write(0x620, 0x0000);
1314 }
1315
1316 void BT_baseband(void)
1317 {
1318         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1319
1320         if(wm8994_current_mode==wm8994_BT_baseband)return;
1321         wm8994_codec_first_incall();
1322         wm8994_current_mode=wm8994_BT_baseband;
1323         wm8994_reset();
1324         msleep(WM8994_DELAY);
1325
1326         wm8994_write(0x700, 0xA101);
1327         wm8994_write(0x705, 0xA101);
1328         wm8994_write(0x01,  0x0023);
1329         wm8994_write(0x200, 0x0000);
1330         msleep(WM8994_DELAY);
1331
1332         //roger_chen@20100524
1333         //8KHz, BCLK=8KHz*128=1024KHz, Fout=2.048MHz
1334         wm8994_write(0x220, 0x0000);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=0, FLL1_OSC_ENA=0, FLL1_ENA=0
1335         wm8994_write(0x221, 0x0700);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (2)(221H):  0700  FLL1_OUTDIV=2Fh, FLL1_CTRL_RATE=000, FLL1_FRATIO=000
1336         wm8994_write(0x222, 0x3126);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (3)(222H):  8FD5  FLL1_K=3126h
1337         wm8994_write(0x223, 0x0100);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (4)(223H):  00E0  FLL1_N=8h, FLL1_GAIN=0000
1338
1339         wm8994_write(0x220, 0x0004);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=0
1340         msleep(10);
1341         wm8994_write(0x220, 0x0005);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=1
1342         msleep(5);
1343
1344         wm8994_write(0x200, 0x0010);
1345         wm8994_write(0x208, 0x0008);
1346         wm8994_write(0x208, 0x000A);
1347
1348         wm8994_write(0x210, 0x0083);    // SMbus_16inx_16dat     Write  0x34      * SR=48KHz
1349 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
1350         wm8994_write(0x302, 0x3000);
1351         msleep(30);
1352         wm8994_write(0x302, 0x7000);
1353         wm8994_write(0x303, 0x0040);
1354         wm8994_write(0x304, 0x0040);
1355         wm8994_write(0x305, 0x0040);
1356         wm8994_write(0x300, 0xC050);    //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
1357 #endif
1358         wm8994_write(0x200, 0x0011);
1359
1360         wm8994_write(0x204, 0x0000);
1361         msleep(WM8994_DELAY);
1362         wm8994_write(0x240, 0x0000);
1363         wm8994_write(0x241, 0x2F00);
1364         wm8994_write(0x242, 0x3126);
1365         wm8994_write(0x243, 0x0100);
1366
1367         wm8994_write(0x240, 0x0004);
1368         msleep(10);
1369         wm8994_write(0x240, 0x0005);
1370         msleep(5);
1371
1372         wm8994_write(0x204, 0x0018);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1373         wm8994_write(0x208, 0x000E);
1374         wm8994_write(0x211, 0x0003);
1375 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
1376         wm8994_write(0x312, 0x3000);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Master/Slave(312H): 7000  AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
1377         msleep(30);
1378         wm8994_write(0x312, 0x7000);
1379         wm8994_write(0x313, 0x0020);    // SMbus_16inx_16dat     Write  0x34      * AIF2 BCLK DIV--------AIF1CLK/2
1380         wm8994_write(0x314, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 ADCLRCK DIV-----BCLK/128
1381         wm8994_write(0x315, 0x0080);
1382         wm8994_write(0x310, 0x0118);    //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
1383 #endif
1384         wm8994_write(0x204, 0x0019);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1385
1386         //roger_chen@20100519
1387         //enable AIF2 BCLK,LRCK
1388         //Rev.B and Rev.D is different
1389         wm8994_write(0x702, 0x2100);
1390         wm8994_write(0x703, 0x2100);
1391
1392         wm8994_write(0x704, 0xA100);
1393         wm8994_write(0x707, 0xA100);
1394         wm8994_write(0x708, 0x2100);
1395         wm8994_write(0x709, 0x2100);
1396         wm8994_write(0x70A, 0x2100);
1397
1398         wm8994_write(0x01,   0x3003);
1399         wm8994_write(0x02,   0x63A0);
1400         wm8994_write(0x03,   0x33F0);
1401         wm8994_write(0x04,   0x3303);
1402         wm8994_write(0x05,   0x3303);
1403         wm8994_write(0x06,   0x000A);
1404         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1405         wm8994_write(0x1E,   0x0006);
1406         wm8994_write(0x29,   0x0100);
1407         wm8994_write(0x2A,   0x0100);
1408
1409         wm8994_set_channel_vol();
1410
1411 #ifdef CONFIG_SND_BB_NORMAL_INPUT
1412         wm8994_write(0x28,   0x00C0);
1413 #endif
1414 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
1415         /*vol = BT_incall_vol;
1416         if(vol>6)vol=6;
1417         if(vol<-12)vol=-12;
1418         wm8994_write(0x2B, (vol+12)/3 + 1);*/
1419         wm8994_write(0x28,   0x00CC);
1420 #endif
1421         wm8994_write(0x22,   0x0000);
1422         wm8994_write(0x23,   0x0100);
1423         wm8994_write(0x24,   0x0009);
1424         wm8994_write(0x29,   0x0130);
1425         wm8994_write(0x2A,   0x0130);
1426         wm8994_write(0x2D,   0x0001);
1427         wm8994_write(0x2E,   0x0001);
1428         wm8994_write(0x34,   0x0001);
1429         wm8994_write(0x36,   0x0004);
1430         wm8994_write(0x4C,   0x9F25);
1431         wm8994_write(0x60,   0x00EE);
1432         wm8994_write(0x01,   0x3023);
1433
1434         wm8994_write(0x440, 0x0018);
1435         wm8994_write(0x450, 0x0018);
1436         wm8994_write(0x540, 0x01BF); //open nosie gate
1437         wm8994_write(0x550, 0x01BF); //open nosie gate
1438         wm8994_write(0x480, 0x0000);
1439         wm8994_write(0x481, 0x0000);
1440         wm8994_write(0x4A0, 0x0000);
1441         wm8994_write(0x4A1, 0x0000);
1442         wm8994_write(0x520, 0x0000);
1443         wm8994_write(0x540, 0x0018);
1444         wm8994_write(0x580, 0x0000);
1445         wm8994_write(0x581, 0x0000);
1446         wm8994_write(0x601, 0x0004);
1447         if(!first_incall){
1448                 wm8994_write(0x602, 0x0001);
1449         }
1450         wm8994_write(0x603, 0x000C);
1451         wm8994_write(0x604, 0x0010);
1452         wm8994_write(0x605, 0x0010);
1453         wm8994_write(0x610, 0x01C0);
1454         wm8994_write(0x611, 0x01C0);
1455         wm8994_write(0x612, 0x01C0);
1456         wm8994_write(0x613, 0x01C0);
1457         wm8994_write(0x620, 0x0000);
1458         wm8994_write(0x420, 0x0000);
1459 }
1460
1461 void BT_baseband_old(void)
1462 {
1463         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1464
1465         if(wm8994_current_mode==wm8994_BT_baseband)return;
1466         wm8994_codec_first_incall();
1467         wm8994_current_mode=wm8994_BT_baseband;
1468         wm8994_reset();
1469         msleep(WM8994_DELAY);
1470
1471         wm8994_write(0x01, 0x3003);
1472         wm8994_write(0x02, 0x63A0);
1473         wm8994_write(0x03, 0x33F0);
1474         wm8994_write(0x04, 0x3303);
1475         wm8994_write(0x05, 0x3303);
1476         wm8994_write(0x06, 0x000A);
1477         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1478         wm8994_write(0x1E, 0x0006);
1479         wm8994_write(0x29, 0x0100);
1480         wm8994_write(0x2A, 0x0100);
1481
1482         wm8994_set_channel_vol();
1483
1484 #ifdef CONFIG_SND_BB_NORMAL_INPUT
1485         wm8994_write(0x28, 0x00C0);
1486 #endif
1487 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
1488         /*vol = BT_incall_vol;
1489         if(vol>6)vol=6;
1490         if(vol<-12)vol=-12;
1491         wm8994_write(0x2B, (vol+12)/3 + 1);*/
1492         wm8994_write(0x28, 0x00CC);
1493 #endif
1494         wm8994_write(0x22, 0x0000);
1495         wm8994_write(0x23, 0x0100);
1496         wm8994_write(0x24, 0x0009);
1497         wm8994_write(0x29, 0x0130);
1498         wm8994_write(0x2A, 0x0130);
1499         wm8994_write(0x2D, 0x0001);
1500         wm8994_write(0x2E, 0x0001);
1501         wm8994_write(0x34, 0x0001);
1502         wm8994_write(0x36, 0x0004);
1503         wm8994_write(0x4C, 0x9F25);
1504         wm8994_write(0x60, 0x00EE);
1505         wm8994_write(0x01, 0x3023);
1506         //roger_chen@20100524
1507         //8KHz, BCLK=8KHz*128=1024KHz, Fout=2.048MHz
1508         wm8994_write(0x200, 0x0001);
1509         wm8994_write(0x204, 0x0001);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=00, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1510         wm8994_write(0x208, 0x000E);
1511         wm8994_write(0x220, 0x0000);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=0, FLL1_OSC_ENA=0, FLL1_ENA=0
1512         wm8994_write(0x221, 0x0700);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (2)(221H):  0700  FLL1_OUTDIV=2Fh, FLL1_CTRL_RATE=000, FLL1_FRATIO=000
1513         wm8994_write(0x222, 0x3126);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (3)(222H):  8FD5  FLL1_K=3126h
1514         wm8994_write(0x223, 0x0100);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (4)(223H):  00E0  FLL1_N=8h, FLL1_GAIN=0000
1515
1516         wm8994_write(0x303, 0x0040);
1517         wm8994_write(0x304, 0x0040);
1518         wm8994_write(0x305, 0x0040);
1519         wm8994_write(0x300, 0xC050);    //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
1520
1521         wm8994_write(0x210, 0x0083);    // SMbus_16inx_16dat     Write  0x34      * SR=48KHz
1522         wm8994_write(0x220, 0x0004);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=0
1523         msleep(50);
1524         wm8994_write(0x220, 0x0005);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=1
1525
1526         wm8994_write(0x240, 0x0000);
1527         wm8994_write(0x241, 0x2F00);
1528         wm8994_write(0x242, 0x3126);
1529         wm8994_write(0x243, 0x0100);
1530
1531         wm8994_write(0x313, 0x0020);    // SMbus_16inx_16dat     Write  0x34      * AIF2 BCLK DIV--------AIF1CLK/2
1532         wm8994_write(0x314, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 ADCLRCK DIV-----BCLK/128
1533         wm8994_write(0x315, 0x0080);
1534         wm8994_write(0x310, 0x0118);    //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
1535
1536         wm8994_write(0x211, 0x0003);    // SMbus_16inx_16dat     Write  0x34      * SR=8KHz
1537         wm8994_write(0x240, 0x0004);
1538         msleep(50);
1539         wm8994_write(0x240, 0x0005);
1540
1541         wm8994_write(0x200, 0x0011);
1542         wm8994_write(0x204, 0x0019);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1543         wm8994_write(0x440, 0x0018);
1544         wm8994_write(0x450, 0x0018);
1545         wm8994_write(0x540, 0x01BF); //open nosie gate
1546         wm8994_write(0x550, 0x01BF); //open nosie gate
1547         wm8994_write(0x480, 0x0000);
1548         wm8994_write(0x481, 0x0000);
1549         wm8994_write(0x4A0, 0x0000);
1550         wm8994_write(0x4A1, 0x0000);
1551         wm8994_write(0x520, 0x0000);
1552         wm8994_write(0x540, 0x0018);
1553         wm8994_write(0x580, 0x0000);
1554         wm8994_write(0x581, 0x0000);
1555         wm8994_write(0x601, 0x0004);
1556         if(!first_incall){
1557                 wm8994_write(0x602, 0x0001);
1558         }
1559         wm8994_write(0x603, 0x000C);
1560         wm8994_write(0x604, 0x0010);
1561         wm8994_write(0x605, 0x0010);
1562         wm8994_write(0x610, 0x01C0);
1563         wm8994_write(0x611, 0x01C0);
1564         wm8994_write(0x612, 0x01C0);
1565         wm8994_write(0x613, 0x01C0);
1566         wm8994_write(0x620, 0x0000);
1567         wm8994_write(0x420, 0x0000);
1568
1569         //roger_chen@20100519
1570         //enable AIF2 BCLK,LRCK
1571         //Rev.B and Rev.D is different
1572         wm8994_write(0x702, 0x2100);
1573         wm8994_write(0x703, 0x2100);
1574
1575         wm8994_write(0x704, 0xA100);
1576         wm8994_write(0x707, 0xA100);
1577         wm8994_write(0x708, 0x2100);
1578         wm8994_write(0x709, 0x2100);
1579         wm8994_write(0x70A, 0x2100);
1580 #ifdef CONFIG_SND_RK29_CODEC_SOC_MASTER
1581         wm8994_write(0x700, 0xA101);
1582         wm8994_write(0x705, 0xA101);
1583         wm8994_write(0x302, 0x3000);
1584         msleep(30);
1585         wm8994_write(0x302, 0x7000);
1586         msleep(30);
1587         wm8994_write(0x312, 0x3000);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Master/Slave(312H): 7000  AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
1588         msleep(30);
1589         wm8994_write(0x312, 0x7000);
1590 #endif
1591 }
1592
1593 void BT_baseband_and_record(void)
1594 {
1595         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1596
1597         if(wm8994_current_mode==wm8994_BT_baseband_and_record)return;
1598         wm8994_current_mode=wm8994_BT_baseband_and_record;
1599         wm8994_reset();
1600         msleep(WM8994_DELAY);
1601
1602         wm8994_write(0x01, 0x0023);
1603         wm8994_write(0x02, 0x63A0);
1604         wm8994_write(0x03, 0x30A0);
1605         wm8994_write(0x04, 0x3303);
1606         wm8994_write(0x05, 0x3002);
1607         wm8994_write(0x06, 0x000A);
1608         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1609         wm8994_write(0x1E, 0x0006);
1610         wm8994_write(0x28, 0x00CC);
1611         wm8994_write(0x29, 0x0100);
1612         wm8994_write(0x2A, 0x0100);
1613         wm8994_write(0x2D, 0x0001);
1614         wm8994_write(0x34, 0x0001);
1615         wm8994_write(0x200, 0x0001);
1616
1617         //roger_chen@20100524
1618         //8KHz, BCLK=8KHz*128=1024KHz, Fout=2.048MHz
1619         wm8994_write(0x204, 0x0001);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=00, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1620         wm8994_write(0x208, 0x000F);
1621         wm8994_write(0x220, 0x0000);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=0, FLL1_OSC_ENA=0, FLL1_ENA=0
1622         wm8994_write(0x221, 0x2F00);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (2)(221H):  0700  FLL1_OUTDIV=2Fh, FLL1_CTRL_RATE=000, FLL1_FRATIO=000
1623         wm8994_write(0x222, 0x3126);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (3)(222H):  8FD5  FLL1_K=3126h
1624         wm8994_write(0x223, 0x0100);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (4)(223H):  00E0  FLL1_N=8h, FLL1_GAIN=0000
1625         wm8994_write(0x302, 0x4000);
1626         wm8994_write(0x303, 0x0090);
1627         wm8994_write(0x310, 0xC118);  //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
1628         wm8994_write(0x312, 0x4000);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Master/Slave(312H): 7000  AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
1629         wm8994_write(0x313, 0x0020);    // SMbus_16inx_16dat     Write  0x34      * AIF2 BCLK DIV--------AIF1CLK/2
1630         wm8994_write(0x314, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 ADCLRCK DIV-----BCLK/128
1631         wm8994_write(0x315, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 DACLRCK DIV-----BCLK/128
1632         wm8994_write(0x210, 0x0003);    // SMbus_16inx_16dat     Write  0x34      * SR=8KHz
1633         wm8994_write(0x220, 0x0004);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=0
1634         msleep(WM8994_DELAY);
1635         wm8994_write(0x220, 0x0005);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=1
1636         wm8994_write(0x204, 0x0011);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1637
1638         wm8994_write(0x440, 0x0018);
1639         wm8994_write(0x450, 0x0018);
1640         wm8994_write(0x480, 0x0000);
1641         wm8994_write(0x481, 0x0000);
1642         wm8994_write(0x4A0, 0x0000);
1643         wm8994_write(0x4A1, 0x0000);
1644         wm8994_write(0x520, 0x0000);
1645         wm8994_write(0x540, 0x0018);
1646         wm8994_write(0x580, 0x0000);
1647         wm8994_write(0x581, 0x0000);
1648         wm8994_write(0x601, 0x0004);
1649         wm8994_write(0x603, 0x000C);
1650         wm8994_write(0x604, 0x0010);
1651         wm8994_write(0x605, 0x0010);
1652         wm8994_write(0x606, 0x0003);
1653         wm8994_write(0x607, 0x0003);
1654         wm8994_write(0x610, 0x01C0);
1655         wm8994_write(0x612, 0x01C0);
1656         wm8994_write(0x613, 0x01C0);
1657         wm8994_write(0x620, 0x0000);
1658
1659         //roger_chen@20100519
1660         //enable AIF2 BCLK,LRCK
1661         //Rev.B and Rev.D is different
1662         wm8994_write(0x702, 0xA100);
1663         wm8994_write(0x703, 0xA100);
1664
1665         wm8994_write(0x704, 0xA100);
1666         wm8994_write(0x707, 0xA100);
1667         wm8994_write(0x708, 0x2100);
1668         wm8994_write(0x709, 0x2100);
1669         wm8994_write(0x70A, 0x2100);
1670 }
1671
1672 #else //PCM_BB
1673
1674 /******************PCM BB BEGIN*****************/
1675
1676 void handsetMIC_to_baseband_to_headset(void) //pcmbaseband
1677 {
1678         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1679
1680         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset)return;
1681         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset;
1682         wm8994_reset();
1683         msleep(50);
1684
1685         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1686         msleep(50);
1687         wm8994_write(0x221, 0x0700);
1688         wm8994_write(0x222, 0x3127);
1689         wm8994_write(0x223, 0x0100);
1690         wm8994_write(0x220, 0x0004);
1691         msleep(50);
1692         wm8994_write(0x220, 0x0005);
1693
1694         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);  ///0x0303);         // sysclk = fll (bit4 =1)   0x0011
1695         wm8994_write(0x02,  0x0240);
1696         wm8994_write(0x03,  0x0030);
1697         wm8994_write(0x04,  0x3003);
1698         wm8994_write(0x05,  0x3003);  // i2s 16 bits
1699         wm8994_write(0x18,  0x010B);
1700         wm8994_write(0x28,  0x0030);
1701         wm8994_write(0x29,  0x0020);
1702         wm8994_write(0x2D,  0x0100);  //0x0100);DAC1L_TO_HPOUT1L    ;;;bit 8
1703         wm8994_write(0x2E,  0x0100);  //0x0100);DAC1R_TO_HPOUT1R    ;;;bit 8
1704         wm8994_write(0x4C,  0x9F25);
1705         wm8994_write(0x60,  0x00EE);
1706         wm8994_write(0x200, 0x0001);
1707         wm8994_write(0x204, 0x0001);
1708         wm8994_write(0x208, 0x0007);
1709         wm8994_write(0x520, 0x0000);
1710         wm8994_write(0x601, 0x0004);  //AIF2DACL_TO_DAC1L
1711         wm8994_write(0x602, 0x0004);  //AIF2DACR_TO_DAC1R
1712
1713         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1714         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1715         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1716         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1717
1718         wm8994_write(0x702, 0xC100);
1719         wm8994_write(0x703, 0xC100);
1720         wm8994_write(0x704, 0xC100);
1721         wm8994_write(0x706, 0x4100);
1722         wm8994_write(0x204, 0x0011);
1723         wm8994_write(0x211, 0x0009);
1724         #ifdef TD688_MODE
1725         wm8994_write(0x310, 0x4108); ///0x4118);  ///interface dsp mode 16bit
1726         #endif
1727         #ifdef CHONGY_MODE
1728         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1729         #endif
1730         #ifdef MU301_MODE
1731         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1732         wm8994_write(0x241, 0x2f04);
1733         wm8994_write(0x242, 0x0000);
1734         wm8994_write(0x243, 0x0300);
1735         wm8994_write(0x240, 0x0004);
1736         msleep(40);
1737         wm8994_write(0x240, 0x0005);
1738         wm8994_write(0x204, 0x0019);
1739         wm8994_write(0x211, 0x0003);
1740         wm8994_write(0x244, 0x0c83);
1741         wm8994_write(0x620, 0x0000);
1742         #endif
1743         #ifdef THINKWILL_M800_MODE
1744         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1745         #endif
1746         wm8994_write(0x313, 0x00F0);
1747         wm8994_write(0x314, 0x0020);
1748         wm8994_write(0x315, 0x0020);
1749         wm8994_write(0x603, 0x018c);  ///0x000C);  //Rev.D ADCL SideTone
1750         wm8994_write(0x604, 0x0010); //XX
1751         wm8994_write(0x605, 0x0010); //XX
1752         wm8994_write(0x621, 0x0000);  //0x0001);   ///0x0000);
1753         wm8994_write(0x317, 0x0003);
1754         wm8994_write(0x312, 0x0000); /// as slave  ///0x4000);  //AIF2 SET AS MASTER
1755
1756         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1757 }
1758
1759 void handsetMIC_to_baseband_to_headset_and_record(void) //pcmbaseband
1760 {
1761         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1762
1763         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record)return;
1764         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset_and_record;
1765         wm8994_reset();
1766         msleep(50);
1767
1768         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1769         msleep(50);
1770         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1771         wm8994_write(0x222, 0x3127);
1772         wm8994_write(0x223, 0x0100);
1773         wm8994_write(0x220, 0x0004);
1774         msleep(50);
1775         wm8994_write(0x220, 0x0005);
1776
1777         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);
1778         wm8994_write(0x02,  0x0240);
1779         wm8994_write(0x03,  0x0030);
1780         wm8994_write(0x04,  0x3003);
1781         wm8994_write(0x05,  0x3003);
1782         wm8994_write(0x18,  0x010B);  // 0x011F=+30dB for MIC
1783         wm8994_write(0x28,  0x0030);
1784         wm8994_write(0x29,  0x0020);
1785         wm8994_write(0x2D,  0x0100);
1786         wm8994_write(0x2E,  0x0100);
1787         wm8994_write(0x4C,  0x9F25);
1788         wm8994_write(0x60,  0x00EE);
1789         wm8994_write(0x200, 0x0001);
1790         wm8994_write(0x204, 0x0001);
1791         wm8994_write(0x208, 0x0007);
1792         wm8994_write(0x520, 0x0000);
1793         wm8994_write(0x601, 0x0004);
1794         wm8994_write(0x602, 0x0004);
1795
1796         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1797         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1798         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1799         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1800
1801         wm8994_write(0x700, 0x8141);  //SYNC issue, AIF1 ADCLRC1 from LRCK1
1802         wm8994_write(0x702, 0xC100);
1803         wm8994_write(0x703, 0xC100);
1804         wm8994_write(0x704, 0xC100);
1805         wm8994_write(0x706, 0x4100);
1806         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1807         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1808         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1809         wm8994_write(0x313, 0x00F0);
1810         wm8994_write(0x314, 0x0020);
1811         wm8994_write(0x315, 0x0020);
1812
1813         wm8994_write(0x603, 0x018c);  ///0x000C);  //Rev.D ADCL SideTone
1814         wm8994_write(0x604, 0x0010);
1815         wm8994_write(0x605, 0x0010);
1816         wm8994_write(0x621, 0x0000);
1817         //wm8994_write(0x317, 0x0003);
1818         //wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1819 ////AIF1
1820         wm8994_write(0x04,   0x3303);
1821         wm8994_write(0x200,  0x0001);
1822         wm8994_write(0x208,  0x000F);
1823         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1824         wm8994_write(0x300,  0x0118);  //DSP/PCM 16bits, R ADC = L ADC
1825         wm8994_write(0x606,  0x0003);
1826         wm8994_write(0x607,  0x0003);
1827
1828 ////AIF1 Master Clock(SR=8KHz)
1829         wm8994_write(0x200,  0x0011);
1830         wm8994_write(0x302,  0x4000);
1831         wm8994_write(0x303,  0x00F0);
1832         wm8994_write(0x304,  0x0020);
1833         wm8994_write(0x305,  0x0020);
1834
1835 ////AIF1 DAC1 HP
1836         wm8994_write(0x05,   0x3303);
1837         wm8994_write(0x420,  0x0000);
1838         wm8994_write(0x601,  0x0001);
1839         wm8994_write(0x602,  0x0001);
1840         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1841
1842         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1843 }
1844
1845 void mainMIC_to_baseband_to_earpiece(void) //pcmbaseband
1846 {
1847         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1848
1849         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)return;
1850         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
1851         wm8994_reset();
1852         msleep(50);
1853
1854         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1855         msleep(50);
1856         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1857         wm8994_write(0x222, 0x3127);
1858         wm8994_write(0x223, 0x0100);
1859         wm8994_write(0x220, 0x0004);
1860         msleep(50);
1861         wm8994_write(0x220, 0x0005);
1862
1863         wm8994_write(0x01,  0x0803|wm8994_mic_VCC);   ///0x0813);
1864         wm8994_write(0x02,  0x0240);   ///0x0110);
1865         wm8994_write(0x03,  0x00F0);
1866         wm8994_write(0x04,  0x3003);
1867         wm8994_write(0x05,  0x3003);
1868         wm8994_write(0x18,  0x011F);
1869         wm8994_write(0x1F,  0x0000);
1870         wm8994_write(0x28,  0x0030);  ///0x0003);
1871         wm8994_write(0x29,  0x0020);
1872         wm8994_write(0x2D,  0x0001);
1873         wm8994_write(0x2E,  0x0001);
1874         wm8994_write(0x33,  0x0018);
1875         wm8994_write(0x200, 0x0001);
1876         wm8994_write(0x204, 0x0001);
1877         wm8994_write(0x208, 0x0007);
1878         wm8994_write(0x520, 0x0000);
1879         wm8994_write(0x601, 0x0004);
1880         wm8994_write(0x602, 0x0004);
1881
1882         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1883         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1884         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1885         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1886
1887         wm8994_write(0x702, 0xC100);
1888         wm8994_write(0x703, 0xC100);
1889         wm8994_write(0x704, 0xC100);
1890         wm8994_write(0x706, 0x4100);
1891         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1892         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1893         #ifdef TD688_MODE
1894         wm8994_write(0x310, 0x4108); ///0x4118);  ///interface dsp mode 16bit
1895         #endif
1896         #ifdef CHONGY_MODE
1897         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1898         #endif
1899         #ifdef MU301_MODE
1900         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1901         wm8994_write(0x241, 0x2f04);
1902         wm8994_write(0x242, 0x0000);
1903         wm8994_write(0x243, 0x0300);
1904         wm8994_write(0x240, 0x0004);
1905         msleep(40);
1906         wm8994_write(0x240, 0x0005);
1907         wm8994_write(0x204, 0x0019);
1908         wm8994_write(0x211, 0x0003);
1909         wm8994_write(0x244, 0x0c83);
1910         wm8994_write(0x620, 0x0000);
1911         #endif
1912         #ifdef THINKWILL_M800_MODE
1913         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1914         #endif
1915         wm8994_write(0x313, 0x00F0);
1916         wm8994_write(0x314, 0x0020);
1917         wm8994_write(0x315, 0x0020);
1918
1919         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1920         wm8994_write(0x604, 0x0010);
1921         wm8994_write(0x605, 0x0010);
1922         wm8994_write(0x621, 0x0000);  ///0x0001);
1923         wm8994_write(0x317, 0x0003);
1924         wm8994_write(0x312, 0x0000);  //AIF2 SET AS MASTER
1925
1926         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1927 }
1928
1929 void mainMIC_to_baseband_to_earpiece_and_record(void) //pcmbaseband
1930 {
1931         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1932
1933         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)return;
1934         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
1935         wm8994_reset();
1936         msleep(50);
1937
1938         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1939         msleep(50);
1940         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1941         wm8994_write(0x222, 0x3127);
1942         wm8994_write(0x223, 0x0100);
1943         wm8994_write(0x220, 0x0004);
1944         msleep(50);
1945         wm8994_write(0x220, 0x0005);
1946
1947         wm8994_write(0x01,  0x0803|wm8994_mic_VCC);
1948         wm8994_write(0x02,  0x0110);
1949         wm8994_write(0x03,  0x00F0);
1950         wm8994_write(0x04,  0x3003);
1951         wm8994_write(0x05,  0x3003);
1952         wm8994_write(0x1A,  0x010B);
1953         wm8994_write(0x1F,  0x0000);
1954         wm8994_write(0x28,  0x0003);
1955         wm8994_write(0x2A,  0x0020);
1956         wm8994_write(0x2D,  0x0001);
1957         wm8994_write(0x2E,  0x0001);
1958         wm8994_write(0x33,  0x0018);
1959         wm8994_write(0x200, 0x0001);
1960         wm8994_write(0x204, 0x0001);
1961         wm8994_write(0x208, 0x0007);
1962         wm8994_write(0x520, 0x0000);
1963         wm8994_write(0x601, 0x0004);
1964         wm8994_write(0x602, 0x0004);
1965
1966         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1967         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1968         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1969         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1970
1971         wm8994_write(0x702, 0xC100);
1972         wm8994_write(0x703, 0xC100);
1973         wm8994_write(0x704, 0xC100);
1974         wm8994_write(0x706, 0x4100);
1975         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1976         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1977         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1978         wm8994_write(0x313, 0x00F0);
1979         wm8994_write(0x314, 0x0020);
1980         wm8994_write(0x315, 0x0020);
1981
1982         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1983         wm8994_write(0x604, 0x0010);
1984         wm8994_write(0x605, 0x0010);
1985         wm8994_write(0x621, 0x0001);
1986
1987 ////AIF1
1988         wm8994_write(0x04,   0x3303);
1989         wm8994_write(0x200,  0x0001);
1990         wm8994_write(0x208,  0x000F);
1991         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1992         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1993         wm8994_write(0x606,  0x0003);
1994         wm8994_write(0x607,  0x0003);
1995
1996 ////AIF1 Master Clock(SR=8KHz)
1997         wm8994_write(0x200,  0x0011);
1998         wm8994_write(0x302,  0x4000);
1999         wm8994_write(0x303,  0x00F0);
2000         wm8994_write(0x304,  0x0020);
2001         wm8994_write(0x305,  0x0020);
2002
2003 ////AIF1 DAC1 HP
2004         wm8994_write(0x05,   0x3303);
2005         wm8994_write(0x420,  0x0000);
2006         wm8994_write(0x601,  0x0001);
2007         wm8994_write(0x602,  0x0001);
2008         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
2009
2010         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
2011 }
2012
2013 void mainMIC_to_baseband_to_speakers(void) //pcmbaseband
2014 {
2015         DBG("%s::%d\n",__FUNCTION__,__LINE__);
2016
2017         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers)return;
2018         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers;
2019         wm8994_reset();
2020         msleep(50);
2021
2022         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);  //0x0013);
2023         msleep(50);
2024         wm8994_write(0x221, 0x0700);  //MCLK=12MHz   //FLL1 CONTRLO(2)
2025         wm8994_write(0x222, 0x3127);  //FLL1 CONTRLO(3)
2026         wm8994_write(0x223, 0x0100);  //FLL1 CONTRLO(4)
2027         wm8994_write(0x220, 0x0004);  //FLL1 CONTRLO(1)
2028         msleep(50);
2029         wm8994_write(0x220, 0x0005);  //FLL1 CONTRLO(1)
2030
2031         wm8994_write(0x01,  0x3003|wm8994_mic_VCC);
2032         wm8994_write(0x02,  0x0110);
2033         wm8994_write(0x03,  0x0030);  ///0x0330);
2034         wm8994_write(0x04,  0x3003);
2035         wm8994_write(0x05,  0x3003);
2036         wm8994_write(0x1A,  0x011F);
2037         wm8994_write(0x22,  0x0000);
2038         wm8994_write(0x23,  0x0100);  ///0x0000);
2039         //wm8994_write(0x25,  0x0152);
2040         wm8994_write(0x28,  0x0003);
2041         wm8994_write(0x2A,  0x0020);
2042         wm8994_write(0x2D,  0x0001);
2043         wm8994_write(0x2E,  0x0001);
2044         wm8994_write(0x36,  0x000C);  //MIXOUTL_TO_SPKMIXL  MIXOUTR_TO_SPKMIXR
2045         wm8994_write(0x200, 0x0001);  //AIF1 CLOCKING(1)
2046         wm8994_write(0x204, 0x0001);  //AIF2 CLOCKING(1)
2047         wm8994_write(0x208, 0x0007);  //CLOCKING(1)
2048         wm8994_write(0x520, 0x0000);  //AIF2 DAC FILTERS(1)
2049         wm8994_write(0x601, 0x0004);  //AIF2DACL_DAC1L
2050         wm8994_write(0x602, 0x0004);  //AIF2DACR_DAC1R
2051
2052         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
2053         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
2054         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
2055         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
2056
2057         wm8994_write(0x702, 0xC100);  //GPIO3
2058         wm8994_write(0x703, 0xC100);  //GPIO4
2059         wm8994_write(0x704, 0xC100);  //GPIO5
2060         wm8994_write(0x706, 0x4100);  //GPIO7
2061         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
2062         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
2063         #ifdef TD688_MODE
2064         wm8994_write(0x310, 0xc108); ///0x4118);  ///interface dsp mode 16bit
2065         #endif
2066         #ifdef CHONGY_MODE
2067         wm8994_write(0x310, 0xc018); ///0x4118);  ///interface dsp mode 16bit
2068         #endif
2069         #ifdef MU301_MODE
2070         wm8994_write(0x310, 0xc118); ///0x4118);  ///interface dsp mode 16bit
2071         wm8994_write(0x241, 0x2f04);
2072         wm8994_write(0x242, 0x0000);
2073         wm8994_write(0x243, 0x0300);
2074         wm8994_write(0x240, 0x0004);
2075         msleep(40);
2076         wm8994_write(0x240, 0x0005);
2077         wm8994_write(0x204, 0x0019);
2078         wm8994_write(0x211, 0x0003);
2079         wm8994_write(0x244, 0x0c83);
2080         wm8994_write(0x620, 0x0000);
2081         #endif
2082         #ifdef THINKWILL_M800_MODE
2083         wm8994_write(0x310, 0xc118); ///0x4118);  ///interface dsp mode 16bit
2084         #endif
2085         wm8994_write(0x313, 0x00F0);  //AIF2BCLK
2086         wm8994_write(0x314, 0x0020);  //AIF2ADCLRCK
2087         wm8994_write(0x315, 0x0020);  //AIF2DACLRCLK
2088
2089         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
2090         wm8994_write(0x604, 0x0020);  ///0x0010);  //ADC2_TO_DAC2L
2091         wm8994_write(0x605, 0x0020);  //0x0010);  //ADC2_TO_DAC2R
2092         wm8994_write(0x621, 0x0000);  ///0x0001);
2093         wm8994_write(0x317, 0x0003);
2094         wm8994_write(0x312, 0x0000);  //AIF2 SET AS MASTER
2095
2096         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
2097 }
2098
2099 void mainMIC_to_baseband_to_speakers_and_record(void) //pcmbaseband
2100 {
2101         DBG("%s::%d\n",__FUNCTION__,__LINE__);
2102
2103         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record)return;
2104         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
2105         wm8994_reset();
2106         msleep(50);
2107
2108         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
2109         msleep(50);
2110         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
2111         wm8994_write(0x222, 0x3127);
2112         wm8994_write(0x223, 0x0100);
2113         wm8994_write(0x220, 0x0004);
2114         msleep(50);
2115         wm8994_write(0x220, 0x0005);
2116
2117         wm8994_write(0x02,  0x0110);
2118         wm8994_write(0x03,  0x0330);
2119         wm8994_write(0x04,  0x3003);
2120         wm8994_write(0x05,  0x3003);
2121         wm8994_write(0x1A,  0x010B);
2122         wm8994_write(0x22,  0x0000);
2123         wm8994_write(0x23,  0x0000);
2124         wm8994_write(0x28,  0x0003);
2125         wm8994_write(0x2A,  0x0020);
2126         wm8994_write(0x2D,  0x0001);
2127         wm8994_write(0x2E,  0x0001);
2128         wm8994_write(0x36,  0x000C);
2129         wm8994_write(0x200, 0x0001);
2130         wm8994_write(0x204, 0x0001);
2131         wm8994_write(0x208, 0x0007);
2132         wm8994_write(0x520, 0x0000);
2133         wm8994_write(0x601, 0x0004);
2134         wm8994_write(0x602, 0x0004);
2135
2136         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
2137         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
2138         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
2139         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
2140
2141         wm8994_write(0x700, 0x8141);
2142         wm8994_write(0x702, 0xC100);
2143         wm8994_write(0x703, 0xC100);
2144         wm8994_write(0x704, 0xC100);
2145         wm8994_write(0x706, 0x4100);
2146         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
2147         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
2148         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
2149         wm8994_write(0x313, 0x00F0);
2150         wm8994_write(0x314, 0x0020);
2151         wm8994_write(0x315, 0x0020);
2152
2153         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
2154         wm8994_write(0x604, 0x0010);
2155         wm8994_write(0x605, 0x0010);
2156         wm8994_write(0x621, 0x0001);
2157
2158 ////AIF1
2159         wm8994_write(0x04,   0x3303);
2160         wm8994_write(0x200,  0x0001);
2161         wm8994_write(0x208,  0x000F);
2162         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
2163         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
2164         wm8994_write(0x606,  0x0003);
2165         wm8994_write(0x607,  0x0003);
2166
2167 ////AIF1 Master Clock(SR=8KHz)
2168         wm8994_write(0x200,  0x0011);
2169         wm8994_write(0x302,  0x4000);
2170         wm8994_write(0x303,  0x00F0);
2171         wm8994_write(0x304,  0x0020);
2172         wm8994_write(0x305,  0x0020);
2173
2174 ////AIF1 DAC1 HP
2175         wm8994_write(0x05,   0x3303);
2176         wm8994_write(0x420,  0x0000);
2177         wm8994_write(0x601,  0x0001);
2178         wm8994_write(0x602,  0x0001);
2179         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
2180
2181         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
2182 }
2183
2184 void BT_baseband(void) //pcmbaseband
2185 {
2186         DBG("%s::%d\n",__FUNCTION__,__LINE__);
2187
2188         if(wm8994_current_mode==wm8994_BT_baseband)return;
2189         wm8994_current_mode=wm8994_BT_baseband;
2190         wm8994_reset();
2191         msleep(50);
2192
2193         wm8994_write(0x01 ,0x0003);
2194         msleep (50);
2195
2196         wm8994_write(0x200 ,0x0001);
2197         wm8994_write(0x221 ,0x0700);//MCLK=12MHz
2198         wm8994_write(0x222 ,0x3127);
2199         wm8994_write(0x223 ,0x0100);
2200         wm8994_write(0x220 ,0x0004);
2201         msleep (50);
2202         wm8994_write(0x220 ,0x0005);
2203
2204         wm8994_write(0x02 ,0x0000);
2205         wm8994_write(0x200 ,0x0011);// AIF1 MCLK=FLL1
2206         wm8994_write(0x210 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
2207         wm8994_write(0x300 ,0x4018);// DSP/PCM 16bits
2208
2209         wm8994_write(0x204 ,0x0011);// AIF2 MCLK=FLL1
2210         wm8994_write(0x211 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
2211         wm8994_write(0x310 ,0x4118);// DSP/PCM 16bits
2212         wm8994_write(0x208 ,0x000F);
2213
2214 /////AIF1
2215         wm8994_write(0x700 ,0x8101);
2216 /////AIF2
2217         wm8994_write(0x702 ,0xC100);
2218         wm8994_write(0x703 ,0xC100);
2219         wm8994_write(0x704 ,0xC100);
2220         wm8994_write(0x706 ,0x4100);
2221 /////AIF3
2222         wm8994_write(0x707 ,0xA100);
2223         wm8994_write(0x708 ,0xA100);
2224         wm8994_write(0x709 ,0xA100);
2225         wm8994_write(0x70A ,0xA100);
2226
2227         wm8994_write(0x06 ,0x0001);
2228
2229         wm8994_write(0x02 ,0x0300);
2230         wm8994_write(0x03 ,0x0030);
2231         wm8994_write(0x04 ,0x3301);//ADCL off
2232         wm8994_write(0x05 ,0x3301);//DACL off
2233
2234         wm8994_write(0x2A ,0x0005);
2235
2236         wm8994_write(0x313 ,0x00F0);
2237         wm8994_write(0x314 ,0x0020);
2238         wm8994_write(0x315 ,0x0020);
2239
2240         wm8994_write(0x2E ,0x0001);
2241         wm8994_write(0x420 ,0x0000);
2242         wm8994_write(0x520 ,0x0000);
2243         wm8994_write(0x601 ,0x0001);
2244         wm8994_write(0x602 ,0x0001);
2245         wm8994_write(0x604 ,0x0001);
2246         wm8994_write(0x605 ,0x0001);
2247         wm8994_write(0x607 ,0x0002);
2248         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
2249         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
2250         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
2251
2252
2253         wm8994_write(0x312 ,0x4000);
2254
2255         wm8994_write(0x606 ,0x0001);
2256         wm8994_write(0x607 ,0x0003);//R channel for data mix/CPU record data
2257
2258
2259 ////////////HP output test
2260         wm8994_write(0x01 ,0x0303);
2261         wm8994_write(0x4C ,0x9F25);
2262         wm8994_write(0x60 ,0x00EE);
2263 ///////////end HP test
2264
2265         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
2266 }
2267
2268 void BT_baseband_and_record(void) //pcmbaseband
2269 {
2270         DBG("%s::%d\n",__FUNCTION__,__LINE__);
2271
2272         if(wm8994_current_mode==wm8994_BT_baseband_and_record)return;
2273         wm8994_current_mode=wm8994_BT_baseband_and_record;
2274         wm8994_reset();
2275         msleep(50);
2276
2277         wm8994_write(0x01  ,0x0003);
2278         msleep (50);
2279
2280         wm8994_write(0x200 ,0x0001);
2281         wm8994_write(0x221 ,0x0700);//MCLK=12MHz
2282         wm8994_write(0x222 ,0x3127);
2283         wm8994_write(0x223 ,0x0100);
2284         wm8994_write(0x220 ,0x0004);
2285         msleep (50);
2286         wm8994_write(0x220 ,0x0005);
2287
2288         wm8994_write(0x02 ,0x0000);
2289         wm8994_write(0x200 ,0x0011);// AIF1 MCLK=FLL1
2290         wm8994_write(0x210 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
2291         wm8994_write(0x300 ,0x4018);// DSP/PCM 16bits
2292
2293         wm8994_write(0x204 ,0x0011);// AIF2 MCLK=FLL1
2294         wm8994_write(0x211 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
2295         wm8994_write(0x310 ,0x4118);// DSP/PCM 16bits
2296         wm8994_write(0x208 ,0x000F);
2297
2298 /////AIF1
2299         wm8994_write(0x700 ,0x8101);
2300 /////AIF2
2301         wm8994_write(0x702 ,0xC100);
2302         wm8994_write(0x703 ,0xC100);
2303         wm8994_write(0x704 ,0xC100);
2304         wm8994_write(0x706 ,0x4100);
2305 /////AIF3
2306         wm8994_write(0x707 ,0xA100);
2307         wm8994_write(0x708 ,0xA100);
2308         wm8994_write(0x709 ,0xA100);
2309         wm8994_write(0x70A ,0xA100);
2310
2311         wm8994_write(0x06 ,0x0001);
2312         wm8994_write(0x02 ,0x0300);
2313         wm8994_write(0x03 ,0x0030);
2314         wm8994_write(0x04 ,0x3301);//ADCL off
2315         wm8994_write(0x05 ,0x3301);//DACL off
2316         wm8994_write(0x2A ,0x0005);
2317
2318         wm8994_write(0x313 ,0x00F0);
2319         wm8994_write(0x314 ,0x0020);
2320         wm8994_write(0x315 ,0x0020);
2321
2322         wm8994_write(0x2E  ,0x0001);
2323         wm8994_write(0x420 ,0x0000);
2324         wm8994_write(0x520 ,0x0000);
2325         wm8994_write(0x602 ,0x0001);
2326         wm8994_write(0x604 ,0x0001);
2327         wm8994_write(0x605 ,0x0001);
2328         wm8994_write(0x607 ,0x0002);
2329         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
2330         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
2331         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
2332
2333         wm8994_write(0x312 ,0x4000);
2334
2335         wm8994_write(0x606 ,0x0001);
2336         wm8994_write(0x607 ,0x0003);//R channel for data mix/CPU record data
2337 ////////////HP output test
2338         wm8994_write(0x01 ,0x0303);
2339         wm8994_write(0x4C ,0x9F25);
2340         wm8994_write(0x60 ,0x00EE);
2341 ///////////end HP test
2342
2343         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
2344 }
2345 #endif //PCM_BB
2346
2347
2348 typedef void (wm8994_codec_fnc_t) (void);
2349
2350 wm8994_codec_fnc_t *wm8994_codec_sequence[] = {
2351         AP_to_headset,
2352         AP_to_speakers,
2353         AP_to_speakers_and_headset,
2354         recorder_and_AP_to_headset,
2355         recorder_and_AP_to_speakers,
2356         FM_to_headset,
2357         FM_to_headset_and_record,
2358         FM_to_speakers,
2359         FM_to_speakers_and_record,
2360         handsetMIC_to_baseband_to_headset,
2361         mainMIC_to_baseband_to_headset,
2362         handsetMIC_to_baseband_to_headset_and_record,
2363         mainMIC_to_baseband_to_earpiece,
2364         mainMIC_to_baseband_to_earpiece_and_record,
2365         mainMIC_to_baseband_to_speakers,
2366         mainMIC_to_baseband_to_speakers_and_record,
2367         BT_baseband,
2368         BT_baseband_and_record,
2369 };
2370
2371 void wm8994_set_AIF1DAC_EQ(void){
2372
2373         wm8994_write(0x0480, 0x0001|((bank_vol[1]+12)<<11)|
2374                 ((bank_vol[2]+12)<<6)|((bank_vol[3]+12)<<1));
2375         wm8994_write(0x0481, 0x0000|((bank_vol[4]+12)<<11)|
2376                 ((bank_vol[5]+12)<<6));
2377 }
2378
2379 void wm8994_set_channel_vol(void)
2380 {
2381         switch(wm8994_current_mode){
2382         case wm8994_AP_to_speakers_and_headset:
2383                 if(speaker_normal_vol > 6)
2384                         speaker_normal_vol = 6;
2385                 else if(speaker_normal_vol < -57)
2386                         speaker_normal_vol = -57;
2387                 if(headset_normal_vol > 6)
2388                         headset_normal_vol = 6;
2389                 else if(headset_normal_vol < -57)
2390                         headset_normal_vol = -57;
2391
2392                 DBG("headset_normal_vol = %ddB \n",headset_normal_vol);
2393                 DBG("speaker_normal_vol = %ddB \n",speaker_normal_vol);
2394
2395                 vol = speaker_normal_vol;
2396                 if(vol<=6){
2397                         wm8994_write(0x26,  320+vol+57);  //-57dB~6dB
2398                         wm8994_write(0x27,  320+vol+57);  //-57dB~6dB
2399                 }else{
2400                 //      wm8994_write(0x25,  0x003F);      //0~12dB
2401                         wm8994_write(0x26,  320+vol+45);  //-57dB~6dB
2402                         wm8994_write(0x27,  320+vol+45);  //-57dB~6dB
2403                 }
2404                 vol = headset_normal_vol-4;
2405
2406                 //for turn down headset volume when ringtone
2407                 if(vol >= -48)
2408                         vol -= 14;
2409                 else
2410                         vol = -57;
2411
2412                 wm8994_write(0x1C,  320+vol+57);  //-57dB~6dB
2413                 wm8994_write(0x1D,  320+vol+57);  //-57dB~6dB
2414
2415                 wm8994_set_AIF1DAC_EQ();
2416                 break;
2417
2418         case wm8994_recorder_and_AP_to_headset:
2419                 if(headset_normal_vol > 6)
2420                         headset_normal_vol = 6;
2421                 else if(headset_normal_vol < -57)
2422                         headset_normal_vol = -57;
2423                 if(recorder_vol > 60)
2424                         recorder_vol = 60;
2425                 else if(recorder_vol < -16)
2426                         recorder_vol = -16;
2427
2428                 DBG("recorder_vol = %ddB \n",recorder_vol);
2429                 DBG("headset_normal_vol = %ddB \n",headset_normal_vol);
2430
2431                 vol = recorder_vol;
2432                 if(vol<30){
2433                         wm8994_write(0x1A,  320+(vol+16)*10/15);  //mic vol
2434                 }else{
2435                         wm8994_write(0x2A,  0x0030);
2436                         wm8994_write(0x1A,  320+(vol-14)*10/15);  //mic vol
2437                 }
2438                 vol = headset_normal_vol;
2439                 wm8994_write(0x1C,  320+vol+57);  //-57dB~6dB
2440                 wm8994_write(0x1D,  320+vol+57);  //-57dB~6dB
2441                 break;
2442
2443         case wm8994_recorder_and_AP_to_speakers:
2444                 if(recorder_vol > 60)
2445                         recorder_vol = 60;
2446                 else if(recorder_vol < -16)
2447                         recorder_vol = -16;
2448                 if(speaker_normal_vol > 6)
2449                         speaker_normal_vol = 6;
2450                 else if(speaker_normal_vol < -57)
2451                         speaker_normal_vol = -57;
2452
2453                 DBG("speaker_normal_vol = %ddB \n",speaker_normal_vol);
2454                 DBG("recorder_vol = %ddB \n",recorder_vol);
2455
2456                 vol = recorder_vol;
2457                 if(vol<30){
2458                         wm8994_write(0x1A,  320+(vol+16)*10/15);  //mic vol
2459                 }else{
2460                         wm8994_write(0x2A,  0x0030);
2461                         wm8994_write(0x1A,  320+(vol-14)*10/15);  //mic vol
2462                 }
2463
2464                 vol = speaker_normal_vol;
2465                 wm8994_write(0x26,  320+vol+57);  //-57dB~6dB
2466                 wm8994_write(0x27,  320+vol+57);  //-57dB~6dB
2467
2468                 wm8994_set_AIF1DAC_EQ();
2469                 break;
2470
2471         case wm8994_handsetMIC_to_baseband_to_headset:
2472                 if(headset_incall_vol > 6)
2473                         headset_incall_vol = 6;
2474                 else if(headset_incall_vol < -12)
2475                         headset_incall_vol = -12;
2476                 if(headset_incall_mic_vol > 30)
2477                         headset_incall_mic_vol = 30;
2478                 else if(headset_incall_mic_vol < -22)
2479                         headset_incall_mic_vol = -22;
2480
2481                 DBG("headset_incall_mic_vol = %ddB \n",headset_incall_mic_vol);
2482                 DBG("headset_incall_vol = %ddB \n",headset_incall_vol);
2483
2484                 vol = headset_incall_mic_vol;
2485                 if(vol<-16){
2486                         wm8994_write(0x1E,  0x0016);  //mic vol
2487                         wm8994_write(0x18,  320+(vol+22)*10/15);  //mic vol
2488                 }else{
2489                         wm8994_write(0x1E,  0x0006);  //mic vol
2490                         wm8994_write(0x18,  320+(vol+16)*10/15);  //mic vol
2491                 }
2492 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
2493                 vol = headset_incall_vol;
2494                 wm8994_write(0x2B,  (vol+12)/3+1);  //-12~6dB
2495 #endif
2496                 break;
2497
2498         case wm8994_mainMIC_to_baseband_to_headset:
2499                 if(headset_incall_vol > 6)
2500                         headset_incall_vol = 6;
2501                 else if(headset_incall_vol < -12)
2502                         headset_incall_vol = -12;
2503                 if(speaker_incall_mic_vol > 30)
2504                         speaker_incall_mic_vol = 30;
2505                 else if(speaker_incall_mic_vol < -22)
2506                         speaker_incall_mic_vol = -22;
2507
2508                 DBG("speaker_incall_mic_vol = %ddB \n",speaker_incall_mic_vol);
2509                 DBG("headset_incall_vol = %ddB \n",headset_incall_vol);
2510
2511                 vol=speaker_incall_mic_vol;
2512                 if(vol<-16){
2513                         wm8994_write(0x1E,  0x0016);  //mic vol
2514                         wm8994_write(0x1A,  320+(vol+22)*10/15);  //mic vol
2515                 }else{
2516                         wm8994_write(0x1E,  0x0006);  //mic vol
2517                         wm8994_write(0x1A,  320+(vol+16)*10/15);  //mic vol
2518                 }
2519 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
2520                 vol = headset_incall_vol;
2521                 wm8994_write(0x2B,  (vol+12)/3+1);  //-12~6dB
2522 #endif
2523                 break;
2524
2525         case wm8994_mainMIC_to_baseband_to_earpiece:
2526                 if(speaker_incall_mic_vol > 30)
2527                         speaker_incall_mic_vol = 30;
2528                 else if(speaker_incall_mic_vol < -22)
2529                         speaker_incall_mic_vol = -22;
2530                 if(earpiece_incall_vol>6)
2531                         earpiece_incall_vol = 6;
2532                 else if(earpiece_incall_vol<-21)
2533                         earpiece_incall_vol = -21;
2534
2535                 DBG("earpiece_incall_vol = %ddB \n",earpiece_incall_vol);
2536                 DBG("speaker_incall_mic_vol = %ddB \n",speaker_incall_mic_vol);
2537
2538                 vol = earpiece_incall_vol;
2539                 if(vol>=0){
2540                         wm8994_write(0x33,  0x0018);  //6dB
2541                         wm8994_write(0x31,  (((6-vol)/3)<<3)+(6-vol)/3);  //-21dB
2542                 }else{
2543                         wm8994_write(0x33,  0x0010);
2544                         wm8994_write(0x31,  (((-vol)/3)<<3)+(-vol)/3);  //-21dB
2545                 }
2546 #ifdef CONFIG_SND_INSIDE_EARPIECE
2547                 vol = speaker_incall_mic_vol;
2548                 if(vol<-16){
2549                         wm8994_write(0x1E,  0x0016);
2550                         wm8994_write(0x1A,  320+(vol+22)*10/15);
2551                 }else{
2552                         wm8994_write(0x1E,  0x0006);
2553                         wm8994_write(0x1A,  320+(vol+16)*10/15);
2554                 }
2555 #endif
2556 #ifdef CONFIG_SND_OUTSIDE_EARPIECE
2557                 vol = headset_incall_mic_vol;
2558                 if(vol<-16){
2559                         wm8994_write(0x1E,  0x0016);  //mic vol
2560                         wm8994_write(0x18,  320+(vol+22)*10/15);  //mic vol
2561                 }else{
2562                         wm8994_write(0x1E,  0x0006);  //mic vol
2563                         wm8994_write(0x18,  320+(vol+16)*10/15);  //mic vol
2564                 }
2565 #endif
2566                 break;
2567
2568         case wm8994_mainMIC_to_baseband_to_speakers:
2569                 if(speaker_incall_mic_vol > 30)
2570                         speaker_incall_mic_vol = 30;
2571                 else if(speaker_incall_mic_vol < -22)
2572                         speaker_incall_mic_vol = -22;
2573                 if(speaker_incall_vol > 12)
2574                         speaker_incall_vol = 12;
2575                 else if(speaker_incall_vol < -21)
2576                         speaker_incall_vol = -21;
2577
2578                 DBG("speaker_incall_vol = %ddB \n",speaker_incall_vol);
2579                 DBG("speaker_incall_mic_vol = %ddB \n",speaker_incall_mic_vol);
2580
2581                 vol = speaker_incall_mic_vol;
2582                 if(vol<-16){
2583                         wm8994_write(0x1E,  0x0016);
2584                         wm8994_write(0x1A,  320+(vol+22)*10/15);
2585                 }else{
2586                         wm8994_write(0x1E,  0x0006);
2587                         wm8994_write(0x1A,  320+(vol+16)*10/15);
2588                 }
2589                 vol = speaker_incall_vol;
2590                 if(vol<=0){
2591                         wm8994_write(0x31,  (((-vol)/3)<<3)+(-vol)/3);
2592                 }else if(vol <= 9){
2593                 //      wm8994_write(0x25,  ((vol*10/15)<<3)+vol*10/15);
2594                 }else{
2595                 //      wm8994_write(0x25,  0x003F);
2596                 }
2597                 break;
2598
2599         case wm8994_BT_baseband:
2600                 if(BT_incall_vol > 30)
2601                         BT_incall_vol = 30;
2602                 else if(BT_incall_vol < -16)
2603                         BT_incall_vol = -16;
2604                 if(BT_incall_mic_vol > 6)
2605                         BT_incall_mic_vol = 6;
2606                 else if(BT_incall_mic_vol < -57)
2607                         BT_incall_mic_vol = -57;
2608
2609                 DBG("BT_incall_mic_vol = %ddB \n",BT_incall_mic_vol);
2610                 DBG("BT_incall_vol = %ddB \n",BT_incall_vol);
2611
2612                 vol = BT_incall_mic_vol;
2613                 wm8994_write(0x20,  320+vol+57);
2614
2615                 vol = BT_incall_vol;
2616                 wm8994_write(0x19, 0x0500+(vol+16)*10/15);
2617                 break;
2618         default:
2619                 printk("route error !\n");
2620         }
2621
2622 }
2623
2624 void wm8994_codec_set_volume(unsigned char system_type,unsigned char volume)
2625 {
2626         DBG("%s:: system_type = %d volume = %d \n",__FUNCTION__,system_type,volume);
2627
2628         if(system_type == VOICE_CALL)
2629         {
2630                 if(volume <= call_maxvol)
2631                         call_vol=volume;
2632                 else{
2633                         printk("%s----%d::max value is 7\n",__FUNCTION__,__LINE__);
2634                         call_vol=call_maxvol;
2635                 }
2636                 if(wm8994_current_mode<=wm8994_mainMIC_to_baseband_to_speakers_and_record&&
2637                 wm8994_current_mode>=wm8994_handsetMIC_to_baseband_to_headset)
2638                         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
2639         }else if(system_type == BLUETOOTH_SCO){
2640                 if(volume <= BT_call_maxvol)
2641                         BT_call_vol = volume;
2642                 else{
2643                         printk("%s----%d::max value is 15\n",__FUNCTION__,__LINE__);
2644                         BT_call_vol = BT_call_maxvol;
2645                 }
2646                 if(wm8994_current_mode<null&&
2647                 wm8994_current_mode>=wm8994_BT_baseband)
2648                         wm8994_set_volume(wm8994_current_mode,BT_call_vol,BT_call_maxvol);
2649         }else{
2650                 return;
2651                 printk("%s----%d::system type error!\n",__FUNCTION__,__LINE__);
2652         }
2653 }
2654
2655 void wm8994_set_volume(unsigned char wm8994_mode,unsigned char volume,unsigned char max_volume)
2656 {
2657         unsigned short lvol=0,rvol=0;
2658
2659 //      DBG("%s::volume = %d \n",__FUNCTION__,volume);
2660
2661         if(volume>max_volume)volume=max_volume;
2662
2663         if(wm8994_mode == wm8994_handsetMIC_to_baseband_to_headset_and_record||
2664         wm8994_mode == wm8994_handsetMIC_to_baseband_to_headset||
2665         wm8994_mode == wm8994_mainMIC_to_baseband_to_headset)
2666         {
2667                 wm8994_read(0x001C, &lvol);
2668                 wm8994_read(0x001D, &rvol);
2669                 //HPOUT1L_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2670                 wm8994_write(0x001C, (lvol&~0x003f)|headset_vol_table[volume]);
2671                 //HPOUT1R_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2672                 wm8994_write(0x001D, (rvol&~0x003f)|headset_vol_table[volume]);
2673         }
2674         else if(wm8994_mode == wm8994_mainMIC_to_baseband_to_speakers_and_record||
2675         wm8994_mode == wm8994_mainMIC_to_baseband_to_speakers)
2676         {
2677                 wm8994_read(0x0026, &lvol);
2678                 wm8994_read(0x0027, &rvol);
2679                 //SPKOUTL_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2680                 wm8994_write(0x0026, (lvol&~0x003f)|speakers_vol_table[volume]);
2681                 //SPKOUTR_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2682                 wm8994_write(0x0027, (rvol&~0x003f)|speakers_vol_table[volume]);
2683         }
2684         else if(wm8994_mode == wm8994_mainMIC_to_baseband_to_earpiece||
2685         wm8994_mode == wm8994_mainMIC_to_baseband_to_earpiece_and_record)
2686         {
2687                 wm8994_read(0x0020, &lvol);
2688                 wm8994_read(0x0021, &rvol);
2689
2690                 //MIXOUTL_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2691                 wm8994_write(0x0020, (lvol&~0x003f)|earpiece_vol_table[volume]);
2692                 //MIXOUTR_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2693                 wm8994_write(0x0021, (rvol&~0x003f)|earpiece_vol_table[volume]);
2694         }
2695         else if(wm8994_mode == wm8994_BT_baseband||wm8994_mode==wm8994_BT_baseband_and_record)
2696         {
2697                 //bit 0~4 /-16.5dB to +30dB in 1.5dB steps
2698                 DBG("BT_vol_table[volume] = 0x%x\n",BT_vol_table[volume]);
2699                 wm8994_write(0x0500, BT_vol_table[volume]);
2700                 wm8994_write(0x0501, 0x0100);
2701         }
2702         else if(wm8994_mode == null)
2703         {
2704                 wm8994_read(0x001C, &lvol);
2705                 wm8994_read(0x001D, &rvol);
2706                 wm8994_write(0x001C, (lvol&~0x003f)|headset_vol_table[volume]);
2707                 wm8994_write(0x001D, (rvol&~0x003f)|headset_vol_table[volume]);
2708                 wm8994_read(0x0026, &lvol);
2709                 wm8994_read(0x0027, &rvol);
2710                 wm8994_write(0x0026, (lvol&~0x003f)|speakers_vol_table[volume]);
2711                 wm8994_write(0x0027, (rvol&~0x003f)|speakers_vol_table[volume]);
2712                 wm8994_read(0x0020, &lvol);
2713                 wm8994_read(0x0021, &rvol);
2714                 wm8994_write(0x0020, (lvol&~0x003f)|earpiece_vol_table[volume]);
2715                 wm8994_write(0x0021, (rvol&~0x003f)|earpiece_vol_table[volume]);
2716         }
2717 }
2718
2719 void wm8994_check_channel(void)
2720 {
2721         wm8994_codec_fnc_t **wm8994_fnc_ptr = wm8994_codec_sequence;
2722         unsigned char wm8994_mode = wm8994_current_mode;
2723
2724         DBG("%s--%d::Enter\n",__FUNCTION__,__LINE__);
2725
2726         isWM8994SetChannel = true;
2727
2728         if(wm8994_mode < wm8994_AP_to_headset ||
2729                 wm8994_mode > wm8994_BT_baseband_and_record)
2730         {
2731                 wm8994_mode = wm8994_recorder_and_AP_to_speakers;
2732                 printk("%s--%d--: Wm8994 set channel with null mode\n",__FUNCTION__,__LINE__);
2733         }
2734
2735         wm8994_fnc_ptr += wm8994_mode;
2736
2737         while(isSetChannelErr){
2738                 gpio_request(WM_EN_PIN, NULL);
2739                 gpio_direction_output(WM_EN_PIN,GPIO_LOW);
2740                 gpio_free(WM_EN_PIN);
2741
2742                 msleep(50);
2743
2744                 gpio_request(WM_EN_PIN, NULL);
2745                 gpio_direction_output(WM_EN_PIN,GPIO_HIGH);
2746                 gpio_free(WM_EN_PIN);
2747
2748                 msleep(50);
2749
2750                 wm8994_current_mode = null;
2751                 isSetChannelErr = false;
2752
2753                 (*wm8994_fnc_ptr)() ;
2754         }
2755
2756         isWM8994SetChannel = false;
2757
2758         DBG("%s--%d::Exit\n",__FUNCTION__,__LINE__);
2759 }
2760
2761 #define SOC_DOUBLE_SWITCH_WM8994CODEC(xname, route) \
2762 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2763         .info = snd_soc_info_route, \
2764         .get = snd_soc_get_route, .put = snd_soc_put_route, \
2765         .private_value = route }
2766
2767 int snd_soc_info_route(struct snd_kcontrol *kcontrol,
2768         struct snd_ctl_elem_info *uinfo)
2769 {
2770         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2771
2772         uinfo->count = 1;
2773         uinfo->value.integer.min = 0;
2774         uinfo->value.integer.max = 0;
2775         return 0;
2776 }
2777
2778 int snd_soc_get_route(struct snd_kcontrol *kcontrol,
2779         struct snd_ctl_elem_value *ucontrol)
2780 {
2781         return 0;
2782 }
2783
2784 int snd_soc_put_route(struct snd_kcontrol *kcontrol,
2785         struct snd_ctl_elem_value *ucontrol)
2786 {
2787         char route = kcontrol->private_value & 0xff;
2788
2789 #ifdef WM8994_PROC
2790         wm8994_current_route = route;
2791 #endif
2792         isWM8994SetChannel = true;
2793         switch(route)
2794         {
2795                 /* Speaker*/
2796                 case SPEAKER_NORMAL: //AP-> 8994Codec -> Speaker
2797                         recorder_and_AP_to_speakers();
2798                         break;
2799
2800                 case SPEAKER_INCALL: //BB-> 8994Codec -> Speaker
2801                         mainMIC_to_baseband_to_speakers();
2802                         break;
2803
2804                 /* Headset */
2805                 case HEADSET_NORMAL:    //AP-> 8994Codec -> Headset
2806                         recorder_and_AP_to_headset();
2807                         break;
2808                 case HEADSET_INCALL:    //AP-> 8994Codec -> Headset
2809                 //      if(isHSKey_MIC())
2810                                 handsetMIC_to_baseband_to_headset();
2811                 //      else
2812                 //              mainMIC_to_baseband_to_headset();
2813
2814                         break;
2815
2816                 /* Earpiece*/
2817                 case EARPIECE_INCALL:   //:BB-> 8994Codec -> EARPIECE
2818 //#ifdef CONFIG_SND_NO_EARPIECE
2819 //                      mainMIC_to_baseband_to_speakers();
2820 //#else
2821                         mainMIC_to_baseband_to_earpiece();
2822 //#endif
2823                         break;
2824
2825                 case EARPIECE_NORMAL:   //:BB-> 8994Codec -> EARPIECE
2826                         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset||
2827                         wm8994_mainMIC_to_baseband_to_headset)
2828                                 recorder_and_AP_to_headset();
2829                         else if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers||
2830                                 wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)
2831                                 recorder_and_AP_to_speakers();
2832                         else if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers||
2833                                 wm8994_current_mode==wm8994_recorder_and_AP_to_speakers)
2834                                 break;
2835                         else{
2836                                 recorder_and_AP_to_speakers();
2837                                 printk("%s--%d--: wm8994 with null mode\n",__FUNCTION__,__LINE__);
2838                         }
2839                         break;
2840
2841
2842                 /* BLUETOOTH_SCO*/
2843                 case BLUETOOTH_SCO_INCALL:      //BB-> 8994Codec -> BLUETOOTH_SCO
2844                         BT_baseband();
2845                         break;
2846
2847                 /* BLUETOOTH_A2DP*/
2848                 case BLUETOOTH_A2DP_NORMAL:     //AP-> 8994Codec -> BLUETOOTH_A2DP
2849                         break;
2850
2851                 case MIC_CAPTURE:
2852                         if(wm8994_current_mode==wm8994_AP_to_headset)
2853                                 recorder_and_AP_to_headset();
2854                         else if(wm8994_current_mode==wm8994_AP_to_speakers)
2855                                 recorder_and_AP_to_speakers();
2856                         else if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers||
2857                                 wm8994_current_mode==wm8994_recorder_and_AP_to_headset)
2858                                 break;
2859                         else{
2860                                 recorder_and_AP_to_speakers();
2861                                 printk("%s--%d--: wm8994 with null mode\n",__FUNCTION__,__LINE__);
2862                         }
2863                         break;
2864
2865                 case EARPIECE_RINGTONE:
2866                         recorder_and_AP_to_speakers();
2867                         break;
2868
2869                 case HEADSET_RINGTONE:
2870                         AP_to_speakers_and_headset();
2871                         break;
2872
2873                 case SPEAKER_RINGTONE:
2874                         recorder_and_AP_to_speakers();
2875                         break;
2876
2877                 default:
2878                         //codec_daout_route();
2879                         break;
2880         }
2881         wm8994_check_channel();
2882
2883         isWM8994SetChannel = false;
2884
2885         return 0;
2886 }
2887 /*
2888  * WM8994 Controls
2889  */
2890
2891 static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
2892 static const struct soc_enum bass_boost =
2893         SOC_ENUM_SINGLE(WM8994_BASS, 7, 2, bass_boost_txt);
2894
2895 static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
2896 static const struct soc_enum bass_filter =
2897         SOC_ENUM_SINGLE(WM8994_BASS, 6, 2, bass_filter_txt);
2898
2899 static const char *treble_txt[] = {"8kHz", "4kHz"};
2900 static const struct soc_enum treble =
2901         SOC_ENUM_SINGLE(WM8994_TREBLE, 6, 2, treble_txt);
2902
2903 static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
2904 static const struct soc_enum stereo_3d_lc =
2905         SOC_ENUM_SINGLE(WM8994_3D, 5, 2, stereo_3d_lc_txt);
2906
2907 static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
2908 static const struct soc_enum stereo_3d_uc =
2909         SOC_ENUM_SINGLE(WM8994_3D, 6, 2, stereo_3d_uc_txt);
2910
2911 static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
2912 static const struct soc_enum stereo_3d_func =
2913         SOC_ENUM_SINGLE(WM8994_3D, 7, 2, stereo_3d_func_txt);
2914
2915 static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
2916 static const struct soc_enum alc_func =
2917         SOC_ENUM_SINGLE(WM8994_ALC1, 7, 4, alc_func_txt);
2918
2919 static const char *ng_type_txt[] = {"Constant PGA Gain",
2920                                     "Mute ADC Output"};
2921 static const struct soc_enum ng_type =
2922         SOC_ENUM_SINGLE(WM8994_NGATE, 1, 2, ng_type_txt);
2923
2924 static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
2925 static const struct soc_enum deemph =
2926         SOC_ENUM_SINGLE(WM8994_ADCDAC, 1, 4, deemph_txt);
2927
2928 static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
2929                                    "L + R Invert"};
2930 static const struct soc_enum adcpol =
2931         SOC_ENUM_SINGLE(WM8994_ADCDAC, 5, 4, adcpol_txt);
2932
2933 static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
2934 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
2935 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
2936 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
2937 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
2938
2939 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
2940
2941 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker incall Switch", SPEAKER_INCALL),
2942 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker normal Switch", SPEAKER_NORMAL),
2943
2944 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece incall Switch", EARPIECE_INCALL),
2945 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece normal Switch", EARPIECE_NORMAL),
2946
2947 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset incall Switch", HEADSET_INCALL),
2948 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset normal Switch", HEADSET_NORMAL),
2949
2950 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth incall Switch", BLUETOOTH_SCO_INCALL),
2951 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth normal Switch", BLUETOOTH_SCO_NORMAL),
2952
2953 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP incall Switch", BLUETOOTH_A2DP_INCALL),
2954 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP normal Switch", BLUETOOTH_A2DP_NORMAL),
2955
2956 SOC_DOUBLE_SWITCH_WM8994CODEC("Capture Switch", MIC_CAPTURE),
2957
2958 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece ringtone Switch",EARPIECE_RINGTONE),
2959 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker ringtone Switch",SPEAKER_RINGTONE),
2960 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset ringtone Switch",HEADSET_RINGTONE),
2961 };
2962
2963 /*
2964  * DAPM Controls
2965  */
2966
2967 static int wm8994_lrc_control(struct snd_soc_dapm_widget *w,
2968                               struct snd_kcontrol *kcontrol, int event)
2969 {
2970         return 0;
2971 }
2972
2973 static const char *wm8994_line_texts[] = {
2974         "Line 1", "Line 2", "PGA", "Differential"};
2975
2976 static const unsigned int wm8994_line_values[] = {
2977         0, 1, 3, 4};
2978
2979 static const struct soc_enum wm8994_lline_enum =
2980         SOC_VALUE_ENUM_SINGLE(WM8994_LOUTM1, 0, 7,
2981                               ARRAY_SIZE(wm8994_line_texts),
2982                               wm8994_line_texts,
2983                               wm8994_line_values);
2984 static const struct snd_kcontrol_new wm8994_left_line_controls =
2985         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
2986
2987 static const struct soc_enum wm8994_rline_enum =
2988         SOC_VALUE_ENUM_SINGLE(WM8994_ROUTM1, 0, 7,
2989                               ARRAY_SIZE(wm8994_line_texts),
2990                               wm8994_line_texts,
2991                               wm8994_line_values);
2992 static const struct snd_kcontrol_new wm8994_right_line_controls =
2993         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
2994
2995 /* Left Mixer */
2996 static const struct snd_kcontrol_new wm8994_left_mixer_controls[] = {
2997         SOC_DAPM_SINGLE("Playback Switch", WM8994_LOUTM1, 8, 1, 0),
2998         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_LOUTM1, 7, 1, 0),
2999         SOC_DAPM_SINGLE("Right Playback Switch", WM8994_LOUTM2, 8, 1, 0),
3000         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_LOUTM2, 7, 1, 0),
3001 };
3002
3003 /* Right Mixer */
3004 static const struct snd_kcontrol_new wm8994_right_mixer_controls[] = {
3005         SOC_DAPM_SINGLE("Left Playback Switch", WM8994_ROUTM1, 8, 1, 0),
3006         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_ROUTM1, 7, 1, 0),
3007         SOC_DAPM_SINGLE("Playback Switch", WM8994_ROUTM2, 8, 1, 0),
3008         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_ROUTM2, 7, 1, 0),
3009 };
3010
3011 static const char *wm8994_pga_sel[] = {"Line 1", "Line 2", "Differential"};
3012 static const unsigned int wm8994_pga_val[] = { 0, 1, 3 };
3013
3014 /* Left PGA Mux */
3015 static const struct soc_enum wm8994_lpga_enum =
3016         SOC_VALUE_ENUM_SINGLE(WM8994_LADCIN, 6, 3,
3017                               ARRAY_SIZE(wm8994_pga_sel),
3018                               wm8994_pga_sel,
3019                               wm8994_pga_val);
3020 static const struct snd_kcontrol_new wm8994_left_pga_controls =
3021         SOC_DAPM_VALUE_ENUM("Route", wm8994_lpga_enum);
3022
3023 /* Right PGA Mux */
3024 static const struct soc_enum wm8994_rpga_enum =
3025         SOC_VALUE_ENUM_SINGLE(WM8994_RADCIN, 6, 3,
3026                               ARRAY_SIZE(wm8994_pga_sel),
3027                               wm8994_pga_sel,
3028                               wm8994_pga_val);
3029 static const struct snd_kcontrol_new wm8994_right_pga_controls =
3030         SOC_DAPM_VALUE_ENUM("Route", wm8994_rpga_enum);
3031
3032 /* Differential Mux */
3033 static const char *wm8994_diff_sel[] = {"Line 1", "Line 2"};
3034 static const struct soc_enum diffmux =
3035         SOC_ENUM_SINGLE(WM8994_ADCIN, 8, 2, wm8994_diff_sel);
3036 static const struct snd_kcontrol_new wm8994_diffmux_controls =
3037         SOC_DAPM_ENUM("Route", diffmux);
3038
3039 /* Mono ADC Mux */
3040 static const char *wm8994_mono_mux[] = {"Stereo", "Mono (Left)",
3041         "Mono (Right)", "Digital Mono"};
3042 static const struct soc_enum monomux =
3043         SOC_ENUM_SINGLE(WM8994_ADCIN, 6, 4, wm8994_mono_mux);
3044 static const struct snd_kcontrol_new wm8994_monomux_controls =
3045         SOC_DAPM_ENUM("Route", monomux);
3046
3047 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
3048         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8994_PWR1, 1, 0),
3049
3050         SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
3051                 &wm8994_diffmux_controls),
3052         SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
3053                 &wm8994_monomux_controls),
3054         SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
3055                 &wm8994_monomux_controls),
3056
3057         SND_SOC_DAPM_MUX("Left PGA Mux", WM8994_PWR1, 5, 0,
3058                 &wm8994_left_pga_controls),
3059         SND_SOC_DAPM_MUX("Right PGA Mux", WM8994_PWR1, 4, 0,
3060                 &wm8994_right_pga_controls),
3061
3062         SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
3063                 &wm8994_left_line_controls),
3064         SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
3065                 &wm8994_right_line_controls),
3066
3067         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8994_PWR1, 2, 0),
3068         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8994_PWR1, 3, 0),
3069
3070         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8994_PWR2, 7, 0),
3071         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8994_PWR2, 8, 0),
3072
3073         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
3074                 &wm8994_left_mixer_controls[0],
3075                 ARRAY_SIZE(wm8994_left_mixer_controls)),
3076         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
3077                 &wm8994_right_mixer_controls[0],
3078                 ARRAY_SIZE(wm8994_right_mixer_controls)),
3079
3080         SND_SOC_DAPM_PGA("Right Out 2", WM8994_PWR2, 3, 0, NULL, 0),
3081         SND_SOC_DAPM_PGA("Left Out 2", WM8994_PWR2, 4, 0, NULL, 0),
3082         SND_SOC_DAPM_PGA("Right Out 1", WM8994_PWR2, 5, 0, NULL, 0),
3083         SND_SOC_DAPM_PGA("Left Out 1", WM8994_PWR2, 6, 0, NULL, 0),
3084
3085         SND_SOC_DAPM_POST("LRC control", wm8994_lrc_control),
3086
3087         SND_SOC_DAPM_OUTPUT("LOUT1"),
3088         SND_SOC_DAPM_OUTPUT("ROUT1"),
3089         SND_SOC_DAPM_OUTPUT("LOUT2"),
3090         SND_SOC_DAPM_OUTPUT("ROUT2"),
3091         SND_SOC_DAPM_OUTPUT("VREF"),
3092
3093         SND_SOC_DAPM_INPUT("LINPUT1"),
3094         SND_SOC_DAPM_INPUT("LINPUT2"),
3095         SND_SOC_DAPM_INPUT("RINPUT1"),
3096         SND_SOC_DAPM_INPUT("RINPUT2"),
3097 };
3098
3099 static const struct snd_soc_dapm_route audio_map[] = {
3100
3101         { "Left Line Mux", "Line 1", "LINPUT1" },
3102         { "Left Line Mux", "Line 2", "LINPUT2" },
3103         { "Left Line Mux", "PGA", "Left PGA Mux" },
3104         { "Left Line Mux", "Differential", "Differential Mux" },
3105
3106         { "Right Line Mux", "Line 1", "RINPUT1" },
3107         { "Right Line Mux", "Line 2", "RINPUT2" },
3108         { "Right Line Mux", "PGA", "Right PGA Mux" },
3109         { "Right Line Mux", "Differential", "Differential Mux" },
3110
3111         { "Left PGA Mux", "Line 1", "LINPUT1" },
3112         { "Left PGA Mux", "Line 2", "LINPUT2" },
3113         { "Left PGA Mux", "Differential", "Differential Mux" },
3114
3115         { "Right PGA Mux", "Line 1", "RINPUT1" },
3116         { "Right PGA Mux", "Line 2", "RINPUT2" },
3117         { "Right PGA Mux", "Differential", "Differential Mux" },
3118
3119         { "Differential Mux", "Line 1", "LINPUT1" },
3120         { "Differential Mux", "Line 1", "RINPUT1" },
3121         { "Differential Mux", "Line 2", "LINPUT2" },
3122         { "Differential Mux", "Line 2", "RINPUT2" },
3123
3124         { "Left ADC Mux", "Stereo", "Left PGA Mux" },
3125         { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
3126         { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
3127
3128         { "Right ADC Mux", "Stereo", "Right PGA Mux" },
3129         { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
3130         { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
3131
3132         { "Left ADC", NULL, "Left ADC Mux" },
3133         { "Right ADC", NULL, "Right ADC Mux" },
3134
3135         { "Left Line Mux", "Line 1", "LINPUT1" },
3136         { "Left Line Mux", "Line 2", "LINPUT2" },
3137         { "Left Line Mux", "PGA", "Left PGA Mux" },
3138         { "Left Line Mux", "Differential", "Differential Mux" },
3139
3140         { "Right Line Mux", "Line 1", "RINPUT1" },
3141         { "Right Line Mux", "Line 2", "RINPUT2" },
3142         { "Right Line Mux", "PGA", "Right PGA Mux" },
3143         { "Right Line Mux", "Differential", "Differential Mux" },
3144
3145         { "Left Mixer", "Playback Switch", "Left DAC" },
3146         { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
3147         { "Left Mixer", "Right Playback Switch", "Right DAC" },
3148         { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
3149
3150         { "Right Mixer", "Left Playback Switch", "Left DAC" },
3151         { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
3152         { "Right Mixer", "Playback Switch", "Right DAC" },
3153         { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
3154
3155         { "Left Out 1", NULL, "Left Mixer" },
3156         { "LOUT1", NULL, "Left Out 1" },
3157         { "Right Out 1", NULL, "Right Mixer" },
3158         { "ROUT1", NULL, "Right Out 1" },
3159
3160         { "Left Out 2", NULL, "Left Mixer" },
3161         { "LOUT2", NULL, "Left Out 2" },
3162         { "Right Out 2", NULL, "Right Mixer" },
3163         { "ROUT2", NULL, "Right Out 2" },
3164 };
3165
3166 struct _coeff_div {
3167         u32 mclk;
3168         u32 rate;
3169         u16 fs;
3170         u8 sr:5;
3171         u8 usb:1;
3172 };
3173
3174 /* codec hifi mclk clock divider coefficients */
3175 static const struct _coeff_div coeff_div[] = {
3176         /* 8k */
3177         {12288000, 8000, 1536, 0x6, 0x0},
3178         {11289600, 8000, 1408, 0x16, 0x0},
3179         {18432000, 8000, 2304, 0x7, 0x0},
3180         {16934400, 8000, 2112, 0x17, 0x0},
3181         {12000000, 8000, 1500, 0x6, 0x1},
3182
3183         /* 11.025k */
3184         {11289600, 11025, 1024, 0x18, 0x0},
3185         {16934400, 11025, 1536, 0x19, 0x0},
3186         {12000000, 11025, 1088, 0x19, 0x1},
3187
3188         /* 16k */
3189         {12288000, 16000, 768, 0xa, 0x0},
3190         {18432000, 16000, 1152, 0xb, 0x0},
3191         {12000000, 16000, 750, 0xa, 0x1},
3192
3193         /* 22.05k */
3194         {11289600, 22050, 512, 0x1a, 0x0},
3195         {16934400, 22050, 768, 0x1b, 0x0},
3196         {12000000, 22050, 544, 0x1b, 0x1},
3197
3198         /* 32k */
3199         {12288000, 32000, 384, 0xc, 0x0},
3200         {18432000, 32000, 576, 0xd, 0x0},
3201         {12000000, 32000, 375, 0xa, 0x1},
3202
3203         /* 44.1k */
3204         {11289600, 44100, 256, 0x10, 0x0},
3205         {16934400, 44100, 384, 0x11, 0x0},
3206         {12000000, 44100, 272, 0x11, 0x1},
3207
3208         /* 48k */
3209         {12288000, 48000, 256, 0x0, 0x0},
3210         {18432000, 48000, 384, 0x1, 0x0},
3211         {12000000, 48000, 250, 0x0, 0x1},
3212
3213         /* 88.2k */
3214         {11289600, 88200, 128, 0x1e, 0x0},
3215         {16934400, 88200, 192, 0x1f, 0x0},
3216         {12000000, 88200, 136, 0x1f, 0x1},
3217
3218         /* 96k */
3219         {12288000, 96000, 128, 0xe, 0x0},
3220         {18432000, 96000, 192, 0xf, 0x0},
3221         {12000000, 96000, 125, 0xe, 0x1},
3222 };
3223
3224
3225 static inline int get_coeff(int mclk, int rate)
3226 {
3227         int i;
3228
3229         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
3230                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
3231                         return i;
3232         }
3233
3234         return -EINVAL;
3235 }
3236
3237 /* The set of rates we can generate from the above for each SYSCLK */
3238
3239 static unsigned int rates_12288[] = {
3240         8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
3241 };
3242
3243 static struct snd_pcm_hw_constraint_list constraints_12288 = {
3244         .count  = ARRAY_SIZE(rates_12288),
3245         .list   = rates_12288,
3246 };
3247
3248 static unsigned int rates_112896[] = {
3249         8000, 11025, 22050, 44100,
3250 };
3251
3252 static struct snd_pcm_hw_constraint_list constraints_112896 = {
3253         .count  = ARRAY_SIZE(rates_112896),
3254         .list   = rates_112896,
3255 };
3256
3257 static unsigned int rates_12[] = {
3258         8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
3259         48000, 88235, 96000,
3260 };
3261
3262 static struct snd_pcm_hw_constraint_list constraints_12 = {
3263         .count  = ARRAY_SIZE(rates_12),
3264         .list   = rates_12,
3265 };
3266
3267 /*
3268  * Note that this should be called from init rather than from hw_params.
3269  */
3270 static int wm8994_set_dai_sysclk(struct snd_soc_dai *codec_dai,
3271                 int clk_id, unsigned int freq, int dir)
3272 {
3273         struct snd_soc_codec *codec = codec_dai->codec;
3274         struct wm8994_priv *wm8994 = codec->private_data;
3275
3276         DBG("%s----%d\n",__FUNCTION__,__LINE__);
3277
3278         switch (freq) {
3279         case 11289600:
3280         case 18432000:
3281         case 22579200:
3282         case 36864000:
3283                 wm8994->sysclk_constraints = &constraints_112896;
3284                 wm8994->sysclk = freq;
3285                 return 0;
3286
3287         case 12288000:
3288         case 16934400:
3289         case 24576000:
3290         case 33868800:
3291                 wm8994->sysclk_constraints = &constraints_12288;
3292                 wm8994->sysclk = freq;
3293                 return 0;
3294
3295         case 12000000:
3296         case 24000000:
3297                 wm8994->sysclk_constraints = &constraints_12;
3298                 wm8994->sysclk = freq;
3299                 return 0;
3300         }
3301         return -EINVAL;
3302 }
3303
3304 static int wm8994_set_dai_fmt(struct snd_soc_dai *codec_dai,
3305                 unsigned int fmt)
3306 {
3307         return 0;
3308 }
3309
3310 static int wm8994_pcm_startup(struct snd_pcm_substream *substream,
3311                               struct snd_soc_dai *dai)
3312 {
3313         struct snd_soc_codec *codec = dai->codec;
3314         struct wm8994_priv *wm8994 = codec->private_data;
3315
3316         /* The set of sample rates that can be supported depends on the
3317          * MCLK supplied to the CODEC - enforce this.
3318          */
3319
3320         if (!wm8994->sysclk) {
3321                 dev_err(codec->dev,
3322                         "No MCLK configured, call set_sysclk() on init\n");
3323                 return -EINVAL;
3324         }
3325
3326         snd_pcm_hw_constraint_list(substream->runtime, 0,
3327                                    SNDRV_PCM_HW_PARAM_RATE,
3328                                    wm8994->sysclk_constraints);
3329
3330         return 0;
3331 }
3332
3333 static int wm8994_pcm_hw_params(struct snd_pcm_substream *substream,
3334                                 struct snd_pcm_hw_params *params,
3335                                 struct snd_soc_dai *dai)
3336 {
3337         struct snd_soc_pcm_runtime *rtd = substream->private_data;
3338         struct snd_soc_device *socdev = rtd->socdev;
3339         struct snd_soc_codec *codec = socdev->card->codec;
3340         struct wm8994_priv *wm8994 = codec->private_data;
3341         int coeff;
3342
3343         coeff = get_coeff(wm8994->sysclk, params_rate(params));
3344         if (coeff < 0) {
3345                 coeff = get_coeff(wm8994->sysclk / 2, params_rate(params));
3346         }
3347         if (coeff < 0) {
3348                 dev_err(codec->dev,
3349                         "Unable to configure sample rate %dHz with %dHz MCLK\n",
3350                         params_rate(params), wm8994->sysclk);
3351                 return coeff;
3352         }
3353         params_format(params);
3354
3355         return 0;
3356 }
3357
3358 static int wm8994_mute(struct snd_soc_dai *dai, int mute)
3359 {
3360         return 0;
3361 }
3362
3363 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
3364                                  enum snd_soc_bias_level level)
3365 {
3366
3367         codec->bias_level = level;
3368         return 0;
3369 }
3370
3371 #define WM8994_RATES SNDRV_PCM_RATE_48000
3372
3373 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3374         SNDRV_PCM_FMTBIT_S24_LE)
3375
3376 static struct snd_soc_dai_ops wm8994_ops = {
3377         .startup = wm8994_pcm_startup,
3378         .hw_params = wm8994_pcm_hw_params,
3379         .set_fmt = wm8994_set_dai_fmt,
3380         .set_sysclk = wm8994_set_dai_sysclk,
3381         .digital_mute = wm8994_mute,
3382         /*add by qiuen for volume*/
3383         .set_volume = wm8994_codec_set_volume,
3384 };
3385
3386 struct snd_soc_dai wm8994_dai = {
3387         .name = "WM8994",
3388         .playback = {
3389                 .stream_name = "Playback",
3390                 .channels_min = 1,
3391                 .channels_max = 2,
3392                 .rates = WM8994_RATES,
3393                 .formats = WM8994_FORMATS,
3394         },
3395         .capture = {
3396                 .stream_name = "Capture",
3397                 .channels_min = 2,
3398                 .channels_max = 2,
3399                 .rates = WM8994_RATES,
3400                 .formats = WM8994_FORMATS,
3401          },
3402         .ops = &wm8994_ops,
3403         .symmetric_rates = 1,
3404 };
3405 EXPORT_SYMBOL_GPL(wm8994_dai);
3406
3407 static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
3408 {
3409         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3410         struct snd_soc_codec *codec = socdev->card->codec;
3411
3412         isWM8994SetChannel = true;
3413         wm8994_set_bias_level(codec,SND_SOC_BIAS_OFF);
3414         wm8994_write(0x00, 0x00);
3415         msleep(50);
3416
3417         gpio_request(WM_EN_PIN, NULL);
3418         gpio_direction_output(WM_EN_PIN,GPIO_LOW);
3419         gpio_free(WM_EN_PIN);
3420
3421         msleep(50);
3422
3423         return 0;
3424 }
3425
3426 static int wm8994_resume(struct platform_device *pdev)
3427 {
3428         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3429         struct snd_soc_codec *codec = socdev->card->codec;
3430         wm8994_codec_fnc_t **wm8994_fnc_ptr = wm8994_codec_sequence;
3431         unsigned char wm8994_resume_mode = wm8994_current_mode;
3432         wm8994_current_mode = null;
3433
3434         gpio_request(WM_EN_PIN, NULL);
3435         gpio_direction_output(WM_EN_PIN,GPIO_HIGH);
3436         gpio_free(WM_EN_PIN);
3437
3438         msleep(50);
3439
3440         wm8994_set_bias_level(codec,SND_SOC_BIAS_STANDBY);
3441         if(wm8994_resume_mode == wm8994_recorder_and_AP_to_speakers ||
3442         wm8994_resume_mode == wm8994_recorder_and_AP_to_headset)
3443         {
3444                 DBG("wm8994 resume\n");
3445         }
3446         else if(wm8994_resume_mode > wm8994_BT_baseband_and_record)
3447         {
3448                 wm8994_resume_mode = wm8994_recorder_and_AP_to_speakers;
3449                 printk("%s--%d--: Wm8994 resume with null mode\n",__FUNCTION__,__LINE__);
3450         }
3451         else
3452                 printk("%s--%d--: Wm8994 resume with error mode\n",__FUNCTION__,__LINE__);
3453
3454         wm8994_fnc_ptr += wm8994_resume_mode;
3455         (*wm8994_fnc_ptr)() ;
3456
3457         wm8994_check_channel();
3458
3459         isWM8994SetChannel = false;
3460         return 0;
3461 }
3462
3463 static struct snd_soc_codec *wm8994_codec;
3464
3465 #ifdef WM8994_PROC
3466 static ssize_t wm8994_proc_write(struct file *file, const char __user *buffer,
3467                            unsigned long len, void *data)
3468 {
3469         char *cookie_pot;
3470         char *p;
3471         int reg;
3472         int value;
3473
3474         char procadd = 0;
3475         unsigned short eqvol;
3476         unsigned char wm8994_proc_mode;
3477         wm8994_codec_fnc_t **wm8994_fnc_ptr = wm8994_codec_sequence;
3478
3479         cookie_pot = (char *)vmalloc( len );
3480         if (!cookie_pot)
3481         {
3482                 return -ENOMEM;
3483         }
3484         else
3485         {
3486                 if (copy_from_user( cookie_pot, buffer, len ))
3487                         return -EFAULT;
3488         }
3489
3490         switch(cookie_pot[0])
3491         {
3492         case 'n':
3493         case 'N':
3494                 if(*(cookie_pot+1)=='+'){
3495                         procadd = 3;
3496                 }else if(*(cookie_pot+1)=='-'){
3497                         procadd = -3;
3498                 }else{
3499                         printk("Please press '+' or '-' follow 'n'!\n");
3500                         return -1;
3501                 }
3502                 switch(wm8994_current_route){
3503                 case HEADSET_NORMAL:
3504                         if(procadd == 3)
3505                                 headset_normal_vol += 3;
3506                         else
3507                                 headset_normal_vol -= 3;
3508
3509                         if(headset_normal_vol > 6)
3510                                 headset_normal_vol = 6;
3511                         else if(headset_normal_vol < -57)
3512                                 headset_normal_vol = -57;
3513
3514                         printk("headset_normal_vol = %ddB \n",headset_normal_vol);
3515                         break;
3516
3517                 case SPEAKER_NORMAL:
3518                 case EARPIECE_NORMAL:
3519                 case SPEAKER_RINGTONE:
3520                 case EARPIECE_RINGTONE:
3521                 case BLUETOOTH_SCO_INCALL:
3522                         if(procadd == 3)
3523                                 speaker_normal_vol += 3;
3524                         else
3525                                 speaker_normal_vol -= 3;
3526
3527                         if(speaker_normal_vol > 6)
3528                                 speaker_normal_vol = 6;
3529                         else if(speaker_normal_vol < -57)
3530                                 speaker_normal_vol = -57;
3531
3532                         printk("speaker_normal_vol = %ddB \n",speaker_normal_vol);
3533                         break;
3534
3535                 case HEADSET_RINGTONE:
3536                         if(procadd == 3){
3537                                 headset_normal_vol += 3;
3538                                 speaker_normal_vol += 3;
3539                         }else{
3540                                 headset_normal_vol -= 3;
3541                                 speaker_normal_vol -= 3;
3542                         }
3543
3544                         if(speaker_normal_vol > 6)
3545                                 speaker_normal_vol = 6;
3546                         else if(speaker_normal_vol < -57)
3547                                 speaker_normal_vol = -57;
3548                         if(headset_normal_vol > 6)
3549                                 headset_normal_vol = 6;
3550                         else if(headset_normal_vol < -57)
3551                                 headset_normal_vol = -57;
3552
3553                         printk("headset_normal_vol = %ddB \n",headset_normal_vol);
3554                         printk("speaker_normal_vol = %ddB \n",speaker_normal_vol);
3555                         break;
3556
3557                 default:
3558                         printk("Current channel does not match to normal mode!\n");
3559                         return -1;
3560                 }
3561                 break;
3562         case 'i':
3563         case 'I':
3564                 if(*(cookie_pot+1)=='+'){
3565                         procadd = 3;
3566                 }else if(*(cookie_pot+1)=='-'){
3567                         procadd = -3;
3568                 }else{
3569                         printk("Please press '+' or '-' follow 'i'!\n");
3570                         return -1;
3571                 }
3572
3573                 switch(wm8994_current_route){
3574                 case HEADSET_INCALL:
3575                         if(procadd == 3)
3576                                 headset_incall_vol += 3;
3577                         else
3578                                 headset_incall_vol -= 3;
3579
3580                         if(headset_incall_vol > 6)
3581                                 headset_incall_vol = 6;
3582                         else if(headset_incall_vol < -12)
3583                                 headset_incall_vol = -12;
3584
3585                         printk("headset_incall_vol = %ddB \n",headset_incall_vol);
3586                         break;
3587
3588                 case EARPIECE_INCALL:
3589                         if(procadd == 3)
3590                                 earpiece_incall_vol += 3;
3591                         else
3592                                 earpiece_incall_vol -= 3;
3593
3594                         if(earpiece_incall_vol>6)
3595                                 earpiece_incall_vol = 6;
3596                         else if(earpiece_incall_vol<-21)
3597                                 earpiece_incall_vol = -21;
3598
3599                         printk("earpiece_incall_vol = %ddB \n",earpiece_incall_vol);
3600                         break;
3601
3602                 case SPEAKER_INCALL:
3603                         if(procadd == 3)
3604                                 speaker_incall_vol += 3;
3605                         else
3606                                 speaker_incall_vol -= 3;
3607
3608                         if(speaker_incall_vol > 12)
3609                                 speaker_incall_vol = 12;
3610                         else if(speaker_incall_vol < -21)
3611                                 speaker_incall_vol = -21;
3612
3613                         printk("speaker_incall_vol = %ddB \n",speaker_incall_vol);
3614                         break;
3615
3616                 case BLUETOOTH_SCO_INCALL:
3617                         if(procadd == 3)
3618                                 BT_incall_vol += 3;
3619                         else
3620                                 BT_incall_vol -= 3;
3621
3622                         if(BT_incall_vol > 30)
3623                                 BT_incall_vol = 30;
3624                         else if(BT_incall_vol < -16)
3625                                 BT_incall_vol = -16;
3626
3627                         printk("BT_incall_vol = %ddB \n",BT_incall_vol);
3628                         break;
3629
3630                 default:
3631                         printk("Current channel does not match to incall mode!\n");
3632                         return -1;
3633                 }
3634                 break;
3635         case 'm':
3636         case 'M':
3637                 if(*(cookie_pot+1)=='+'){
3638                         procadd = 3;
3639                 }else if(*(cookie_pot+1)=='-'){
3640                         procadd = -3;
3641                 }else{
3642                         printk("Please press '+' or '-' follow 'm'!\n");
3643                         return -1;
3644                 }
3645                 switch(wm8994_current_route){
3646                 case HEADSET_INCALL:
3647                         if(procadd == 3)
3648                                 headset_incall_mic_vol += 3;
3649                         else
3650                                 headset_incall_mic_vol -= 3;
3651
3652                         if(speaker_incall_mic_vol > 30)
3653                                 speaker_incall_mic_vol = 30;
3654                         else if(speaker_incall_mic_vol < -22)
3655                                 speaker_incall_mic_vol = -22;
3656
3657                         printk("speaker_incall_mic_vol = %ddB \n",speaker_incall_mic_vol);
3658                         break;
3659
3660                 case EARPIECE_INCALL:
3661                         if(procadd == 3)
3662                                 speaker_incall_mic_vol += 3;
3663                         else
3664                                 speaker_incall_mic_vol -= 3;
3665
3666                         if(speaker_incall_mic_vol > 30)
3667                                 speaker_incall_mic_vol = 30;
3668                         else if(speaker_incall_mic_vol < -22)
3669                                 speaker_incall_mic_vol = -22;
3670
3671                         printk("speaker_incall_mic_vol = %ddB \n",speaker_incall_mic_vol);
3672                         break;
3673
3674                 case SPEAKER_INCALL:
3675                         if(procadd == 3)
3676                                 speaker_incall_mic_vol += 3;
3677                         else
3678                                 speaker_incall_mic_vol -= 3;
3679
3680                         if(speaker_incall_mic_vol > 30)
3681                                 speaker_incall_mic_vol = 30;
3682                         else if(speaker_incall_mic_vol < -22)
3683                                 speaker_incall_mic_vol = -22;
3684
3685                         printk("speaker_incall_mic_vol = %ddB \n",speaker_incall_mic_vol);
3686                         break;
3687
3688                 case BLUETOOTH_SCO_INCALL:
3689                         if(procadd == 3)
3690                                 BT_incall_mic_vol += 3;
3691                         else
3692                                 BT_incall_mic_vol -= 3;
3693
3694                         if(BT_incall_mic_vol > 6)
3695                                 BT_incall_mic_vol = 6;
3696                         else if(BT_incall_mic_vol < -57)
3697                                 BT_incall_mic_vol = -57;
3698
3699                         printk("BT_incall_mic_vol = %ddB \n",BT_incall_mic_vol);
3700                         break;
3701
3702                 case MIC_CAPTURE:
3703                         if(procadd == 3)
3704                                 recorder_vol += 3;
3705                         else
3706                                 recorder_vol -= 3;
3707
3708                         if(recorder_vol > 60)
3709                                 recorder_vol = 60;
3710                         else if(recorder_vol < -16)
3711                                 recorder_vol = -16;
3712
3713                         printk("recorder_vol = %ddB \n",recorder_vol);
3714                         break;
3715
3716                 default:
3717                         printk("Current channel does not match to mic mode!\n");
3718                         return -1;
3719                 }
3720                 break;
3721         case 'l':
3722         case 'L':
3723                 {
3724                 printk("headset_normal_vol = %ddB \n",headset_normal_vol);
3725                 printk("speaker_normal_vol = %ddB \n",speaker_normal_vol);
3726                 printk("headset_incall_vol = %ddB \n",headset_incall_vol);
3727                 printk("earpiece_incall_vol = %ddB \n",earpiece_incall_vol);
3728                 printk("speaker_incall_vol = %ddB \n",speaker_incall_vol);
3729                 printk("BT_incall_vol = %ddB \n",BT_incall_vol);
3730                 printk("headset_incall_mic_vol = %ddB \n",headset_incall_mic_vol);
3731                 printk("speaker_incall_mic_vol = %ddB \n",speaker_incall_mic_vol);
3732                 printk("BT_incall_mic_vol = %ddB \n",BT_incall_mic_vol);
3733                 printk("recorder_vol = %ddB \n",recorder_vol);
3734                 printk("bank_vol[1] = %ddB \n",bank_vol[1]);
3735                 printk("bank_vol[2] = %ddB \n",bank_vol[2]);
3736                 printk("bank_vol[3] = %ddB \n",bank_vol[3]);
3737                 printk("bank_vol[4] = %ddB \n",bank_vol[4]);
3738                 printk("bank_vol[5] = %ddB \n",bank_vol[5]);
3739                 }
3740                 return 0;
3741                 break;
3742         case 'c':
3743         case 'C':
3744                 if(((*(cookie_pot+1) == 't') || (*(cookie_pot+1) == 'T')) &&
3745                 ((*(cookie_pot+2) == 'a') || (*(cookie_pot+2) == 'A'))){
3746                         if(earpiece_vol_table[5] == 0x013D){
3747                                 earpiece_vol_table[0] = 0x0127;//for cta
3748                                 earpiece_vol_table[1] = 0x012D;
3749                                 earpiece_vol_table[2] = 0x0130;
3750                                 earpiece_vol_table[3] = 0x0135;
3751                                 earpiece_vol_table[4] = 0x0137;
3752                                 earpiece_vol_table[5] = 0x0135;
3753                                 printk("CTA on,earpiece table value is:0x0127,0x012D,0x0130,0x0135,0x0137,0x0135\n");
3754                         }
3755                         return 0;
3756                         break;
3757                 }
3758                 isWM8994SetChannel = true;
3759                 if(*(cookie_pot+1) == '+'){
3760                         wm8994_proc_mode = wm8994_current_mode+1;
3761
3762                         if(wm8994_proc_mode > wm8994_BT_baseband)
3763                                 wm8994_proc_mode = wm8994_AP_to_headset;
3764                 }else if(*(cookie_pot+1) == '-'){
3765                         wm8994_proc_mode = wm8994_current_mode-1;
3766
3767                         if(wm8994_proc_mode == null || wm8994_proc_mode > wm8994_BT_baseband)
3768                                 wm8994_proc_mode = wm8994_BT_baseband;
3769                 }else{
3770                         wm8994_proc_mode = wm8994_current_mode;
3771                         wm8994_current_mode = null;
3772                 }
3773
3774                 wm8994_fnc_ptr += wm8994_proc_mode;
3775                 (*wm8994_fnc_ptr)();
3776                 isWM8994SetChannel = false;
3777                 return 0;
3778                 break;
3779         case 'e':
3780         case 'E':
3781                 if(*(cookie_pot+1)=='+'){
3782                         procadd = 3;
3783                 }else if(*(cookie_pot+1)=='-'){
3784                         procadd = -3;
3785                 }else if(*(cookie_pot+1)=='c'){
3786                         wm8994_write(0x0480, 0x0000);
3787                         return 0;
3788                 }else if(*(cookie_pot+1)=='o'){
3789                         wm8994_write(0x0480, 0x0001|((bank_vol[1]+12)<<11)|
3790                         ((bank_vol[2]+12)<<6)|((bank_vol[3]+12)<<1));
3791                         wm8994_write(0x0481, 0x0000|((bank_vol[4]+12)<<11)|
3792                         ((bank_vol[5]+12)<<6));
3793                         return 0;
3794                 }else{
3795                         printk("Please press '+' '-' 'o' 'c' follow 'e'!\n");
3796                         return -1;
3797                 }
3798
3799                 switch(*(cookie_pot+2)){
3800                 case '1':
3801                         if(procadd == 3)
3802                                 bank_vol[1] += 3;
3803                         else
3804                                 bank_vol[1] -= 3;
3805
3806                         if(bank_vol[1] > 12)bank_vol[1] = 12;
3807                         if(bank_vol[1] < -12)bank_vol[1] = -12;
3808
3809                         wm8994_read(0x0480, &eqvol);
3810                         wm8994_write(0x0480, (eqvol&0x07FF)|((bank_vol[1]+12)<<11));
3811
3812                         printk("bank_vol[1] = %ddB \n",bank_vol[1]);
3813                         break;
3814
3815                 case '2':
3816                         if(procadd == 3)
3817                                 bank_vol[2] += 3;
3818                         else
3819                                 bank_vol[2] -= 3;
3820
3821                         if(bank_vol[2] > 12)bank_vol[2] = 12;
3822                         if(bank_vol[2] < -12)bank_vol[2] = -12;
3823
3824                         wm8994_read(0x0480, &eqvol);
3825                         wm8994_write(0x0480, (eqvol&0xF83F)|((bank_vol[2]+12)<<6));
3826
3827                         printk("bank_vol[2] = %ddB \n",bank_vol[2]);
3828                         break;
3829
3830                 case '3':
3831                         if(procadd == 3)
3832                                 bank_vol[3] += 3;
3833                         else
3834                                 bank_vol[3] -= 3;
3835
3836                         if(bank_vol[3] > 12)bank_vol[3] = 12;
3837                         if(bank_vol[3] < -12)bank_vol[3] = -12;
3838
3839                         wm8994_read(0x0480, &eqvol);
3840                         wm8994_write(0x0480, (eqvol&0xFFC1)|((bank_vol[3]+12)<<1));
3841
3842                         printk("bank_vol[3] = %ddB \n",bank_vol[3]);
3843                         break;
3844
3845                 case '4':
3846                         if(procadd == 3)
3847                                 bank_vol[4] += 3;
3848                         else
3849                                 bank_vol[4] -= 3;
3850
3851                         if(bank_vol[4] > 12)bank_vol[4] = 12;
3852                         if(bank_vol[4] < -12)bank_vol[4] = -12;
3853
3854                         wm8994_read(0x0481, &eqvol);
3855                         wm8994_write(0x0481, (eqvol&0x07FF)|((bank_vol[4]+12)<<11));
3856
3857                         printk("bank_vol[4] = %ddB \n",bank_vol[4]);
3858                         break;
3859
3860                 case '5':
3861                         if(procadd == 3)
3862                                 bank_vol[5] += 3;
3863                         else
3864                                 bank_vol[5] -= 3;
3865
3866                         if(bank_vol[5] > 12)bank_vol[5] = 12;
3867                         if(bank_vol[5] < -12)bank_vol[5] = -12;
3868
3869                         wm8994_read(0x0481, &eqvol);
3870                         wm8994_write(0x0481, (eqvol&0xF83F)|((bank_vol[5]+12)<<6));
3871
3872                         printk("bank_vol[5] = %ddB \n",bank_vol[5]);
3873                         break;
3874
3875                 default:
3876                         printk("Please press bank '1' to '5' follow 'e+' or 'e-'!\n");
3877                         return -1;
3878                 }
3879                 return 0;
3880                 break;
3881 //------------------------------------------------------------------------------
3882 //------------------------------------------------------------------------------
3883 //------------------------------------------------------------------------------
3884         case 'd':
3885         case 'D':
3886                 debug_write_read ++;
3887                 debug_write_read %= 2;
3888                 if(debug_write_read != 0)
3889                         DBG("Debug read and write reg on\n");
3890                 else
3891                         DBG("Debug read and write reg off\n");
3892                 break;
3893         case 'r':
3894         case 'R':
3895                 DBG("Read reg debug\n");
3896                 if(cookie_pot[1] ==':')
3897                 {
3898                         debug_write_read = 1;
3899                         strsep(&cookie_pot,":");
3900                         while((p=strsep(&cookie_pot,",")))
3901                         {
3902                                 wm8994_read(simple_strtol(p,NULL,16),(unsigned short *)&value);
3903                         }
3904                         debug_write_read = 0;;
3905                         DBG("\n");
3906                 }
3907                 else
3908                 {
3909                         DBG("Error Read reg debug.\n");
3910                         DBG("For example: echo 'r:22,23,24,25'>wm8994_ts\n");
3911                 }
3912                 break;
3913         case 'w':
3914         case 'W':
3915                 DBG("Write reg debug\n");
3916                 if(cookie_pot[1] ==':')
3917                 {
3918                         debug_write_read = 1;
3919                         strsep(&cookie_pot,":");
3920                         while((p=strsep(&cookie_pot,"=")))
3921                         {
3922                                 reg = simple_strtol(p,NULL,16);
3923                                 p=strsep(&cookie_pot,",");
3924                                 value = simple_strtol(p,NULL,16);
3925                                 wm8994_write(reg,value);
3926                         }
3927                         debug_write_read = 0;;
3928                         DBG("\n");
3929                 }
3930                 else
3931                 {
3932                         DBG("Error Write reg debug.\n");
3933                         DBG("For example: w:22=0,23=0,24=0,25=0\n");
3934                 }
3935                 break;
3936         case 's':
3937                 AP_to_speakers();
3938                 break;
3939         case 'h':
3940                 recorder_and_AP_to_headset();
3941                 break;
3942         default:
3943                 DBG("Help for wm8994_ts .\n-->The Cmd list: \n");
3944                 DBG("-->'d&&D' Open or Off the debug\n");
3945                 DBG("-->'r&&R' Read reg debug,Example: echo 'r:22,23,24,25'>wm8994_ts\n");
3946                 DBG("-->'w&&W' Write reg debug,Example: echo 'w:22=0,23=0,24=0,25=0'>wm8994_ts\n");
3947                 break;
3948         }
3949
3950         wm8994_set_channel_vol();
3951         return len;
3952 }
3953
3954 static const struct file_operations wm8994_proc_fops = {
3955         .owner          = THIS_MODULE,
3956         //.open         = snd_mem_proc_open,
3957         //.read         = seq_read,
3958 //#ifdef CONFIG_PCI
3959         .write          = wm8994_proc_write,
3960 //#endif
3961         //.llseek       = seq_lseek,
3962         //.release      = single_release,
3963 };
3964
3965 static int wm8994_proc_init(void){
3966
3967         struct proc_dir_entry *wm8994_proc_entry;
3968
3969         wm8994_proc_entry = create_proc_entry("driver/wm8994_ts", 0777, NULL);
3970
3971         if(wm8994_proc_entry != NULL){
3972
3973                 wm8994_proc_entry->write_proc = wm8994_proc_write;
3974
3975                 return -1;
3976         }else{
3977                 printk("create proc error !\n");
3978         }
3979
3980         return 0;
3981 }
3982
3983 #endif
3984
3985 static int wm8994_probe(struct platform_device *pdev)
3986 {
3987         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
3988         struct snd_soc_codec *codec;
3989         unsigned long wm8994_port = 0;
3990         int ret = 0;
3991         char b[20];
3992
3993 #ifdef WM8994_PROC
3994         wm8994_proc_init();
3995 #endif
3996
3997         if (wm8994_codec == NULL) {
3998                 dev_err(&pdev->dev, "Codec device not registered\n");
3999                 return -ENODEV;
4000         }
4001
4002         socdev->card->codec = wm8994_codec;
4003         codec = wm8994_codec;
4004
4005 //      recorder_and_AP_to_speakers();
4006
4007         setup_timer(&wm8994_timer, wm8994_codec_timer, wm8994_port);
4008         wm8994_timer.expires  = jiffies+500;//=500ms
4009         add_timer(&wm8994_timer);
4010
4011         sprintf(b, "wm8994_workqueue");
4012         wm8994_workqueue = create_freezeable_workqueue(b);
4013         if (!wm8994_workqueue)
4014                 printk("cannot create wm8994 workqueue\n");
4015         else
4016                 INIT_WORK(&wm8994_work, wm8994_work_handler);
4017
4018         if (wm8994_codec == NULL) {
4019                 dev_err(&pdev->dev, "Codec device not registered\n");
4020                 return -ENODEV;
4021         }
4022
4023
4024         /* register pcms */
4025         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
4026         if (ret < 0) {
4027                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
4028                 goto pcm_err;
4029         }
4030
4031         snd_soc_add_controls(codec,wm8994_snd_controls,
4032                                 ARRAY_SIZE(wm8994_snd_controls));
4033         snd_soc_dapm_new_controls(codec,wm8994_dapm_widgets,
4034                                   ARRAY_SIZE(wm8994_dapm_widgets));
4035         snd_soc_dapm_add_routes(codec,audio_map, ARRAY_SIZE(audio_map));
4036         snd_soc_dapm_new_widgets(codec);
4037
4038         ret = snd_soc_init_card(socdev);
4039         if (ret < 0) {
4040                 dev_err(codec->dev, "failed to register card: %d\n", ret);
4041                 goto card_err;
4042         }
4043
4044         return ret;
4045
4046 card_err:
4047         snd_soc_free_pcms(socdev);
4048         snd_soc_dapm_free(socdev);
4049 pcm_err:
4050         return ret;
4051 }
4052
4053 static int wm8994_remove(struct platform_device *pdev)
4054 {
4055         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
4056
4057         snd_soc_free_pcms(socdev);
4058         snd_soc_dapm_free(socdev);
4059
4060         return 0;
4061 }
4062
4063 struct snd_soc_codec_device soc_codec_dev_wm8994 = {
4064         .probe =        wm8994_probe,
4065         .remove =       wm8994_remove,
4066         .suspend =      wm8994_suspend,
4067         .resume =       wm8994_resume,
4068 };
4069 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
4070
4071 static int wm8994_register(struct wm8994_priv *wm8994,
4072                            enum snd_soc_control_type control)
4073 {
4074         struct snd_soc_codec *codec = &wm8994->codec;
4075         int ret;
4076
4077         if (wm8994_codec) {
4078                 dev_err(codec->dev, "Another WM8994 is registered\n");
4079                 ret = -EINVAL;
4080                 goto err;
4081         }
4082
4083         mutex_init(&codec->mutex);
4084         INIT_LIST_HEAD(&codec->dapm_widgets);
4085         INIT_LIST_HEAD(&codec->dapm_paths);
4086
4087         codec->private_data = wm8994;
4088         codec->name = "WM8994";
4089         codec->owner = THIS_MODULE;
4090         codec->dai = &wm8994_dai;
4091         codec->num_dai = 1;
4092         codec->reg_cache_size = ARRAY_SIZE(wm8994->reg_cache);
4093         codec->reg_cache = &wm8994->reg_cache;
4094         codec->bias_level = SND_SOC_BIAS_OFF;
4095         codec->set_bias_level = wm8994_set_bias_level;
4096
4097         memcpy(codec->reg_cache, wm8994_reg,
4098                sizeof(wm8994_reg));
4099
4100         ret = snd_soc_codec_set_cache_io(codec,7, 9, control);
4101         if (ret < 0) {
4102                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
4103                 goto err;
4104         }
4105
4106         ret = 0;
4107         if (ret < 0) {
4108                 dev_err(codec->dev, "Failed to issue reset\n");
4109                 goto err;
4110         }
4111
4112         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_STANDBY);
4113
4114         wm8994_dai.dev = codec->dev;
4115
4116         wm8994_codec = codec;
4117
4118         ret = snd_soc_register_codec(codec);
4119         if (ret != 0) {
4120                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
4121                 goto err;
4122         }
4123
4124         ret = snd_soc_register_dai(&wm8994_dai);
4125         if (ret != 0) {
4126                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
4127                 snd_soc_unregister_codec(codec);
4128                 goto err_codec;
4129         }
4130         return 0;
4131
4132 err_codec:
4133         snd_soc_unregister_codec(codec);
4134 err:
4135         kfree(wm8994);
4136         return ret;
4137 }
4138
4139 static void wm8994_unregister(struct wm8994_priv *wm8994)
4140 {
4141         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_OFF);
4142         snd_soc_unregister_dai(&wm8994_dai);
4143         snd_soc_unregister_codec(&wm8994->codec);
4144         kfree(wm8994);
4145         wm8994_codec = NULL;
4146 }
4147
4148 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
4149 static int wm8994_i2c_probe(struct i2c_client *i2c,
4150                             const struct i2c_device_id *id)
4151 {
4152         struct wm8994_priv *wm8994;
4153         struct snd_soc_codec *codec;
4154         wm8994_client=i2c;
4155
4156         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
4157         if (wm8994 == NULL)
4158                 return -ENOMEM;
4159
4160         codec = &wm8994->codec;
4161
4162         i2c_set_clientdata(i2c, wm8994);
4163         codec->control_data = i2c;
4164
4165         codec->dev = &i2c->dev;
4166
4167         return wm8994_register(wm8994, SND_SOC_I2C);
4168 }
4169
4170 static int wm8994_i2c_remove(struct i2c_client *client)
4171 {
4172         struct wm8994_priv *wm8994 = i2c_get_clientdata(client);
4173         wm8994_unregister(wm8994);
4174         return 0;
4175 }
4176
4177 #ifdef CONFIG_PM
4178 static int wm8994_i2c_suspend(struct i2c_client *client, pm_message_t msg)
4179 {
4180         return snd_soc_suspend_device(&client->dev);
4181 }
4182
4183 static int wm8994_i2c_resume(struct i2c_client *client)
4184 {
4185         return snd_soc_resume_device(&client->dev);
4186 }
4187 #else
4188 #define wm8994_i2c_suspend NULL
4189 #define wm8994_i2c_resume NULL
4190 #endif
4191
4192 static const struct i2c_device_id wm8994_i2c_id[] = {
4193         { "wm8994", 0 },
4194         { }
4195 };
4196 MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
4197
4198 static struct i2c_driver wm8994_i2c_driver = {
4199         .driver = {
4200                 .name = "WM8994",
4201                 .owner = THIS_MODULE,
4202         },
4203         .probe = wm8994_i2c_probe,
4204         .remove = wm8994_i2c_remove,
4205         .suspend = wm8994_i2c_suspend,
4206         .resume = wm8994_i2c_resume,
4207         .id_table = wm8994_i2c_id,
4208 };
4209
4210 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate)
4211 {
4212         int ret;
4213         struct i2c_adapter *adap = client->adapter;
4214         struct i2c_msg msg;
4215         char tx_buf[4];
4216
4217         memcpy(tx_buf, reg, 2);
4218         memcpy(tx_buf+2, data, 2);
4219         msg.addr = client->addr;
4220         msg.buf = tx_buf;
4221         msg.len = 4;
4222         msg.flags = client->flags;
4223         msg.scl_rate = scl_rate;
4224         msg.read_type = 0;
4225         ret = i2c_transfer(adap, &msg, 1);
4226
4227         return ret;
4228 }
4229
4230 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate)
4231 {
4232         int ret;
4233         struct i2c_adapter *adap = client->adapter;
4234         struct i2c_msg msgs[2];
4235
4236         msgs[0].addr = client->addr;
4237         msgs[0].buf = (char *)reg;
4238         msgs[0].flags = client->flags;
4239         msgs[0].len = 2;
4240         msgs[0].scl_rate = scl_rate;
4241         msgs[0].read_type = 2;
4242
4243         msgs[1].addr = client->addr;
4244         msgs[1].buf = (char *)buf;
4245         msgs[1].flags = client->flags | I2C_M_RD;
4246         msgs[1].len = 2;
4247         msgs[1].scl_rate = scl_rate;
4248         msgs[1].read_type = 2;
4249
4250         ret = i2c_transfer(adap, msgs, 2);
4251
4252         return ret;
4253 }
4254
4255 #endif
4256
4257 #if defined(CONFIG_SPI_MASTER)
4258 static int __devinit wm8994_spi_probe(struct spi_device *spi)
4259 {
4260         struct wm8994_priv *wm8994;
4261         struct snd_soc_codec *codec;
4262
4263         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
4264         if (wm8994 == NULL)
4265                 return -ENOMEM;
4266
4267         codec = &wm8994->codec;
4268         codec->control_data = spi;
4269         codec->dev = &spi->dev;
4270
4271         dev_set_drvdata(&spi->dev, wm8994);
4272
4273         return wm8994_register(wm8994, SND_SOC_SPI);
4274 }
4275
4276 static int __devexit wm8994_spi_remove(struct spi_device *spi)
4277 {
4278         struct wm8994_priv *wm8994 = dev_get_drvdata(&spi->dev);
4279
4280         wm8994_unregister(wm8994);
4281
4282         return 0;
4283 }
4284
4285 #ifdef CONFIG_PM
4286 static int wm8994_spi_suspend(struct spi_device *spi, pm_message_t msg)
4287 {
4288         return snd_soc_suspend_device(&spi->dev);
4289 }
4290
4291 static int wm8994_spi_resume(struct spi_device *spi)
4292 {
4293         return snd_soc_resume_device(&spi->dev);
4294 }
4295 #else
4296 #define wm8994_spi_suspend NULL
4297 #define wm8994_spi_resume NULL
4298 #endif
4299
4300 static struct spi_driver wm8994_spi_driver = {
4301         .driver = {
4302                 .name   = "wm8994",
4303                 .bus    = &spi_bus_type,
4304                 .owner  = THIS_MODULE,
4305         },
4306         .probe          = wm8994_spi_probe,
4307         .remove         = __devexit_p(wm8994_spi_remove),
4308         .suspend        = wm8994_spi_suspend,
4309         .resume         = wm8994_spi_resume,
4310 };
4311 #endif
4312
4313 static int __init wm8994_modinit(void)
4314 {
4315         int ret;
4316
4317 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
4318         ret = i2c_add_driver(&wm8994_i2c_driver);
4319         if (ret != 0)
4320                 pr_err("WM8994: Unable to register I2C driver: %d\n", ret);
4321 #endif
4322 #if defined(CONFIG_SPI_MASTER)
4323         ret = spi_register_driver(&wm8994_spi_driver);
4324         if (ret != 0)
4325                 pr_err("WM8994: Unable to register SPI driver: %d\n", ret);
4326 #endif
4327         return ret;
4328 }
4329 module_init(wm8994_modinit);
4330
4331 static void __exit wm8994_exit(void)
4332 {
4333 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
4334         i2c_del_driver(&wm8994_i2c_driver);
4335 #endif
4336 #if defined(CONFIG_SPI_MASTER)
4337         spi_unregister_driver(&wm8994_spi_driver);
4338 #endif
4339 }
4340 module_exit(wm8994_exit);
4341
4342
4343 MODULE_DESCRIPTION("ASoC WM8994 driver");
4344 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4345 MODULE_LICENSE("GPL");