sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM1811_JACKDET_MODE_NONE  0x0000
  42 #define WM1811_JACKDET_MODE_JACK  0x0100
  43 #define WM1811_JACKDET_MODE_MIC   0x0080
  44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
  45
  46 #define WM8994_NUM_DRC 3
  47 #define WM8994_NUM_EQ  3
  48
  49 static int wm8994_drc_base[] = {
  50         WM8994_AIF1_DRC1_1,
  51         WM8994_AIF1_DRC2_1,
  52         WM8994_AIF2_DRC_1,
  53 };
  54
  55 static int wm8994_retune_mobile_base[] = {
  56         WM8994_AIF1_DAC1_EQ_GAINS_1,
  57         WM8994_AIF1_DAC2_EQ_GAINS_1,
  58         WM8994_AIF2_EQ_GAINS_1,
  59 };
  60
  61 static void wm8958_default_micdet(u16 status, void *data);
  62
  63 static const struct wm8958_micd_rate micdet_rates[] = {
  64         { 32768,       true,  1, 4 },
  65         { 32768,       false, 1, 1 },
  66         { 44100 * 256, true,  7, 10 },
  67         { 44100 * 256, false, 7, 10 },
  68 };
  69
  70 static const struct wm8958_micd_rate jackdet_rates[] = {
  71         { 32768,       true,  0, 1 },
  72         { 32768,       false, 0, 1 },
  73         { 44100 * 256, true,  7, 10 },
  74         { 44100 * 256, false, 7, 10 },
  75 };
  76
  77 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
  78 {
  79         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  80         int best, i, sysclk, val;
  81         bool idle;
  82         const struct wm8958_micd_rate *rates;
  83         int num_rates;
  84
  85         if (wm8994->jack_cb != wm8958_default_micdet)
  86                 return;
  87
  88         idle = !wm8994->jack_mic;
  89
  90         sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
  91         if (sysclk & WM8994_SYSCLK_SRC)
  92                 sysclk = wm8994->aifclk[1];
  93         else
  94                 sysclk = wm8994->aifclk[0];
  95
  96         if (wm8994->pdata && wm8994->pdata->micd_rates) {
  97                 rates = wm8994->pdata->micd_rates;
  98                 num_rates = wm8994->pdata->num_micd_rates;
  99         } else if (wm8994->jackdet) {
 100                 rates = jackdet_rates;
 101                 num_rates = ARRAY_SIZE(jackdet_rates);
 102         } else {
 103                 rates = micdet_rates;
 104                 num_rates = ARRAY_SIZE(micdet_rates);
 105         }
 106
 107         best = 0;
 108         for (i = 0; i < num_rates; i++) {
 109                 if (rates[i].idle != idle)
 110                         continue;
 111                 if (abs(rates[i].sysclk - sysclk) <
 112                     abs(rates[best].sysclk - sysclk))
 113                         best = i;
 114                 else if (rates[best].idle != idle)
 115                         best = i;
 116         }
 117
 118         val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
 119                 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
 120
 121         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
 122                             WM8958_MICD_BIAS_STARTTIME_MASK |
 123                             WM8958_MICD_RATE_MASK, val);
 124 }
 125
 126 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 127 {
 128         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 129         int rate;
 130         int reg1 = 0;
 131         int offset;
 132
 133         if (aif)
 134                 offset = 4;
 135         else
 136                 offset = 0;
 137
 138         switch (wm8994->sysclk[aif]) {
 139         case WM8994_SYSCLK_MCLK1:
 140                 rate = wm8994->mclk[0];
 141                 break;
 142
 143         case WM8994_SYSCLK_MCLK2:
 144                 reg1 |= 0x8;
 145                 rate = wm8994->mclk[1];
 146                 break;
 147
 148         case WM8994_SYSCLK_FLL1:
 149                 reg1 |= 0x10;
 150                 rate = wm8994->fll[0].out;
 151                 break;
 152
 153         case WM8994_SYSCLK_FLL2:
 154                 reg1 |= 0x18;
 155                 rate = wm8994->fll[1].out;
 156                 break;
 157
 158         default:
 159                 return -EINVAL;
 160         }
 161
 162         if (rate >= 13500000) {
 163                 rate /= 2;
 164                 reg1 |= WM8994_AIF1CLK_DIV;
 165
 166                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 167                         aif + 1, rate);
 168         }
 169
 170         wm8994->aifclk[aif] = rate;
 171
 172         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 173                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 174                             reg1);
 175
 176         return 0;
 177 }
 178
 179 static int configure_clock(struct snd_soc_codec *codec)
 180 {
 181         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 182         int change, new;
 183
 184         /* Bring up the AIF clocks first */
 185         configure_aif_clock(codec, 0);
 186         configure_aif_clock(codec, 1);
 187
 188         /* Then switch CLK_SYS over to the higher of them; a change
 189          * can only happen as a result of a clocking change which can
 190          * only be made outside of DAPM so we can safely redo the
 191          * clocking.
 192          */
 193
 194         /* If they're equal it doesn't matter which is used */
 195         if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
 196                 wm8958_micd_set_rate(codec);
 197                 return 0;
 198         }
 199
 200         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 201                 new = WM8994_SYSCLK_SRC;
 202         else
 203                 new = 0;
 204
 205         change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 206                                      WM8994_SYSCLK_SRC, new);
 207         if (change)
 208                 snd_soc_dapm_sync(&codec->dapm);
 209
 210         wm8958_micd_set_rate(codec);
 211
 212         return 0;
 213 }
 214
 215 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 216                          struct snd_soc_dapm_widget *sink)
 217 {
 218         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 219         const char *clk;
 220
 221         /* Check what we're currently using for CLK_SYS */
 222         if (reg & WM8994_SYSCLK_SRC)
 223                 clk = "AIF2CLK";
 224         else
 225                 clk = "AIF1CLK";
 226
 227         return strcmp(source->name, clk) == 0;
 228 }
 229
 230 static const char *sidetone_hpf_text[] = {
 231         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 232 };
 233
 234 static const struct soc_enum sidetone_hpf =
 235         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 236
 237 static const char *adc_hpf_text[] = {
 238         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 239 };
 240
 241 static const struct soc_enum aif1adc1_hpf =
 242         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 243
 244 static const struct soc_enum aif1adc2_hpf =
 245         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 246
 247 static const struct soc_enum aif2adc_hpf =
 248         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 249
 250 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 251 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 252 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 253 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 254 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 255 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
 256 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
 257
 258 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 259 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 260         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 261         .put = wm8994_put_drc_sw, \
 262         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 263
 264 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 265                              struct snd_ctl_elem_value *ucontrol)
 266 {
 267         struct soc_mixer_control *mc =
 268                 (struct soc_mixer_control *)kcontrol->private_value;
 269         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 270         int mask, ret;
 271
 272         /* Can't enable both ADC and DAC paths simultaneously */
 273         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 274                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 275                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 276         else
 277                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 278
 279         ret = snd_soc_read(codec, mc->reg);
 280         if (ret < 0)
 281                 return ret;
 282         if (ret & mask)
 283                 return -EINVAL;
 284
 285         return snd_soc_put_volsw(kcontrol, ucontrol);
 286 }
 287
 288 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 289 {
 290         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 291         struct wm8994_pdata *pdata = wm8994->pdata;
 292         int base = wm8994_drc_base[drc];
 293         int cfg = wm8994->drc_cfg[drc];
 294         int save, i;
 295
 296         /* Save any enables; the configuration should clear them. */
 297         save = snd_soc_read(codec, base);
 298         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 299                 WM8994_AIF1ADC1R_DRC_ENA;
 300
 301         for (i = 0; i < WM8994_DRC_REGS; i++)
 302                 snd_soc_update_bits(codec, base + i, 0xffff,
 303                                     pdata->drc_cfgs[cfg].regs[i]);
 304
 305         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 306                              WM8994_AIF1ADC1L_DRC_ENA |
 307                              WM8994_AIF1ADC1R_DRC_ENA, save);
 308 }
 309
 310 /* Icky as hell but saves code duplication */
 311 static int wm8994_get_drc(const char *name)
 312 {
 313         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 314                 return 0;
 315         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 316                 return 1;
 317         if (strcmp(name, "AIF2DRC Mode") == 0)
 318                 return 2;
 319         return -EINVAL;
 320 }
 321
 322 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 323                                struct snd_ctl_elem_value *ucontrol)
 324 {
 325         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 326         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 327         struct wm8994_pdata *pdata = wm8994->pdata;
 328         int drc = wm8994_get_drc(kcontrol->id.name);
 329         int value = ucontrol->value.integer.value[0];
 330
 331         if (drc < 0)
 332                 return drc;
 333
 334         if (value >= pdata->num_drc_cfgs)
 335                 return -EINVAL;
 336
 337         wm8994->drc_cfg[drc] = value;
 338
 339         wm8994_set_drc(codec, drc);
 340
 341         return 0;
 342 }
 343
 344 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 345                                struct snd_ctl_elem_value *ucontrol)
 346 {
 347         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 348         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 349         int drc = wm8994_get_drc(kcontrol->id.name);
 350
 351         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 352
 353         return 0;
 354 }
 355
 356 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 357 {
 358         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 359         struct wm8994_pdata *pdata = wm8994->pdata;
 360         int base = wm8994_retune_mobile_base[block];
 361         int iface, best, best_val, save, i, cfg;
 362
 363         if (!pdata || !wm8994->num_retune_mobile_texts)
 364                 return;
 365
 366         switch (block) {
 367         case 0:
 368         case 1:
 369                 iface = 0;
 370                 break;
 371         case 2:
 372                 iface = 1;
 373                 break;
 374         default:
 375                 return;
 376         }
 377
 378         /* Find the version of the currently selected configuration
 379          * with the nearest sample rate. */
 380         cfg = wm8994->retune_mobile_cfg[block];
 381         best = 0;
 382         best_val = INT_MAX;
 383         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 384                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 385                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 386                     abs(pdata->retune_mobile_cfgs[i].rate
 387                         - wm8994->dac_rates[iface]) < best_val) {
 388                         best = i;
 389                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 390                                        - wm8994->dac_rates[iface]);
 391                 }
 392         }
 393
 394         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 395                 block,
 396                 pdata->retune_mobile_cfgs[best].name,
 397                 pdata->retune_mobile_cfgs[best].rate,
 398                 wm8994->dac_rates[iface]);
 399
 400         /* The EQ will be disabled while reconfiguring it, remember the
 401          * current configuration.
 402          */
 403         save = snd_soc_read(codec, base);
 404         save &= WM8994_AIF1DAC1_EQ_ENA;
 405
 406         for (i = 0; i < WM8994_EQ_REGS; i++)
 407                 snd_soc_update_bits(codec, base + i, 0xffff,
 408                                 pdata->retune_mobile_cfgs[best].regs[i]);
 409
 410         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 411 }
 412
 413 /* Icky as hell but saves code duplication */
 414 static int wm8994_get_retune_mobile_block(const char *name)
 415 {
 416         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 417                 return 0;
 418         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 419                 return 1;
 420         if (strcmp(name, "AIF2 EQ Mode") == 0)
 421                 return 2;
 422         return -EINVAL;
 423 }
 424
 425 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 426                                          struct snd_ctl_elem_value *ucontrol)
 427 {
 428         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 429         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 430         struct wm8994_pdata *pdata = wm8994->pdata;
 431         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 432         int value = ucontrol->value.integer.value[0];
 433
 434         if (block < 0)
 435                 return block;
 436
 437         if (value >= pdata->num_retune_mobile_cfgs)
 438                 return -EINVAL;
 439
 440         wm8994->retune_mobile_cfg[block] = value;
 441
 442         wm8994_set_retune_mobile(codec, block);
 443
 444         return 0;
 445 }
 446
 447 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 448                                          struct snd_ctl_elem_value *ucontrol)
 449 {
 450         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 451         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 452         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 453
 454         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 455
 456         return 0;
 457 }
 458
 459 static const char *aif_chan_src_text[] = {
 460         "Left", "Right"
 461 };
 462
 463 static const struct soc_enum aif1adcl_src =
 464         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 465
 466 static const struct soc_enum aif1adcr_src =
 467         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 468
 469 static const struct soc_enum aif2adcl_src =
 470         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 471
 472 static const struct soc_enum aif2adcr_src =
 473         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 474
 475 static const struct soc_enum aif1dacl_src =
 476         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 477
 478 static const struct soc_enum aif1dacr_src =
 479         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 480
 481 static const struct soc_enum aif2dacl_src =
 482         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 483
 484 static const struct soc_enum aif2dacr_src =
 485         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 486
 487 static const char *osr_text[] = {
 488         "Low Power", "High Performance",
 489 };
 490
 491 static const struct soc_enum dac_osr =
 492         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 493
 494 static const struct soc_enum adc_osr =
 495         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 496
 497 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 498 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 499                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 500                  1, 119, 0, digital_tlv),
 501 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 502                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 503                  1, 119, 0, digital_tlv),
 504 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 505                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 506                  1, 119, 0, digital_tlv),
 507
 508 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 509 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 510 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 511 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 512
 513 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 514 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 515 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 516 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 517
 518 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 519                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 520 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 521                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 522 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 523                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 524
 525 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 526 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 527
 528 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 529 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 530 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 531
 532 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 533 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 534 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 535
 536 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 537 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 538 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 539
 540 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 541 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 542 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 543
 544 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 545                5, 12, 0, st_tlv),
 546 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 547                0, 12, 0, st_tlv),
 548 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 549                5, 12, 0, st_tlv),
 550 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 551                0, 12, 0, st_tlv),
 552 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 553 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 554
 555 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 556 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 557
 558 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 559 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 560
 561 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 562 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 563
 564 SOC_ENUM("ADC OSR", adc_osr),
 565 SOC_ENUM("DAC OSR", dac_osr),
 566
 567 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 568                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 569 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 570              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 571
 572 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 573                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 574 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 575              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 576
 577 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 578                6, 1, 1, wm_hubs_spkmix_tlv),
 579 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 580                2, 1, 1, wm_hubs_spkmix_tlv),
 581
 582 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 583                6, 1, 1, wm_hubs_spkmix_tlv),
 584 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 585                2, 1, 1, wm_hubs_spkmix_tlv),
 586
 587 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 588                10, 15, 0, wm8994_3d_tlv),
 589 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 590            8, 1, 0),
 591 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 592                10, 15, 0, wm8994_3d_tlv),
 593 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 594            8, 1, 0),
 595 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 596                10, 15, 0, wm8994_3d_tlv),
 597 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 598            8, 1, 0),
 599 };
 600
 601 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 602 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 603                eq_tlv),
 604 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 605                eq_tlv),
 606 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 607                eq_tlv),
 608 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 609                eq_tlv),
 610 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 611                eq_tlv),
 612
 613 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 614                eq_tlv),
 615 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 616                eq_tlv),
 617 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 618                eq_tlv),
 619 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 620                eq_tlv),
 621 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 622                eq_tlv),
 623
 624 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 625                eq_tlv),
 626 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 627                eq_tlv),
 628 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 629                eq_tlv),
 630 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 631                eq_tlv),
 632 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 633                eq_tlv),
 634 };
 635
 636 static const char *wm8958_ng_text[] = {
 637         "30ms", "125ms", "250ms", "500ms",
 638 };
 639
 640 static const struct soc_enum wm8958_aif1dac1_ng_hold =
 641         SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
 642                         WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
 643
 644 static const struct soc_enum wm8958_aif1dac2_ng_hold =
 645         SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
 646                         WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
 647
 648 static const struct soc_enum wm8958_aif2dac_ng_hold =
 649         SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
 650                         WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
 651
 652 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 653 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 654
 655 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
 656            WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
 657 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
 658 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
 659                WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
 660                7, 1, ng_tlv),
 661
 662 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
 663            WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
 664 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
 665 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
 666                WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
 667                7, 1, ng_tlv),
 668
 669 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
 670            WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
 671 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
 672 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
 673                WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
 674                7, 1, ng_tlv),
 675 };
 676
 677 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
 678 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
 679                mixin_boost_tlv),
 680 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
 681                mixin_boost_tlv),
 682 };
 683
 684 /* We run all mode setting through a function to enforce audio mode */
 685 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
 686 {
 687         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 688
 689         if (wm8994->active_refcount)
 690                 mode = WM1811_JACKDET_MODE_AUDIO;
 691
 692         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 693                             WM1811_JACKDET_MODE_MASK, mode);
 694
 695         if (mode == WM1811_JACKDET_MODE_MIC)
 696                 msleep(2);
 697 }
 698
 699 static void active_reference(struct snd_soc_codec *codec)
 700 {
 701         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 702
 703         mutex_lock(&wm8994->accdet_lock);
 704
 705         wm8994->active_refcount++;
 706
 707         dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
 708                 wm8994->active_refcount);
 709
 710         if (wm8994->active_refcount == 1) {
 711                 /* If we're using jack detection go into audio mode */
 712                 if (wm8994->jackdet && wm8994->jack_cb) {
 713                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 714                                             WM1811_JACKDET_MODE_MASK,
 715                                             WM1811_JACKDET_MODE_AUDIO);
 716                         msleep(2);
 717                 }
 718         }
 719
 720         mutex_unlock(&wm8994->accdet_lock);
 721 }
 722
 723 static void active_dereference(struct snd_soc_codec *codec)
 724 {
 725         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 726         u16 mode;
 727
 728         mutex_lock(&wm8994->accdet_lock);
 729
 730         wm8994->active_refcount--;
 731
 732         dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
 733                 wm8994->active_refcount);
 734
 735         if (wm8994->active_refcount == 0) {
 736                 /* Go into appropriate detection only mode */
 737                 if (wm8994->jackdet && wm8994->jack_cb) {
 738                         if (wm8994->jack_mic || wm8994->mic_detecting)
 739                                 mode = WM1811_JACKDET_MODE_MIC;
 740                         else
 741                                 mode = WM1811_JACKDET_MODE_JACK;
 742
 743                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 744                                             WM1811_JACKDET_MODE_MASK,
 745                                             mode);
 746                 }
 747         }
 748
 749         mutex_unlock(&wm8994->accdet_lock);
 750 }
 751
 752 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 753                          struct snd_kcontrol *kcontrol, int event)
 754 {
 755         struct snd_soc_codec *codec = w->codec;
 756
 757         switch (event) {
 758         case SND_SOC_DAPM_PRE_PMU:
 759                 return configure_clock(codec);
 760
 761         case SND_SOC_DAPM_POST_PMD:
 762                 configure_clock(codec);
 763                 break;
 764         }
 765
 766         return 0;
 767 }
 768
 769 static void vmid_reference(struct snd_soc_codec *codec)
 770 {
 771         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 772
 773         wm8994->vmid_refcount++;
 774
 775         dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
 776                 wm8994->vmid_refcount);
 777
 778         if (wm8994->vmid_refcount == 1) {
 779                 /* Startup bias, VMID ramp & buffer */
 780                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 781                                     WM8994_STARTUP_BIAS_ENA |
 782                                     WM8994_VMID_BUF_ENA |
 783                                     WM8994_VMID_RAMP_MASK,
 784                                     WM8994_STARTUP_BIAS_ENA |
 785                                     WM8994_VMID_BUF_ENA |
 786                                     (0x11 << WM8994_VMID_RAMP_SHIFT));
 787
 788                 /* Main bias enable, VMID=2x40k */
 789                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 790                                     WM8994_BIAS_ENA |
 791                                     WM8994_VMID_SEL_MASK,
 792                                     WM8994_BIAS_ENA | 0x2);
 793
 794                 msleep(20);
 795         }
 796 }
 797
 798 static void vmid_dereference(struct snd_soc_codec *codec)
 799 {
 800         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 801
 802         wm8994->vmid_refcount--;
 803
 804         dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
 805                 wm8994->vmid_refcount);
 806
 807         if (wm8994->vmid_refcount == 0) {
 808                 /* Switch over to startup biases */
 809                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 810                                     WM8994_BIAS_SRC |
 811                                     WM8994_STARTUP_BIAS_ENA |
 812                                     WM8994_VMID_BUF_ENA |
 813                                     WM8994_VMID_RAMP_MASK,
 814                                     WM8994_BIAS_SRC |
 815                                     WM8994_STARTUP_BIAS_ENA |
 816                                     WM8994_VMID_BUF_ENA |
 817                                     (1 << WM8994_VMID_RAMP_SHIFT));
 818
 819                 /* Disable main biases */
 820                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
 821                                     WM8994_BIAS_ENA |
 822                                     WM8994_VMID_SEL_MASK, 0);
 823
 824                 /* Discharge line */
 825                 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
 826                                     WM8994_LINEOUT1_DISCH |
 827                                     WM8994_LINEOUT2_DISCH,
 828                                     WM8994_LINEOUT1_DISCH |
 829                                     WM8994_LINEOUT2_DISCH);
 830
 831                 msleep(5);
 832
 833                 /* Switch off startup biases */
 834                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
 835                                     WM8994_BIAS_SRC |
 836                                     WM8994_STARTUP_BIAS_ENA |
 837                                     WM8994_VMID_BUF_ENA |
 838                                     WM8994_VMID_RAMP_MASK, 0);
 839         }
 840 }
 841
 842 static int vmid_event(struct snd_soc_dapm_widget *w,
 843                       struct snd_kcontrol *kcontrol, int event)
 844 {
 845         struct snd_soc_codec *codec = w->codec;
 846
 847         switch (event) {
 848         case SND_SOC_DAPM_PRE_PMU:
 849                 vmid_reference(codec);
 850                 break;
 851
 852         case SND_SOC_DAPM_POST_PMD:
 853                 vmid_dereference(codec);
 854                 break;
 855         }
 856
 857         return 0;
 858 }
 859
 860 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 861 {
 862         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 863         int enable = 1;
 864         int source = 0;  /* GCC flow analysis can't track enable */
 865         int reg, reg_r;
 866
 867         /* Only support direct DAC->headphone paths */
 868         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 869         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 870                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 871                 enable = 0;
 872         }
 873
 874         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 875         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 876                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 877                 enable = 0;
 878         }
 879
 880         /* We also need the same setting for L/R and only one path */
 881         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 882         switch (reg) {
 883         case WM8994_AIF2DACL_TO_DAC1L:
 884                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 885                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 886                 break;
 887         case WM8994_AIF1DAC2L_TO_DAC1L:
 888                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 889                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 890                 break;
 891         case WM8994_AIF1DAC1L_TO_DAC1L:
 892                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 893                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 894                 break;
 895         default:
 896                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 897                 enable = 0;
 898                 break;
 899         }
 900
 901         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 902         if (reg_r != reg) {
 903                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 904                 enable = 0;
 905         }
 906
 907         if (enable) {
 908                 dev_dbg(codec->dev, "Class W enabled\n");
 909                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 910                                     WM8994_CP_DYN_PWR |
 911                                     WM8994_CP_DYN_SRC_SEL_MASK,
 912                                     source | WM8994_CP_DYN_PWR);
 913                 wm8994->hubs.class_w = true;
 914
 915         } else {
 916                 dev_dbg(codec->dev, "Class W disabled\n");
 917                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 918                                     WM8994_CP_DYN_PWR, 0);
 919                 wm8994->hubs.class_w = false;
 920         }
 921 }
 922
 923 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 924                           struct snd_kcontrol *kcontrol, int event)
 925 {
 926         struct snd_soc_codec *codec = w->codec;
 927         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 928
 929         switch (event) {
 930         case SND_SOC_DAPM_PRE_PMU:
 931                 if (wm8994->aif1clk_enable) {
 932                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 933                                             WM8994_AIF1CLK_ENA_MASK,
 934                                             WM8994_AIF1CLK_ENA);
 935                         wm8994->aif1clk_enable = 0;
 936                 }
 937                 if (wm8994->aif2clk_enable) {
 938                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 939                                             WM8994_AIF2CLK_ENA_MASK,
 940                                             WM8994_AIF2CLK_ENA);
 941                         wm8994->aif2clk_enable = 0;
 942                 }
 943                 break;
 944         }
 945
 946         /* We may also have postponed startup of DSP, handle that. */
 947         wm8958_aif_ev(w, kcontrol, event);
 948
 949         return 0;
 950 }
 951
 952 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 953                            struct snd_kcontrol *kcontrol, int event)
 954 {
 955         struct snd_soc_codec *codec = w->codec;
 956         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 957
 958         switch (event) {
 959         case SND_SOC_DAPM_POST_PMD:
 960                 if (wm8994->aif1clk_disable) {
 961                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 962                                             WM8994_AIF1CLK_ENA_MASK, 0);
 963                         wm8994->aif1clk_disable = 0;
 964                 }
 965                 if (wm8994->aif2clk_disable) {
 966                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 967                                             WM8994_AIF2CLK_ENA_MASK, 0);
 968                         wm8994->aif2clk_disable = 0;
 969                 }
 970                 break;
 971         }
 972
 973         return 0;
 974 }
 975
 976 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 977                       struct snd_kcontrol *kcontrol, int event)
 978 {
 979         struct snd_soc_codec *codec = w->codec;
 980         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 981
 982         switch (event) {
 983         case SND_SOC_DAPM_PRE_PMU:
 984                 wm8994->aif1clk_enable = 1;
 985                 break;
 986         case SND_SOC_DAPM_POST_PMD:
 987                 wm8994->aif1clk_disable = 1;
 988                 break;
 989         }
 990
 991         return 0;
 992 }
 993
 994 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 995                       struct snd_kcontrol *kcontrol, int event)
 996 {
 997         struct snd_soc_codec *codec = w->codec;
 998         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 999
1000         switch (event) {
1001         case SND_SOC_DAPM_PRE_PMU:
1002                 wm8994->aif2clk_enable = 1;
1003                 break;
1004         case SND_SOC_DAPM_POST_PMD:
1005                 wm8994->aif2clk_disable = 1;
1006                 break;
1007         }
1008
1009         return 0;
1010 }
1011
1012 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1013                       struct snd_kcontrol *kcontrol, int event)
1014 {
1015         late_enable_ev(w, kcontrol, event);
1016         return 0;
1017 }
1018
1019 static int micbias_ev(struct snd_soc_dapm_widget *w,
1020                       struct snd_kcontrol *kcontrol, int event)
1021 {
1022         late_enable_ev(w, kcontrol, event);
1023         return 0;
1024 }
1025
1026 static int dac_ev(struct snd_soc_dapm_widget *w,
1027                   struct snd_kcontrol *kcontrol, int event)
1028 {
1029         struct snd_soc_codec *codec = w->codec;
1030         unsigned int mask = 1 << w->shift;
1031
1032         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1033                             mask, mask);
1034         return 0;
1035 }
1036
1037 static const char *hp_mux_text[] = {
1038         "Mixer",
1039         "DAC",
1040 };
1041
1042 #define WM8994_HP_ENUM(xname, xenum) \
1043 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1044         .info = snd_soc_info_enum_double, \
1045         .get = snd_soc_dapm_get_enum_double, \
1046         .put = wm8994_put_hp_enum, \
1047         .private_value = (unsigned long)&xenum }
1048
1049 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1050                               struct snd_ctl_elem_value *ucontrol)
1051 {
1052         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1053         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1054         struct snd_soc_codec *codec = w->codec;
1055         int ret;
1056
1057         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1058
1059         wm8994_update_class_w(codec);
1060
1061         return ret;
1062 }
1063
1064 static const struct soc_enum hpl_enum =
1065         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1066
1067 static const struct snd_kcontrol_new hpl_mux =
1068         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1069
1070 static const struct soc_enum hpr_enum =
1071         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1072
1073 static const struct snd_kcontrol_new hpr_mux =
1074         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1075
1076 static const char *adc_mux_text[] = {
1077         "ADC",
1078         "DMIC",
1079 };
1080
1081 static const struct soc_enum adc_enum =
1082         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1083
1084 static const struct snd_kcontrol_new adcl_mux =
1085         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1086
1087 static const struct snd_kcontrol_new adcr_mux =
1088         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1089
1090 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1091 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1092 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1093 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1094 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1095 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1096 };
1097
1098 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1099 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1100 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1101 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1102 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1103 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1104 };
1105
1106 /* Debugging; dump chip status after DAPM transitions */
1107 static int post_ev(struct snd_soc_dapm_widget *w,
1108             struct snd_kcontrol *kcontrol, int event)
1109 {
1110         struct snd_soc_codec *codec = w->codec;
1111         dev_dbg(codec->dev, "SRC status: %x\n",
1112                 snd_soc_read(codec,
1113                              WM8994_RATE_STATUS));
1114         return 0;
1115 }
1116
1117 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1118 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1119                 1, 1, 0),
1120 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1121                 0, 1, 0),
1122 };
1123
1124 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1125 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1126                 1, 1, 0),
1127 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1128                 0, 1, 0),
1129 };
1130
1131 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1132 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1133                 1, 1, 0),
1134 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1135                 0, 1, 0),
1136 };
1137
1138 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1139 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1140                 1, 1, 0),
1141 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1142                 0, 1, 0),
1143 };
1144
1145 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1146 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1147                 5, 1, 0),
1148 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1149                 4, 1, 0),
1150 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1151                 2, 1, 0),
1152 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1153                 1, 1, 0),
1154 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1155                 0, 1, 0),
1156 };
1157
1158 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1159 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1160                 5, 1, 0),
1161 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1162                 4, 1, 0),
1163 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1164                 2, 1, 0),
1165 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1166                 1, 1, 0),
1167 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1168                 0, 1, 0),
1169 };
1170
1171 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1172 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1173         .info = snd_soc_info_volsw, \
1174         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1175         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1176
1177 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1178                               struct snd_ctl_elem_value *ucontrol)
1179 {
1180         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1181         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1182         struct snd_soc_codec *codec = w->codec;
1183         int ret;
1184
1185         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1186
1187         wm8994_update_class_w(codec);
1188
1189         return ret;
1190 }
1191
1192 static const struct snd_kcontrol_new dac1l_mix[] = {
1193 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1194                       5, 1, 0),
1195 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1196                       4, 1, 0),
1197 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1198                       2, 1, 0),
1199 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1200                       1, 1, 0),
1201 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1202                       0, 1, 0),
1203 };
1204
1205 static const struct snd_kcontrol_new dac1r_mix[] = {
1206 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1207                       5, 1, 0),
1208 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1209                       4, 1, 0),
1210 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1211                       2, 1, 0),
1212 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1213                       1, 1, 0),
1214 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1215                       0, 1, 0),
1216 };
1217
1218 static const char *sidetone_text[] = {
1219         "ADC/DMIC1", "DMIC2",
1220 };
1221
1222 static const struct soc_enum sidetone1_enum =
1223         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1224
1225 static const struct snd_kcontrol_new sidetone1_mux =
1226         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1227
1228 static const struct soc_enum sidetone2_enum =
1229         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1230
1231 static const struct snd_kcontrol_new sidetone2_mux =
1232         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1233
1234 static const char *aif1dac_text[] = {
1235         "AIF1DACDAT", "AIF3DACDAT",
1236 };
1237
1238 static const struct soc_enum aif1dac_enum =
1239         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1240
1241 static const struct snd_kcontrol_new aif1dac_mux =
1242         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1243
1244 static const char *aif2dac_text[] = {
1245         "AIF2DACDAT", "AIF3DACDAT",
1246 };
1247
1248 static const struct soc_enum aif2dac_enum =
1249         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1250
1251 static const struct snd_kcontrol_new aif2dac_mux =
1252         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1253
1254 static const char *aif2adc_text[] = {
1255         "AIF2ADCDAT", "AIF3DACDAT",
1256 };
1257
1258 static const struct soc_enum aif2adc_enum =
1259         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1260
1261 static const struct snd_kcontrol_new aif2adc_mux =
1262         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1263
1264 static const char *aif3adc_text[] = {
1265         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1266 };
1267
1268 static const struct soc_enum wm8994_aif3adc_enum =
1269         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1270
1271 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1272         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1273
1274 static const struct soc_enum wm8958_aif3adc_enum =
1275         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1276
1277 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1278         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1279
1280 static const char *mono_pcm_out_text[] = {
1281         "None", "AIF2ADCL", "AIF2ADCR",
1282 };
1283
1284 static const struct soc_enum mono_pcm_out_enum =
1285         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1286
1287 static const struct snd_kcontrol_new mono_pcm_out_mux =
1288         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1289
1290 static const char *aif2dac_src_text[] = {
1291         "AIF2", "AIF3",
1292 };
1293
1294 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1295 static const struct soc_enum aif2dacl_src_enum =
1296         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1297
1298 static const struct snd_kcontrol_new aif2dacl_src_mux =
1299         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1300
1301 static const struct soc_enum aif2dacr_src_enum =
1302         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1303
1304 static const struct snd_kcontrol_new aif2dacr_src_mux =
1305         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1306
1307 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1308 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1309         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1310 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1311         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1312
1313 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1314         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1315 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1316         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1317 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1318         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1319 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1320         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1321 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1322         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1323
1324 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1325                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1326                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1327 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1328                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1329                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1330 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1331                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1332 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1333                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1334
1335 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1336 };
1337
1338 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1339 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1340 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1341 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1342 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1343                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1344 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1345                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1346 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1347 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1348 };
1349
1350 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1351 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1352         dac_ev, SND_SOC_DAPM_PRE_PMU),
1353 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1354         dac_ev, SND_SOC_DAPM_PRE_PMU),
1355 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1356         dac_ev, SND_SOC_DAPM_PRE_PMU),
1357 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1358         dac_ev, SND_SOC_DAPM_PRE_PMU),
1359 };
1360
1361 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1362 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1363 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1364 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1365 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1366 };
1367
1368 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1369 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1370                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1371 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1372                         adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1373 };
1374
1375 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1376 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1377 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1378 };
1379
1380 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1381 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1382 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1383 SND_SOC_DAPM_INPUT("Clock"),
1384
1385 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1386                       SND_SOC_DAPM_PRE_PMU),
1387 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1388                     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1389
1390 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1391                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1392
1393 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1394 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1395 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1396
1397 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1398                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1399 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1400                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1401 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1402                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1403                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1404 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1405                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1406                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1407
1408 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1409                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1410 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1411                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1412 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1413                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1414                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1415 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1416                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1417                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1418
1419 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1420                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1421 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1422                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1423
1424 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1425                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1426 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1427                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1428
1429 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1430                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1431 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1432                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1433
1434 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1435 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1436
1437 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1438                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1439 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1440                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1441
1442 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1443                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1444 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1445                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1446 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1447                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1448                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1449 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1450                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1451                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1452
1453 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1454 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1455 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1456 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1457
1458 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1459 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1460 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1461
1462 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1463 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1464
1465 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1466
1467 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1468 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1469 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1470 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1471
1472 /* Power is done with the muxes since the ADC power also controls the
1473  * downsampling chain, the chip will automatically manage the analogue
1474  * specific portions.
1475  */
1476 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1477 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1478
1479 SND_SOC_DAPM_POST("Debug log", post_ev),
1480 };
1481
1482 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1483 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1484 };
1485
1486 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1487 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1488 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1489 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1490 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1491 };
1492
1493 static const struct snd_soc_dapm_route intercon[] = {
1494         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1495         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1496
1497         { "DSP1CLK", NULL, "CLK_SYS" },
1498         { "DSP2CLK", NULL, "CLK_SYS" },
1499         { "DSPINTCLK", NULL, "CLK_SYS" },
1500
1501         { "AIF1ADC1L", NULL, "AIF1CLK" },
1502         { "AIF1ADC1L", NULL, "DSP1CLK" },
1503         { "AIF1ADC1R", NULL, "AIF1CLK" },
1504         { "AIF1ADC1R", NULL, "DSP1CLK" },
1505         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1506
1507         { "AIF1DAC1L", NULL, "AIF1CLK" },
1508         { "AIF1DAC1L", NULL, "DSP1CLK" },
1509         { "AIF1DAC1R", NULL, "AIF1CLK" },
1510         { "AIF1DAC1R", NULL, "DSP1CLK" },
1511         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1512
1513         { "AIF1ADC2L", NULL, "AIF1CLK" },
1514         { "AIF1ADC2L", NULL, "DSP1CLK" },
1515         { "AIF1ADC2R", NULL, "AIF1CLK" },
1516         { "AIF1ADC2R", NULL, "DSP1CLK" },
1517         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1518
1519         { "AIF1DAC2L", NULL, "AIF1CLK" },
1520         { "AIF1DAC2L", NULL, "DSP1CLK" },
1521         { "AIF1DAC2R", NULL, "AIF1CLK" },
1522         { "AIF1DAC2R", NULL, "DSP1CLK" },
1523         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1524
1525         { "AIF2ADCL", NULL, "AIF2CLK" },
1526         { "AIF2ADCL", NULL, "DSP2CLK" },
1527         { "AIF2ADCR", NULL, "AIF2CLK" },
1528         { "AIF2ADCR", NULL, "DSP2CLK" },
1529         { "AIF2ADCR", NULL, "DSPINTCLK" },
1530
1531         { "AIF2DACL", NULL, "AIF2CLK" },
1532         { "AIF2DACL", NULL, "DSP2CLK" },
1533         { "AIF2DACR", NULL, "AIF2CLK" },
1534         { "AIF2DACR", NULL, "DSP2CLK" },
1535         { "AIF2DACR", NULL, "DSPINTCLK" },
1536
1537         { "DMIC1L", NULL, "DMIC1DAT" },
1538         { "DMIC1L", NULL, "CLK_SYS" },
1539         { "DMIC1R", NULL, "DMIC1DAT" },
1540         { "DMIC1R", NULL, "CLK_SYS" },
1541         { "DMIC2L", NULL, "DMIC2DAT" },
1542         { "DMIC2L", NULL, "CLK_SYS" },
1543         { "DMIC2R", NULL, "DMIC2DAT" },
1544         { "DMIC2R", NULL, "CLK_SYS" },
1545
1546         { "ADCL", NULL, "AIF1CLK" },
1547         { "ADCL", NULL, "DSP1CLK" },
1548         { "ADCL", NULL, "DSPINTCLK" },
1549
1550         { "ADCR", NULL, "AIF1CLK" },
1551         { "ADCR", NULL, "DSP1CLK" },
1552         { "ADCR", NULL, "DSPINTCLK" },
1553
1554         { "ADCL Mux", "ADC", "ADCL" },
1555         { "ADCL Mux", "DMIC", "DMIC1L" },
1556         { "ADCR Mux", "ADC", "ADCR" },
1557         { "ADCR Mux", "DMIC", "DMIC1R" },
1558
1559         { "DAC1L", NULL, "AIF1CLK" },
1560         { "DAC1L", NULL, "DSP1CLK" },
1561         { "DAC1L", NULL, "DSPINTCLK" },
1562
1563         { "DAC1R", NULL, "AIF1CLK" },
1564         { "DAC1R", NULL, "DSP1CLK" },
1565         { "DAC1R", NULL, "DSPINTCLK" },
1566
1567         { "DAC2L", NULL, "AIF2CLK" },
1568         { "DAC2L", NULL, "DSP2CLK" },
1569         { "DAC2L", NULL, "DSPINTCLK" },
1570
1571         { "DAC2R", NULL, "AIF2DACR" },
1572         { "DAC2R", NULL, "AIF2CLK" },
1573         { "DAC2R", NULL, "DSP2CLK" },
1574         { "DAC2R", NULL, "DSPINTCLK" },
1575
1576         { "TOCLK", NULL, "CLK_SYS" },
1577
1578         /* AIF1 outputs */
1579         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1580         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1581         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1582
1583         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1584         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1585         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1586
1587         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1588         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1589         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1590
1591         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1592         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1593         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1594
1595         /* Pin level routing for AIF3 */
1596         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1597         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1598         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1599         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1600
1601         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1602         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1603         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1604         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1605         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1606         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1607         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1608
1609         /* DAC1 inputs */
1610         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1611         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1612         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1613         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1614         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1615
1616         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1617         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1618         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1619         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1620         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1621
1622         /* DAC2/AIF2 outputs  */
1623         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1624         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1625         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1626         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1627         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1628         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1629
1630         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1631         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1632         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1633         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1634         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1635         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1636
1637         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1638         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1639         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1640         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1641
1642         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1643
1644         /* AIF3 output */
1645         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1646         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1647         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1648         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1649         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1650         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1651         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1652         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1653
1654         /* Sidetone */
1655         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1656         { "Left Sidetone", "DMIC2", "DMIC2L" },
1657         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1658         { "Right Sidetone", "DMIC2", "DMIC2R" },
1659
1660         /* Output stages */
1661         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1662         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1663
1664         { "SPKL", "DAC1 Switch", "DAC1L" },
1665         { "SPKL", "DAC2 Switch", "DAC2L" },
1666
1667         { "SPKR", "DAC1 Switch", "DAC1R" },
1668         { "SPKR", "DAC2 Switch", "DAC2R" },
1669
1670         { "Left Headphone Mux", "DAC", "DAC1L" },
1671         { "Right Headphone Mux", "DAC", "DAC1R" },
1672 };
1673
1674 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1675         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1676         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1677         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1678         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1679         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1680         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1681         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1682         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1683 };
1684
1685 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1686         { "DAC1L", NULL, "DAC1L Mixer" },
1687         { "DAC1R", NULL, "DAC1R Mixer" },
1688         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1689         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1690 };
1691
1692 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1693         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1694         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1695         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1696         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1697         { "MICBIAS1", NULL, "CLK_SYS" },
1698         { "MICBIAS1", NULL, "MICBIAS Supply" },
1699         { "MICBIAS2", NULL, "CLK_SYS" },
1700         { "MICBIAS2", NULL, "MICBIAS Supply" },
1701 };
1702
1703 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1704         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1705         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1706         { "MICBIAS1", NULL, "VMID" },
1707         { "MICBIAS2", NULL, "VMID" },
1708 };
1709
1710 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1711         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1712         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1713
1714         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1715         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1716         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1717         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1718
1719         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1720         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1721
1722         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1723 };
1724
1725 /* The size in bits of the FLL divide multiplied by 10
1726  * to allow rounding later */
1727 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1728
1729 struct fll_div {
1730         u16 outdiv;
1731         u16 n;
1732         u16 k;
1733         u16 clk_ref_div;
1734         u16 fll_fratio;
1735 };
1736
1737 static int wm8994_get_fll_config(struct fll_div *fll,
1738                                  int freq_in, int freq_out)
1739 {
1740         u64 Kpart;
1741         unsigned int K, Ndiv, Nmod;
1742
1743         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1744
1745         /* Scale the input frequency down to <= 13.5MHz */
1746         fll->clk_ref_div = 0;
1747         while (freq_in > 13500000) {
1748                 fll->clk_ref_div++;
1749                 freq_in /= 2;
1750
1751                 if (fll->clk_ref_div > 3)
1752                         return -EINVAL;
1753         }
1754         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1755
1756         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1757         fll->outdiv = 3;
1758         while (freq_out * (fll->outdiv + 1) < 90000000) {
1759                 fll->outdiv++;
1760                 if (fll->outdiv > 63)
1761                         return -EINVAL;
1762         }
1763         freq_out *= fll->outdiv + 1;
1764         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1765
1766         if (freq_in > 1000000) {
1767                 fll->fll_fratio = 0;
1768         } else if (freq_in > 256000) {
1769                 fll->fll_fratio = 1;
1770                 freq_in *= 2;
1771         } else if (freq_in > 128000) {
1772                 fll->fll_fratio = 2;
1773                 freq_in *= 4;
1774         } else if (freq_in > 64000) {
1775                 fll->fll_fratio = 3;
1776                 freq_in *= 8;
1777         } else {
1778                 fll->fll_fratio = 4;
1779                 freq_in *= 16;
1780         }
1781         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1782
1783         /* Now, calculate N.K */
1784         Ndiv = freq_out / freq_in;
1785
1786         fll->n = Ndiv;
1787         Nmod = freq_out % freq_in;
1788         pr_debug("Nmod=%d\n", Nmod);
1789
1790         /* Calculate fractional part - scale up so we can round. */
1791         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1792
1793         do_div(Kpart, freq_in);
1794
1795         K = Kpart & 0xFFFFFFFF;
1796
1797         if ((K % 10) >= 5)
1798                 K += 5;
1799
1800         /* Move down to proper range now rounding is done */
1801         fll->k = K / 10;
1802
1803         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1804
1805         return 0;
1806 }
1807
1808 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1809                           unsigned int freq_in, unsigned int freq_out)
1810 {
1811         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1812         struct wm8994 *control = wm8994->wm8994;
1813         int reg_offset, ret;
1814         struct fll_div fll;
1815         u16 reg, aif1, aif2;
1816         unsigned long timeout;
1817         bool was_enabled;
1818
1819         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1820                 & WM8994_AIF1CLK_ENA;
1821
1822         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1823                 & WM8994_AIF2CLK_ENA;
1824
1825         switch (id) {
1826         case WM8994_FLL1:
1827                 reg_offset = 0;
1828                 id = 0;
1829                 break;
1830         case WM8994_FLL2:
1831                 reg_offset = 0x20;
1832                 id = 1;
1833                 break;
1834         default:
1835                 return -EINVAL;
1836         }
1837
1838         reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1839         was_enabled = reg & WM8994_FLL1_ENA;
1840
1841         switch (src) {
1842         case 0:
1843                 /* Allow no source specification when stopping */
1844                 if (freq_out)
1845                         return -EINVAL;
1846                 src = wm8994->fll[id].src;
1847                 break;
1848         case WM8994_FLL_SRC_MCLK1:
1849         case WM8994_FLL_SRC_MCLK2:
1850         case WM8994_FLL_SRC_LRCLK:
1851         case WM8994_FLL_SRC_BCLK:
1852                 break;
1853         default:
1854                 return -EINVAL;
1855         }
1856
1857         /* Are we changing anything? */
1858         if (wm8994->fll[id].src == src &&
1859             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1860                 return 0;
1861
1862         /* If we're stopping the FLL redo the old config - no
1863          * registers will actually be written but we avoid GCC flow
1864          * analysis bugs spewing warnings.
1865          */
1866         if (freq_out)
1867                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1868         else
1869                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1870                                             wm8994->fll[id].out);
1871         if (ret < 0)
1872                 return ret;
1873
1874         /* Gate the AIF clocks while we reclock */
1875         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1876                             WM8994_AIF1CLK_ENA, 0);
1877         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1878                             WM8994_AIF2CLK_ENA, 0);
1879
1880         /* We always need to disable the FLL while reconfiguring */
1881         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1882                             WM8994_FLL1_ENA, 0);
1883
1884         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1885                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1886         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1887                             WM8994_FLL1_OUTDIV_MASK |
1888                             WM8994_FLL1_FRATIO_MASK, reg);
1889
1890         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1891
1892         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1893                             WM8994_FLL1_N_MASK,
1894                                     fll.n << WM8994_FLL1_N_SHIFT);
1895
1896         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1897                             WM8994_FLL1_REFCLK_DIV_MASK |
1898                             WM8994_FLL1_REFCLK_SRC_MASK,
1899                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1900                             (src - 1));
1901
1902         /* Clear any pending completion from a previous failure */
1903         try_wait_for_completion(&wm8994->fll_locked[id]);
1904
1905         /* Enable (with fractional mode if required) */
1906         if (freq_out) {
1907                 /* Enable VMID if we need it */
1908                 if (!was_enabled) {
1909                         active_reference(codec);
1910
1911                         switch (control->type) {
1912                         case WM8994:
1913                                 vmid_reference(codec);
1914                                 break;
1915                         case WM8958:
1916                                 if (wm8994->revision < 1)
1917                                         vmid_reference(codec);
1918                                 break;
1919                         default:
1920                                 break;
1921                         }
1922                 }
1923
1924                 if (fll.k)
1925                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1926                 else
1927                         reg = WM8994_FLL1_ENA;
1928                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1929                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1930                                     reg);
1931
1932                 if (wm8994->fll_locked_irq) {
1933                         timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1934                                                               msecs_to_jiffies(10));
1935                         if (timeout == 0)
1936                                 dev_warn(codec->dev,
1937                                          "Timed out waiting for FLL lock\n");
1938                 } else {
1939                         msleep(5);
1940                 }
1941         } else {
1942                 if (was_enabled) {
1943                         switch (control->type) {
1944                         case WM8994:
1945                                 vmid_dereference(codec);
1946                                 break;
1947                         case WM8958:
1948                                 if (wm8994->revision < 1)
1949                                         vmid_dereference(codec);
1950                                 break;
1951                         default:
1952                                 break;
1953                         }
1954
1955                         active_dereference(codec);
1956                 }
1957         }
1958
1959         wm8994->fll[id].in = freq_in;
1960         wm8994->fll[id].out = freq_out;
1961         wm8994->fll[id].src = src;
1962
1963         /* Enable any gated AIF clocks */
1964         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1965                             WM8994_AIF1CLK_ENA, aif1);
1966         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1967                             WM8994_AIF2CLK_ENA, aif2);
1968
1969         configure_clock(codec);
1970
1971         return 0;
1972 }
1973
1974 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1975 {
1976         struct completion *completion = data;
1977
1978         complete(completion);
1979
1980         return IRQ_HANDLED;
1981 }
1982
1983 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1984
1985 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1986                           unsigned int freq_in, unsigned int freq_out)
1987 {
1988         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1989 }
1990
1991 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1992                 int clk_id, unsigned int freq, int dir)
1993 {
1994         struct snd_soc_codec *codec = dai->codec;
1995         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1996         int i;
1997
1998         switch (dai->id) {
1999         case 1:
2000         case 2:
2001                 break;
2002
2003         default:
2004                 /* AIF3 shares clocking with AIF1/2 */
2005                 return -EINVAL;
2006         }
2007
2008         switch (clk_id) {
2009         case WM8994_SYSCLK_MCLK1:
2010                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2011                 wm8994->mclk[0] = freq;
2012                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2013                         dai->id, freq);
2014                 break;
2015
2016         case WM8994_SYSCLK_MCLK2:
2017                 /* TODO: Set GPIO AF */
2018                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2019                 wm8994->mclk[1] = freq;
2020                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2021                         dai->id, freq);
2022                 break;
2023
2024         case WM8994_SYSCLK_FLL1:
2025                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2026                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2027                 break;
2028
2029         case WM8994_SYSCLK_FLL2:
2030                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2031                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2032                 break;
2033
2034         case WM8994_SYSCLK_OPCLK:
2035                 /* Special case - a division (times 10) is given and
2036                  * no effect on main clocking.
2037                  */
2038                 if (freq) {
2039                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2040                                 if (opclk_divs[i] == freq)
2041                                         break;
2042                         if (i == ARRAY_SIZE(opclk_divs))
2043                                 return -EINVAL;
2044                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2045                                             WM8994_OPCLK_DIV_MASK, i);
2046                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2047                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2048                 } else {
2049                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2050                                             WM8994_OPCLK_ENA, 0);
2051                 }
2052
2053         default:
2054                 return -EINVAL;
2055         }
2056
2057         configure_clock(codec);
2058
2059         return 0;
2060 }
2061
2062 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2063                                  enum snd_soc_bias_level level)
2064 {
2065         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2066         struct wm8994 *control = wm8994->wm8994;
2067
2068         switch (level) {
2069         case SND_SOC_BIAS_ON:
2070                 break;
2071
2072         case SND_SOC_BIAS_PREPARE:
2073                 /* MICBIAS into regulating mode */
2074                 switch (control->type) {
2075                 case WM8958:
2076                 case WM1811:
2077                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2078                                             WM8958_MICB1_MODE, 0);
2079                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2080                                             WM8958_MICB2_MODE, 0);
2081                         break;
2082                 default:
2083                         break;
2084                 }
2085
2086                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2087                         active_reference(codec);
2088                 break;
2089
2090         case SND_SOC_BIAS_STANDBY:
2091                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2092                         switch (control->type) {
2093                         case WM8994:
2094                                 if (wm8994->revision < 4) {
2095                                         /* Tweak DC servo and DSP
2096                                          * configuration for improved
2097                                          * performance. */
2098                                         snd_soc_write(codec, 0x102, 0x3);
2099                                         snd_soc_write(codec, 0x56, 0x3);
2100                                         snd_soc_write(codec, 0x817, 0);
2101                                         snd_soc_write(codec, 0x102, 0);
2102                                 }
2103                                 break;
2104
2105                         case WM8958:
2106                                 if (wm8994->revision == 0) {
2107                                         /* Optimise performance for rev A */
2108                                         snd_soc_write(codec, 0x102, 0x3);
2109                                         snd_soc_write(codec, 0xcb, 0x81);
2110                                         snd_soc_write(codec, 0x817, 0);
2111                                         snd_soc_write(codec, 0x102, 0);
2112
2113                                         snd_soc_update_bits(codec,
2114                                                             WM8958_CHARGE_PUMP_2,
2115                                                             WM8958_CP_DISCH,
2116                                                             WM8958_CP_DISCH);
2117                                 }
2118                                 break;
2119
2120                         case WM1811:
2121                                 if (wm8994->revision < 2) {
2122                                         snd_soc_write(codec, 0x102, 0x3);
2123                                         snd_soc_write(codec, 0x5d, 0x7e);
2124                                         snd_soc_write(codec, 0x5e, 0x0);
2125                                         snd_soc_write(codec, 0x102, 0x0);
2126                                 }
2127                                 break;
2128                         }
2129
2130                         /* Discharge LINEOUT1 & 2 */
2131                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2132                                             WM8994_LINEOUT1_DISCH |
2133                                             WM8994_LINEOUT2_DISCH,
2134                                             WM8994_LINEOUT1_DISCH |
2135                                             WM8994_LINEOUT2_DISCH);
2136                 }
2137
2138                 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2139                         active_dereference(codec);
2140
2141                 /* MICBIAS into bypass mode on newer devices */
2142                 switch (control->type) {
2143                 case WM8958:
2144                 case WM1811:
2145                         snd_soc_update_bits(codec, WM8958_MICBIAS1,
2146                                             WM8958_MICB1_MODE,
2147                                             WM8958_MICB1_MODE);
2148                         snd_soc_update_bits(codec, WM8958_MICBIAS2,
2149                                             WM8958_MICB2_MODE,
2150                                             WM8958_MICB2_MODE);
2151                         break;
2152                 default:
2153                         break;
2154                 }
2155                 break;
2156
2157         case SND_SOC_BIAS_OFF:
2158                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2159                         wm8994->cur_fw = NULL;
2160                 break;
2161         }
2162         codec->dapm.bias_level = level;
2163
2164         return 0;
2165 }
2166
2167 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2168 {
2169         struct snd_soc_codec *codec = dai->codec;
2170         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2171         struct wm8994 *control = wm8994->wm8994;
2172         int ms_reg;
2173         int aif1_reg;
2174         int ms = 0;
2175         int aif1 = 0;
2176
2177         switch (dai->id) {
2178         case 1:
2179                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2180                 aif1_reg = WM8994_AIF1_CONTROL_1;
2181                 break;
2182         case 2:
2183                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2184                 aif1_reg = WM8994_AIF2_CONTROL_1;
2185                 break;
2186         default:
2187                 return -EINVAL;
2188         }
2189
2190         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2191         case SND_SOC_DAIFMT_CBS_CFS:
2192                 break;
2193         case SND_SOC_DAIFMT_CBM_CFM:
2194                 ms = WM8994_AIF1_MSTR;
2195                 break;
2196         default:
2197                 return -EINVAL;
2198         }
2199
2200         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2201         case SND_SOC_DAIFMT_DSP_B:
2202                 aif1 |= WM8994_AIF1_LRCLK_INV;
2203         case SND_SOC_DAIFMT_DSP_A:
2204                 aif1 |= 0x18;
2205                 break;
2206         case SND_SOC_DAIFMT_I2S:
2207                 aif1 |= 0x10;
2208                 break;
2209         case SND_SOC_DAIFMT_RIGHT_J:
2210                 break;
2211         case SND_SOC_DAIFMT_LEFT_J:
2212                 aif1 |= 0x8;
2213                 break;
2214         default:
2215                 return -EINVAL;
2216         }
2217
2218         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2219         case SND_SOC_DAIFMT_DSP_A:
2220         case SND_SOC_DAIFMT_DSP_B:
2221                 /* frame inversion not valid for DSP modes */
2222                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2223                 case SND_SOC_DAIFMT_NB_NF:
2224                         break;
2225                 case SND_SOC_DAIFMT_IB_NF:
2226                         aif1 |= WM8994_AIF1_BCLK_INV;
2227                         break;
2228                 default:
2229                         return -EINVAL;
2230                 }
2231                 break;
2232
2233         case SND_SOC_DAIFMT_I2S:
2234         case SND_SOC_DAIFMT_RIGHT_J:
2235         case SND_SOC_DAIFMT_LEFT_J:
2236                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2237                 case SND_SOC_DAIFMT_NB_NF:
2238                         break;
2239                 case SND_SOC_DAIFMT_IB_IF:
2240                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2241                         break;
2242                 case SND_SOC_DAIFMT_IB_NF:
2243                         aif1 |= WM8994_AIF1_BCLK_INV;
2244                         break;
2245                 case SND_SOC_DAIFMT_NB_IF:
2246                         aif1 |= WM8994_AIF1_LRCLK_INV;
2247                         break;
2248                 default:
2249                         return -EINVAL;
2250                 }
2251                 break;
2252         default:
2253                 return -EINVAL;
2254         }
2255
2256         /* The AIF2 format configuration needs to be mirrored to AIF3
2257          * on WM8958 if it's in use so just do it all the time. */
2258         switch (control->type) {
2259         case WM1811:
2260         case WM8958:
2261                 if (dai->id == 2)
2262                         snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2263                                             WM8994_AIF1_LRCLK_INV |
2264                                             WM8958_AIF3_FMT_MASK, aif1);
2265                 break;
2266
2267         default:
2268                 break;
2269         }
2270
2271         snd_soc_update_bits(codec, aif1_reg,
2272                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2273                             WM8994_AIF1_FMT_MASK,
2274                             aif1);
2275         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2276                             ms);
2277
2278         return 0;
2279 }
2280
2281 static struct {
2282         int val, rate;
2283 } srs[] = {
2284         { 0,   8000 },
2285         { 1,  11025 },
2286         { 2,  12000 },
2287         { 3,  16000 },
2288         { 4,  22050 },
2289         { 5,  24000 },
2290         { 6,  32000 },
2291         { 7,  44100 },
2292         { 8,  48000 },
2293         { 9,  88200 },
2294         { 10, 96000 },
2295 };
2296
2297 static int fs_ratios[] = {
2298         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2299 };
2300
2301 static int bclk_divs[] = {
2302         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2303         640, 880, 960, 1280, 1760, 1920
2304 };
2305
2306 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2307                             struct snd_pcm_hw_params *params,
2308                             struct snd_soc_dai *dai)
2309 {
2310         struct snd_soc_codec *codec = dai->codec;
2311         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2312         int aif1_reg;
2313         int aif2_reg;
2314         int bclk_reg;
2315         int lrclk_reg;
2316         int rate_reg;
2317         int aif1 = 0;
2318         int aif2 = 0;
2319         int bclk = 0;
2320         int lrclk = 0;
2321         int rate_val = 0;
2322         int id = dai->id - 1;
2323
2324         int i, cur_val, best_val, bclk_rate, best;
2325
2326         switch (dai->id) {
2327         case 1:
2328                 aif1_reg = WM8994_AIF1_CONTROL_1;
2329                 aif2_reg = WM8994_AIF1_CONTROL_2;
2330                 bclk_reg = WM8994_AIF1_BCLK;
2331                 rate_reg = WM8994_AIF1_RATE;
2332                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2333                     wm8994->lrclk_shared[0]) {
2334                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2335                 } else {
2336                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2337                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2338                 }
2339                 break;
2340         case 2:
2341                 aif1_reg = WM8994_AIF2_CONTROL_1;
2342                 aif2_reg = WM8994_AIF2_CONTROL_2;
2343                 bclk_reg = WM8994_AIF2_BCLK;
2344                 rate_reg = WM8994_AIF2_RATE;
2345                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2346                     wm8994->lrclk_shared[1]) {
2347                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2348                 } else {
2349                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2350                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2351                 }
2352                 break;
2353         default:
2354                 return -EINVAL;
2355         }
2356
2357         bclk_rate = params_rate(params) * 2;
2358         switch (params_format(params)) {
2359         case SNDRV_PCM_FORMAT_S16_LE:
2360                 bclk_rate *= 16;
2361                 break;
2362         case SNDRV_PCM_FORMAT_S20_3LE:
2363                 bclk_rate *= 20;
2364                 aif1 |= 0x20;
2365                 break;
2366         case SNDRV_PCM_FORMAT_S24_LE:
2367                 bclk_rate *= 24;
2368                 aif1 |= 0x40;
2369                 break;
2370         case SNDRV_PCM_FORMAT_S32_LE:
2371                 bclk_rate *= 32;
2372                 aif1 |= 0x60;
2373                 break;
2374         default:
2375                 return -EINVAL;
2376         }
2377
2378         /* Try to find an appropriate sample rate; look for an exact match. */
2379         for (i = 0; i < ARRAY_SIZE(srs); i++)
2380                 if (srs[i].rate == params_rate(params))
2381                         break;
2382         if (i == ARRAY_SIZE(srs))
2383                 return -EINVAL;
2384         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2385
2386         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2387         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2388                 dai->id, wm8994->aifclk[id], bclk_rate);
2389
2390         if (params_channels(params) == 1 &&
2391             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2392                 aif2 |= WM8994_AIF1_MONO;
2393
2394         if (wm8994->aifclk[id] == 0) {
2395                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2396                 return -EINVAL;
2397         }
2398
2399         /* AIFCLK/fs ratio; look for a close match in either direction */
2400         best = 0;
2401         best_val = abs((fs_ratios[0] * params_rate(params))
2402                        - wm8994->aifclk[id]);
2403         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2404                 cur_val = abs((fs_ratios[i] * params_rate(params))
2405                               - wm8994->aifclk[id]);
2406                 if (cur_val >= best_val)
2407                         continue;
2408                 best = i;
2409                 best_val = cur_val;
2410         }
2411         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2412                 dai->id, fs_ratios[best]);
2413         rate_val |= best;
2414
2415         /* We may not get quite the right frequency if using
2416          * approximate clocks so look for the closest match that is
2417          * higher than the target (we need to ensure that there enough
2418          * BCLKs to clock out the samples).
2419          */
2420         best = 0;
2421         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2422                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2423                 if (cur_val < 0) /* BCLK table is sorted */
2424                         break;
2425                 best = i;
2426         }
2427         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2428         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2429                 bclk_divs[best], bclk_rate);
2430         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2431
2432         lrclk = bclk_rate / params_rate(params);
2433         if (!lrclk) {
2434                 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2435                         bclk_rate);
2436                 return -EINVAL;
2437         }
2438         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2439                 lrclk, bclk_rate / lrclk);
2440
2441         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2442         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2443         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2444         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2445                             lrclk);
2446         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2447                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2448
2449         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2450                 switch (dai->id) {
2451                 case 1:
2452                         wm8994->dac_rates[0] = params_rate(params);
2453                         wm8994_set_retune_mobile(codec, 0);
2454                         wm8994_set_retune_mobile(codec, 1);
2455                         break;
2456                 case 2:
2457                         wm8994->dac_rates[1] = params_rate(params);
2458                         wm8994_set_retune_mobile(codec, 2);
2459                         break;
2460                 }
2461         }
2462
2463         return 0;
2464 }
2465
2466 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2467                                  struct snd_pcm_hw_params *params,
2468                                  struct snd_soc_dai *dai)
2469 {
2470         struct snd_soc_codec *codec = dai->codec;
2471         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2472         struct wm8994 *control = wm8994->wm8994;
2473         int aif1_reg;
2474         int aif1 = 0;
2475
2476         switch (dai->id) {
2477         case 3:
2478                 switch (control->type) {
2479                 case WM1811:
2480                 case WM8958:
2481                         aif1_reg = WM8958_AIF3_CONTROL_1;
2482                         break;
2483                 default:
2484                         return 0;
2485                 }
2486         default:
2487                 return 0;
2488         }
2489
2490         switch (params_format(params)) {
2491         case SNDRV_PCM_FORMAT_S16_LE:
2492                 break;
2493         case SNDRV_PCM_FORMAT_S20_3LE:
2494                 aif1 |= 0x20;
2495                 break;
2496         case SNDRV_PCM_FORMAT_S24_LE:
2497                 aif1 |= 0x40;
2498                 break;
2499         case SNDRV_PCM_FORMAT_S32_LE:
2500                 aif1 |= 0x60;
2501                 break;
2502         default:
2503                 return -EINVAL;
2504         }
2505
2506         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2507 }
2508
2509 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2510                                 struct snd_soc_dai *dai)
2511 {
2512         struct snd_soc_codec *codec = dai->codec;
2513         int rate_reg = 0;
2514
2515         switch (dai->id) {
2516         case 1:
2517                 rate_reg = WM8994_AIF1_RATE;
2518                 break;
2519         case 2:
2520                 rate_reg = WM8994_AIF2_RATE;
2521                 break;
2522         default:
2523                 break;
2524         }
2525
2526         /* If the DAI is idle then configure the divider tree for the
2527          * lowest output rate to save a little power if the clock is
2528          * still active (eg, because it is system clock).
2529          */
2530         if (rate_reg && !dai->playback_active && !dai->capture_active)
2531                 snd_soc_update_bits(codec, rate_reg,
2532                                     WM8994_AIF1_SR_MASK |
2533                                     WM8994_AIF1CLK_RATE_MASK, 0x9);
2534 }
2535
2536 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2537 {
2538         struct snd_soc_codec *codec = codec_dai->codec;
2539         int mute_reg;
2540         int reg;
2541
2542         switch (codec_dai->id) {
2543         case 1:
2544                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2545                 break;
2546         case 2:
2547                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2548                 break;
2549         default:
2550                 return -EINVAL;
2551         }
2552
2553         if (mute)
2554                 reg = WM8994_AIF1DAC1_MUTE;
2555         else
2556                 reg = 0;
2557
2558         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2559
2560         return 0;
2561 }
2562
2563 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2564 {
2565         struct snd_soc_codec *codec = codec_dai->codec;
2566         int reg, val, mask;
2567
2568         switch (codec_dai->id) {
2569         case 1:
2570                 reg = WM8994_AIF1_MASTER_SLAVE;
2571                 mask = WM8994_AIF1_TRI;
2572                 break;
2573         case 2:
2574                 reg = WM8994_AIF2_MASTER_SLAVE;
2575                 mask = WM8994_AIF2_TRI;
2576                 break;
2577         case 3:
2578                 reg = WM8994_POWER_MANAGEMENT_6;
2579                 mask = WM8994_AIF3_TRI;
2580                 break;
2581         default:
2582                 return -EINVAL;
2583         }
2584
2585         if (tristate)
2586                 val = mask;
2587         else
2588                 val = 0;
2589
2590         return snd_soc_update_bits(codec, reg, mask, val);
2591 }
2592
2593 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2594 {
2595         struct snd_soc_codec *codec = dai->codec;
2596
2597         /* Disable the pulls on the AIF if we're using it to save power. */
2598         snd_soc_update_bits(codec, WM8994_GPIO_3,
2599                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2600         snd_soc_update_bits(codec, WM8994_GPIO_4,
2601                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2602         snd_soc_update_bits(codec, WM8994_GPIO_5,
2603                             WM8994_GPN_PU | WM8994_GPN_PD, 0);
2604
2605         return 0;
2606 }
2607
2608 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2609
2610 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2611                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2612
2613 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2614         .set_sysclk     = wm8994_set_dai_sysclk,
2615         .set_fmt        = wm8994_set_dai_fmt,
2616         .hw_params      = wm8994_hw_params,
2617         .shutdown       = wm8994_aif_shutdown,
2618         .digital_mute   = wm8994_aif_mute,
2619         .set_pll        = wm8994_set_fll,
2620         .set_tristate   = wm8994_set_tristate,
2621 };
2622
2623 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2624         .set_sysclk     = wm8994_set_dai_sysclk,
2625         .set_fmt        = wm8994_set_dai_fmt,
2626         .hw_params      = wm8994_hw_params,
2627         .shutdown       = wm8994_aif_shutdown,
2628         .digital_mute   = wm8994_aif_mute,
2629         .set_pll        = wm8994_set_fll,
2630         .set_tristate   = wm8994_set_tristate,
2631 };
2632
2633 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2634         .hw_params      = wm8994_aif3_hw_params,
2635         .set_tristate   = wm8994_set_tristate,
2636 };
2637
2638 static struct snd_soc_dai_driver wm8994_dai[] = {
2639         {
2640                 .name = "wm8994-aif1",
2641                 .id = 1,
2642                 .playback = {
2643                         .stream_name = "AIF1 Playback",
2644                         .channels_min = 1,
2645                         .channels_max = 2,
2646                         .rates = WM8994_RATES,
2647                         .formats = WM8994_FORMATS,
2648                         .sig_bits = 24,
2649                 },
2650                 .capture = {
2651                         .stream_name = "AIF1 Capture",
2652                         .channels_min = 1,
2653                         .channels_max = 2,
2654                         .rates = WM8994_RATES,
2655                         .formats = WM8994_FORMATS,
2656                         .sig_bits = 24,
2657                  },
2658                 .ops = &wm8994_aif1_dai_ops,
2659         },
2660         {
2661                 .name = "wm8994-aif2",
2662                 .id = 2,
2663                 .playback = {
2664                         .stream_name = "AIF2 Playback",
2665                         .channels_min = 1,
2666                         .channels_max = 2,
2667                         .rates = WM8994_RATES,
2668                         .formats = WM8994_FORMATS,
2669                         .sig_bits = 24,
2670                 },
2671                 .capture = {
2672                         .stream_name = "AIF2 Capture",
2673                         .channels_min = 1,
2674                         .channels_max = 2,
2675                         .rates = WM8994_RATES,
2676                         .formats = WM8994_FORMATS,
2677                         .sig_bits = 24,
2678                 },
2679                 .probe = wm8994_aif2_probe,
2680                 .ops = &wm8994_aif2_dai_ops,
2681         },
2682         {
2683                 .name = "wm8994-aif3",
2684                 .id = 3,
2685                 .playback = {
2686                         .stream_name = "AIF3 Playback",
2687                         .channels_min = 1,
2688                         .channels_max = 2,
2689                         .rates = WM8994_RATES,
2690                         .formats = WM8994_FORMATS,
2691                         .sig_bits = 24,
2692                 },
2693                 .capture = {
2694                         .stream_name = "AIF3 Capture",
2695                         .channels_min = 1,
2696                         .channels_max = 2,
2697                         .rates = WM8994_RATES,
2698                         .formats = WM8994_FORMATS,
2699                         .sig_bits = 24,
2700                  },
2701                 .ops = &wm8994_aif3_dai_ops,
2702         }
2703 };
2704
2705 #ifdef CONFIG_PM
2706 static int wm8994_suspend(struct snd_soc_codec *codec)
2707 {
2708         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2709         struct wm8994 *control = wm8994->wm8994;
2710         int i, ret;
2711
2712         switch (control->type) {
2713         case WM8994:
2714                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2715                 break;
2716         case WM1811:
2717                 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2718                                     WM1811_JACKDET_MODE_MASK, 0);
2719                 /* Fall through */
2720         case WM8958:
2721                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2722                                     WM8958_MICD_ENA, 0);
2723                 break;
2724         }
2725
2726         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2727                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2728                        sizeof(struct wm8994_fll_config));
2729                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2730                 if (ret < 0)
2731                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2732                                  i + 1, ret);
2733         }
2734
2735         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2736
2737         return 0;
2738 }
2739
2740 static int wm8994_resume(struct snd_soc_codec *codec)
2741 {
2742         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2743         struct wm8994 *control = wm8994->wm8994;
2744         int i, ret;
2745         unsigned int val, mask;
2746
2747         if (wm8994->revision < 4) {
2748                 /* force a HW read */
2749                 ret = regmap_read(control->regmap,
2750                                   WM8994_POWER_MANAGEMENT_5, &val);
2751
2752                 /* modify the cache only */
2753                 codec->cache_only = 1;
2754                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2755                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2756                 val &= mask;
2757                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2758                                     mask, val);
2759                 codec->cache_only = 0;
2760         }
2761
2762         /* Restore the registers */
2763         ret = snd_soc_cache_sync(codec);
2764         if (ret != 0)
2765                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2766
2767         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2768
2769         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2770                 if (!wm8994->fll_suspend[i].out)
2771                         continue;
2772
2773                 ret = _wm8994_set_fll(codec, i + 1,
2774                                      wm8994->fll_suspend[i].src,
2775                                      wm8994->fll_suspend[i].in,
2776                                      wm8994->fll_suspend[i].out);
2777                 if (ret < 0)
2778                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2779                                  i + 1, ret);
2780         }
2781
2782         switch (control->type) {
2783         case WM8994:
2784                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2785                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2786                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2787                 break;
2788         case WM1811:
2789                 if (wm8994->jackdet && wm8994->jack_cb) {
2790                         /* Restart from idle */
2791                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2792                                             WM1811_JACKDET_MODE_MASK,
2793                                             WM1811_JACKDET_MODE_JACK);
2794                         break;
2795                 }
2796         case WM8958:
2797                 if (wm8994->jack_cb)
2798                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2799                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2800                 break;
2801         }
2802
2803         return 0;
2804 }
2805 #else
2806 #define wm8994_suspend NULL
2807 #define wm8994_resume NULL
2808 #endif
2809
2810 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2811 {
2812         struct snd_soc_codec *codec = wm8994->codec;
2813         struct wm8994_pdata *pdata = wm8994->pdata;
2814         struct snd_kcontrol_new controls[] = {
2815                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2816                              wm8994->retune_mobile_enum,
2817                              wm8994_get_retune_mobile_enum,
2818                              wm8994_put_retune_mobile_enum),
2819                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2820                              wm8994->retune_mobile_enum,
2821                              wm8994_get_retune_mobile_enum,
2822                              wm8994_put_retune_mobile_enum),
2823                 SOC_ENUM_EXT("AIF2 EQ Mode",
2824                              wm8994->retune_mobile_enum,
2825                              wm8994_get_retune_mobile_enum,
2826                              wm8994_put_retune_mobile_enum),
2827         };
2828         int ret, i, j;
2829         const char **t;
2830
2831         /* We need an array of texts for the enum API but the number
2832          * of texts is likely to be less than the number of
2833          * configurations due to the sample rate dependency of the
2834          * configurations. */
2835         wm8994->num_retune_mobile_texts = 0;
2836         wm8994->retune_mobile_texts = NULL;
2837         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2838                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2839                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2840                                    wm8994->retune_mobile_texts[j]) == 0)
2841                                 break;
2842                 }
2843
2844                 if (j != wm8994->num_retune_mobile_texts)
2845                         continue;
2846
2847                 /* Expand the array... */
2848                 t = krealloc(wm8994->retune_mobile_texts,
2849                              sizeof(char *) *
2850                              (wm8994->num_retune_mobile_texts + 1),
2851                              GFP_KERNEL);
2852                 if (t == NULL)
2853                         continue;
2854
2855                 /* ...store the new entry... */
2856                 t[wm8994->num_retune_mobile_texts] =
2857                         pdata->retune_mobile_cfgs[i].name;
2858
2859                 /* ...and remember the new version. */
2860                 wm8994->num_retune_mobile_texts++;
2861                 wm8994->retune_mobile_texts = t;
2862         }
2863
2864         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2865                 wm8994->num_retune_mobile_texts);
2866
2867         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2868         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2869
2870         ret = snd_soc_add_codec_controls(wm8994->codec, controls,
2871                                    ARRAY_SIZE(controls));
2872         if (ret != 0)
2873                 dev_err(wm8994->codec->dev,
2874                         "Failed to add ReTune Mobile controls: %d\n", ret);
2875 }
2876
2877 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2878 {
2879         struct snd_soc_codec *codec = wm8994->codec;
2880         struct wm8994_pdata *pdata = wm8994->pdata;
2881         int ret, i;
2882
2883         if (!pdata)
2884                 return;
2885
2886         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2887                                       pdata->lineout2_diff,
2888                                       pdata->lineout1fb,
2889                                       pdata->lineout2fb,
2890                                       pdata->jd_scthr,
2891                                       pdata->jd_thr,
2892                                       pdata->micbias1_lvl,
2893                                       pdata->micbias2_lvl);
2894
2895         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2896
2897         if (pdata->num_drc_cfgs) {
2898                 struct snd_kcontrol_new controls[] = {
2899                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2900                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2901                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2902                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2903                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2904                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2905                 };
2906
2907                 /* We need an array of texts for the enum API */
2908                 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2909                             sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
2910                 if (!wm8994->drc_texts) {
2911                         dev_err(wm8994->codec->dev,
2912                                 "Failed to allocate %d DRC config texts\n",
2913                                 pdata->num_drc_cfgs);
2914                         return;
2915                 }
2916
2917                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2918                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2919
2920                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2921                 wm8994->drc_enum.texts = wm8994->drc_texts;
2922
2923                 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
2924                                            ARRAY_SIZE(controls));
2925                 if (ret != 0)
2926                         dev_err(wm8994->codec->dev,
2927                                 "Failed to add DRC mode controls: %d\n", ret);
2928
2929                 for (i = 0; i < WM8994_NUM_DRC; i++)
2930                         wm8994_set_drc(codec, i);
2931         }
2932
2933         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2934                 pdata->num_retune_mobile_cfgs);
2935
2936         if (pdata->num_retune_mobile_cfgs)
2937                 wm8994_handle_retune_mobile_pdata(wm8994);
2938         else
2939                 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
2940                                      ARRAY_SIZE(wm8994_eq_controls));
2941
2942         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2943                 if (pdata->micbias[i]) {
2944                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2945                                 pdata->micbias[i] & 0xffff);
2946                 }
2947         }
2948 }
2949
2950 /**
2951  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2952  *
2953  * @codec:   WM8994 codec
2954  * @jack:    jack to report detection events on
2955  * @micbias: microphone bias to detect on
2956  * @det:     value to report for presence detection
2957  * @shrt:    value to report for short detection
2958  *
2959  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2960  * being used to bring out signals to the processor then only platform
2961  * data configuration is needed for WM8994 and processor GPIOs should
2962  * be configured using snd_soc_jack_add_gpios() instead.
2963  *
2964  * Configuration of detection levels is available via the micbias1_lvl
2965  * and micbias2_lvl platform data members.
2966  */
2967 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2968                       int micbias, int det, int shrt)
2969 {
2970         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2971         struct wm8994_micdet *micdet;
2972         struct wm8994 *control = wm8994->wm8994;
2973         int reg;
2974
2975         if (control->type != WM8994)
2976                 return -EINVAL;
2977
2978         switch (micbias) {
2979         case 1:
2980                 micdet = &wm8994->micdet[0];
2981                 break;
2982         case 2:
2983                 micdet = &wm8994->micdet[1];
2984                 break;
2985         default:
2986                 return -EINVAL;
2987         }
2988
2989         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2990                 micbias, det, shrt);
2991
2992         /* Store the configuration */
2993         micdet->jack = jack;
2994         micdet->det = det;
2995         micdet->shrt = shrt;
2996
2997         /* If either of the jacks is set up then enable detection */
2998         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2999                 reg = WM8994_MICD_ENA;
3000         else
3001                 reg = 0;
3002
3003         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3004
3005         return 0;
3006 }
3007 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3008
3009 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3010 {
3011         struct wm8994_priv *priv = data;
3012         struct snd_soc_codec *codec = priv->codec;
3013         int reg;
3014         int report;
3015
3016 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3017         trace_snd_soc_jack_irq(dev_name(codec->dev));
3018 #endif
3019
3020         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3021         if (reg < 0) {
3022                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3023                         reg);
3024                 return IRQ_HANDLED;
3025         }
3026
3027         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3028
3029         report = 0;
3030         if (reg & WM8994_MIC1_DET_STS)
3031                 report |= priv->micdet[0].det;
3032         if (reg & WM8994_MIC1_SHRT_STS)
3033                 report |= priv->micdet[0].shrt;
3034         snd_soc_jack_report(priv->micdet[0].jack, report,
3035                             priv->micdet[0].det | priv->micdet[0].shrt);
3036
3037         report = 0;
3038         if (reg & WM8994_MIC2_DET_STS)
3039                 report |= priv->micdet[1].det;
3040         if (reg & WM8994_MIC2_SHRT_STS)
3041                 report |= priv->micdet[1].shrt;
3042         snd_soc_jack_report(priv->micdet[1].jack, report,
3043                             priv->micdet[1].det | priv->micdet[1].shrt);
3044
3045         return IRQ_HANDLED;
3046 }
3047
3048 /* Default microphone detection handler for WM8958 - the user can
3049  * override this if they wish.
3050  */
3051 static void wm8958_default_micdet(u16 status, void *data)
3052 {
3053         struct snd_soc_codec *codec = data;
3054         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3055         int report;
3056
3057         dev_dbg(codec->dev, "MICDET %x\n", status);
3058
3059         /* Either nothing present or just starting detection */
3060         if (!(status & WM8958_MICD_STS)) {
3061                 if (!wm8994->jackdet) {
3062                         /* If nothing present then clear our statuses */
3063                         dev_dbg(codec->dev, "Detected open circuit\n");
3064                         wm8994->jack_mic = false;
3065                         wm8994->mic_detecting = true;
3066
3067                         wm8958_micd_set_rate(codec);
3068
3069                         snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3070                                             wm8994->btn_mask |
3071                                              SND_JACK_HEADSET);
3072                 }
3073                 return;
3074         }
3075
3076         /* If the measurement is showing a high impedence we've got a
3077          * microphone.
3078          */
3079         if (wm8994->mic_detecting && (status & 0x600)) {
3080                 dev_dbg(codec->dev, "Detected microphone\n");
3081
3082                 wm8994->mic_detecting = false;
3083                 wm8994->jack_mic = true;
3084
3085                 wm8958_micd_set_rate(codec);
3086
3087                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3088                                     SND_JACK_HEADSET);
3089         }
3090
3091
3092         if (wm8994->mic_detecting && status & 0xfc) {
3093                 dev_dbg(codec->dev, "Detected headphone\n");
3094                 wm8994->mic_detecting = false;
3095
3096                 wm8958_micd_set_rate(codec);
3097
3098                 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3099                                     SND_JACK_HEADSET);
3100
3101                 /* If we have jackdet that will detect removal */
3102                 if (wm8994->jackdet) {
3103                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3104                                             WM8958_MICD_ENA, 0);
3105
3106                         wm1811_jackdet_set_mode(codec,
3107                                                 WM1811_JACKDET_MODE_JACK);
3108                 }
3109         }
3110
3111         /* Report short circuit as a button */
3112         if (wm8994->jack_mic) {
3113                 report = 0;
3114                 if (status & 0x4)
3115                         report |= SND_JACK_BTN_0;
3116
3117                 if (status & 0x8)
3118                         report |= SND_JACK_BTN_1;
3119
3120                 if (status & 0x10)
3121                         report |= SND_JACK_BTN_2;
3122
3123                 if (status & 0x20)
3124                         report |= SND_JACK_BTN_3;
3125
3126                 if (status & 0x40)
3127                         report |= SND_JACK_BTN_4;
3128
3129                 if (status & 0x80)
3130                         report |= SND_JACK_BTN_5;
3131
3132                 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3133                                     wm8994->btn_mask);
3134         }
3135 }
3136
3137 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3138 {
3139         struct wm8994_priv *wm8994 = data;
3140         struct snd_soc_codec *codec = wm8994->codec;
3141         int reg;
3142
3143         mutex_lock(&wm8994->accdet_lock);
3144
3145         reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3146         if (reg < 0) {
3147                 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3148                 mutex_unlock(&wm8994->accdet_lock);
3149                 return IRQ_NONE;
3150         }
3151
3152         dev_dbg(codec->dev, "JACKDET %x\n", reg);
3153
3154         if (reg & WM1811_JACKDET_LVL) {
3155                 dev_dbg(codec->dev, "Jack detected\n");
3156
3157                 snd_soc_jack_report(wm8994->micdet[0].jack,
3158                                     SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3159
3160                 /*
3161                  * Start off measument of microphone impedence to find
3162                  * out what's actually there.
3163                  */
3164                 wm8994->mic_detecting = true;
3165                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3166                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3167                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
3168         } else {
3169                 dev_dbg(codec->dev, "Jack not detected\n");
3170
3171                 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3172                                     SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3173                                     wm8994->btn_mask);
3174
3175                 wm8994->mic_detecting = false;
3176                 wm8994->jack_mic = false;
3177                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3178                                     WM8958_MICD_ENA, 0);
3179                 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3180         }
3181
3182         mutex_unlock(&wm8994->accdet_lock);
3183
3184         return IRQ_HANDLED;
3185 }
3186
3187 /**
3188  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3189  *
3190  * @codec:   WM8958 codec
3191  * @jack:    jack to report detection events on
3192  *
3193  * Enable microphone detection functionality for the WM8958.  By
3194  * default simple detection which supports the detection of up to 6
3195  * buttons plus video and microphone functionality is supported.
3196  *
3197  * The WM8958 has an advanced jack detection facility which is able to
3198  * support complex accessory detection, especially when used in
3199  * conjunction with external circuitry.  In order to provide maximum
3200  * flexiblity a callback is provided which allows a completely custom
3201  * detection algorithm.
3202  */
3203 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3204                       wm8958_micdet_cb cb, void *cb_data)
3205 {
3206         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3207         struct wm8994 *control = wm8994->wm8994;
3208         u16 micd_lvl_sel;
3209
3210         switch (control->type) {
3211         case WM1811:
3212         case WM8958:
3213                 break;
3214         default:
3215                 return -EINVAL;
3216         }
3217
3218         if (jack) {
3219                 if (!cb) {
3220                         dev_dbg(codec->dev, "Using default micdet callback\n");
3221                         cb = wm8958_default_micdet;
3222                         cb_data = codec;
3223                 }
3224
3225                 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3226
3227                 wm8994->micdet[0].jack = jack;
3228                 wm8994->jack_cb = cb;
3229                 wm8994->jack_cb_data = cb_data;
3230
3231                 wm8994->mic_detecting = true;
3232                 wm8994->jack_mic = false;
3233
3234                 wm8958_micd_set_rate(codec);
3235
3236                 /* Detect microphones and short circuits by default */
3237                 if (wm8994->pdata->micd_lvl_sel)
3238                         micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3239                 else
3240                         micd_lvl_sel = 0x41;
3241
3242                 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3243                         SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3244                         SND_JACK_BTN_4 | SND_JACK_BTN_5;
3245
3246                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3247                                     WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3248
3249                 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3250
3251                 /*
3252                  * If we can use jack detection start off with that,
3253                  * otherwise jump straight to microphone detection.
3254                  */
3255                 if (wm8994->jackdet) {
3256                         snd_soc_update_bits(codec, WM8994_LDO_1,
3257                                             WM8994_LDO1_DISCH, 0);
3258                         wm1811_jackdet_set_mode(codec,
3259                                                 WM1811_JACKDET_MODE_JACK);
3260                 } else {
3261                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3262                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
3263                 }
3264
3265         } else {
3266                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3267                                     WM8958_MICD_ENA, 0);
3268                 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3269         }
3270
3271         return 0;
3272 }
3273 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3274
3275 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3276 {
3277         struct wm8994_priv *wm8994 = data;
3278         struct snd_soc_codec *codec = wm8994->codec;
3279         int reg, count;
3280
3281         mutex_lock(&wm8994->accdet_lock);
3282
3283         /*
3284          * Jack detection may have detected a removal simulataneously
3285          * with an update of the MICDET status; if so it will have
3286          * stopped detection and we can ignore this interrupt.
3287          */
3288         if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3289                 mutex_unlock(&wm8994->accdet_lock);
3290                 return IRQ_HANDLED;
3291         }
3292
3293         /* We may occasionally read a detection without an impedence
3294          * range being provided - if that happens loop again.
3295          */
3296         count = 10;
3297         do {
3298                 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3299                 if (reg < 0) {
3300                         mutex_unlock(&wm8994->accdet_lock);
3301                         dev_err(codec->dev,
3302                                 "Failed to read mic detect status: %d\n",
3303                                 reg);
3304                         return IRQ_NONE;
3305                 }
3306
3307                 if (!(reg & WM8958_MICD_VALID)) {
3308                         dev_dbg(codec->dev, "Mic detect data not valid\n");
3309                         goto out;
3310                 }
3311
3312                 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3313                         break;
3314
3315                 msleep(1);
3316         } while (count--);
3317
3318         if (count == 0)
3319                 dev_warn(codec->dev, "No impedence range reported for jack\n");
3320
3321 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3322         trace_snd_soc_jack_irq(dev_name(codec->dev));
3323 #endif
3324
3325         if (wm8994->jack_cb)
3326                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3327         else
3328                 dev_warn(codec->dev, "Accessory detection with no callback\n");
3329
3330 out:
3331         mutex_unlock(&wm8994->accdet_lock);
3332
3333         return IRQ_HANDLED;
3334 }
3335
3336 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3337 {
3338         struct snd_soc_codec *codec = data;
3339
3340         dev_err(codec->dev, "FIFO error\n");
3341
3342         return IRQ_HANDLED;
3343 }
3344
3345 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3346 {
3347         struct snd_soc_codec *codec = data;
3348
3349         dev_err(codec->dev, "Thermal warning\n");
3350
3351         return IRQ_HANDLED;
3352 }
3353
3354 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3355 {
3356         struct snd_soc_codec *codec = data;
3357
3358         dev_crit(codec->dev, "Thermal shutdown\n");
3359
3360         return IRQ_HANDLED;
3361 }
3362
3363 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3364 {
3365         struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3366         struct wm8994_priv *wm8994;
3367         struct snd_soc_dapm_context *dapm = &codec->dapm;
3368         unsigned int reg;
3369         int ret, i;
3370
3371         codec->control_data = control->regmap;
3372
3373         wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3374                               GFP_KERNEL);
3375         if (wm8994 == NULL)
3376                 return -ENOMEM;
3377         snd_soc_codec_set_drvdata(codec, wm8994);
3378
3379         snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3380
3381         wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
3382         wm8994->pdata = dev_get_platdata(codec->dev->parent);
3383         wm8994->codec = codec;
3384
3385         mutex_init(&wm8994->accdet_lock);
3386
3387         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3388                 init_completion(&wm8994->fll_locked[i]);
3389
3390         if (wm8994->pdata && wm8994->pdata->micdet_irq)
3391                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3392         else if (wm8994->pdata && wm8994->pdata->irq_base)
3393                 wm8994->micdet_irq = wm8994->pdata->irq_base +
3394                                      WM8994_IRQ_MIC1_DET;
3395
3396         pm_runtime_enable(codec->dev);
3397         pm_runtime_resume(codec->dev);
3398
3399         /* By default use idle_bias_off, will override for WM8994 */
3400         codec->dapm.idle_bias_off = 1;
3401
3402         /* Set revision-specific configuration */
3403         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3404         switch (control->type) {
3405         case WM8994:
3406                 /* Single ended line outputs should have VMID on. */
3407                 if (!wm8994->pdata->lineout1_diff ||
3408                     !wm8994->pdata->lineout2_diff)
3409                         codec->dapm.idle_bias_off = 0;
3410
3411                 switch (wm8994->revision) {
3412                 case 2:
3413                 case 3:
3414                         wm8994->hubs.dcs_codes_l = -5;
3415                         wm8994->hubs.dcs_codes_r = -5;
3416                         wm8994->hubs.hp_startup_mode = 1;
3417                         wm8994->hubs.dcs_readback_mode = 1;
3418                         wm8994->hubs.series_startup = 1;
3419                         break;
3420                 default:
3421                         wm8994->hubs.dcs_readback_mode = 2;
3422                         break;
3423                 }
3424                 break;
3425
3426         case WM8958:
3427                 wm8994->hubs.dcs_readback_mode = 1;
3428                 break;
3429
3430         case WM1811:
3431                 wm8994->hubs.dcs_readback_mode = 2;
3432                 wm8994->hubs.no_series_update = 1;
3433
3434                 switch (wm8994->revision) {
3435                 case 0:
3436                 case 1:
3437                 case 2:
3438                 case 3:
3439                         wm8994->hubs.dcs_codes_l = -9;
3440                         wm8994->hubs.dcs_codes_r = -5;
3441                         break;
3442                 default:
3443                         break;
3444                 }
3445
3446                 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3447                                     WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3448                 break;
3449
3450         default:
3451                 break;
3452         }
3453
3454         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3455                            wm8994_fifo_error, "FIFO error", codec);
3456         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3457                            wm8994_temp_warn, "Thermal warning", codec);
3458         wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3459                            wm8994_temp_shut, "Thermal shutdown", codec);
3460
3461         ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3462                                  wm_hubs_dcs_done, "DC servo done",
3463                                  &wm8994->hubs);
3464         if (ret == 0)
3465                 wm8994->hubs.dcs_done_irq = true;
3466
3467         switch (control->type) {
3468         case WM8994:
3469                 if (wm8994->micdet_irq) {
3470                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3471                                                    wm8994_mic_irq,
3472                                                    IRQF_TRIGGER_RISING,
3473                                                    "Mic1 detect",
3474                                                    wm8994);
3475                         if (ret != 0)
3476                                 dev_warn(codec->dev,
3477                                          "Failed to request Mic1 detect IRQ: %d\n",
3478                                          ret);
3479                 }
3480
3481                 ret = wm8994_request_irq(wm8994->wm8994,
3482                                          WM8994_IRQ_MIC1_SHRT,
3483                                          wm8994_mic_irq, "Mic 1 short",
3484                                          wm8994);
3485                 if (ret != 0)
3486                         dev_warn(codec->dev,
3487                                  "Failed to request Mic1 short IRQ: %d\n",
3488                                  ret);
3489
3490                 ret = wm8994_request_irq(wm8994->wm8994,
3491                                          WM8994_IRQ_MIC2_DET,
3492                                          wm8994_mic_irq, "Mic 2 detect",
3493                                          wm8994);
3494                 if (ret != 0)
3495                         dev_warn(codec->dev,
3496                                  "Failed to request Mic2 detect IRQ: %d\n",
3497                                  ret);
3498
3499                 ret = wm8994_request_irq(wm8994->wm8994,
3500                                          WM8994_IRQ_MIC2_SHRT,
3501                                          wm8994_mic_irq, "Mic 2 short",
3502                                          wm8994);
3503                 if (ret != 0)
3504                         dev_warn(codec->dev,
3505                                  "Failed to request Mic2 short IRQ: %d\n",
3506                                  ret);
3507                 break;
3508
3509         case WM8958:
3510         case WM1811:
3511                 if (wm8994->micdet_irq) {
3512                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3513                                                    wm8958_mic_irq,
3514                                                    IRQF_TRIGGER_RISING,
3515                                                    "Mic detect",
3516                                                    wm8994);
3517                         if (ret != 0)
3518                                 dev_warn(codec->dev,
3519                                          "Failed to request Mic detect IRQ: %d\n",
3520                                          ret);
3521                 }
3522         }
3523
3524         switch (control->type) {
3525         case WM1811:
3526                 if (wm8994->revision > 1) {
3527                         ret = wm8994_request_irq(wm8994->wm8994,
3528                                                  WM8994_IRQ_GPIO(6),
3529                                                  wm1811_jackdet_irq, "JACKDET",
3530                                                  wm8994);
3531                         if (ret == 0)
3532                                 wm8994->jackdet = true;
3533                 }
3534                 break;
3535         default:
3536                 break;
3537         }
3538
3539         wm8994->fll_locked_irq = true;
3540         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3541                 ret = wm8994_request_irq(wm8994->wm8994,
3542                                          WM8994_IRQ_FLL1_LOCK + i,
3543                                          wm8994_fll_locked_irq, "FLL lock",
3544                                          &wm8994->fll_locked[i]);
3545                 if (ret != 0)
3546                         wm8994->fll_locked_irq = false;
3547         }
3548
3549         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
3550          * configured on init - if a system wants to do this dynamically
3551          * at runtime we can deal with that then.
3552          */
3553         ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
3554         if (ret < 0) {
3555                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3556                 goto err_irq;
3557         }
3558         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3559                 wm8994->lrclk_shared[0] = 1;
3560                 wm8994_dai[0].symmetric_rates = 1;
3561         } else {
3562                 wm8994->lrclk_shared[0] = 0;
3563         }
3564
3565         ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
3566         if (ret < 0) {
3567                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3568                 goto err_irq;
3569         }
3570         if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3571                 wm8994->lrclk_shared[1] = 1;
3572                 wm8994_dai[1].symmetric_rates = 1;
3573         } else {
3574                 wm8994->lrclk_shared[1] = 0;
3575         }
3576
3577         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3578
3579         /* Latch volume updates (right only; we always do left then right). */
3580         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3581                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3582         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3583                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3584         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3585                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3586         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3587                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3588         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3589                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3590         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3591                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3592         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3593                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3594         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3595                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3596         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3597                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3598         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3599                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3600         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3601                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3602         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3603                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3604         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3605                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3606         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3607                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3608         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3609                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3610         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3611                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3612
3613         /* Set the low bit of the 3D stereo depth so TLV matches */
3614         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3615                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3616                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3617         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3618                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3619                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3620         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3621                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3622                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3623
3624         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3625          * use this; it only affects behaviour on idle TDM clock
3626          * cycles. */
3627         switch (control->type) {
3628         case WM8994:
3629         case WM8958:
3630                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3631                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3632                 break;
3633         default:
3634                 break;
3635         }
3636
3637         /* Put MICBIAS into bypass mode by default on newer devices */
3638         switch (control->type) {
3639         case WM8958:
3640         case WM1811:
3641                 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3642                                     WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3643                 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3644                                     WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3645                 break;
3646         default:
3647                 break;
3648         }
3649
3650         wm8994_update_class_w(codec);
3651
3652         wm8994_handle_pdata(wm8994);
3653
3654         wm_hubs_add_analogue_controls(codec);
3655         snd_soc_add_codec_controls(codec, wm8994_snd_controls,
3656                              ARRAY_SIZE(wm8994_snd_controls));
3657         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3658                                   ARRAY_SIZE(wm8994_dapm_widgets));
3659
3660         switch (control->type) {
3661         case WM8994:
3662                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3663                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3664                 if (wm8994->revision < 4) {
3665                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3666                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3667                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3668                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3669                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3670                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3671                 } else {
3672                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3673                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3674                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3675                                                   ARRAY_SIZE(wm8994_adc_widgets));
3676                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3677                                                   ARRAY_SIZE(wm8994_dac_widgets));
3678                 }
3679                 break;
3680         case WM8958:
3681                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3682                                      ARRAY_SIZE(wm8958_snd_controls));
3683                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3684                                           ARRAY_SIZE(wm8958_dapm_widgets));
3685                 if (wm8994->revision < 1) {
3686                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3687                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3688                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3689                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3690                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3691                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3692                 } else {
3693                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3694                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3695                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3696                                                   ARRAY_SIZE(wm8994_adc_widgets));
3697                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3698                                                   ARRAY_SIZE(wm8994_dac_widgets));
3699                 }
3700                 break;
3701
3702         case WM1811:
3703                 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
3704                                      ARRAY_SIZE(wm8958_snd_controls));
3705                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3706                                           ARRAY_SIZE(wm8958_dapm_widgets));
3707                 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3708                                           ARRAY_SIZE(wm8994_lateclk_widgets));
3709                 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3710                                           ARRAY_SIZE(wm8994_adc_widgets));
3711                 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3712                                           ARRAY_SIZE(wm8994_dac_widgets));
3713                 break;
3714         }
3715
3716
3717         wm_hubs_add_analogue_routes(codec, 0, 0);
3718         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3719
3720         switch (control->type) {
3721         case WM8994:
3722                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3723                                         ARRAY_SIZE(wm8994_intercon));
3724
3725                 if (wm8994->revision < 4) {
3726                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3727                                                 ARRAY_SIZE(wm8994_revd_intercon));
3728                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3729                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3730                 } else {
3731                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3732                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3733                 }
3734                 break;
3735         case WM8958:
3736                 if (wm8994->revision < 1) {
3737                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3738                                                 ARRAY_SIZE(wm8994_revd_intercon));
3739                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3740                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3741                 } else {
3742                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3743                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3744                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3745                                                 ARRAY_SIZE(wm8958_intercon));
3746                 }
3747
3748                 wm8958_dsp2_init(codec);
3749                 break;
3750         case WM1811:
3751                 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3752                                         ARRAY_SIZE(wm8994_lateclk_intercon));
3753                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3754                                         ARRAY_SIZE(wm8958_intercon));
3755                 break;
3756         }
3757
3758         return 0;
3759
3760 err_irq:
3761         if (wm8994->jackdet)
3762                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3763         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3764         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3765         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
3766         if (wm8994->micdet_irq)
3767                 free_irq(wm8994->micdet_irq, wm8994);
3768         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3769                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3770                                 &wm8994->fll_locked[i]);
3771         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3772                         &wm8994->hubs);
3773         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3774         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3775         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3776
3777         return ret;
3778 }
3779
3780 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3781 {
3782         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3783         struct wm8994 *control = wm8994->wm8994;
3784         int i;
3785
3786         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3787
3788         pm_runtime_disable(codec->dev);
3789
3790         for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3791                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
3792                                 &wm8994->fll_locked[i]);
3793
3794         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3795                         &wm8994->hubs);
3796         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3797         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3798         wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
3799
3800         if (wm8994->jackdet)
3801                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3802
3803         switch (control->type) {
3804         case WM8994:
3805                 if (wm8994->micdet_irq)
3806                         free_irq(wm8994->micdet_irq, wm8994);
3807                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3808                                 wm8994);
3809                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3810                                 wm8994);
3811                 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3812                                 wm8994);
3813                 break;
3814
3815         case WM1811:
3816         case WM8958:
3817                 if (wm8994->micdet_irq)
3818                         free_irq(wm8994->micdet_irq, wm8994);
3819                 break;
3820         }
3821         if (wm8994->mbc)
3822                 release_firmware(wm8994->mbc);
3823         if (wm8994->mbc_vss)
3824                 release_firmware(wm8994->mbc_vss);
3825         if (wm8994->enh_eq)
3826                 release_firmware(wm8994->enh_eq);
3827         kfree(wm8994->retune_mobile_texts);
3828
3829         return 0;
3830 }
3831
3832 static int wm8994_soc_volatile(struct snd_soc_codec *codec,
3833                                unsigned int reg)
3834 {
3835         return true;
3836 }
3837
3838 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3839         .probe =        wm8994_codec_probe,
3840         .remove =       wm8994_codec_remove,
3841         .suspend =      wm8994_suspend,
3842         .resume =       wm8994_resume,
3843         .set_bias_level = wm8994_set_bias_level,
3844         .reg_cache_size = WM8994_MAX_REGISTER,
3845         .volatile_register = wm8994_soc_volatile,
3846 };
3847
3848 static int __devinit wm8994_probe(struct platform_device *pdev)
3849 {
3850         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3851                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3852 }
3853
3854 static int __devexit wm8994_remove(struct platform_device *pdev)
3855 {
3856         snd_soc_unregister_codec(&pdev->dev);
3857         return 0;
3858 }
3859
3860 static struct platform_driver wm8994_codec_driver = {
3861         .driver = {
3862                    .name = "wm8994-codec",
3863                    .owner = THIS_MODULE,
3864                    },
3865         .probe = wm8994_probe,
3866         .remove = __devexit_p(wm8994_remove),
3867 };
3868
3869 module_platform_driver(wm8994_codec_driver);
3870
3871 MODULE_DESCRIPTION("ASoC WM8994 driver");
3872 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3873 MODULE_LICENSE("GPL");
3874 MODULE_ALIAS("platform:wm8994-codec");