sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c -- WM8994 ALSA SoC audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  * Copyright 2005 Openedhand Ltd.
   6  *
   7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/platform_device.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/tlv.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29
  30 #include <mach/iomux.h>
  31 #include <mach/gpio.h>
  32
  33 #include "wm8994.h"
  34 #include <linux/miscdevice.h>
  35 #include <linux/circ_buf.h>
  36 #include <mach/spi_fpga.h>
  37
  38 /* If digital BB is used,open this define. */
  39 //#define PCM_BB
  40
  41 /* Open wm8994 with diferent ways. */
  42 //#define chinaone
  43 #define rk28SDK
  44
  45 /* Define what kind of digital BB is used. */
  46 #ifdef PCM_BB
  47 #define TD688_MODE
  48 //#define MU301_MODE
  49 //#define CHONGY_MODE
  50 //#define THINKWILL_M800_MODE
  51 #endif //PCM_BB
  52
  53 #if 1
  54 #define DBG(x...) printk(KERN_INFO x)
  55 #else
  56 #define DBG(x...) do { } while (0)
  57 #endif
  58 #define wm8994_mic_VCC 0x0010
  59 #define WM8994_DELAY 50
  60
  61 struct i2c_client *wm8994_client;
  62 //struct wm8994_board wm8994_codec_board_data;
  63 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate);
  64 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate);
  65
  66 enum wm8994_codec_mode
  67 {
  68   wm8994_AP_to_headset,
  69   wm8994_AP_to_speakers,
  70   wm8994_recorder_and_AP_to_headset,
  71   wm8994_recorder_and_AP_to_speakers,
  72   wm8994_FM_to_headset,
  73   wm8994_FM_to_headset_and_record,
  74   wm8994_FM_to_speakers,
  75   wm8994_FM_to_speakers_and_record,
  76   wm8994_handsetMIC_to_baseband_to_headset,
  77   wm8994_handsetMIC_to_baseband_to_headset_and_record,
  78   wm8994_mainMIC_to_baseband_to_earpiece,
  79   wm8994_mainMIC_to_baseband_to_earpiece_and_record,
  80   wm8994_mainMIC_to_baseband_to_speakers,
  81   wm8994_mainMIC_to_baseband_with_AP_to_speakers,
  82   wm8994_mainMIC_to_baseband_to_speakers_and_record,
  83   wm8994_BT_baseband,
  84   wm8994_BT_baseband_and_record,
  85   null
  86 };
  87
  88 /* wm8994_current_mode:save current wm8994 mode */
  89 unsigned char wm8994_current_mode=null;//,wm8994_mic_VCC=0x0000;
  90
  91 void wm8994_set_volume(unsigned char wm8994_mode,unsigned char volume,unsigned char max_volume);
  92
  93 enum stream_type_wm8994
  94 {
  95         VOICE_CALL      =0,
  96         BLUETOOTH_SCO,
  97 };
  98
  99 /* For voice device route set, add by phc  */
 100 enum VoiceDeviceSwitch
 101 {
 102         SPEAKER_INCALL,
 103         SPEAKER_NORMAL,
 104
 105         HEADSET_INCALL,
 106         HEADSET_NORMAL,
 107
 108         EARPIECE_INCALL,
 109         EARPIECE_NORMAL,
 110
 111         BLUETOOTH_SCO_INCALL,
 112         BLUETOOTH_SCO_NORMAL,
 113
 114         BLUETOOTH_A2DP_INCALL,
 115         BLUETOOTH_A2DP_NORMAL,
 116
 117         MIC_CAPTURE,
 118
 119         EARPIECE_RINGTONE,
 120         SPEAKER_RINGTONE,
 121         HEADSET_RINGTONE,
 122
 123         ALL_OPEN,
 124         ALL_CLOSED
 125 };
 126
 127
 128 #define call_maxvol 5
 129
 130 /* call_vol:  save all kinds of system volume value. */
 131 unsigned char call_vol=3;
 132 int vol;
 133 unsigned short headset_vol_table[6]     ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 134 unsigned short speakers_vol_table[6]    ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 135 unsigned short earpiece_vol_table[6]    ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 136 unsigned short BT_vol_table[6]          ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 137
 138 /*
 139  * wm8994 register cache
 140  * We can't read the WM8994 register space when we
 141  * are using 2 wire for device control, so we cache them instead.
 142  */
 143 static const u16 wm8994_reg[] = {
 144         0x0097, 0x0097, 0x0079, 0x0079,  /*  0 */
 145         0x0000, 0x0008, 0x0000, 0x000a,  /*  4 */
 146         0x0000, 0x0000, 0x00ff, 0x00ff,  /*  8 */
 147         0x000f, 0x000f, 0x0000, 0x0000,  /* 12 */
 148         0x0000, 0x007b, 0x0000, 0x0032,  /* 16 */
 149         0x0000, 0x00c3, 0x00c3, 0x00c0,  /* 20 */
 150         0x0000, 0x0000, 0x0000, 0x0000,  /* 24 */
 151         0x0000, 0x0000, 0x0000, 0x0000,  /* 28 */
 152         0x0000, 0x0000, 0x0050, 0x0050,  /* 32 */
 153         0x0050, 0x0050, 0x0050, 0x0050,  /* 36 */
 154         0x0079, 0x0079, 0x0079,          /* 40 */
 155 };
 156
 157 /* codec private data */
 158 struct wm8994_priv {
 159         unsigned int sysclk;
 160         struct snd_soc_codec codec;
 161         struct snd_pcm_hw_constraint_list *sysclk_constraints;
 162         u16 reg_cache[WM8994_NUM_REG];
 163 };
 164
 165 static int wm8994_read(unsigned short reg,unsigned short *value)
 166 {
 167         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values;
 168
 169         if (reg_recv_data(wm8994_client,&regs,&values,400000) > 0)
 170         {
 171                 *value=((values>>8)& 0x00FF)|((values<<8)&0xFF00);
 172                 return 0;
 173         }
 174
 175         printk("%s---line->%d:Codec read error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,*value);
 176
 177         return -EIO;
 178 }
 179
 180
 181 static int wm8994_write(unsigned short reg,unsigned short value)
 182 {
 183         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values=((value>>8)&0x00FF)|((value<<8)&0xFF00);
 184
 185         if (reg_send_data(wm8994_client,&regs,&values,400000) > 0)
 186                 return 0;
 187
 188         printk("%s---line->%d:Codec write error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,value);
 189
 190         return -EIO;
 191 }
 192
 193 #define wm8994_reset()  wm8994_write(WM8994_RESET, 0)
 194 void AP_to_headset(void)
 195 {
 196         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 197
 198         if(wm8994_current_mode==wm8994_AP_to_headset)return;
 199         wm8994_current_mode=wm8994_AP_to_headset;
 200         wm8994_reset();
 201         msleep(WM8994_DELAY);
 202
 203         wm8994_write(0x01,  0x0003);
 204         msleep(WM8994_DELAY);
 205
 206         wm8994_write(0x200, 0x0001);
 207         wm8994_write(0x220, 0x0000);
 208         wm8994_write(0x221, 0x0700);
 209         wm8994_write(0x222, 0x3126);
 210         wm8994_write(0x223, 0x0100);
 211
 212         wm8994_write(0x210, 0x0083); // SR=48KHz
 213         wm8994_write(0x220, 0x0004);
 214         msleep(WM8994_DELAY);
 215         wm8994_write(0x220, 0x0005);
 216         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 217         wm8994_write(0x300, 0x4010);  // i2s 16 bits
 218
 219         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1/ q
 220         wm8994_write(0x05,  0x0303);
 221         wm8994_write(0x2D,  0x0100);
 222         wm8994_write(0x2E,  0x0100);
 223
 224         wm8994_write(0x4C,  0x9F25);
 225         msleep(5);
 226         wm8994_write(0x01,  0x0303);
 227         msleep(50);
 228         wm8994_write(0x60,  0x0022);
 229         wm8994_write(0x60,  0x00FF);
 230
 231         wm8994_write(0x208, 0x000A);
 232         wm8994_write(0x420, 0x0000);
 233         wm8994_write(0x601, 0x0001);
 234         wm8994_write(0x602, 0x0001);
 235
 236         wm8994_write(0x610, 0x01A0);  //DAC1 Left Volume bit0~7
 237         wm8994_write(0x611, 0x01A0);  //DAC1 Right Volume bit0~7
 238         wm8994_write(0x03,  0x3030);
 239         wm8994_write(0x22,  0x0000);
 240         wm8994_write(0x23,  0x0100);
 241         wm8994_write(0x36,  0x0003);
 242         wm8994_write(0x1C,  0x017F);  //HPOUT1L Volume
 243         wm8994_write(0x1D,  0x017F);  //HPOUT1R Volume
 244
 245 #ifdef  CONFIG_SND_CODEC_SOC_MASTER
 246         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 247         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 248         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 249         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 250 #endif
 251 }
 252
 253 void AP_to_speakers(void)
 254 {
 255         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 256
 257         if(wm8994_current_mode==wm8994_AP_to_speakers)return;
 258         wm8994_current_mode=wm8994_AP_to_speakers;
 259         wm8994_reset();
 260         msleep(WM8994_DELAY);
 261
 262         wm8994_write(0x01,  0x0003);
 263         msleep(WM8994_DELAY);
 264
 265         wm8994_write(0x200, 0x0001);
 266         wm8994_write(0x220, 0x0000);
 267         wm8994_write(0x221, 0x0700);
 268         wm8994_write(0x222, 0x3126);
 269         wm8994_write(0x223, 0x0100);
 270
 271         wm8994_write(0x210, 0x0083); // SR=48KHz
 272         wm8994_write(0x220, 0x0004);
 273         msleep(WM8994_DELAY);
 274         wm8994_write(0x220, 0x0005);
 275         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 276         wm8994_write(0x300, 0xC010);  // i2s 16 bits
 277
 278         wm8994_write(0x01,  0x3003);
 279         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 280         wm8994_write(0x05,  0x0303);
 281         wm8994_write(0x2D,  0x0100);
 282         wm8994_write(0x2E,  0x0100);
 283         wm8994_write(0x4C,  0x9F25);
 284         wm8994_write(0x60,  0x00EE);
 285         wm8994_write(0x208, 0x000A);
 286         wm8994_write(0x420, 0x0000);
 287
 288         wm8994_write(0x601, 0x0001);
 289         wm8994_write(0x602, 0x0001);
 290
 291         wm8994_write(0x610, 0x01c0);  //DAC1 Left Volume bit0~7
 292         wm8994_write(0x611, 0x01c0);  //DAC1 Right Volume bit0~7
 293         wm8994_write(0x03,  0x0330);
 294         wm8994_write(0x22,  0x0000);
 295         wm8994_write(0x23,  0x0100);
 296         wm8994_write(0x36,  0x0003);
 297         wm8994_write(0x26,  0x017F);  //Speaker Left Output Volume
 298         wm8994_write(0x27,  0x017F);  //Speaker Right Output Volume
 299
 300 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 301         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 302         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 303         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 304         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 305 #endif
 306 }
 307
 308 void recorder_and_AP_to_headset(void)
 309 {
 310         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 311
 312         if(wm8994_current_mode==wm8994_recorder_and_AP_to_headset)return;
 313         wm8994_current_mode=wm8994_recorder_and_AP_to_headset;
 314         wm8994_reset();
 315         msleep(WM8994_DELAY);
 316
 317         wm8994_write(0x01,  0x0003);
 318         msleep(WM8994_DELAY);
 319
 320 //MCLK=12MHz
 321 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 322
 323         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 324         wm8994_write(0x220, 0x0000);
 325         wm8994_write(0x221, 0x0700);
 326         wm8994_write(0x222, 0x3126);
 327         wm8994_write(0x223, 0x0100);
 328         wm8994_write(0x210, 0x0083); // SR=48KHz
 329         wm8994_write(0x220, 0x0004);
 330         msleep(WM8994_DELAY);
 331         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 332         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 333
 334         vol=CONFIG_WM8994_RECORDER_VOL;
 335         if(vol>60)vol=60;
 336         if(vol<-16)vol=-16;
 337         if(vol<30){
 338                 wm8994_write(0x1A,  320+(vol+16)*10/15);  //mic vol
 339         }else{
 340                 wm8994_write(0x2A,  0x0030);
 341                 wm8994_write(0x1A,  320+(vol-14)*10/15);  //mic vol
 342         }
 343         vol=CONFIG_WM8994_HEADSET_NORMAL_VOL;
 344         if(vol>6)vol=6;
 345         if(vol<-57)vol=-57;
 346         wm8994_write(0x1C,  320+vol+57);  //-57dB~6dB
 347         wm8994_write(0x1D,  320+vol+57);  //-57dB~6dB
 348
 349         wm8994_write(0x28,  0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
 350         wm8994_write(0x200, 0x0011); // AIF1CLK_ENA=1
 351         wm8994_write(0x208, 0x000A); // DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 352         wm8994_write(0x300, 0xC050); // AIF1ADCL_SRC=1, AIF1ADCR_SRC=1, AIF1_WL=10, AIF1_FMT=10
 353         wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
 354         wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
 355         wm8994_write(0x620, 0x0000);
 356         wm8994_write(0x700, 0xA101);
 357
 358         wm8994_write(0x402, 0x01FF); // AIF1ADC1L_VOL [7:0]
 359         wm8994_write(0x403, 0x01FF); // AIF1ADC1R_VOL [7:0]
 360         wm8994_write(0x2D,  0x0100); // DAC1L_TO_HPOUT1L=1
 361         wm8994_write(0x2E,  0x0100); // DAC1R_TO_HPOUT1R=1
 362
 363         wm8994_write(0x4C,  0x9F25);
 364         mdelay(5);
 365         wm8994_write(0x01,  0x0313);
 366         mdelay(50);
 367         wm8994_write(0x60,  0x0022);
 368         wm8994_write(0x60,  0x00EE);
 369
 370         wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
 371         wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
 372         wm8994_write(0x610, 0x01A0); // DAC1_VU=1, DAC1L_VOL=1100_0000
 373         wm8994_write(0x611, 0x01A0); // DAC1_VU=1, DAC1R_VOL=1100_0000
 374         wm8994_write(0x02,  0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
 375         wm8994_write(0x03,  0x3030);
 376         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 377         wm8994_write(0x05,  0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
 378         wm8994_write(0x420, 0x0000);
 379
 380 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 381         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 382         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 383         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 384         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 385 #endif
 386 }
 387
 388 void recorder_and_AP_to_speakers(void)
 389 {
 390         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 391
 392         if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers)return;
 393         wm8994_current_mode=wm8994_recorder_and_AP_to_speakers;
 394         wm8994_reset();
 395         msleep(WM8994_DELAY);
 396
 397         wm8994_write(0x01,  0x0003);
 398         msleep(WM8994_DELAY);
 399
 400 //MCLK=12MHz
 401 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 402
 403         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 404         wm8994_write(0x220, 0x0000);
 405         wm8994_write(0x221, 0x0700);
 406         wm8994_write(0x222, 0x3126);
 407         wm8994_write(0x223, 0x0100);
 408         wm8994_write(0x210, 0x0083); // SR=48KHz
 409
 410         wm8994_write(0x220, 0x0004);
 411         msleep(WM8994_DELAY);
 412         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 413         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 414
 415         wm8994_write(0x02,  0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
 416         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 417         wm8994_write(0x28,  0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
 418         vol=CONFIG_WM8994_RECORDER_VOL;
 419         if(vol>60)vol=60;
 420         if(vol<-16)vol=-16;
 421         if(vol<30){
 422                 wm8994_write(0x1A,  320+(vol+16)*10/15);  //mic vol
 423         }else{
 424                 wm8994_write(0x2A,  0x0030);
 425                 wm8994_write(0x1A,  320+(vol-14)*10/15);  //mic vol
 426         }
 427
 428         vol=CONFIG_WM8994_SPEAKER_NORMAL_VOL;
 429         if(vol>18)vol=18;
 430         if(vol<-57)vol=-57;
 431         if(vol<=6){
 432                 wm8994_write(0x26,  320+vol+57);  //-57dB~6dB
 433                 wm8994_write(0x27,  320+vol+57);  //-57dB~6dB
 434         }else{
 435                 wm8994_write(0x25,  0x003F);  //0~12dB
 436                 wm8994_write(0x26,  320+vol+39);  //-57dB~6dB
 437                 wm8994_write(0x27,  320+vol+39);  //-57dB~6dB
 438         }
 439
 440         wm8994_write(0x200, 0x0011); // AIF1CLK_ENA=1
 441         wm8994_write(0x208, 0x000A); // DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 442         wm8994_write(0x300, 0xC050); // AIF1ADCL_SRC=1, AIF1ADCR_SRC=1, AIF1_WL=10, AIF1_FMT=10
 443         wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
 444         wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
 445         wm8994_write(0x620, 0x0000);
 446
 447         wm8994_write(0x402, 0x01FF); // AIF1ADC1L_VOL [7:0]
 448         wm8994_write(0x403, 0x01FF); // AIF1ADC1R_VOL [7:0]
 449
 450         wm8994_write(0x700, 0xA101);
 451
 452         wm8994_write(0x01,  0x3013);
 453         wm8994_write(0x03,  0x0330); // SPKRVOL_ENA=1, SPKLVOL_ENA=1, MIXOUTL_ENA=1, MIXOUTR_ENA=1
 454         wm8994_write(0x05,  0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
 455         wm8994_write(0x22,  0x0000);
 456         wm8994_write(0x23,  0x0100); // SPKOUT_CLASSAB=1
 457
 458         wm8994_write(0x2D,  0x0001); // DAC1L_TO_MIXOUTL=1
 459         wm8994_write(0x2E,  0x0001); // DAC1R_TO_MIXOUTR=1
 460         wm8994_write(0x4C,  0x9F25);
 461         wm8994_write(0x60,  0x00EE);
 462         wm8994_write(0x36,  0x000C); // MIXOUTL_TO_SPKMIXL=1, MIXOUTR_TO_SPKMIXR=1
 463         wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
 464         wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
 465         wm8994_write(0x610, 0x01C0); // DAC1_VU=1, DAC1L_VOL=1100_0000
 466         wm8994_write(0x611, 0x01C0); // DAC1_VU=1, DAC1R_VOL=1100_0000
 467         wm8994_write(0x420, 0x0000);
 468 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 469         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 470         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 471         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 472         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 473 #endif
 474 }
 475
 476 void FM_to_headset(void)
 477 {
 478         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 479
 480         if(wm8994_current_mode==wm8994_FM_to_headset)return;
 481         wm8994_current_mode=wm8994_FM_to_headset;
 482         wm8994_reset();
 483         msleep(WM8994_DELAY);
 484
 485         wm8994_write(0x01,  0x0323);
 486         wm8994_write(0x02,  0x03A0);
 487         wm8994_write(0x03,  0x0030);
 488         wm8994_write(0x19,  0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 489         wm8994_write(0x1B,  0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 490
 491         wm8994_write(0x28,  0x0044);
 492         wm8994_write(0x29,  0x0100);
 493         wm8994_write(0x2A,  0x0100);
 494         wm8994_write(0x2D,  0x0040);
 495         wm8994_write(0x2E,  0x0040);
 496         wm8994_write(0x4C,  0x9F25);
 497         wm8994_write(0x60,  0x00EE);
 498         wm8994_write(0x220, 0x0003);
 499         wm8994_write(0x221, 0x0700);
 500         wm8994_write(0x224, 0x0CC0);
 501         wm8994_write(0x200, 0x0011);
 502         wm8994_write(0x1C,  0x01F9);  //LEFT OUTPUT VOLUME
 503         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 504 }
 505
 506 void FM_to_headset_and_record(void)
 507 {
 508         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 509
 510         if(wm8994_current_mode==wm8994_FM_to_headset_and_record)return;
 511         wm8994_current_mode=wm8994_FM_to_headset_and_record;
 512         wm8994_reset();
 513         msleep(WM8994_DELAY);
 514
 515         wm8994_write(0x01,   0x0003);
 516         msleep(WM8994_DELAY);
 517         wm8994_write(0x221,  0x1900);  //8~13BIT div
 518
 519 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 520         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 521         wm8994_write(0x303,  0x0040);  // master  0x0050 lrck 7.94kHz bclk 510KHz
 522 #endif
 523
 524         wm8994_write(0x220,  0x0004);
 525         msleep(WM8994_DELAY);
 526         wm8994_write(0x220,  0x0005);
 527
 528         wm8994_write(0x01,   0x0323);
 529         wm8994_write(0x02,   0x03A0);
 530         wm8994_write(0x03,   0x0030);
 531         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 532         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 533
 534         wm8994_write(0x28,   0x0044);
 535         wm8994_write(0x29,   0x0100);
 536         wm8994_write(0x2A,   0x0100);
 537         wm8994_write(0x2D,   0x0040);
 538         wm8994_write(0x2E,   0x0040);
 539         wm8994_write(0x4C,   0x9F25);
 540         wm8994_write(0x60,   0x00EE);
 541         wm8994_write(0x200,  0x0011);
 542         wm8994_write(0x1C,   0x01F9);  //LEFT OUTPUT VOLUME
 543         wm8994_write(0x1D,   0x01F9);  //RIGHT OUTPUT VOLUME
 544         wm8994_write(0x04,   0x0303);
 545         wm8994_write(0x208,  0x000A);
 546         wm8994_write(0x300,  0x4050);
 547         wm8994_write(0x606,  0x0002);
 548         wm8994_write(0x607,  0x0002);
 549         wm8994_write(0x620,  0x0000);
 550 }
 551
 552 void FM_to_speakers(void)
 553 {
 554         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 555
 556         if(wm8994_current_mode==wm8994_FM_to_speakers)return;
 557         wm8994_current_mode=wm8994_FM_to_speakers;
 558         wm8994_reset();
 559         msleep(WM8994_DELAY);
 560
 561         wm8994_write(0x01,   0x3023);
 562         wm8994_write(0x02,   0x03A0);
 563         wm8994_write(0x03,   0x0330);
 564         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 565         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 566
 567         wm8994_write(0x22,   0x0000);
 568         wm8994_write(0x23,   0x0000);
 569         wm8994_write(0x36,   0x000C);
 570
 571         wm8994_write(0x28,   0x0044);
 572         wm8994_write(0x29,   0x0100);
 573         wm8994_write(0x2A,   0x0100);
 574         wm8994_write(0x2D,   0x0040);
 575         wm8994_write(0x2E,   0x0040);
 576
 577         wm8994_write(0x220,  0x0003);
 578         wm8994_write(0x221,  0x0700);
 579         wm8994_write(0x224,  0x0CC0);
 580
 581         wm8994_write(0x200,  0x0011);
 582         wm8994_write(0x20,   0x01F9);
 583         wm8994_write(0x21,   0x01F9);
 584 }
 585
 586 void FM_to_speakers_and_record(void)
 587 {
 588         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 589
 590         if(wm8994_current_mode==wm8994_FM_to_speakers_and_record)return;
 591         wm8994_current_mode=wm8994_FM_to_speakers_and_record;
 592         wm8994_reset();
 593         msleep(WM8994_DELAY);
 594
 595         wm8994_write(0x01,   0x0003);
 596         msleep(WM8994_DELAY);
 597
 598 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 599         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 600         wm8994_write(0x303,  0x0090);  //
 601 #endif
 602
 603         wm8994_write(0x220,  0x0006);
 604         msleep(WM8994_DELAY);
 605
 606         wm8994_write(0x01,   0x3023);
 607         wm8994_write(0x02,   0x03A0);
 608         wm8994_write(0x03,   0x0330);
 609         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 610         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 611
 612         wm8994_write(0x22,   0x0000);
 613         wm8994_write(0x23,   0x0000);
 614         wm8994_write(0x36,   0x000C);
 615
 616         wm8994_write(0x28,   0x0044);
 617         wm8994_write(0x29,   0x0100);
 618         wm8994_write(0x2A,   0x0100);
 619         wm8994_write(0x2D,   0x0040);
 620         wm8994_write(0x2E,   0x0040);
 621
 622         wm8994_write(0x220,  0x0003);
 623         wm8994_write(0x221,  0x0700);
 624         wm8994_write(0x224,  0x0CC0);
 625
 626         wm8994_write(0x200,  0x0011);
 627         wm8994_write(0x20,   0x01F9);
 628         wm8994_write(0x21,   0x01F9);
 629         wm8994_write(0x04,   0x0303);
 630         wm8994_write(0x208,  0x000A);
 631         wm8994_write(0x300,  0x4050);
 632         wm8994_write(0x606,  0x0002);
 633         wm8994_write(0x607,  0x0002);
 634         wm8994_write(0x620,  0x0000);
 635 }
 636 #ifndef PCM_BB
 637 void handsetMIC_to_baseband_to_headset(void)
 638 {
 639         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 640
 641         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset)return;
 642         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset;
 643         wm8994_reset();
 644         msleep(WM8994_DELAY);
 645
 646         wm8994_write(0x01,  0x0003);
 647         msleep(50);
 648
 649         wm8994_write(0x200, 0x0001);
 650         wm8994_write(0x220, 0x0000);
 651         wm8994_write(0x221, 0x0700);
 652         wm8994_write(0x222, 0x3126);
 653         wm8994_write(0x223, 0x0100);
 654
 655         wm8994_write(0x210, 0x0083); // SR=48KHz
 656         wm8994_write(0x220, 0x0004);
 657         msleep(WM8994_DELAY);
 658         wm8994_write(0x220, 0x0005);
 659         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 660         wm8994_write(0x300, 0xC010);  // i2s 16 bits
 661
 662         vol=CONFIG_WM8994_HEADSET_INCALL_MIC_VOL;
 663         if(vol>30)vol=30;
 664         if(vol<-22)vol=-22;
 665         if(vol<-16){
 666                 wm8994_write(0x1E,  0x0016);  //mic vol
 667                 wm8994_write(0x18,  320+(vol+22)*10/15);  //mic vol
 668         }else{
 669                 wm8994_write(0x1E,  0x0006);  //mic vol
 670                 wm8994_write(0x18,  320+(vol+16)*10/15);  //mic vol
 671         }
 672         vol=CONFIG_WM8994_HEADSET_INCALL_VOL;
 673         if(vol>0)vol=0;
 674         if(vol<-21)vol=-21;
 675         wm8994_write(0x31,  (((-vol)/3)<<3)+(-vol)/3);  //-21dB
 676
 677         wm8994_write(0x22,  0x0000);
 678         wm8994_write(0x23,  0x0100);
 679         wm8994_write(0x28,  0x0030);  //IN1LN_TO_IN1L IN1LP_TO_IN1L
 680         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 681
 682 #ifdef CONFIG_SND_BB_NORMAL_INPUT
 683         wm8994_write(0x2D,  0x0003);  //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
 684         wm8994_write(0x2E,  0x0003);  //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
 685 #endif
 686 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
 687         wm8994_write(0x02,  0x6240);
 688         wm8994_write(0x2B,  0x0005);  //VRX_MIXINL_VOL
 689         wm8994_write(0x2D,  0x0041);  //bit 1 MIXINL_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
 690         wm8994_write(0x2E,  0x0081);  //bit 1 MIXINL_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
 691 #endif
 692
 693         wm8994_write(0x34,  0x0002);  //IN1L_TO_LINEOUT1P
 694         wm8994_write(0x36,  0x0003);
 695
 696         wm8994_write(0x4C,  0x9F25);
 697         msleep(5);
 698         wm8994_write(0x01,  0x0323);
 699         msleep(50);
 700         wm8994_write(0x60,  0x0022);
 701         wm8994_write(0x60,  0x00EE);
 702
 703         wm8994_write(0x02,  0x6040);
 704         wm8994_write(0x03,  0x3030);
 705         wm8994_write(0x04,  0x0300); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1
 706         wm8994_write(0x05,  0x0303);
 707         wm8994_write(0x208, 0x000A);
 708         wm8994_write(0x224, 0x0CC0);
 709         wm8994_write(0x420, 0x0000);
 710         wm8994_write(0x601, 0x0001);
 711         wm8994_write(0x602, 0x0001);
 712
 713         wm8994_write(0x610, 0x01A0);  //DAC1 Left Volume bit0~7
 714         wm8994_write(0x611, 0x01A0);  //DAC1 Right Volume bit0~7
 715 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 716         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 717         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 718         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 719         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 720 #endif
 721 }
 722
 723 void handsetMIC_to_baseband_to_headset_and_record(void)
 724 {
 725         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 726
 727         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record)return;
 728         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset_and_record;
 729         wm8994_reset();
 730         msleep(WM8994_DELAY);
 731
 732         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);
 733         wm8994_write(0x02,  0x62C0);
 734         wm8994_write(0x03,  0x3030);
 735         wm8994_write(0x04,  0x0303);
 736         wm8994_write(0x18,  0x014B);  //volume
 737         wm8994_write(0x19,  0x014B);  //volume
 738         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 739         wm8994_write(0x1E,  0x0006);
 740         wm8994_write(0x28,  0x00B0);  //IN2LP_TO_IN2L
 741         wm8994_write(0x29,  0x0120);
 742         wm8994_write(0x2D,  0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 743         wm8994_write(0x2E,  0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 744         wm8994_write(0x34,  0x0002);
 745         wm8994_write(0x4C,  0x9F25);
 746         wm8994_write(0x60,  0x00EE);
 747         wm8994_write(0x200, 0x0001);
 748         wm8994_write(0x208, 0x000A);
 749         wm8994_write(0x300, 0x0050);
 750
 751 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 752         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 753         wm8994_write(0x303, 0x0090);  // master lrck 16k
 754 #endif
 755
 756         wm8994_write(0x606, 0x0002);
 757         wm8994_write(0x607, 0x0002);
 758         wm8994_write(0x620, 0x0000);
 759 }
 760
 761 void mainMIC_to_baseband_to_earpiece(void)
 762 {
 763         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 764
 765         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)return;
 766         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
 767         wm8994_reset();
 768         msleep(WM8994_DELAY);
 769
 770         wm8994_write(0x01,  0x0003);
 771         msleep(WM8994_DELAY);
 772
 773         wm8994_write(0x200, 0x0001);
 774         wm8994_write(0x220, 0x0000);
 775         wm8994_write(0x221, 0x0700);
 776         wm8994_write(0x222, 0x3126);
 777         wm8994_write(0x223, 0x0100);
 778
 779         wm8994_write(0x210, 0x0083); // SR=48KHz
 780         wm8994_write(0x220, 0x0004);
 781         msleep(WM8994_DELAY);
 782         wm8994_write(0x220, 0x0005);
 783         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
 784         wm8994_write(0x300, 0x4010); // i2s 16 bits
 785
 786         wm8994_write(0x01,  0x0833); //HPOUT2_ENA=1, VMID_SEL=01, BIAS_ENA=1
 787         wm8994_write(0x02,  0x6250); //bit4 IN1R_ENV bit6 IN1L_ENV
 788         wm8994_write(0x03,  0x30F0);
 789         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 790         wm8994_write(0x05,  0x0303);
 791         wm8994_write(0x1F,  0x0000);
 792 #if defined(CONFIG_SND_INSIDE_EARPIECE)||defined(CONFIG_SND_OUTSIDE_EARPIECE)
 793         vol=CONFIG_WM8994_EARPIECE_INCALL_VOL;
 794         if(vol>30)vol=30;
 795         if(vol<-27)vol=-27;
 796         if(vol>9){
 797                 wm8994_write(0x2E,  0x0081);  //30dB
 798                 wm8994_write(0x33,  0x0018);  //30dB
 799                 wm8994_write(0x31,  (((30-vol)/3)<<3)+(30-vol)/3);  //-21dB
 800         }else if(vol>3){
 801                 wm8994_write(0x2E,  0x0081);  //30dB
 802                 wm8994_write(0x33,  0x0018);  //30dB
 803                 wm8994_write(0x31,  (((24-vol)/3)<<3)+(24-vol)/3);  //-21dB
 804                 wm8994_write(0x1F,  0x0010);
 805         }else if(vol>=0){
 806         }else if(vol>-21){
 807                 wm8994_write(0x31,  (((-vol)/3)<<3)+(-vol)/3);  //-21dB
 808         }else{
 809                 wm8994_write(0x1F,  0x0010);
 810                 wm8994_write(0x31,  (((-vol-6)/3)<<3)+(-vol-6)/3);  //-21dB
 811         }
 812 #ifdef CONFIG_SND_INSIDE_EARPIECE
 813         wm8994_write(0x28,  0x0003); //IN1RP_TO_IN1R IN1RN_TO_IN1R
 814         wm8994_write(0x34,  0x0004); //IN1R_TO_LINEOUT1P
 815         vol=CONFIG_WM8994_SPEAKER_INCALL_MIC_VOL;
 816         if(vol>30)vol=30;
 817         if(vol<-22)vol=-22;
 818         if(vol<-16){
 819                 wm8994_write(0x1E,  0x0016);
 820                 wm8994_write(0x1A,  320+(vol+22)*10/15);
 821         }else{
 822                 wm8994_write(0x1E,  0x0006);
 823                 wm8994_write(0x1A,  320+(vol+16)*10/15);
 824         }
 825 #endif
 826 #ifdef CONFIG_SND_OUTSIDE_EARPIECE
 827         wm8994_write(0x28,  0x0030); //IN1LP_TO_IN1L IN1LN_TO_IN1L
 828         wm8994_write(0x34,  0x0002); //IN1L_TO_LINEOUT1P
 829         vol=CONFIG_WM8994_HEADSET_INCALL_MIC_VOL;
 830         if(vol>30)vol=30;
 831         if(vol<-22)vol=-22;
 832         if(vol<-16){
 833                 wm8994_write(0x1E,  0x0016);  //mic vol
 834                 wm8994_write(0x18,  320+(vol+22)*10/15);  //mic vol
 835         }else{
 836                 wm8994_write(0x1E,  0x0006);  //mic vol
 837                 wm8994_write(0x18,  320+(vol+16)*10/15);  //mic vol
 838         }
 839 #endif
 840 #endif
 841 #ifdef CONFIG_SND_BB_NORMAL_INPUT
 842         wm8994_write(0x2D,  0x0003);  //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
 843         wm8994_write(0x2E,  0x0003);  //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
 844 #endif
 845 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
 846         wm8994_write(0x2B,  0x0005);  //VRX_MIXINL_VOL
 847         wm8994_write(0x2D,  0x0041);  //bit 1 MIXINL_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
 848         wm8994_write(0x2E,  0x0081);  //bit 1 MIXINL_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
 849 #endif
 850         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 851         wm8994_write(0x33,  0x0010);
 852
 853         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 854         wm8994_write(0x601, 0x0001); //AIF1DAC1L_TO_DAC1L=1
 855         wm8994_write(0x602, 0x0001); //AIF1DAC1R_TO_DAC1R=1
 856         wm8994_write(0x610, 0x01C0); //DAC1_VU=1, DAC1L_VOL=1100_0000
 857         wm8994_write(0x611, 0x01C0); //DAC1_VU=1, DAC1R_VOL=1100_0000
 858
 859         wm8994_write(0x420, 0x0000);
 860
 861 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 862         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 863         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 864         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 865         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 866 #endif
 867 }
 868
 869 void mainMIC_to_baseband_to_earpiece_I2S(void)
 870 {
 871         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 872
 873         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)return;
 874         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
 875         wm8994_reset();
 876         msleep(WM8994_DELAY);
 877
 878         wm8994_write(0x01,  0x0003);
 879         msleep(WM8994_DELAY);
 880
 881         wm8994_write(0x200, 0x0001);
 882         wm8994_write(0x220, 0x0000);
 883         wm8994_write(0x221, 0x0700);
 884         wm8994_write(0x222, 0x3126);
 885         wm8994_write(0x223, 0x0100);
 886
 887         wm8994_write(0x210, 0x0083); // SR=48KHz
 888         wm8994_write(0x220, 0x0004);
 889         msleep(WM8994_DELAY);
 890         wm8994_write(0x220, 0x0005);
 891         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 892
 893         wm8994_write(0x02,  0x6240);
 894         wm8994_write(0x04,  0x0303);  // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 895         wm8994_write(0x18,  0x015B);  //IN1_VU=1, IN1L_MUTE=0, IN1L_ZC=1, IN1L_VOL=0_1011
 896         wm8994_write(0x1E,  0x0006);
 897         wm8994_write(0x1F,  0x0000);
 898         wm8994_write(0x28,  0x0030);
 899         wm8994_write(0x29,  0x0020); //IN1L_TO_MIXINL=1, IN1L_MIXINL_VOL=0, MIXOUTL_MIXINL_VOL=000
 900         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 901
 902         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011 //cjq
 903
 904         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 905         wm8994_write(0x300, 0x0050); //AIF1ADCL_SRC=1, AIF1ADCR_SRC=1
 906         wm8994_write(0x606, 0x0002); //ADC1L_TO_AIF1ADC1L=1
 907         wm8994_write(0x607, 0x0002); //ADC1R_TO_AIF1ADC1R=1
 908
 909         wm8994_write(0x620, 0x0000); //cjq
 910         wm8994_write(0x700, 0xA101); //cjq
 911
 912         wm8994_write(0x01,  0x0833); //HPOUT2_ENA=1, VMID_SEL=01, BIAS_ENA=1
 913         wm8994_write(0x03,  0x30F0);
 914         wm8994_write(0x05,  0x0303);
 915         wm8994_write(0x2D,  0x0021); //DAC1L_TO_MIXOUTL=1
 916         wm8994_write(0x2E,  0x0001); //DAC1R_TO_MIXOUTR=1
 917
 918         wm8994_write(0x4C,  0x9F25); //cjq
 919         wm8994_write(0x60,  0x00EE); //cjq
 920
 921         wm8994_write(0x33,  0x0010);
 922         wm8994_write(0x34,  0x0002);
 923
 924         wm8994_write(0x601, 0x0001); //AIF1DAC1L_TO_DAC1L=1
 925         wm8994_write(0x602, 0x0001); //AIF1DAC1R_TO_DAC1R=1
 926         wm8994_write(0x610, 0x01FF); //DAC1_VU=1, DAC1L_VOL=1100_0000
 927         wm8994_write(0x611, 0x01FF); //DAC1_VU=1, DAC1R_VOL=1100_0000
 928
 929         wm8994_write(0x420, 0x0000);
 930
 931 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 932         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 933         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 934         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 935         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 936 #endif
 937 }
 938
 939 void mainMIC_to_baseband_to_earpiece_and_record(void)
 940 {
 941         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 942
 943         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)return;
 944         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
 945         wm8994_reset();
 946         msleep(WM8994_DELAY);
 947
 948         wm8994_write(0x01  ,0x0803|wm8994_mic_VCC);
 949         wm8994_write(0x02  ,0x6310);
 950         wm8994_write(0x03  ,0x30A0);
 951         wm8994_write(0x04  ,0x0303);
 952         wm8994_write(0x1A  ,0x014F);
 953         wm8994_write(0x1E  ,0x0006);
 954         wm8994_write(0x1F  ,0x0000);
 955         wm8994_write(0x28  ,0x0003);  //MAINMIC_TO_IN1R  //
 956         wm8994_write(0x2A  ,0x0020);  //IN1R_TO_MIXINR   //
 957         wm8994_write(0x2B  ,0x0005);  //VRX_MIXINL_VOL bit 0~2
 958         wm8994_write(0x2C  ,0x0005);  //VRX_MIXINR_VOL
 959         wm8994_write(0x2D  ,0x0040);  //MIXINL_TO_MIXOUTL
 960         wm8994_write(0x33  ,0x0010);  //MIXOUTLVOL_TO_HPOUT2
 961         wm8994_write(0x34  ,0x0004);  //IN1R_TO_LINEOUT1 //
 962         wm8994_write(0x200 ,0x0001);
 963         wm8994_write(0x208 ,0x000A);
 964         wm8994_write(0x300 ,0xC050);
 965         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 966
 967 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 968         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 969         wm8994_write(0x303, 0x0090);  // master lrck 16k
 970 #endif
 971
 972         wm8994_write(0x606 ,0x0002);
 973         wm8994_write(0x607 ,0x0002);
 974         wm8994_write(0x620 ,0x0000);
 975 }
 976
 977 void mainMIC_to_baseband_to_speakers(void)
 978 {
 979         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 980
 981         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers)return;
 982         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers;
 983         wm8994_reset();
 984         msleep(WM8994_DELAY);
 985
 986         wm8994_write(0x01,  0x0003);
 987         msleep(WM8994_DELAY);
 988
 989         wm8994_write(0x200, 0x0001);
 990         wm8994_write(0x220, 0x0000);
 991         wm8994_write(0x221, 0x0700);
 992         wm8994_write(0x222, 0x3126);
 993         wm8994_write(0x223, 0x0100);
 994
 995         wm8994_write(0x210, 0x0083); // SR=48KHz
 996         msleep(WM8994_DELAY);
 997         wm8994_write(0x220, 0x0005);
 998         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 999         wm8994_write(0x300, 0xC010);  // i2s 16 bits
1000
1001         wm8994_write(0x01,  0x3013);
1002         wm8994_write(0x02,  0x6210);
1003         wm8994_write(0x03,  0x33F0);
1004         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
1005         wm8994_write(0x05,  0x0303);
1006         wm8994_write(0x22,  0x0000);
1007         wm8994_write(0x23,  0x0100);
1008         vol=CONFIG_WM8994_SPEAKER_INCALL_MIC_VOL;
1009         if(vol>30)vol=30;
1010         if(vol<-22)vol=-22;
1011         if(vol<-16){
1012                 wm8994_write(0x1E,  0x0016);
1013                 wm8994_write(0x1A,  320+(vol+22)*10/15);
1014         }else{
1015                 wm8994_write(0x1E,  0x0006);
1016                 wm8994_write(0x1A,  320+(vol+16)*10/15);
1017         }
1018         vol=CONFIG_WM8994_SPEAKER_INCALL_VOL;
1019         if(vol>12)vol=12;
1020         if(vol<-21)vol=-21;
1021         if(vol<0){
1022                 wm8994_write(0x31,  (((-vol)/3)<<3)+(-vol)/3);
1023         }else{
1024                 wm8994_write(0x25,  ((vol*10/15)<<3)+vol*10/15);
1025         }
1026         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1027         wm8994_write(0x28,  0x0003);  //IN1RP_TO_IN1R  IN1RN_TO_IN1R
1028 #ifdef CONFIG_SND_BB_NORMAL_INPUT
1029         wm8994_write(0x2D,  0x0003);  //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
1030         wm8994_write(0x2E,  0x0003);  //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
1031 #endif
1032 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
1033         wm8994_write(0x2B,  0x0005);  //VRX_MIXINL_VOL
1034         wm8994_write(0x2D,  0x0041);  //bit 1 MIXINL_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
1035         wm8994_write(0x2E,  0x0081);  //bit 1 MIXINL_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
1036 #endif
1037         wm8994_write(0x4C,  0x9F25);
1038         wm8994_write(0x60,  0x00EE);
1039         wm8994_write(0x34,  0x0004);
1040         wm8994_write(0x36,  0x000C);  //MIXOUTL_TO_SPKMIXL  MIXOUTR_TO_SPKMIXR
1041
1042         wm8994_write(0x208, 0x000A);
1043         wm8994_write(0x420, 0x0000);
1044
1045         wm8994_write(0x601, 0x0001);
1046         wm8994_write(0x602, 0x0001);
1047
1048         wm8994_write(0x610, 0x01c0);  //DAC1 Left Volume bit0~7
1049         wm8994_write(0x611, 0x01c0);  //DAC1 Right Volume bit0~7
1050
1051 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1052         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
1053         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
1054         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
1055         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
1056 #endif
1057 }
1058
1059 void mainMIC_to_baseband_to_speakers_and_record(void)
1060 {
1061         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1062
1063         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record)return;
1064         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
1065         wm8994_reset();
1066         msleep(WM8994_DELAY);
1067
1068         wm8994_write(0x01, 0x3003|wm8994_mic_VCC);
1069         wm8994_write(0x02, 0x6330);
1070         wm8994_write(0x03, 0x3330);
1071         wm8994_write(0x04, 0x0303);
1072         wm8994_write(0x1A, 0x014B);
1073         wm8994_write(0x1B, 0x014B);
1074         wm8994_write(0x1E, 0x0006);
1075         wm8994_write(0x22, 0x0000);
1076         wm8994_write(0x23, 0x0100);
1077         wm8994_write(0x28, 0x0007);
1078         wm8994_write(0x2A, 0x0120);
1079         wm8994_write(0x2D, 0x0002);  //bit 1 IN2LP_TO_MIXOUTL
1080         wm8994_write(0x2E, 0x0002);  //bit 1 IN2RP_TO_MIXOUTR
1081         wm8994_write(0x34, 0x0004);
1082         wm8994_write(0x36, 0x000C);
1083         wm8994_write(0x200, 0x0001);
1084         wm8994_write(0x208, 0x000A);
1085         wm8994_write(0x300, 0xC050);
1086         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1087
1088 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1089         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
1090         wm8994_write(0x303, 0x0090);  // master lrck 16k
1091 #endif
1092
1093         wm8994_write(0x606, 0x0002);
1094         wm8994_write(0x607, 0x0002);
1095         wm8994_write(0x620, 0x0000);
1096 }
1097
1098 void BT_baseband(void)
1099 {
1100         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1101
1102         if(wm8994_current_mode==wm8994_BT_baseband)return;
1103         wm8994_current_mode=wm8994_BT_baseband;
1104         wm8994_reset();
1105         msleep(WM8994_DELAY);
1106
1107         wm8994_write(0x01, 0x0003);
1108         wm8994_write(0x02, 0x63A0);
1109         wm8994_write(0x03, 0x30A0);
1110         wm8994_write(0x04, 0x3303);
1111         wm8994_write(0x05, 0x3002);
1112         wm8994_write(0x06, 0x000A);
1113         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1114         wm8994_write(0x1E, 0x0006);
1115         wm8994_write(0x29, 0x0100);
1116         vol=CONFIG_WM8994_BT_INCALL_MIC_VOL;
1117         if(vol>6)vol=6;
1118         if(vol<-57)vol=-57;
1119         wm8994_write(0x20,  320+vol+57);
1120
1121         vol=CONFIG_WM8994_BT_INCALL_VOL;
1122         if(vol>30)vol=30;
1123         if(vol<0)vol=0;
1124         if(vol>30)wm8994_write(0x29, 0x0130);
1125
1126 #ifdef CONFIG_SND_BB_NORMAL_INPUT
1127         wm8994_write(0x28, 0x00C0);
1128 #endif
1129 #ifdef CONFIG_SND_BB_DIFFERENTIAL_INPUT
1130         wm8994_write(0x28, 0x00CC);
1131 #endif
1132         wm8994_write(0x2A, 0x0100);
1133         wm8994_write(0x2D, 0x0001);
1134         wm8994_write(0x34, 0x0001);
1135         wm8994_write(0x200, 0x0001);
1136
1137         //roger_chen@20100524
1138         //8KHz, BCLK=8KHz*128=1024KHz, Fout=2.048MHz
1139         wm8994_write(0x204, 0x0001);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=00, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1140         wm8994_write(0x208, 0x000F);
1141         wm8994_write(0x220, 0x0000);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=0, FLL1_OSC_ENA=0, FLL1_ENA=0
1142         wm8994_write(0x221, 0x2F00);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (2)(221H):  0700  FLL1_OUTDIV=2Fh, FLL1_CTRL_RATE=000, FLL1_FRATIO=000
1143         wm8994_write(0x222, 0x3126);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (3)(222H):  8FD5  FLL1_K=3126h
1144         wm8994_write(0x223, 0x0100);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (4)(223H):  00E0  FLL1_N=8h, FLL1_GAIN=0000
1145         wm8994_write(0x310, 0xC118);  //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
1146         wm8994_write(0x210, 0x0003);    // SMbus_16inx_16dat     Write  0x34      * SR=8KHz
1147         wm8994_write(0x220, 0x0004);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=0
1148         msleep(50);
1149         wm8994_write(0x220, 0x0005);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=1
1150         wm8994_write(0x200, 0x0011);
1151         wm8994_write(0x204, 0x0011);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1152
1153         wm8994_write(0x440, 0x0018);
1154         wm8994_write(0x450, 0x0018);
1155         wm8994_write(0x480, 0x0000);
1156         wm8994_write(0x481, 0x0000);
1157         wm8994_write(0x4A0, 0x0000);
1158         wm8994_write(0x4A1, 0x0000);
1159         wm8994_write(0x520, 0x0000);
1160         wm8994_write(0x540, 0x0018);
1161         wm8994_write(0x580, 0x0000);
1162         wm8994_write(0x581, 0x0000);
1163         wm8994_write(0x601, 0x0004);
1164         wm8994_write(0x603, 0x000C);
1165         wm8994_write(0x604, 0x0010);
1166         wm8994_write(0x605, 0x0010);
1167         //wm8994_write(0x606, 0x0003);
1168         //wm8994_write(0x607, 0x0003);
1169         wm8994_write(0x610, 0x01C0);
1170         wm8994_write(0x612, 0x01C0);
1171         wm8994_write(0x613, 0x01C0);
1172         wm8994_write(0x620, 0x0000);
1173
1174         //roger_chen@20100519
1175         //enable AIF2 BCLK,LRCK
1176         //Rev.B and Rev.D is different
1177         wm8994_write(0x702, 0xA100);
1178         wm8994_write(0x703, 0xA100);
1179
1180         wm8994_write(0x704, 0xA100);
1181         wm8994_write(0x707, 0xA100);
1182         wm8994_write(0x708, 0x2100);
1183         wm8994_write(0x709, 0x2100);
1184         wm8994_write(0x70A, 0x2100);
1185
1186 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1187         wm8994_write(0x303, 0x0090);
1188         wm8994_write(0x313, 0x0020);    // SMbus_16inx_16dat     Write  0x34      * AIF2 BCLK DIV--------AIF1CLK/2
1189         wm8994_write(0x314, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 ADCLRCK DIV-----BCLK/128
1190         wm8994_write(0x315, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 DACLRCK DIV-----BCLK/128
1191         wm8994_write(0x302, 0x4000);
1192         wm8994_write(0x312, 0x4000);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Master/Slave(312H): 7000  AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
1193 #endif
1194 }
1195
1196 void BT_baseband_and_record(void)
1197 {
1198         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1199
1200         if(wm8994_current_mode==wm8994_BT_baseband_and_record)return;
1201         wm8994_current_mode=wm8994_BT_baseband_and_record;
1202         wm8994_reset();
1203         msleep(WM8994_DELAY);
1204
1205         wm8994_write(0x01, 0x0003);
1206         wm8994_write(0x02, 0x63A0);
1207         wm8994_write(0x03, 0x30A0);
1208         wm8994_write(0x04, 0x3303);
1209         wm8994_write(0x05, 0x3002);
1210         wm8994_write(0x06, 0x000A);
1211         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1212         wm8994_write(0x1E, 0x0006);
1213         wm8994_write(0x28, 0x00CC);
1214         wm8994_write(0x29, 0x0100);
1215         wm8994_write(0x2A, 0x0100);
1216         wm8994_write(0x2D, 0x0001);
1217         wm8994_write(0x34, 0x0001);
1218         wm8994_write(0x200, 0x0001);
1219
1220         //roger_chen@20100524
1221         //8KHz, BCLK=8KHz*128=1024KHz, Fout=2.048MHz
1222         wm8994_write(0x204, 0x0001);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=00, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1223         wm8994_write(0x208, 0x000F);
1224         wm8994_write(0x220, 0x0000);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=0, FLL1_OSC_ENA=0, FLL1_ENA=0
1225         wm8994_write(0x221, 0x2F00);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (2)(221H):  0700  FLL1_OUTDIV=2Fh, FLL1_CTRL_RATE=000, FLL1_FRATIO=000
1226         wm8994_write(0x222, 0x3126);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (3)(222H):  8FD5  FLL1_K=3126h
1227         wm8994_write(0x223, 0x0100);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (4)(223H):  00E0  FLL1_N=8h, FLL1_GAIN=0000
1228         wm8994_write(0x302, 0x4000);
1229         wm8994_write(0x303, 0x0090);
1230         wm8994_write(0x310, 0xC118);  //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
1231         wm8994_write(0x312, 0x4000);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Master/Slave(312H): 7000  AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
1232         wm8994_write(0x313, 0x0020);    // SMbus_16inx_16dat     Write  0x34      * AIF2 BCLK DIV--------AIF1CLK/2
1233         wm8994_write(0x314, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 ADCLRCK DIV-----BCLK/128
1234         wm8994_write(0x315, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 DACLRCK DIV-----BCLK/128
1235         wm8994_write(0x210, 0x0003);    // SMbus_16inx_16dat     Write  0x34      * SR=8KHz
1236         wm8994_write(0x220, 0x0004);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=0
1237         msleep(WM8994_DELAY);
1238         wm8994_write(0x220, 0x0005);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=1
1239         wm8994_write(0x204, 0x0011);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1240
1241         wm8994_write(0x440, 0x0018);
1242         wm8994_write(0x450, 0x0018);
1243         wm8994_write(0x480, 0x0000);
1244         wm8994_write(0x481, 0x0000);
1245         wm8994_write(0x4A0, 0x0000);
1246         wm8994_write(0x4A1, 0x0000);
1247         wm8994_write(0x520, 0x0000);
1248         wm8994_write(0x540, 0x0018);
1249         wm8994_write(0x580, 0x0000);
1250         wm8994_write(0x581, 0x0000);
1251         wm8994_write(0x601, 0x0004);
1252         wm8994_write(0x603, 0x000C);
1253         wm8994_write(0x604, 0x0010);
1254         wm8994_write(0x605, 0x0010);
1255         wm8994_write(0x606, 0x0003);
1256         wm8994_write(0x607, 0x0003);
1257         wm8994_write(0x610, 0x01C0);
1258         wm8994_write(0x612, 0x01C0);
1259         wm8994_write(0x613, 0x01C0);
1260         wm8994_write(0x620, 0x0000);
1261
1262         //roger_chen@20100519
1263         //enable AIF2 BCLK,LRCK
1264         //Rev.B and Rev.D is different
1265         wm8994_write(0x702, 0xA100);
1266         wm8994_write(0x703, 0xA100);
1267
1268         wm8994_write(0x704, 0xA100);
1269         wm8994_write(0x707, 0xA100);
1270         wm8994_write(0x708, 0x2100);
1271         wm8994_write(0x709, 0x2100);
1272         wm8994_write(0x70A, 0x2100);
1273 }
1274
1275 #else //PCM_BB
1276
1277 /******************PCM BB BEGIN*****************/
1278
1279 void handsetMIC_to_baseband_to_headset(void) //pcmbaseband
1280 {
1281         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1282
1283         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset)return;
1284         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset;
1285         wm8994_reset();
1286         msleep(50);
1287
1288         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1289         msleep(50);
1290         wm8994_write(0x221, 0x0700);
1291         wm8994_write(0x222, 0x3127);
1292         wm8994_write(0x223, 0x0100);
1293         wm8994_write(0x220, 0x0004);
1294         msleep(50);
1295         wm8994_write(0x220, 0x0005);
1296
1297         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);  ///0x0303);         // sysclk = fll (bit4 =1)   0x0011
1298         wm8994_write(0x02,  0x0240);
1299         wm8994_write(0x03,  0x0030);
1300         wm8994_write(0x04,  0x3003);
1301         wm8994_write(0x05,  0x3003);  // i2s 16 bits
1302         wm8994_write(0x18,  0x010B);
1303         wm8994_write(0x28,  0x0030);
1304         wm8994_write(0x29,  0x0020);
1305         wm8994_write(0x2D,  0x0100);  //0x0100);DAC1L_TO_HPOUT1L    ;;;bit 8
1306         wm8994_write(0x2E,  0x0100);  //0x0100);DAC1R_TO_HPOUT1R    ;;;bit 8
1307         wm8994_write(0x4C,  0x9F25);
1308         wm8994_write(0x60,  0x00EE);
1309         wm8994_write(0x200, 0x0001);
1310         wm8994_write(0x204, 0x0001);
1311         wm8994_write(0x208, 0x0007);
1312         wm8994_write(0x520, 0x0000);
1313         wm8994_write(0x601, 0x0004);  //AIF2DACL_TO_DAC1L
1314         wm8994_write(0x602, 0x0004);  //AIF2DACR_TO_DAC1R
1315
1316         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1317         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1318         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1319         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1320
1321         wm8994_write(0x702, 0xC100);
1322         wm8994_write(0x703, 0xC100);
1323         wm8994_write(0x704, 0xC100);
1324         wm8994_write(0x706, 0x4100);
1325         wm8994_write(0x204, 0x0011);
1326         wm8994_write(0x211, 0x0009);
1327         #ifdef TD688_MODE
1328         wm8994_write(0x310, 0x4108); ///0x4118);  ///interface dsp mode 16bit
1329         #endif
1330         #ifdef CHONGY_MODE
1331         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1332         #endif
1333         #ifdef MU301_MODE
1334         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1335         wm8994_write(0x241, 0x2f04);
1336         wm8994_write(0x242, 0x0000);
1337         wm8994_write(0x243, 0x0300);
1338         wm8994_write(0x240, 0x0004);
1339         msleep(40);
1340         wm8994_write(0x240, 0x0005);
1341         wm8994_write(0x204, 0x0019);
1342         wm8994_write(0x211, 0x0003);
1343         wm8994_write(0x244, 0x0c83);
1344         wm8994_write(0x620, 0x0000);
1345         #endif
1346         #ifdef THINKWILL_M800_MODE
1347         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1348         #endif
1349         wm8994_write(0x313, 0x00F0);
1350         wm8994_write(0x314, 0x0020);
1351         wm8994_write(0x315, 0x0020);
1352         wm8994_write(0x603, 0x018c);  ///0x000C);  //Rev.D ADCL SideTone
1353         wm8994_write(0x604, 0x0010); //XX
1354         wm8994_write(0x605, 0x0010); //XX
1355         wm8994_write(0x621, 0x0000);  //0x0001);   ///0x0000);
1356         wm8994_write(0x317, 0x0003);
1357         wm8994_write(0x312, 0x0000); /// as slave  ///0x4000);  //AIF2 SET AS MASTER
1358
1359         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1360 }
1361
1362 void handsetMIC_to_baseband_to_headset_and_record(void) //pcmbaseband
1363 {
1364         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1365
1366         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record)return;
1367         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset_and_record;
1368         wm8994_reset();
1369         msleep(50);
1370
1371         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1372         msleep(50);
1373         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1374         wm8994_write(0x222, 0x3127);
1375         wm8994_write(0x223, 0x0100);
1376         wm8994_write(0x220, 0x0004);
1377         msleep(50);
1378         wm8994_write(0x220, 0x0005);
1379
1380         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);
1381         wm8994_write(0x02,  0x0240);
1382         wm8994_write(0x03,  0x0030);
1383         wm8994_write(0x04,  0x3003);
1384         wm8994_write(0x05,  0x3003);
1385         wm8994_write(0x18,  0x010B);  // 0x011F=+30dB for MIC
1386         wm8994_write(0x28,  0x0030);
1387         wm8994_write(0x29,  0x0020);
1388         wm8994_write(0x2D,  0x0100);
1389         wm8994_write(0x2E,  0x0100);
1390         wm8994_write(0x4C,  0x9F25);
1391         wm8994_write(0x60,  0x00EE);
1392         wm8994_write(0x200, 0x0001);
1393         wm8994_write(0x204, 0x0001);
1394         wm8994_write(0x208, 0x0007);
1395         wm8994_write(0x520, 0x0000);
1396         wm8994_write(0x601, 0x0004);
1397         wm8994_write(0x602, 0x0004);
1398
1399         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1400         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1401         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1402         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1403
1404         wm8994_write(0x700, 0x8141);  //SYNC issue, AIF1 ADCLRC1 from LRCK1
1405         wm8994_write(0x702, 0xC100);
1406         wm8994_write(0x703, 0xC100);
1407         wm8994_write(0x704, 0xC100);
1408         wm8994_write(0x706, 0x4100);
1409         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1410         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1411         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1412         wm8994_write(0x313, 0x00F0);
1413         wm8994_write(0x314, 0x0020);
1414         wm8994_write(0x315, 0x0020);
1415
1416         wm8994_write(0x603, 0x018c);  ///0x000C);  //Rev.D ADCL SideTone
1417         wm8994_write(0x604, 0x0010);
1418         wm8994_write(0x605, 0x0010);
1419         wm8994_write(0x621, 0x0000);
1420         //wm8994_write(0x317, 0x0003);
1421         //wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1422 ////AIF1
1423         wm8994_write(0x04,   0x3303);
1424         wm8994_write(0x200,  0x0001);
1425         wm8994_write(0x208,  0x000F);
1426         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1427         wm8994_write(0x300,  0x0118);  //DSP/PCM 16bits, R ADC = L ADC
1428         wm8994_write(0x606,  0x0003);
1429         wm8994_write(0x607,  0x0003);
1430
1431 ////AIF1 Master Clock(SR=8KHz)
1432         wm8994_write(0x200,  0x0011);
1433         wm8994_write(0x302,  0x4000);
1434         wm8994_write(0x303,  0x00F0);
1435         wm8994_write(0x304,  0x0020);
1436         wm8994_write(0x305,  0x0020);
1437
1438 ////AIF1 DAC1 HP
1439         wm8994_write(0x05,   0x3303);
1440         wm8994_write(0x420,  0x0000);
1441         wm8994_write(0x601,  0x0001);
1442         wm8994_write(0x602,  0x0001);
1443         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1444
1445         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1446 }
1447
1448 void mainMIC_to_baseband_to_earpiece(void) //pcmbaseband
1449 {
1450         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1451
1452         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)return;
1453         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
1454         wm8994_reset();
1455         msleep(50);
1456
1457         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1458         msleep(50);
1459         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1460         wm8994_write(0x222, 0x3127);
1461         wm8994_write(0x223, 0x0100);
1462         wm8994_write(0x220, 0x0004);
1463         msleep(50);
1464         wm8994_write(0x220, 0x0005);
1465
1466         wm8994_write(0x01,  0x0803|wm8994_mic_VCC);   ///0x0813);
1467         wm8994_write(0x02,  0x0240);   ///0x0110);
1468         wm8994_write(0x03,  0x00F0);
1469         wm8994_write(0x04,  0x3003);
1470         wm8994_write(0x05,  0x3003);
1471         wm8994_write(0x18,  0x011F);
1472         //wm8994_write(0x1A,  0x010B);
1473         wm8994_write(0x1F,  0x0000);
1474         wm8994_write(0x28,  0x0030);  ///0x0003);
1475         wm8994_write(0x29,  0x0020);
1476         //wm8994_write(0x2A,  0x0020);
1477         wm8994_write(0x2D,  0x0001);
1478         wm8994_write(0x2E,  0x0001);
1479         wm8994_write(0x33,  0x0018);
1480         //wm8994_write(0x4C,  0x9F25);
1481         //wm8994_write(0x60,  0x00EE);
1482         wm8994_write(0x200, 0x0001);
1483         wm8994_write(0x204, 0x0001);
1484         wm8994_write(0x208, 0x0007);
1485         wm8994_write(0x520, 0x0000);
1486         wm8994_write(0x601, 0x0004);
1487         wm8994_write(0x602, 0x0004);
1488
1489         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1490         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1491         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1492         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1493
1494         //wm8994_write(0x700, 0x8141);
1495         wm8994_write(0x702, 0xC100);
1496         wm8994_write(0x703, 0xC100);
1497         wm8994_write(0x704, 0xC100);
1498         wm8994_write(0x706, 0x4100);
1499         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1500         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1501         ///wm8994_write(0x310, 0x4108); /// 0x4118);  ///0x4118);  //DSP/PCM 16bits
1502         #ifdef TD688_MODE
1503         wm8994_write(0x310, 0x4108); ///0x4118);  ///interface dsp mode 16bit
1504         #endif
1505         #ifdef CHONGY_MODE
1506         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1507         #endif
1508         #ifdef MU301_MODE
1509         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1510         wm8994_write(0x241, 0x2f04);
1511         wm8994_write(0x242, 0x0000);
1512         wm8994_write(0x243, 0x0300);
1513         wm8994_write(0x240, 0x0004);
1514         msleep(40);
1515         wm8994_write(0x240, 0x0005);
1516         wm8994_write(0x204, 0x0019);
1517         wm8994_write(0x211, 0x0003);
1518         wm8994_write(0x244, 0x0c83);
1519         wm8994_write(0x620, 0x0000);
1520         #endif
1521         #ifdef THINKWILL_M800_MODE
1522         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1523         #endif
1524         wm8994_write(0x313, 0x00F0);
1525         wm8994_write(0x314, 0x0020);
1526         wm8994_write(0x315, 0x0020);
1527
1528         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1529         wm8994_write(0x604, 0x0010);
1530         wm8994_write(0x605, 0x0010);
1531         wm8994_write(0x621, 0x0000);  ///0x0001);
1532         wm8994_write(0x317, 0x0003);
1533         wm8994_write(0x312, 0x0000);  //AIF2 SET AS MASTER
1534
1535         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1536 }
1537
1538 void mainMIC_to_baseband_to_earpiece_and_record(void) //pcmbaseband
1539 {
1540         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1541
1542         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)return;
1543         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
1544         wm8994_reset();
1545         msleep(50);
1546
1547         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1548         msleep(50);
1549         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1550         wm8994_write(0x222, 0x3127);
1551         wm8994_write(0x223, 0x0100);
1552         wm8994_write(0x220, 0x0004);
1553         msleep(50);
1554         wm8994_write(0x220, 0x0005);
1555
1556         wm8994_write(0x01,  0x0803|wm8994_mic_VCC);
1557         wm8994_write(0x02,  0x0110);
1558         wm8994_write(0x03,  0x00F0);
1559         wm8994_write(0x04,  0x3003);
1560         wm8994_write(0x05,  0x3003);
1561         wm8994_write(0x1A,  0x010B);
1562         wm8994_write(0x1F,  0x0000);
1563         wm8994_write(0x28,  0x0003);
1564         wm8994_write(0x2A,  0x0020);
1565         wm8994_write(0x2D,  0x0001);
1566         wm8994_write(0x2E,  0x0001);
1567         wm8994_write(0x33,  0x0018);
1568         //wm8994_write(0x4C,  0x9F25);
1569         //wm8994_write(0x60,  0x00EE);
1570         wm8994_write(0x200, 0x0001);
1571         wm8994_write(0x204, 0x0001);
1572         wm8994_write(0x208, 0x0007);
1573         wm8994_write(0x520, 0x0000);
1574         wm8994_write(0x601, 0x0004);
1575         wm8994_write(0x602, 0x0004);
1576
1577         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1578         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1579         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1580         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1581
1582         wm8994_write(0x702, 0xC100);
1583         wm8994_write(0x703, 0xC100);
1584         wm8994_write(0x704, 0xC100);
1585         wm8994_write(0x706, 0x4100);
1586         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1587         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1588         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1589         wm8994_write(0x313, 0x00F0);
1590         wm8994_write(0x314, 0x0020);
1591         wm8994_write(0x315, 0x0020);
1592
1593         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1594         wm8994_write(0x604, 0x0010);
1595         wm8994_write(0x605, 0x0010);
1596         wm8994_write(0x621, 0x0001);
1597         //wm8994_write(0x317, 0x0003);
1598         //wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1599
1600 ////AIF1
1601         wm8994_write(0x04,   0x3303);
1602         wm8994_write(0x200,  0x0001);
1603         wm8994_write(0x208,  0x000F);
1604         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1605         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1606         wm8994_write(0x606,  0x0003);
1607         wm8994_write(0x607,  0x0003);
1608
1609 ////AIF1 Master Clock(SR=8KHz)
1610         wm8994_write(0x200,  0x0011);
1611         wm8994_write(0x302,  0x4000);
1612         wm8994_write(0x303,  0x00F0);
1613         wm8994_write(0x304,  0x0020);
1614         wm8994_write(0x305,  0x0020);
1615
1616 ////AIF1 DAC1 HP
1617         wm8994_write(0x05,   0x3303);
1618         wm8994_write(0x420,  0x0000);
1619         wm8994_write(0x601,  0x0001);
1620         wm8994_write(0x602,  0x0001);
1621         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1622
1623         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1624 }
1625
1626 void mainMIC_to_baseband_to_speakers(void) //pcmbaseband
1627 {
1628         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1629
1630         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers)return;
1631         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers;
1632         wm8994_reset();
1633         msleep(50);
1634
1635         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);  //0x0013);
1636         msleep(50);
1637         wm8994_write(0x221, 0x0700);  //MCLK=12MHz   //FLL1 CONTRLO(2)
1638         wm8994_write(0x222, 0x3127);  //FLL1 CONTRLO(3)
1639         wm8994_write(0x223, 0x0100);  //FLL1 CONTRLO(4)
1640         wm8994_write(0x220, 0x0004);  //FLL1 CONTRLO(1)
1641         msleep(50);
1642         wm8994_write(0x220, 0x0005);  //FLL1 CONTRLO(1)
1643
1644         wm8994_write(0x01,  0x3003|wm8994_mic_VCC);
1645         wm8994_write(0x02,  0x0110);
1646         wm8994_write(0x03,  0x0030);  ///0x0330);
1647         wm8994_write(0x04,  0x3003);
1648         wm8994_write(0x05,  0x3003);
1649         wm8994_write(0x1A,  0x011F);
1650         wm8994_write(0x22,  0x0000);
1651         wm8994_write(0x23,  0x0100);  ///0x0000);
1652         wm8994_write(0x25,  0x0152);
1653         wm8994_write(0x28,  0x0003);
1654         wm8994_write(0x2A,  0x0020);
1655         wm8994_write(0x2D,  0x0001);
1656         wm8994_write(0x2E,  0x0001);
1657         wm8994_write(0x36,  0x000C);  //MIXOUTL_TO_SPKMIXL  MIXOUTR_TO_SPKMIXR
1658         //wm8994_write(0x4C,  0x9F25);
1659         //wm8994_write(0x60,  0x00EE);
1660         wm8994_write(0x200, 0x0001);  //AIF1 CLOCKING(1)
1661         wm8994_write(0x204, 0x0001);  //AIF2 CLOCKING(1)
1662         wm8994_write(0x208, 0x0007);  //CLOCKING(1)
1663         wm8994_write(0x520, 0x0000);  //AIF2 DAC FILTERS(1)
1664         wm8994_write(0x601, 0x0004);  //AIF2DACL_DAC1L
1665         wm8994_write(0x602, 0x0004);  //AIF2DACR_DAC1R
1666
1667         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1668         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1669         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1670         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1671
1672         wm8994_write(0x702, 0xC100);  //GPIO3
1673         wm8994_write(0x703, 0xC100);  //GPIO4
1674         wm8994_write(0x704, 0xC100);  //GPIO5
1675         wm8994_write(0x706, 0x4100);  //GPIO7
1676         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1677         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1678         #ifdef TD688_MODE
1679         wm8994_write(0x310, 0xc108); ///0x4118);  ///interface dsp mode 16bit
1680         #endif
1681         #ifdef CHONGY_MODE
1682         wm8994_write(0x310, 0xc018); ///0x4118);  ///interface dsp mode 16bit
1683         #endif
1684         #ifdef MU301_MODE
1685         wm8994_write(0x310, 0xc118); ///0x4118);  ///interface dsp mode 16bit
1686         wm8994_write(0x241, 0x2f04);
1687         wm8994_write(0x242, 0x0000);
1688         wm8994_write(0x243, 0x0300);
1689         wm8994_write(0x240, 0x0004);
1690         msleep(40);
1691         wm8994_write(0x240, 0x0005);
1692         wm8994_write(0x204, 0x0019);
1693         wm8994_write(0x211, 0x0003);
1694         wm8994_write(0x244, 0x0c83);
1695         wm8994_write(0x620, 0x0000);
1696         #endif
1697         #ifdef THINKWILL_M800_MODE
1698         wm8994_write(0x310, 0xc118); ///0x4118);  ///interface dsp mode 16bit
1699         #endif
1700         //wm8994_write(0x310, 0xc008);  //0xC018);//  //4118);  //DSP/PCM 16bits
1701         wm8994_write(0x313, 0x00F0);  //AIF2BCLK
1702         wm8994_write(0x314, 0x0020);  //AIF2ADCLRCK
1703         wm8994_write(0x315, 0x0020);  //AIF2DACLRCLK
1704
1705         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1706         wm8994_write(0x604, 0x0020);  ///0x0010);  //ADC2_TO_DAC2L
1707         wm8994_write(0x605, 0x0020);  //0x0010);  //ADC2_TO_DAC2R
1708         wm8994_write(0x621, 0x0000);  ///0x0001);
1709         wm8994_write(0x317, 0x0003);
1710         wm8994_write(0x312, 0x0000);  //AIF2 SET AS MASTER
1711
1712         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1713 }
1714
1715 void mainMIC_to_baseband_to_speakers_and_record(void) //pcmbaseband
1716 {
1717         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1718
1719         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record)return;
1720         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
1721         wm8994_reset();
1722         msleep(50);
1723
1724         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1725         msleep(50);
1726         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1727         wm8994_write(0x222, 0x3127);
1728         wm8994_write(0x223, 0x0100);
1729         wm8994_write(0x220, 0x0004);
1730         msleep(50);
1731         wm8994_write(0x220, 0x0005);
1732
1733         wm8994_write(0x02,  0x0110);
1734         wm8994_write(0x03,  0x0330);
1735         wm8994_write(0x04,  0x3003);
1736         wm8994_write(0x05,  0x3003);
1737         wm8994_write(0x1A,  0x010B);
1738         wm8994_write(0x22,  0x0000);
1739         wm8994_write(0x23,  0x0000);
1740         wm8994_write(0x28,  0x0003);
1741         wm8994_write(0x2A,  0x0020);
1742         wm8994_write(0x2D,  0x0001);
1743         wm8994_write(0x2E,  0x0001);
1744         wm8994_write(0x36,  0x000C);
1745         //wm8994_write(0x4C,  0x9F25);
1746         //wm8994_write(0x60,  0x00EE);
1747         wm8994_write(0x200, 0x0001);
1748         wm8994_write(0x204, 0x0001);
1749         wm8994_write(0x208, 0x0007);
1750         wm8994_write(0x520, 0x0000);
1751         wm8994_write(0x601, 0x0004);
1752         wm8994_write(0x602, 0x0004);
1753
1754         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1755         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1756         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1757         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1758
1759         wm8994_write(0x700, 0x8141);
1760         wm8994_write(0x702, 0xC100);
1761         wm8994_write(0x703, 0xC100);
1762         wm8994_write(0x704, 0xC100);
1763         wm8994_write(0x706, 0x4100);
1764         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1765         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1766         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1767         wm8994_write(0x313, 0x00F0);
1768         wm8994_write(0x314, 0x0020);
1769         wm8994_write(0x315, 0x0020);
1770
1771         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1772         wm8994_write(0x604, 0x0010);
1773         wm8994_write(0x605, 0x0010);
1774         wm8994_write(0x621, 0x0001);
1775         //wm8994_write(0x317, 0x0003);
1776         //wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1777
1778 ////AIF1
1779         wm8994_write(0x04,   0x3303);
1780         wm8994_write(0x200,  0x0001);
1781         wm8994_write(0x208,  0x000F);
1782         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1783         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1784         wm8994_write(0x606,  0x0003);
1785         wm8994_write(0x607,  0x0003);
1786
1787 ////AIF1 Master Clock(SR=8KHz)
1788         wm8994_write(0x200,  0x0011);
1789         wm8994_write(0x302,  0x4000);
1790         wm8994_write(0x303,  0x00F0);
1791         wm8994_write(0x304,  0x0020);
1792         wm8994_write(0x305,  0x0020);
1793
1794 ////AIF1 DAC1 HP
1795         wm8994_write(0x05,   0x3303);
1796         wm8994_write(0x420,  0x0000);
1797         wm8994_write(0x601,  0x0001);
1798         wm8994_write(0x602,  0x0001);
1799         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1800
1801         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1802 }
1803
1804 void BT_baseband(void) //pcmbaseband
1805 {
1806         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1807
1808         if(wm8994_current_mode==wm8994_BT_baseband)return;
1809         wm8994_current_mode=wm8994_BT_baseband;
1810         wm8994_reset();
1811         msleep(50);
1812
1813         wm8994_write(0x01 ,0x0003);
1814         msleep (50);
1815
1816         wm8994_write(0x200 ,0x0001);
1817         wm8994_write(0x221 ,0x0700);//MCLK=12MHz
1818         wm8994_write(0x222 ,0x3127);
1819         wm8994_write(0x223 ,0x0100);
1820         wm8994_write(0x220 ,0x0004);
1821         msleep (50);
1822         wm8994_write(0x220 ,0x0005);
1823
1824         wm8994_write(0x02 ,0x0000);
1825         wm8994_write(0x200 ,0x0011);// AIF1 MCLK=FLL1
1826         wm8994_write(0x210 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1827         wm8994_write(0x300 ,0x4018);// DSP/PCM 16bits
1828
1829         wm8994_write(0x204 ,0x0011);// AIF2 MCLK=FLL1
1830         wm8994_write(0x211 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1831         wm8994_write(0x310 ,0x4118);// DSP/PCM 16bits
1832         wm8994_write(0x208 ,0x000F);
1833
1834 /////AIF1
1835         wm8994_write(0x700 ,0x8101);
1836 /////AIF2
1837         wm8994_write(0x702 ,0xC100);
1838         wm8994_write(0x703 ,0xC100);
1839         wm8994_write(0x704 ,0xC100);
1840         wm8994_write(0x706 ,0x4100);
1841 /////AIF3
1842         wm8994_write(0x707 ,0xA100);
1843         wm8994_write(0x708 ,0xA100);
1844         wm8994_write(0x709 ,0xA100);
1845         wm8994_write(0x70A ,0xA100);
1846
1847         wm8994_write(0x06 ,0x0001);
1848
1849         wm8994_write(0x02 ,0x0300);
1850         wm8994_write(0x03 ,0x0030);
1851         wm8994_write(0x04 ,0x3301);//ADCL off
1852         wm8994_write(0x05 ,0x3301);//DACL off
1853
1854 //      wm8994_write(0x29 ,0x0005);
1855         wm8994_write(0x2A ,0x0005);
1856
1857         wm8994_write(0x313 ,0x00F0);
1858         wm8994_write(0x314 ,0x0020);
1859         wm8994_write(0x315 ,0x0020);
1860
1861 //      wm8994_write(0x2D ,0x0001);
1862         wm8994_write(0x2E ,0x0001);
1863         wm8994_write(0x420 ,0x0000);
1864         wm8994_write(0x520 ,0x0000);
1865         wm8994_write(0x601 ,0x0001);
1866         wm8994_write(0x602 ,0x0001);
1867         wm8994_write(0x604 ,0x0001);
1868         wm8994_write(0x605 ,0x0001);
1869 //      wm8994_write(0x606 ,0x0002);
1870         wm8994_write(0x607 ,0x0002);
1871 //      wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1872         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1873         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1874         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1875
1876
1877         wm8994_write(0x312 ,0x4000);
1878
1879         wm8994_write(0x606 ,0x0001);
1880         wm8994_write(0x607 ,0x0003);//R channel for data mix/CPU record data
1881
1882
1883 ////////////HP output test
1884         wm8994_write(0x01 ,0x0303);
1885         wm8994_write(0x4C ,0x9F25);
1886         wm8994_write(0x60 ,0x00EE);
1887 ///////////end HP test
1888
1889         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1890 }
1891
1892 void BT_baseband_and_record(void) //pcmbaseband
1893 {
1894         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1895
1896         if(wm8994_current_mode==wm8994_BT_baseband_and_record)return;
1897         wm8994_current_mode=wm8994_BT_baseband_and_record;
1898         wm8994_reset();
1899         msleep(50);
1900
1901         wm8994_write(0x01  ,0x0003);
1902         msleep (50);
1903
1904         wm8994_write(0x200 ,0x0001);
1905         wm8994_write(0x221 ,0x0700);//MCLK=12MHz
1906         wm8994_write(0x222 ,0x3127);
1907         wm8994_write(0x223 ,0x0100);
1908         wm8994_write(0x220 ,0x0004);
1909         msleep (50);
1910         wm8994_write(0x220 ,0x0005);
1911
1912         wm8994_write(0x02 ,0x0000);
1913         wm8994_write(0x200 ,0x0011);// AIF1 MCLK=FLL1
1914         wm8994_write(0x210 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1915         wm8994_write(0x300 ,0x4018);// DSP/PCM 16bits
1916
1917         wm8994_write(0x204 ,0x0011);// AIF2 MCLK=FLL1
1918         wm8994_write(0x211 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1919         wm8994_write(0x310 ,0x4118);// DSP/PCM 16bits
1920         wm8994_write(0x208 ,0x000F);
1921
1922 /////AIF1
1923         wm8994_write(0x700 ,0x8101);
1924 /////AIF2
1925         wm8994_write(0x702 ,0xC100);
1926         wm8994_write(0x703 ,0xC100);
1927         wm8994_write(0x704 ,0xC100);
1928         wm8994_write(0x706 ,0x4100);
1929 /////AIF3
1930         wm8994_write(0x707 ,0xA100);
1931         wm8994_write(0x708 ,0xA100);
1932         wm8994_write(0x709 ,0xA100);
1933         wm8994_write(0x70A ,0xA100);
1934
1935         wm8994_write(0x06 ,0x0001);
1936
1937         wm8994_write(0x02 ,0x0300);
1938         wm8994_write(0x03 ,0x0030);
1939         wm8994_write(0x04 ,0x3301);//ADCL off
1940         wm8994_write(0x05 ,0x3301);//DACL off
1941
1942 //   wm8994_write(0x29 ,0x0005);
1943         wm8994_write(0x2A ,0x0005);
1944
1945         wm8994_write(0x313 ,0x00F0);
1946         wm8994_write(0x314 ,0x0020);
1947         wm8994_write(0x315 ,0x0020);
1948
1949 //   wm8994_write(0x2D ,0x0001);
1950         wm8994_write(0x2E ,0x0001);
1951         wm8994_write(0x420 ,0x0000);
1952         wm8994_write(0x520 ,0x0000);
1953 //  wm8994_write(0x601 ,0x0001);
1954         wm8994_write(0x602 ,0x0001);
1955         wm8994_write(0x604 ,0x0001);
1956         wm8994_write(0x605 ,0x0001);
1957 //  wm8994_write(0x606 ,0x0002);
1958         wm8994_write(0x607 ,0x0002);
1959 //      wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1960         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1961         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1962         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1963
1964
1965         wm8994_write(0x312 ,0x4000);
1966
1967         wm8994_write(0x606 ,0x0001);
1968         wm8994_write(0x607 ,0x0003);//R channel for data mix/CPU record data
1969
1970
1971 ////////////HP output test
1972         wm8994_write(0x01 ,0x0303);
1973         wm8994_write(0x4C ,0x9F25);
1974         wm8994_write(0x60 ,0x00EE);
1975 ///////////end HP test
1976
1977         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1978 }
1979 #endif //PCM_BB
1980
1981
1982 typedef void (wm8994_codec_fnc_t) (void);
1983
1984 wm8994_codec_fnc_t *wm8994_codec_sequence[] = {
1985         AP_to_headset,
1986         AP_to_speakers,
1987         recorder_and_AP_to_headset,
1988         recorder_and_AP_to_speakers,
1989         FM_to_headset,
1990         FM_to_headset_and_record,
1991         FM_to_speakers,
1992         FM_to_speakers_and_record,
1993         handsetMIC_to_baseband_to_headset,
1994         handsetMIC_to_baseband_to_headset_and_record,
1995         mainMIC_to_baseband_to_earpiece,
1996         mainMIC_to_baseband_to_earpiece_and_record,
1997         mainMIC_to_baseband_to_speakers,
1998         mainMIC_to_baseband_to_speakers_and_record,
1999         BT_baseband,
2000         BT_baseband_and_record,
2001 };
2002
2003 /********************set wm8994 volume*****volume=0\1\2\3\4\5\6\7*******************/
2004
2005 void wm8994_codec_set_volume(unsigned char system_type,unsigned char volume)
2006 {
2007         DBG("%s::%d\n",__FUNCTION__,__LINE__);
2008
2009         if(system_type == VOICE_CALL||system_type == BLUETOOTH_SCO )
2010         {
2011                 if(volume<=call_maxvol)
2012                         call_vol=volume;
2013                 else{
2014                         printk("%s----%d::call volume more than max value 7\n",__FUNCTION__,__LINE__);
2015                         call_vol=call_maxvol;
2016                 }
2017                 if(wm8994_current_mode<null&&wm8994_current_mode>=wm8994_handsetMIC_to_baseband_to_headset)
2018                         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
2019         }
2020         else
2021                 printk("%s----%d::system type error!\n",__FUNCTION__,__LINE__);
2022 }
2023
2024 void wm8994_set_volume(unsigned char wm8994_mode,unsigned char volume,unsigned char max_volume)
2025 {
2026         unsigned short lvol=0,rvol=0;
2027
2028         if(volume>max_volume)volume=max_volume;
2029
2030         if(wm8994_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record||
2031         wm8994_mode==wm8994_handsetMIC_to_baseband_to_headset)
2032         {
2033                 wm8994_read(0x001C, &lvol);
2034                 wm8994_read(0x001D, &rvol);
2035                 //HPOUT1L_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2036                 wm8994_write(0x001C, (lvol&~0x003f)|headset_vol_table[volume]);
2037                 //HPOUT1R_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2038                 wm8994_write(0x001D, (lvol&~0x003f)|headset_vol_table[volume]);
2039         }
2040         else if(wm8994_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record||
2041         wm8994_mode==wm8994_mainMIC_to_baseband_to_speakers||
2042         wm8994_mode==wm8994_mainMIC_to_baseband_with_AP_to_speakers)
2043         {
2044                 wm8994_read(0x0026, &lvol);
2045                 wm8994_read(0x0027, &rvol);
2046                 //SPKOUTL_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2047                 wm8994_write(0x0026, (lvol&~0x003f)|speakers_vol_table[volume]);
2048                 //SPKOUTR_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2049                 wm8994_write(0x0027, (lvol&~0x003f)|speakers_vol_table[volume]);
2050         }
2051         else if(wm8994_mode==wm8994_mainMIC_to_baseband_to_earpiece||
2052         wm8994_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)
2053         {
2054                 wm8994_read(0x0020, &lvol);
2055                 wm8994_read(0x0021, &rvol);
2056
2057                 //MIXOUTL_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2058                 wm8994_write(0x0020, (lvol&~0x003f)|earpiece_vol_table[volume]);
2059                 //MIXOUTR_VOL bit 0~5 /-57dB to +6dB in 1dB steps
2060                 wm8994_write(0x0021, (lvol&~0x003f)|earpiece_vol_table[volume]);
2061         }
2062         else if(wm8994_mode==wm8994_BT_baseband||wm8994_mode==wm8994_BT_baseband_and_record)
2063         {
2064                 wm8994_read(0x0019, &lvol);
2065                 wm8994_read(0x001b, &rvol);
2066                 //bit 0~4 /-16.5dB to +30dB in 1.5dB steps
2067                 wm8994_write(0x0019, (lvol&~0x000f)|BT_vol_table[volume]);
2068                 //bit 0~4 /-16.5dB to +30dB in 1.5dB steps
2069                 wm8994_write(0x001b, (lvol&~0x000f)|BT_vol_table[volume]);
2070         }
2071 }
2072
2073 #define SOC_DOUBLE_SWITCH_WM8994CODEC(xname, route) \
2074 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2075         .info = snd_soc_info_route, \
2076         .get = snd_soc_get_route, .put = snd_soc_put_route, \
2077         .private_value = route }
2078
2079 int snd_soc_info_route(struct snd_kcontrol *kcontrol,
2080         struct snd_ctl_elem_info *uinfo)
2081 {
2082         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2083
2084         uinfo->count = 1;
2085         uinfo->value.integer.min = 0;
2086         uinfo->value.integer.max = 0;
2087         return 0;
2088 }
2089
2090 int snd_soc_get_route(struct snd_kcontrol *kcontrol,
2091         struct snd_ctl_elem_value *ucontrol)
2092 {
2093         return 0;
2094 }
2095
2096 int snd_soc_put_route(struct snd_kcontrol *kcontrol,
2097         struct snd_ctl_elem_value *ucontrol)
2098 {
2099         int route = kcontrol->private_value & 0xff;
2100
2101         switch(route)
2102         {
2103                 /* Speaker*/
2104                 case SPEAKER_NORMAL: //AP-> 8994Codec -> Speaker
2105                         recorder_and_AP_to_speakers();
2106                         break;
2107                 case SPEAKER_INCALL: //BB-> 8994Codec -> Speaker
2108                         mainMIC_to_baseband_to_speakers();
2109                         break;
2110
2111                 /* Headset */
2112                 case HEADSET_NORMAL:    //AP-> 8994Codec -> Headset
2113                         recorder_and_AP_to_headset();
2114                         break;
2115                 case HEADSET_INCALL:    //AP-> 8994Codec -> Headset
2116                         handsetMIC_to_baseband_to_headset();
2117                         break;
2118
2119                 /* Earpiece*/
2120                 case EARPIECE_INCALL:   //:BB-> 8994Codec -> EARPIECE
2121 #ifdef CONFIG_SND_NO_EARPIECE
2122                         mainMIC_to_baseband_to_speakers();
2123 #else
2124                         mainMIC_to_baseband_to_earpiece();
2125 #endif
2126                         break;
2127
2128                 case EARPIECE_NORMAL:   //:BB-> 8994Codec -> EARPIECE
2129                         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset)
2130                                 recorder_and_AP_to_headset();
2131                         else if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers||
2132                                 wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)
2133                                 recorder_and_AP_to_speakers();
2134                         else if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers||
2135                                 wm8994_current_mode==wm8994_recorder_and_AP_to_speakers)
2136                                 break;
2137                         else{
2138                                 recorder_and_AP_to_speakers();
2139                                 printk("%s--%d--: wm8994 with null mode\n",__FUNCTION__,__LINE__);
2140                         }
2141                         break;
2142
2143
2144                 /* BLUETOOTH_SCO*/
2145                 case BLUETOOTH_SCO_INCALL:      //BB-> 8994Codec -> BLUETOOTH_SCO
2146                         BT_baseband();
2147                         break;
2148
2149                 /* BLUETOOTH_A2DP*/
2150                 case BLUETOOTH_A2DP_NORMAL:     //AP-> 8994Codec -> BLUETOOTH_A2DP
2151                         break;
2152
2153                 case MIC_CAPTURE:
2154                         if(wm8994_current_mode==wm8994_AP_to_headset)
2155                                 recorder_and_AP_to_headset();
2156                         else if(wm8994_current_mode==wm8994_AP_to_speakers)
2157                                 recorder_and_AP_to_speakers();
2158                         else if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers||
2159                                 wm8994_current_mode==wm8994_recorder_and_AP_to_headset)
2160                                 break;
2161                         else{
2162                                 recorder_and_AP_to_speakers();
2163                                 printk("%s--%d--: wm8994 with null mode\n",__FUNCTION__,__LINE__);
2164                         }
2165                         break;
2166
2167                 case EARPIECE_RINGTONE:
2168                         AP_to_speakers();
2169                         break;
2170
2171                 case HEADSET_RINGTONE:
2172                         AP_to_headset();
2173                         break;
2174
2175                 case SPEAKER_RINGTONE:
2176                         AP_to_speakers();
2177                         break;
2178
2179                 default:
2180                         //codec_daout_route();
2181                         break;
2182         }
2183         return 0;
2184 }
2185 /*
2186  * WM8994 Controls
2187  */
2188
2189 static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
2190 static const struct soc_enum bass_boost =
2191         SOC_ENUM_SINGLE(WM8994_BASS, 7, 2, bass_boost_txt);
2192
2193 static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
2194 static const struct soc_enum bass_filter =
2195         SOC_ENUM_SINGLE(WM8994_BASS, 6, 2, bass_filter_txt);
2196
2197 static const char *treble_txt[] = {"8kHz", "4kHz"};
2198 static const struct soc_enum treble =
2199         SOC_ENUM_SINGLE(WM8994_TREBLE, 6, 2, treble_txt);
2200
2201 static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
2202 static const struct soc_enum stereo_3d_lc =
2203         SOC_ENUM_SINGLE(WM8994_3D, 5, 2, stereo_3d_lc_txt);
2204
2205 static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
2206 static const struct soc_enum stereo_3d_uc =
2207         SOC_ENUM_SINGLE(WM8994_3D, 6, 2, stereo_3d_uc_txt);
2208
2209 static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
2210 static const struct soc_enum stereo_3d_func =
2211         SOC_ENUM_SINGLE(WM8994_3D, 7, 2, stereo_3d_func_txt);
2212
2213 static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
2214 static const struct soc_enum alc_func =
2215         SOC_ENUM_SINGLE(WM8994_ALC1, 7, 4, alc_func_txt);
2216
2217 static const char *ng_type_txt[] = {"Constant PGA Gain",
2218                                     "Mute ADC Output"};
2219 static const struct soc_enum ng_type =
2220         SOC_ENUM_SINGLE(WM8994_NGATE, 1, 2, ng_type_txt);
2221
2222 static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
2223 static const struct soc_enum deemph =
2224         SOC_ENUM_SINGLE(WM8994_ADCDAC, 1, 4, deemph_txt);
2225
2226 static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
2227                                    "L + R Invert"};
2228 static const struct soc_enum adcpol =
2229         SOC_ENUM_SINGLE(WM8994_ADCDAC, 5, 4, adcpol_txt);
2230
2231 static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
2232 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
2233 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
2234 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
2235 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
2236
2237 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
2238
2239 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker incall Switch", SPEAKER_INCALL),
2240 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker normal Switch", SPEAKER_NORMAL),
2241
2242 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece incall Switch", EARPIECE_INCALL),
2243 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece normal Switch", EARPIECE_NORMAL),
2244
2245 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset incall Switch", HEADSET_INCALL),
2246 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset normal Switch", HEADSET_NORMAL),
2247
2248 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth incall Switch", BLUETOOTH_SCO_INCALL),
2249 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth normal Switch", BLUETOOTH_SCO_NORMAL),
2250
2251 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP incall Switch", BLUETOOTH_A2DP_INCALL),
2252 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP normal Switch", BLUETOOTH_A2DP_NORMAL),
2253
2254 SOC_DOUBLE_SWITCH_WM8994CODEC("Capture Switch", MIC_CAPTURE),
2255
2256 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece ringtone Switch",EARPIECE_RINGTONE),
2257 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker ringtone Switch",SPEAKER_RINGTONE),
2258 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset ringtone Switch",HEADSET_RINGTONE),
2259 };
2260
2261 /*
2262  * DAPM Controls
2263  */
2264
2265 static int wm8994_lrc_control(struct snd_soc_dapm_widget *w,
2266                               struct snd_kcontrol *kcontrol, int event)
2267 {
2268         return 0;
2269 }
2270
2271 static const char *wm8994_line_texts[] = {
2272         "Line 1", "Line 2", "PGA", "Differential"};
2273
2274 static const unsigned int wm8994_line_values[] = {
2275         0, 1, 3, 4};
2276
2277 static const struct soc_enum wm8994_lline_enum =
2278         SOC_VALUE_ENUM_SINGLE(WM8994_LOUTM1, 0, 7,
2279                               ARRAY_SIZE(wm8994_line_texts),
2280                               wm8994_line_texts,
2281                               wm8994_line_values);
2282 static const struct snd_kcontrol_new wm8994_left_line_controls =
2283         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
2284
2285 static const struct soc_enum wm8994_rline_enum =
2286         SOC_VALUE_ENUM_SINGLE(WM8994_ROUTM1, 0, 7,
2287                               ARRAY_SIZE(wm8994_line_texts),
2288                               wm8994_line_texts,
2289                               wm8994_line_values);
2290 static const struct snd_kcontrol_new wm8994_right_line_controls =
2291         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
2292
2293 /* Left Mixer */
2294 static const struct snd_kcontrol_new wm8994_left_mixer_controls[] = {
2295         SOC_DAPM_SINGLE("Playback Switch", WM8994_LOUTM1, 8, 1, 0),
2296         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_LOUTM1, 7, 1, 0),
2297         SOC_DAPM_SINGLE("Right Playback Switch", WM8994_LOUTM2, 8, 1, 0),
2298         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_LOUTM2, 7, 1, 0),
2299 };
2300
2301 /* Right Mixer */
2302 static const struct snd_kcontrol_new wm8994_right_mixer_controls[] = {
2303         SOC_DAPM_SINGLE("Left Playback Switch", WM8994_ROUTM1, 8, 1, 0),
2304         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_ROUTM1, 7, 1, 0),
2305         SOC_DAPM_SINGLE("Playback Switch", WM8994_ROUTM2, 8, 1, 0),
2306         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_ROUTM2, 7, 1, 0),
2307 };
2308
2309 static const char *wm8994_pga_sel[] = {"Line 1", "Line 2", "Differential"};
2310 static const unsigned int wm8994_pga_val[] = { 0, 1, 3 };
2311
2312 /* Left PGA Mux */
2313 static const struct soc_enum wm8994_lpga_enum =
2314         SOC_VALUE_ENUM_SINGLE(WM8994_LADCIN, 6, 3,
2315                               ARRAY_SIZE(wm8994_pga_sel),
2316                               wm8994_pga_sel,
2317                               wm8994_pga_val);
2318 static const struct snd_kcontrol_new wm8994_left_pga_controls =
2319         SOC_DAPM_VALUE_ENUM("Route", wm8994_lpga_enum);
2320
2321 /* Right PGA Mux */
2322 static const struct soc_enum wm8994_rpga_enum =
2323         SOC_VALUE_ENUM_SINGLE(WM8994_RADCIN, 6, 3,
2324                               ARRAY_SIZE(wm8994_pga_sel),
2325                               wm8994_pga_sel,
2326                               wm8994_pga_val);
2327 static const struct snd_kcontrol_new wm8994_right_pga_controls =
2328         SOC_DAPM_VALUE_ENUM("Route", wm8994_rpga_enum);
2329
2330 /* Differential Mux */
2331 static const char *wm8994_diff_sel[] = {"Line 1", "Line 2"};
2332 static const struct soc_enum diffmux =
2333         SOC_ENUM_SINGLE(WM8994_ADCIN, 8, 2, wm8994_diff_sel);
2334 static const struct snd_kcontrol_new wm8994_diffmux_controls =
2335         SOC_DAPM_ENUM("Route", diffmux);
2336
2337 /* Mono ADC Mux */
2338 static const char *wm8994_mono_mux[] = {"Stereo", "Mono (Left)",
2339         "Mono (Right)", "Digital Mono"};
2340 static const struct soc_enum monomux =
2341         SOC_ENUM_SINGLE(WM8994_ADCIN, 6, 4, wm8994_mono_mux);
2342 static const struct snd_kcontrol_new wm8994_monomux_controls =
2343         SOC_DAPM_ENUM("Route", monomux);
2344
2345 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
2346         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8994_PWR1, 1, 0),
2347
2348         SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
2349                 &wm8994_diffmux_controls),
2350         SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
2351                 &wm8994_monomux_controls),
2352         SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
2353                 &wm8994_monomux_controls),
2354
2355         SND_SOC_DAPM_MUX("Left PGA Mux", WM8994_PWR1, 5, 0,
2356                 &wm8994_left_pga_controls),
2357         SND_SOC_DAPM_MUX("Right PGA Mux", WM8994_PWR1, 4, 0,
2358                 &wm8994_right_pga_controls),
2359
2360         SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
2361                 &wm8994_left_line_controls),
2362         SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
2363                 &wm8994_right_line_controls),
2364
2365         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8994_PWR1, 2, 0),
2366         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8994_PWR1, 3, 0),
2367
2368         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8994_PWR2, 7, 0),
2369         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8994_PWR2, 8, 0),
2370
2371         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
2372                 &wm8994_left_mixer_controls[0],
2373                 ARRAY_SIZE(wm8994_left_mixer_controls)),
2374         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
2375                 &wm8994_right_mixer_controls[0],
2376                 ARRAY_SIZE(wm8994_right_mixer_controls)),
2377
2378         SND_SOC_DAPM_PGA("Right Out 2", WM8994_PWR2, 3, 0, NULL, 0),
2379         SND_SOC_DAPM_PGA("Left Out 2", WM8994_PWR2, 4, 0, NULL, 0),
2380         SND_SOC_DAPM_PGA("Right Out 1", WM8994_PWR2, 5, 0, NULL, 0),
2381         SND_SOC_DAPM_PGA("Left Out 1", WM8994_PWR2, 6, 0, NULL, 0),
2382
2383         SND_SOC_DAPM_POST("LRC control", wm8994_lrc_control),
2384
2385         SND_SOC_DAPM_OUTPUT("LOUT1"),
2386         SND_SOC_DAPM_OUTPUT("ROUT1"),
2387         SND_SOC_DAPM_OUTPUT("LOUT2"),
2388         SND_SOC_DAPM_OUTPUT("ROUT2"),
2389         SND_SOC_DAPM_OUTPUT("VREF"),
2390
2391         SND_SOC_DAPM_INPUT("LINPUT1"),
2392         SND_SOC_DAPM_INPUT("LINPUT2"),
2393         SND_SOC_DAPM_INPUT("RINPUT1"),
2394         SND_SOC_DAPM_INPUT("RINPUT2"),
2395 };
2396
2397 static const struct snd_soc_dapm_route audio_map[] = {
2398
2399         { "Left Line Mux", "Line 1", "LINPUT1" },
2400         { "Left Line Mux", "Line 2", "LINPUT2" },
2401         { "Left Line Mux", "PGA", "Left PGA Mux" },
2402         { "Left Line Mux", "Differential", "Differential Mux" },
2403
2404         { "Right Line Mux", "Line 1", "RINPUT1" },
2405         { "Right Line Mux", "Line 2", "RINPUT2" },
2406         { "Right Line Mux", "PGA", "Right PGA Mux" },
2407         { "Right Line Mux", "Differential", "Differential Mux" },
2408
2409         { "Left PGA Mux", "Line 1", "LINPUT1" },
2410         { "Left PGA Mux", "Line 2", "LINPUT2" },
2411         { "Left PGA Mux", "Differential", "Differential Mux" },
2412
2413         { "Right PGA Mux", "Line 1", "RINPUT1" },
2414         { "Right PGA Mux", "Line 2", "RINPUT2" },
2415         { "Right PGA Mux", "Differential", "Differential Mux" },
2416
2417         { "Differential Mux", "Line 1", "LINPUT1" },
2418         { "Differential Mux", "Line 1", "RINPUT1" },
2419         { "Differential Mux", "Line 2", "LINPUT2" },
2420         { "Differential Mux", "Line 2", "RINPUT2" },
2421
2422         { "Left ADC Mux", "Stereo", "Left PGA Mux" },
2423         { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
2424         { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
2425
2426         { "Right ADC Mux", "Stereo", "Right PGA Mux" },
2427         { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
2428         { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
2429
2430         { "Left ADC", NULL, "Left ADC Mux" },
2431         { "Right ADC", NULL, "Right ADC Mux" },
2432
2433         { "Left Line Mux", "Line 1", "LINPUT1" },
2434         { "Left Line Mux", "Line 2", "LINPUT2" },
2435         { "Left Line Mux", "PGA", "Left PGA Mux" },
2436         { "Left Line Mux", "Differential", "Differential Mux" },
2437
2438         { "Right Line Mux", "Line 1", "RINPUT1" },
2439         { "Right Line Mux", "Line 2", "RINPUT2" },
2440         { "Right Line Mux", "PGA", "Right PGA Mux" },
2441         { "Right Line Mux", "Differential", "Differential Mux" },
2442
2443         { "Left Mixer", "Playback Switch", "Left DAC" },
2444         { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
2445         { "Left Mixer", "Right Playback Switch", "Right DAC" },
2446         { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
2447
2448         { "Right Mixer", "Left Playback Switch", "Left DAC" },
2449         { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
2450         { "Right Mixer", "Playback Switch", "Right DAC" },
2451         { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
2452
2453         { "Left Out 1", NULL, "Left Mixer" },
2454         { "LOUT1", NULL, "Left Out 1" },
2455         { "Right Out 1", NULL, "Right Mixer" },
2456         { "ROUT1", NULL, "Right Out 1" },
2457
2458         { "Left Out 2", NULL, "Left Mixer" },
2459         { "LOUT2", NULL, "Left Out 2" },
2460         { "Right Out 2", NULL, "Right Mixer" },
2461         { "ROUT2", NULL, "Right Out 2" },
2462 };
2463
2464 struct _coeff_div {
2465         u32 mclk;
2466         u32 rate;
2467         u16 fs;
2468         u8 sr:5;
2469         u8 usb:1;
2470 };
2471
2472 /* codec hifi mclk clock divider coefficients */
2473 static const struct _coeff_div coeff_div[] = {
2474         /* 8k */
2475         {12288000, 8000, 1536, 0x6, 0x0},
2476         {11289600, 8000, 1408, 0x16, 0x0},
2477         {18432000, 8000, 2304, 0x7, 0x0},
2478         {16934400, 8000, 2112, 0x17, 0x0},
2479         {12000000, 8000, 1500, 0x6, 0x1},
2480
2481         /* 11.025k */
2482         {11289600, 11025, 1024, 0x18, 0x0},
2483         {16934400, 11025, 1536, 0x19, 0x0},
2484         {12000000, 11025, 1088, 0x19, 0x1},
2485
2486         /* 16k */
2487         {12288000, 16000, 768, 0xa, 0x0},
2488         {18432000, 16000, 1152, 0xb, 0x0},
2489         {12000000, 16000, 750, 0xa, 0x1},
2490
2491         /* 22.05k */
2492         {11289600, 22050, 512, 0x1a, 0x0},
2493         {16934400, 22050, 768, 0x1b, 0x0},
2494         {12000000, 22050, 544, 0x1b, 0x1},
2495
2496         /* 32k */
2497         {12288000, 32000, 384, 0xc, 0x0},
2498         {18432000, 32000, 576, 0xd, 0x0},
2499         {12000000, 32000, 375, 0xa, 0x1},
2500
2501         /* 44.1k */
2502         {11289600, 44100, 256, 0x10, 0x0},
2503         {16934400, 44100, 384, 0x11, 0x0},
2504         {12000000, 44100, 272, 0x11, 0x1},
2505
2506         /* 48k */
2507         {12288000, 48000, 256, 0x0, 0x0},
2508         {18432000, 48000, 384, 0x1, 0x0},
2509         {12000000, 48000, 250, 0x0, 0x1},
2510
2511         /* 88.2k */
2512         {11289600, 88200, 128, 0x1e, 0x0},
2513         {16934400, 88200, 192, 0x1f, 0x0},
2514         {12000000, 88200, 136, 0x1f, 0x1},
2515
2516         /* 96k */
2517         {12288000, 96000, 128, 0xe, 0x0},
2518         {18432000, 96000, 192, 0xf, 0x0},
2519         {12000000, 96000, 125, 0xe, 0x1},
2520 };
2521
2522
2523 static inline int get_coeff(int mclk, int rate)
2524 {
2525         int i;
2526
2527         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
2528                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
2529                         return i;
2530         }
2531
2532         return -EINVAL;
2533 }
2534
2535 /* The set of rates we can generate from the above for each SYSCLK */
2536
2537 static unsigned int rates_12288[] = {
2538         8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
2539 };
2540
2541 static struct snd_pcm_hw_constraint_list constraints_12288 = {
2542         .count  = ARRAY_SIZE(rates_12288),
2543         .list   = rates_12288,
2544 };
2545
2546 static unsigned int rates_112896[] = {
2547         8000, 11025, 22050, 44100,
2548 };
2549
2550 static struct snd_pcm_hw_constraint_list constraints_112896 = {
2551         .count  = ARRAY_SIZE(rates_112896),
2552         .list   = rates_112896,
2553 };
2554
2555 static unsigned int rates_12[] = {
2556         8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
2557         48000, 88235, 96000,
2558 };
2559
2560 static struct snd_pcm_hw_constraint_list constraints_12 = {
2561         .count  = ARRAY_SIZE(rates_12),
2562         .list   = rates_12,
2563 };
2564
2565 /*
2566  * Note that this should be called from init rather than from hw_params.
2567  */
2568 static int wm8994_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2569                 int clk_id, unsigned int freq, int dir)
2570 {
2571         struct snd_soc_codec *codec = codec_dai->codec;
2572         struct wm8994_priv *wm8994 = codec->private_data;
2573
2574         DBG("%s----%d\n",__FUNCTION__,__LINE__);
2575
2576         switch (freq) {
2577         case 11289600:
2578         case 18432000:
2579         case 22579200:
2580         case 36864000:
2581                 wm8994->sysclk_constraints = &constraints_112896;
2582                 wm8994->sysclk = freq;
2583                 return 0;
2584
2585         case 12288000:
2586         case 16934400:
2587         case 24576000:
2588         case 33868800:
2589                 wm8994->sysclk_constraints = &constraints_12288;
2590                 wm8994->sysclk = freq;
2591                 return 0;
2592
2593         case 12000000:
2594         case 24000000:
2595                 wm8994->sysclk_constraints = &constraints_12;
2596                 wm8994->sysclk = freq;
2597                 return 0;
2598         }
2599         return -EINVAL;
2600 }
2601
2602 static int wm8994_set_dai_fmt(struct snd_soc_dai *codec_dai,
2603                 unsigned int fmt)
2604 {
2605         return 0;
2606 }
2607
2608 static int wm8994_pcm_startup(struct snd_pcm_substream *substream,
2609                               struct snd_soc_dai *dai)
2610 {
2611         struct snd_soc_codec *codec = dai->codec;
2612         struct wm8994_priv *wm8994 = codec->private_data;
2613
2614         /* The set of sample rates that can be supported depends on the
2615          * MCLK supplied to the CODEC - enforce this.
2616          */
2617
2618         if (!wm8994->sysclk) {
2619                 dev_err(codec->dev,
2620                         "No MCLK configured, call set_sysclk() on init\n");
2621                 return -EINVAL;
2622         }
2623
2624         snd_pcm_hw_constraint_list(substream->runtime, 0,
2625                                    SNDRV_PCM_HW_PARAM_RATE,
2626                                    wm8994->sysclk_constraints);
2627
2628         return 0;
2629 }
2630
2631 static int wm8994_pcm_hw_params(struct snd_pcm_substream *substream,
2632                                 struct snd_pcm_hw_params *params,
2633                                 struct snd_soc_dai *dai)
2634 {
2635         struct snd_soc_pcm_runtime *rtd = substream->private_data;
2636         struct snd_soc_device *socdev = rtd->socdev;
2637         struct snd_soc_codec *codec = socdev->card->codec;
2638         struct wm8994_priv *wm8994 = codec->private_data;
2639         int coeff;
2640
2641         coeff = get_coeff(wm8994->sysclk, params_rate(params));
2642         if (coeff < 0) {
2643                 coeff = get_coeff(wm8994->sysclk / 2, params_rate(params));
2644         }
2645         if (coeff < 0) {
2646                 dev_err(codec->dev,
2647                         "Unable to configure sample rate %dHz with %dHz MCLK\n",
2648                         params_rate(params), wm8994->sysclk);
2649                 return coeff;
2650         }
2651         params_format(params);
2652
2653         return 0;
2654 }
2655
2656 static int wm8994_mute(struct snd_soc_dai *dai, int mute)
2657 {
2658         return 0;
2659 }
2660
2661 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2662                                  enum snd_soc_bias_level level)
2663 {
2664
2665         codec->bias_level = level;
2666         return 0;
2667 }
2668
2669 #define WM8994_RATES SNDRV_PCM_RATE_48000
2670
2671 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2672         SNDRV_PCM_FMTBIT_S24_LE)
2673
2674 static struct snd_soc_dai_ops wm8994_ops = {
2675         .startup = wm8994_pcm_startup,
2676         .hw_params = wm8994_pcm_hw_params,
2677         .set_fmt = wm8994_set_dai_fmt,
2678         .set_sysclk = wm8994_set_dai_sysclk,
2679         .digital_mute = wm8994_mute,
2680         /*add by qiuen for volume*/
2681         .set_volume = wm8994_codec_set_volume,
2682 };
2683
2684 struct snd_soc_dai wm8994_dai = {
2685         .name = "WM8994",
2686         .playback = {
2687                 .stream_name = "Playback",
2688                 .channels_min = 1,
2689                 .channels_max = 2,
2690                 .rates = WM8994_RATES,
2691                 .formats = WM8994_FORMATS,
2692         },
2693         .capture = {
2694                 .stream_name = "Capture",
2695                 .channels_min = 2,
2696                 .channels_max = 2,
2697                 .rates = WM8994_RATES,
2698                 .formats = WM8994_FORMATS,
2699          },
2700         .ops = &wm8994_ops,
2701         .symmetric_rates = 1,
2702 };
2703 EXPORT_SYMBOL_GPL(wm8994_dai);
2704
2705 static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
2706 {
2707         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2708         struct snd_soc_codec *codec = socdev->card->codec;
2709
2710         wm8994_set_bias_level(codec,SND_SOC_BIAS_OFF);
2711         wm8994_reset();
2712         msleep(WM8994_DELAY);
2713         return 0;
2714 }
2715
2716 static int wm8994_resume(struct platform_device *pdev)
2717 {
2718         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2719         struct snd_soc_codec *codec = socdev->card->codec;
2720         wm8994_codec_fnc_t **wm8994_fnc_ptr=wm8994_codec_sequence;
2721         unsigned char wm8994_resume_mode=wm8994_current_mode;
2722         wm8994_current_mode=null;
2723
2724         wm8994_set_bias_level(codec,SND_SOC_BIAS_STANDBY);
2725         if(wm8994_resume_mode<=wm8994_recorder_and_AP_to_speakers)
2726         {
2727                 wm8994_fnc_ptr+=wm8994_resume_mode;
2728                 (*wm8994_fnc_ptr)() ;
2729         }
2730         else if(wm8994_resume_mode>wm8994_BT_baseband_and_record)
2731         {
2732                 printk("%s--%d--: Wm8994 resume with null mode\n",__FUNCTION__,__LINE__);
2733         }
2734         else
2735         {
2736                 wm8994_fnc_ptr+=wm8994_resume_mode;
2737                 (*wm8994_fnc_ptr)();
2738                 printk("%s--%d--: Wm8994 resume with error mode\n",__FUNCTION__,__LINE__);
2739         }
2740
2741         return 0;
2742 }
2743
2744 static struct snd_soc_codec *wm8994_codec;
2745
2746 static int wm8994_probe(struct platform_device *pdev)
2747 {
2748         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2749         struct snd_soc_codec *codec;
2750         int ret = 0;
2751
2752         if (wm8994_codec == NULL) {
2753                 dev_err(&pdev->dev, "Codec device not registered\n");
2754                 return -ENODEV;
2755         }
2756
2757         socdev->card->codec = wm8994_codec;
2758         codec = wm8994_codec;
2759
2760         /* register pcms */
2761         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2762         if (ret < 0) {
2763                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
2764                 goto pcm_err;
2765         }
2766
2767         snd_soc_add_controls(codec,wm8994_snd_controls,
2768                                 ARRAY_SIZE(wm8994_snd_controls));
2769         snd_soc_dapm_new_controls(codec,wm8994_dapm_widgets,
2770                                   ARRAY_SIZE(wm8994_dapm_widgets));
2771         snd_soc_dapm_add_routes(codec,audio_map, ARRAY_SIZE(audio_map));
2772         snd_soc_dapm_new_widgets(codec);
2773
2774         ret = snd_soc_init_card(socdev);
2775         if (ret < 0) {
2776                 dev_err(codec->dev, "failed to register card: %d\n", ret);
2777                 goto card_err;
2778         }
2779
2780         return ret;
2781
2782 card_err:
2783         snd_soc_free_pcms(socdev);
2784         snd_soc_dapm_free(socdev);
2785 pcm_err:
2786         return ret;
2787 }
2788
2789 static int wm8994_remove(struct platform_device *pdev)
2790 {
2791         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2792
2793         snd_soc_free_pcms(socdev);
2794         snd_soc_dapm_free(socdev);
2795
2796         return 0;
2797 }
2798
2799 struct snd_soc_codec_device soc_codec_dev_wm8994 = {
2800         .probe =        wm8994_probe,
2801         .remove =       wm8994_remove,
2802         .suspend =      wm8994_suspend,
2803         .resume =       wm8994_resume,
2804 };
2805 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
2806
2807 static int wm8994_register(struct wm8994_priv *wm8994,
2808                            enum snd_soc_control_type control)
2809 {
2810         struct snd_soc_codec *codec = &wm8994->codec;
2811         int ret;
2812
2813         if (wm8994_codec) {
2814                 dev_err(codec->dev, "Another WM8994 is registered\n");
2815                 ret = -EINVAL;
2816                 goto err;
2817         }
2818
2819         mutex_init(&codec->mutex);
2820         INIT_LIST_HEAD(&codec->dapm_widgets);
2821         INIT_LIST_HEAD(&codec->dapm_paths);
2822
2823         codec->private_data = wm8994;
2824         codec->name = "WM8994";
2825         codec->owner = THIS_MODULE;
2826         codec->dai = &wm8994_dai;
2827         codec->num_dai = 1;
2828         codec->reg_cache_size = ARRAY_SIZE(wm8994->reg_cache);
2829         codec->reg_cache = &wm8994->reg_cache;
2830         codec->bias_level = SND_SOC_BIAS_OFF;
2831         codec->set_bias_level = wm8994_set_bias_level;
2832
2833         memcpy(codec->reg_cache, wm8994_reg,
2834                sizeof(wm8994_reg));
2835
2836         ret = snd_soc_codec_set_cache_io(codec,7, 9, control);
2837         if (ret < 0) {
2838                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2839                 goto err;
2840         }
2841
2842         ret = 0;//wm8994_reset(); cjq
2843         if (ret < 0) {
2844                 dev_err(codec->dev, "Failed to issue reset\n");
2845                 goto err;
2846         }
2847
2848         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_STANDBY);
2849
2850         wm8994_dai.dev = codec->dev;
2851
2852         wm8994_codec = codec;
2853
2854         ret = snd_soc_register_codec(codec);
2855         if (ret != 0) {
2856                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2857                 goto err;
2858         }
2859
2860         ret = snd_soc_register_dai(&wm8994_dai);
2861         if (ret != 0) {
2862                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
2863                 snd_soc_unregister_codec(codec);
2864                 goto err_codec;
2865         }
2866         return 0;
2867
2868 err_codec:
2869         snd_soc_unregister_codec(codec);
2870 err:
2871         kfree(wm8994);
2872         return ret;
2873 }
2874
2875 static void wm8994_unregister(struct wm8994_priv *wm8994)
2876 {
2877         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_OFF);
2878         snd_soc_unregister_dai(&wm8994_dai);
2879         snd_soc_unregister_codec(&wm8994->codec);
2880         kfree(wm8994);
2881         wm8994_codec = NULL;
2882 }
2883
2884 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2885 static int wm8994_i2c_probe(struct i2c_client *i2c,
2886                             const struct i2c_device_id *id)
2887 {
2888         struct wm8994_priv *wm8994;
2889         struct snd_soc_codec *codec;
2890         wm8994_client=i2c;
2891
2892         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2893         if (wm8994 == NULL)
2894                 return -ENOMEM;
2895
2896         codec = &wm8994->codec;
2897
2898         i2c_set_clientdata(i2c, wm8994);
2899         codec->control_data = i2c;
2900
2901         codec->dev = &i2c->dev;
2902
2903         return wm8994_register(wm8994, SND_SOC_I2C);
2904 }
2905
2906 static int wm8994_i2c_remove(struct i2c_client *client)
2907 {
2908         struct wm8994_priv *wm8994 = i2c_get_clientdata(client);
2909         wm8994_unregister(wm8994);
2910         return 0;
2911 }
2912
2913 #ifdef CONFIG_PM
2914 static int wm8994_i2c_suspend(struct i2c_client *client, pm_message_t msg)
2915 {
2916         return snd_soc_suspend_device(&client->dev);
2917 }
2918
2919 static int wm8994_i2c_resume(struct i2c_client *client)
2920 {
2921         return snd_soc_resume_device(&client->dev);
2922 }
2923 #else
2924 #define wm8994_i2c_suspend NULL
2925 #define wm8994_i2c_resume NULL
2926 #endif
2927
2928 static const struct i2c_device_id wm8994_i2c_id[] = {
2929         { "wm8994", 0 },
2930         { }
2931 };
2932 MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
2933
2934 static struct i2c_driver wm8994_i2c_driver = {
2935         .driver = {
2936                 .name = "WM8994",
2937                 .owner = THIS_MODULE,
2938         },
2939         .probe = wm8994_i2c_probe,
2940         .remove = wm8994_i2c_remove,
2941         .suspend = wm8994_i2c_suspend,
2942         .resume = wm8994_i2c_resume,
2943         .id_table = wm8994_i2c_id,
2944 };
2945
2946 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate)
2947 {
2948         int ret;
2949         struct i2c_adapter *adap = client->adapter;
2950         struct i2c_msg msg;
2951         char tx_buf[4];
2952
2953         memcpy(tx_buf, reg, 2);
2954         memcpy(tx_buf+2, data, 2);
2955         msg.addr = client->addr;
2956         msg.buf = tx_buf;
2957         msg.len = 4;
2958         msg.flags = client->flags;
2959         msg.scl_rate = scl_rate;
2960         msg.read_type = I2C_NORMAL;
2961         ret = i2c_transfer(adap, &msg, 1);
2962
2963         return ret;
2964 }
2965
2966 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate)
2967 {
2968         int ret;
2969         struct i2c_adapter *adap = client->adapter;
2970         struct i2c_msg msgs[2];
2971
2972         msgs[0].addr = client->addr;
2973         msgs[0].buf = (char *)reg;
2974         msgs[0].flags = client->flags;
2975         msgs[0].len = 2;
2976         msgs[0].scl_rate = scl_rate;
2977         msgs[0].read_type = I2C_NO_STOP;
2978
2979         msgs[1].addr = client->addr;
2980         msgs[1].buf = (char *)buf;
2981         msgs[1].flags = client->flags | I2C_M_RD;
2982         msgs[1].len = 2;
2983         msgs[1].scl_rate = scl_rate;
2984         msgs[1].read_type = I2C_NO_STOP;
2985
2986         ret = i2c_transfer(adap, msgs, 2);
2987
2988         return ret;
2989 }
2990
2991 #endif
2992
2993 #if defined(CONFIG_SPI_MASTER)
2994 static int __devinit wm8994_spi_probe(struct spi_device *spi)
2995 {
2996         struct wm8994_priv *wm8994;
2997         struct snd_soc_codec *codec;
2998
2999         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
3000         if (wm8994 == NULL)
3001                 return -ENOMEM;
3002
3003         codec = &wm8994->codec;
3004         codec->control_data = spi;
3005         codec->dev = &spi->dev;
3006
3007         dev_set_drvdata(&spi->dev, wm8994);
3008
3009         return wm8994_register(wm8994, SND_SOC_SPI);
3010 }
3011
3012 static int __devexit wm8994_spi_remove(struct spi_device *spi)
3013 {
3014         struct wm8994_priv *wm8994 = dev_get_drvdata(&spi->dev);
3015
3016         wm8994_unregister(wm8994);
3017
3018         return 0;
3019 }
3020
3021 #ifdef CONFIG_PM
3022 static int wm8994_spi_suspend(struct spi_device *spi, pm_message_t msg)
3023 {
3024         return snd_soc_suspend_device(&spi->dev);
3025 }
3026
3027 static int wm8994_spi_resume(struct spi_device *spi)
3028 {
3029         return snd_soc_resume_device(&spi->dev);
3030 }
3031 #else
3032 #define wm8994_spi_suspend NULL
3033 #define wm8994_spi_resume NULL
3034 #endif
3035
3036 static struct spi_driver wm8994_spi_driver = {
3037         .driver = {
3038                 .name   = "wm8994",
3039                 .bus    = &spi_bus_type,
3040                 .owner  = THIS_MODULE,
3041         },
3042         .probe          = wm8994_spi_probe,
3043         .remove         = __devexit_p(wm8994_spi_remove),
3044         .suspend        = wm8994_spi_suspend,
3045         .resume         = wm8994_spi_resume,
3046 };
3047 #endif
3048
3049 static int __init wm8994_modinit(void)
3050 {
3051         int ret;
3052
3053 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
3054         ret = i2c_add_driver(&wm8994_i2c_driver);
3055         if (ret != 0)
3056                 pr_err("WM8994: Unable to register I2C driver: %d\n", ret);
3057 #endif
3058 #if defined(CONFIG_SPI_MASTER)
3059         ret = spi_register_driver(&wm8994_spi_driver);
3060         if (ret != 0)
3061                 pr_err("WM8994: Unable to register SPI driver: %d\n", ret);
3062 #endif
3063         return ret;
3064 }
3065 module_init(wm8994_modinit);
3066
3067 static void __exit wm8994_exit(void)
3068 {
3069 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
3070         i2c_del_driver(&wm8994_i2c_driver);
3071 #endif
3072 #if defined(CONFIG_SPI_MASTER)
3073         spi_unregister_driver(&wm8994_spi_driver);
3074 #endif
3075 }
3076 module_exit(wm8994_exit);
3077
3078
3079 MODULE_DESCRIPTION("ASoC WM8994 driver");
3080 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3081 MODULE_LICENSE("GPL");