sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <trace/events/asoc.h>
  32
  33 #include <linux/mfd/wm8994/core.h>
  34 #include <linux/mfd/wm8994/registers.h>
  35 #include <linux/mfd/wm8994/pdata.h>
  36 #include <linux/mfd/wm8994/gpio.h>
  37
  38 #include "wm8994.h"
  39 #include "wm_hubs.h"
  40
  41 #define WM8994_NUM_DRC 3
  42 #define WM8994_NUM_EQ  3
  43
  44 static int wm8994_drc_base[] = {
  45         WM8994_AIF1_DRC1_1,
  46         WM8994_AIF1_DRC2_1,
  47         WM8994_AIF2_DRC_1,
  48 };
  49
  50 static int wm8994_retune_mobile_base[] = {
  51         WM8994_AIF1_DAC1_EQ_GAINS_1,
  52         WM8994_AIF1_DAC2_EQ_GAINS_1,
  53         WM8994_AIF2_EQ_GAINS_1,
  54 };
  55
  56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
  57 {
  58         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  59         struct wm8994 *control = wm8994->control_data;
  60
  61         switch (reg) {
  62         case WM8994_GPIO_1:
  63         case WM8994_GPIO_2:
  64         case WM8994_GPIO_3:
  65         case WM8994_GPIO_4:
  66         case WM8994_GPIO_5:
  67         case WM8994_GPIO_6:
  68         case WM8994_GPIO_7:
  69         case WM8994_GPIO_8:
  70         case WM8994_GPIO_9:
  71         case WM8994_GPIO_10:
  72         case WM8994_GPIO_11:
  73         case WM8994_INTERRUPT_STATUS_1:
  74         case WM8994_INTERRUPT_STATUS_2:
  75         case WM8994_INTERRUPT_RAW_STATUS_2:
  76                 return 1;
  77
  78         case WM8958_DSP2_PROGRAM:
  79         case WM8958_DSP2_CONFIG:
  80         case WM8958_DSP2_EXECCONTROL:
  81                 if (control->type == WM8958)
  82                         return 1;
  83                 else
  84                         return 0;
  85
  86         default:
  87                 break;
  88         }
  89
  90         if (reg >= WM8994_CACHE_SIZE)
  91                 return 0;
  92         return wm8994_access_masks[reg].readable != 0;
  93 }
  94
  95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
  96 {
  97         if (reg >= WM8994_CACHE_SIZE)
  98                 return 1;
  99
 100         switch (reg) {
 101         case WM8994_SOFTWARE_RESET:
 102         case WM8994_CHIP_REVISION:
 103         case WM8994_DC_SERVO_1:
 104         case WM8994_DC_SERVO_READBACK:
 105         case WM8994_RATE_STATUS:
 106         case WM8994_LDO_1:
 107         case WM8994_LDO_2:
 108         case WM8958_DSP2_EXECCONTROL:
 109         case WM8958_MIC_DETECT_3:
 110                 return 1;
 111         default:
 112                 return 0;
 113         }
 114 }
 115
 116 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 117         unsigned int value)
 118 {
 119         int ret;
 120
 121         BUG_ON(reg > WM8994_MAX_REGISTER);
 122
 123         if (!wm8994_volatile(codec, reg)) {
 124                 ret = snd_soc_cache_write(codec, reg, value);
 125                 if (ret != 0)
 126                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 127                                 reg, ret);
 128         }
 129
 130         return wm8994_reg_write(codec->control_data, reg, value);
 131 }
 132
 133 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 134                                 unsigned int reg)
 135 {
 136         unsigned int val;
 137         int ret;
 138
 139         BUG_ON(reg > WM8994_MAX_REGISTER);
 140
 141         if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
 142             reg < codec->driver->reg_cache_size) {
 143                 ret = snd_soc_cache_read(codec, reg, &val);
 144                 if (ret >= 0)
 145                         return val;
 146                 else
 147                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 148                                 reg, ret);
 149         }
 150
 151         return wm8994_reg_read(codec->control_data, reg);
 152 }
 153
 154 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 155 {
 156         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 157         int rate;
 158         int reg1 = 0;
 159         int offset;
 160
 161         if (aif)
 162                 offset = 4;
 163         else
 164                 offset = 0;
 165
 166         switch (wm8994->sysclk[aif]) {
 167         case WM8994_SYSCLK_MCLK1:
 168                 rate = wm8994->mclk[0];
 169                 break;
 170
 171         case WM8994_SYSCLK_MCLK2:
 172                 reg1 |= 0x8;
 173                 rate = wm8994->mclk[1];
 174                 break;
 175
 176         case WM8994_SYSCLK_FLL1:
 177                 reg1 |= 0x10;
 178                 rate = wm8994->fll[0].out;
 179                 break;
 180
 181         case WM8994_SYSCLK_FLL2:
 182                 reg1 |= 0x18;
 183                 rate = wm8994->fll[1].out;
 184                 break;
 185
 186         default:
 187                 return -EINVAL;
 188         }
 189
 190         if (rate >= 13500000) {
 191                 rate /= 2;
 192                 reg1 |= WM8994_AIF1CLK_DIV;
 193
 194                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 195                         aif + 1, rate);
 196         }
 197
 198         if (rate && rate < 3000000)
 199                 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
 200                          aif + 1, rate);
 201
 202         wm8994->aifclk[aif] = rate;
 203
 204         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 205                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 206                             reg1);
 207
 208         return 0;
 209 }
 210
 211 static int configure_clock(struct snd_soc_codec *codec)
 212 {
 213         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 214         int old, new;
 215
 216         /* Bring up the AIF clocks first */
 217         configure_aif_clock(codec, 0);
 218         configure_aif_clock(codec, 1);
 219
 220         /* Then switch CLK_SYS over to the higher of them; a change
 221          * can only happen as a result of a clocking change which can
 222          * only be made outside of DAPM so we can safely redo the
 223          * clocking.
 224          */
 225
 226         /* If they're equal it doesn't matter which is used */
 227         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 228                 return 0;
 229
 230         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 231                 new = WM8994_SYSCLK_SRC;
 232         else
 233                 new = 0;
 234
 235         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 236
 237         /* If there's no change then we're done. */
 238         if (old == new)
 239                 return 0;
 240
 241         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 242
 243         snd_soc_dapm_sync(&codec->dapm);
 244
 245         return 0;
 246 }
 247
 248 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 249                          struct snd_soc_dapm_widget *sink)
 250 {
 251         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 252         const char *clk;
 253
 254         /* Check what we're currently using for CLK_SYS */
 255         if (reg & WM8994_SYSCLK_SRC)
 256                 clk = "AIF2CLK";
 257         else
 258                 clk = "AIF1CLK";
 259
 260         return strcmp(source->name, clk) == 0;
 261 }
 262
 263 static const char *sidetone_hpf_text[] = {
 264         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 265 };
 266
 267 static const struct soc_enum sidetone_hpf =
 268         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 269
 270 static const char *adc_hpf_text[] = {
 271         "HiFi", "Voice 1", "Voice 2", "Voice 3"
 272 };
 273
 274 static const struct soc_enum aif1adc1_hpf =
 275         SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
 276
 277 static const struct soc_enum aif1adc2_hpf =
 278         SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
 279
 280 static const struct soc_enum aif2adc_hpf =
 281         SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
 282
 283 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 284 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 285 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 286 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 287 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 288
 289 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 290 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 291         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 292         .put = wm8994_put_drc_sw, \
 293         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 294
 295 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 296                              struct snd_ctl_elem_value *ucontrol)
 297 {
 298         struct soc_mixer_control *mc =
 299                 (struct soc_mixer_control *)kcontrol->private_value;
 300         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 301         int mask, ret;
 302
 303         /* Can't enable both ADC and DAC paths simultaneously */
 304         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 305                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 306                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 307         else
 308                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 309
 310         ret = snd_soc_read(codec, mc->reg);
 311         if (ret < 0)
 312                 return ret;
 313         if (ret & mask)
 314                 return -EINVAL;
 315
 316         return snd_soc_put_volsw(kcontrol, ucontrol);
 317 }
 318
 319 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 320 {
 321         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 322         struct wm8994_pdata *pdata = wm8994->pdata;
 323         int base = wm8994_drc_base[drc];
 324         int cfg = wm8994->drc_cfg[drc];
 325         int save, i;
 326
 327         /* Save any enables; the configuration should clear them. */
 328         save = snd_soc_read(codec, base);
 329         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 330                 WM8994_AIF1ADC1R_DRC_ENA;
 331
 332         for (i = 0; i < WM8994_DRC_REGS; i++)
 333                 snd_soc_update_bits(codec, base + i, 0xffff,
 334                                     pdata->drc_cfgs[cfg].regs[i]);
 335
 336         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 337                              WM8994_AIF1ADC1L_DRC_ENA |
 338                              WM8994_AIF1ADC1R_DRC_ENA, save);
 339 }
 340
 341 /* Icky as hell but saves code duplication */
 342 static int wm8994_get_drc(const char *name)
 343 {
 344         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 345                 return 0;
 346         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 347                 return 1;
 348         if (strcmp(name, "AIF2DRC Mode") == 0)
 349                 return 2;
 350         return -EINVAL;
 351 }
 352
 353 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 354                                struct snd_ctl_elem_value *ucontrol)
 355 {
 356         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 357         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 358         struct wm8994_pdata *pdata = wm8994->pdata;
 359         int drc = wm8994_get_drc(kcontrol->id.name);
 360         int value = ucontrol->value.integer.value[0];
 361
 362         if (drc < 0)
 363                 return drc;
 364
 365         if (value >= pdata->num_drc_cfgs)
 366                 return -EINVAL;
 367
 368         wm8994->drc_cfg[drc] = value;
 369
 370         wm8994_set_drc(codec, drc);
 371
 372         return 0;
 373 }
 374
 375 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 376                                struct snd_ctl_elem_value *ucontrol)
 377 {
 378         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 379         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 380         int drc = wm8994_get_drc(kcontrol->id.name);
 381
 382         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 383
 384         return 0;
 385 }
 386
 387 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 388 {
 389         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 390         struct wm8994_pdata *pdata = wm8994->pdata;
 391         int base = wm8994_retune_mobile_base[block];
 392         int iface, best, best_val, save, i, cfg;
 393
 394         if (!pdata || !wm8994->num_retune_mobile_texts)
 395                 return;
 396
 397         switch (block) {
 398         case 0:
 399         case 1:
 400                 iface = 0;
 401                 break;
 402         case 2:
 403                 iface = 1;
 404                 break;
 405         default:
 406                 return;
 407         }
 408
 409         /* Find the version of the currently selected configuration
 410          * with the nearest sample rate. */
 411         cfg = wm8994->retune_mobile_cfg[block];
 412         best = 0;
 413         best_val = INT_MAX;
 414         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 415                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 416                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 417                     abs(pdata->retune_mobile_cfgs[i].rate
 418                         - wm8994->dac_rates[iface]) < best_val) {
 419                         best = i;
 420                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 421                                        - wm8994->dac_rates[iface]);
 422                 }
 423         }
 424
 425         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 426                 block,
 427                 pdata->retune_mobile_cfgs[best].name,
 428                 pdata->retune_mobile_cfgs[best].rate,
 429                 wm8994->dac_rates[iface]);
 430
 431         /* The EQ will be disabled while reconfiguring it, remember the
 432          * current configuration.
 433          */
 434         save = snd_soc_read(codec, base);
 435         save &= WM8994_AIF1DAC1_EQ_ENA;
 436
 437         for (i = 0; i < WM8994_EQ_REGS; i++)
 438                 snd_soc_update_bits(codec, base + i, 0xffff,
 439                                 pdata->retune_mobile_cfgs[best].regs[i]);
 440
 441         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 442 }
 443
 444 /* Icky as hell but saves code duplication */
 445 static int wm8994_get_retune_mobile_block(const char *name)
 446 {
 447         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 448                 return 0;
 449         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 450                 return 1;
 451         if (strcmp(name, "AIF2 EQ Mode") == 0)
 452                 return 2;
 453         return -EINVAL;
 454 }
 455
 456 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 457                                          struct snd_ctl_elem_value *ucontrol)
 458 {
 459         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 460         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 461         struct wm8994_pdata *pdata = wm8994->pdata;
 462         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 463         int value = ucontrol->value.integer.value[0];
 464
 465         if (block < 0)
 466                 return block;
 467
 468         if (value >= pdata->num_retune_mobile_cfgs)
 469                 return -EINVAL;
 470
 471         wm8994->retune_mobile_cfg[block] = value;
 472
 473         wm8994_set_retune_mobile(codec, block);
 474
 475         return 0;
 476 }
 477
 478 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 479                                          struct snd_ctl_elem_value *ucontrol)
 480 {
 481         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 482         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 483         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 484
 485         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 486
 487         return 0;
 488 }
 489
 490 static const char *aif_chan_src_text[] = {
 491         "Left", "Right"
 492 };
 493
 494 static const struct soc_enum aif1adcl_src =
 495         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 496
 497 static const struct soc_enum aif1adcr_src =
 498         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 499
 500 static const struct soc_enum aif2adcl_src =
 501         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 502
 503 static const struct soc_enum aif2adcr_src =
 504         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 505
 506 static const struct soc_enum aif1dacl_src =
 507         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 508
 509 static const struct soc_enum aif1dacr_src =
 510         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 511
 512 static const struct soc_enum aif2dacl_src =
 513         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 514
 515 static const struct soc_enum aif2dacr_src =
 516         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 517
 518 static const char *osr_text[] = {
 519         "Low Power", "High Performance",
 520 };
 521
 522 static const struct soc_enum dac_osr =
 523         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
 524
 525 static const struct soc_enum adc_osr =
 526         SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
 527
 528 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 529 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 530                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 531                  1, 119, 0, digital_tlv),
 532 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 533                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 534                  1, 119, 0, digital_tlv),
 535 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 536                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 537                  1, 119, 0, digital_tlv),
 538
 539 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 540 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 541 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
 542 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
 543
 544 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 545 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 546 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
 547 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
 548
 549 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 550                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 551 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 552                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 553 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 554                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 555
 556 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 557 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 558
 559 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 560 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 561 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 562
 563 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 564 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 565 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 566
 567 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 568 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 569 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 570
 571 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 572 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 573 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 574
 575 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 576                5, 12, 0, st_tlv),
 577 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 578                0, 12, 0, st_tlv),
 579 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 580                5, 12, 0, st_tlv),
 581 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 582                0, 12, 0, st_tlv),
 583 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 584 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 585
 586 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
 587 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
 588
 589 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
 590 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
 591
 592 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
 593 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
 594
 595 SOC_ENUM("ADC OSR", adc_osr),
 596 SOC_ENUM("DAC OSR", dac_osr),
 597
 598 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 599                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 600 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 601              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 602
 603 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 604                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 605 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 606              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 607
 608 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 609                6, 1, 1, wm_hubs_spkmix_tlv),
 610 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 611                2, 1, 1, wm_hubs_spkmix_tlv),
 612
 613 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 614                6, 1, 1, wm_hubs_spkmix_tlv),
 615 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 616                2, 1, 1, wm_hubs_spkmix_tlv),
 617
 618 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 619                10, 15, 0, wm8994_3d_tlv),
 620 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
 621            8, 1, 0),
 622 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 623                10, 15, 0, wm8994_3d_tlv),
 624 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 625            8, 1, 0),
 626 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
 627                10, 15, 0, wm8994_3d_tlv),
 628 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
 629            8, 1, 0),
 630 };
 631
 632 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 633 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 634                eq_tlv),
 635 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 636                eq_tlv),
 637 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 638                eq_tlv),
 639 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 640                eq_tlv),
 641 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 642                eq_tlv),
 643
 644 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 645                eq_tlv),
 646 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 647                eq_tlv),
 648 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 649                eq_tlv),
 650 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 651                eq_tlv),
 652 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 653                eq_tlv),
 654
 655 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 656                eq_tlv),
 657 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 658                eq_tlv),
 659 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 660                eq_tlv),
 661 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 662                eq_tlv),
 663 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 664                eq_tlv),
 665 };
 666
 667 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 668 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 669 };
 670
 671 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 672                          struct snd_kcontrol *kcontrol, int event)
 673 {
 674         struct snd_soc_codec *codec = w->codec;
 675
 676         switch (event) {
 677         case SND_SOC_DAPM_PRE_PMU:
 678                 return configure_clock(codec);
 679
 680         case SND_SOC_DAPM_POST_PMD:
 681                 configure_clock(codec);
 682                 break;
 683         }
 684
 685         return 0;
 686 }
 687
 688 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 689 {
 690         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 691         int enable = 1;
 692         int source = 0;  /* GCC flow analysis can't track enable */
 693         int reg, reg_r;
 694
 695         /* Only support direct DAC->headphone paths */
 696         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 697         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 698                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 699                 enable = 0;
 700         }
 701
 702         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 703         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 704                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 705                 enable = 0;
 706         }
 707
 708         /* We also need the same setting for L/R and only one path */
 709         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 710         switch (reg) {
 711         case WM8994_AIF2DACL_TO_DAC1L:
 712                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 713                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 714                 break;
 715         case WM8994_AIF1DAC2L_TO_DAC1L:
 716                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 717                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 718                 break;
 719         case WM8994_AIF1DAC1L_TO_DAC1L:
 720                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 721                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 722                 break;
 723         default:
 724                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 725                 enable = 0;
 726                 break;
 727         }
 728
 729         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 730         if (reg_r != reg) {
 731                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 732                 enable = 0;
 733         }
 734
 735         if (enable) {
 736                 dev_dbg(codec->dev, "Class W enabled\n");
 737                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 738                                     WM8994_CP_DYN_PWR |
 739                                     WM8994_CP_DYN_SRC_SEL_MASK,
 740                                     source | WM8994_CP_DYN_PWR);
 741                 wm8994->hubs.class_w = true;
 742
 743         } else {
 744                 dev_dbg(codec->dev, "Class W disabled\n");
 745                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 746                                     WM8994_CP_DYN_PWR, 0);
 747                 wm8994->hubs.class_w = false;
 748         }
 749 }
 750
 751 static int late_enable_ev(struct snd_soc_dapm_widget *w,
 752                           struct snd_kcontrol *kcontrol, int event)
 753 {
 754         struct snd_soc_codec *codec = w->codec;
 755         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 756
 757         switch (event) {
 758         case SND_SOC_DAPM_PRE_PMU:
 759                 if (wm8994->aif1clk_enable) {
 760                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 761                                             WM8994_AIF1CLK_ENA_MASK,
 762                                             WM8994_AIF1CLK_ENA);
 763                         wm8994->aif1clk_enable = 0;
 764                 }
 765                 if (wm8994->aif2clk_enable) {
 766                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 767                                             WM8994_AIF2CLK_ENA_MASK,
 768                                             WM8994_AIF2CLK_ENA);
 769                         wm8994->aif2clk_enable = 0;
 770                 }
 771                 break;
 772         }
 773
 774         /* We may also have postponed startup of DSP, handle that. */
 775         wm8958_aif_ev(w, kcontrol, event);
 776
 777         return 0;
 778 }
 779
 780 static int late_disable_ev(struct snd_soc_dapm_widget *w,
 781                            struct snd_kcontrol *kcontrol, int event)
 782 {
 783         struct snd_soc_codec *codec = w->codec;
 784         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 785
 786         switch (event) {
 787         case SND_SOC_DAPM_POST_PMD:
 788                 if (wm8994->aif1clk_disable) {
 789                         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
 790                                             WM8994_AIF1CLK_ENA_MASK, 0);
 791                         wm8994->aif1clk_disable = 0;
 792                 }
 793                 if (wm8994->aif2clk_disable) {
 794                         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
 795                                             WM8994_AIF2CLK_ENA_MASK, 0);
 796                         wm8994->aif2clk_disable = 0;
 797                 }
 798                 break;
 799         }
 800
 801         return 0;
 802 }
 803
 804 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
 805                       struct snd_kcontrol *kcontrol, int event)
 806 {
 807         struct snd_soc_codec *codec = w->codec;
 808         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 809
 810         switch (event) {
 811         case SND_SOC_DAPM_PRE_PMU:
 812                 wm8994->aif1clk_enable = 1;
 813                 break;
 814         case SND_SOC_DAPM_POST_PMD:
 815                 wm8994->aif1clk_disable = 1;
 816                 break;
 817         }
 818
 819         return 0;
 820 }
 821
 822 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
 823                       struct snd_kcontrol *kcontrol, int event)
 824 {
 825         struct snd_soc_codec *codec = w->codec;
 826         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 827
 828         switch (event) {
 829         case SND_SOC_DAPM_PRE_PMU:
 830                 wm8994->aif2clk_enable = 1;
 831                 break;
 832         case SND_SOC_DAPM_POST_PMD:
 833                 wm8994->aif2clk_disable = 1;
 834                 break;
 835         }
 836
 837         return 0;
 838 }
 839
 840 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
 841                       struct snd_kcontrol *kcontrol, int event)
 842 {
 843         late_enable_ev(w, kcontrol, event);
 844         return 0;
 845 }
 846
 847 static int micbias_ev(struct snd_soc_dapm_widget *w,
 848                       struct snd_kcontrol *kcontrol, int event)
 849 {
 850         late_enable_ev(w, kcontrol, event);
 851         return 0;
 852 }
 853
 854 static int dac_ev(struct snd_soc_dapm_widget *w,
 855                   struct snd_kcontrol *kcontrol, int event)
 856 {
 857         struct snd_soc_codec *codec = w->codec;
 858         unsigned int mask = 1 << w->shift;
 859
 860         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
 861                             mask, mask);
 862         return 0;
 863 }
 864
 865 static const char *hp_mux_text[] = {
 866         "Mixer",
 867         "DAC",
 868 };
 869
 870 #define WM8994_HP_ENUM(xname, xenum) \
 871 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 872         .info = snd_soc_info_enum_double, \
 873         .get = snd_soc_dapm_get_enum_double, \
 874         .put = wm8994_put_hp_enum, \
 875         .private_value = (unsigned long)&xenum }
 876
 877 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
 878                               struct snd_ctl_elem_value *ucontrol)
 879 {
 880         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
 881         struct snd_soc_dapm_widget *w = wlist->widgets[0];
 882         struct snd_soc_codec *codec = w->codec;
 883         int ret;
 884
 885         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
 886
 887         wm8994_update_class_w(codec);
 888
 889         return ret;
 890 }
 891
 892 static const struct soc_enum hpl_enum =
 893         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
 894
 895 static const struct snd_kcontrol_new hpl_mux =
 896         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
 897
 898 static const struct soc_enum hpr_enum =
 899         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
 900
 901 static const struct snd_kcontrol_new hpr_mux =
 902         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
 903
 904 static const char *adc_mux_text[] = {
 905         "ADC",
 906         "DMIC",
 907 };
 908
 909 static const struct soc_enum adc_enum =
 910         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
 911
 912 static const struct snd_kcontrol_new adcl_mux =
 913         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
 914
 915 static const struct snd_kcontrol_new adcr_mux =
 916         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
 917
 918 static const struct snd_kcontrol_new left_speaker_mixer[] = {
 919 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
 920 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
 921 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
 922 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
 923 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
 924 };
 925
 926 static const struct snd_kcontrol_new right_speaker_mixer[] = {
 927 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
 928 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
 929 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
 930 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
 931 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
 932 };
 933
 934 /* Debugging; dump chip status after DAPM transitions */
 935 static int post_ev(struct snd_soc_dapm_widget *w,
 936             struct snd_kcontrol *kcontrol, int event)
 937 {
 938         struct snd_soc_codec *codec = w->codec;
 939         dev_dbg(codec->dev, "SRC status: %x\n",
 940                 snd_soc_read(codec,
 941                              WM8994_RATE_STATUS));
 942         return 0;
 943 }
 944
 945 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
 946 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 947                 1, 1, 0),
 948 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
 949                 0, 1, 0),
 950 };
 951
 952 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
 953 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 954                 1, 1, 0),
 955 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
 956                 0, 1, 0),
 957 };
 958
 959 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
 960 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 961                 1, 1, 0),
 962 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
 963                 0, 1, 0),
 964 };
 965
 966 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
 967 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
 968                 1, 1, 0),
 969 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
 970                 0, 1, 0),
 971 };
 972
 973 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
 974 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 975                 5, 1, 0),
 976 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 977                 4, 1, 0),
 978 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 979                 2, 1, 0),
 980 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 981                 1, 1, 0),
 982 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
 983                 0, 1, 0),
 984 };
 985
 986 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
 987 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 988                 5, 1, 0),
 989 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 990                 4, 1, 0),
 991 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 992                 2, 1, 0),
 993 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 994                 1, 1, 0),
 995 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
 996                 0, 1, 0),
 997 };
 998
 999 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1000 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1001         .info = snd_soc_info_volsw, \
1002         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1003         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1004
1005 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1006                               struct snd_ctl_elem_value *ucontrol)
1007 {
1008         struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1009         struct snd_soc_dapm_widget *w = wlist->widgets[0];
1010         struct snd_soc_codec *codec = w->codec;
1011         int ret;
1012
1013         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1014
1015         wm8994_update_class_w(codec);
1016
1017         return ret;
1018 }
1019
1020 static const struct snd_kcontrol_new dac1l_mix[] = {
1021 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1022                       5, 1, 0),
1023 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1024                       4, 1, 0),
1025 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1026                       2, 1, 0),
1027 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1028                       1, 1, 0),
1029 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1030                       0, 1, 0),
1031 };
1032
1033 static const struct snd_kcontrol_new dac1r_mix[] = {
1034 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1035                       5, 1, 0),
1036 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1037                       4, 1, 0),
1038 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1039                       2, 1, 0),
1040 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1041                       1, 1, 0),
1042 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1043                       0, 1, 0),
1044 };
1045
1046 static const char *sidetone_text[] = {
1047         "ADC/DMIC1", "DMIC2",
1048 };
1049
1050 static const struct soc_enum sidetone1_enum =
1051         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1052
1053 static const struct snd_kcontrol_new sidetone1_mux =
1054         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1055
1056 static const struct soc_enum sidetone2_enum =
1057         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1058
1059 static const struct snd_kcontrol_new sidetone2_mux =
1060         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1061
1062 static const char *aif1dac_text[] = {
1063         "AIF1DACDAT", "AIF3DACDAT",
1064 };
1065
1066 static const struct soc_enum aif1dac_enum =
1067         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1068
1069 static const struct snd_kcontrol_new aif1dac_mux =
1070         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1071
1072 static const char *aif2dac_text[] = {
1073         "AIF2DACDAT", "AIF3DACDAT",
1074 };
1075
1076 static const struct soc_enum aif2dac_enum =
1077         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1078
1079 static const struct snd_kcontrol_new aif2dac_mux =
1080         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1081
1082 static const char *aif2adc_text[] = {
1083         "AIF2ADCDAT", "AIF3DACDAT",
1084 };
1085
1086 static const struct soc_enum aif2adc_enum =
1087         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1088
1089 static const struct snd_kcontrol_new aif2adc_mux =
1090         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1091
1092 static const char *aif3adc_text[] = {
1093         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1094 };
1095
1096 static const struct soc_enum wm8994_aif3adc_enum =
1097         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1098
1099 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1100         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1101
1102 static const struct soc_enum wm8958_aif3adc_enum =
1103         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1104
1105 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1106         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1107
1108 static const char *mono_pcm_out_text[] = {
1109         "None", "AIF2ADCL", "AIF2ADCR",
1110 };
1111
1112 static const struct soc_enum mono_pcm_out_enum =
1113         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1114
1115 static const struct snd_kcontrol_new mono_pcm_out_mux =
1116         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1117
1118 static const char *aif2dac_src_text[] = {
1119         "AIF2", "AIF3",
1120 };
1121
1122 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1123 static const struct soc_enum aif2dacl_src_enum =
1124         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1125
1126 static const struct snd_kcontrol_new aif2dacl_src_mux =
1127         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1128
1129 static const struct soc_enum aif2dacr_src_enum =
1130         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1131
1132 static const struct snd_kcontrol_new aif2dacr_src_mux =
1133         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1134
1135 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1136 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1137         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1138 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1139         SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1140
1141 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1142         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1143 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1144         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1145 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1146         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1147 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1148         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1149 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1150         late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1151
1152 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1153                      left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1154                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1155 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1156                      right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1157                      late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1158 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1159                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1160 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1161                    late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1162
1163 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1164 };
1165
1166 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1167 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1168 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1169 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1170 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1171                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1172 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1173                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1174 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1175 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1176 };
1177
1178 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1179 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1180         dac_ev, SND_SOC_DAPM_PRE_PMU),
1181 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1182         dac_ev, SND_SOC_DAPM_PRE_PMU),
1183 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1184         dac_ev, SND_SOC_DAPM_PRE_PMU),
1185 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1186         dac_ev, SND_SOC_DAPM_PRE_PMU),
1187 };
1188
1189 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1190 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1191 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1192 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1193 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1194 };
1195
1196 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1197 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1198                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1199 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1200                    adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1201 };
1202
1203 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1204 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1205 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1206 };
1207
1208 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1209 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1210 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1211 SND_SOC_DAPM_INPUT("Clock"),
1212
1213 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8994_MICBIAS, 2, 0),
1214 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1215                       SND_SOC_DAPM_PRE_PMU),
1216
1217 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1218                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1219
1220 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1221 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1222 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1223
1224 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1225                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1226 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1227                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1228 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1229                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1230                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1231 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1232                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1233                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1234
1235 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1236                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1237 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1238                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1239 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1240                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1241                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1242 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1243                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1244                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1245
1246 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1247                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1248 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1249                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1250
1251 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1252                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1253 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1254                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1255
1256 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1257                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1258 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1259                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1260
1261 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1262 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1263
1264 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1265                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1266 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1267                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1268
1269 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1270                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1271 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1272                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1273 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1274                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1275                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1276 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1277                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1278                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1279
1280 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1281 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1282 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1283 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1284
1285 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1286 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1287 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1288
1289 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1290 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1291
1292 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1293
1294 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1295 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1296 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1297 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1298
1299 /* Power is done with the muxes since the ADC power also controls the
1300  * downsampling chain, the chip will automatically manage the analogue
1301  * specific portions.
1302  */
1303 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1304 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1305
1306 SND_SOC_DAPM_POST("Debug log", post_ev),
1307 };
1308
1309 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1310 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1311 };
1312
1313 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1314 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1315 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1316 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1317 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1318 };
1319
1320 static const struct snd_soc_dapm_route intercon[] = {
1321         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1322         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1323
1324         { "DSP1CLK", NULL, "CLK_SYS" },
1325         { "DSP2CLK", NULL, "CLK_SYS" },
1326         { "DSPINTCLK", NULL, "CLK_SYS" },
1327
1328         { "AIF1ADC1L", NULL, "AIF1CLK" },
1329         { "AIF1ADC1L", NULL, "DSP1CLK" },
1330         { "AIF1ADC1R", NULL, "AIF1CLK" },
1331         { "AIF1ADC1R", NULL, "DSP1CLK" },
1332         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1333
1334         { "AIF1DAC1L", NULL, "AIF1CLK" },
1335         { "AIF1DAC1L", NULL, "DSP1CLK" },
1336         { "AIF1DAC1R", NULL, "AIF1CLK" },
1337         { "AIF1DAC1R", NULL, "DSP1CLK" },
1338         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1339
1340         { "AIF1ADC2L", NULL, "AIF1CLK" },
1341         { "AIF1ADC2L", NULL, "DSP1CLK" },
1342         { "AIF1ADC2R", NULL, "AIF1CLK" },
1343         { "AIF1ADC2R", NULL, "DSP1CLK" },
1344         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1345
1346         { "AIF1DAC2L", NULL, "AIF1CLK" },
1347         { "AIF1DAC2L", NULL, "DSP1CLK" },
1348         { "AIF1DAC2R", NULL, "AIF1CLK" },
1349         { "AIF1DAC2R", NULL, "DSP1CLK" },
1350         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1351
1352         { "AIF2ADCL", NULL, "AIF2CLK" },
1353         { "AIF2ADCL", NULL, "DSP2CLK" },
1354         { "AIF2ADCR", NULL, "AIF2CLK" },
1355         { "AIF2ADCR", NULL, "DSP2CLK" },
1356         { "AIF2ADCR", NULL, "DSPINTCLK" },
1357
1358         { "AIF2DACL", NULL, "AIF2CLK" },
1359         { "AIF2DACL", NULL, "DSP2CLK" },
1360         { "AIF2DACR", NULL, "AIF2CLK" },
1361         { "AIF2DACR", NULL, "DSP2CLK" },
1362         { "AIF2DACR", NULL, "DSPINTCLK" },
1363
1364         { "DMIC1L", NULL, "DMIC1DAT" },
1365         { "DMIC1L", NULL, "CLK_SYS" },
1366         { "DMIC1R", NULL, "DMIC1DAT" },
1367         { "DMIC1R", NULL, "CLK_SYS" },
1368         { "DMIC2L", NULL, "DMIC2DAT" },
1369         { "DMIC2L", NULL, "CLK_SYS" },
1370         { "DMIC2R", NULL, "DMIC2DAT" },
1371         { "DMIC2R", NULL, "CLK_SYS" },
1372
1373         { "ADCL", NULL, "AIF1CLK" },
1374         { "ADCL", NULL, "DSP1CLK" },
1375         { "ADCL", NULL, "DSPINTCLK" },
1376
1377         { "ADCR", NULL, "AIF1CLK" },
1378         { "ADCR", NULL, "DSP1CLK" },
1379         { "ADCR", NULL, "DSPINTCLK" },
1380
1381         { "ADCL Mux", "ADC", "ADCL" },
1382         { "ADCL Mux", "DMIC", "DMIC1L" },
1383         { "ADCR Mux", "ADC", "ADCR" },
1384         { "ADCR Mux", "DMIC", "DMIC1R" },
1385
1386         { "DAC1L", NULL, "AIF1CLK" },
1387         { "DAC1L", NULL, "DSP1CLK" },
1388         { "DAC1L", NULL, "DSPINTCLK" },
1389
1390         { "DAC1R", NULL, "AIF1CLK" },
1391         { "DAC1R", NULL, "DSP1CLK" },
1392         { "DAC1R", NULL, "DSPINTCLK" },
1393
1394         { "DAC2L", NULL, "AIF2CLK" },
1395         { "DAC2L", NULL, "DSP2CLK" },
1396         { "DAC2L", NULL, "DSPINTCLK" },
1397
1398         { "DAC2R", NULL, "AIF2DACR" },
1399         { "DAC2R", NULL, "AIF2CLK" },
1400         { "DAC2R", NULL, "DSP2CLK" },
1401         { "DAC2R", NULL, "DSPINTCLK" },
1402
1403         { "TOCLK", NULL, "CLK_SYS" },
1404
1405         /* AIF1 outputs */
1406         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1407         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1408         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1409
1410         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1411         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1412         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1413
1414         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1415         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1416         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1417
1418         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1419         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1420         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1421
1422         /* Pin level routing for AIF3 */
1423         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1424         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1425         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1426         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1427
1428         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1429         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1430         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1431         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1432         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1433         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1434         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1435
1436         /* DAC1 inputs */
1437         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1438         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1439         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1440         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1441         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1442
1443         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1444         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1445         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1446         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1447         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1448
1449         /* DAC2/AIF2 outputs  */
1450         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1451         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1452         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1453         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1454         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1455         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1456
1457         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1458         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1459         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1460         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1461         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1462         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1463
1464         { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1465         { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1466         { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1467         { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1468
1469         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1470
1471         /* AIF3 output */
1472         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1473         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1474         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1475         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1476         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1477         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1478         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1479         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1480
1481         /* Sidetone */
1482         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1483         { "Left Sidetone", "DMIC2", "DMIC2L" },
1484         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1485         { "Right Sidetone", "DMIC2", "DMIC2R" },
1486
1487         /* Output stages */
1488         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1489         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1490
1491         { "SPKL", "DAC1 Switch", "DAC1L" },
1492         { "SPKL", "DAC2 Switch", "DAC2L" },
1493
1494         { "SPKR", "DAC1 Switch", "DAC1R" },
1495         { "SPKR", "DAC2 Switch", "DAC2R" },
1496
1497         { "Left Headphone Mux", "DAC", "DAC1L" },
1498         { "Right Headphone Mux", "DAC", "DAC1R" },
1499 };
1500
1501 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1502         { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1503         { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1504         { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1505         { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1506         { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1507         { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1508         { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1509         { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1510 };
1511
1512 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1513         { "DAC1L", NULL, "DAC1L Mixer" },
1514         { "DAC1R", NULL, "DAC1R Mixer" },
1515         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1516         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1517 };
1518
1519 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1520         { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1521         { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1522         { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1523         { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1524         { "MICBIAS", NULL, "CLK_SYS" },
1525         { "MICBIAS", NULL, "MICBIAS Supply" },
1526 };
1527
1528 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1529         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1530         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1531 };
1532
1533 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1534         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1535         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1536
1537         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1538         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1539         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1540         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1541
1542         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1543         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1544
1545         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1546 };
1547
1548 /* The size in bits of the FLL divide multiplied by 10
1549  * to allow rounding later */
1550 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1551
1552 struct fll_div {
1553         u16 outdiv;
1554         u16 n;
1555         u16 k;
1556         u16 clk_ref_div;
1557         u16 fll_fratio;
1558 };
1559
1560 static int wm8994_get_fll_config(struct fll_div *fll,
1561                                  int freq_in, int freq_out)
1562 {
1563         u64 Kpart;
1564         unsigned int K, Ndiv, Nmod;
1565
1566         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1567
1568         /* Scale the input frequency down to <= 13.5MHz */
1569         fll->clk_ref_div = 0;
1570         while (freq_in > 13500000) {
1571                 fll->clk_ref_div++;
1572                 freq_in /= 2;
1573
1574                 if (fll->clk_ref_div > 3)
1575                         return -EINVAL;
1576         }
1577         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1578
1579         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1580         fll->outdiv = 3;
1581         while (freq_out * (fll->outdiv + 1) < 90000000) {
1582                 fll->outdiv++;
1583                 if (fll->outdiv > 63)
1584                         return -EINVAL;
1585         }
1586         freq_out *= fll->outdiv + 1;
1587         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1588
1589         if (freq_in > 1000000) {
1590                 fll->fll_fratio = 0;
1591         } else if (freq_in > 256000) {
1592                 fll->fll_fratio = 1;
1593                 freq_in *= 2;
1594         } else if (freq_in > 128000) {
1595                 fll->fll_fratio = 2;
1596                 freq_in *= 4;
1597         } else if (freq_in > 64000) {
1598                 fll->fll_fratio = 3;
1599                 freq_in *= 8;
1600         } else {
1601                 fll->fll_fratio = 4;
1602                 freq_in *= 16;
1603         }
1604         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1605
1606         /* Now, calculate N.K */
1607         Ndiv = freq_out / freq_in;
1608
1609         fll->n = Ndiv;
1610         Nmod = freq_out % freq_in;
1611         pr_debug("Nmod=%d\n", Nmod);
1612
1613         /* Calculate fractional part - scale up so we can round. */
1614         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1615
1616         do_div(Kpart, freq_in);
1617
1618         K = Kpart & 0xFFFFFFFF;
1619
1620         if ((K % 10) >= 5)
1621                 K += 5;
1622
1623         /* Move down to proper range now rounding is done */
1624         fll->k = K / 10;
1625
1626         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1627
1628         return 0;
1629 }
1630
1631 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1632                           unsigned int freq_in, unsigned int freq_out)
1633 {
1634         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1635         int reg_offset, ret;
1636         struct fll_div fll;
1637         u16 reg, aif1, aif2;
1638
1639         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1640                 & WM8994_AIF1CLK_ENA;
1641
1642         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1643                 & WM8994_AIF2CLK_ENA;
1644
1645         switch (id) {
1646         case WM8994_FLL1:
1647                 reg_offset = 0;
1648                 id = 0;
1649                 break;
1650         case WM8994_FLL2:
1651                 reg_offset = 0x20;
1652                 id = 1;
1653                 break;
1654         default:
1655                 return -EINVAL;
1656         }
1657
1658         switch (src) {
1659         case 0:
1660                 /* Allow no source specification when stopping */
1661                 if (freq_out)
1662                         return -EINVAL;
1663                 src = wm8994->fll[id].src;
1664                 break;
1665         case WM8994_FLL_SRC_MCLK1:
1666         case WM8994_FLL_SRC_MCLK2:
1667         case WM8994_FLL_SRC_LRCLK:
1668         case WM8994_FLL_SRC_BCLK:
1669                 break;
1670         default:
1671                 return -EINVAL;
1672         }
1673
1674         /* Are we changing anything? */
1675         if (wm8994->fll[id].src == src &&
1676             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1677                 return 0;
1678
1679         /* If we're stopping the FLL redo the old config - no
1680          * registers will actually be written but we avoid GCC flow
1681          * analysis bugs spewing warnings.
1682          */
1683         if (freq_out)
1684                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1685         else
1686                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1687                                             wm8994->fll[id].out);
1688         if (ret < 0)
1689                 return ret;
1690
1691         /* Gate the AIF clocks while we reclock */
1692         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1693                             WM8994_AIF1CLK_ENA, 0);
1694         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1695                             WM8994_AIF2CLK_ENA, 0);
1696
1697         /* We always need to disable the FLL while reconfiguring */
1698         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1699                             WM8994_FLL1_ENA, 0);
1700
1701         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1702                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1703         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1704                             WM8994_FLL1_OUTDIV_MASK |
1705                             WM8994_FLL1_FRATIO_MASK, reg);
1706
1707         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1708
1709         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1710                             WM8994_FLL1_N_MASK,
1711                                     fll.n << WM8994_FLL1_N_SHIFT);
1712
1713         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1714                             WM8994_FLL1_REFCLK_DIV_MASK |
1715                             WM8994_FLL1_REFCLK_SRC_MASK,
1716                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1717                             (src - 1));
1718
1719         /* Enable (with fractional mode if required) */
1720         if (freq_out) {
1721                 if (fll.k)
1722                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1723                 else
1724                         reg = WM8994_FLL1_ENA;
1725                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1726                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1727                                     reg);
1728
1729                 msleep(5);
1730         }
1731
1732         wm8994->fll[id].in = freq_in;
1733         wm8994->fll[id].out = freq_out;
1734         wm8994->fll[id].src = src;
1735
1736         /* Enable any gated AIF clocks */
1737         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1738                             WM8994_AIF1CLK_ENA, aif1);
1739         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1740                             WM8994_AIF2CLK_ENA, aif2);
1741
1742         configure_clock(codec);
1743
1744         return 0;
1745 }
1746
1747
1748 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1749
1750 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1751                           unsigned int freq_in, unsigned int freq_out)
1752 {
1753         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1754 }
1755
1756 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1757                 int clk_id, unsigned int freq, int dir)
1758 {
1759         struct snd_soc_codec *codec = dai->codec;
1760         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1761         int i;
1762
1763         switch (dai->id) {
1764         case 1:
1765         case 2:
1766                 break;
1767
1768         default:
1769                 /* AIF3 shares clocking with AIF1/2 */
1770                 return -EINVAL;
1771         }
1772
1773         switch (clk_id) {
1774         case WM8994_SYSCLK_MCLK1:
1775                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1776                 wm8994->mclk[0] = freq;
1777                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1778                         dai->id, freq);
1779                 break;
1780
1781         case WM8994_SYSCLK_MCLK2:
1782                 /* TODO: Set GPIO AF */
1783                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1784                 wm8994->mclk[1] = freq;
1785                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1786                         dai->id, freq);
1787                 break;
1788
1789         case WM8994_SYSCLK_FLL1:
1790                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1791                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1792                 break;
1793
1794         case WM8994_SYSCLK_FLL2:
1795                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1796                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1797                 break;
1798
1799         case WM8994_SYSCLK_OPCLK:
1800                 /* Special case - a division (times 10) is given and
1801                  * no effect on main clocking.
1802                  */
1803                 if (freq) {
1804                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1805                                 if (opclk_divs[i] == freq)
1806                                         break;
1807                         if (i == ARRAY_SIZE(opclk_divs))
1808                                 return -EINVAL;
1809                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1810                                             WM8994_OPCLK_DIV_MASK, i);
1811                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1812                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1813                 } else {
1814                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1815                                             WM8994_OPCLK_ENA, 0);
1816                 }
1817
1818         default:
1819                 return -EINVAL;
1820         }
1821
1822         configure_clock(codec);
1823
1824         return 0;
1825 }
1826
1827 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1828                                  enum snd_soc_bias_level level)
1829 {
1830         struct wm8994 *control = codec->control_data;
1831         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1832
1833         switch (level) {
1834         case SND_SOC_BIAS_ON:
1835                 break;
1836
1837         case SND_SOC_BIAS_PREPARE:
1838                 /* VMID=2x40k */
1839                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1840                                     WM8994_VMID_SEL_MASK, 0x2);
1841                 break;
1842
1843         case SND_SOC_BIAS_STANDBY:
1844                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1845                         pm_runtime_get_sync(codec->dev);
1846
1847                         switch (control->type) {
1848                         case WM8994:
1849                                 if (wm8994->revision < 4) {
1850                                         /* Tweak DC servo and DSP
1851                                          * configuration for improved
1852                                          * performance. */
1853                                         snd_soc_write(codec, 0x102, 0x3);
1854                                         snd_soc_write(codec, 0x56, 0x3);
1855                                         snd_soc_write(codec, 0x817, 0);
1856                                         snd_soc_write(codec, 0x102, 0);
1857                                 }
1858                                 break;
1859
1860                         case WM8958:
1861                                 if (wm8994->revision == 0) {
1862                                         /* Optimise performance for rev A */
1863                                         snd_soc_write(codec, 0x102, 0x3);
1864                                         snd_soc_write(codec, 0xcb, 0x81);
1865                                         snd_soc_write(codec, 0x817, 0);
1866                                         snd_soc_write(codec, 0x102, 0);
1867
1868                                         snd_soc_update_bits(codec,
1869                                                             WM8958_CHARGE_PUMP_2,
1870                                                             WM8958_CP_DISCH,
1871                                                             WM8958_CP_DISCH);
1872                                 }
1873                                 break;
1874                         }
1875
1876                         /* Discharge LINEOUT1 & 2 */
1877                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1878                                             WM8994_LINEOUT1_DISCH |
1879                                             WM8994_LINEOUT2_DISCH,
1880                                             WM8994_LINEOUT1_DISCH |
1881                                             WM8994_LINEOUT2_DISCH);
1882
1883                         /* Startup bias, VMID ramp & buffer */
1884                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1885                                             WM8994_STARTUP_BIAS_ENA |
1886                                             WM8994_VMID_BUF_ENA |
1887                                             WM8994_VMID_RAMP_MASK,
1888                                             WM8994_STARTUP_BIAS_ENA |
1889                                             WM8994_VMID_BUF_ENA |
1890                                             (0x11 << WM8994_VMID_RAMP_SHIFT));
1891
1892                         /* Main bias enable, VMID=2x40k */
1893                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1894                                             WM8994_BIAS_ENA |
1895                                             WM8994_VMID_SEL_MASK,
1896                                             WM8994_BIAS_ENA | 0x2);
1897
1898                         msleep(20);
1899                 }
1900
1901                 /* VMID=2x500k */
1902                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1903                                     WM8994_VMID_SEL_MASK, 0x4);
1904
1905                 break;
1906
1907         case SND_SOC_BIAS_OFF:
1908                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1909                         /* Switch over to startup biases */
1910                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1911                                             WM8994_BIAS_SRC |
1912                                             WM8994_STARTUP_BIAS_ENA |
1913                                             WM8994_VMID_BUF_ENA |
1914                                             WM8994_VMID_RAMP_MASK,
1915                                             WM8994_BIAS_SRC |
1916                                             WM8994_STARTUP_BIAS_ENA |
1917                                             WM8994_VMID_BUF_ENA |
1918                                             (1 << WM8994_VMID_RAMP_SHIFT));
1919
1920                         /* Disable main biases */
1921                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1922                                             WM8994_BIAS_ENA |
1923                                             WM8994_VMID_SEL_MASK, 0);
1924
1925                         /* Discharge line */
1926                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1927                                             WM8994_LINEOUT1_DISCH |
1928                                             WM8994_LINEOUT2_DISCH,
1929                                             WM8994_LINEOUT1_DISCH |
1930                                             WM8994_LINEOUT2_DISCH);
1931
1932                         msleep(5);
1933
1934                         /* Switch off startup biases */
1935                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1936                                             WM8994_BIAS_SRC |
1937                                             WM8994_STARTUP_BIAS_ENA |
1938                                             WM8994_VMID_BUF_ENA |
1939                                             WM8994_VMID_RAMP_MASK, 0);
1940
1941                         wm8994->cur_fw = NULL;
1942
1943                         pm_runtime_put(codec->dev);
1944                 }
1945                 break;
1946         }
1947         codec->dapm.bias_level = level;
1948         return 0;
1949 }
1950
1951 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1952 {
1953         struct snd_soc_codec *codec = dai->codec;
1954         struct wm8994 *control = codec->control_data;
1955         int ms_reg;
1956         int aif1_reg;
1957         int ms = 0;
1958         int aif1 = 0;
1959
1960         switch (dai->id) {
1961         case 1:
1962                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1963                 aif1_reg = WM8994_AIF1_CONTROL_1;
1964                 break;
1965         case 2:
1966                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1967                 aif1_reg = WM8994_AIF2_CONTROL_1;
1968                 break;
1969         default:
1970                 return -EINVAL;
1971         }
1972
1973         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1974         case SND_SOC_DAIFMT_CBS_CFS:
1975                 break;
1976         case SND_SOC_DAIFMT_CBM_CFM:
1977                 ms = WM8994_AIF1_MSTR;
1978                 break;
1979         default:
1980                 return -EINVAL;
1981         }
1982
1983         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1984         case SND_SOC_DAIFMT_DSP_B:
1985                 aif1 |= WM8994_AIF1_LRCLK_INV;
1986         case SND_SOC_DAIFMT_DSP_A:
1987                 aif1 |= 0x18;
1988                 break;
1989         case SND_SOC_DAIFMT_I2S:
1990                 aif1 |= 0x10;
1991                 break;
1992         case SND_SOC_DAIFMT_RIGHT_J:
1993                 break;
1994         case SND_SOC_DAIFMT_LEFT_J:
1995                 aif1 |= 0x8;
1996                 break;
1997         default:
1998                 return -EINVAL;
1999         }
2000
2001         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2002         case SND_SOC_DAIFMT_DSP_A:
2003         case SND_SOC_DAIFMT_DSP_B:
2004                 /* frame inversion not valid for DSP modes */
2005                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2006                 case SND_SOC_DAIFMT_NB_NF:
2007                         break;
2008                 case SND_SOC_DAIFMT_IB_NF:
2009                         aif1 |= WM8994_AIF1_BCLK_INV;
2010                         break;
2011                 default:
2012                         return -EINVAL;
2013                 }
2014                 break;
2015
2016         case SND_SOC_DAIFMT_I2S:
2017         case SND_SOC_DAIFMT_RIGHT_J:
2018         case SND_SOC_DAIFMT_LEFT_J:
2019                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2020                 case SND_SOC_DAIFMT_NB_NF:
2021                         break;
2022                 case SND_SOC_DAIFMT_IB_IF:
2023                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2024                         break;
2025                 case SND_SOC_DAIFMT_IB_NF:
2026                         aif1 |= WM8994_AIF1_BCLK_INV;
2027                         break;
2028                 case SND_SOC_DAIFMT_NB_IF:
2029                         aif1 |= WM8994_AIF1_LRCLK_INV;
2030                         break;
2031                 default:
2032                         return -EINVAL;
2033                 }
2034                 break;
2035         default:
2036                 return -EINVAL;
2037         }
2038
2039         /* The AIF2 format configuration needs to be mirrored to AIF3
2040          * on WM8958 if it's in use so just do it all the time. */
2041         if (control->type == WM8958 && dai->id == 2)
2042                 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2043                                     WM8994_AIF1_LRCLK_INV |
2044                                     WM8958_AIF3_FMT_MASK, aif1);
2045
2046         snd_soc_update_bits(codec, aif1_reg,
2047                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2048                             WM8994_AIF1_FMT_MASK,
2049                             aif1);
2050         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2051                             ms);
2052
2053         return 0;
2054 }
2055
2056 static struct {
2057         int val, rate;
2058 } srs[] = {
2059         { 0,   8000 },
2060         { 1,  11025 },
2061         { 2,  12000 },
2062         { 3,  16000 },
2063         { 4,  22050 },
2064         { 5,  24000 },
2065         { 6,  32000 },
2066         { 7,  44100 },
2067         { 8,  48000 },
2068         { 9,  88200 },
2069         { 10, 96000 },
2070 };
2071
2072 static int fs_ratios[] = {
2073         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2074 };
2075
2076 static int bclk_divs[] = {
2077         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2078         640, 880, 960, 1280, 1760, 1920
2079 };
2080
2081 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2082                             struct snd_pcm_hw_params *params,
2083                             struct snd_soc_dai *dai)
2084 {
2085         struct snd_soc_codec *codec = dai->codec;
2086         struct wm8994 *control = codec->control_data;
2087         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2088         int aif1_reg;
2089         int aif2_reg;
2090         int bclk_reg;
2091         int lrclk_reg;
2092         int rate_reg;
2093         int aif1 = 0;
2094         int aif2 = 0;
2095         int bclk = 0;
2096         int lrclk = 0;
2097         int rate_val = 0;
2098         int id = dai->id - 1;
2099
2100         int i, cur_val, best_val, bclk_rate, best;
2101
2102         switch (dai->id) {
2103         case 1:
2104                 aif1_reg = WM8994_AIF1_CONTROL_1;
2105                 aif2_reg = WM8994_AIF1_CONTROL_2;
2106                 bclk_reg = WM8994_AIF1_BCLK;
2107                 rate_reg = WM8994_AIF1_RATE;
2108                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2109                     wm8994->lrclk_shared[0]) {
2110                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2111                 } else {
2112                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2113                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2114                 }
2115                 break;
2116         case 2:
2117                 aif1_reg = WM8994_AIF2_CONTROL_1;
2118                 aif2_reg = WM8994_AIF2_CONTROL_2;
2119                 bclk_reg = WM8994_AIF2_BCLK;
2120                 rate_reg = WM8994_AIF2_RATE;
2121                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2122                     wm8994->lrclk_shared[1]) {
2123                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2124                 } else {
2125                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2126                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2127                 }
2128                 break;
2129         case 3:
2130                 switch (control->type) {
2131                 case WM8958:
2132                         aif1_reg = WM8958_AIF3_CONTROL_1;
2133                         break;
2134                 default:
2135                         return 0;
2136                 }
2137         default:
2138                 return -EINVAL;
2139         }
2140
2141         bclk_rate = params_rate(params) * 2;
2142         switch (params_format(params)) {
2143         case SNDRV_PCM_FORMAT_S16_LE:
2144                 bclk_rate *= 16;
2145                 break;
2146         case SNDRV_PCM_FORMAT_S20_3LE:
2147                 bclk_rate *= 20;
2148                 aif1 |= 0x20;
2149                 break;
2150         case SNDRV_PCM_FORMAT_S24_LE:
2151                 bclk_rate *= 24;
2152                 aif1 |= 0x40;
2153                 break;
2154         case SNDRV_PCM_FORMAT_S32_LE:
2155                 bclk_rate *= 32;
2156                 aif1 |= 0x60;
2157                 break;
2158         default:
2159                 return -EINVAL;
2160         }
2161
2162         /* Try to find an appropriate sample rate; look for an exact match. */
2163         for (i = 0; i < ARRAY_SIZE(srs); i++)
2164                 if (srs[i].rate == params_rate(params))
2165                         break;
2166         if (i == ARRAY_SIZE(srs))
2167                 return -EINVAL;
2168         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2169
2170         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2171         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2172                 dai->id, wm8994->aifclk[id], bclk_rate);
2173
2174         if (params_channels(params) == 1 &&
2175             (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2176                 aif2 |= WM8994_AIF1_MONO;
2177
2178         if (wm8994->aifclk[id] == 0) {
2179                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2180                 return -EINVAL;
2181         }
2182
2183         /* AIFCLK/fs ratio; look for a close match in either direction */
2184         best = 0;
2185         best_val = abs((fs_ratios[0] * params_rate(params))
2186                        - wm8994->aifclk[id]);
2187         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2188                 cur_val = abs((fs_ratios[i] * params_rate(params))
2189                               - wm8994->aifclk[id]);
2190                 if (cur_val >= best_val)
2191                         continue;
2192                 best = i;
2193                 best_val = cur_val;
2194         }
2195         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2196                 dai->id, fs_ratios[best]);
2197         rate_val |= best;
2198
2199         /* We may not get quite the right frequency if using
2200          * approximate clocks so look for the closest match that is
2201          * higher than the target (we need to ensure that there enough
2202          * BCLKs to clock out the samples).
2203          */
2204         best = 0;
2205         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2206                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2207                 if (cur_val < 0) /* BCLK table is sorted */
2208                         break;
2209                 best = i;
2210         }
2211         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2212         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2213                 bclk_divs[best], bclk_rate);
2214         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2215
2216         lrclk = bclk_rate / params_rate(params);
2217         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2218                 lrclk, bclk_rate / lrclk);
2219
2220         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2221         snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2222         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2223         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2224                             lrclk);
2225         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2226                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2227
2228         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2229                 switch (dai->id) {
2230                 case 1:
2231                         wm8994->dac_rates[0] = params_rate(params);
2232                         wm8994_set_retune_mobile(codec, 0);
2233                         wm8994_set_retune_mobile(codec, 1);
2234                         break;
2235                 case 2:
2236                         wm8994->dac_rates[1] = params_rate(params);
2237                         wm8994_set_retune_mobile(codec, 2);
2238                         break;
2239                 }
2240         }
2241
2242         return 0;
2243 }
2244
2245 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2246                                  struct snd_pcm_hw_params *params,
2247                                  struct snd_soc_dai *dai)
2248 {
2249         struct snd_soc_codec *codec = dai->codec;
2250         struct wm8994 *control = codec->control_data;
2251         int aif1_reg;
2252         int aif1 = 0;
2253
2254         switch (dai->id) {
2255         case 3:
2256                 switch (control->type) {
2257                 case WM8958:
2258                         aif1_reg = WM8958_AIF3_CONTROL_1;
2259                         break;
2260                 default:
2261                         return 0;
2262                 }
2263         default:
2264                 return 0;
2265         }
2266
2267         switch (params_format(params)) {
2268         case SNDRV_PCM_FORMAT_S16_LE:
2269                 break;
2270         case SNDRV_PCM_FORMAT_S20_3LE:
2271                 aif1 |= 0x20;
2272                 break;
2273         case SNDRV_PCM_FORMAT_S24_LE:
2274                 aif1 |= 0x40;
2275                 break;
2276         case SNDRV_PCM_FORMAT_S32_LE:
2277                 aif1 |= 0x60;
2278                 break;
2279         default:
2280                 return -EINVAL;
2281         }
2282
2283         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2284 }
2285
2286 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2287 {
2288         struct snd_soc_codec *codec = codec_dai->codec;
2289         int mute_reg;
2290         int reg;
2291
2292         switch (codec_dai->id) {
2293         case 1:
2294                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2295                 break;
2296         case 2:
2297                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2298                 break;
2299         default:
2300                 return -EINVAL;
2301         }
2302
2303         if (mute)
2304                 reg = WM8994_AIF1DAC1_MUTE;
2305         else
2306                 reg = 0;
2307
2308         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2309
2310         return 0;
2311 }
2312
2313 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2314 {
2315         struct snd_soc_codec *codec = codec_dai->codec;
2316         int reg, val, mask;
2317
2318         switch (codec_dai->id) {
2319         case 1:
2320                 reg = WM8994_AIF1_MASTER_SLAVE;
2321                 mask = WM8994_AIF1_TRI;
2322                 break;
2323         case 2:
2324                 reg = WM8994_AIF2_MASTER_SLAVE;
2325                 mask = WM8994_AIF2_TRI;
2326                 break;
2327         case 3:
2328                 reg = WM8994_POWER_MANAGEMENT_6;
2329                 mask = WM8994_AIF3_TRI;
2330                 break;
2331         default:
2332                 return -EINVAL;
2333         }
2334
2335         if (tristate)
2336                 val = mask;
2337         else
2338                 val = 0;
2339
2340         return snd_soc_update_bits(codec, reg, mask, val);
2341 }
2342
2343 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2344
2345 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2346                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2347
2348 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2349         .set_sysclk     = wm8994_set_dai_sysclk,
2350         .set_fmt        = wm8994_set_dai_fmt,
2351         .hw_params      = wm8994_hw_params,
2352         .digital_mute   = wm8994_aif_mute,
2353         .set_pll        = wm8994_set_fll,
2354         .set_tristate   = wm8994_set_tristate,
2355 };
2356
2357 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2358         .set_sysclk     = wm8994_set_dai_sysclk,
2359         .set_fmt        = wm8994_set_dai_fmt,
2360         .hw_params      = wm8994_hw_params,
2361         .digital_mute   = wm8994_aif_mute,
2362         .set_pll        = wm8994_set_fll,
2363         .set_tristate   = wm8994_set_tristate,
2364 };
2365
2366 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2367         .hw_params      = wm8994_aif3_hw_params,
2368         .set_tristate   = wm8994_set_tristate,
2369 };
2370
2371 static struct snd_soc_dai_driver wm8994_dai[] = {
2372         {
2373                 .name = "wm8994-aif1",
2374                 .id = 1,
2375                 .playback = {
2376                         .stream_name = "AIF1 Playback",
2377                         .channels_min = 1,
2378                         .channels_max = 2,
2379                         .rates = WM8994_RATES,
2380                         .formats = WM8994_FORMATS,
2381                 },
2382                 .capture = {
2383                         .stream_name = "AIF1 Capture",
2384                         .channels_min = 1,
2385                         .channels_max = 2,
2386                         .rates = WM8994_RATES,
2387                         .formats = WM8994_FORMATS,
2388                  },
2389                 .ops = &wm8994_aif1_dai_ops,
2390         },
2391         {
2392                 .name = "wm8994-aif2",
2393                 .id = 2,
2394                 .playback = {
2395                         .stream_name = "AIF2 Playback",
2396                         .channels_min = 1,
2397                         .channels_max = 2,
2398                         .rates = WM8994_RATES,
2399                         .formats = WM8994_FORMATS,
2400                 },
2401                 .capture = {
2402                         .stream_name = "AIF2 Capture",
2403                         .channels_min = 1,
2404                         .channels_max = 2,
2405                         .rates = WM8994_RATES,
2406                         .formats = WM8994_FORMATS,
2407                 },
2408                 .ops = &wm8994_aif2_dai_ops,
2409         },
2410         {
2411                 .name = "wm8994-aif3",
2412                 .id = 3,
2413                 .playback = {
2414                         .stream_name = "AIF3 Playback",
2415                         .channels_min = 1,
2416                         .channels_max = 2,
2417                         .rates = WM8994_RATES,
2418                         .formats = WM8994_FORMATS,
2419                 },
2420                 .capture = {
2421                         .stream_name = "AIF3 Capture",
2422                         .channels_min = 1,
2423                         .channels_max = 2,
2424                         .rates = WM8994_RATES,
2425                         .formats = WM8994_FORMATS,
2426                 },
2427                 .ops = &wm8994_aif3_dai_ops,
2428         }
2429 };
2430
2431 #ifdef CONFIG_PM
2432 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2433 {
2434         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2435         struct wm8994 *control = codec->control_data;
2436         int i, ret;
2437
2438         switch (control->type) {
2439         case WM8994:
2440                 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2441                 break;
2442         case WM8958:
2443                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2444                                     WM8958_MICD_ENA, 0);
2445                 break;
2446         }
2447
2448         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2449                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2450                        sizeof(struct wm8994_fll_config));
2451                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2452                 if (ret < 0)
2453                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2454                                  i + 1, ret);
2455         }
2456
2457         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2458
2459         return 0;
2460 }
2461
2462 static int wm8994_resume(struct snd_soc_codec *codec)
2463 {
2464         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2465         struct wm8994 *control = codec->control_data;
2466         int i, ret;
2467         unsigned int val, mask;
2468
2469         if (wm8994->revision < 4) {
2470                 /* force a HW read */
2471                 val = wm8994_reg_read(codec->control_data,
2472                                       WM8994_POWER_MANAGEMENT_5);
2473
2474                 /* modify the cache only */
2475                 codec->cache_only = 1;
2476                 mask =  WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2477                         WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2478                 val &= mask;
2479                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2480                                     mask, val);
2481                 codec->cache_only = 0;
2482         }
2483
2484         /* Restore the registers */
2485         ret = snd_soc_cache_sync(codec);
2486         if (ret != 0)
2487                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2488
2489         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2490
2491         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2492                 if (!wm8994->fll_suspend[i].out)
2493                         continue;
2494
2495                 ret = _wm8994_set_fll(codec, i + 1,
2496                                      wm8994->fll_suspend[i].src,
2497                                      wm8994->fll_suspend[i].in,
2498                                      wm8994->fll_suspend[i].out);
2499                 if (ret < 0)
2500                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2501                                  i + 1, ret);
2502         }
2503
2504         switch (control->type) {
2505         case WM8994:
2506                 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2507                         snd_soc_update_bits(codec, WM8994_MICBIAS,
2508                                             WM8994_MICD_ENA, WM8994_MICD_ENA);
2509                 break;
2510         case WM8958:
2511                 if (wm8994->jack_cb)
2512                         snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2513                                             WM8958_MICD_ENA, WM8958_MICD_ENA);
2514                 break;
2515         }
2516
2517         return 0;
2518 }
2519 #else
2520 #define wm8994_suspend NULL
2521 #define wm8994_resume NULL
2522 #endif
2523
2524 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2525 {
2526         struct snd_soc_codec *codec = wm8994->codec;
2527         struct wm8994_pdata *pdata = wm8994->pdata;
2528         struct snd_kcontrol_new controls[] = {
2529                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2530                              wm8994->retune_mobile_enum,
2531                              wm8994_get_retune_mobile_enum,
2532                              wm8994_put_retune_mobile_enum),
2533                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2534                              wm8994->retune_mobile_enum,
2535                              wm8994_get_retune_mobile_enum,
2536                              wm8994_put_retune_mobile_enum),
2537                 SOC_ENUM_EXT("AIF2 EQ Mode",
2538                              wm8994->retune_mobile_enum,
2539                              wm8994_get_retune_mobile_enum,
2540                              wm8994_put_retune_mobile_enum),
2541         };
2542         int ret, i, j;
2543         const char **t;
2544
2545         /* We need an array of texts for the enum API but the number
2546          * of texts is likely to be less than the number of
2547          * configurations due to the sample rate dependency of the
2548          * configurations. */
2549         wm8994->num_retune_mobile_texts = 0;
2550         wm8994->retune_mobile_texts = NULL;
2551         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2552                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2553                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2554                                    wm8994->retune_mobile_texts[j]) == 0)
2555                                 break;
2556                 }
2557
2558                 if (j != wm8994->num_retune_mobile_texts)
2559                         continue;
2560
2561                 /* Expand the array... */
2562                 t = krealloc(wm8994->retune_mobile_texts,
2563                              sizeof(char *) *
2564                              (wm8994->num_retune_mobile_texts + 1),
2565                              GFP_KERNEL);
2566                 if (t == NULL)
2567                         continue;
2568
2569                 /* ...store the new entry... */
2570                 t[wm8994->num_retune_mobile_texts] =
2571                         pdata->retune_mobile_cfgs[i].name;
2572
2573                 /* ...and remember the new version. */
2574                 wm8994->num_retune_mobile_texts++;
2575                 wm8994->retune_mobile_texts = t;
2576         }
2577
2578         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2579                 wm8994->num_retune_mobile_texts);
2580
2581         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2582         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2583
2584         ret = snd_soc_add_controls(wm8994->codec, controls,
2585                                    ARRAY_SIZE(controls));
2586         if (ret != 0)
2587                 dev_err(wm8994->codec->dev,
2588                         "Failed to add ReTune Mobile controls: %d\n", ret);
2589 }
2590
2591 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2592 {
2593         struct snd_soc_codec *codec = wm8994->codec;
2594         struct wm8994_pdata *pdata = wm8994->pdata;
2595         int ret, i;
2596
2597         if (!pdata)
2598                 return;
2599
2600         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2601                                       pdata->lineout2_diff,
2602                                       pdata->lineout1fb,
2603                                       pdata->lineout2fb,
2604                                       pdata->jd_scthr,
2605                                       pdata->jd_thr,
2606                                       pdata->micbias1_lvl,
2607                                       pdata->micbias2_lvl);
2608
2609         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2610
2611         if (pdata->num_drc_cfgs) {
2612                 struct snd_kcontrol_new controls[] = {
2613                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2614                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2615                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2616                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2617                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2618                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2619                 };
2620
2621                 /* We need an array of texts for the enum API */
2622                 wm8994->drc_texts = kmalloc(sizeof(char *)
2623                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2624                 if (!wm8994->drc_texts) {
2625                         dev_err(wm8994->codec->dev,
2626                                 "Failed to allocate %d DRC config texts\n",
2627                                 pdata->num_drc_cfgs);
2628                         return;
2629                 }
2630
2631                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2632                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2633
2634                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2635                 wm8994->drc_enum.texts = wm8994->drc_texts;
2636
2637                 ret = snd_soc_add_controls(wm8994->codec, controls,
2638                                            ARRAY_SIZE(controls));
2639                 if (ret != 0)
2640                         dev_err(wm8994->codec->dev,
2641                                 "Failed to add DRC mode controls: %d\n", ret);
2642
2643                 for (i = 0; i < WM8994_NUM_DRC; i++)
2644                         wm8994_set_drc(codec, i);
2645         }
2646
2647         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2648                 pdata->num_retune_mobile_cfgs);
2649
2650         if (pdata->num_retune_mobile_cfgs)
2651                 wm8994_handle_retune_mobile_pdata(wm8994);
2652         else
2653                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2654                                      ARRAY_SIZE(wm8994_eq_controls));
2655
2656         for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2657                 if (pdata->micbias[i]) {
2658                         snd_soc_write(codec, WM8958_MICBIAS1 + i,
2659                                 pdata->micbias[i] & 0xffff);
2660                 }
2661         }
2662 }
2663
2664 /**
2665  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2666  *
2667  * @codec:   WM8994 codec
2668  * @jack:    jack to report detection events on
2669  * @micbias: microphone bias to detect on
2670  * @det:     value to report for presence detection
2671  * @shrt:    value to report for short detection
2672  *
2673  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2674  * being used to bring out signals to the processor then only platform
2675  * data configuration is needed for WM8994 and processor GPIOs should
2676  * be configured using snd_soc_jack_add_gpios() instead.
2677  *
2678  * Configuration of detection levels is available via the micbias1_lvl
2679  * and micbias2_lvl platform data members.
2680  */
2681 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2682                       int micbias, int det, int shrt)
2683 {
2684         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2685         struct wm8994_micdet *micdet;
2686         struct wm8994 *control = codec->control_data;
2687         int reg;
2688
2689         if (control->type != WM8994)
2690                 return -EINVAL;
2691
2692         switch (micbias) {
2693         case 1:
2694                 micdet = &wm8994->micdet[0];
2695                 break;
2696         case 2:
2697                 micdet = &wm8994->micdet[1];
2698                 break;
2699         default:
2700                 return -EINVAL;
2701         }
2702
2703         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2704                 micbias, det, shrt);
2705
2706         /* Store the configuration */
2707         micdet->jack = jack;
2708         micdet->det = det;
2709         micdet->shrt = shrt;
2710
2711         /* If either of the jacks is set up then enable detection */
2712         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2713                 reg = WM8994_MICD_ENA;
2714         else
2715                 reg = 0;
2716
2717         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2718
2719         return 0;
2720 }
2721 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2722
2723 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2724 {
2725         struct wm8994_priv *priv = data;
2726         struct snd_soc_codec *codec = priv->codec;
2727         int reg;
2728         int report;
2729
2730 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2731         trace_snd_soc_jack_irq(dev_name(codec->dev));
2732 #endif
2733
2734         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2735         if (reg < 0) {
2736                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2737                         reg);
2738                 return IRQ_HANDLED;
2739         }
2740
2741         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2742
2743         report = 0;
2744         if (reg & WM8994_MIC1_DET_STS)
2745                 report |= priv->micdet[0].det;
2746         if (reg & WM8994_MIC1_SHRT_STS)
2747                 report |= priv->micdet[0].shrt;
2748         snd_soc_jack_report(priv->micdet[0].jack, report,
2749                             priv->micdet[0].det | priv->micdet[0].shrt);
2750
2751         report = 0;
2752         if (reg & WM8994_MIC2_DET_STS)
2753                 report |= priv->micdet[1].det;
2754         if (reg & WM8994_MIC2_SHRT_STS)
2755                 report |= priv->micdet[1].shrt;
2756         snd_soc_jack_report(priv->micdet[1].jack, report,
2757                             priv->micdet[1].det | priv->micdet[1].shrt);
2758
2759         return IRQ_HANDLED;
2760 }
2761
2762 /* Default microphone detection handler for WM8958 - the user can
2763  * override this if they wish.
2764  */
2765 static void wm8958_default_micdet(u16 status, void *data)
2766 {
2767         struct snd_soc_codec *codec = data;
2768         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2769         int report = 0;
2770
2771         /* If nothing present then clear our statuses */
2772         if (!(status & WM8958_MICD_STS))
2773                 goto done;
2774
2775         report = SND_JACK_MICROPHONE;
2776
2777         /* Everything else is buttons; just assign slots */
2778         if (status & 0x1c0)
2779                 report |= SND_JACK_BTN_0;
2780
2781 done:
2782         snd_soc_jack_report(wm8994->micdet[0].jack, report,
2783                             SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2784 }
2785
2786 /**
2787  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2788  *
2789  * @codec:   WM8958 codec
2790  * @jack:    jack to report detection events on
2791  *
2792  * Enable microphone detection functionality for the WM8958.  By
2793  * default simple detection which supports the detection of up to 6
2794  * buttons plus video and microphone functionality is supported.
2795  *
2796  * The WM8958 has an advanced jack detection facility which is able to
2797  * support complex accessory detection, especially when used in
2798  * conjunction with external circuitry.  In order to provide maximum
2799  * flexiblity a callback is provided which allows a completely custom
2800  * detection algorithm.
2801  */
2802 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2803                       wm8958_micdet_cb cb, void *cb_data)
2804 {
2805         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2806         struct wm8994 *control = codec->control_data;
2807
2808         if (control->type != WM8958)
2809                 return -EINVAL;
2810
2811         if (jack) {
2812                 if (!cb) {
2813                         dev_dbg(codec->dev, "Using default micdet callback\n");
2814                         cb = wm8958_default_micdet;
2815                         cb_data = codec;
2816                 }
2817
2818                 wm8994->micdet[0].jack = jack;
2819                 wm8994->jack_cb = cb;
2820                 wm8994->jack_cb_data = cb_data;
2821
2822                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2823                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
2824         } else {
2825                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2826                                     WM8958_MICD_ENA, 0);
2827         }
2828
2829         return 0;
2830 }
2831 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2832
2833 static irqreturn_t wm8958_mic_irq(int irq, void *data)
2834 {
2835         struct wm8994_priv *wm8994 = data;
2836         struct snd_soc_codec *codec = wm8994->codec;
2837         int reg;
2838
2839         reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2840         if (reg < 0) {
2841                 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2842                         reg);
2843                 return IRQ_NONE;
2844         }
2845
2846         if (!(reg & WM8958_MICD_VALID)) {
2847                 dev_dbg(codec->dev, "Mic detect data not valid\n");
2848                 goto out;
2849         }
2850
2851 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2852         trace_snd_soc_jack_irq(dev_name(codec->dev));
2853 #endif
2854
2855         if (wm8994->jack_cb)
2856                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2857         else
2858                 dev_warn(codec->dev, "Accessory detection with no callback\n");
2859
2860 out:
2861         return IRQ_HANDLED;
2862 }
2863
2864 static int wm8994_codec_probe(struct snd_soc_codec *codec)
2865 {
2866         struct wm8994 *control;
2867         struct wm8994_priv *wm8994;
2868         struct snd_soc_dapm_context *dapm = &codec->dapm;
2869         int ret, i;
2870
2871         codec->control_data = dev_get_drvdata(codec->dev->parent);
2872         control = codec->control_data;
2873
2874         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2875         if (wm8994 == NULL)
2876                 return -ENOMEM;
2877         snd_soc_codec_set_drvdata(codec, wm8994);
2878
2879         wm8994->pdata = dev_get_platdata(codec->dev->parent);
2880         wm8994->codec = codec;
2881
2882         if (wm8994->pdata && wm8994->pdata->micdet_irq)
2883                 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2884         else if (wm8994->pdata && wm8994->pdata->irq_base)
2885                 wm8994->micdet_irq = wm8994->pdata->irq_base +
2886                                      WM8994_IRQ_MIC1_DET;
2887
2888         pm_runtime_enable(codec->dev);
2889         pm_runtime_resume(codec->dev);
2890
2891         /* Read our current status back from the chip - we don't want to
2892          * reset as this may interfere with the GPIO or LDO operation. */
2893         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2894                 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
2895                         continue;
2896
2897                 ret = wm8994_reg_read(codec->control_data, i);
2898                 if (ret <= 0)
2899                         continue;
2900
2901                 ret = snd_soc_cache_write(codec, i, ret);
2902                 if (ret != 0) {
2903                         dev_err(codec->dev,
2904                                 "Failed to initialise cache for 0x%x: %d\n",
2905                                 i, ret);
2906                         goto err;
2907                 }
2908         }
2909
2910         /* Set revision-specific configuration */
2911         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2912         switch (control->type) {
2913         case WM8994:
2914                 switch (wm8994->revision) {
2915                 case 2:
2916                 case 3:
2917                         wm8994->hubs.dcs_codes = -5;
2918                         wm8994->hubs.hp_startup_mode = 1;
2919                         wm8994->hubs.dcs_readback_mode = 1;
2920                         wm8994->hubs.series_startup = 1;
2921                         break;
2922                 default:
2923                         wm8994->hubs.dcs_readback_mode = 1;
2924                         break;
2925                 }
2926
2927         case WM8958:
2928                 wm8994->hubs.dcs_readback_mode = 1;
2929                 break;
2930
2931         default:
2932                 break;
2933         }
2934
2935         ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
2936                                  wm_hubs_dcs_done, "DC servo done",
2937                                  &wm8994->hubs);
2938         if (ret == 0)
2939                 wm8994->hubs.dcs_done_irq = true;
2940
2941         switch (control->type) {
2942         case WM8994:
2943                 if (wm8994->micdet_irq) {
2944                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
2945                                                    wm8994_mic_irq,
2946                                                    IRQF_TRIGGER_RISING,
2947                                                    "Mic1 detect",
2948                                                    wm8994);
2949                         if (ret != 0)
2950                                 dev_warn(codec->dev,
2951                                          "Failed to request Mic1 detect IRQ: %d\n",
2952                                          ret);
2953                 }
2954
2955                 ret = wm8994_request_irq(codec->control_data,
2956                                          WM8994_IRQ_MIC1_SHRT,
2957                                          wm8994_mic_irq, "Mic 1 short",
2958                                          wm8994);
2959                 if (ret != 0)
2960                         dev_warn(codec->dev,
2961                                  "Failed to request Mic1 short IRQ: %d\n",
2962                                  ret);
2963
2964                 ret = wm8994_request_irq(codec->control_data,
2965                                          WM8994_IRQ_MIC2_DET,
2966                                          wm8994_mic_irq, "Mic 2 detect",
2967                                          wm8994);
2968                 if (ret != 0)
2969                         dev_warn(codec->dev,
2970                                  "Failed to request Mic2 detect IRQ: %d\n",
2971                                  ret);
2972
2973                 ret = wm8994_request_irq(codec->control_data,
2974                                          WM8994_IRQ_MIC2_SHRT,
2975                                          wm8994_mic_irq, "Mic 2 short",
2976                                          wm8994);
2977                 if (ret != 0)
2978                         dev_warn(codec->dev,
2979                                  "Failed to request Mic2 short IRQ: %d\n",
2980                                  ret);
2981                 break;
2982
2983         case WM8958:
2984                 if (wm8994->micdet_irq) {
2985                         ret = request_threaded_irq(wm8994->micdet_irq, NULL,
2986                                                    wm8958_mic_irq,
2987                                                    IRQF_TRIGGER_RISING,
2988                                                    "Mic detect",
2989                                                    wm8994);
2990                         if (ret != 0)
2991                                 dev_warn(codec->dev,
2992                                          "Failed to request Mic detect IRQ: %d\n",
2993                                          ret);
2994                 }
2995         }
2996
2997         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
2998          * configured on init - if a system wants to do this dynamically
2999          * at runtime we can deal with that then.
3000          */
3001         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3002         if (ret < 0) {
3003                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3004                 goto err_irq;
3005         }
3006         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3007                 wm8994->lrclk_shared[0] = 1;
3008                 wm8994_dai[0].symmetric_rates = 1;
3009         } else {
3010                 wm8994->lrclk_shared[0] = 0;
3011         }
3012
3013         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3014         if (ret < 0) {
3015                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3016                 goto err_irq;
3017         }
3018         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3019                 wm8994->lrclk_shared[1] = 1;
3020                 wm8994_dai[1].symmetric_rates = 1;
3021         } else {
3022                 wm8994->lrclk_shared[1] = 0;
3023         }
3024
3025         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3026
3027         /* Latch volume updates (right only; we always do left then right). */
3028         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3029                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3030         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3031                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3032         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3033                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3034         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3035                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3036         snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3037                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3038         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3039                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3040         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3041                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3042         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3043                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3044         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3045                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3046         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3047                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3048         snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3049                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3050         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3051                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3052         snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3053                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3054         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3055                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3056         snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3057                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3058         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3059                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3060
3061         /* Set the low bit of the 3D stereo depth so TLV matches */
3062         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3063                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3064                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3065         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3066                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3067                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3068         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3069                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3070                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3071
3072         /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3073          * use this; it only affects behaviour on idle TDM clock
3074          * cycles. */
3075         switch (control->type) {
3076         case WM8994:
3077         case WM8958:
3078                 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3079                                     WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3080                 break;
3081         default:
3082                 break;
3083         }
3084
3085         wm8994_update_class_w(codec);
3086
3087         wm8994_handle_pdata(wm8994);
3088
3089         wm_hubs_add_analogue_controls(codec);
3090         snd_soc_add_controls(codec, wm8994_snd_controls,
3091                              ARRAY_SIZE(wm8994_snd_controls));
3092         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3093                                   ARRAY_SIZE(wm8994_dapm_widgets));
3094
3095         switch (control->type) {
3096         case WM8994:
3097                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3098                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3099                 if (wm8994->revision < 4) {
3100                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3101                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3102                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3103                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3104                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3105                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3106                 } else {
3107                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3108                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3109                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3110                                                   ARRAY_SIZE(wm8994_adc_widgets));
3111                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3112                                                   ARRAY_SIZE(wm8994_dac_widgets));
3113                 }
3114                 break;
3115         case WM8958:
3116                 snd_soc_add_controls(codec, wm8958_snd_controls,
3117                                      ARRAY_SIZE(wm8958_snd_controls));
3118                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3119                                           ARRAY_SIZE(wm8958_dapm_widgets));
3120                 if (wm8994->revision < 1) {
3121                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3122                                                   ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3123                         snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3124                                                   ARRAY_SIZE(wm8994_adc_revd_widgets));
3125                         snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3126                                                   ARRAY_SIZE(wm8994_dac_revd_widgets));
3127                 } else {
3128                         snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3129                                                   ARRAY_SIZE(wm8994_lateclk_widgets));
3130                         snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3131                                                   ARRAY_SIZE(wm8994_adc_widgets));
3132                         snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3133                                                   ARRAY_SIZE(wm8994_dac_widgets));
3134                 }
3135                 break;
3136         }
3137
3138
3139         wm_hubs_add_analogue_routes(codec, 0, 0);
3140         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3141
3142         switch (control->type) {
3143         case WM8994:
3144                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3145                                         ARRAY_SIZE(wm8994_intercon));
3146
3147                 if (wm8994->revision < 4) {
3148                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3149                                                 ARRAY_SIZE(wm8994_revd_intercon));
3150                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3151                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3152                 } else {
3153                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3154                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3155                 }
3156                 break;
3157         case WM8958:
3158                 if (wm8994->revision < 1) {
3159                         snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3160                                                 ARRAY_SIZE(wm8994_revd_intercon));
3161                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3162                                                 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3163                 } else {
3164                         snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3165                                                 ARRAY_SIZE(wm8994_lateclk_intercon));
3166                         snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3167                                                 ARRAY_SIZE(wm8958_intercon));
3168                 }
3169
3170                 wm8958_dsp2_init(codec);
3171                 break;
3172         }
3173
3174         return 0;
3175
3176 err_irq:
3177         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3178         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3179         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3180         if (wm8994->micdet_irq)
3181                 free_irq(wm8994->micdet_irq, wm8994);
3182         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3183                         &wm8994->hubs);
3184 err:
3185         kfree(wm8994);
3186         return ret;
3187 }
3188
3189 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3190 {
3191         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3192         struct wm8994 *control = codec->control_data;
3193
3194         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3195
3196         pm_runtime_disable(codec->dev);
3197
3198         wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3199                         &wm8994->hubs);
3200
3201         switch (control->type) {
3202         case WM8994:
3203                 if (wm8994->micdet_irq)
3204                         free_irq(wm8994->micdet_irq, wm8994);
3205                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3206                                 wm8994);
3207                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3208                                 wm8994);
3209                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3210                                 wm8994);
3211                 break;
3212
3213         case WM8958:
3214                 if (wm8994->micdet_irq)
3215                         free_irq(wm8994->micdet_irq, wm8994);
3216                 break;
3217         }
3218         if (wm8994->mbc)
3219                 release_firmware(wm8994->mbc);
3220         if (wm8994->mbc_vss)
3221                 release_firmware(wm8994->mbc_vss);
3222         if (wm8994->enh_eq)
3223                 release_firmware(wm8994->enh_eq);
3224         kfree(wm8994->retune_mobile_texts);
3225         kfree(wm8994->drc_texts);
3226         kfree(wm8994);
3227
3228         return 0;
3229 }
3230
3231 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3232         .probe =        wm8994_codec_probe,
3233         .remove =       wm8994_codec_remove,
3234         .suspend =      wm8994_suspend,
3235         .resume =       wm8994_resume,
3236         .read =         wm8994_read,
3237         .write =        wm8994_write,
3238         .readable_register = wm8994_readable,
3239         .volatile_register = wm8994_volatile,
3240         .set_bias_level = wm8994_set_bias_level,
3241
3242         .reg_cache_size = WM8994_CACHE_SIZE,
3243         .reg_cache_default = wm8994_reg_defaults,
3244         .reg_word_size = 2,
3245         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3246 };
3247
3248 static int __devinit wm8994_probe(struct platform_device *pdev)
3249 {
3250         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3251                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3252 }
3253
3254 static int __devexit wm8994_remove(struct platform_device *pdev)
3255 {
3256         snd_soc_unregister_codec(&pdev->dev);
3257         return 0;
3258 }
3259
3260 static struct platform_driver wm8994_codec_driver = {
3261         .driver = {
3262                    .name = "wm8994-codec",
3263                    .owner = THIS_MODULE,
3264                    },
3265         .probe = wm8994_probe,
3266         .remove = __devexit_p(wm8994_remove),
3267 };
3268
3269 static __init int wm8994_init(void)
3270 {
3271         return platform_driver_register(&wm8994_codec_driver);
3272 }
3273 module_init(wm8994_init);
3274
3275 static __exit void wm8994_exit(void)
3276 {
3277         platform_driver_unregister(&wm8994_codec_driver);
3278 }
3279 module_exit(wm8994_exit);
3280
3281
3282 MODULE_DESCRIPTION("ASoC WM8994 driver");
3283 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3284 MODULE_LICENSE("GPL");
3285 MODULE_ALIAS("platform:wm8994-codec");