2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009-12 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM1811_JACKDET_MODE_NONE 0x0000
42 #define WM1811_JACKDET_MODE_JACK 0x0100
43 #define WM1811_JACKDET_MODE_MIC 0x0080
44 #define WM1811_JACKDET_MODE_AUDIO 0x0180
46 #define WM8994_NUM_DRC 3
47 #define WM8994_NUM_EQ 3
52 } wm8994_vu_bits[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
82 static int wm8994_drc_base[] = {
88 static int wm8994_retune_mobile_base[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1,
90 WM8994_AIF1_DAC2_EQ_GAINS_1,
91 WM8994_AIF2_EQ_GAINS_1,
94 static const struct wm8958_micd_rate micdet_rates[] = {
95 { 32768, true, 1, 4 },
96 { 32768, false, 1, 1 },
97 { 44100 * 256, true, 7, 10 },
98 { 44100 * 256, false, 7, 10 },
101 static const struct wm8958_micd_rate jackdet_rates[] = {
102 { 32768, true, 0, 1 },
103 { 32768, false, 0, 1 },
104 { 44100 * 256, true, 10, 10 },
105 { 44100 * 256, false, 7, 8 },
108 static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
111 struct wm8994 *control = wm8994->wm8994;
112 int best, i, sysclk, val;
114 const struct wm8958_micd_rate *rates;
117 idle = !wm8994->jack_mic;
119 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
120 if (sysclk & WM8994_SYSCLK_SRC)
121 sysclk = wm8994->aifclk[1];
123 sysclk = wm8994->aifclk[0];
125 if (control->pdata.micd_rates) {
126 rates = control->pdata.micd_rates;
127 num_rates = control->pdata.num_micd_rates;
128 } else if (wm8994->jackdet) {
129 rates = jackdet_rates;
130 num_rates = ARRAY_SIZE(jackdet_rates);
132 rates = micdet_rates;
133 num_rates = ARRAY_SIZE(micdet_rates);
137 for (i = 0; i < num_rates; i++) {
138 if (rates[i].idle != idle)
140 if (abs(rates[i].sysclk - sysclk) <
141 abs(rates[best].sysclk - sysclk))
143 else if (rates[best].idle != idle)
147 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
148 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
150 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
151 rates[best].start, rates[best].rate, sysclk,
152 idle ? "idle" : "active");
154 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
155 WM8958_MICD_BIAS_STARTTIME_MASK |
156 WM8958_MICD_RATE_MASK, val);
159 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
171 switch (wm8994->sysclk[aif]) {
172 case WM8994_SYSCLK_MCLK1:
173 rate = wm8994->mclk[0];
176 case WM8994_SYSCLK_MCLK2:
178 rate = wm8994->mclk[1];
181 case WM8994_SYSCLK_FLL1:
183 rate = wm8994->fll[0].out;
186 case WM8994_SYSCLK_FLL2:
188 rate = wm8994->fll[1].out;
195 if (rate >= 13500000) {
197 reg1 |= WM8994_AIF1CLK_DIV;
199 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
203 wm8994->aifclk[aif] = rate;
205 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
206 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
212 static int configure_clock(struct snd_soc_codec *codec)
214 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
217 /* Bring up the AIF clocks first */
218 configure_aif_clock(codec, 0);
219 configure_aif_clock(codec, 1);
221 /* Then switch CLK_SYS over to the higher of them; a change
222 * can only happen as a result of a clocking change which can
223 * only be made outside of DAPM so we can safely redo the
227 /* If they're equal it doesn't matter which is used */
228 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
229 wm8958_micd_set_rate(codec);
233 if (wm8994->aifclk[0] < wm8994->aifclk[1])
234 new = WM8994_SYSCLK_SRC;
238 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
239 WM8994_SYSCLK_SRC, new);
241 snd_soc_dapm_sync(&codec->dapm);
243 wm8958_micd_set_rate(codec);
248 static int check_clk_sys(struct snd_soc_dapm_widget *source,
249 struct snd_soc_dapm_widget *sink)
251 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
254 /* Check what we're currently using for CLK_SYS */
255 if (reg & WM8994_SYSCLK_SRC)
260 return strcmp(source->name, clk) == 0;
263 static const char *sidetone_hpf_text[] = {
264 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
267 static const struct soc_enum sidetone_hpf =
268 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
270 static const char *adc_hpf_text[] = {
271 "HiFi", "Voice 1", "Voice 2", "Voice 3"
274 static const struct soc_enum aif1adc1_hpf =
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
277 static const struct soc_enum aif1adc2_hpf =
278 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
280 static const struct soc_enum aif2adc_hpf =
281 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
283 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
284 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
285 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
286 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
287 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
288 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
289 static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
291 #define WM8994_DRC_SWITCH(xname, reg, shift) \
292 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
293 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
294 .put = wm8994_put_drc_sw, \
295 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
297 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
298 struct snd_ctl_elem_value *ucontrol)
300 struct soc_mixer_control *mc =
301 (struct soc_mixer_control *)kcontrol->private_value;
302 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
305 /* Can't enable both ADC and DAC paths simultaneously */
306 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
307 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
308 WM8994_AIF1ADC1R_DRC_ENA_MASK;
310 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
312 ret = snd_soc_read(codec, mc->reg);
318 return snd_soc_put_volsw(kcontrol, ucontrol);
321 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
323 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
324 struct wm8994 *control = wm8994->wm8994;
325 struct wm8994_pdata *pdata = &control->pdata;
326 int base = wm8994_drc_base[drc];
327 int cfg = wm8994->drc_cfg[drc];
330 /* Save any enables; the configuration should clear them. */
331 save = snd_soc_read(codec, base);
332 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
333 WM8994_AIF1ADC1R_DRC_ENA;
335 for (i = 0; i < WM8994_DRC_REGS; i++)
336 snd_soc_update_bits(codec, base + i, 0xffff,
337 pdata->drc_cfgs[cfg].regs[i]);
339 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
340 WM8994_AIF1ADC1L_DRC_ENA |
341 WM8994_AIF1ADC1R_DRC_ENA, save);
344 /* Icky as hell but saves code duplication */
345 static int wm8994_get_drc(const char *name)
347 if (strcmp(name, "AIF1DRC1 Mode") == 0)
349 if (strcmp(name, "AIF1DRC2 Mode") == 0)
351 if (strcmp(name, "AIF2DRC Mode") == 0)
356 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
357 struct snd_ctl_elem_value *ucontrol)
359 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
360 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
361 struct wm8994 *control = wm8994->wm8994;
362 struct wm8994_pdata *pdata = &control->pdata;
363 int drc = wm8994_get_drc(kcontrol->id.name);
364 int value = ucontrol->value.integer.value[0];
369 if (value >= pdata->num_drc_cfgs)
372 wm8994->drc_cfg[drc] = value;
374 wm8994_set_drc(codec, drc);
379 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
382 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
383 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
384 int drc = wm8994_get_drc(kcontrol->id.name);
388 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
393 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
395 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
396 struct wm8994 *control = wm8994->wm8994;
397 struct wm8994_pdata *pdata = &control->pdata;
398 int base = wm8994_retune_mobile_base[block];
399 int iface, best, best_val, save, i, cfg;
401 if (!pdata || !wm8994->num_retune_mobile_texts)
416 /* Find the version of the currently selected configuration
417 * with the nearest sample rate. */
418 cfg = wm8994->retune_mobile_cfg[block];
421 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
422 if (strcmp(pdata->retune_mobile_cfgs[i].name,
423 wm8994->retune_mobile_texts[cfg]) == 0 &&
424 abs(pdata->retune_mobile_cfgs[i].rate
425 - wm8994->dac_rates[iface]) < best_val) {
427 best_val = abs(pdata->retune_mobile_cfgs[i].rate
428 - wm8994->dac_rates[iface]);
432 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
434 pdata->retune_mobile_cfgs[best].name,
435 pdata->retune_mobile_cfgs[best].rate,
436 wm8994->dac_rates[iface]);
438 /* The EQ will be disabled while reconfiguring it, remember the
439 * current configuration.
441 save = snd_soc_read(codec, base);
442 save &= WM8994_AIF1DAC1_EQ_ENA;
444 for (i = 0; i < WM8994_EQ_REGS; i++)
445 snd_soc_update_bits(codec, base + i, 0xffff,
446 pdata->retune_mobile_cfgs[best].regs[i]);
448 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
451 /* Icky as hell but saves code duplication */
452 static int wm8994_get_retune_mobile_block(const char *name)
454 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
456 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
458 if (strcmp(name, "AIF2 EQ Mode") == 0)
463 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
464 struct snd_ctl_elem_value *ucontrol)
466 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
468 struct wm8994 *control = wm8994->wm8994;
469 struct wm8994_pdata *pdata = &control->pdata;
470 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
471 int value = ucontrol->value.integer.value[0];
476 if (value >= pdata->num_retune_mobile_cfgs)
479 wm8994->retune_mobile_cfg[block] = value;
481 wm8994_set_retune_mobile(codec, block);
486 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
487 struct snd_ctl_elem_value *ucontrol)
489 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
490 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
491 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
496 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
501 static const char *aif_chan_src_text[] = {
505 static const struct soc_enum aif1adcl_src =
506 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
508 static const struct soc_enum aif1adcr_src =
509 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
511 static const struct soc_enum aif2adcl_src =
512 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
514 static const struct soc_enum aif2adcr_src =
515 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
517 static const struct soc_enum aif1dacl_src =
518 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
520 static const struct soc_enum aif1dacr_src =
521 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
523 static const struct soc_enum aif2dacl_src =
524 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
526 static const struct soc_enum aif2dacr_src =
527 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
529 static const char *osr_text[] = {
530 "Low Power", "High Performance",
533 static const struct soc_enum dac_osr =
534 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
536 static const struct soc_enum adc_osr =
537 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
539 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
540 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
541 WM8994_AIF1_ADC1_RIGHT_VOLUME,
542 1, 119, 0, digital_tlv),
543 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
544 WM8994_AIF1_ADC2_RIGHT_VOLUME,
545 1, 119, 0, digital_tlv),
546 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
547 WM8994_AIF2_ADC_RIGHT_VOLUME,
548 1, 119, 0, digital_tlv),
550 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
551 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
552 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
553 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
555 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
556 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
557 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
558 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
560 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
561 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
563 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
564 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
565 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
567 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
568 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
570 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
571 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
572 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
574 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
575 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
576 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
578 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
579 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
580 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
582 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
583 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
584 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
586 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
588 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
590 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
592 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
594 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
595 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
597 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
598 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
600 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
601 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
603 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
604 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
606 SOC_ENUM("ADC OSR", adc_osr),
607 SOC_ENUM("DAC OSR", dac_osr),
609 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
610 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
611 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
612 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
614 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
615 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
616 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
617 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
619 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
620 6, 1, 1, wm_hubs_spkmix_tlv),
621 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
622 2, 1, 1, wm_hubs_spkmix_tlv),
624 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
625 6, 1, 1, wm_hubs_spkmix_tlv),
626 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
627 2, 1, 1, wm_hubs_spkmix_tlv),
629 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
631 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
633 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
634 10, 15, 0, wm8994_3d_tlv),
635 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
637 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
638 10, 15, 0, wm8994_3d_tlv),
639 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
643 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
644 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
646 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
648 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
650 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
652 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
655 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
657 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
659 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
661 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
663 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
666 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
668 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
670 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
672 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
674 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
678 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
679 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
680 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
681 WM8994_AIF1ADC1R_DRC_ENA),
682 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
683 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
684 WM8994_AIF1ADC2R_DRC_ENA),
685 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
686 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
687 WM8994_AIF2ADCR_DRC_ENA),
690 static const char *wm8958_ng_text[] = {
691 "30ms", "125ms", "250ms", "500ms",
694 static const struct soc_enum wm8958_aif1dac1_ng_hold =
695 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
696 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
698 static const struct soc_enum wm8958_aif1dac2_ng_hold =
699 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
700 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
702 static const struct soc_enum wm8958_aif2dac_ng_hold =
703 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
704 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
706 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
707 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
709 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
710 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
711 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
712 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
713 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
716 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
717 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
718 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
719 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
720 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
723 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
724 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
725 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
726 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
727 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
731 static const struct snd_kcontrol_new wm1811_snd_controls[] = {
732 SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
734 SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
738 /* We run all mode setting through a function to enforce audio mode */
739 static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
741 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
743 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
746 if (wm8994->active_refcount)
747 mode = WM1811_JACKDET_MODE_AUDIO;
749 if (mode == wm8994->jackdet_mode)
752 wm8994->jackdet_mode = mode;
754 /* Always use audio mode to detect while the system is active */
755 if (mode != WM1811_JACKDET_MODE_NONE)
756 mode = WM1811_JACKDET_MODE_AUDIO;
758 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
759 WM1811_JACKDET_MODE_MASK, mode);
762 static void active_reference(struct snd_soc_codec *codec)
764 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
766 mutex_lock(&wm8994->accdet_lock);
768 wm8994->active_refcount++;
770 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
771 wm8994->active_refcount);
773 /* If we're using jack detection go into audio mode */
774 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
776 mutex_unlock(&wm8994->accdet_lock);
779 static void active_dereference(struct snd_soc_codec *codec)
781 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
784 mutex_lock(&wm8994->accdet_lock);
786 wm8994->active_refcount--;
788 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
789 wm8994->active_refcount);
791 if (wm8994->active_refcount == 0) {
792 /* Go into appropriate detection only mode */
793 if (wm8994->jack_mic || wm8994->mic_detecting)
794 mode = WM1811_JACKDET_MODE_MIC;
796 mode = WM1811_JACKDET_MODE_JACK;
798 wm1811_jackdet_set_mode(codec, mode);
801 mutex_unlock(&wm8994->accdet_lock);
804 static int clk_sys_event(struct snd_soc_dapm_widget *w,
805 struct snd_kcontrol *kcontrol, int event)
807 struct snd_soc_codec *codec = w->codec;
808 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
811 case SND_SOC_DAPM_PRE_PMU:
812 return configure_clock(codec);
814 case SND_SOC_DAPM_POST_PMU:
816 * JACKDET won't run until we start the clock and it
817 * only reports deltas, make sure we notify the state
818 * up the stack on startup. Use a *very* generous
819 * timeout for paranoia, there's no urgency and we
820 * don't want false reports.
822 if (wm8994->jackdet && !wm8994->clk_has_run) {
823 schedule_delayed_work(&wm8994->jackdet_bootstrap,
824 msecs_to_jiffies(1000));
825 wm8994->clk_has_run = true;
829 case SND_SOC_DAPM_POST_PMD:
830 configure_clock(codec);
837 static void vmid_reference(struct snd_soc_codec *codec)
839 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
841 pm_runtime_get_sync(codec->dev);
843 wm8994->vmid_refcount++;
845 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
846 wm8994->vmid_refcount);
848 if (wm8994->vmid_refcount == 1) {
849 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
850 WM8994_LINEOUT1_DISCH |
851 WM8994_LINEOUT2_DISCH, 0);
853 wm_hubs_vmid_ena(codec);
855 switch (wm8994->vmid_mode) {
857 WARN_ON(NULL == "Invalid VMID mode");
858 case WM8994_VMID_NORMAL:
859 /* Startup bias, VMID ramp & buffer */
860 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
863 WM8994_STARTUP_BIAS_ENA |
864 WM8994_VMID_BUF_ENA |
865 WM8994_VMID_RAMP_MASK,
867 WM8994_STARTUP_BIAS_ENA |
868 WM8994_VMID_BUF_ENA |
869 (0x2 << WM8994_VMID_RAMP_SHIFT));
871 /* Main bias enable, VMID=2x40k */
872 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
874 WM8994_VMID_SEL_MASK,
875 WM8994_BIAS_ENA | 0x2);
879 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
880 WM8994_VMID_RAMP_MASK |
885 case WM8994_VMID_FORCE:
886 /* Startup bias, slow VMID ramp & buffer */
887 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
890 WM8994_STARTUP_BIAS_ENA |
891 WM8994_VMID_BUF_ENA |
892 WM8994_VMID_RAMP_MASK,
894 WM8994_STARTUP_BIAS_ENA |
895 WM8994_VMID_BUF_ENA |
896 (0x2 << WM8994_VMID_RAMP_SHIFT));
898 /* Main bias enable, VMID=2x40k */
899 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
901 WM8994_VMID_SEL_MASK,
902 WM8994_BIAS_ENA | 0x2);
906 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
907 WM8994_VMID_RAMP_MASK |
915 static void vmid_dereference(struct snd_soc_codec *codec)
917 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
919 wm8994->vmid_refcount--;
921 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
922 wm8994->vmid_refcount);
924 if (wm8994->vmid_refcount == 0) {
925 if (wm8994->hubs.lineout1_se)
926 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
927 WM8994_LINEOUT1N_ENA |
928 WM8994_LINEOUT1P_ENA,
929 WM8994_LINEOUT1N_ENA |
930 WM8994_LINEOUT1P_ENA);
932 if (wm8994->hubs.lineout2_se)
933 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
934 WM8994_LINEOUT2N_ENA |
935 WM8994_LINEOUT2P_ENA,
936 WM8994_LINEOUT2N_ENA |
937 WM8994_LINEOUT2P_ENA);
939 /* Start discharging VMID */
940 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
946 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
947 WM8994_VMID_SEL_MASK, 0);
951 /* Active discharge */
952 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
953 WM8994_LINEOUT1_DISCH |
954 WM8994_LINEOUT2_DISCH,
955 WM8994_LINEOUT1_DISCH |
956 WM8994_LINEOUT2_DISCH);
958 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
959 WM8994_LINEOUT1N_ENA |
960 WM8994_LINEOUT1P_ENA |
961 WM8994_LINEOUT2N_ENA |
962 WM8994_LINEOUT2P_ENA, 0);
964 /* Switch off startup biases */
965 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
967 WM8994_STARTUP_BIAS_ENA |
968 WM8994_VMID_BUF_ENA |
969 WM8994_VMID_RAMP_MASK, 0);
971 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
972 WM8994_VMID_SEL_MASK, 0);
975 pm_runtime_put(codec->dev);
978 static int vmid_event(struct snd_soc_dapm_widget *w,
979 struct snd_kcontrol *kcontrol, int event)
981 struct snd_soc_codec *codec = w->codec;
984 case SND_SOC_DAPM_PRE_PMU:
985 vmid_reference(codec);
988 case SND_SOC_DAPM_POST_PMD:
989 vmid_dereference(codec);
996 static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
998 int source = 0; /* GCC flow analysis can't track enable */
1001 /* We also need the same AIF source for L/R and only one path */
1002 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1004 case WM8994_AIF2DACL_TO_DAC1L:
1005 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1006 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1008 case WM8994_AIF1DAC2L_TO_DAC1L:
1009 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1010 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1012 case WM8994_AIF1DAC1L_TO_DAC1L:
1013 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1014 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1017 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1021 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1023 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1027 /* Set the source up */
1028 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1029 WM8994_CP_DYN_SRC_SEL_MASK, source);
1034 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1035 struct snd_kcontrol *kcontrol, int event)
1037 struct snd_soc_codec *codec = w->codec;
1038 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1039 struct wm8994 *control = wm8994->wm8994;
1040 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1046 switch (control->type) {
1049 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1056 case SND_SOC_DAPM_PRE_PMU:
1057 /* Don't enable timeslot 2 if not in use */
1058 if (wm8994->channels[0] <= 2)
1059 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1061 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1062 if ((val & WM8994_AIF1ADCL_SRC) &&
1063 (val & WM8994_AIF1ADCR_SRC))
1064 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1065 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1066 !(val & WM8994_AIF1ADCR_SRC))
1067 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1069 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1070 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1072 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1073 if ((val & WM8994_AIF1DACL_SRC) &&
1074 (val & WM8994_AIF1DACR_SRC))
1075 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1076 else if (!(val & WM8994_AIF1DACL_SRC) &&
1077 !(val & WM8994_AIF1DACR_SRC))
1078 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1080 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1081 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1083 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1085 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1087 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1088 WM8994_AIF1DSPCLK_ENA |
1089 WM8994_SYSDSPCLK_ENA,
1090 WM8994_AIF1DSPCLK_ENA |
1091 WM8994_SYSDSPCLK_ENA);
1092 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1093 WM8994_AIF1ADC1R_ENA |
1094 WM8994_AIF1ADC1L_ENA |
1095 WM8994_AIF1ADC2R_ENA |
1096 WM8994_AIF1ADC2L_ENA);
1097 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1098 WM8994_AIF1DAC1R_ENA |
1099 WM8994_AIF1DAC1L_ENA |
1100 WM8994_AIF1DAC2R_ENA |
1101 WM8994_AIF1DAC2L_ENA);
1104 case SND_SOC_DAPM_POST_PMU:
1105 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1106 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1108 wm8994_vu_bits[i].reg));
1111 case SND_SOC_DAPM_PRE_PMD:
1112 case SND_SOC_DAPM_POST_PMD:
1113 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1115 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1118 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1119 if (val & WM8994_AIF2DSPCLK_ENA)
1120 val = WM8994_SYSDSPCLK_ENA;
1123 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1124 WM8994_SYSDSPCLK_ENA |
1125 WM8994_AIF1DSPCLK_ENA, val);
1132 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1133 struct snd_kcontrol *kcontrol, int event)
1135 struct snd_soc_codec *codec = w->codec;
1142 case SND_SOC_DAPM_PRE_PMU:
1143 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1144 if ((val & WM8994_AIF2ADCL_SRC) &&
1145 (val & WM8994_AIF2ADCR_SRC))
1146 adc = WM8994_AIF2ADCR_ENA;
1147 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1148 !(val & WM8994_AIF2ADCR_SRC))
1149 adc = WM8994_AIF2ADCL_ENA;
1151 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1154 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1155 if ((val & WM8994_AIF2DACL_SRC) &&
1156 (val & WM8994_AIF2DACR_SRC))
1157 dac = WM8994_AIF2DACR_ENA;
1158 else if (!(val & WM8994_AIF2DACL_SRC) &&
1159 !(val & WM8994_AIF2DACR_SRC))
1160 dac = WM8994_AIF2DACL_ENA;
1162 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1164 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1165 WM8994_AIF2ADCL_ENA |
1166 WM8994_AIF2ADCR_ENA, adc);
1167 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1168 WM8994_AIF2DACL_ENA |
1169 WM8994_AIF2DACR_ENA, dac);
1170 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1171 WM8994_AIF2DSPCLK_ENA |
1172 WM8994_SYSDSPCLK_ENA,
1173 WM8994_AIF2DSPCLK_ENA |
1174 WM8994_SYSDSPCLK_ENA);
1175 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1176 WM8994_AIF2ADCL_ENA |
1177 WM8994_AIF2ADCR_ENA,
1178 WM8994_AIF2ADCL_ENA |
1179 WM8994_AIF2ADCR_ENA);
1180 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1181 WM8994_AIF2DACL_ENA |
1182 WM8994_AIF2DACR_ENA,
1183 WM8994_AIF2DACL_ENA |
1184 WM8994_AIF2DACR_ENA);
1187 case SND_SOC_DAPM_POST_PMU:
1188 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1189 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1191 wm8994_vu_bits[i].reg));
1194 case SND_SOC_DAPM_PRE_PMD:
1195 case SND_SOC_DAPM_POST_PMD:
1196 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1197 WM8994_AIF2DACL_ENA |
1198 WM8994_AIF2DACR_ENA, 0);
1199 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1200 WM8994_AIF2ADCL_ENA |
1201 WM8994_AIF2ADCR_ENA, 0);
1203 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1204 if (val & WM8994_AIF1DSPCLK_ENA)
1205 val = WM8994_SYSDSPCLK_ENA;
1208 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1209 WM8994_SYSDSPCLK_ENA |
1210 WM8994_AIF2DSPCLK_ENA, val);
1217 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1218 struct snd_kcontrol *kcontrol, int event)
1220 struct snd_soc_codec *codec = w->codec;
1221 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1224 case SND_SOC_DAPM_PRE_PMU:
1225 wm8994->aif1clk_enable = 1;
1227 case SND_SOC_DAPM_POST_PMD:
1228 wm8994->aif1clk_disable = 1;
1235 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1236 struct snd_kcontrol *kcontrol, int event)
1238 struct snd_soc_codec *codec = w->codec;
1239 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1242 case SND_SOC_DAPM_PRE_PMU:
1243 wm8994->aif2clk_enable = 1;
1245 case SND_SOC_DAPM_POST_PMD:
1246 wm8994->aif2clk_disable = 1;
1253 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1254 struct snd_kcontrol *kcontrol, int event)
1256 struct snd_soc_codec *codec = w->codec;
1257 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1260 case SND_SOC_DAPM_PRE_PMU:
1261 if (wm8994->aif1clk_enable) {
1262 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1263 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1264 WM8994_AIF1CLK_ENA_MASK,
1265 WM8994_AIF1CLK_ENA);
1266 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1267 wm8994->aif1clk_enable = 0;
1269 if (wm8994->aif2clk_enable) {
1270 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1271 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1272 WM8994_AIF2CLK_ENA_MASK,
1273 WM8994_AIF2CLK_ENA);
1274 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1275 wm8994->aif2clk_enable = 0;
1280 /* We may also have postponed startup of DSP, handle that. */
1281 wm8958_aif_ev(w, kcontrol, event);
1286 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1287 struct snd_kcontrol *kcontrol, int event)
1289 struct snd_soc_codec *codec = w->codec;
1290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1293 case SND_SOC_DAPM_POST_PMD:
1294 if (wm8994->aif1clk_disable) {
1295 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1296 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1297 WM8994_AIF1CLK_ENA_MASK, 0);
1298 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1299 wm8994->aif1clk_disable = 0;
1301 if (wm8994->aif2clk_disable) {
1302 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1303 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1304 WM8994_AIF2CLK_ENA_MASK, 0);
1305 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1306 wm8994->aif2clk_disable = 0;
1314 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1315 struct snd_kcontrol *kcontrol, int event)
1317 late_enable_ev(w, kcontrol, event);
1321 static int micbias_ev(struct snd_soc_dapm_widget *w,
1322 struct snd_kcontrol *kcontrol, int event)
1324 late_enable_ev(w, kcontrol, event);
1328 static int dac_ev(struct snd_soc_dapm_widget *w,
1329 struct snd_kcontrol *kcontrol, int event)
1331 struct snd_soc_codec *codec = w->codec;
1332 unsigned int mask = 1 << w->shift;
1334 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1339 static const char *adc_mux_text[] = {
1344 static const struct soc_enum adc_enum =
1345 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1347 static const struct snd_kcontrol_new adcl_mux =
1348 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1350 static const struct snd_kcontrol_new adcr_mux =
1351 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1353 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1354 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1355 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1356 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1357 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1358 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1361 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1362 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1363 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1364 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1365 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1366 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1369 /* Debugging; dump chip status after DAPM transitions */
1370 static int post_ev(struct snd_soc_dapm_widget *w,
1371 struct snd_kcontrol *kcontrol, int event)
1373 struct snd_soc_codec *codec = w->codec;
1374 dev_dbg(codec->dev, "SRC status: %x\n",
1376 WM8994_RATE_STATUS));
1380 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1381 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1383 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1387 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1388 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1390 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1394 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1395 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1397 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1401 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1402 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1404 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1408 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1409 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1411 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1413 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1415 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1417 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1421 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1422 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1424 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1426 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1428 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1430 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1434 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1435 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1436 .info = snd_soc_info_volsw, \
1437 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1438 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1440 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1441 struct snd_ctl_elem_value *ucontrol)
1443 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1444 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1445 struct snd_soc_codec *codec = w->codec;
1448 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1450 wm_hubs_update_class_w(codec);
1455 static const struct snd_kcontrol_new dac1l_mix[] = {
1456 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1458 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1460 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1462 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1464 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1468 static const struct snd_kcontrol_new dac1r_mix[] = {
1469 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1471 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1473 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1475 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1477 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1481 static const char *sidetone_text[] = {
1482 "ADC/DMIC1", "DMIC2",
1485 static const struct soc_enum sidetone1_enum =
1486 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1488 static const struct snd_kcontrol_new sidetone1_mux =
1489 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1491 static const struct soc_enum sidetone2_enum =
1492 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1494 static const struct snd_kcontrol_new sidetone2_mux =
1495 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1497 static const char *aif1dac_text[] = {
1498 "AIF1DACDAT", "AIF3DACDAT",
1501 static const struct soc_enum aif1dac_enum =
1502 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1504 static const struct snd_kcontrol_new aif1dac_mux =
1505 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1507 static const char *aif2dac_text[] = {
1508 "AIF2DACDAT", "AIF3DACDAT",
1511 static const struct soc_enum aif2dac_enum =
1512 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1514 static const struct snd_kcontrol_new aif2dac_mux =
1515 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1517 static const char *aif2adc_text[] = {
1518 "AIF2ADCDAT", "AIF3DACDAT",
1521 static const struct soc_enum aif2adc_enum =
1522 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1524 static const struct snd_kcontrol_new aif2adc_mux =
1525 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1527 static const char *aif3adc_text[] = {
1528 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1531 static const struct soc_enum wm8994_aif3adc_enum =
1532 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1534 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1535 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1537 static const struct soc_enum wm8958_aif3adc_enum =
1538 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1540 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1541 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1543 static const char *mono_pcm_out_text[] = {
1544 "None", "AIF2ADCL", "AIF2ADCR",
1547 static const struct soc_enum mono_pcm_out_enum =
1548 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1550 static const struct snd_kcontrol_new mono_pcm_out_mux =
1551 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1553 static const char *aif2dac_src_text[] = {
1557 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1558 static const struct soc_enum aif2dacl_src_enum =
1559 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1561 static const struct snd_kcontrol_new aif2dacl_src_mux =
1562 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1564 static const struct soc_enum aif2dacr_src_enum =
1565 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1567 static const struct snd_kcontrol_new aif2dacr_src_mux =
1568 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1570 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1571 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1572 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1573 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1574 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1576 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1577 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1578 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1579 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1580 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1581 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1582 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1583 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1584 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1585 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1587 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1588 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1589 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1590 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1591 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1592 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1593 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1594 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1595 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1596 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1598 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1601 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1602 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1603 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1604 SND_SOC_DAPM_PRE_PMD),
1605 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1606 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1607 SND_SOC_DAPM_PRE_PMD),
1608 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1609 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1610 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1611 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1612 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1613 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1614 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1617 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1618 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1619 dac_ev, SND_SOC_DAPM_PRE_PMU),
1620 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1621 dac_ev, SND_SOC_DAPM_PRE_PMU),
1622 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1623 dac_ev, SND_SOC_DAPM_PRE_PMU),
1624 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1625 dac_ev, SND_SOC_DAPM_PRE_PMU),
1628 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1629 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1630 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1631 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1632 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1635 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1636 SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1637 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1638 SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1639 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1642 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1643 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1644 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1647 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1648 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1649 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1650 SND_SOC_DAPM_INPUT("Clock"),
1652 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1653 SND_SOC_DAPM_PRE_PMU),
1654 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1655 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1657 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1658 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1659 SND_SOC_DAPM_PRE_PMD),
1661 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1662 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1663 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1665 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1666 0, SND_SOC_NOPM, 9, 0),
1667 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1668 0, SND_SOC_NOPM, 8, 0),
1669 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1670 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1671 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1672 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1673 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1674 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1676 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1677 0, SND_SOC_NOPM, 11, 0),
1678 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1679 0, SND_SOC_NOPM, 10, 0),
1680 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1681 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1682 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1683 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1684 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1685 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1687 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1688 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1689 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1690 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1692 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1693 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1694 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1695 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1697 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1698 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1699 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1700 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1702 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1703 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1705 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1706 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1707 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1708 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1710 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1711 SND_SOC_NOPM, 13, 0),
1712 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1713 SND_SOC_NOPM, 12, 0),
1714 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1715 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1716 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1717 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1718 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1719 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1721 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1722 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1723 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1724 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1726 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1727 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1728 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1730 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1731 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1733 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1735 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1736 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1737 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1738 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1740 /* Power is done with the muxes since the ADC power also controls the
1741 * downsampling chain, the chip will automatically manage the analogue
1742 * specific portions.
1744 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1745 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1747 SND_SOC_DAPM_POST("Debug log", post_ev),
1750 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1751 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1754 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1755 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1756 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1757 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1758 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1759 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1762 static const struct snd_soc_dapm_route intercon[] = {
1763 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1764 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1766 { "DSP1CLK", NULL, "CLK_SYS" },
1767 { "DSP2CLK", NULL, "CLK_SYS" },
1768 { "DSPINTCLK", NULL, "CLK_SYS" },
1770 { "AIF1ADC1L", NULL, "AIF1CLK" },
1771 { "AIF1ADC1L", NULL, "DSP1CLK" },
1772 { "AIF1ADC1R", NULL, "AIF1CLK" },
1773 { "AIF1ADC1R", NULL, "DSP1CLK" },
1774 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1776 { "AIF1DAC1L", NULL, "AIF1CLK" },
1777 { "AIF1DAC1L", NULL, "DSP1CLK" },
1778 { "AIF1DAC1R", NULL, "AIF1CLK" },
1779 { "AIF1DAC1R", NULL, "DSP1CLK" },
1780 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1782 { "AIF1ADC2L", NULL, "AIF1CLK" },
1783 { "AIF1ADC2L", NULL, "DSP1CLK" },
1784 { "AIF1ADC2R", NULL, "AIF1CLK" },
1785 { "AIF1ADC2R", NULL, "DSP1CLK" },
1786 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1788 { "AIF1DAC2L", NULL, "AIF1CLK" },
1789 { "AIF1DAC2L", NULL, "DSP1CLK" },
1790 { "AIF1DAC2R", NULL, "AIF1CLK" },
1791 { "AIF1DAC2R", NULL, "DSP1CLK" },
1792 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1794 { "AIF2ADCL", NULL, "AIF2CLK" },
1795 { "AIF2ADCL", NULL, "DSP2CLK" },
1796 { "AIF2ADCR", NULL, "AIF2CLK" },
1797 { "AIF2ADCR", NULL, "DSP2CLK" },
1798 { "AIF2ADCR", NULL, "DSPINTCLK" },
1800 { "AIF2DACL", NULL, "AIF2CLK" },
1801 { "AIF2DACL", NULL, "DSP2CLK" },
1802 { "AIF2DACR", NULL, "AIF2CLK" },
1803 { "AIF2DACR", NULL, "DSP2CLK" },
1804 { "AIF2DACR", NULL, "DSPINTCLK" },
1806 { "DMIC1L", NULL, "DMIC1DAT" },
1807 { "DMIC1L", NULL, "CLK_SYS" },
1808 { "DMIC1R", NULL, "DMIC1DAT" },
1809 { "DMIC1R", NULL, "CLK_SYS" },
1810 { "DMIC2L", NULL, "DMIC2DAT" },
1811 { "DMIC2L", NULL, "CLK_SYS" },
1812 { "DMIC2R", NULL, "DMIC2DAT" },
1813 { "DMIC2R", NULL, "CLK_SYS" },
1815 { "ADCL", NULL, "AIF1CLK" },
1816 { "ADCL", NULL, "DSP1CLK" },
1817 { "ADCL", NULL, "DSPINTCLK" },
1819 { "ADCR", NULL, "AIF1CLK" },
1820 { "ADCR", NULL, "DSP1CLK" },
1821 { "ADCR", NULL, "DSPINTCLK" },
1823 { "ADCL Mux", "ADC", "ADCL" },
1824 { "ADCL Mux", "DMIC", "DMIC1L" },
1825 { "ADCR Mux", "ADC", "ADCR" },
1826 { "ADCR Mux", "DMIC", "DMIC1R" },
1828 { "DAC1L", NULL, "AIF1CLK" },
1829 { "DAC1L", NULL, "DSP1CLK" },
1830 { "DAC1L", NULL, "DSPINTCLK" },
1832 { "DAC1R", NULL, "AIF1CLK" },
1833 { "DAC1R", NULL, "DSP1CLK" },
1834 { "DAC1R", NULL, "DSPINTCLK" },
1836 { "DAC2L", NULL, "AIF2CLK" },
1837 { "DAC2L", NULL, "DSP2CLK" },
1838 { "DAC2L", NULL, "DSPINTCLK" },
1840 { "DAC2R", NULL, "AIF2DACR" },
1841 { "DAC2R", NULL, "AIF2CLK" },
1842 { "DAC2R", NULL, "DSP2CLK" },
1843 { "DAC2R", NULL, "DSPINTCLK" },
1845 { "TOCLK", NULL, "CLK_SYS" },
1847 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1848 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1849 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1851 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1852 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1853 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1856 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1857 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1858 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1860 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1861 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1862 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1864 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1865 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1866 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1868 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1869 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1870 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1872 /* Pin level routing for AIF3 */
1873 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1874 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1875 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1876 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1878 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1879 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1880 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1881 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1882 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1883 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1884 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1887 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1888 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1889 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1890 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1891 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1893 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1894 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1895 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1896 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1897 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1899 /* DAC2/AIF2 outputs */
1900 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1901 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1902 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1903 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1904 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1905 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1907 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1908 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1909 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1910 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1911 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1912 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1914 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1915 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1916 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1917 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1919 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1922 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1923 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1924 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1925 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1926 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1927 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1928 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1929 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1932 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1933 { "Left Sidetone", "DMIC2", "DMIC2L" },
1934 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1935 { "Right Sidetone", "DMIC2", "DMIC2R" },
1938 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1939 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1941 { "SPKL", "DAC1 Switch", "DAC1L" },
1942 { "SPKL", "DAC2 Switch", "DAC2L" },
1944 { "SPKR", "DAC1 Switch", "DAC1R" },
1945 { "SPKR", "DAC2 Switch", "DAC2R" },
1947 { "Left Headphone Mux", "DAC", "DAC1L" },
1948 { "Right Headphone Mux", "DAC", "DAC1R" },
1951 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1952 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1953 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1954 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1955 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1956 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1957 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1958 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1959 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1962 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1963 { "DAC1L", NULL, "DAC1L Mixer" },
1964 { "DAC1R", NULL, "DAC1R Mixer" },
1965 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1966 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1969 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1970 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1971 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1972 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1973 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1974 { "MICBIAS1", NULL, "CLK_SYS" },
1975 { "MICBIAS1", NULL, "MICBIAS Supply" },
1976 { "MICBIAS2", NULL, "CLK_SYS" },
1977 { "MICBIAS2", NULL, "MICBIAS Supply" },
1980 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1981 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1982 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1983 { "MICBIAS1", NULL, "VMID" },
1984 { "MICBIAS2", NULL, "VMID" },
1987 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1988 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1989 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1991 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1992 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1993 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1994 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1996 { "AIF3DACDAT", NULL, "AIF3" },
1997 { "AIF3ADCDAT", NULL, "AIF3" },
1999 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2000 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2002 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2005 /* The size in bits of the FLL divide multiplied by 10
2006 * to allow rounding later */
2007 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2017 static int wm8994_get_fll_config(struct fll_div *fll,
2018 int freq_in, int freq_out)
2021 unsigned int K, Ndiv, Nmod;
2023 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2025 /* Scale the input frequency down to <= 13.5MHz */
2026 fll->clk_ref_div = 0;
2027 while (freq_in > 13500000) {
2031 if (fll->clk_ref_div > 3)
2034 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2036 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2038 while (freq_out * (fll->outdiv + 1) < 90000000) {
2040 if (fll->outdiv > 63)
2043 freq_out *= fll->outdiv + 1;
2044 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2046 if (freq_in > 1000000) {
2047 fll->fll_fratio = 0;
2048 } else if (freq_in > 256000) {
2049 fll->fll_fratio = 1;
2051 } else if (freq_in > 128000) {
2052 fll->fll_fratio = 2;
2054 } else if (freq_in > 64000) {
2055 fll->fll_fratio = 3;
2058 fll->fll_fratio = 4;
2061 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2063 /* Now, calculate N.K */
2064 Ndiv = freq_out / freq_in;
2067 Nmod = freq_out % freq_in;
2068 pr_debug("Nmod=%d\n", Nmod);
2070 /* Calculate fractional part - scale up so we can round. */
2071 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2073 do_div(Kpart, freq_in);
2075 K = Kpart & 0xFFFFFFFF;
2080 /* Move down to proper range now rounding is done */
2083 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2088 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2089 unsigned int freq_in, unsigned int freq_out)
2091 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2092 struct wm8994 *control = wm8994->wm8994;
2093 int reg_offset, ret;
2095 u16 reg, clk1, aif_reg, aif_src;
2096 unsigned long timeout;
2114 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2115 was_enabled = reg & WM8994_FLL1_ENA;
2119 /* Allow no source specification when stopping */
2122 src = wm8994->fll[id].src;
2124 case WM8994_FLL_SRC_MCLK1:
2125 case WM8994_FLL_SRC_MCLK2:
2126 case WM8994_FLL_SRC_LRCLK:
2127 case WM8994_FLL_SRC_BCLK:
2129 case WM8994_FLL_SRC_INTERNAL:
2131 freq_out = 12000000;
2137 /* Are we changing anything? */
2138 if (wm8994->fll[id].src == src &&
2139 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2142 /* If we're stopping the FLL redo the old config - no
2143 * registers will actually be written but we avoid GCC flow
2144 * analysis bugs spewing warnings.
2147 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2149 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2150 wm8994->fll[id].out);
2154 /* Make sure that we're not providing SYSCLK right now */
2155 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2156 if (clk1 & WM8994_SYSCLK_SRC)
2157 aif_reg = WM8994_AIF2_CLOCKING_1;
2159 aif_reg = WM8994_AIF1_CLOCKING_1;
2160 reg = snd_soc_read(codec, aif_reg);
2162 if ((reg & WM8994_AIF1CLK_ENA) &&
2163 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2164 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2169 /* We always need to disable the FLL while reconfiguring */
2170 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2171 WM8994_FLL1_ENA, 0);
2173 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2174 freq_in == freq_out && freq_out) {
2175 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2176 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2177 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2181 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2182 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2183 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2184 WM8994_FLL1_OUTDIV_MASK |
2185 WM8994_FLL1_FRATIO_MASK, reg);
2187 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2188 WM8994_FLL1_K_MASK, fll.k);
2190 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2192 fll.n << WM8994_FLL1_N_SHIFT);
2194 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2195 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2196 WM8994_FLL1_REFCLK_DIV_MASK |
2197 WM8994_FLL1_REFCLK_SRC_MASK,
2198 ((src == WM8994_FLL_SRC_INTERNAL)
2199 << WM8994_FLL1_FRC_NCO_SHIFT) |
2200 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2203 /* Clear any pending completion from a previous failure */
2204 try_wait_for_completion(&wm8994->fll_locked[id]);
2206 /* Enable (with fractional mode if required) */
2208 /* Enable VMID if we need it */
2210 active_reference(codec);
2212 switch (control->type) {
2214 vmid_reference(codec);
2217 if (control->revision < 1)
2218 vmid_reference(codec);
2225 reg = WM8994_FLL1_ENA;
2228 reg |= WM8994_FLL1_FRAC;
2229 if (src == WM8994_FLL_SRC_INTERNAL)
2230 reg |= WM8994_FLL1_OSC_ENA;
2232 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2233 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2234 WM8994_FLL1_FRAC, reg);
2236 if (wm8994->fll_locked_irq) {
2237 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2238 msecs_to_jiffies(10));
2240 dev_warn(codec->dev,
2241 "Timed out waiting for FLL lock\n");
2247 switch (control->type) {
2249 vmid_dereference(codec);
2252 if (control->revision < 1)
2253 vmid_dereference(codec);
2259 active_dereference(codec);
2264 wm8994->fll[id].in = freq_in;
2265 wm8994->fll[id].out = freq_out;
2266 wm8994->fll[id].src = src;
2268 configure_clock(codec);
2271 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2274 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2275 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2277 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2278 & WM8994_AIF1CLK_RATE_MASK;
2279 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2280 & WM8994_AIF1CLK_RATE_MASK;
2282 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2283 WM8994_AIF1CLK_RATE_MASK, 0x1);
2284 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2285 WM8994_AIF2CLK_RATE_MASK, 0x1);
2286 } else if (wm8994->aifdiv[0]) {
2287 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2288 WM8994_AIF1CLK_RATE_MASK,
2290 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2291 WM8994_AIF2CLK_RATE_MASK,
2294 wm8994->aifdiv[0] = 0;
2295 wm8994->aifdiv[1] = 0;
2301 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2303 struct completion *completion = data;
2305 complete(completion);
2310 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2312 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2313 unsigned int freq_in, unsigned int freq_out)
2315 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2318 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2319 int clk_id, unsigned int freq, int dir)
2321 struct snd_soc_codec *codec = dai->codec;
2322 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2331 /* AIF3 shares clocking with AIF1/2 */
2336 case WM8994_SYSCLK_MCLK1:
2337 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2338 wm8994->mclk[0] = freq;
2339 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2343 case WM8994_SYSCLK_MCLK2:
2344 /* TODO: Set GPIO AF */
2345 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2346 wm8994->mclk[1] = freq;
2347 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2351 case WM8994_SYSCLK_FLL1:
2352 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2353 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2356 case WM8994_SYSCLK_FLL2:
2357 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2358 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2361 case WM8994_SYSCLK_OPCLK:
2362 /* Special case - a division (times 10) is given and
2363 * no effect on main clocking.
2366 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2367 if (opclk_divs[i] == freq)
2369 if (i == ARRAY_SIZE(opclk_divs))
2371 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2372 WM8994_OPCLK_DIV_MASK, i);
2373 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2374 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2376 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2377 WM8994_OPCLK_ENA, 0);
2384 configure_clock(codec);
2387 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2390 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2391 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2393 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2394 & WM8994_AIF1CLK_RATE_MASK;
2395 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2396 & WM8994_AIF1CLK_RATE_MASK;
2398 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2399 WM8994_AIF1CLK_RATE_MASK, 0x1);
2400 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2401 WM8994_AIF2CLK_RATE_MASK, 0x1);
2402 } else if (wm8994->aifdiv[0]) {
2403 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2404 WM8994_AIF1CLK_RATE_MASK,
2406 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2407 WM8994_AIF2CLK_RATE_MASK,
2410 wm8994->aifdiv[0] = 0;
2411 wm8994->aifdiv[1] = 0;
2417 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2418 enum snd_soc_bias_level level)
2420 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2421 struct wm8994 *control = wm8994->wm8994;
2423 wm_hubs_set_bias_level(codec, level);
2426 case SND_SOC_BIAS_ON:
2429 case SND_SOC_BIAS_PREPARE:
2430 /* MICBIAS into regulating mode */
2431 switch (control->type) {
2434 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2435 WM8958_MICB1_MODE, 0);
2436 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2437 WM8958_MICB2_MODE, 0);
2443 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2444 active_reference(codec);
2447 case SND_SOC_BIAS_STANDBY:
2448 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2449 switch (control->type) {
2451 if (control->revision == 0) {
2452 /* Optimise performance for rev A */
2453 snd_soc_update_bits(codec,
2454 WM8958_CHARGE_PUMP_2,
2464 /* Discharge LINEOUT1 & 2 */
2465 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2466 WM8994_LINEOUT1_DISCH |
2467 WM8994_LINEOUT2_DISCH,
2468 WM8994_LINEOUT1_DISCH |
2469 WM8994_LINEOUT2_DISCH);
2472 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2473 active_dereference(codec);
2475 /* MICBIAS into bypass mode on newer devices */
2476 switch (control->type) {
2479 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2482 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2491 case SND_SOC_BIAS_OFF:
2492 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2493 wm8994->cur_fw = NULL;
2497 codec->dapm.bias_level = level;
2502 int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2504 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2507 case WM8994_VMID_NORMAL:
2508 if (wm8994->hubs.lineout1_se) {
2509 snd_soc_dapm_disable_pin(&codec->dapm,
2510 "LINEOUT1N Driver");
2511 snd_soc_dapm_disable_pin(&codec->dapm,
2512 "LINEOUT1P Driver");
2514 if (wm8994->hubs.lineout2_se) {
2515 snd_soc_dapm_disable_pin(&codec->dapm,
2516 "LINEOUT2N Driver");
2517 snd_soc_dapm_disable_pin(&codec->dapm,
2518 "LINEOUT2P Driver");
2521 /* Do the sync with the old mode to allow it to clean up */
2522 snd_soc_dapm_sync(&codec->dapm);
2523 wm8994->vmid_mode = mode;
2526 case WM8994_VMID_FORCE:
2527 if (wm8994->hubs.lineout1_se) {
2528 snd_soc_dapm_force_enable_pin(&codec->dapm,
2529 "LINEOUT1N Driver");
2530 snd_soc_dapm_force_enable_pin(&codec->dapm,
2531 "LINEOUT1P Driver");
2533 if (wm8994->hubs.lineout2_se) {
2534 snd_soc_dapm_force_enable_pin(&codec->dapm,
2535 "LINEOUT2N Driver");
2536 snd_soc_dapm_force_enable_pin(&codec->dapm,
2537 "LINEOUT2P Driver");
2540 wm8994->vmid_mode = mode;
2541 snd_soc_dapm_sync(&codec->dapm);
2551 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2553 struct snd_soc_codec *codec = dai->codec;
2554 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2555 struct wm8994 *control = wm8994->wm8994;
2563 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2564 aif1_reg = WM8994_AIF1_CONTROL_1;
2567 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2568 aif1_reg = WM8994_AIF2_CONTROL_1;
2574 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2575 case SND_SOC_DAIFMT_CBS_CFS:
2577 case SND_SOC_DAIFMT_CBM_CFM:
2578 ms = WM8994_AIF1_MSTR;
2584 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2585 case SND_SOC_DAIFMT_DSP_B:
2586 aif1 |= WM8994_AIF1_LRCLK_INV;
2587 case SND_SOC_DAIFMT_DSP_A:
2590 case SND_SOC_DAIFMT_I2S:
2593 case SND_SOC_DAIFMT_RIGHT_J:
2595 case SND_SOC_DAIFMT_LEFT_J:
2602 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2603 case SND_SOC_DAIFMT_DSP_A:
2604 case SND_SOC_DAIFMT_DSP_B:
2605 /* frame inversion not valid for DSP modes */
2606 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2607 case SND_SOC_DAIFMT_NB_NF:
2609 case SND_SOC_DAIFMT_IB_NF:
2610 aif1 |= WM8994_AIF1_BCLK_INV;
2617 case SND_SOC_DAIFMT_I2S:
2618 case SND_SOC_DAIFMT_RIGHT_J:
2619 case SND_SOC_DAIFMT_LEFT_J:
2620 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2621 case SND_SOC_DAIFMT_NB_NF:
2623 case SND_SOC_DAIFMT_IB_IF:
2624 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2626 case SND_SOC_DAIFMT_IB_NF:
2627 aif1 |= WM8994_AIF1_BCLK_INV;
2629 case SND_SOC_DAIFMT_NB_IF:
2630 aif1 |= WM8994_AIF1_LRCLK_INV;
2640 /* The AIF2 format configuration needs to be mirrored to AIF3
2641 * on WM8958 if it's in use so just do it all the time. */
2642 switch (control->type) {
2646 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2647 WM8994_AIF1_LRCLK_INV |
2648 WM8958_AIF3_FMT_MASK, aif1);
2655 snd_soc_update_bits(codec, aif1_reg,
2656 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2657 WM8994_AIF1_FMT_MASK,
2659 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2681 static int fs_ratios[] = {
2682 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2685 static int bclk_divs[] = {
2686 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2687 640, 880, 960, 1280, 1760, 1920
2690 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2691 struct snd_pcm_hw_params *params,
2692 struct snd_soc_dai *dai)
2694 struct snd_soc_codec *codec = dai->codec;
2695 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2696 struct wm8994 *control = wm8994->wm8994;
2697 struct wm8994_pdata *pdata = &control->pdata;
2708 int id = dai->id - 1;
2710 int i, cur_val, best_val, bclk_rate, best;
2714 aif1_reg = WM8994_AIF1_CONTROL_1;
2715 aif2_reg = WM8994_AIF1_CONTROL_2;
2716 bclk_reg = WM8994_AIF1_BCLK;
2717 rate_reg = WM8994_AIF1_RATE;
2718 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2719 wm8994->lrclk_shared[0]) {
2720 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2722 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2723 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2727 aif1_reg = WM8994_AIF2_CONTROL_1;
2728 aif2_reg = WM8994_AIF2_CONTROL_2;
2729 bclk_reg = WM8994_AIF2_BCLK;
2730 rate_reg = WM8994_AIF2_RATE;
2731 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2732 wm8994->lrclk_shared[1]) {
2733 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2735 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2736 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2743 bclk_rate = params_rate(params);
2744 switch (params_format(params)) {
2745 case SNDRV_PCM_FORMAT_S16_LE:
2748 case SNDRV_PCM_FORMAT_S20_3LE:
2752 case SNDRV_PCM_FORMAT_S24_LE:
2756 case SNDRV_PCM_FORMAT_S32_LE:
2764 wm8994->channels[id] = params_channels(params);
2765 if (pdata->max_channels_clocked[id] &&
2766 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2767 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2768 pdata->max_channels_clocked[id], wm8994->channels[id]);
2769 wm8994->channels[id] = pdata->max_channels_clocked[id];
2772 switch (wm8994->channels[id]) {
2782 /* Try to find an appropriate sample rate; look for an exact match. */
2783 for (i = 0; i < ARRAY_SIZE(srs); i++)
2784 if (srs[i].rate == params_rate(params))
2786 if (i == ARRAY_SIZE(srs))
2788 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2790 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2791 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2792 dai->id, wm8994->aifclk[id], bclk_rate);
2794 if (wm8994->channels[id] == 1 &&
2795 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2796 aif2 |= WM8994_AIF1_MONO;
2798 if (wm8994->aifclk[id] == 0) {
2799 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2803 /* AIFCLK/fs ratio; look for a close match in either direction */
2805 best_val = abs((fs_ratios[0] * params_rate(params))
2806 - wm8994->aifclk[id]);
2807 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2808 cur_val = abs((fs_ratios[i] * params_rate(params))
2809 - wm8994->aifclk[id]);
2810 if (cur_val >= best_val)
2815 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2816 dai->id, fs_ratios[best]);
2819 /* We may not get quite the right frequency if using
2820 * approximate clocks so look for the closest match that is
2821 * higher than the target (we need to ensure that there enough
2822 * BCLKs to clock out the samples).
2825 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2826 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2827 if (cur_val < 0) /* BCLK table is sorted */
2831 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2832 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2833 bclk_divs[best], bclk_rate);
2834 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2836 lrclk = bclk_rate / params_rate(params);
2838 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2842 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2843 lrclk, bclk_rate / lrclk);
2845 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2846 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2847 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2848 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2850 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2851 WM8994_AIF1CLK_RATE_MASK, rate_val);
2853 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2856 wm8994->dac_rates[0] = params_rate(params);
2857 wm8994_set_retune_mobile(codec, 0);
2858 wm8994_set_retune_mobile(codec, 1);
2861 wm8994->dac_rates[1] = params_rate(params);
2862 wm8994_set_retune_mobile(codec, 2);
2870 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2871 struct snd_pcm_hw_params *params,
2872 struct snd_soc_dai *dai)
2874 struct snd_soc_codec *codec = dai->codec;
2875 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2876 struct wm8994 *control = wm8994->wm8994;
2882 switch (control->type) {
2885 aif1_reg = WM8958_AIF3_CONTROL_1;
2895 switch (params_format(params)) {
2896 case SNDRV_PCM_FORMAT_S16_LE:
2898 case SNDRV_PCM_FORMAT_S20_3LE:
2901 case SNDRV_PCM_FORMAT_S24_LE:
2904 case SNDRV_PCM_FORMAT_S32_LE:
2911 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2914 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2916 struct snd_soc_codec *codec = codec_dai->codec;
2920 switch (codec_dai->id) {
2922 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2925 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2932 reg = WM8994_AIF1DAC1_MUTE;
2936 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2941 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2943 struct snd_soc_codec *codec = codec_dai->codec;
2946 switch (codec_dai->id) {
2948 reg = WM8994_AIF1_MASTER_SLAVE;
2949 mask = WM8994_AIF1_TRI;
2952 reg = WM8994_AIF2_MASTER_SLAVE;
2953 mask = WM8994_AIF2_TRI;
2964 return snd_soc_update_bits(codec, reg, mask, val);
2967 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2969 struct snd_soc_codec *codec = dai->codec;
2971 /* Disable the pulls on the AIF if we're using it to save power. */
2972 snd_soc_update_bits(codec, WM8994_GPIO_3,
2973 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2974 snd_soc_update_bits(codec, WM8994_GPIO_4,
2975 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2976 snd_soc_update_bits(codec, WM8994_GPIO_5,
2977 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2982 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2984 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2985 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2987 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2988 .set_sysclk = wm8994_set_dai_sysclk,
2989 .set_fmt = wm8994_set_dai_fmt,
2990 .hw_params = wm8994_hw_params,
2991 .digital_mute = wm8994_aif_mute,
2992 .set_pll = wm8994_set_fll,
2993 .set_tristate = wm8994_set_tristate,
2996 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2997 .set_sysclk = wm8994_set_dai_sysclk,
2998 .set_fmt = wm8994_set_dai_fmt,
2999 .hw_params = wm8994_hw_params,
3000 .digital_mute = wm8994_aif_mute,
3001 .set_pll = wm8994_set_fll,
3002 .set_tristate = wm8994_set_tristate,
3005 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3006 .hw_params = wm8994_aif3_hw_params,
3009 static struct snd_soc_dai_driver wm8994_dai[] = {
3011 .name = "wm8994-aif1",
3014 .stream_name = "AIF1 Playback",
3017 .rates = WM8994_RATES,
3018 .formats = WM8994_FORMATS,
3022 .stream_name = "AIF1 Capture",
3025 .rates = WM8994_RATES,
3026 .formats = WM8994_FORMATS,
3029 .ops = &wm8994_aif1_dai_ops,
3032 .name = "wm8994-aif2",
3035 .stream_name = "AIF2 Playback",
3038 .rates = WM8994_RATES,
3039 .formats = WM8994_FORMATS,
3043 .stream_name = "AIF2 Capture",
3046 .rates = WM8994_RATES,
3047 .formats = WM8994_FORMATS,
3050 .probe = wm8994_aif2_probe,
3051 .ops = &wm8994_aif2_dai_ops,
3054 .name = "wm8994-aif3",
3057 .stream_name = "AIF3 Playback",
3060 .rates = WM8994_RATES,
3061 .formats = WM8994_FORMATS,
3065 .stream_name = "AIF3 Capture",
3068 .rates = WM8994_RATES,
3069 .formats = WM8994_FORMATS,
3072 .ops = &wm8994_aif3_dai_ops,
3077 static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3079 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3082 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3083 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3084 sizeof(struct wm8994_fll_config));
3085 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3087 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3091 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3096 static int wm8994_codec_resume(struct snd_soc_codec *codec)
3098 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3099 struct wm8994 *control = wm8994->wm8994;
3101 unsigned int val, mask;
3103 if (control->revision < 4) {
3104 /* force a HW read */
3105 ret = regmap_read(control->regmap,
3106 WM8994_POWER_MANAGEMENT_5, &val);
3108 /* modify the cache only */
3109 codec->cache_only = 1;
3110 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3111 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3113 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3115 codec->cache_only = 0;
3118 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3119 if (!wm8994->fll_suspend[i].out)
3122 ret = _wm8994_set_fll(codec, i + 1,
3123 wm8994->fll_suspend[i].src,
3124 wm8994->fll_suspend[i].in,
3125 wm8994->fll_suspend[i].out);
3127 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3134 #define wm8994_codec_suspend NULL
3135 #define wm8994_codec_resume NULL
3138 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3140 struct snd_soc_codec *codec = wm8994->hubs.codec;
3141 struct wm8994 *control = wm8994->wm8994;
3142 struct wm8994_pdata *pdata = &control->pdata;
3143 struct snd_kcontrol_new controls[] = {
3144 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3145 wm8994->retune_mobile_enum,
3146 wm8994_get_retune_mobile_enum,
3147 wm8994_put_retune_mobile_enum),
3148 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3149 wm8994->retune_mobile_enum,
3150 wm8994_get_retune_mobile_enum,
3151 wm8994_put_retune_mobile_enum),
3152 SOC_ENUM_EXT("AIF2 EQ Mode",
3153 wm8994->retune_mobile_enum,
3154 wm8994_get_retune_mobile_enum,
3155 wm8994_put_retune_mobile_enum),
3160 /* We need an array of texts for the enum API but the number
3161 * of texts is likely to be less than the number of
3162 * configurations due to the sample rate dependency of the
3163 * configurations. */
3164 wm8994->num_retune_mobile_texts = 0;
3165 wm8994->retune_mobile_texts = NULL;
3166 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3167 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3168 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3169 wm8994->retune_mobile_texts[j]) == 0)
3173 if (j != wm8994->num_retune_mobile_texts)
3176 /* Expand the array... */
3177 t = krealloc(wm8994->retune_mobile_texts,
3179 (wm8994->num_retune_mobile_texts + 1),
3184 /* ...store the new entry... */
3185 t[wm8994->num_retune_mobile_texts] =
3186 pdata->retune_mobile_cfgs[i].name;
3188 /* ...and remember the new version. */
3189 wm8994->num_retune_mobile_texts++;
3190 wm8994->retune_mobile_texts = t;
3193 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3194 wm8994->num_retune_mobile_texts);
3196 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3197 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3199 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3200 ARRAY_SIZE(controls));
3202 dev_err(wm8994->hubs.codec->dev,
3203 "Failed to add ReTune Mobile controls: %d\n", ret);
3206 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3208 struct snd_soc_codec *codec = wm8994->hubs.codec;
3209 struct wm8994 *control = wm8994->wm8994;
3210 struct wm8994_pdata *pdata = &control->pdata;
3216 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3217 pdata->lineout2_diff,
3224 pdata->micbias1_lvl,
3225 pdata->micbias2_lvl);
3227 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3229 if (pdata->num_drc_cfgs) {
3230 struct snd_kcontrol_new controls[] = {
3231 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3232 wm8994_get_drc_enum, wm8994_put_drc_enum),
3233 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3234 wm8994_get_drc_enum, wm8994_put_drc_enum),
3235 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3236 wm8994_get_drc_enum, wm8994_put_drc_enum),
3239 /* We need an array of texts for the enum API */
3240 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3241 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3242 if (!wm8994->drc_texts) {
3243 dev_err(wm8994->hubs.codec->dev,
3244 "Failed to allocate %d DRC config texts\n",
3245 pdata->num_drc_cfgs);
3249 for (i = 0; i < pdata->num_drc_cfgs; i++)
3250 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3252 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3253 wm8994->drc_enum.texts = wm8994->drc_texts;
3255 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3256 ARRAY_SIZE(controls));
3257 for (i = 0; i < WM8994_NUM_DRC; i++)
3258 wm8994_set_drc(codec, i);
3260 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3261 wm8994_drc_controls,
3262 ARRAY_SIZE(wm8994_drc_controls));
3266 dev_err(wm8994->hubs.codec->dev,
3267 "Failed to add DRC mode controls: %d\n", ret);
3270 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3271 pdata->num_retune_mobile_cfgs);
3273 if (pdata->num_retune_mobile_cfgs)
3274 wm8994_handle_retune_mobile_pdata(wm8994);
3276 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3277 ARRAY_SIZE(wm8994_eq_controls));
3279 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3280 if (pdata->micbias[i]) {
3281 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3282 pdata->micbias[i] & 0xffff);
3288 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3290 * @codec: WM8994 codec
3291 * @jack: jack to report detection events on
3292 * @micbias: microphone bias to detect on
3294 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3295 * being used to bring out signals to the processor then only platform
3296 * data configuration is needed for WM8994 and processor GPIOs should
3297 * be configured using snd_soc_jack_add_gpios() instead.
3299 * Configuration of detection levels is available via the micbias1_lvl
3300 * and micbias2_lvl platform data members.
3302 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3305 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3306 struct wm8994_micdet *micdet;
3307 struct wm8994 *control = wm8994->wm8994;
3310 if (control->type != WM8994) {
3311 dev_warn(codec->dev, "Not a WM8994\n");
3317 micdet = &wm8994->micdet[0];
3319 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3322 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3326 micdet = &wm8994->micdet[1];
3328 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3331 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3335 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3340 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3343 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3346 /* Store the configuration */
3347 micdet->jack = jack;
3348 micdet->detecting = true;
3350 /* If either of the jacks is set up then enable detection */
3351 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3352 reg = WM8994_MICD_ENA;
3356 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3358 /* enable MICDET and MICSHRT deboune */
3359 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3360 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3361 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3362 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3364 snd_soc_dapm_sync(&codec->dapm);
3368 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3370 static void wm8994_mic_work(struct work_struct *work)
3372 struct wm8994_priv *priv = container_of(work,
3375 struct regmap *regmap = priv->wm8994->regmap;
3376 struct device *dev = priv->wm8994->dev;
3381 pm_runtime_get_sync(dev);
3383 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®);
3385 dev_err(dev, "Failed to read microphone status: %d\n",
3387 pm_runtime_put(dev);
3391 dev_dbg(dev, "Microphone status: %x\n", reg);
3394 if (reg & WM8994_MIC1_DET_STS) {
3395 if (priv->micdet[0].detecting)
3396 report = SND_JACK_HEADSET;
3398 if (reg & WM8994_MIC1_SHRT_STS) {
3399 if (priv->micdet[0].detecting)
3400 report = SND_JACK_HEADPHONE;
3402 report |= SND_JACK_BTN_0;
3405 priv->micdet[0].detecting = false;
3407 priv->micdet[0].detecting = true;
3409 snd_soc_jack_report(priv->micdet[0].jack, report,
3410 SND_JACK_HEADSET | SND_JACK_BTN_0);
3413 if (reg & WM8994_MIC2_DET_STS) {
3414 if (priv->micdet[1].detecting)
3415 report = SND_JACK_HEADSET;
3417 if (reg & WM8994_MIC2_SHRT_STS) {
3418 if (priv->micdet[1].detecting)
3419 report = SND_JACK_HEADPHONE;
3421 report |= SND_JACK_BTN_0;
3424 priv->micdet[1].detecting = false;
3426 priv->micdet[1].detecting = true;
3428 snd_soc_jack_report(priv->micdet[1].jack, report,
3429 SND_JACK_HEADSET | SND_JACK_BTN_0);
3431 pm_runtime_put(dev);
3434 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3436 struct wm8994_priv *priv = data;
3437 struct snd_soc_codec *codec = priv->hubs.codec;
3439 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3440 trace_snd_soc_jack_irq(dev_name(codec->dev));
3443 pm_wakeup_event(codec->dev, 300);
3445 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
3450 static void wm1811_micd_stop(struct snd_soc_codec *codec)
3452 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3454 if (!wm8994->jackdet)
3457 mutex_lock(&wm8994->accdet_lock);
3459 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3461 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3463 mutex_unlock(&wm8994->accdet_lock);
3465 if (wm8994->wm8994->pdata.jd_ext_cap)
3466 snd_soc_dapm_disable_pin(&codec->dapm,
3470 static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3472 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3477 report |= SND_JACK_BTN_0;
3480 report |= SND_JACK_BTN_1;
3483 report |= SND_JACK_BTN_2;
3486 report |= SND_JACK_BTN_3;
3489 report |= SND_JACK_BTN_4;
3492 report |= SND_JACK_BTN_5;
3494 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3498 static void wm8958_mic_id(void *data, u16 status)
3500 struct snd_soc_codec *codec = data;
3501 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3503 /* Either nothing present or just starting detection */
3504 if (!(status & WM8958_MICD_STS)) {
3505 /* If nothing present then clear our statuses */
3506 dev_dbg(codec->dev, "Detected open circuit\n");
3507 wm8994->jack_mic = false;
3508 wm8994->mic_detecting = true;
3510 wm1811_micd_stop(codec);
3512 wm8958_micd_set_rate(codec);
3514 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3520 /* If the measurement is showing a high impedence we've got a
3523 if (status & 0x600) {
3524 dev_dbg(codec->dev, "Detected microphone\n");
3526 wm8994->mic_detecting = false;
3527 wm8994->jack_mic = true;
3529 wm8958_micd_set_rate(codec);
3531 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3536 if (status & 0xfc) {
3537 dev_dbg(codec->dev, "Detected headphone\n");
3538 wm8994->mic_detecting = false;
3540 wm8958_micd_set_rate(codec);
3542 /* If we have jackdet that will detect removal */
3543 wm1811_micd_stop(codec);
3545 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3550 /* Deferred mic detection to allow for extra settling time */
3551 static void wm1811_mic_work(struct work_struct *work)
3553 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3555 struct wm8994 *control = wm8994->wm8994;
3556 struct snd_soc_codec *codec = wm8994->hubs.codec;
3558 pm_runtime_get_sync(codec->dev);
3560 /* If required for an external cap force MICBIAS on */
3561 if (control->pdata.jd_ext_cap) {
3562 snd_soc_dapm_force_enable_pin(&codec->dapm,
3564 snd_soc_dapm_sync(&codec->dapm);
3567 mutex_lock(&wm8994->accdet_lock);
3569 dev_dbg(codec->dev, "Starting mic detection\n");
3571 /* Use a user-supplied callback if we have one */
3572 if (wm8994->micd_cb) {
3573 wm8994->micd_cb(wm8994->micd_cb_data);
3576 * Start off measument of microphone impedence to find out
3577 * what's actually there.
3579 wm8994->mic_detecting = true;
3580 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3582 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3583 WM8958_MICD_ENA, WM8958_MICD_ENA);
3586 mutex_unlock(&wm8994->accdet_lock);
3588 pm_runtime_put(codec->dev);
3591 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3593 struct wm8994_priv *wm8994 = data;
3594 struct wm8994 *control = wm8994->wm8994;
3595 struct snd_soc_codec *codec = wm8994->hubs.codec;
3599 pm_runtime_get_sync(codec->dev);
3601 mutex_lock(&wm8994->accdet_lock);
3603 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3605 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3606 mutex_unlock(&wm8994->accdet_lock);
3607 pm_runtime_put(codec->dev);
3611 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3613 present = reg & WM1811_JACKDET_LVL;
3616 dev_dbg(codec->dev, "Jack detected\n");
3618 wm8958_micd_set_rate(codec);
3620 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3621 WM8958_MICB2_DISCH, 0);
3623 /* Disable debounce while inserted */
3624 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3625 WM1811_JACKDET_DB, 0);
3627 delay = control->pdata.micdet_delay;
3628 schedule_delayed_work(&wm8994->mic_work,
3629 msecs_to_jiffies(delay));
3631 dev_dbg(codec->dev, "Jack not detected\n");
3633 cancel_delayed_work_sync(&wm8994->mic_work);
3635 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3636 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3638 /* Enable debounce while removed */
3639 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3640 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3642 wm8994->mic_detecting = false;
3643 wm8994->jack_mic = false;
3644 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3645 WM8958_MICD_ENA, 0);
3646 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3649 mutex_unlock(&wm8994->accdet_lock);
3651 /* Turn off MICBIAS if it was on for an external cap */
3652 if (control->pdata.jd_ext_cap && !present)
3653 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3656 snd_soc_jack_report(wm8994->micdet[0].jack,
3657 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3659 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3660 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3663 /* Since we only report deltas force an update, ensures we
3664 * avoid bootstrapping issues with the core. */
3665 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3667 pm_runtime_put(codec->dev);
3671 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3673 struct wm8994_priv *wm8994 = container_of(work,
3675 jackdet_bootstrap.work);
3676 wm1811_jackdet_irq(0, wm8994);
3680 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3682 * @codec: WM8958 codec
3683 * @jack: jack to report detection events on
3685 * Enable microphone detection functionality for the WM8958. By
3686 * default simple detection which supports the detection of up to 6
3687 * buttons plus video and microphone functionality is supported.
3689 * The WM8958 has an advanced jack detection facility which is able to
3690 * support complex accessory detection, especially when used in
3691 * conjunction with external circuitry. In order to provide maximum
3692 * flexiblity a callback is provided which allows a completely custom
3693 * detection algorithm.
3695 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3696 wm1811_micdet_cb det_cb, void *det_cb_data,
3697 wm1811_mic_id_cb id_cb, void *id_cb_data)
3699 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3700 struct wm8994 *control = wm8994->wm8994;
3703 switch (control->type) {
3712 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3713 snd_soc_dapm_sync(&codec->dapm);
3715 wm8994->micdet[0].jack = jack;
3718 wm8994->micd_cb = det_cb;
3719 wm8994->micd_cb_data = det_cb_data;
3721 wm8994->mic_detecting = true;
3722 wm8994->jack_mic = false;
3726 wm8994->mic_id_cb = id_cb;
3727 wm8994->mic_id_cb_data = id_cb_data;
3729 wm8994->mic_id_cb = wm8958_mic_id;
3730 wm8994->mic_id_cb_data = codec;
3733 wm8958_micd_set_rate(codec);
3735 /* Detect microphones and short circuits by default */
3736 if (control->pdata.micd_lvl_sel)
3737 micd_lvl_sel = control->pdata.micd_lvl_sel;
3739 micd_lvl_sel = 0x41;
3741 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3742 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3743 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3745 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3746 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3748 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3751 * If we can use jack detection start off with that,
3752 * otherwise jump straight to microphone detection.
3754 if (wm8994->jackdet) {
3755 /* Disable debounce for the initial detect */
3756 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3757 WM1811_JACKDET_DB, 0);
3759 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3761 WM8958_MICB2_DISCH);
3762 snd_soc_update_bits(codec, WM8994_LDO_1,
3763 WM8994_LDO1_DISCH, 0);
3764 wm1811_jackdet_set_mode(codec,
3765 WM1811_JACKDET_MODE_JACK);
3767 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3768 WM8958_MICD_ENA, WM8958_MICD_ENA);
3772 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3773 WM8958_MICD_ENA, 0);
3774 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3775 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3776 snd_soc_dapm_sync(&codec->dapm);
3781 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3783 static irqreturn_t wm8958_mic_irq(int irq, void *data)
3785 struct wm8994_priv *wm8994 = data;
3786 struct snd_soc_codec *codec = wm8994->hubs.codec;
3787 int reg, count, ret;
3790 * Jack detection may have detected a removal simulataneously
3791 * with an update of the MICDET status; if so it will have
3792 * stopped detection and we can ignore this interrupt.
3794 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3797 pm_runtime_get_sync(codec->dev);
3799 /* We may occasionally read a detection without an impedence
3800 * range being provided - if that happens loop again.
3804 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3807 "Failed to read mic detect status: %d\n",
3809 pm_runtime_put(codec->dev);
3813 if (!(reg & WM8958_MICD_VALID)) {
3814 dev_dbg(codec->dev, "Mic detect data not valid\n");
3818 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3825 dev_warn(codec->dev, "No impedance range reported for jack\n");
3827 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3828 trace_snd_soc_jack_irq(dev_name(codec->dev));
3831 /* Avoid a transient report when the accessory is being removed */
3832 if (wm8994->jackdet) {
3833 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3835 dev_err(codec->dev, "Failed to read jack status: %d\n",
3837 } else if (!(ret & WM1811_JACKDET_LVL)) {
3838 dev_dbg(codec->dev, "Ignoring removed jack\n");
3841 } else if (!(reg & WM8958_MICD_STS)) {
3842 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3843 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3848 if (wm8994->mic_detecting)
3849 wm8994->mic_id_cb(wm8994->mic_id_cb_data, reg);
3851 wm8958_button_det(codec, reg);
3854 pm_runtime_put(codec->dev);
3858 static irqreturn_t wm8994_fifo_error(int irq, void *data)
3860 struct snd_soc_codec *codec = data;
3862 dev_err(codec->dev, "FIFO error\n");
3867 static irqreturn_t wm8994_temp_warn(int irq, void *data)
3869 struct snd_soc_codec *codec = data;
3871 dev_err(codec->dev, "Thermal warning\n");
3876 static irqreturn_t wm8994_temp_shut(int irq, void *data)
3878 struct snd_soc_codec *codec = data;
3880 dev_crit(codec->dev, "Thermal shutdown\n");
3885 static int wm8994_codec_probe(struct snd_soc_codec *codec)
3887 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3888 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3889 struct snd_soc_dapm_context *dapm = &codec->dapm;
3893 wm8994->hubs.codec = codec;
3894 codec->control_data = control->regmap;
3896 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3898 mutex_init(&wm8994->accdet_lock);
3899 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3900 wm1811_jackdet_bootstrap);
3902 switch (control->type) {
3904 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3907 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3913 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3914 init_completion(&wm8994->fll_locked[i]);
3916 wm8994->micdet_irq = control->pdata.micdet_irq;
3918 pm_runtime_enable(codec->dev);
3919 pm_runtime_idle(codec->dev);
3921 /* By default use idle_bias_off, will override for WM8994 */
3922 codec->dapm.idle_bias_off = 1;
3924 /* Set revision-specific configuration */
3925 switch (control->type) {
3927 /* Single ended line outputs should have VMID on. */
3928 if (!control->pdata.lineout1_diff ||
3929 !control->pdata.lineout2_diff)
3930 codec->dapm.idle_bias_off = 0;
3932 switch (control->revision) {
3935 wm8994->hubs.dcs_codes_l = -5;
3936 wm8994->hubs.dcs_codes_r = -5;
3937 wm8994->hubs.hp_startup_mode = 1;
3938 wm8994->hubs.dcs_readback_mode = 1;
3939 wm8994->hubs.series_startup = 1;
3942 wm8994->hubs.dcs_readback_mode = 2;
3948 wm8994->hubs.dcs_readback_mode = 1;
3949 wm8994->hubs.hp_startup_mode = 1;
3951 switch (control->revision) {
3955 wm8994->fll_byp = true;
3961 wm8994->hubs.dcs_readback_mode = 2;
3962 wm8994->hubs.no_series_update = 1;
3963 wm8994->hubs.hp_startup_mode = 1;
3964 wm8994->hubs.no_cache_dac_hp_direct = true;
3965 wm8994->fll_byp = true;
3967 wm8994->hubs.dcs_codes_l = -9;
3968 wm8994->hubs.dcs_codes_r = -7;
3970 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3971 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3978 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3979 wm8994_fifo_error, "FIFO error", codec);
3980 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
3981 wm8994_temp_warn, "Thermal warning", codec);
3982 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
3983 wm8994_temp_shut, "Thermal shutdown", codec);
3985 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
3986 wm_hubs_dcs_done, "DC servo done",
3989 wm8994->hubs.dcs_done_irq = true;
3991 switch (control->type) {
3993 if (wm8994->micdet_irq) {
3994 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3996 IRQF_TRIGGER_RISING,
4000 dev_warn(codec->dev,
4001 "Failed to request Mic1 detect IRQ: %d\n",
4005 ret = wm8994_request_irq(wm8994->wm8994,
4006 WM8994_IRQ_MIC1_SHRT,
4007 wm8994_mic_irq, "Mic 1 short",
4010 dev_warn(codec->dev,
4011 "Failed to request Mic1 short IRQ: %d\n",
4014 ret = wm8994_request_irq(wm8994->wm8994,
4015 WM8994_IRQ_MIC2_DET,
4016 wm8994_mic_irq, "Mic 2 detect",
4019 dev_warn(codec->dev,
4020 "Failed to request Mic2 detect IRQ: %d\n",
4023 ret = wm8994_request_irq(wm8994->wm8994,
4024 WM8994_IRQ_MIC2_SHRT,
4025 wm8994_mic_irq, "Mic 2 short",
4028 dev_warn(codec->dev,
4029 "Failed to request Mic2 short IRQ: %d\n",
4035 if (wm8994->micdet_irq) {
4036 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4038 IRQF_TRIGGER_RISING,
4042 dev_warn(codec->dev,
4043 "Failed to request Mic detect IRQ: %d\n",
4046 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4047 wm8958_mic_irq, "Mic detect",
4052 switch (control->type) {
4054 if (control->cust_id > 1 || control->revision > 1) {
4055 ret = wm8994_request_irq(wm8994->wm8994,
4057 wm1811_jackdet_irq, "JACKDET",
4060 wm8994->jackdet = true;
4067 wm8994->fll_locked_irq = true;
4068 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4069 ret = wm8994_request_irq(wm8994->wm8994,
4070 WM8994_IRQ_FLL1_LOCK + i,
4071 wm8994_fll_locked_irq, "FLL lock",
4072 &wm8994->fll_locked[i]);
4074 wm8994->fll_locked_irq = false;
4077 /* Make sure we can read from the GPIOs if they're inputs */
4078 pm_runtime_get_sync(codec->dev);
4080 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4081 * configured on init - if a system wants to do this dynamically
4082 * at runtime we can deal with that then.
4084 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®);
4086 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4089 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4090 wm8994->lrclk_shared[0] = 1;
4091 wm8994_dai[0].symmetric_rates = 1;
4093 wm8994->lrclk_shared[0] = 0;
4096 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®);
4098 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4101 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4102 wm8994->lrclk_shared[1] = 1;
4103 wm8994_dai[1].symmetric_rates = 1;
4105 wm8994->lrclk_shared[1] = 0;
4108 pm_runtime_put(codec->dev);
4110 /* Latch volume update bits */
4111 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4112 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4113 wm8994_vu_bits[i].mask,
4114 wm8994_vu_bits[i].mask);
4116 /* Set the low bit of the 3D stereo depth so TLV matches */
4117 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4118 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4119 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4120 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4121 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4122 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4123 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4124 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4125 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4127 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4128 * use this; it only affects behaviour on idle TDM clock
4130 switch (control->type) {
4133 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4134 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4140 /* Put MICBIAS into bypass mode by default on newer devices */
4141 switch (control->type) {
4144 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4145 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4146 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4147 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4153 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4154 wm_hubs_update_class_w(codec);
4156 wm8994_handle_pdata(wm8994);
4158 wm_hubs_add_analogue_controls(codec);
4159 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4160 ARRAY_SIZE(wm8994_snd_controls));
4161 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4162 ARRAY_SIZE(wm8994_dapm_widgets));
4164 switch (control->type) {
4166 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4167 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4168 if (control->revision < 4) {
4169 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4170 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4171 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4172 ARRAY_SIZE(wm8994_adc_revd_widgets));
4173 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4174 ARRAY_SIZE(wm8994_dac_revd_widgets));
4176 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4177 ARRAY_SIZE(wm8994_lateclk_widgets));
4178 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4179 ARRAY_SIZE(wm8994_adc_widgets));
4180 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4181 ARRAY_SIZE(wm8994_dac_widgets));
4185 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4186 ARRAY_SIZE(wm8958_snd_controls));
4187 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4188 ARRAY_SIZE(wm8958_dapm_widgets));
4189 if (control->revision < 1) {
4190 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4191 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4192 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4193 ARRAY_SIZE(wm8994_adc_revd_widgets));
4194 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4195 ARRAY_SIZE(wm8994_dac_revd_widgets));
4197 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4198 ARRAY_SIZE(wm8994_lateclk_widgets));
4199 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4200 ARRAY_SIZE(wm8994_adc_widgets));
4201 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4202 ARRAY_SIZE(wm8994_dac_widgets));
4207 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4208 ARRAY_SIZE(wm8958_snd_controls));
4209 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4210 ARRAY_SIZE(wm8958_dapm_widgets));
4211 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4212 ARRAY_SIZE(wm8994_lateclk_widgets));
4213 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4214 ARRAY_SIZE(wm8994_adc_widgets));
4215 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4216 ARRAY_SIZE(wm8994_dac_widgets));
4220 wm_hubs_add_analogue_routes(codec, 0, 0);
4221 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4223 switch (control->type) {
4225 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4226 ARRAY_SIZE(wm8994_intercon));
4228 if (control->revision < 4) {
4229 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4230 ARRAY_SIZE(wm8994_revd_intercon));
4231 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4232 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4234 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4235 ARRAY_SIZE(wm8994_lateclk_intercon));
4239 if (control->revision < 1) {
4240 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4241 ARRAY_SIZE(wm8994_intercon));
4242 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4243 ARRAY_SIZE(wm8994_revd_intercon));
4244 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4245 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4247 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4248 ARRAY_SIZE(wm8994_lateclk_intercon));
4249 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4250 ARRAY_SIZE(wm8958_intercon));
4253 wm8958_dsp2_init(codec);
4256 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4257 ARRAY_SIZE(wm8994_lateclk_intercon));
4258 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4259 ARRAY_SIZE(wm8958_intercon));
4266 if (wm8994->jackdet)
4267 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4268 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4269 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4270 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4271 if (wm8994->micdet_irq)
4272 free_irq(wm8994->micdet_irq, wm8994);
4273 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4274 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4275 &wm8994->fll_locked[i]);
4276 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4278 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4279 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4280 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4285 static int wm8994_codec_remove(struct snd_soc_codec *codec)
4287 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4288 struct wm8994 *control = wm8994->wm8994;
4291 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4293 pm_runtime_disable(codec->dev);
4295 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4296 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4297 &wm8994->fll_locked[i]);
4299 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4301 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4302 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4303 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4305 if (wm8994->jackdet)
4306 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4308 switch (control->type) {
4310 if (wm8994->micdet_irq)
4311 free_irq(wm8994->micdet_irq, wm8994);
4312 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4314 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4316 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4322 if (wm8994->micdet_irq)
4323 free_irq(wm8994->micdet_irq, wm8994);
4326 release_firmware(wm8994->mbc);
4327 release_firmware(wm8994->mbc_vss);
4328 release_firmware(wm8994->enh_eq);
4329 kfree(wm8994->retune_mobile_texts);
4333 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4334 .probe = wm8994_codec_probe,
4335 .remove = wm8994_codec_remove,
4336 .suspend = wm8994_codec_suspend,
4337 .resume = wm8994_codec_resume,
4338 .set_bias_level = wm8994_set_bias_level,
4341 static int wm8994_probe(struct platform_device *pdev)
4343 struct wm8994_priv *wm8994;
4345 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4349 platform_set_drvdata(pdev, wm8994);
4351 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4353 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4354 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4357 static int wm8994_remove(struct platform_device *pdev)
4359 snd_soc_unregister_codec(&pdev->dev);
4363 #ifdef CONFIG_PM_SLEEP
4364 static int wm8994_suspend(struct device *dev)
4366 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4368 /* Drop down to power saving mode when system is suspended */
4369 if (wm8994->jackdet && !wm8994->active_refcount)
4370 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4371 WM1811_JACKDET_MODE_MASK,
4372 wm8994->jackdet_mode);
4377 static int wm8994_resume(struct device *dev)
4379 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4381 if (wm8994->jackdet && wm8994->jackdet_mode)
4382 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4383 WM1811_JACKDET_MODE_MASK,
4384 WM1811_JACKDET_MODE_AUDIO);
4390 static const struct dev_pm_ops wm8994_pm_ops = {
4391 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4394 static struct platform_driver wm8994_codec_driver = {
4396 .name = "wm8994-codec",
4397 .owner = THIS_MODULE,
4398 .pm = &wm8994_pm_ops,
4400 .probe = wm8994_probe,
4401 .remove = wm8994_remove,
4404 module_platform_driver(wm8994_codec_driver);
4406 MODULE_DESCRIPTION("ASoC WM8994 driver");
4407 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4408 MODULE_LICENSE("GPL");
4409 MODULE_ALIAS("platform:wm8994-codec");