sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c -- WM8994 ALSA SoC audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  * Copyright 2005 Openedhand Ltd.
   6  *
   7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/platform_device.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/tlv.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29
  30 #include <mach/iomux.h>
  31 #include <mach/gpio.h>
  32
  33 #include "wm8994.h"
  34 #include <linux/miscdevice.h>
  35 #include <linux/circ_buf.h>
  36 #include <mach/spi_fpga.h>
  37
  38 /* If digital BB is used,open this define. */
  39 //#define PCM_BB
  40
  41 /* Open wm8994 with diferent ways. */
  42 //#define chinaone
  43 #define rk28SDK
  44
  45 /* Define what kind of digital BB is used. */
  46 #ifdef PCM_BB
  47 #define TD688_MODE
  48 //#define MU301_MODE
  49 //#define CHONGY_MODE
  50 //#define THINKWILL_M800_MODE
  51 #endif //PCM_BB
  52
  53 /* Define mic VCC */
  54 #ifdef rk28SDK
  55         #define wm8994_mic_VCC 0x0010
  56 #else
  57         #define wm8994_mic_VCC 0x0000
  58 #endif
  59
  60 #if 1
  61 #define DBG(x...) printk(KERN_INFO x)
  62 #else
  63 #define DBG(x...) do { } while (0)
  64 #endif
  65
  66 #define WM8994_DELAY 50
  67
  68 struct i2c_client *wm8994_client;
  69 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate);
  70 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate);
  71
  72 enum wm8994_codec_mode
  73 {
  74   wm8994_AP_to_headset,
  75   wm8994_AP_to_speakers,
  76   wm8994_recorder,
  77   wm8994_recorder_and_AP_to_headset,
  78   wm8994_recorder_and_AP_to_speakers,
  79   wm8994_FM_to_headset,
  80   wm8994_FM_to_headset_and_record,
  81   wm8994_FM_to_speakers,
  82   wm8994_FM_to_speakers_and_record,
  83   wm8994_handsetMIC_to_baseband_to_headset,
  84   wm8994_handsetMIC_to_baseband_to_headset_and_record,
  85   wm8994_mainMIC_to_baseband_to_earpiece,
  86   wm8994_mainMIC_to_baseband_to_earpiece_and_record,
  87   wm8994_mainMIC_to_baseband_to_speakers,
  88   wm8994_mainMIC_to_baseband_with_AP_to_speakers,
  89   wm8994_mainMIC_to_baseband_to_speakers_and_record,
  90   wm8994_BT_baseband,
  91   wm8994_BT_baseband_and_record,
  92   null
  93 };
  94
  95 /* wm8994_current_mode:save current wm8994 mode */
  96 unsigned char wm8994_current_mode=null;
  97
  98 void wm8994_set_volume(unsigned char wm8994_mode,unsigned char volume,unsigned char max_volume);
  99
 100 enum stream_type_wm8994
 101 {
 102         VOICE_CALL      =0,
 103         BLUETOOTH_SCO,
 104 };
 105
 106 /* For voice device route set, add by phc  */
 107 enum VoiceDeviceSwitch
 108 {
 109         SPEAKER_INCALL,
 110         SPEAKER_NORMAL,
 111
 112         HEADSET_INCALL,
 113         HEADSET_NORMAL,
 114
 115         EARPIECE_INCALL,
 116         EARPIECE_NORMAL,
 117
 118         BLUETOOTH_SCO_INCALL,
 119         BLUETOOTH_SCO_NORMAL,
 120
 121         BLUETOOTH_A2DP_INCALL,
 122         BLUETOOTH_A2DP_NORMAL,
 123
 124         MIC_CAPTURE,
 125
 126         ALL_OPEN,
 127         ALL_CLOSED
 128 };
 129
 130 #define call_maxvol 5
 131
 132 /* call_vol:  save all kinds of system volume value. */
 133 unsigned char call_vol=5;
 134 unsigned short headset_vol_table[6]     ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 135 unsigned short speakers_vol_table[6]    ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 136 unsigned short earpiece_vol_table[6]    ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 137 unsigned short BT_vol_table[6]          ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 138
 139 /*
 140  * wm8994 register cache
 141  * We can't read the WM8994 register space when we
 142  * are using 2 wire for device control, so we cache them instead.
 143  */
 144 static const u16 wm8994_reg[] = {
 145         0x0097, 0x0097, 0x0079, 0x0079,  /*  0 */
 146         0x0000, 0x0008, 0x0000, 0x000a,  /*  4 */
 147         0x0000, 0x0000, 0x00ff, 0x00ff,  /*  8 */
 148         0x000f, 0x000f, 0x0000, 0x0000,  /* 12 */
 149         0x0000, 0x007b, 0x0000, 0x0032,  /* 16 */
 150         0x0000, 0x00c3, 0x00c3, 0x00c0,  /* 20 */
 151         0x0000, 0x0000, 0x0000, 0x0000,  /* 24 */
 152         0x0000, 0x0000, 0x0000, 0x0000,  /* 28 */
 153         0x0000, 0x0000, 0x0050, 0x0050,  /* 32 */
 154         0x0050, 0x0050, 0x0050, 0x0050,  /* 36 */
 155         0x0079, 0x0079, 0x0079,          /* 40 */
 156 };
 157
 158 /* codec private data */
 159 struct wm8994_priv {
 160         unsigned int sysclk;
 161         struct snd_soc_codec codec;
 162         struct snd_pcm_hw_constraint_list *sysclk_constraints;
 163         u16 reg_cache[WM8994_NUM_REG];
 164 };
 165
 166 static int wm8994_read(unsigned short reg,unsigned short *value)
 167 {
 168         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values;
 169
 170         if (reg_recv_data(wm8994_client,&regs,&values,400000) >= 0)
 171         {
 172                 *value=((values>>8)& 0x00FF)|((values<<8)&0xFF00);
 173                 return 0;
 174         }
 175
 176         printk("%s---line->%d:Codec read error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,*value);
 177
 178         return -EIO;
 179 }
 180
 181
 182 static int wm8994_write(unsigned short reg,unsigned short value)
 183 {
 184         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values=((value>>8)&0x00FF)|((value<<8)&0xFF00);
 185
 186         if (reg_send_data(wm8994_client,&regs,&values,400000)>=0)
 187                 return 0;
 188
 189         printk("%s---line->%d:Codec write error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,value);
 190
 191         return -EIO;
 192 }
 193
 194 #define wm8994_reset()  wm8994_write(WM8994_RESET, 0)
 195
 196 void AP_to_headset(void)
 197 {
 198         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 199
 200         wm8994_current_mode=wm8994_AP_to_headset;
 201         wm8994_reset();
 202         mdelay(WM8994_DELAY);
 203
 204         wm8994_write(0x01,  0x0003);
 205         mdelay(WM8994_DELAY);
 206
 207         wm8994_write(0x200, 0x0001);
 208         wm8994_write(0x220, 0x0000);
 209         wm8994_write(0x221, 0x0700);
 210         wm8994_write(0x222, 0x3126);
 211         wm8994_write(0x223, 0x0100);
 212
 213         wm8994_write(0x210, 0x0083); // SR=48KHz
 214         wm8994_write(0x220, 0x0004);
 215         mdelay(WM8994_DELAY);
 216         wm8994_write(0x220, 0x0005);
 217         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 218         wm8994_write(0x300, 0x4010);  // i2s 16 bits
 219
 220         wm8994_write(0x01,  0x0303);
 221         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1//cjq
 222         wm8994_write(0x05,  0x0303);
 223         wm8994_write(0x2D,  0x0100);
 224         wm8994_write(0x2E,  0x0100);
 225         wm8994_write(0x4C,  0x9F25);
 226         wm8994_write(0x60,  0x00EE);
 227         wm8994_write(0x208, 0x000A);
 228         wm8994_write(0x420, 0x0000);
 229         wm8994_write(0x601, 0x0001);
 230         wm8994_write(0x602, 0x0001);
 231
 232         wm8994_write(0x610, 0x01A0);  //DAC1 Left Volume bit0~7
 233         wm8994_write(0x611, 0x01A0);  //DAC1 Right Volume bit0~7
 234         wm8994_write(0x03,  0x3030);
 235         wm8994_write(0x22,  0x0000);
 236         wm8994_write(0x23,  0x0100);
 237         wm8994_write(0x36,  0x0003);
 238         wm8994_write(0x1C,  0x017F);  //HPOUT1L Volume
 239         wm8994_write(0x1D,  0x017F);  //HPOUT1R Volume
 240
 241 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 242         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 243         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 244         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 245         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 246 #endif
 247
 248         mdelay(WM8994_DELAY);
 249 }
 250
 251 void AP_to_speakers(void)
 252 {
 253         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 254
 255         wm8994_current_mode=wm8994_AP_to_speakers;
 256         wm8994_reset();
 257         mdelay(WM8994_DELAY);
 258
 259
 260         wm8994_write(0x01,  0x0003);
 261         mdelay(WM8994_DELAY);
 262
 263         wm8994_write(0x200, 0x0001);
 264         wm8994_write(0x220, 0x0000);
 265         wm8994_write(0x221, 0x0700);
 266         wm8994_write(0x222, 0x3126);
 267         wm8994_write(0x223, 0x0100);
 268
 269         wm8994_write(0x210, 0x0083); // SR=48KHz
 270         wm8994_write(0x220, 0x0004);
 271         mdelay(WM8994_DELAY);
 272         wm8994_write(0x220, 0x0005);
 273         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 274         wm8994_write(0x300, 0xC010);  // i2s 16 bits
 275
 276         wm8994_write(0x01,  0x3003);
 277         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1//cjq
 278         wm8994_write(0x05,  0x0303);
 279         wm8994_write(0x2D,  0x0100);
 280         wm8994_write(0x2E,  0x0100);
 281         wm8994_write(0x4C,  0x9F25);
 282         wm8994_write(0x60,  0x00EE);
 283         wm8994_write(0x208, 0x000A);
 284         wm8994_write(0x420, 0x0000);
 285
 286         wm8994_write(0x601, 0x0001);
 287         wm8994_write(0x602, 0x0001);
 288
 289         wm8994_write(0x610, 0x01c0);  //DAC1 Left Volume bit0~7
 290         wm8994_write(0x611, 0x01c0);  //DAC1 Right Volume bit0~7
 291         wm8994_write(0x03,  0x0330);
 292         wm8994_write(0x22,  0x0000);
 293         wm8994_write(0x23,  0x0100);
 294         wm8994_write(0x36,  0x0003);
 295         wm8994_write(0x26,  0x017F);  //Speaker Left Output Volume
 296         wm8994_write(0x27,  0x017F);  //Speaker Right Output Volume
 297
 298 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 299         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 300         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 301         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 302         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 303 #endif
 304
 305         mdelay(WM8994_DELAY);
 306 }
 307
 308 void recorder(void)
 309 {
 310         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 311
 312         wm8994_current_mode=wm8994_recorder;
 313         wm8994_reset();
 314         mdelay(WM8994_DELAY);
 315
 316         wm8994_write(0x01,   0x0003|wm8994_mic_VCC);
 317         mdelay(WM8994_DELAY);
 318         wm8994_write(0x221,  0x0D00);
 319         wm8994_write(0x222,  0x3300);
 320         wm8994_write(0x223,  0x00E0);
 321
 322 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 323         wm8994_write(0x302,  0x4000);  //master = 0x4000  slave= 0x0000
 324         wm8994_write(0x303,  0x0090);  //master  0x0090 lrck1 8kHz bclk1 515KHz
 325         wm8994_write(0x305,  0x00F0);  //master  0x00F0 lrck1 8kHz bclk1 515KHz
 326 #endif
 327
 328         wm8994_write(0x220,  0x0004);
 329         mdelay(WM8994_DELAY);
 330         wm8994_write(0x220,  0x0005);
 331
 332         wm8994_write(0x02,   0x6110);
 333         wm8994_write(0x04,   0x0303);
 334         wm8994_write(0x1A,   0x015F);  //volume
 335
 336         wm8994_write(0x28,   0x0003);
 337         wm8994_write(0x2A,   0x0020);
 338         wm8994_write(0x200,  0x0011);
 339         wm8994_write(0x208,  0x000A);
 340         wm8994_write(0x300,  0xC050);
 341         wm8994_write(0x606,  0x0002);
 342         wm8994_write(0x607,  0x0002);
 343         wm8994_write(0x620,  0x0000);
 344
 345 }
 346
 347 void recorder_and_AP_to_headset(void)
 348 {
 349         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 350
 351         wm8994_current_mode=wm8994_recorder_and_AP_to_headset;
 352         wm8994_reset();
 353         mdelay(WM8994_DELAY);
 354
 355         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
 356         mdelay(WM8994_DELAY);
 357
 358 //MCLK=12MHz
 359 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 360
 361         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 362         wm8994_write(0x220, 0x0000);
 363         wm8994_write(0x221, 0x0700);
 364         wm8994_write(0x222, 0x3126);
 365         wm8994_write(0x223, 0x0100);
 366
 367         wm8994_write(0x210, 0x0083); // SR=48KHz
 368
 369         wm8994_write(0x220, 0x0004);
 370         mdelay(WM8994_DELAY);
 371         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 372         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 373
 374         wm8994_write(0x02,  0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
 375         wm8994_write(0x03,  0x3030);
 376         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 377         wm8994_write(0x1A,  0x014B); // IN1_VU=1, IN1R_ZC=1, IN1R_VOL=0_1011
 378         wm8994_write(0x28,  0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
 379         wm8994_write(0x2A,  0x0020); // IN1R_TO_MIXINR=1
 380         wm8994_write(0x200, 0x0011); // AIF1CLK_ENA=1
 381         wm8994_write(0x208, 0x000A); // DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 382         wm8994_write(0x300, 0xC010); // AIF1ADCL_SRC=1, AIF1ADCR_SRC=1, AIF1_WL=10, AIF1_FMT=10
 383         wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
 384         wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
 385         wm8994_write(0x620, 0x0000);
 386
 387         wm8994_write(0x700, 0xA101);
 388
 389         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);
 390         wm8994_write(0x05,  0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
 391         wm8994_write(0x2D,  0x0100); // DAC1L_TO_HPOUT1L=1
 392         wm8994_write(0x2E,  0x0100); // DAC1R_TO_HPOUT1R=1
 393         wm8994_write(0x4C,  0x9F25); // CP_ENA=1
 394         wm8994_write(0x60,  0x00EE); // HPOUT1L_RMV_SHORT=1, HPOUT1L_OUTP=1, HPOUT1L_DLY=1, HPOUT1R_RMV_SHORT=1, HPOUT1R_OUTP=1, HPOUT1R_DLY=1
 395         wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
 396         wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
 397         wm8994_write(0x610, 0x01A0); // DAC1_VU=1, DAC1L_VOL=1100_0000
 398         wm8994_write(0x611, 0x01A0); // DAC1_VU=1, DAC1R_VOL=1100_0000
 399         wm8994_write(0x1C,  0x017F);  //HPOUT1L Volume
 400         wm8994_write(0x1D,  0x017F);  //HPOUT1R Volume
 401         wm8994_write(0x420, 0x0000);
 402
 403 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 404         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 405         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 406         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 407         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 408 #endif
 409 }
 410
 411 void recorder_and_AP_to_speakers(void)
 412 {
 413         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 414
 415         wm8994_current_mode=wm8994_recorder_and_AP_to_speakers;
 416         wm8994_reset();
 417         mdelay(WM8994_DELAY);
 418
 419         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
 420         mdelay(WM8994_DELAY);
 421
 422 //MCLK=12MHz
 423 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 424
 425         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 426         wm8994_write(0x220, 0x0000);
 427         wm8994_write(0x221, 0x0700);
 428         wm8994_write(0x222, 0x3126);
 429         wm8994_write(0x223, 0x0100);
 430         wm8994_write(0x210, 0x0083); // SR=48KHz
 431
 432         wm8994_write(0x220, 0x0004);
 433         mdelay(WM8994_DELAY);
 434         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 435         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 436
 437         wm8994_write(0x02,  0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
 438         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 439         wm8994_write(0x1A,  0x014B); // IN1_VU=1, IN1R_ZC=1, IN1R_VOL=0_1011
 440         wm8994_write(0x28,  0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
 441         wm8994_write(0x2A,  0x0020); // IN1R_TO_MIXINR=1
 442         wm8994_write(0x200, 0x0011); // AIF1CLK_ENA=1
 443         wm8994_write(0x208, 0x000A); // DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 444         wm8994_write(0x300, 0xC010); // AIF1ADCL_SRC=1, AIF1ADCR_SRC=1, AIF1_WL=10, AIF1_FMT=10
 445         wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
 446         wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
 447         wm8994_write(0x620, 0x0000);
 448
 449         wm8994_write(0x700, 0xA101);
 450
 451         wm8994_write(0x01,  0x3003|wm8994_mic_VCC);
 452         wm8994_write(0x03,  0x0330); // SPKRVOL_ENA=1, SPKLVOL_ENA=1, MIXOUTL_ENA=1, MIXOUTR_ENA=1
 453         wm8994_write(0x05,  0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
 454         wm8994_write(0x22,  0x0000);
 455         wm8994_write(0x23,  0x0100); // SPKOUT_CLASSAB=1
 456
 457         wm8994_write(0x2D,  0x0001); // DAC1L_TO_MIXOUTL=1
 458         wm8994_write(0x2E,  0x0001); // DAC1R_TO_MIXOUTR=1
 459         wm8994_write(0x36,  0x000C); // MIXOUTL_TO_SPKMIXL=1, MIXOUTR_TO_SPKMIXR=1
 460         wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
 461         wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
 462         wm8994_write(0x610, 0x01C0); // DAC1_VU=1, DAC1L_VOL=1100_0000
 463         wm8994_write(0x611, 0x01C0); // DAC1_VU=1, DAC1R_VOL=1100_0000
 464         wm8994_write(0x26,  0x017F);  //Speaker Left Output Volume
 465         wm8994_write(0x27,  0x017F);  //Speaker Right Output Volume
 466         wm8994_write(0x420, 0x0000);
 467
 468 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 469         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 470         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 471         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 472         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 473 #endif
 474 }
 475
 476 void FM_to_headset(void)
 477 {
 478         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 479
 480         wm8994_current_mode=wm8994_FM_to_headset;
 481         wm8994_reset();
 482         mdelay(WM8994_DELAY);
 483
 484         wm8994_write(0x01,  0x0323);
 485         wm8994_write(0x02,  0x03A0);
 486         wm8994_write(0x03,  0x0030);
 487         wm8994_write(0x19,  0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 488         wm8994_write(0x1B,  0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 489
 490         wm8994_write(0x28,  0x0044);
 491         wm8994_write(0x29,  0x0100);
 492         wm8994_write(0x2A,  0x0100);
 493         wm8994_write(0x2D,  0x0040);
 494         wm8994_write(0x2E,  0x0040);
 495         wm8994_write(0x4C,  0x9F25);
 496         wm8994_write(0x60,  0x00EE);
 497         wm8994_write(0x220, 0x0003);
 498         wm8994_write(0x221, 0x0700);
 499         wm8994_write(0x224, 0x0CC0);
 500         wm8994_write(0x200, 0x0011);
 501         wm8994_write(0x1C,  0x01F9);  //LEFT OUTPUT VOLUME
 502         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 503 }
 504
 505 void FM_to_headset_and_record(void)
 506 {
 507         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 508
 509         wm8994_current_mode=wm8994_FM_to_headset_and_record;
 510         wm8994_reset();
 511         mdelay(WM8994_DELAY);
 512
 513         wm8994_write(0x01,   0x0003);
 514         mdelay(WM8994_DELAY);
 515         wm8994_write(0x221,  0x1900);  //8~13BIT div
 516
 517 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 518         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 519         wm8994_write(0x303,  0x0040);  // master  0x0050 lrck 7.94kHz bclk 510KHz
 520 #endif
 521
 522         wm8994_write(0x220,  0x0004);
 523         mdelay(WM8994_DELAY);
 524         wm8994_write(0x220,  0x0005);
 525
 526         wm8994_write(0x01,   0x0323);
 527         wm8994_write(0x02,   0x03A0);
 528         wm8994_write(0x03,   0x0030);
 529         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 530         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 531
 532         wm8994_write(0x28,   0x0044);
 533         wm8994_write(0x29,   0x0100);
 534         wm8994_write(0x2A,   0x0100);
 535         wm8994_write(0x2D,   0x0040);
 536         wm8994_write(0x2E,   0x0040);
 537         wm8994_write(0x4C,   0x9F25);
 538         wm8994_write(0x60,   0x00EE);
 539         wm8994_write(0x200,  0x0011);
 540         wm8994_write(0x1C,   0x01F9);  //LEFT OUTPUT VOLUME
 541         wm8994_write(0x1D,   0x01F9);  //RIGHT OUTPUT VOLUME
 542         wm8994_write(0x04,   0x0303);
 543         wm8994_write(0x208,  0x000A);
 544         wm8994_write(0x300,  0x4050);
 545         wm8994_write(0x606,  0x0002);
 546         wm8994_write(0x607,  0x0002);
 547         wm8994_write(0x620,  0x0000);
 548 }
 549
 550 void FM_to_speakers(void)
 551 {
 552         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 553
 554         wm8994_current_mode=wm8994_FM_to_speakers;
 555         wm8994_reset();
 556         mdelay(WM8994_DELAY);
 557
 558         wm8994_write(0x01,   0x3023);
 559         wm8994_write(0x02,   0x03A0);
 560         wm8994_write(0x03,   0x0330);
 561         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 562         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 563
 564         wm8994_write(0x22,   0x0000);
 565         wm8994_write(0x23,   0x0000);
 566         wm8994_write(0x36,   0x000C);
 567
 568         wm8994_write(0x28,   0x0044);
 569         wm8994_write(0x29,   0x0100);
 570         wm8994_write(0x2A,   0x0100);
 571         wm8994_write(0x2D,   0x0040);
 572         wm8994_write(0x2E,   0x0040);
 573
 574         wm8994_write(0x220,  0x0003);
 575         wm8994_write(0x221,  0x0700);
 576         wm8994_write(0x224,  0x0CC0);
 577
 578         wm8994_write(0x200,  0x0011);
 579         wm8994_write(0x20,   0x01F9);
 580         wm8994_write(0x21,   0x01F9);
 581 }
 582
 583 void FM_to_speakers_and_record(void)
 584 {
 585         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 586
 587         wm8994_current_mode=wm8994_FM_to_speakers_and_record;
 588         wm8994_reset();
 589         mdelay(WM8994_DELAY);
 590
 591         wm8994_write(0x01,   0x0003);
 592         mdelay(WM8994_DELAY);
 593
 594 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 595         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 596         wm8994_write(0x303,  0x0090);  //
 597 #endif
 598
 599         wm8994_write(0x220,  0x0006);
 600         mdelay(WM8994_DELAY);
 601
 602         wm8994_write(0x01,   0x3023);
 603         wm8994_write(0x02,   0x03A0);
 604         wm8994_write(0x03,   0x0330);
 605         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 606         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 607
 608         wm8994_write(0x22,   0x0000);
 609         wm8994_write(0x23,   0x0000);
 610         wm8994_write(0x36,   0x000C);
 611
 612         wm8994_write(0x28,   0x0044);
 613         wm8994_write(0x29,   0x0100);
 614         wm8994_write(0x2A,   0x0100);
 615         wm8994_write(0x2D,   0x0040);
 616         wm8994_write(0x2E,   0x0040);
 617
 618         wm8994_write(0x220,  0x0003);
 619         wm8994_write(0x221,  0x0700);
 620         wm8994_write(0x224,  0x0CC0);
 621
 622         wm8994_write(0x200,  0x0011);
 623         wm8994_write(0x20,   0x01F9);
 624         wm8994_write(0x21,   0x01F9);
 625         wm8994_write(0x04,   0x0303);
 626         wm8994_write(0x208,  0x000A);
 627         wm8994_write(0x300,  0x4050);
 628         wm8994_write(0x606,  0x0002);
 629         wm8994_write(0x607,  0x0002);
 630         wm8994_write(0x620,  0x0000);
 631 }
 632 #ifndef PCM_BB
 633 void handsetMIC_to_baseband_to_headset(void)
 634 {
 635         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 636
 637         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset;
 638         wm8994_reset();
 639         mdelay(WM8994_DELAY);
 640
 641         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);
 642         wm8994_write(0x02,  0x6040);
 643         wm8994_write(0x03,  0x3030);
 644         wm8994_write(0x18,  0x014B);  //mic volume
 645         wm8994_write(0x1E,  0x0006);
 646         wm8994_write(0x28,  0x0030);
 647         wm8994_write(0x2D,  0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 648         wm8994_write(0x2E,  0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 649         wm8994_write(0x34,  0x0002);
 650         wm8994_write(0x4C,  0x9F25);
 651         wm8994_write(0x60,  0x00EE);
 652         wm8994_write(0x220, 0x0003);
 653         wm8994_write(0x221, 0x0700);
 654         wm8994_write(0x224, 0x0CC0);
 655
 656 //Note: free-running start first, then open AIF1 clock setting
 657         wm8994_write(0x200, 0x0011);
 658 //Note: 0x1C/0x1D=0x01FF-->bypass volume no gain/attenuation
 659         wm8994_write(0x1C,  0x01FF);  //LEFT OUTPUT VOLUME
 660         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 661
 662         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 663 }
 664
 665 void handsetMIC_to_baseband_to_headset_and_record(void)
 666 {
 667         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 668
 669         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset_and_record;
 670         wm8994_reset();
 671         mdelay(WM8994_DELAY);
 672
 673         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);
 674         wm8994_write(0x02,  0x62C0);
 675         wm8994_write(0x03,  0x3030);
 676         wm8994_write(0x04,  0x0303);
 677         wm8994_write(0x18,  0x014B);  //volume
 678         wm8994_write(0x19,  0x014B);  //volume
 679         wm8994_write(0x1C,  0x01FF);  //LEFT OUTPUT VOLUME
 680         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 681         wm8994_write(0x1E,  0x0006);
 682         wm8994_write(0x28,  0x00B0);  //IN2LP_TO_IN2L
 683         wm8994_write(0x29,  0x0120);
 684         wm8994_write(0x2D,  0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 685         wm8994_write(0x2E,  0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 686         wm8994_write(0x34,  0x0002);
 687         wm8994_write(0x4C,  0x9F25);
 688         wm8994_write(0x60,  0x00EE);
 689         wm8994_write(0x200, 0x0001);
 690         wm8994_write(0x208, 0x000A);
 691         wm8994_write(0x300, 0x0050);
 692
 693 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 694         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 695         wm8994_write(0x303, 0x0090);  // master lrck 16k
 696 #endif
 697
 698         wm8994_write(0x606, 0x0002);
 699         wm8994_write(0x607, 0x0002);
 700         wm8994_write(0x620, 0x0000);
 701
 702         wm8994_write(0x1C,  0x01F9);
 703         wm8994_write(0x1D,  0x01F9);
 704
 705         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 706 }
 707
 708 void mainMIC_to_baseband_to_earpiece(void)
 709 {
 710         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 711
 712         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
 713         wm8994_reset();
 714         mdelay(WM8994_DELAY);
 715
 716         wm8994_write(0x01, 0x0803|wm8994_mic_VCC);
 717         wm8994_write(0x02, 0x6210);
 718         wm8994_write(0x03, 0x30A0);
 719         wm8994_write(0x1A, 0x015F);  //main mic volume
 720         wm8994_write(0x1E, 0x0006);
 721         wm8994_write(0x1F, 0x0000);
 722         wm8994_write(0x28, 0x0003);
 723         wm8994_write(0x2B, 0x0005);  //VRX_MIXINL_VOL
 724         wm8994_write(0x2D, 0x0040);
 725         wm8994_write(0x33, 0x0010);
 726         wm8994_write(0x34, 0x0004);
 727
 728         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 729 }
 730
 731 void mainMIC_to_baseband_to_earpiece_and_record(void)
 732 {
 733         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 734
 735         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
 736         wm8994_reset();
 737         mdelay(WM8994_DELAY);
 738
 739         wm8994_write(0x01  ,0x0803|wm8994_mic_VCC);
 740         wm8994_write(0x02  ,0x6310);
 741         wm8994_write(0x03  ,0x30A0);
 742         wm8994_write(0x04  ,0x0303);
 743         wm8994_write(0x1A  ,0x014F);
 744         wm8994_write(0x1E  ,0x0006);
 745         wm8994_write(0x1F  ,0x0000);
 746         wm8994_write(0x28  ,0x0003);  //MAINMIC_TO_IN1R  //
 747         wm8994_write(0x2A  ,0x0020);  //IN1R_TO_MIXINR   //
 748         wm8994_write(0x2B  ,0x0005);  //VRX_MIXINL_VOL bit 0~2
 749         wm8994_write(0x2C  ,0x0005);  //VRX_MIXINR_VOL
 750         wm8994_write(0x2D  ,0x0040);  //MIXINL_TO_MIXOUTL
 751         wm8994_write(0x33  ,0x0010);  //MIXOUTLVOL_TO_HPOUT2
 752         wm8994_write(0x34  ,0x0004);  //IN1R_TO_LINEOUT1 //
 753         wm8994_write(0x200 ,0x0001);
 754         wm8994_write(0x208 ,0x000A);
 755         wm8994_write(0x300 ,0xC050);
 756
 757 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 758         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 759         wm8994_write(0x303, 0x0090);  // master lrck 16k
 760 #endif
 761
 762         wm8994_write(0x606 ,0x0002);
 763         wm8994_write(0x607 ,0x0002);
 764         wm8994_write(0x620 ,0x0000);
 765
 766         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 767 }
 768
 769 void mainMIC_to_baseband_to_speakers(void)
 770 {
 771         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 772
 773         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers;
 774         wm8994_reset();
 775         mdelay(WM8994_DELAY);
 776
 777         wm8994_write(0x01 ,0x3003|wm8994_mic_VCC);
 778         wm8994_write(0x02 ,0x6210);
 779         wm8994_write(0x03 ,0x3330);
 780         wm8994_write(0x1A ,0x015F);
 781         wm8994_write(0x1E ,0x0006);
 782         wm8994_write(0x22 ,0x0000);
 783         wm8994_write(0x23 ,0x0100);
 784         wm8994_write(0x26 ,0x017F);  //Speaker Volume Left bit 0~5
 785         wm8994_write(0x27 ,0x017F);  //Speaker Volume Right bit 0~5
 786         wm8994_write(0x28 ,0x0003);
 787         wm8994_write(0x2D ,0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 788         wm8994_write(0x2E ,0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 789         wm8994_write(0x34 ,0x0004);
 790         wm8994_write(0x36 ,0x000C);
 791
 792         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 793 }
 794
 795 void mainMIC_to_baseband_with_AP_to_speakers(void)
 796 {
 797         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 798
 799         wm8994_current_mode=wm8994_mainMIC_to_baseband_with_AP_to_speakers;
 800         wm8994_reset();
 801         mdelay(WM8994_DELAY);
 802
 803         wm8994_write(0x01,  0x3003|wm8994_mic_VCC);
 804         mdelay(WM8994_DELAY);
 805
 806         wm8994_write(0x200, 0x0001);
 807         wm8994_write(0x220, 0x0000);
 808         wm8994_write(0x221, 0x0700);
 809         wm8994_write(0x222, 0x3126);
 810         wm8994_write(0x223, 0x0100);
 811
 812         wm8994_write(0x210, 0x0083); // SR=48KHz
 813         mdelay(WM8994_DELAY);
 814         wm8994_write(0x220, 0x0005);
 815         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 816         wm8994_write(0x300, 0xC010);  // i2s 16 bits
 817
 818         wm8994_write(0x01,  0x3003|wm8994_mic_VCC);
 819         wm8994_write(0x02,  0x6210);
 820         wm8994_write(0x03,  0x3330);
 821         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1//cjq
 822         wm8994_write(0x05,  0x0303);
 823         wm8994_write(0x1A,  0x015F);
 824         wm8994_write(0x1E,  0x0006);
 825         wm8994_write(0x22,  0x0000);
 826         wm8994_write(0x23,  0x0100);
 827         wm8994_write(0x26,  0x017F);  //Speaker Volume Left bit 0~5
 828         wm8994_write(0x27,  0x017F);  //Speaker Volume Right bit 0~5
 829         wm8994_write(0x28,  0x0003);
 830         wm8994_write(0x2D,  0x0003);  //bit 1 IN2LP_TO_MIXOUTL
 831         wm8994_write(0x2E,  0x0003);  //bit 1 IN2RP_TO_MIXOUTR
 832         wm8994_write(0x4C,  0x9F25);
 833         wm8994_write(0x60,  0x00EE);
 834         wm8994_write(0x34,  0x0004);
 835         wm8994_write(0x36,  0x000C);
 836
 837         wm8994_write(0x208, 0x000A);
 838         wm8994_write(0x420, 0x0000);
 839
 840         wm8994_write(0x601, 0x0001);
 841         wm8994_write(0x602, 0x0001);
 842
 843         wm8994_write(0x610, 0x01c0);  //DAC1 Left Volume bit0~7
 844         wm8994_write(0x611, 0x01c0);  //DAC1 Right Volume bit0~7
 845
 846 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 847         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 848         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 849         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 850         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 851 #endif
 852
 853         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 854 }
 855
 856 void mainMIC_to_baseband_to_speakers_and_record(void)
 857 {
 858         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 859
 860         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
 861         wm8994_reset();
 862         mdelay(WM8994_DELAY);
 863
 864         wm8994_write(0x01, 0x3003|wm8994_mic_VCC);
 865         wm8994_write(0x02, 0x6330);
 866         wm8994_write(0x03, 0x3330);
 867         wm8994_write(0x04, 0x0303);
 868         wm8994_write(0x1A, 0x014B);
 869         wm8994_write(0x1B, 0x014B);
 870         wm8994_write(0x1E, 0x0006);
 871         wm8994_write(0x22, 0x0000);
 872         wm8994_write(0x23, 0x0100);
 873         wm8994_write(0x28, 0x0007);
 874         wm8994_write(0x2A, 0x0120);
 875         wm8994_write(0x2D, 0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 876         wm8994_write(0x2E, 0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 877         wm8994_write(0x34, 0x0004);
 878         wm8994_write(0x36, 0x000C);
 879         wm8994_write(0x200, 0x0001);
 880         wm8994_write(0x208, 0x000A);
 881         wm8994_write(0x300, 0xC050);
 882
 883 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 884         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 885         wm8994_write(0x303, 0x0090);  // master lrck 16k
 886 #endif
 887
 888         wm8994_write(0x606, 0x0002);
 889         wm8994_write(0x607, 0x0002);
 890         wm8994_write(0x620, 0x0000);
 891
 892         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 893 }
 894
 895 void BT_baseband(void)
 896 {
 897         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 898
 899         wm8994_current_mode=wm8994_BT_baseband;
 900         wm8994_reset();
 901         mdelay(WM8994_DELAY);
 902
 903         wm8994_write(0x01,  0x0003);
 904         mdelay(WM8994_DELAY);
 905         wm8994_write(0x221, 0x0700);
 906         wm8994_write(0x222, 0x3127);
 907         wm8994_write(0x223, 0x0100);
 908         wm8994_write(0x220, 0x0004);
 909         mdelay(WM8994_DELAY);
 910         wm8994_write(0x220, 0x0005);
 911
 912         wm8994_write(0x01,  0x0003);
 913         wm8994_write(0x03,  0x30F0);
 914         wm8994_write(0x05,  0x3003);
 915         wm8994_write(0x2D,  0x0001);
 916         wm8994_write(0x2E,  0x0001);
 917
 918         wm8994_write(0x200, 0x0001);
 919         wm8994_write(0x204, 0x0001);
 920         wm8994_write(0x208, 0x0007);
 921         wm8994_write(0x520, 0x0000);
 922         wm8994_write(0x601, 0x0004);
 923         wm8994_write(0x602, 0x0004);
 924         wm8994_write(0x610, 0x01C0);
 925         wm8994_write(0x611, 0x01C0);
 926         wm8994_write(0x613, 0x01C0);
 927
 928         wm8994_write(0x702, 0xC100);
 929         wm8994_write(0x703, 0xC100);
 930         wm8994_write(0x704, 0xC100);
 931         wm8994_write(0x706, 0x4100);
 932
 933         wm8994_write(0x204, 0x0011);  // AIF2 MCLK=FLL                            //MASTER
 934         wm8994_write(0x211, 0x0039);  //LRCK=8KHZ,Rate=MCLK/1536                         //MASTER
 935         wm8994_write(0x310, 0xC118);  //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
 936
 937         wm8994_write(0x313, 0x00F0);
 938         wm8994_write(0x314, 0x0020);
 939         wm8994_write(0x315, 0x0020);
 940         wm8994_write(0x2B,  0x0005);
 941         wm8994_write(0x2C,  0x0005);
 942         wm8994_write(0x02,  0x6300);
 943         wm8994_write(0x04,  0x3003);
 944
 945         wm8994_write(0x1E,  0x0006);  //LINEOUT1N_MUTE(001Eh);
 946         wm8994_write(0x34,  0x0001);  //LINEOUT1_MODE=1;LINEOUT_VMID_BUF_ENA=1;
 947
 948         wm8994_write(0x603, 0x018C);
 949         wm8994_write(0x604, 0x0010);
 950         wm8994_write(0x605, 0x0010);
 951         wm8994_write(0x621, 0x0001);
 952         wm8994_write(0x317, 0x0003);
 953
 954 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 955         wm8994_write(0x312, 0x4000);  //set 0x312 PCM2 as Master
 956         wm8994_write(0x313, 0x0090);  //master   0x0090 lrck2 8kHz bclk2 1MH
 957         wm8994_write(0x315, 0x007D);  //master   0x007D lrck2 8kHz bclk2 1MH
 958 #endif
 959
 960         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 961 }
 962
 963 void BT_baseband_and_record(void)
 964 {
 965         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 966
 967         wm8994_current_mode=wm8994_BT_baseband_and_record;
 968         wm8994_reset();
 969         mdelay(WM8994_DELAY);
 970
 971         wm8994_write(0x01, 0x0003);
 972         wm8994_write(0x02, 0x63A0);
 973         wm8994_write(0x03, 0x30A0);
 974         wm8994_write(0x04, 0x3303);
 975         wm8994_write(0x05, 0x3002);
 976         wm8994_write(0x06, 0x000A);
 977         wm8994_write(0x19, 0x014B);
 978         wm8994_write(0x1B, 0x014B);
 979         wm8994_write(0x1E, 0x0006);
 980         wm8994_write(0x28, 0x00CC);
 981         wm8994_write(0x29, 0x0100);
 982         wm8994_write(0x2A, 0x0100);
 983         wm8994_write(0x2D, 0x0001);
 984         wm8994_write(0x34, 0x0001);
 985         wm8994_write(0x200, 0x0001);
 986
 987         //roger_chen@20100524
 988         //8KHz, BCLK=8KHz*128=1024KHz, Fout=2.048MHz
 989         wm8994_write(0x204, 0x0001);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=00, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
 990         wm8994_write(0x208, 0x000F);
 991         wm8994_write(0x220, 0x0000);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=0, FLL1_OSC_ENA=0, FLL1_ENA=0
 992         wm8994_write(0x221, 0x2F00);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (2)(221H):  0700  FLL1_OUTDIV=2Fh, FLL1_CTRL_RATE=000, FLL1_FRATIO=000
 993         wm8994_write(0x222, 0x3126);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (3)(222H):  8FD5  FLL1_K=3126h
 994         wm8994_write(0x223, 0x0100);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (4)(223H):  00E0  FLL1_N=8h, FLL1_GAIN=0000
 995         wm8994_write(0x302, 0x4000);
 996         wm8994_write(0x303, 0x0090);
 997         wm8994_write(0x310, 0xC118);  //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
 998         wm8994_write(0x312, 0x4000);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Master/Slave(312H): 7000  AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
 999         wm8994_write(0x313, 0x0020);    // SMbus_16inx_16dat     Write  0x34      * AIF2 BCLK DIV--------AIF1CLK/2
1000         wm8994_write(0x314, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 ADCLRCK DIV-----BCLK/128
1001         wm8994_write(0x315, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 DACLRCK DIV-----BCLK/128
1002         wm8994_write(0x210, 0x0003);    // SMbus_16inx_16dat     Write  0x34      * SR=8KHz
1003         wm8994_write(0x220, 0x0004);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=0
1004         mdelay(WM8994_DELAY);
1005         wm8994_write(0x220, 0x0005);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=1
1006         wm8994_write(0x204, 0x0011);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1007
1008         wm8994_write(0x440, 0x0018);
1009         wm8994_write(0x450, 0x0018);
1010         wm8994_write(0x480, 0x0000);
1011         wm8994_write(0x481, 0x0000);
1012         wm8994_write(0x4A0, 0x0000);
1013         wm8994_write(0x4A1, 0x0000);
1014         wm8994_write(0x520, 0x0000);
1015         wm8994_write(0x540, 0x0018);
1016         wm8994_write(0x580, 0x0000);
1017         wm8994_write(0x581, 0x0000);
1018         wm8994_write(0x601, 0x0004);
1019         wm8994_write(0x603, 0x000C);
1020         wm8994_write(0x604, 0x0010);
1021         wm8994_write(0x605, 0x0010);
1022         wm8994_write(0x606, 0x0003);
1023         wm8994_write(0x607, 0x0003);
1024         wm8994_write(0x610, 0x01C0);
1025         wm8994_write(0x612, 0x01C0);
1026         wm8994_write(0x613, 0x01C0);
1027         wm8994_write(0x620, 0x0000);
1028
1029         //roger_chen@20100519
1030         //enable AIF2 BCLK,LRCK
1031         //Rev.B and Rev.D is different
1032         wm8994_write(0x702, 0xA100);
1033         wm8994_write(0x703, 0xA100);
1034
1035         wm8994_write(0x704, 0xA100);
1036         wm8994_write(0x707, 0xA100);
1037         wm8994_write(0x708, 0x2100);
1038         wm8994_write(0x709, 0x2100);
1039         wm8994_write(0x70A, 0x2100);
1040
1041         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1042 }
1043
1044 #else //PCM_BB
1045
1046 /******************PCM BB BEGIN*****************/
1047
1048 void handsetMIC_to_baseband_to_headset(void) //pcmbaseband
1049 {
1050         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1051
1052         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset;
1053         wm8994_reset();
1054         mdelay(50);
1055
1056         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1057         mdelay(50);
1058         wm8994_write(0x221, 0x0700);
1059         wm8994_write(0x222, 0x3127);
1060         wm8994_write(0x223, 0x0100);
1061         wm8994_write(0x220, 0x0004);
1062         mdelay(50);
1063         wm8994_write(0x220, 0x0005);
1064
1065         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);  ///0x0303);         // sysclk = fll (bit4 =1)   0x0011
1066         wm8994_write(0x02,  0x0240);
1067         wm8994_write(0x03,  0x0030);
1068         wm8994_write(0x04,  0x3003);
1069         wm8994_write(0x05,  0x3003);  // i2s 16 bits
1070         wm8994_write(0x18,  0x010B);
1071         wm8994_write(0x28,  0x0030);
1072         wm8994_write(0x29,  0x0020);
1073         wm8994_write(0x2D,  0x0100);  //0x0100);DAC1L_TO_HPOUT1L    ;;;bit 8
1074         wm8994_write(0x2E,  0x0100);  //0x0100);DAC1R_TO_HPOUT1R    ;;;bit 8
1075         wm8994_write(0x4C,  0x9F25);
1076         wm8994_write(0x60,  0x00EE);
1077         wm8994_write(0x200, 0x0001);
1078         wm8994_write(0x204, 0x0001);
1079         wm8994_write(0x208, 0x0007);
1080         wm8994_write(0x520, 0x0000);
1081         wm8994_write(0x601, 0x0004);  //AIF2DACL_TO_DAC1L
1082         wm8994_write(0x602, 0x0004);  //AIF2DACR_TO_DAC1R
1083
1084         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1085         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1086         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1087         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1088
1089         wm8994_write(0x702, 0xC100);
1090         wm8994_write(0x703, 0xC100);
1091         wm8994_write(0x704, 0xC100);
1092         wm8994_write(0x706, 0x4100);
1093         wm8994_write(0x204, 0x0011);
1094         wm8994_write(0x211, 0x0009);
1095         #ifdef TD688_MODE
1096         wm8994_write(0x310, 0x4108); ///0x4118);  ///interface dsp mode 16bit
1097         #endif
1098         #ifdef CHONGY_MODE
1099         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1100         #endif
1101         #ifdef MU301_MODE
1102         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1103         wm8994_write(0x241, 0x2f04);
1104         wm8994_write(0x242, 0x0000);
1105         wm8994_write(0x243, 0x0300);
1106         wm8994_write(0x240, 0x0004);
1107         mdelay(40);
1108         wm8994_write(0x240, 0x0005);
1109         wm8994_write(0x204, 0x0019);
1110         wm8994_write(0x211, 0x0003);
1111         wm8994_write(0x244, 0x0c83);
1112         wm8994_write(0x620, 0x0000);
1113         #endif
1114         #ifdef THINKWILL_M800_MODE
1115         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1116         #endif
1117         wm8994_write(0x313, 0x00F0);
1118         wm8994_write(0x314, 0x0020);
1119         wm8994_write(0x315, 0x0020);
1120         wm8994_write(0x603, 0x018c);  ///0x000C);  //Rev.D ADCL SideTone
1121         wm8994_write(0x604, 0x0010); //XX
1122         wm8994_write(0x605, 0x0010); //XX
1123         wm8994_write(0x621, 0x0000);  //0x0001);   ///0x0000);
1124         wm8994_write(0x317, 0x0003);
1125         wm8994_write(0x312, 0x0000); /// as slave  ///0x4000);  //AIF2 SET AS MASTER
1126
1127         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1128 }
1129
1130 void handsetMIC_to_baseband_to_headset_and_record(void) //pcmbaseband
1131 {
1132         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1133
1134         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset_and_record;
1135         wm8994_reset();
1136         mdelay(50);
1137
1138         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1139         mdelay(50);
1140         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1141         wm8994_write(0x222, 0x3127);
1142         wm8994_write(0x223, 0x0100);
1143         wm8994_write(0x220, 0x0004);
1144         mdelay(50);
1145         wm8994_write(0x220, 0x0005);
1146
1147         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);
1148         wm8994_write(0x02,  0x0240);
1149         wm8994_write(0x03,  0x0030);
1150         wm8994_write(0x04,  0x3003);
1151         wm8994_write(0x05,  0x3003);
1152         wm8994_write(0x18,  0x010B);  // 0x011F=+30dB for MIC
1153         wm8994_write(0x28,  0x0030);
1154         wm8994_write(0x29,  0x0020);
1155         wm8994_write(0x2D,  0x0100);
1156         wm8994_write(0x2E,  0x0100);
1157         wm8994_write(0x4C,  0x9F25);
1158         wm8994_write(0x60,  0x00EE);
1159         wm8994_write(0x200, 0x0001);
1160         wm8994_write(0x204, 0x0001);
1161         wm8994_write(0x208, 0x0007);
1162         wm8994_write(0x520, 0x0000);
1163         wm8994_write(0x601, 0x0004);
1164         wm8994_write(0x602, 0x0004);
1165
1166         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1167         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1168         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1169         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1170
1171         wm8994_write(0x700, 0x8141);  //SYNC issue, AIF1 ADCLRC1 from LRCK1
1172         wm8994_write(0x702, 0xC100);
1173         wm8994_write(0x703, 0xC100);
1174         wm8994_write(0x704, 0xC100);
1175         wm8994_write(0x706, 0x4100);
1176         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1177         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1178         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1179         wm8994_write(0x313, 0x00F0);
1180         wm8994_write(0x314, 0x0020);
1181         wm8994_write(0x315, 0x0020);
1182
1183         wm8994_write(0x603, 0x018c);  ///0x000C);  //Rev.D ADCL SideTone
1184         wm8994_write(0x604, 0x0010);
1185         wm8994_write(0x605, 0x0010);
1186         wm8994_write(0x621, 0x0000);
1187         //wm8994_write(0x317, 0x0003);
1188         //wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1189 ////AIF1
1190         wm8994_write(0x04,   0x3303);
1191         wm8994_write(0x200,  0x0001);
1192         wm8994_write(0x208,  0x000F);
1193         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1194         wm8994_write(0x300,  0x0118);  //DSP/PCM 16bits, R ADC = L ADC
1195         wm8994_write(0x606,  0x0003);
1196         wm8994_write(0x607,  0x0003);
1197
1198 ////AIF1 Master Clock(SR=8KHz)
1199         wm8994_write(0x200,  0x0011);
1200         wm8994_write(0x302,  0x4000);
1201         wm8994_write(0x303,  0x00F0);
1202         wm8994_write(0x304,  0x0020);
1203         wm8994_write(0x305,  0x0020);
1204
1205 ////AIF1 DAC1 HP
1206         wm8994_write(0x05,   0x3303);
1207         wm8994_write(0x420,  0x0000);
1208         wm8994_write(0x601,  0x0001);
1209         wm8994_write(0x602,  0x0001);
1210         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1211
1212         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1213 }
1214
1215 void mainMIC_to_baseband_to_earpiece(void) //pcmbaseband
1216 {
1217         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1218
1219         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
1220         wm8994_reset();
1221         mdelay(50);
1222
1223         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1224         mdelay(50);
1225         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1226         wm8994_write(0x222, 0x3127);
1227         wm8994_write(0x223, 0x0100);
1228         wm8994_write(0x220, 0x0004);
1229         mdelay(50);
1230         wm8994_write(0x220, 0x0005);
1231
1232         wm8994_write(0x01,  0x0803|wm8994_mic_VCC);   ///0x0813);
1233         wm8994_write(0x02,  0x0240);   ///0x0110);
1234         wm8994_write(0x03,  0x00F0);
1235         wm8994_write(0x04,  0x3003);
1236         wm8994_write(0x05,  0x3003);
1237         wm8994_write(0x18,  0x011F);
1238         //wm8994_write(0x1A,  0x010B);
1239         wm8994_write(0x1F,  0x0000);
1240         wm8994_write(0x28,  0x0030);  ///0x0003);
1241         wm8994_write(0x29,  0x0020);
1242         //wm8994_write(0x2A,  0x0020);
1243         wm8994_write(0x2D,  0x0001);
1244         wm8994_write(0x2E,  0x0001);
1245         wm8994_write(0x33,  0x0018);
1246         //wm8994_write(0x4C,  0x9F25);
1247         //wm8994_write(0x60,  0x00EE);
1248         wm8994_write(0x200, 0x0001);
1249         wm8994_write(0x204, 0x0001);
1250         wm8994_write(0x208, 0x0007);
1251         wm8994_write(0x520, 0x0000);
1252         wm8994_write(0x601, 0x0004);
1253         wm8994_write(0x602, 0x0004);
1254
1255         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1256         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1257         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1258         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1259
1260         //wm8994_write(0x700, 0x8141);
1261         wm8994_write(0x702, 0xC100);
1262         wm8994_write(0x703, 0xC100);
1263         wm8994_write(0x704, 0xC100);
1264         wm8994_write(0x706, 0x4100);
1265         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1266         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1267         ///wm8994_write(0x310, 0x4108); /// 0x4118);  ///0x4118);  //DSP/PCM 16bits
1268         #ifdef TD688_MODE
1269         wm8994_write(0x310, 0x4108); ///0x4118);  ///interface dsp mode 16bit
1270         #endif
1271         #ifdef CHONGY_MODE
1272         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1273         #endif
1274         #ifdef MU301_MODE
1275         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1276         wm8994_write(0x241, 0x2f04);
1277         wm8994_write(0x242, 0x0000);
1278         wm8994_write(0x243, 0x0300);
1279         wm8994_write(0x240, 0x0004);
1280         mdelay(40);
1281         wm8994_write(0x240, 0x0005);
1282         wm8994_write(0x204, 0x0019);
1283         wm8994_write(0x211, 0x0003);
1284         wm8994_write(0x244, 0x0c83);
1285         wm8994_write(0x620, 0x0000);
1286         #endif
1287         #ifdef THINKWILL_M800_MODE
1288         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1289         #endif
1290         wm8994_write(0x313, 0x00F0);
1291         wm8994_write(0x314, 0x0020);
1292         wm8994_write(0x315, 0x0020);
1293
1294         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1295         wm8994_write(0x604, 0x0010);
1296         wm8994_write(0x605, 0x0010);
1297         wm8994_write(0x621, 0x0000);  ///0x0001);
1298         wm8994_write(0x317, 0x0003);
1299         wm8994_write(0x312, 0x0000);  //AIF2 SET AS MASTER
1300
1301         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1302 }
1303
1304 void mainMIC_to_baseband_to_earpiece_and_record(void) //pcmbaseband
1305 {
1306         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1307
1308         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
1309         wm8994_reset();
1310         mdelay(50);
1311
1312         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1313         mdelay(50);
1314         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1315         wm8994_write(0x222, 0x3127);
1316         wm8994_write(0x223, 0x0100);
1317         wm8994_write(0x220, 0x0004);
1318         mdelay(50);
1319         wm8994_write(0x220, 0x0005);
1320
1321         wm8994_write(0x01,  0x0803|wm8994_mic_VCC);
1322         wm8994_write(0x02,  0x0110);
1323         wm8994_write(0x03,  0x00F0);
1324         wm8994_write(0x04,  0x3003);
1325         wm8994_write(0x05,  0x3003);
1326         wm8994_write(0x1A,  0x010B);
1327         wm8994_write(0x1F,  0x0000);
1328         wm8994_write(0x28,  0x0003);
1329         wm8994_write(0x2A,  0x0020);
1330         wm8994_write(0x2D,  0x0001);
1331         wm8994_write(0x2E,  0x0001);
1332         wm8994_write(0x33,  0x0018);
1333         //wm8994_write(0x4C,  0x9F25);
1334         //wm8994_write(0x60,  0x00EE);
1335         wm8994_write(0x200, 0x0001);
1336         wm8994_write(0x204, 0x0001);
1337         wm8994_write(0x208, 0x0007);
1338         wm8994_write(0x520, 0x0000);
1339         wm8994_write(0x601, 0x0004);
1340         wm8994_write(0x602, 0x0004);
1341
1342         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1343         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1344         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1345         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1346
1347         wm8994_write(0x702, 0xC100);
1348         wm8994_write(0x703, 0xC100);
1349         wm8994_write(0x704, 0xC100);
1350         wm8994_write(0x706, 0x4100);
1351         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1352         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1353         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1354         wm8994_write(0x313, 0x00F0);
1355         wm8994_write(0x314, 0x0020);
1356         wm8994_write(0x315, 0x0020);
1357
1358         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1359         wm8994_write(0x604, 0x0010);
1360         wm8994_write(0x605, 0x0010);
1361         wm8994_write(0x621, 0x0001);
1362         //wm8994_write(0x317, 0x0003);
1363         //wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1364
1365 ////AIF1
1366         wm8994_write(0x04,   0x3303);
1367         wm8994_write(0x200,  0x0001);
1368         wm8994_write(0x208,  0x000F);
1369         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1370         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1371         wm8994_write(0x606,  0x0003);
1372         wm8994_write(0x607,  0x0003);
1373
1374 ////AIF1 Master Clock(SR=8KHz)
1375         wm8994_write(0x200,  0x0011);
1376         wm8994_write(0x302,  0x4000);
1377         wm8994_write(0x303,  0x00F0);
1378         wm8994_write(0x304,  0x0020);
1379         wm8994_write(0x305,  0x0020);
1380
1381 ////AIF1 DAC1 HP
1382         wm8994_write(0x05,   0x3303);
1383         wm8994_write(0x420,  0x0000);
1384         wm8994_write(0x601,  0x0001);
1385         wm8994_write(0x602,  0x0001);
1386         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1387
1388         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1389 }
1390
1391 void mainMIC_to_baseband_to_speakers(void) //pcmbaseband
1392 {
1393         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1394
1395         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers;
1396         wm8994_reset();
1397         mdelay(50);
1398
1399         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);  //0x0013);
1400         mdelay(50);
1401         wm8994_write(0x221, 0x0700);  //MCLK=12MHz   //FLL1 CONTRLO(2)
1402         wm8994_write(0x222, 0x3127);  //FLL1 CONTRLO(3)
1403         wm8994_write(0x223, 0x0100);  //FLL1 CONTRLO(4)
1404         wm8994_write(0x220, 0x0004);  //FLL1 CONTRLO(1)
1405         mdelay(50);
1406         wm8994_write(0x220, 0x0005);  //FLL1 CONTRLO(1)
1407
1408         wm8994_write(0x01,  0x3003|wm8994_mic_VCC);
1409         wm8994_write(0x02,  0x0110);
1410         wm8994_write(0x03,  0x0030);  ///0x0330);
1411         wm8994_write(0x04,  0x3003);
1412         wm8994_write(0x05,  0x3003);
1413         wm8994_write(0x1A,  0x011F);
1414         wm8994_write(0x22,  0x0000);
1415         wm8994_write(0x23,  0x0100);  ///0x0000);
1416         wm8994_write(0x25,  0x0152);
1417         wm8994_write(0x28,  0x0003);
1418         wm8994_write(0x2A,  0x0020);
1419         wm8994_write(0x2D,  0x0001);
1420         wm8994_write(0x2E,  0x0001);
1421         wm8994_write(0x36,  0x000C);  //MIXOUTL_TO_SPKMIXL  MIXOUTR_TO_SPKMIXR
1422         //wm8994_write(0x4C,  0x9F25);
1423         //wm8994_write(0x60,  0x00EE);
1424         wm8994_write(0x200, 0x0001);  //AIF1 CLOCKING(1)
1425         wm8994_write(0x204, 0x0001);  //AIF2 CLOCKING(1)
1426         wm8994_write(0x208, 0x0007);  //CLOCKING(1)
1427         wm8994_write(0x520, 0x0000);  //AIF2 DAC FILTERS(1)
1428         wm8994_write(0x601, 0x0004);  //AIF2DACL_DAC1L
1429         wm8994_write(0x602, 0x0004);  //AIF2DACR_DAC1R
1430
1431         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1432         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1433         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1434         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1435
1436         wm8994_write(0x702, 0xC100);  //GPIO3
1437         wm8994_write(0x703, 0xC100);  //GPIO4
1438         wm8994_write(0x704, 0xC100);  //GPIO5
1439         wm8994_write(0x706, 0x4100);  //GPIO7
1440         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1441         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1442         #ifdef TD688_MODE
1443         wm8994_write(0x310, 0xc108); ///0x4118);  ///interface dsp mode 16bit
1444         #endif
1445         #ifdef CHONGY_MODE
1446         wm8994_write(0x310, 0xc018); ///0x4118);  ///interface dsp mode 16bit
1447         #endif
1448         #ifdef MU301_MODE
1449         wm8994_write(0x310, 0xc118); ///0x4118);  ///interface dsp mode 16bit
1450         wm8994_write(0x241, 0x2f04);
1451         wm8994_write(0x242, 0x0000);
1452         wm8994_write(0x243, 0x0300);
1453         wm8994_write(0x240, 0x0004);
1454         mdelay(40);
1455         wm8994_write(0x240, 0x0005);
1456         wm8994_write(0x204, 0x0019);
1457         wm8994_write(0x211, 0x0003);
1458         wm8994_write(0x244, 0x0c83);
1459         wm8994_write(0x620, 0x0000);
1460         #endif
1461         #ifdef THINKWILL_M800_MODE
1462         wm8994_write(0x310, 0xc118); ///0x4118);  ///interface dsp mode 16bit
1463         #endif
1464         //wm8994_write(0x310, 0xc008);  //0xC018);//  //4118);  //DSP/PCM 16bits
1465         wm8994_write(0x313, 0x00F0);  //AIF2BCLK
1466         wm8994_write(0x314, 0x0020);  //AIF2ADCLRCK
1467         wm8994_write(0x315, 0x0020);  //AIF2DACLRCLK
1468
1469         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1470         wm8994_write(0x604, 0x0020);  ///0x0010);  //ADC2_TO_DAC2L
1471         wm8994_write(0x605, 0x0020);  //0x0010);  //ADC2_TO_DAC2R
1472         wm8994_write(0x621, 0x0000);  ///0x0001);
1473         wm8994_write(0x317, 0x0003);
1474         wm8994_write(0x312, 0x0000);  //AIF2 SET AS MASTER
1475
1476         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1477 }
1478
1479 void mainMIC_to_baseband_with_AP_to_speakers(void) //pcmbaseband
1480 {
1481         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1482
1483         wm8994_current_mode=wm8994_mainMIC_to_baseband_with_AP_to_speakers;
1484         wm8994_reset();
1485         mdelay(50);
1486
1487         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);  //0x0013);
1488         mdelay(50);
1489         wm8994_write(0x221, 0x0700);  //MCLK=12MHz   //FLL1 CONTRLO(2)
1490         wm8994_write(0x222, 0x3127);  //FLL1 CONTRLO(3)
1491         wm8994_write(0x223, 0x0100);  //FLL1 CONTRLO(4)
1492         wm8994_write(0x220, 0x0004);  //FLL1 CONTRLO(1)
1493         mdelay(50);
1494         wm8994_write(0x220, 0x0005);  //FLL1 CONTRLO(1)
1495
1496         wm8994_write(0x01,  0x3003|wm8994_mic_VCC);
1497         wm8994_write(0x02,  0x0110);
1498         wm8994_write(0x03,  0x0030);  ///0x0330);
1499         wm8994_write(0x04,  0x3003);
1500         wm8994_write(0x05,  0x3003);
1501         wm8994_write(0x1A,  0x011F);
1502         wm8994_write(0x22,  0x0000);
1503         wm8994_write(0x23,  0x0100);  ///0x0000);
1504         wm8994_write(0x25,  0x0152);
1505         wm8994_write(0x28,  0x0003);
1506         wm8994_write(0x2A,  0x0020);
1507         wm8994_write(0x2D,  0x0001);
1508         wm8994_write(0x2E,  0x0001);
1509         wm8994_write(0x36,  0x000C);  //MIXOUTL_TO_SPKMIXL  MIXOUTR_TO_SPKMIXR
1510         //wm8994_write(0x4C,  0x9F25);
1511         //wm8994_write(0x60,  0x00EE);
1512         wm8994_write(0x200, 0x0001);  //AIF1 CLOCKING(1)
1513         wm8994_write(0x204, 0x0001);  //AIF2 CLOCKING(1)
1514         wm8994_write(0x208, 0x0007);  //CLOCKING(1)
1515         wm8994_write(0x520, 0x0000);  //AIF2 DAC FILTERS(1)
1516         wm8994_write(0x601, 0x0004);  //AIF2DACL_DAC1L
1517         wm8994_write(0x602, 0x0004);  //AIF2DACR_DAC1R
1518
1519         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1520         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1521         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1522         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1523
1524         wm8994_write(0x702, 0xC100);  //GPIO3
1525         wm8994_write(0x703, 0xC100);  //GPIO4
1526         wm8994_write(0x704, 0xC100);  //GPIO5
1527         wm8994_write(0x706, 0x4100);  //GPIO7
1528         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1529         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1530         #ifdef TD688_MODE
1531         wm8994_write(0x310, 0xc108); ///0x4118);  ///interface dsp mode 16bit
1532         #endif
1533         #ifdef CHONGY_MODE
1534         wm8994_write(0x310, 0xc018); ///0x4118);  ///interface dsp mode 16bit
1535         #endif
1536         #ifdef MU301_MODE
1537         wm8994_write(0x310, 0xc118); ///0x4118);  ///interface dsp mode 16bit
1538         wm8994_write(0x241, 0x2f04);
1539         wm8994_write(0x242, 0x0000);
1540         wm8994_write(0x243, 0x0300);
1541         wm8994_write(0x240, 0x0004);
1542         mdelay(40);
1543         wm8994_write(0x240, 0x0005);
1544         wm8994_write(0x204, 0x0019);
1545         wm8994_write(0x211, 0x0003);
1546         wm8994_write(0x244, 0x0c83);
1547         wm8994_write(0x620, 0x0000);
1548         #endif
1549         #ifdef THINKWILL_M800_MODE
1550         wm8994_write(0x310, 0xc118); ///0x4118);  ///interface dsp mode 16bit
1551         #endif
1552         //wm8994_write(0x310, 0xc008);  //0xC018);//  //4118);  //DSP/PCM 16bits
1553         wm8994_write(0x313, 0x00F0);  //AIF2BCLK
1554         wm8994_write(0x314, 0x0020);  //AIF2ADCLRCK
1555         wm8994_write(0x315, 0x0020);  //AIF2DACLRCLK
1556
1557         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1558         wm8994_write(0x604, 0x0020);  ///0x0010);  //ADC2_TO_DAC2L
1559         wm8994_write(0x605, 0x0020);  //0x0010);  //ADC2_TO_DAC2R
1560         wm8994_write(0x621, 0x0000);  ///0x0001);
1561         wm8994_write(0x317, 0x0003);
1562         wm8994_write(0x312, 0x0000);  //AIF2 SET AS MASTER
1563
1564         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1565 }
1566
1567 void mainMIC_to_baseband_to_speakers_and_record(void) //pcmbaseband
1568 {
1569         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1570
1571         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
1572         wm8994_reset();
1573         mdelay(50);
1574
1575         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1576         mdelay(50);
1577         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1578         wm8994_write(0x222, 0x3127);
1579         wm8994_write(0x223, 0x0100);
1580         wm8994_write(0x220, 0x0004);
1581         mdelay(50);
1582         wm8994_write(0x220, 0x0005);
1583
1584         wm8994_write(0x02,  0x0110);
1585         wm8994_write(0x03,  0x0330);
1586         wm8994_write(0x04,  0x3003);
1587         wm8994_write(0x05,  0x3003);
1588         wm8994_write(0x1A,  0x010B);
1589         wm8994_write(0x22,  0x0000);
1590         wm8994_write(0x23,  0x0000);
1591         wm8994_write(0x28,  0x0003);
1592         wm8994_write(0x2A,  0x0020);
1593         wm8994_write(0x2D,  0x0001);
1594         wm8994_write(0x2E,  0x0001);
1595         wm8994_write(0x36,  0x000C);
1596         //wm8994_write(0x4C,  0x9F25);
1597         //wm8994_write(0x60,  0x00EE);
1598         wm8994_write(0x200, 0x0001);
1599         wm8994_write(0x204, 0x0001);
1600         wm8994_write(0x208, 0x0007);
1601         wm8994_write(0x520, 0x0000);
1602         wm8994_write(0x601, 0x0004);
1603         wm8994_write(0x602, 0x0004);
1604
1605         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1606         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1607         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1608         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1609
1610         wm8994_write(0x700, 0x8141);
1611         wm8994_write(0x702, 0xC100);
1612         wm8994_write(0x703, 0xC100);
1613         wm8994_write(0x704, 0xC100);
1614         wm8994_write(0x706, 0x4100);
1615         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1616         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1617         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1618         wm8994_write(0x313, 0x00F0);
1619         wm8994_write(0x314, 0x0020);
1620         wm8994_write(0x315, 0x0020);
1621
1622         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1623         wm8994_write(0x604, 0x0010);
1624         wm8994_write(0x605, 0x0010);
1625         wm8994_write(0x621, 0x0001);
1626         //wm8994_write(0x317, 0x0003);
1627         //wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1628
1629 ////AIF1
1630         wm8994_write(0x04,   0x3303);
1631         wm8994_write(0x200,  0x0001);
1632         wm8994_write(0x208,  0x000F);
1633         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1634         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1635         wm8994_write(0x606,  0x0003);
1636         wm8994_write(0x607,  0x0003);
1637
1638 ////AIF1 Master Clock(SR=8KHz)
1639         wm8994_write(0x200,  0x0011);
1640         wm8994_write(0x302,  0x4000);
1641         wm8994_write(0x303,  0x00F0);
1642         wm8994_write(0x304,  0x0020);
1643         wm8994_write(0x305,  0x0020);
1644
1645 ////AIF1 DAC1 HP
1646         wm8994_write(0x05,   0x3303);
1647         wm8994_write(0x420,  0x0000);
1648         wm8994_write(0x601,  0x0001);
1649         wm8994_write(0x602,  0x0001);
1650         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1651
1652         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1653 }
1654
1655 void BT_baseband(void) //pcmbaseband
1656 {
1657         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1658
1659         wm8994_current_mode=wm8994_BT_baseband;
1660         wm8994_reset();
1661         mdelay(50);
1662
1663         wm8994_write(0x01 ,0x0003);
1664         mdelay (50);
1665
1666         wm8994_write(0x200 ,0x0001);
1667         wm8994_write(0x221 ,0x0700);//MCLK=12MHz
1668         wm8994_write(0x222 ,0x3127);
1669         wm8994_write(0x223 ,0x0100);
1670         wm8994_write(0x220 ,0x0004);
1671         mdelay (50);
1672         wm8994_write(0x220 ,0x0005);
1673
1674         wm8994_write(0x02 ,0x0000);
1675         wm8994_write(0x200 ,0x0011);// AIF1 MCLK=FLL1
1676         wm8994_write(0x210 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1677         wm8994_write(0x300 ,0x4018);// DSP/PCM 16bits
1678
1679         wm8994_write(0x204 ,0x0011);// AIF2 MCLK=FLL1
1680         wm8994_write(0x211 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1681         wm8994_write(0x310 ,0x4118);// DSP/PCM 16bits
1682         wm8994_write(0x208 ,0x000F);
1683
1684 /////AIF1
1685         wm8994_write(0x700 ,0x8101);
1686 /////AIF2
1687         wm8994_write(0x702 ,0xC100);
1688         wm8994_write(0x703 ,0xC100);
1689         wm8994_write(0x704 ,0xC100);
1690         wm8994_write(0x706 ,0x4100);
1691 /////AIF3
1692         wm8994_write(0x707 ,0xA100);
1693         wm8994_write(0x708 ,0xA100);
1694         wm8994_write(0x709 ,0xA100);
1695         wm8994_write(0x70A ,0xA100);
1696
1697         wm8994_write(0x06 ,0x0001);
1698
1699         wm8994_write(0x02 ,0x0300);
1700         wm8994_write(0x03 ,0x0030);
1701         wm8994_write(0x04 ,0x3301);//ADCL off
1702         wm8994_write(0x05 ,0x3301);//DACL off
1703
1704 //      wm8994_write(0x29 ,0x0005);
1705         wm8994_write(0x2A ,0x0005);
1706
1707         wm8994_write(0x313 ,0x00F0);
1708         wm8994_write(0x314 ,0x0020);
1709         wm8994_write(0x315 ,0x0020);
1710
1711 //      wm8994_write(0x2D ,0x0001);
1712         wm8994_write(0x2E ,0x0001);
1713         wm8994_write(0x420 ,0x0000);
1714         wm8994_write(0x520 ,0x0000);
1715         wm8994_write(0x601 ,0x0001);
1716         wm8994_write(0x602 ,0x0001);
1717         wm8994_write(0x604 ,0x0001);
1718         wm8994_write(0x605 ,0x0001);
1719 //      wm8994_write(0x606 ,0x0002);
1720         wm8994_write(0x607 ,0x0002);
1721 //      wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1722         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1723         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1724         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1725
1726
1727         wm8994_write(0x312 ,0x4000);
1728
1729         wm8994_write(0x606 ,0x0001);
1730         wm8994_write(0x607 ,0x0003);//R channel for data mix/CPU record data
1731
1732
1733 ////////////HP output test
1734         wm8994_write(0x01 ,0x0303);
1735         wm8994_write(0x4C ,0x9F25);
1736         wm8994_write(0x60 ,0x00EE);
1737 ///////////end HP test
1738
1739         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1740 }
1741
1742 void BT_baseband_and_record(void) //pcmbaseband
1743 {
1744         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1745
1746         wm8994_current_mode=wm8994_BT_baseband_and_record;
1747         wm8994_reset();
1748         mdelay(50);
1749
1750         wm8994_write(0x01  ,0x0003);
1751         mdelay (50);
1752
1753         wm8994_write(0x200 ,0x0001);
1754         wm8994_write(0x221 ,0x0700);//MCLK=12MHz
1755         wm8994_write(0x222 ,0x3127);
1756         wm8994_write(0x223 ,0x0100);
1757         wm8994_write(0x220 ,0x0004);
1758         mdelay (50);
1759         wm8994_write(0x220 ,0x0005);
1760
1761         wm8994_write(0x02 ,0x0000);
1762         wm8994_write(0x200 ,0x0011);// AIF1 MCLK=FLL1
1763         wm8994_write(0x210 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1764         wm8994_write(0x300 ,0x4018);// DSP/PCM 16bits
1765
1766         wm8994_write(0x204 ,0x0011);// AIF2 MCLK=FLL1
1767         wm8994_write(0x211 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1768         wm8994_write(0x310 ,0x4118);// DSP/PCM 16bits
1769         wm8994_write(0x208 ,0x000F);
1770
1771 /////AIF1
1772         wm8994_write(0x700 ,0x8101);
1773 /////AIF2
1774         wm8994_write(0x702 ,0xC100);
1775         wm8994_write(0x703 ,0xC100);
1776         wm8994_write(0x704 ,0xC100);
1777         wm8994_write(0x706 ,0x4100);
1778 /////AIF3
1779         wm8994_write(0x707 ,0xA100);
1780         wm8994_write(0x708 ,0xA100);
1781         wm8994_write(0x709 ,0xA100);
1782         wm8994_write(0x70A ,0xA100);
1783
1784         wm8994_write(0x06 ,0x0001);
1785
1786         wm8994_write(0x02 ,0x0300);
1787         wm8994_write(0x03 ,0x0030);
1788         wm8994_write(0x04 ,0x3301);//ADCL off
1789         wm8994_write(0x05 ,0x3301);//DACL off
1790
1791 //   wm8994_write(0x29 ,0x0005);
1792         wm8994_write(0x2A ,0x0005);
1793
1794         wm8994_write(0x313 ,0x00F0);
1795         wm8994_write(0x314 ,0x0020);
1796         wm8994_write(0x315 ,0x0020);
1797
1798 //   wm8994_write(0x2D ,0x0001);
1799         wm8994_write(0x2E ,0x0001);
1800         wm8994_write(0x420 ,0x0000);
1801         wm8994_write(0x520 ,0x0000);
1802 //  wm8994_write(0x601 ,0x0001);
1803         wm8994_write(0x602 ,0x0001);
1804         wm8994_write(0x604 ,0x0001);
1805         wm8994_write(0x605 ,0x0001);
1806 //  wm8994_write(0x606 ,0x0002);
1807         wm8994_write(0x607 ,0x0002);
1808 //      wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1809         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1810         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1811         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1812
1813
1814         wm8994_write(0x312 ,0x4000);
1815
1816         wm8994_write(0x606 ,0x0001);
1817         wm8994_write(0x607 ,0x0003);//R channel for data mix/CPU record data
1818
1819
1820 ////////////HP output test
1821         wm8994_write(0x01 ,0x0303);
1822         wm8994_write(0x4C ,0x9F25);
1823         wm8994_write(0x60 ,0x00EE);
1824 ///////////end HP test
1825
1826         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1827 }
1828 #endif //PCM_BB
1829
1830
1831 typedef void (wm8994_codec_fnc_t) (void);
1832
1833 wm8994_codec_fnc_t *wm8994_codec_sequence[] = {
1834         AP_to_headset,
1835         AP_to_speakers,
1836         recorder,
1837         recorder_and_AP_to_headset,
1838         recorder_and_AP_to_speakers,
1839         FM_to_headset,
1840         FM_to_headset_and_record,
1841         FM_to_speakers,
1842         FM_to_speakers_and_record,
1843         handsetMIC_to_baseband_to_headset,
1844         handsetMIC_to_baseband_to_headset_and_record,
1845         mainMIC_to_baseband_to_earpiece,
1846         mainMIC_to_baseband_to_earpiece_and_record,
1847         mainMIC_to_baseband_to_speakers,
1848         mainMIC_to_baseband_to_speakers_and_record,
1849         BT_baseband,
1850         BT_baseband_and_record,
1851 };
1852
1853 /********************set wm8994 volume*****volume=0\1\2\3\4\5\6\7*******************/
1854
1855 void wm8994_codec_set_volume(unsigned char system_type,unsigned char volume)
1856 {
1857         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1858
1859         if(system_type == VOICE_CALL||system_type == BLUETOOTH_SCO )
1860         {
1861                 if(volume<=call_maxvol)
1862                         call_vol=volume;
1863                 else{
1864                         printk("%s----%d::call volume more than max value 7\n",__FUNCTION__,__LINE__);
1865                         call_vol=call_maxvol;
1866                 }
1867                 if(wm8994_current_mode<null&&wm8994_current_mode>=wm8994_handsetMIC_to_baseband_to_headset)
1868                         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1869         }
1870         else
1871                 printk("%s----%d::system type error!\n",__FUNCTION__,__LINE__);
1872 }
1873
1874 void wm8994_set_volume(unsigned char wm8994_mode,unsigned char volume,unsigned char max_volume)
1875 {
1876         unsigned short lvol=0,rvol=0;
1877
1878         if(volume>max_volume)volume=max_volume;
1879
1880         if(wm8994_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record||
1881         wm8994_mode==wm8994_handsetMIC_to_baseband_to_headset)
1882         {
1883                 wm8994_read(0x001C, &lvol);
1884                 wm8994_read(0x001D, &rvol);
1885                 //HPOUT1L_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1886                 wm8994_write(0x001C, (lvol&~0x003f)|headset_vol_table[volume]);
1887                 //HPOUT1R_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1888                 wm8994_write(0x001D, (lvol&~0x003f)|headset_vol_table[volume]);
1889         }
1890         else if(wm8994_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record||
1891         wm8994_mode==wm8994_mainMIC_to_baseband_to_speakers||
1892         wm8994_mode==wm8994_mainMIC_to_baseband_with_AP_to_speakers)
1893         {
1894                 wm8994_read(0x0026, &lvol);
1895                 wm8994_read(0x0027, &rvol);
1896                 //SPKOUTL_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1897                 wm8994_write(0x0026, (lvol&~0x003f)|speakers_vol_table[volume]);
1898                 //SPKOUTR_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1899                 wm8994_write(0x0027, (lvol&~0x003f)|speakers_vol_table[volume]);
1900         }
1901         else if(wm8994_mode==wm8994_mainMIC_to_baseband_to_earpiece||
1902         wm8994_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)
1903         {
1904                 wm8994_read(0x0020, &lvol);
1905                 wm8994_read(0x0021, &rvol);
1906                 //MIXOUTL_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1907                 wm8994_write(0x0020, (lvol&~0x003f)|earpiece_vol_table[volume]);
1908                 //MIXOUTR_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1909                 wm8994_write(0x0021, (lvol&~0x003f)|earpiece_vol_table[volume]);
1910         }
1911         else if(wm8994_mode==wm8994_BT_baseband||wm8994_mode==wm8994_BT_baseband_and_record)
1912         {
1913                 wm8994_read(0x0019, &lvol);
1914                 wm8994_read(0x001b, &rvol);
1915                 //bit 0~4 /-16.5dB to +30dB in 1.5dB steps
1916                 wm8994_write(0x0019, (lvol&~0x000f)|BT_vol_table[volume]);
1917                 //bit 0~4 /-16.5dB to +30dB in 1.5dB steps
1918                 wm8994_write(0x001b, (lvol&~0x000f)|BT_vol_table[volume]);
1919         }
1920 }
1921
1922 #define SOC_DOUBLE_SWITCH_WM8994CODEC(xname, route) \
1923 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
1924         .info = snd_soc_info_route, \
1925         .get = snd_soc_get_route, .put = snd_soc_put_route, \
1926         .private_value = route }
1927
1928 int snd_soc_info_route(struct snd_kcontrol *kcontrol,
1929         struct snd_ctl_elem_info *uinfo)
1930 {
1931         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1932
1933         uinfo->count = 1;
1934         uinfo->value.integer.min = 0;
1935         uinfo->value.integer.max = 0;
1936         return 0;
1937 }
1938
1939 int snd_soc_get_route(struct snd_kcontrol *kcontrol,
1940         struct snd_ctl_elem_value *ucontrol)
1941 {
1942         return 0;
1943 }
1944
1945 int snd_soc_put_route(struct snd_kcontrol *kcontrol,
1946         struct snd_ctl_elem_value *ucontrol)
1947 {
1948
1949         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1950         int route = kcontrol->private_value & 0xff;
1951
1952         switch(route)
1953         {
1954                 /* Speaker*/
1955                 case SPEAKER_NORMAL: //AP-> 8994Codec -> Speaker
1956                     AP_to_speakers();
1957                     break;
1958                 case SPEAKER_INCALL: //BB-> 8994Codec -> Speaker
1959                     mainMIC_to_baseband_with_AP_to_speakers();
1960                     break;
1961
1962                 /* Headset */
1963                 case HEADSET_NORMAL:    //AP-> 8994Codec -> Headset
1964                     AP_to_headset();
1965                     break;
1966                 case HEADSET_INCALL:    //AP-> 8994Codec -> Headset
1967                     handsetMIC_to_baseband_to_headset();
1968                     break;
1969
1970                 /* Earpiece*/
1971                 case EARPIECE_INCALL:   //:BB-> 8994Codec -> EARPIECE
1972                     mainMIC_to_baseband_to_earpiece();
1973                     break;
1974
1975                 /* BLUETOOTH_SCO*/
1976                 case BLUETOOTH_SCO_INCALL:      //BB-> 8994Codec -> BLUETOOTH_SCO
1977                     BT_baseband();
1978                     break;
1979
1980                 /* BLUETOOTH_A2DP*/
1981                 case BLUETOOTH_A2DP_NORMAL:     //AP-> 8994Codec -> BLUETOOTH_A2DP
1982                     break;
1983
1984                 case MIC_CAPTURE:
1985                     if(wm8994_current_mode==wm8994_AP_to_headset||
1986                         wm8994_current_mode==wm8994_recorder_and_AP_to_headset)
1987                         recorder_and_AP_to_headset();
1988                     else if(wm8994_current_mode==wm8994_AP_to_speakers||
1989                         wm8994_current_mode==wm8994_recorder_and_AP_to_speakers)
1990                         recorder_and_AP_to_speakers();
1991                     else{
1992                         recorder_and_AP_to_speakers();
1993                         printk("%s--%d--: wm8994 with null mode\n",__FUNCTION__,__LINE__);
1994                     }
1995
1996                     break;
1997
1998                 default:
1999                     //codec_daout_route();
2000                     break;
2001         }
2002         return 0;
2003 }
2004
2005 /*
2006  * WM8994 Controls
2007  */
2008
2009 static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
2010 static const struct soc_enum bass_boost =
2011         SOC_ENUM_SINGLE(WM8994_BASS, 7, 2, bass_boost_txt);
2012
2013 static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
2014 static const struct soc_enum bass_filter =
2015         SOC_ENUM_SINGLE(WM8994_BASS, 6, 2, bass_filter_txt);
2016
2017 static const char *treble_txt[] = {"8kHz", "4kHz"};
2018 static const struct soc_enum treble =
2019         SOC_ENUM_SINGLE(WM8994_TREBLE, 6, 2, treble_txt);
2020
2021 static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
2022 static const struct soc_enum stereo_3d_lc =
2023         SOC_ENUM_SINGLE(WM8994_3D, 5, 2, stereo_3d_lc_txt);
2024
2025 static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
2026 static const struct soc_enum stereo_3d_uc =
2027         SOC_ENUM_SINGLE(WM8994_3D, 6, 2, stereo_3d_uc_txt);
2028
2029 static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
2030 static const struct soc_enum stereo_3d_func =
2031         SOC_ENUM_SINGLE(WM8994_3D, 7, 2, stereo_3d_func_txt);
2032
2033 static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
2034 static const struct soc_enum alc_func =
2035         SOC_ENUM_SINGLE(WM8994_ALC1, 7, 4, alc_func_txt);
2036
2037 static const char *ng_type_txt[] = {"Constant PGA Gain",
2038                                     "Mute ADC Output"};
2039 static const struct soc_enum ng_type =
2040         SOC_ENUM_SINGLE(WM8994_NGATE, 1, 2, ng_type_txt);
2041
2042 static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
2043 static const struct soc_enum deemph =
2044         SOC_ENUM_SINGLE(WM8994_ADCDAC, 1, 4, deemph_txt);
2045
2046 static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
2047                                    "L + R Invert"};
2048 static const struct soc_enum adcpol =
2049         SOC_ENUM_SINGLE(WM8994_ADCDAC, 5, 4, adcpol_txt);
2050
2051 static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
2052 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
2053 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
2054 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
2055 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
2056
2057 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
2058
2059 /* 鍠囧彮 */
2060 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker incall Switch", SPEAKER_INCALL),
2061 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker normal Switch", SPEAKER_NORMAL),
2062 /* 鍚瓛 */
2063 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece incall Switch", EARPIECE_INCALL),
2064 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece normal Switch", EARPIECE_NORMAL),
2065 /* 鑰虫満 */
2066 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset incall Switch", HEADSET_INCALL),
2067 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset normal Switch", HEADSET_NORMAL),
2068 /* 钃濈墮SCO */
2069 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth incall Switch", BLUETOOTH_SCO_INCALL),
2070 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth normal Switch", BLUETOOTH_SCO_NORMAL),
2071 /* 钃濈墮A2DP */
2072 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP incall Switch", BLUETOOTH_A2DP_INCALL),
2073 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP normal Switch", BLUETOOTH_A2DP_NORMAL),
2074 /* 鑰抽害 */
2075 SOC_DOUBLE_SWITCH_WM8994CODEC("Capture Switch", MIC_CAPTURE),
2076
2077 };
2078
2079 /*
2080  * DAPM Controls
2081  */
2082
2083 static int wm8994_lrc_control(struct snd_soc_dapm_widget *w,
2084                               struct snd_kcontrol *kcontrol, int event)
2085 {
2086         return 0;
2087 }
2088
2089 static const char *wm8994_line_texts[] = {
2090         "Line 1", "Line 2", "PGA", "Differential"};
2091
2092 static const unsigned int wm8994_line_values[] = {
2093         0, 1, 3, 4};
2094
2095 static const struct soc_enum wm8994_lline_enum =
2096         SOC_VALUE_ENUM_SINGLE(WM8994_LOUTM1, 0, 7,
2097                               ARRAY_SIZE(wm8994_line_texts),
2098                               wm8994_line_texts,
2099                               wm8994_line_values);
2100 static const struct snd_kcontrol_new wm8994_left_line_controls =
2101         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
2102
2103 static const struct soc_enum wm8994_rline_enum =
2104         SOC_VALUE_ENUM_SINGLE(WM8994_ROUTM1, 0, 7,
2105                               ARRAY_SIZE(wm8994_line_texts),
2106                               wm8994_line_texts,
2107                               wm8994_line_values);
2108 static const struct snd_kcontrol_new wm8994_right_line_controls =
2109         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
2110
2111 /* Left Mixer */
2112 static const struct snd_kcontrol_new wm8994_left_mixer_controls[] = {
2113         SOC_DAPM_SINGLE("Playback Switch", WM8994_LOUTM1, 8, 1, 0),
2114         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_LOUTM1, 7, 1, 0),
2115         SOC_DAPM_SINGLE("Right Playback Switch", WM8994_LOUTM2, 8, 1, 0),
2116         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_LOUTM2, 7, 1, 0),
2117 };
2118
2119 /* Right Mixer */
2120 static const struct snd_kcontrol_new wm8994_right_mixer_controls[] = {
2121         SOC_DAPM_SINGLE("Left Playback Switch", WM8994_ROUTM1, 8, 1, 0),
2122         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_ROUTM1, 7, 1, 0),
2123         SOC_DAPM_SINGLE("Playback Switch", WM8994_ROUTM2, 8, 1, 0),
2124         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_ROUTM2, 7, 1, 0),
2125 };
2126
2127 static const char *wm8994_pga_sel[] = {"Line 1", "Line 2", "Differential"};
2128 static const unsigned int wm8994_pga_val[] = { 0, 1, 3 };
2129
2130 /* Left PGA Mux */
2131 static const struct soc_enum wm8994_lpga_enum =
2132         SOC_VALUE_ENUM_SINGLE(WM8994_LADCIN, 6, 3,
2133                               ARRAY_SIZE(wm8994_pga_sel),
2134                               wm8994_pga_sel,
2135                               wm8994_pga_val);
2136 static const struct snd_kcontrol_new wm8994_left_pga_controls =
2137         SOC_DAPM_VALUE_ENUM("Route", wm8994_lpga_enum);
2138
2139 /* Right PGA Mux */
2140 static const struct soc_enum wm8994_rpga_enum =
2141         SOC_VALUE_ENUM_SINGLE(WM8994_RADCIN, 6, 3,
2142                               ARRAY_SIZE(wm8994_pga_sel),
2143                               wm8994_pga_sel,
2144                               wm8994_pga_val);
2145 static const struct snd_kcontrol_new wm8994_right_pga_controls =
2146         SOC_DAPM_VALUE_ENUM("Route", wm8994_rpga_enum);
2147
2148 /* Differential Mux */
2149 static const char *wm8994_diff_sel[] = {"Line 1", "Line 2"};
2150 static const struct soc_enum diffmux =
2151         SOC_ENUM_SINGLE(WM8994_ADCIN, 8, 2, wm8994_diff_sel);
2152 static const struct snd_kcontrol_new wm8994_diffmux_controls =
2153         SOC_DAPM_ENUM("Route", diffmux);
2154
2155 /* Mono ADC Mux */
2156 static const char *wm8994_mono_mux[] = {"Stereo", "Mono (Left)",
2157         "Mono (Right)", "Digital Mono"};
2158 static const struct soc_enum monomux =
2159         SOC_ENUM_SINGLE(WM8994_ADCIN, 6, 4, wm8994_mono_mux);
2160 static const struct snd_kcontrol_new wm8994_monomux_controls =
2161         SOC_DAPM_ENUM("Route", monomux);
2162
2163 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
2164         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8994_PWR1, 1, 0),
2165
2166         SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
2167                 &wm8994_diffmux_controls),
2168         SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
2169                 &wm8994_monomux_controls),
2170         SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
2171                 &wm8994_monomux_controls),
2172
2173         SND_SOC_DAPM_MUX("Left PGA Mux", WM8994_PWR1, 5, 0,
2174                 &wm8994_left_pga_controls),
2175         SND_SOC_DAPM_MUX("Right PGA Mux", WM8994_PWR1, 4, 0,
2176                 &wm8994_right_pga_controls),
2177
2178         SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
2179                 &wm8994_left_line_controls),
2180         SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
2181                 &wm8994_right_line_controls),
2182
2183         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8994_PWR1, 2, 0),
2184         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8994_PWR1, 3, 0),
2185
2186         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8994_PWR2, 7, 0),
2187         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8994_PWR2, 8, 0),
2188
2189         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
2190                 &wm8994_left_mixer_controls[0],
2191                 ARRAY_SIZE(wm8994_left_mixer_controls)),
2192         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
2193                 &wm8994_right_mixer_controls[0],
2194                 ARRAY_SIZE(wm8994_right_mixer_controls)),
2195
2196         SND_SOC_DAPM_PGA("Right Out 2", WM8994_PWR2, 3, 0, NULL, 0),
2197         SND_SOC_DAPM_PGA("Left Out 2", WM8994_PWR2, 4, 0, NULL, 0),
2198         SND_SOC_DAPM_PGA("Right Out 1", WM8994_PWR2, 5, 0, NULL, 0),
2199         SND_SOC_DAPM_PGA("Left Out 1", WM8994_PWR2, 6, 0, NULL, 0),
2200
2201         SND_SOC_DAPM_POST("LRC control", wm8994_lrc_control),
2202
2203         SND_SOC_DAPM_OUTPUT("LOUT1"),
2204         SND_SOC_DAPM_OUTPUT("ROUT1"),
2205         SND_SOC_DAPM_OUTPUT("LOUT2"),
2206         SND_SOC_DAPM_OUTPUT("ROUT2"),
2207         SND_SOC_DAPM_OUTPUT("VREF"),
2208
2209         SND_SOC_DAPM_INPUT("LINPUT1"),
2210         SND_SOC_DAPM_INPUT("LINPUT2"),
2211         SND_SOC_DAPM_INPUT("RINPUT1"),
2212         SND_SOC_DAPM_INPUT("RINPUT2"),
2213 };
2214
2215 static const struct snd_soc_dapm_route audio_map[] = {
2216
2217         { "Left Line Mux", "Line 1", "LINPUT1" },
2218         { "Left Line Mux", "Line 2", "LINPUT2" },
2219         { "Left Line Mux", "PGA", "Left PGA Mux" },
2220         { "Left Line Mux", "Differential", "Differential Mux" },
2221
2222         { "Right Line Mux", "Line 1", "RINPUT1" },
2223         { "Right Line Mux", "Line 2", "RINPUT2" },
2224         { "Right Line Mux", "PGA", "Right PGA Mux" },
2225         { "Right Line Mux", "Differential", "Differential Mux" },
2226
2227         { "Left PGA Mux", "Line 1", "LINPUT1" },
2228         { "Left PGA Mux", "Line 2", "LINPUT2" },
2229         { "Left PGA Mux", "Differential", "Differential Mux" },
2230
2231         { "Right PGA Mux", "Line 1", "RINPUT1" },
2232         { "Right PGA Mux", "Line 2", "RINPUT2" },
2233         { "Right PGA Mux", "Differential", "Differential Mux" },
2234
2235         { "Differential Mux", "Line 1", "LINPUT1" },
2236         { "Differential Mux", "Line 1", "RINPUT1" },
2237         { "Differential Mux", "Line 2", "LINPUT2" },
2238         { "Differential Mux", "Line 2", "RINPUT2" },
2239
2240         { "Left ADC Mux", "Stereo", "Left PGA Mux" },
2241         { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
2242         { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
2243
2244         { "Right ADC Mux", "Stereo", "Right PGA Mux" },
2245         { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
2246         { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
2247
2248         { "Left ADC", NULL, "Left ADC Mux" },
2249         { "Right ADC", NULL, "Right ADC Mux" },
2250
2251         { "Left Line Mux", "Line 1", "LINPUT1" },
2252         { "Left Line Mux", "Line 2", "LINPUT2" },
2253         { "Left Line Mux", "PGA", "Left PGA Mux" },
2254         { "Left Line Mux", "Differential", "Differential Mux" },
2255
2256         { "Right Line Mux", "Line 1", "RINPUT1" },
2257         { "Right Line Mux", "Line 2", "RINPUT2" },
2258         { "Right Line Mux", "PGA", "Right PGA Mux" },
2259         { "Right Line Mux", "Differential", "Differential Mux" },
2260
2261         { "Left Mixer", "Playback Switch", "Left DAC" },
2262         { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
2263         { "Left Mixer", "Right Playback Switch", "Right DAC" },
2264         { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
2265
2266         { "Right Mixer", "Left Playback Switch", "Left DAC" },
2267         { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
2268         { "Right Mixer", "Playback Switch", "Right DAC" },
2269         { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
2270
2271         { "Left Out 1", NULL, "Left Mixer" },
2272         { "LOUT1", NULL, "Left Out 1" },
2273         { "Right Out 1", NULL, "Right Mixer" },
2274         { "ROUT1", NULL, "Right Out 1" },
2275
2276         { "Left Out 2", NULL, "Left Mixer" },
2277         { "LOUT2", NULL, "Left Out 2" },
2278         { "Right Out 2", NULL, "Right Mixer" },
2279         { "ROUT2", NULL, "Right Out 2" },
2280 };
2281
2282 struct _coeff_div {
2283         u32 mclk;
2284         u32 rate;
2285         u16 fs;
2286         u8 sr:5;
2287         u8 usb:1;
2288 };
2289
2290 /* codec hifi mclk clock divider coefficients */
2291 static const struct _coeff_div coeff_div[] = {
2292         /* 8k */
2293         {12288000, 8000, 1536, 0x6, 0x0},
2294         {11289600, 8000, 1408, 0x16, 0x0},
2295         {18432000, 8000, 2304, 0x7, 0x0},
2296         {16934400, 8000, 2112, 0x17, 0x0},
2297         {12000000, 8000, 1500, 0x6, 0x1},
2298
2299         /* 11.025k */
2300         {11289600, 11025, 1024, 0x18, 0x0},
2301         {16934400, 11025, 1536, 0x19, 0x0},
2302         {12000000, 11025, 1088, 0x19, 0x1},
2303
2304         /* 16k */
2305         {12288000, 16000, 768, 0xa, 0x0},
2306         {18432000, 16000, 1152, 0xb, 0x0},
2307         {12000000, 16000, 750, 0xa, 0x1},
2308
2309         /* 22.05k */
2310         {11289600, 22050, 512, 0x1a, 0x0},
2311         {16934400, 22050, 768, 0x1b, 0x0},
2312         {12000000, 22050, 544, 0x1b, 0x1},
2313
2314         /* 32k */
2315         {12288000, 32000, 384, 0xc, 0x0},
2316         {18432000, 32000, 576, 0xd, 0x0},
2317         {12000000, 32000, 375, 0xa, 0x1},
2318
2319         /* 44.1k */
2320         {11289600, 44100, 256, 0x10, 0x0},
2321         {16934400, 44100, 384, 0x11, 0x0},
2322         {12000000, 44100, 272, 0x11, 0x1},
2323
2324         /* 48k */
2325         {12288000, 48000, 256, 0x0, 0x0},
2326         {18432000, 48000, 384, 0x1, 0x0},
2327         {12000000, 48000, 250, 0x0, 0x1},
2328
2329         /* 88.2k */
2330         {11289600, 88200, 128, 0x1e, 0x0},
2331         {16934400, 88200, 192, 0x1f, 0x0},
2332         {12000000, 88200, 136, 0x1f, 0x1},
2333
2334         /* 96k */
2335         {12288000, 96000, 128, 0xe, 0x0},
2336         {18432000, 96000, 192, 0xf, 0x0},
2337         {12000000, 96000, 125, 0xe, 0x1},
2338 };
2339
2340
2341 static inline int get_coeff(int mclk, int rate)
2342 {
2343         int i;
2344
2345         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
2346                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
2347                         return i;
2348         }
2349
2350         return -EINVAL;
2351 }
2352
2353 /* The set of rates we can generate from the above for each SYSCLK */
2354
2355 static unsigned int rates_12288[] = {
2356         8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
2357 };
2358
2359 static struct snd_pcm_hw_constraint_list constraints_12288 = {
2360         .count  = ARRAY_SIZE(rates_12288),
2361         .list   = rates_12288,
2362 };
2363
2364 static unsigned int rates_112896[] = {
2365         8000, 11025, 22050, 44100,
2366 };
2367
2368 static struct snd_pcm_hw_constraint_list constraints_112896 = {
2369         .count  = ARRAY_SIZE(rates_112896),
2370         .list   = rates_112896,
2371 };
2372
2373 static unsigned int rates_12[] = {
2374         8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
2375         48000, 88235, 96000,
2376 };
2377
2378 static struct snd_pcm_hw_constraint_list constraints_12 = {
2379         .count  = ARRAY_SIZE(rates_12),
2380         .list   = rates_12,
2381 };
2382
2383 /*
2384  * Note that this should be called from init rather than from hw_params.
2385  */
2386 static int wm8994_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2387                 int clk_id, unsigned int freq, int dir)
2388 {
2389         struct snd_soc_codec *codec = codec_dai->codec;
2390         struct wm8994_priv *wm8994 = codec->private_data;
2391
2392         DBG("%s----%d\n",__FUNCTION__,__LINE__);
2393
2394         switch (freq) {
2395         case 11289600:
2396         case 18432000:
2397         case 22579200:
2398         case 36864000:
2399                 wm8994->sysclk_constraints = &constraints_112896;
2400                 wm8994->sysclk = freq;
2401                 return 0;
2402
2403         case 12288000:
2404         case 16934400:
2405         case 24576000:
2406         case 33868800:
2407                 wm8994->sysclk_constraints = &constraints_12288;
2408                 wm8994->sysclk = freq;
2409                 return 0;
2410
2411         case 12000000:
2412         case 24000000:
2413                 wm8994->sysclk_constraints = &constraints_12;
2414                 wm8994->sysclk = freq;
2415                 return 0;
2416         }
2417         return -EINVAL;
2418 }
2419
2420 static int wm8994_set_dai_fmt(struct snd_soc_dai *codec_dai,
2421                 unsigned int fmt)
2422 {
2423         return 0;
2424 }
2425
2426 static int wm8994_pcm_startup(struct snd_pcm_substream *substream,
2427                               struct snd_soc_dai *dai)
2428 {
2429         struct snd_soc_codec *codec = dai->codec;
2430         struct wm8994_priv *wm8994 = codec->private_data;
2431
2432         /* The set of sample rates that can be supported depends on the
2433          * MCLK supplied to the CODEC - enforce this.
2434          */
2435
2436         if (!wm8994->sysclk) {
2437                 dev_err(codec->dev,
2438                         "No MCLK configured, call set_sysclk() on init\n");
2439                 return -EINVAL;
2440         }
2441
2442         snd_pcm_hw_constraint_list(substream->runtime, 0,
2443                                    SNDRV_PCM_HW_PARAM_RATE,
2444                                    wm8994->sysclk_constraints);
2445
2446         return 0;
2447 }
2448
2449 static int wm8994_pcm_hw_params(struct snd_pcm_substream *substream,
2450                                 struct snd_pcm_hw_params *params,
2451                                 struct snd_soc_dai *dai)
2452 {
2453         struct snd_soc_pcm_runtime *rtd = substream->private_data;
2454         struct snd_soc_device *socdev = rtd->socdev;
2455         struct snd_soc_codec *codec = socdev->card->codec;
2456         struct wm8994_priv *wm8994 = codec->private_data;
2457         int coeff;
2458
2459         coeff = get_coeff(wm8994->sysclk, params_rate(params));
2460         if (coeff < 0) {
2461                 coeff = get_coeff(wm8994->sysclk / 2, params_rate(params));
2462         }
2463         if (coeff < 0) {
2464                 dev_err(codec->dev,
2465                         "Unable to configure sample rate %dHz with %dHz MCLK\n",
2466                         params_rate(params), wm8994->sysclk);
2467                 return coeff;
2468         }
2469         params_format(params);
2470
2471         return 0;
2472 }
2473
2474 static int wm8994_mute(struct snd_soc_dai *dai, int mute)
2475 {
2476         return 0;
2477 }
2478
2479 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2480                                  enum snd_soc_bias_level level)
2481 {
2482
2483         codec->bias_level = level;
2484         return 0;
2485 }
2486
2487 #define WM8994_RATES SNDRV_PCM_RATE_48000
2488
2489 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2490         SNDRV_PCM_FMTBIT_S24_LE)
2491
2492 static struct snd_soc_dai_ops wm8994_ops = {
2493         .startup = wm8994_pcm_startup,
2494         .hw_params = wm8994_pcm_hw_params,
2495         .set_fmt = wm8994_set_dai_fmt,
2496         .set_sysclk = wm8994_set_dai_sysclk,
2497         .digital_mute = wm8994_mute,
2498 };
2499
2500 struct snd_soc_dai wm8994_dai = {
2501         .name = "WM8994",
2502         .playback = {
2503                 .stream_name = "Playback",
2504                 .channels_min = 1,
2505                 .channels_max = 2,
2506                 .rates = WM8994_RATES,
2507                 .formats = WM8994_FORMATS,
2508         },
2509         .capture = {
2510                 .stream_name = "Capture",
2511                 .channels_min = 2,
2512                 .channels_max = 2,
2513                 .rates = WM8994_RATES,
2514                 .formats = WM8994_FORMATS,
2515          },
2516         .ops = &wm8994_ops,
2517         .symmetric_rates = 1,
2518 };
2519 EXPORT_SYMBOL_GPL(wm8994_dai);
2520
2521 static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
2522 {
2523         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2524         struct snd_soc_codec *codec = socdev->card->codec;
2525
2526         wm8994_set_bias_level(codec,SND_SOC_BIAS_OFF);
2527         wm8994_reset();
2528         mdelay(WM8994_DELAY);
2529         return 0;
2530 }
2531
2532 static int wm8994_resume(struct platform_device *pdev)
2533 {
2534         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2535         struct snd_soc_codec *codec = socdev->card->codec;
2536         int i;
2537         u8 data[2];
2538         u16 *cache = codec->reg_cache;
2539         wm8994_codec_fnc_t **wm8994_fnc_ptr=wm8994_codec_sequence;
2540
2541         /* Sync reg_cache with the hardware */
2542         for (i = 0; i < WM8994_NUM_REG; i++) {
2543                 if (i == WM8994_RESET)
2544                         continue;
2545                 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
2546                 data[1] = cache[i] & 0x00ff;
2547                 codec->hw_write(codec->control_data, data, 2);
2548         }
2549
2550         wm8994_set_bias_level(codec,SND_SOC_BIAS_STANDBY);
2551         if(wm8994_current_mode<=wm8994_AP_to_speakers)
2552         {
2553                 wm8994_fnc_ptr+=wm8994_current_mode;
2554                 (*wm8994_fnc_ptr)() ;
2555         }
2556         else if(wm8994_current_mode>wm8994_BT_baseband_and_record)
2557         {
2558                 printk("%s--%d--: Wm8994 resume with null mode\n",__FUNCTION__,__LINE__);
2559         }
2560         else
2561         {
2562                 wm8994_fnc_ptr+=wm8994_current_mode;
2563                 (*wm8994_fnc_ptr)();
2564                 printk("%s--%d--: Wm8994 resume with error mode\n",__FUNCTION__,__LINE__);
2565         }
2566
2567         return 0;
2568 }
2569
2570 static struct snd_soc_codec *wm8994_codec;
2571
2572 static int wm8994_probe(struct platform_device *pdev)
2573 {
2574         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2575         struct snd_soc_codec *codec;
2576         int ret = 0;
2577
2578         if (wm8994_codec == NULL) {
2579                 dev_err(&pdev->dev, "Codec device not registered\n");
2580                 return -ENODEV;
2581         }
2582
2583         socdev->card->codec = wm8994_codec;
2584         codec = wm8994_codec;
2585
2586         /* register pcms */
2587         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2588         if (ret < 0) {
2589                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
2590                 goto pcm_err;
2591         }
2592
2593         snd_soc_add_controls(codec,wm8994_snd_controls,
2594                                 ARRAY_SIZE(wm8994_snd_controls));
2595         snd_soc_dapm_new_controls(codec,wm8994_dapm_widgets,
2596                                   ARRAY_SIZE(wm8994_dapm_widgets));
2597         snd_soc_dapm_add_routes(codec,audio_map, ARRAY_SIZE(audio_map));
2598         snd_soc_dapm_new_widgets(codec);
2599
2600         ret = snd_soc_init_card(socdev);
2601         if (ret < 0) {
2602                 dev_err(codec->dev, "failed to register card: %d\n", ret);
2603                 goto card_err;
2604         }
2605
2606         return ret;
2607
2608 card_err:
2609         snd_soc_free_pcms(socdev);
2610         snd_soc_dapm_free(socdev);
2611 pcm_err:
2612         return ret;
2613 }
2614
2615 static int wm8994_remove(struct platform_device *pdev)
2616 {
2617         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2618
2619         snd_soc_free_pcms(socdev);
2620         snd_soc_dapm_free(socdev);
2621
2622         return 0;
2623 }
2624
2625 struct snd_soc_codec_device soc_codec_dev_wm8994 = {
2626         .probe =        wm8994_probe,
2627         .remove =       wm8994_remove,
2628         .suspend =      wm8994_suspend,
2629         .resume =       wm8994_resume,
2630 };
2631 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
2632
2633 static int wm8994_register(struct wm8994_priv *wm8994,
2634                            enum snd_soc_control_type control)
2635 {
2636         struct snd_soc_codec *codec = &wm8994->codec;
2637         int ret;
2638
2639         if (wm8994_codec) {
2640                 dev_err(codec->dev, "Another WM8994 is registered\n");
2641                 ret = -EINVAL;
2642                 goto err;
2643         }
2644
2645         mutex_init(&codec->mutex);
2646         INIT_LIST_HEAD(&codec->dapm_widgets);
2647         INIT_LIST_HEAD(&codec->dapm_paths);
2648
2649         codec->private_data = wm8994;
2650         codec->name = "WM8994";
2651         codec->owner = THIS_MODULE;
2652         codec->dai = &wm8994_dai;
2653         codec->num_dai = 1;
2654         codec->reg_cache_size = ARRAY_SIZE(wm8994->reg_cache);
2655         codec->reg_cache = &wm8994->reg_cache;
2656         codec->bias_level = SND_SOC_BIAS_OFF;
2657         codec->set_bias_level = wm8994_set_bias_level;
2658
2659         memcpy(codec->reg_cache, wm8994_reg,
2660                sizeof(wm8994_reg));
2661
2662         ret = snd_soc_codec_set_cache_io(codec,7, 9, control);
2663         if (ret < 0) {
2664                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2665                 goto err;
2666         }
2667
2668         ret = 0;//wm8994_reset(); cjq
2669         if (ret < 0) {
2670                 dev_err(codec->dev, "Failed to issue reset\n");
2671                 goto err;
2672         }
2673                 /*disable speaker */
2674                 gpio_request(RK2818_PIN_PF7, "WM8994");
2675                 rk2818_mux_api_set(GPIOE_SPI1_FLASH_SEL_NAME, IOMUXA_GPIO1_A3B7);
2676                 gpio_direction_output(RK2818_PIN_PF7,GPIO_HIGH);
2677
2678
2679         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_STANDBY);
2680
2681         wm8994_dai.dev = codec->dev;
2682
2683         wm8994_codec = codec;
2684
2685         ret = snd_soc_register_codec(codec);
2686         if (ret != 0) {
2687                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2688                 goto err;
2689         }
2690
2691         ret = snd_soc_register_dai(&wm8994_dai);
2692         if (ret != 0) {
2693                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
2694                 snd_soc_unregister_codec(codec);
2695                 goto err_codec;
2696         }
2697         return 0;
2698
2699 err_codec:
2700         snd_soc_unregister_codec(codec);
2701 err:
2702         kfree(wm8994);
2703         return ret;
2704 }
2705
2706 static void wm8994_unregister(struct wm8994_priv *wm8994)
2707 {
2708         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_OFF);
2709         snd_soc_unregister_dai(&wm8994_dai);
2710         snd_soc_unregister_codec(&wm8994->codec);
2711         kfree(wm8994);
2712         wm8994_codec = NULL;
2713 }
2714
2715 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2716 static int wm8994_i2c_probe(struct i2c_client *i2c,
2717                             const struct i2c_device_id *id)
2718 {
2719         struct wm8994_priv *wm8994;
2720         struct snd_soc_codec *codec;
2721         wm8994_client=i2c;
2722         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2723         if (wm8994 == NULL)
2724                 return -ENOMEM;
2725
2726         codec = &wm8994->codec;
2727
2728         i2c_set_clientdata(i2c, wm8994);
2729         codec->control_data = i2c;
2730
2731         codec->dev = &i2c->dev;
2732
2733         return wm8994_register(wm8994, SND_SOC_I2C);
2734 }
2735
2736 static int wm8994_i2c_remove(struct i2c_client *client)
2737 {
2738         struct wm8994_priv *wm8994 = i2c_get_clientdata(client);
2739         wm8994_unregister(wm8994);
2740         return 0;
2741 }
2742
2743 #ifdef CONFIG_PM
2744 static int wm8994_i2c_suspend(struct i2c_client *client, pm_message_t msg)
2745 {
2746         return snd_soc_suspend_device(&client->dev);
2747 }
2748
2749 static int wm8994_i2c_resume(struct i2c_client *client)
2750 {
2751         return snd_soc_resume_device(&client->dev);
2752 }
2753 #else
2754 #define wm8994_i2c_suspend NULL
2755 #define wm8994_i2c_resume NULL
2756 #endif
2757
2758 static const struct i2c_device_id wm8994_i2c_id[] = {
2759         { "wm8994", 0 },
2760         { }
2761 };
2762 MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
2763
2764 static struct i2c_driver wm8994_i2c_driver = {
2765         .driver = {
2766                 .name = "WM8994",
2767                 .owner = THIS_MODULE,
2768         },
2769         .probe = wm8994_i2c_probe,
2770         .remove = wm8994_i2c_remove,
2771         .suspend = wm8994_i2c_suspend,
2772         .resume = wm8994_i2c_resume,
2773         .id_table = wm8994_i2c_id,
2774 };
2775
2776 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate)
2777 {
2778         int ret;
2779         struct i2c_adapter *adap = client->adapter;
2780         struct i2c_msg msg;
2781         char tx_buf[4];
2782
2783         memcpy(tx_buf, reg, 2);
2784         memcpy(tx_buf+2, data, 2);
2785         msg.addr = client->addr;
2786         msg.buf = tx_buf;
2787         msg.len = 4;
2788         msg.flags = client->flags;
2789         msg.scl_rate = scl_rate;
2790         msg.read_type = I2C_NORMAL;
2791
2792         ret = i2c_transfer(adap, &msg, 1);
2793
2794         return ret;
2795 }
2796
2797 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate)
2798 {
2799         int ret;
2800         struct i2c_adapter *adap = client->adapter;
2801         struct i2c_msg msgs[2];
2802
2803         msgs[0].addr = client->addr;
2804         msgs[0].buf = (char *)reg;
2805         msgs[0].flags = client->flags;
2806         msgs[0].len = 2;
2807         msgs[0].scl_rate = scl_rate;
2808         msgs[0].read_type = I2C_NO_STOP;
2809
2810         msgs[1].addr = client->addr;
2811         msgs[1].buf = (char *)buf;
2812         msgs[1].flags = client->flags | I2C_M_RD;
2813         msgs[1].len = 2;
2814         msgs[1].scl_rate = scl_rate;
2815         msgs[1].read_type = I2C_NO_STOP;
2816
2817         ret = i2c_transfer(adap, msgs, 2);
2818
2819         return ret;
2820 }
2821
2822 #endif
2823
2824 #if defined(CONFIG_SPI_MASTER)
2825 static int __devinit wm8994_spi_probe(struct spi_device *spi)
2826 {
2827         struct wm8994_priv *wm8994;
2828         struct snd_soc_codec *codec;
2829
2830         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2831         if (wm8994 == NULL)
2832                 return -ENOMEM;
2833
2834         codec = &wm8994->codec;
2835         codec->control_data = spi;
2836         codec->dev = &spi->dev;
2837
2838         dev_set_drvdata(&spi->dev, wm8994);
2839
2840         return wm8994_register(wm8994, SND_SOC_SPI);
2841 }
2842
2843 static int __devexit wm8994_spi_remove(struct spi_device *spi)
2844 {
2845         struct wm8994_priv *wm8994 = dev_get_drvdata(&spi->dev);
2846
2847         wm8994_unregister(wm8994);
2848
2849         return 0;
2850 }
2851
2852 #ifdef CONFIG_PM
2853 static int wm8994_spi_suspend(struct spi_device *spi, pm_message_t msg)
2854 {
2855         return snd_soc_suspend_device(&spi->dev);
2856 }
2857
2858 static int wm8994_spi_resume(struct spi_device *spi)
2859 {
2860         return snd_soc_resume_device(&spi->dev);
2861 }
2862 #else
2863 #define wm8994_spi_suspend NULL
2864 #define wm8994_spi_resume NULL
2865 #endif
2866
2867 static struct spi_driver wm8994_spi_driver = {
2868         .driver = {
2869                 .name   = "wm8994",
2870                 .bus    = &spi_bus_type,
2871                 .owner  = THIS_MODULE,
2872         },
2873         .probe          = wm8994_spi_probe,
2874         .remove         = __devexit_p(wm8994_spi_remove),
2875         .suspend        = wm8994_spi_suspend,
2876         .resume         = wm8994_spi_resume,
2877 };
2878 #endif
2879
2880 static int __init wm8994_modinit(void)
2881 {
2882         int ret;
2883
2884 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2885         ret = i2c_add_driver(&wm8994_i2c_driver);
2886         if (ret != 0)
2887                 pr_err("WM8994: Unable to register I2C driver: %d\n", ret);
2888 #endif
2889 #if defined(CONFIG_SPI_MASTER)
2890         ret = spi_register_driver(&wm8994_spi_driver);
2891         if (ret != 0)
2892                 pr_err("WM8994: Unable to register SPI driver: %d\n", ret);
2893 #endif
2894         return ret;
2895 }
2896 module_init(wm8994_modinit);
2897
2898 static void __exit wm8994_exit(void)
2899 {
2900 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2901         i2c_del_driver(&wm8994_i2c_driver);
2902 #endif
2903 #if defined(CONFIG_SPI_MASTER)
2904         spi_unregister_driver(&wm8994_spi_driver);
2905 #endif
2906 }
2907 module_exit(wm8994_exit);
2908
2909
2910 MODULE_DESCRIPTION("ASoC WM8994 driver");
2911 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2912 MODULE_LICENSE("GPL");