sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c -- WM8994 ALSA SoC audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  * Copyright 2005 Openedhand Ltd.
   6  *
   7  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/platform_device.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/tlv.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29
  30 #include <mach/iomux.h>
  31 #include <mach/gpio.h>
  32
  33 #include "wm8994.h"
  34 #include <linux/miscdevice.h>
  35 #include <linux/circ_buf.h>
  36 #include <mach/spi_fpga.h>
  37
  38 /* If digital BB is used,open this define. */
  39 //#define PCM_BB
  40
  41 /* Open wm8994 with diferent ways. */
  42 //#define chinaone
  43 #define rk28SDK
  44
  45 /* Define what kind of digital BB is used. */
  46 #ifdef PCM_BB
  47 #define TD688_MODE
  48 //#define MU301_MODE
  49 //#define CHONGY_MODE
  50 //#define THINKWILL_M800_MODE
  51 #endif //PCM_BB
  52
  53 #if 1
  54 #define DBG(x...) printk(KERN_INFO x)
  55 #else
  56 #define DBG(x...) do { } while (0)
  57 #endif
  58 #define wm8994_mic_VCC 0x0010
  59 #define WM8994_DELAY 50
  60
  61 struct i2c_client *wm8994_client;
  62 //struct wm8994_board wm8994_codec_board_data;
  63 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate);
  64 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate);
  65
  66 enum wm8994_codec_mode
  67 {
  68   wm8994_AP_to_headset,
  69   wm8994_AP_to_speakers,
  70   wm8994_recorder_and_AP_to_headset,
  71   wm8994_recorder_and_AP_to_speakers,
  72   wm8994_FM_to_headset,
  73   wm8994_FM_to_headset_and_record,
  74   wm8994_FM_to_speakers,
  75   wm8994_FM_to_speakers_and_record,
  76   wm8994_handsetMIC_to_baseband_to_headset,
  77   wm8994_handsetMIC_to_baseband_to_headset_and_record,
  78   wm8994_mainMIC_to_baseband_to_earpiece,
  79   wm8994_mainMIC_to_baseband_to_earpiece_and_record,
  80   wm8994_mainMIC_to_baseband_to_speakers,
  81   wm8994_mainMIC_to_baseband_with_AP_to_speakers,
  82   wm8994_mainMIC_to_baseband_to_speakers_and_record,
  83   wm8994_BT_baseband,
  84   wm8994_BT_baseband_and_record,
  85   null
  86 };
  87
  88 /* wm8994_current_mode:save current wm8994 mode */
  89 unsigned char wm8994_current_mode=null;//,wm8994_mic_VCC=0x0000;
  90
  91 void wm8994_set_volume(unsigned char wm8994_mode,unsigned char volume,unsigned char max_volume);
  92
  93 enum stream_type_wm8994
  94 {
  95         VOICE_CALL      =0,
  96         BLUETOOTH_SCO,
  97 };
  98
  99 /* For voice device route set, add by phc  */
 100 enum VoiceDeviceSwitch
 101 {
 102         SPEAKER_INCALL,
 103         SPEAKER_NORMAL,
 104
 105         HEADSET_INCALL,
 106         HEADSET_NORMAL,
 107
 108         EARPIECE_INCALL,
 109         EARPIECE_NORMAL,
 110
 111         BLUETOOTH_SCO_INCALL,
 112         BLUETOOTH_SCO_NORMAL,
 113
 114         BLUETOOTH_A2DP_INCALL,
 115         BLUETOOTH_A2DP_NORMAL,
 116
 117         MIC_CAPTURE,
 118
 119         EARPIECE_RINGTONE,
 120         SPEAKER_RINGTONE,
 121         HEADSET_RINGTONE,
 122
 123         ALL_OPEN,
 124         ALL_CLOSED
 125 };
 126
 127
 128 #define call_maxvol 5
 129
 130 /* call_vol:  save all kinds of system volume value. */
 131 unsigned char call_vol=5;
 132 unsigned short headset_vol_table[6]     ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 133 unsigned short speakers_vol_table[6]    ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 134 unsigned short earpiece_vol_table[6]    ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 135 unsigned short BT_vol_table[6]          ={0x0100,0x011d,0x012d,0x0135,0x013b,0x013f};
 136
 137 /*
 138  * wm8994 register cache
 139  * We can't read the WM8994 register space when we
 140  * are using 2 wire for device control, so we cache them instead.
 141  */
 142 static const u16 wm8994_reg[] = {
 143         0x0097, 0x0097, 0x0079, 0x0079,  /*  0 */
 144         0x0000, 0x0008, 0x0000, 0x000a,  /*  4 */
 145         0x0000, 0x0000, 0x00ff, 0x00ff,  /*  8 */
 146         0x000f, 0x000f, 0x0000, 0x0000,  /* 12 */
 147         0x0000, 0x007b, 0x0000, 0x0032,  /* 16 */
 148         0x0000, 0x00c3, 0x00c3, 0x00c0,  /* 20 */
 149         0x0000, 0x0000, 0x0000, 0x0000,  /* 24 */
 150         0x0000, 0x0000, 0x0000, 0x0000,  /* 28 */
 151         0x0000, 0x0000, 0x0050, 0x0050,  /* 32 */
 152         0x0050, 0x0050, 0x0050, 0x0050,  /* 36 */
 153         0x0079, 0x0079, 0x0079,          /* 40 */
 154 };
 155
 156 /* codec private data */
 157 struct wm8994_priv {
 158         unsigned int sysclk;
 159         struct snd_soc_codec codec;
 160         struct snd_pcm_hw_constraint_list *sysclk_constraints;
 161         u16 reg_cache[WM8994_NUM_REG];
 162 };
 163
 164 static int wm8994_read(unsigned short reg,unsigned short *value)
 165 {
 166         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values;
 167
 168         if (reg_recv_data(wm8994_client,&regs,&values,400000) > 0)
 169         {
 170                 *value=((values>>8)& 0x00FF)|((values<<8)&0xFF00);
 171                 return 0;
 172         }
 173
 174         printk("%s---line->%d:Codec read error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,*value);
 175
 176         return -EIO;
 177 }
 178
 179
 180 static int wm8994_write(unsigned short reg,unsigned short value)
 181 {
 182         unsigned short regs=((reg>>8)&0x00FF)|((reg<<8)&0xFF00),values=((value>>8)&0x00FF)|((value<<8)&0xFF00);
 183
 184         if (reg_send_data(wm8994_client,&regs,&values,400000) > 0)
 185                 return 0;
 186
 187         printk("%s---line->%d:Codec write error! reg = 0x%x , value = 0x%x\n",__FUNCTION__,__LINE__,reg,value);
 188
 189         return -EIO;
 190 }
 191
 192 #define wm8994_reset()  wm8994_write(WM8994_RESET, 0)
 193 void AP_to_headset(void)
 194 {
 195         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 196
 197         if(wm8994_current_mode==wm8994_AP_to_headset)return;
 198         wm8994_current_mode=wm8994_AP_to_headset;
 199         wm8994_reset();
 200         msleep(WM8994_DELAY);
 201
 202         wm8994_write(0x01,  0x0003);
 203         msleep(WM8994_DELAY);
 204
 205         wm8994_write(0x200, 0x0001);
 206         wm8994_write(0x220, 0x0000);
 207         wm8994_write(0x221, 0x0700);
 208         wm8994_write(0x222, 0x3126);
 209         wm8994_write(0x223, 0x0100);
 210
 211         wm8994_write(0x210, 0x0083); // SR=48KHz
 212         wm8994_write(0x220, 0x0004);
 213         msleep(WM8994_DELAY);
 214         wm8994_write(0x220, 0x0005);
 215         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 216         wm8994_write(0x300, 0x4010);  // i2s 16 bits
 217
 218         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1/ q
 219         wm8994_write(0x05,  0x0303);
 220         wm8994_write(0x2D,  0x0100);
 221         wm8994_write(0x2E,  0x0100);
 222
 223         wm8994_write(0x4C,  0x9F25);
 224         msleep(5);
 225         wm8994_write(0x01,  0x0303);
 226         msleep(50);
 227         wm8994_write(0x60,  0x0022);
 228         wm8994_write(0x60,  0x00FF);
 229
 230         wm8994_write(0x208, 0x000A);
 231         wm8994_write(0x420, 0x0000);
 232         wm8994_write(0x601, 0x0001);
 233         wm8994_write(0x602, 0x0001);
 234
 235         wm8994_write(0x610, 0x01A0);  //DAC1 Left Volume bit0~7
 236         wm8994_write(0x611, 0x01A0);  //DAC1 Right Volume bit0~7
 237         wm8994_write(0x03,  0x3030);
 238         wm8994_write(0x22,  0x0000);
 239         wm8994_write(0x23,  0x0100);
 240         wm8994_write(0x36,  0x0003);
 241         wm8994_write(0x1C,  0x017F);  //HPOUT1L Volume
 242         wm8994_write(0x1D,  0x017F);  //HPOUT1R Volume
 243
 244 #ifdef  CONFIG_SND_CODEC_SOC_MASTER
 245         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 246         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 247         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 248         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 249 #endif
 250 }
 251
 252 void AP_to_speakers(void)
 253 {
 254         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 255
 256         if(wm8994_current_mode==wm8994_AP_to_speakers)return;
 257         wm8994_current_mode=wm8994_AP_to_speakers;
 258         wm8994_reset();
 259         msleep(WM8994_DELAY);
 260
 261         wm8994_write(0x01,  0x0003);
 262         msleep(WM8994_DELAY);
 263
 264         wm8994_write(0x200, 0x0001);
 265         wm8994_write(0x220, 0x0000);
 266         wm8994_write(0x221, 0x0700);
 267         wm8994_write(0x222, 0x3126);
 268         wm8994_write(0x223, 0x0100);
 269
 270         wm8994_write(0x210, 0x0083); // SR=48KHz
 271         wm8994_write(0x220, 0x0004);
 272         msleep(WM8994_DELAY);
 273         wm8994_write(0x220, 0x0005);
 274         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 275         wm8994_write(0x300, 0xC010);  // i2s 16 bits
 276
 277         wm8994_write(0x01,  0x3003);
 278         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 279         wm8994_write(0x05,  0x0303);
 280         wm8994_write(0x2D,  0x0100);
 281         wm8994_write(0x2E,  0x0100);
 282         wm8994_write(0x4C,  0x9F25);
 283         wm8994_write(0x60,  0x00EE);
 284         wm8994_write(0x208, 0x000A);
 285         wm8994_write(0x420, 0x0000);
 286
 287         wm8994_write(0x601, 0x0001);
 288         wm8994_write(0x602, 0x0001);
 289
 290         wm8994_write(0x610, 0x01c0);  //DAC1 Left Volume bit0~7
 291         wm8994_write(0x611, 0x01c0);  //DAC1 Right Volume bit0~7
 292         wm8994_write(0x03,  0x0330);
 293         wm8994_write(0x22,  0x0000);
 294         wm8994_write(0x23,  0x0100);
 295         wm8994_write(0x36,  0x0003);
 296         wm8994_write(0x26,  0x017F);  //Speaker Left Output Volume
 297         wm8994_write(0x27,  0x017F);  //Speaker Right Output Volume
 298
 299 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 300         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 301         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 302         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 303         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 304 #endif
 305 }
 306
 307 void recorder_and_AP_to_headset(void)
 308 {
 309         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 310
 311         if(wm8994_current_mode==wm8994_recorder_and_AP_to_headset)return;
 312         wm8994_current_mode=wm8994_recorder_and_AP_to_headset;
 313         wm8994_reset();
 314         msleep(WM8994_DELAY);
 315
 316         wm8994_write(0x01,  0x0003);
 317         msleep(WM8994_DELAY);
 318
 319 //MCLK=12MHz
 320 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 321
 322         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 323         wm8994_write(0x220, 0x0000);
 324         wm8994_write(0x221, 0x0700);
 325         wm8994_write(0x222, 0x3126);
 326         wm8994_write(0x223, 0x0100);
 327
 328         wm8994_write(0x210, 0x0083); // SR=48KHz
 329
 330         wm8994_write(0x220, 0x0004);
 331         msleep(WM8994_DELAY);
 332         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 333         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 334
 335         wm8994_write(0x02,  0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
 336         wm8994_write(0x03,  0x3030);
 337         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 338         wm8994_write(0x1A,  0x015F); // IN1_VU=1, IN1R_ZC=1, IN1R_VOL=1_1011
 339         wm8994_write(0x28,  0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
 340         wm8994_write(0x2A,  0x0030); // IN1R_TO_MIXINR=1
 341         wm8994_write(0x200, 0x0011); // AIF1CLK_ENA=1
 342         wm8994_write(0x208, 0x000A); // DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 343         wm8994_write(0x300, 0xC050); // AIF1ADCL_SRC=1, AIF1ADCR_SRC=1, AIF1_WL=10, AIF1_FMT=10
 344         wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
 345         wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
 346         wm8994_write(0x620, 0x0000);
 347
 348         wm8994_write(0x700, 0xA101);
 349
 350         wm8994_write(0x402, 0x01FF); // AIF1ADC1L_VOL [7:0]
 351         wm8994_write(0x403, 0x01FF); // AIF1ADC1R_VOL [7:0]
 352
 353         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);
 354         wm8994_write(0x05,  0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
 355         wm8994_write(0x2D,  0x0100); // DAC1L_TO_HPOUT1L=1
 356         wm8994_write(0x2E,  0x0100); // DAC1R_TO_HPOUT1R=1
 357         wm8994_write(0x4C,  0x9F25); // CP_ENA=1
 358         wm8994_write(0x60,  0x00EE); // HPOUT1L_RMV_SHORT=1, HPOUT1L_OUTP=1, HPOUT1L_DLY=1, HPOUT1R_RMV_SHORT=1, HPOUT1R_OUTP=1, HPOUT1R_DLY=1
 359         wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
 360         wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
 361         wm8994_write(0x610, 0x01A0); // DAC1_VU=1, DAC1L_VOL=1100_0000
 362         wm8994_write(0x611, 0x01A0); // DAC1_VU=1, DAC1R_VOL=1100_0000
 363         wm8994_write(0x1C,  0x017F);  //HPOUT1L Volume
 364         wm8994_write(0x1D,  0x017F);  //HPOUT1R Volume
 365         wm8994_write(0x420, 0x0000);
 366
 367 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 368         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 369         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 370         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 371         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 372 #endif
 373 }
 374
 375 void recorder_and_AP_to_speakers(void)
 376 {
 377         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 378
 379         if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers)return;
 380         wm8994_current_mode=wm8994_recorder_and_AP_to_speakers;
 381         wm8994_reset();
 382         msleep(WM8994_DELAY);
 383
 384         wm8994_write(0x01,  0x0003);
 385         msleep(WM8994_DELAY);
 386
 387 //MCLK=12MHz
 388 //48KHz, BCLK=48KHz*64=3.072MHz, Fout=12.288MHz
 389
 390         wm8994_write(0x200, 0x0001); // AIF1CLK_ENA=1
 391         wm8994_write(0x220, 0x0000);
 392         wm8994_write(0x221, 0x0700);
 393         wm8994_write(0x222, 0x3126);
 394         wm8994_write(0x223, 0x0100);
 395         wm8994_write(0x210, 0x0083); // SR=48KHz
 396
 397         wm8994_write(0x220, 0x0004);
 398         msleep(WM8994_DELAY);
 399         wm8994_write(0x220, 0x0005); // FLL1_FRACN_ENA=1, FLL1_ENA=1
 400         wm8994_write(0x200, 0x0011); // AIF1CLK_SRC=10, AIF1CLK_ENA=1
 401
 402         wm8994_write(0x02,  0x6110); // TSHUT_ENA=1, TSHUT_OPDIS=1, MIXINR_ENA=1,IN1R_ENA=1
 403         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 404         wm8994_write(0x1A,  0x015F); // IN1_VU=1, IN1R_ZC=1, IN1R_VOL=1_1011
 405         wm8994_write(0x28,  0x0003); // IN1RP_TO_IN1R=1, IN1RN_TO_IN1R=1
 406         wm8994_write(0x2A,  0x0030); // IN1R_TO_MIXINR=1
 407         wm8994_write(0x200, 0x0011); // AIF1CLK_ENA=1
 408         wm8994_write(0x208, 0x000A); // DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 409         wm8994_write(0x300, 0xC050); // AIF1ADCL_SRC=1, AIF1ADCR_SRC=1, AIF1_WL=10, AIF1_FMT=10
 410         wm8994_write(0x606, 0x0002); // ADC1L_TO_AIF1ADC1L=1
 411         wm8994_write(0x607, 0x0002); // ADC1R_TO_AIF1ADC1R=1
 412         wm8994_write(0x620, 0x0000);
 413
 414         wm8994_write(0x402, 0x01FF); // AIF1ADC1L_VOL [7:0]
 415         wm8994_write(0x403, 0x01FF); // AIF1ADC1R_VOL [7:0]
 416
 417         wm8994_write(0x700, 0xA101);
 418
 419         wm8994_write(0x01,  0x3003|wm8994_mic_VCC);
 420         wm8994_write(0x03,  0x0330); // SPKRVOL_ENA=1, SPKLVOL_ENA=1, MIXOUTL_ENA=1, MIXOUTR_ENA=1
 421         wm8994_write(0x05,  0x0303); // AIF1DAC1L_ENA=1, AIF1DAC1R_ENA=1, DAC1L_ENA=1, DAC1R_ENA=1
 422         wm8994_write(0x22,  0x0000);
 423         wm8994_write(0x23,  0x0100); // SPKOUT_CLASSAB=1
 424
 425         wm8994_write(0x2D,  0x0001); // DAC1L_TO_MIXOUTL=1
 426         wm8994_write(0x2E,  0x0001); // DAC1R_TO_MIXOUTR=1
 427         wm8994_write(0x4C,  0x9F25);
 428         wm8994_write(0x60,  0x00EE);
 429         wm8994_write(0x36,  0x000C); // MIXOUTL_TO_SPKMIXL=1, MIXOUTR_TO_SPKMIXR=1
 430         wm8994_write(0x601, 0x0001); // AIF1DAC1L_TO_DAC1L=1
 431         wm8994_write(0x602, 0x0001); // AIF1DAC1R_TO_DAC1R=1
 432         wm8994_write(0x610, 0x01C0); // DAC1_VU=1, DAC1L_VOL=1100_0000
 433         wm8994_write(0x611, 0x01C0); // DAC1_VU=1, DAC1R_VOL=1100_0000
 434         wm8994_write(0x26,  0x017F);  //Speaker Left Output Volume
 435         wm8994_write(0x27,  0x017F);  //Speaker Right Output Volume
 436         wm8994_write(0x420, 0x0000);
 437 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 438         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 439         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 440         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 441         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 442 #endif
 443 }
 444
 445 void FM_to_headset(void)
 446 {
 447         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 448
 449         if(wm8994_current_mode==wm8994_FM_to_headset)return;
 450         wm8994_current_mode=wm8994_FM_to_headset;
 451         wm8994_reset();
 452         msleep(WM8994_DELAY);
 453
 454         wm8994_write(0x01,  0x0323);
 455         wm8994_write(0x02,  0x03A0);
 456         wm8994_write(0x03,  0x0030);
 457         wm8994_write(0x19,  0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 458         wm8994_write(0x1B,  0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 459
 460         wm8994_write(0x28,  0x0044);
 461         wm8994_write(0x29,  0x0100);
 462         wm8994_write(0x2A,  0x0100);
 463         wm8994_write(0x2D,  0x0040);
 464         wm8994_write(0x2E,  0x0040);
 465         wm8994_write(0x4C,  0x9F25);
 466         wm8994_write(0x60,  0x00EE);
 467         wm8994_write(0x220, 0x0003);
 468         wm8994_write(0x221, 0x0700);
 469         wm8994_write(0x224, 0x0CC0);
 470         wm8994_write(0x200, 0x0011);
 471         wm8994_write(0x1C,  0x01F9);  //LEFT OUTPUT VOLUME
 472         wm8994_write(0x1D,  0x01F9);  //RIGHT OUTPUT VOLUME
 473 }
 474
 475 void FM_to_headset_and_record(void)
 476 {
 477         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 478
 479         if(wm8994_current_mode==wm8994_FM_to_headset_and_record)return;
 480         wm8994_current_mode=wm8994_FM_to_headset_and_record;
 481         wm8994_reset();
 482         msleep(WM8994_DELAY);
 483
 484         wm8994_write(0x01,   0x0003);
 485         msleep(WM8994_DELAY);
 486         wm8994_write(0x221,  0x1900);  //8~13BIT div
 487
 488 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 489         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 490         wm8994_write(0x303,  0x0040);  // master  0x0050 lrck 7.94kHz bclk 510KHz
 491 #endif
 492
 493         wm8994_write(0x220,  0x0004);
 494         msleep(WM8994_DELAY);
 495         wm8994_write(0x220,  0x0005);
 496
 497         wm8994_write(0x01,   0x0323);
 498         wm8994_write(0x02,   0x03A0);
 499         wm8994_write(0x03,   0x0030);
 500         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 501         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 502
 503         wm8994_write(0x28,   0x0044);
 504         wm8994_write(0x29,   0x0100);
 505         wm8994_write(0x2A,   0x0100);
 506         wm8994_write(0x2D,   0x0040);
 507         wm8994_write(0x2E,   0x0040);
 508         wm8994_write(0x4C,   0x9F25);
 509         wm8994_write(0x60,   0x00EE);
 510         wm8994_write(0x200,  0x0011);
 511         wm8994_write(0x1C,   0x01F9);  //LEFT OUTPUT VOLUME
 512         wm8994_write(0x1D,   0x01F9);  //RIGHT OUTPUT VOLUME
 513         wm8994_write(0x04,   0x0303);
 514         wm8994_write(0x208,  0x000A);
 515         wm8994_write(0x300,  0x4050);
 516         wm8994_write(0x606,  0x0002);
 517         wm8994_write(0x607,  0x0002);
 518         wm8994_write(0x620,  0x0000);
 519 }
 520
 521 void FM_to_speakers(void)
 522 {
 523         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 524
 525         if(wm8994_current_mode==wm8994_FM_to_speakers)return;
 526         wm8994_current_mode=wm8994_FM_to_speakers;
 527         wm8994_reset();
 528         msleep(WM8994_DELAY);
 529
 530         wm8994_write(0x01,   0x3023);
 531         wm8994_write(0x02,   0x03A0);
 532         wm8994_write(0x03,   0x0330);
 533         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 534         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 535
 536         wm8994_write(0x22,   0x0000);
 537         wm8994_write(0x23,   0x0000);
 538         wm8994_write(0x36,   0x000C);
 539
 540         wm8994_write(0x28,   0x0044);
 541         wm8994_write(0x29,   0x0100);
 542         wm8994_write(0x2A,   0x0100);
 543         wm8994_write(0x2D,   0x0040);
 544         wm8994_write(0x2E,   0x0040);
 545
 546         wm8994_write(0x220,  0x0003);
 547         wm8994_write(0x221,  0x0700);
 548         wm8994_write(0x224,  0x0CC0);
 549
 550         wm8994_write(0x200,  0x0011);
 551         wm8994_write(0x20,   0x01F9);
 552         wm8994_write(0x21,   0x01F9);
 553 }
 554
 555 void FM_to_speakers_and_record(void)
 556 {
 557         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 558
 559         if(wm8994_current_mode==wm8994_FM_to_speakers_and_record)return;
 560         wm8994_current_mode=wm8994_FM_to_speakers_and_record;
 561         wm8994_reset();
 562         msleep(WM8994_DELAY);
 563
 564         wm8994_write(0x01,   0x0003);
 565         msleep(WM8994_DELAY);
 566
 567 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 568         wm8994_write(0x302,  0x4000);  // master = 0x4000 // slave= 0x0000
 569         wm8994_write(0x303,  0x0090);  //
 570 #endif
 571
 572         wm8994_write(0x220,  0x0006);
 573         msleep(WM8994_DELAY);
 574
 575         wm8994_write(0x01,   0x3023);
 576         wm8994_write(0x02,   0x03A0);
 577         wm8994_write(0x03,   0x0330);
 578         wm8994_write(0x19,   0x010B);  //LEFT LINE INPUT 3&4 VOLUME
 579         wm8994_write(0x1B,   0x010B);  //RIGHT LINE INPUT 3&4 VOLUME
 580
 581         wm8994_write(0x22,   0x0000);
 582         wm8994_write(0x23,   0x0000);
 583         wm8994_write(0x36,   0x000C);
 584
 585         wm8994_write(0x28,   0x0044);
 586         wm8994_write(0x29,   0x0100);
 587         wm8994_write(0x2A,   0x0100);
 588         wm8994_write(0x2D,   0x0040);
 589         wm8994_write(0x2E,   0x0040);
 590
 591         wm8994_write(0x220,  0x0003);
 592         wm8994_write(0x221,  0x0700);
 593         wm8994_write(0x224,  0x0CC0);
 594
 595         wm8994_write(0x200,  0x0011);
 596         wm8994_write(0x20,   0x01F9);
 597         wm8994_write(0x21,   0x01F9);
 598         wm8994_write(0x04,   0x0303);
 599         wm8994_write(0x208,  0x000A);
 600         wm8994_write(0x300,  0x4050);
 601         wm8994_write(0x606,  0x0002);
 602         wm8994_write(0x607,  0x0002);
 603         wm8994_write(0x620,  0x0000);
 604 }
 605 #ifndef PCM_BB
 606 void handsetMIC_to_baseband_to_headset(void)
 607 {
 608         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 609
 610         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset)return;
 611         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset;
 612         wm8994_reset();
 613         msleep(WM8994_DELAY);
 614
 615         wm8994_write(0x01,  0x0003);
 616         msleep(50);
 617
 618         wm8994_write(0x200, 0x0001);
 619         wm8994_write(0x220, 0x0000);
 620         wm8994_write(0x221, 0x0700);
 621         wm8994_write(0x222, 0x3126);
 622         wm8994_write(0x223, 0x0100);
 623
 624         wm8994_write(0x210, 0x0083); // SR=48KHz
 625         wm8994_write(0x220, 0x0004);
 626         msleep(WM8994_DELAY);
 627         wm8994_write(0x220, 0x0005);
 628         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 629         wm8994_write(0x300, 0xC010);  // i2s 16 bits
 630
 631         wm8994_write(0x02,  0x6040);
 632         wm8994_write(0x03,  0x3030);
 633         wm8994_write(0x04,  0x0300); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1
 634         wm8994_write(0x05,  0x0303);
 635         wm8994_write(0x18,  0x015B); //mic volume
 636         wm8994_write(0x1E,  0x0006);
 637         wm8994_write(0x22,  0x0000);
 638         wm8994_write(0x23,  0x0100);
 639         wm8994_write(0x28,  0x0030);  //IN1LN_TO_IN1L IN1LP_TO_IN1L
 640         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 641
 642         wm8994_write(0x02,  0x6240);
 643         wm8994_write(0x2B,  0x0005);  //VRX_MIXINL_VOL
 644         wm8994_write(0x2D,  0x0041);  //bit 1 IN2LP_TO_MIXOUTL bit 12 DAC1L_TO_HPOUT1L  0x0102
 645         wm8994_write(0x2E,  0x0081);  //bit 1 IN2RP_TO_MIXOUTR bit 12 DAC1R_TO_HPOUT1R  0x0102
 646
 647         wm8994_write(0x34,  0x0002);  //IN1L_TO_LINEOUT1P
 648         wm8994_write(0x36,  0x0003);
 649
 650         wm8994_write(0x4C,  0x9F25);
 651         msleep(5);
 652         wm8994_write(0x01,  0x0323);
 653         msleep(50);
 654         wm8994_write(0x60,  0x0022);
 655         wm8994_write(0x60,  0x00EE);
 656
 657         wm8994_write(0x208, 0x000A);
 658         wm8994_write(0x224, 0x0CC0);
 659         wm8994_write(0x420, 0x0000);
 660         wm8994_write(0x601, 0x0001);
 661         wm8994_write(0x602, 0x0001);
 662
 663         wm8994_write(0x610, 0x01A0);  //DAC1 Left Volume bit0~7
 664         wm8994_write(0x611, 0x01A0);  //DAC1 Right Volume bit0~7
 665 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 666         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 667         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 668         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 669         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 670 #endif
 671 }
 672
 673 void handsetMIC_to_baseband_to_headset_and_record(void)
 674 {
 675         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 676
 677         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record)return;
 678         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset_and_record;
 679         wm8994_reset();
 680         msleep(WM8994_DELAY);
 681
 682         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);
 683         wm8994_write(0x02,  0x62C0);
 684         wm8994_write(0x03,  0x3030);
 685         wm8994_write(0x04,  0x0303);
 686         wm8994_write(0x18,  0x014B);  //volume
 687         wm8994_write(0x19,  0x014B);  //volume
 688         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 689         wm8994_write(0x1E,  0x0006);
 690         wm8994_write(0x28,  0x00B0);  //IN2LP_TO_IN2L
 691         wm8994_write(0x29,  0x0120);
 692         wm8994_write(0x2D,  0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 693         wm8994_write(0x2E,  0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 694         wm8994_write(0x34,  0x0002);
 695         wm8994_write(0x4C,  0x9F25);
 696         wm8994_write(0x60,  0x00EE);
 697         wm8994_write(0x200, 0x0001);
 698         wm8994_write(0x208, 0x000A);
 699         wm8994_write(0x300, 0x0050);
 700
 701 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 702         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 703         wm8994_write(0x303, 0x0090);  // master lrck 16k
 704 #endif
 705
 706         wm8994_write(0x606, 0x0002);
 707         wm8994_write(0x607, 0x0002);
 708         wm8994_write(0x620, 0x0000);
 709 }
 710
 711 void mainMIC_to_baseband_to_earpiece(void)
 712 {
 713         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 714
 715         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)return;
 716         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
 717         wm8994_reset();
 718         msleep(WM8994_DELAY);
 719
 720         wm8994_write(0x01,  0x0003);
 721         msleep(WM8994_DELAY);
 722
 723         wm8994_write(0x200, 0x0001);
 724         wm8994_write(0x220, 0x0000);
 725         wm8994_write(0x221, 0x0700);
 726         wm8994_write(0x222, 0x3126);
 727         wm8994_write(0x223, 0x0100);
 728
 729         wm8994_write(0x210, 0x0083); // SR=48KHz
 730         wm8994_write(0x220, 0x0004);
 731         msleep(WM8994_DELAY);
 732         wm8994_write(0x220, 0x0005);
 733         wm8994_write(0x200, 0x0011); // sysclk = fll (bit4 =1)   0x0011
 734         wm8994_write(0x300, 0x4010); // i2s 16 bits
 735
 736         wm8994_write(0x01,  0x0803|wm8994_mic_VCC); //HPOUT2_ENA=1, VMID_SEL=01, BIAS_ENA=1
 737         wm8994_write(0x02,  0x6210); //bit4 IN1R_ENV bit6 IN1L_ENV
 738         wm8994_write(0x03,  0x30F0);
 739         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 740         //wm8994_write(0x18,  0x015B); //IN1_VU=1, IN1L_MUTE=0, IN1L_ZC=1, IN1L_VOL=0_1011
 741         wm8994_write(0x05,  0x0303);
 742         wm8994_write(0x1A,  0x015F); //in1r main mic volume
 743         wm8994_write(0x1E,  0x0006);
 744         wm8994_write(0x1F,  0x0000);
 745         wm8994_write(0x28,  0x0003); //0x0030
 746         wm8994_write(0x2B,  0x0005); //VRX_MIXINL_VOL
 747         wm8994_write(0x2D,  0x0041); //DAC1L_TO_MIXOUTL=1
 748         wm8994_write(0x2E,  0x0001); //DAC1R_TO_MIXOUTR=1
 749         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 750         wm8994_write(0x33,  0x0010);
 751         wm8994_write(0x34,  0x0004); //MIXOUTR_TO_SPKMIXR =1 un-mute 0x0002
 752
 753         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 754         wm8994_write(0x601, 0x0001); //AIF1DAC1L_TO_DAC1L=1
 755         wm8994_write(0x602, 0x0001); //AIF1DAC1R_TO_DAC1R=1
 756         wm8994_write(0x610, 0x01C0); //DAC1_VU=1, DAC1L_VOL=1100_0000
 757         wm8994_write(0x611, 0x01C0); //DAC1_VU=1, DAC1R_VOL=1100_0000
 758
 759         wm8994_write(0x420, 0x0000);
 760
 761 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 762         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 763         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 764         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 765         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 766 #endif
 767 }
 768
 769 void mainMIC_to_baseband_to_earpiece_I2S(void)
 770 {
 771         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 772
 773         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)return;
 774         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
 775         wm8994_reset();
 776         msleep(WM8994_DELAY);
 777
 778         wm8994_write(0x01,  0x0003);
 779         msleep(WM8994_DELAY);
 780
 781         wm8994_write(0x200, 0x0001);
 782         wm8994_write(0x220, 0x0000);
 783         wm8994_write(0x221, 0x0700);
 784         wm8994_write(0x222, 0x3126);
 785         wm8994_write(0x223, 0x0100);
 786
 787         wm8994_write(0x210, 0x0083); // SR=48KHz
 788         wm8994_write(0x220, 0x0004);
 789         msleep(WM8994_DELAY);
 790         wm8994_write(0x220, 0x0005);
 791         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 792
 793         wm8994_write(0x02,  0x6240);
 794         wm8994_write(0x04,  0x0303);  // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 795         wm8994_write(0x18,  0x015B);  //IN1_VU=1, IN1L_MUTE=0, IN1L_ZC=1, IN1L_VOL=0_1011
 796         wm8994_write(0x1E,  0x0006);
 797         wm8994_write(0x1F,  0x0000);
 798         wm8994_write(0x28,  0x0030);
 799         wm8994_write(0x29,  0x0020); //IN1L_TO_MIXINL=1, IN1L_MIXINL_VOL=0, MIXOUTL_MIXINL_VOL=000
 800         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 801
 802         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011 //cjq
 803
 804         wm8994_write(0x208, 0x000A); //DSP_FS1CLK_ENA=1, DSP_FSINTCLK_ENA=1
 805         wm8994_write(0x300, 0x0050); //AIF1ADCL_SRC=1, AIF1ADCR_SRC=1
 806         wm8994_write(0x606, 0x0002); //ADC1L_TO_AIF1ADC1L=1
 807         wm8994_write(0x607, 0x0002); //ADC1R_TO_AIF1ADC1R=1
 808
 809         wm8994_write(0x620, 0x0000); //cjq
 810         wm8994_write(0x700, 0xA101); //cjq
 811
 812         wm8994_write(0x01,  0x0833); //HPOUT2_ENA=1, VMID_SEL=01, BIAS_ENA=1
 813         wm8994_write(0x03,  0x30F0);
 814         wm8994_write(0x05,  0x0303);
 815         wm8994_write(0x2D,  0x0021); //DAC1L_TO_MIXOUTL=1
 816         wm8994_write(0x2E,  0x0001); //DAC1R_TO_MIXOUTR=1
 817
 818         wm8994_write(0x4C,  0x9F25); //cjq
 819         wm8994_write(0x60,  0x00EE); //cjq
 820
 821         wm8994_write(0x33,  0x0010);
 822         wm8994_write(0x34,  0x0002);
 823
 824         wm8994_write(0x601, 0x0001); //AIF1DAC1L_TO_DAC1L=1
 825         wm8994_write(0x602, 0x0001); //AIF1DAC1R_TO_DAC1R=1
 826         wm8994_write(0x610, 0x01FF); //DAC1_VU=1, DAC1L_VOL=1100_0000
 827         wm8994_write(0x611, 0x01FF); //DAC1_VU=1, DAC1R_VOL=1100_0000
 828
 829         wm8994_write(0x420, 0x0000);
 830
 831 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 832         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 833         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 834         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 835         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 836 #endif
 837 }
 838
 839 void mainMIC_to_baseband_to_earpiece_and_record(void)
 840 {
 841         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 842
 843         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)return;
 844         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
 845         wm8994_reset();
 846         msleep(WM8994_DELAY);
 847
 848         wm8994_write(0x01  ,0x0803|wm8994_mic_VCC);
 849         wm8994_write(0x02  ,0x6310);
 850         wm8994_write(0x03  ,0x30A0);
 851         wm8994_write(0x04  ,0x0303);
 852         wm8994_write(0x1A  ,0x014F);
 853         wm8994_write(0x1E  ,0x0006);
 854         wm8994_write(0x1F  ,0x0000);
 855         wm8994_write(0x28  ,0x0003);  //MAINMIC_TO_IN1R  //
 856         wm8994_write(0x2A  ,0x0020);  //IN1R_TO_MIXINR   //
 857         wm8994_write(0x2B  ,0x0005);  //VRX_MIXINL_VOL bit 0~2
 858         wm8994_write(0x2C  ,0x0005);  //VRX_MIXINR_VOL
 859         wm8994_write(0x2D  ,0x0040);  //MIXINL_TO_MIXOUTL
 860         wm8994_write(0x33  ,0x0010);  //MIXOUTLVOL_TO_HPOUT2
 861         wm8994_write(0x34  ,0x0004);  //IN1R_TO_LINEOUT1 //
 862         wm8994_write(0x200 ,0x0001);
 863         wm8994_write(0x208 ,0x000A);
 864         wm8994_write(0x300 ,0xC050);
 865         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 866
 867 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 868         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 869         wm8994_write(0x303, 0x0090);  // master lrck 16k
 870 #endif
 871
 872         wm8994_write(0x606 ,0x0002);
 873         wm8994_write(0x607 ,0x0002);
 874         wm8994_write(0x620 ,0x0000);
 875 }
 876
 877 void mainMIC_to_baseband_to_speakers(void)
 878 {
 879         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 880
 881         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers)return;
 882         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers;
 883         wm8994_reset();
 884         msleep(WM8994_DELAY);
 885
 886         wm8994_write(0x01,  0x0003);
 887         msleep(WM8994_DELAY);
 888
 889         wm8994_write(0x200, 0x0001);
 890         wm8994_write(0x220, 0x0000);
 891         wm8994_write(0x221, 0x0700);
 892         wm8994_write(0x222, 0x3126);
 893         wm8994_write(0x223, 0x0100);
 894
 895         wm8994_write(0x210, 0x0083); // SR=48KHz
 896         msleep(WM8994_DELAY);
 897         wm8994_write(0x220, 0x0005);
 898         wm8994_write(0x200, 0x0011);  // sysclk = fll (bit4 =1)   0x0011
 899         wm8994_write(0x300, 0xC010);  // i2s 16 bits
 900
 901         wm8994_write(0x01,  0x3013);
 902         wm8994_write(0x02,  0x6210);
 903         wm8994_write(0x03,  0x33F0);
 904         wm8994_write(0x04,  0x0303); // AIF1ADC1L_ENA=1, AIF1ADC1R_ENA=1, ADCL_ENA=1, ADCR_ENA=1
 905         wm8994_write(0x05,  0x0303);
 906         wm8994_write(0x1A,  0x0150);
 907         wm8994_write(0x1E,  0x0006);
 908         wm8994_write(0x22,  0x0000);
 909         wm8994_write(0x23,  0x0100);
 910         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 911         wm8994_write(0x28,  0x0003);  //IN1RP_TO_IN1R  IN1RN_TO_IN1R
 912         wm8994_write(0x2B,  0x0005);  //VRX_MIXINL_VOL
 913         wm8994_write(0x2D,  0x0041);  //bit 1 IN2LP_TO_MIXOUTL //0x0003 for info
 914         wm8994_write(0x2E,  0x0081);  //bit 1 IN2RP_TO_MIXOUTR //0x0003 for info
 915         wm8994_write(0x4C,  0x9F25);
 916         wm8994_write(0x60,  0x00EE);
 917         wm8994_write(0x34,  0x0004);
 918         wm8994_write(0x36,  0x000C);  //MIXOUTL_TO_SPKMIXL  MIXOUTR_TO_SPKMIXR
 919
 920         wm8994_write(0x208, 0x000A);
 921         wm8994_write(0x420, 0x0000);
 922
 923         wm8994_write(0x601, 0x0001);
 924         wm8994_write(0x602, 0x0001);
 925
 926         wm8994_write(0x610, 0x01c0);  //DAC1 Left Volume bit0~7
 927         wm8994_write(0x611, 0x01c0);  //DAC1 Right Volume bit0~7
 928
 929 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 930         wm8994_write(0x303, 0x0040); // AIF1 BCLK DIV--------AIF1CLK/4
 931         wm8994_write(0x304, 0x0040); // AIF1 ADCLRCK DIV-----BCLK/64
 932         wm8994_write(0x305, 0x0040); // AIF1 DACLRCK DIV-----BCLK/64
 933         wm8994_write(0x302, 0x4000); // AIF1_MSTR=1
 934 #endif
 935 }
 936
 937 void mainMIC_to_baseband_to_speakers_and_record(void)
 938 {
 939         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 940
 941         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record)return;
 942         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
 943         wm8994_reset();
 944         msleep(WM8994_DELAY);
 945
 946         wm8994_write(0x01, 0x3003|wm8994_mic_VCC);
 947         wm8994_write(0x02, 0x6330);
 948         wm8994_write(0x03, 0x3330);
 949         wm8994_write(0x04, 0x0303);
 950         wm8994_write(0x1A, 0x014B);
 951         wm8994_write(0x1B, 0x014B);
 952         wm8994_write(0x1E, 0x0006);
 953         wm8994_write(0x22, 0x0000);
 954         wm8994_write(0x23, 0x0100);
 955         wm8994_write(0x28, 0x0007);
 956         wm8994_write(0x2A, 0x0120);
 957         wm8994_write(0x2D, 0x0002);  //bit 1 IN2LP_TO_MIXOUTL
 958         wm8994_write(0x2E, 0x0002);  //bit 1 IN2RP_TO_MIXOUTR
 959         wm8994_write(0x34, 0x0004);
 960         wm8994_write(0x36, 0x000C);
 961         wm8994_write(0x200, 0x0001);
 962         wm8994_write(0x208, 0x000A);
 963         wm8994_write(0x300, 0xC050);
 964         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 965
 966 #ifdef CONFIG_SND_CODEC_SOC_MASTER
 967         wm8994_write(0x302, 0x4000);  // master = 0x4000 // slave= 0x0000
 968         wm8994_write(0x303, 0x0090);  // master lrck 16k
 969 #endif
 970
 971         wm8994_write(0x606, 0x0002);
 972         wm8994_write(0x607, 0x0002);
 973         wm8994_write(0x620, 0x0000);
 974 }
 975
 976 void BT_baseband(void)
 977 {
 978         DBG("%s::%d\n",__FUNCTION__,__LINE__);
 979
 980         if(wm8994_current_mode==wm8994_BT_baseband)return;
 981         wm8994_current_mode=wm8994_BT_baseband;
 982         wm8994_reset();
 983         msleep(WM8994_DELAY);
 984
 985         wm8994_write(0x01, 0x0003);
 986         wm8994_write(0x02, 0x63A0);
 987         wm8994_write(0x03, 0x30A0);
 988         wm8994_write(0x04, 0x3303);
 989         wm8994_write(0x05, 0x3002);
 990         wm8994_write(0x06, 0x000A);
 991         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
 992         wm8994_write(0x1E, 0x0006);
 993         wm8994_write(0x28, 0x00CC);
 994         wm8994_write(0x29, 0x0100);
 995         wm8994_write(0x2A, 0x0100);
 996         wm8994_write(0x2D, 0x0001);
 997         wm8994_write(0x34, 0x0001);
 998         wm8994_write(0x200, 0x0001);
 999
1000         //roger_chen@20100524
1001         //8KHz, BCLK=8KHz*128=1024KHz, Fout=2.048MHz
1002         wm8994_write(0x204, 0x0001);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=00, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1003         wm8994_write(0x208, 0x000F);
1004         wm8994_write(0x220, 0x0000);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=0, FLL1_OSC_ENA=0, FLL1_ENA=0
1005         wm8994_write(0x221, 0x2F00);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (2)(221H):  0700  FLL1_OUTDIV=2Fh, FLL1_CTRL_RATE=000, FLL1_FRATIO=000
1006         wm8994_write(0x222, 0x3126);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (3)(222H):  8FD5  FLL1_K=3126h
1007         wm8994_write(0x223, 0x0100);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (4)(223H):  00E0  FLL1_N=8h, FLL1_GAIN=0000
1008         wm8994_write(0x310, 0xC118);  //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
1009         wm8994_write(0x210, 0x0003);    // SMbus_16inx_16dat     Write  0x34      * SR=8KHz
1010         wm8994_write(0x220, 0x0004);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=0
1011         msleep(50);
1012         wm8994_write(0x220, 0x0005);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=1
1013         wm8994_write(0x204, 0x0011);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1014
1015         wm8994_write(0x440, 0x0018);
1016         wm8994_write(0x450, 0x0018);
1017         wm8994_write(0x480, 0x0000);
1018         wm8994_write(0x481, 0x0000);
1019         wm8994_write(0x4A0, 0x0000);
1020         wm8994_write(0x4A1, 0x0000);
1021         wm8994_write(0x520, 0x0000);
1022         wm8994_write(0x540, 0x0018);
1023         wm8994_write(0x580, 0x0000);
1024         wm8994_write(0x581, 0x0000);
1025         wm8994_write(0x601, 0x0004);
1026         wm8994_write(0x603, 0x000C);
1027         wm8994_write(0x604, 0x0010);
1028         wm8994_write(0x605, 0x0010);
1029         //wm8994_write(0x606, 0x0003);
1030         //wm8994_write(0x607, 0x0003);
1031         wm8994_write(0x610, 0x01C0);
1032         wm8994_write(0x612, 0x01C0);
1033         wm8994_write(0x613, 0x01C0);
1034         wm8994_write(0x620, 0x0000);
1035
1036         //roger_chen@20100519
1037         //enable AIF2 BCLK,LRCK
1038         //Rev.B and Rev.D is different
1039         wm8994_write(0x702, 0xA100);
1040         wm8994_write(0x703, 0xA100);
1041
1042         wm8994_write(0x704, 0xA100);
1043         wm8994_write(0x707, 0xA100);
1044         wm8994_write(0x708, 0x2100);
1045         wm8994_write(0x709, 0x2100);
1046         wm8994_write(0x70A, 0x2100);
1047
1048 #ifdef CONFIG_SND_CODEC_SOC_MASTER
1049         wm8994_write(0x303, 0x0090);
1050         wm8994_write(0x313, 0x0020);    // SMbus_16inx_16dat     Write  0x34      * AIF2 BCLK DIV--------AIF1CLK/2
1051         wm8994_write(0x314, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 ADCLRCK DIV-----BCLK/128
1052         wm8994_write(0x315, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 DACLRCK DIV-----BCLK/128
1053         wm8994_write(0x302, 0x4000);
1054         wm8994_write(0x312, 0x4000);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Master/Slave(312H): 7000  AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
1055 #endif
1056 }
1057
1058 void BT_baseband_and_record(void)
1059 {
1060         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1061
1062         if(wm8994_current_mode==wm8994_BT_baseband_and_record)return;
1063         wm8994_current_mode=wm8994_BT_baseband_and_record;
1064         wm8994_reset();
1065         msleep(WM8994_DELAY);
1066
1067         wm8994_write(0x01, 0x0003);
1068         wm8994_write(0x02, 0x63A0);
1069         wm8994_write(0x03, 0x30A0);
1070         wm8994_write(0x04, 0x3303);
1071         wm8994_write(0x05, 0x3002);
1072         wm8994_write(0x06, 0x000A);
1073         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1074         wm8994_write(0x1E, 0x0006);
1075         wm8994_write(0x28, 0x00CC);
1076         wm8994_write(0x29, 0x0100);
1077         wm8994_write(0x2A, 0x0100);
1078         wm8994_write(0x2D, 0x0001);
1079         wm8994_write(0x34, 0x0001);
1080         wm8994_write(0x200, 0x0001);
1081
1082         //roger_chen@20100524
1083         //8KHz, BCLK=8KHz*128=1024KHz, Fout=2.048MHz
1084         wm8994_write(0x204, 0x0001);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=00, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1085         wm8994_write(0x208, 0x000F);
1086         wm8994_write(0x220, 0x0000);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=0, FLL1_OSC_ENA=0, FLL1_ENA=0
1087         wm8994_write(0x221, 0x2F00);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (2)(221H):  0700  FLL1_OUTDIV=2Fh, FLL1_CTRL_RATE=000, FLL1_FRATIO=000
1088         wm8994_write(0x222, 0x3126);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (3)(222H):  8FD5  FLL1_K=3126h
1089         wm8994_write(0x223, 0x0100);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (4)(223H):  00E0  FLL1_N=8h, FLL1_GAIN=0000
1090         wm8994_write(0x302, 0x4000);
1091         wm8994_write(0x303, 0x0090);
1092         wm8994_write(0x310, 0xC118);  //DSP/PCM; 16bits; ADC L channel = R channel;MODE A
1093         wm8994_write(0x312, 0x4000);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Master/Slave(312H): 7000  AIF2_TRI=0, AIF2_MSTR=1, AIF2_CLK_FRC=0, AIF2_LRCLK_FRC=0
1094         wm8994_write(0x313, 0x0020);    // SMbus_16inx_16dat     Write  0x34      * AIF2 BCLK DIV--------AIF1CLK/2
1095         wm8994_write(0x314, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 ADCLRCK DIV-----BCLK/128
1096         wm8994_write(0x315, 0x0080);    // SMbus_16inx_16dat     Write  0x34      * AIF2 DACLRCK DIV-----BCLK/128
1097         wm8994_write(0x210, 0x0003);    // SMbus_16inx_16dat     Write  0x34      * SR=8KHz
1098         wm8994_write(0x220, 0x0004);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=0
1099         msleep(WM8994_DELAY);
1100         wm8994_write(0x220, 0x0005);    // SMbus_16inx_16dat     Write  0x34      * FLL1 Control (1)(220H):  0005  FLL1_FRACN_ENA=1, FLL1_OSC_ENA=0, FLL1_ENA=1
1101         wm8994_write(0x204, 0x0011);    // SMbus_16inx_16dat     Write  0x34      * AIF2 Clocking (1)(204H): 0011  AIF2CLK_SRC=10, AIF2CLK_INV=0, AIF2CLK_DIV=0, AIF2CLK_ENA=1
1102
1103         wm8994_write(0x440, 0x0018);
1104         wm8994_write(0x450, 0x0018);
1105         wm8994_write(0x480, 0x0000);
1106         wm8994_write(0x481, 0x0000);
1107         wm8994_write(0x4A0, 0x0000);
1108         wm8994_write(0x4A1, 0x0000);
1109         wm8994_write(0x520, 0x0000);
1110         wm8994_write(0x540, 0x0018);
1111         wm8994_write(0x580, 0x0000);
1112         wm8994_write(0x581, 0x0000);
1113         wm8994_write(0x601, 0x0004);
1114         wm8994_write(0x603, 0x000C);
1115         wm8994_write(0x604, 0x0010);
1116         wm8994_write(0x605, 0x0010);
1117         wm8994_write(0x606, 0x0003);
1118         wm8994_write(0x607, 0x0003);
1119         wm8994_write(0x610, 0x01C0);
1120         wm8994_write(0x612, 0x01C0);
1121         wm8994_write(0x613, 0x01C0);
1122         wm8994_write(0x620, 0x0000);
1123
1124         //roger_chen@20100519
1125         //enable AIF2 BCLK,LRCK
1126         //Rev.B and Rev.D is different
1127         wm8994_write(0x702, 0xA100);
1128         wm8994_write(0x703, 0xA100);
1129
1130         wm8994_write(0x704, 0xA100);
1131         wm8994_write(0x707, 0xA100);
1132         wm8994_write(0x708, 0x2100);
1133         wm8994_write(0x709, 0x2100);
1134         wm8994_write(0x70A, 0x2100);
1135 }
1136
1137 #else //PCM_BB
1138
1139 /******************PCM BB BEGIN*****************/
1140
1141 void handsetMIC_to_baseband_to_headset(void) //pcmbaseband
1142 {
1143         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1144
1145         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset)return;
1146         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset;
1147         wm8994_reset();
1148         msleep(50);
1149
1150         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1151         msleep(50);
1152         wm8994_write(0x221, 0x0700);
1153         wm8994_write(0x222, 0x3127);
1154         wm8994_write(0x223, 0x0100);
1155         wm8994_write(0x220, 0x0004);
1156         msleep(50);
1157         wm8994_write(0x220, 0x0005);
1158
1159         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);  ///0x0303);         // sysclk = fll (bit4 =1)   0x0011
1160         wm8994_write(0x02,  0x0240);
1161         wm8994_write(0x03,  0x0030);
1162         wm8994_write(0x04,  0x3003);
1163         wm8994_write(0x05,  0x3003);  // i2s 16 bits
1164         wm8994_write(0x18,  0x010B);
1165         wm8994_write(0x28,  0x0030);
1166         wm8994_write(0x29,  0x0020);
1167         wm8994_write(0x2D,  0x0100);  //0x0100);DAC1L_TO_HPOUT1L    ;;;bit 8
1168         wm8994_write(0x2E,  0x0100);  //0x0100);DAC1R_TO_HPOUT1R    ;;;bit 8
1169         wm8994_write(0x4C,  0x9F25);
1170         wm8994_write(0x60,  0x00EE);
1171         wm8994_write(0x200, 0x0001);
1172         wm8994_write(0x204, 0x0001);
1173         wm8994_write(0x208, 0x0007);
1174         wm8994_write(0x520, 0x0000);
1175         wm8994_write(0x601, 0x0004);  //AIF2DACL_TO_DAC1L
1176         wm8994_write(0x602, 0x0004);  //AIF2DACR_TO_DAC1R
1177
1178         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1179         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1180         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1181         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1182
1183         wm8994_write(0x702, 0xC100);
1184         wm8994_write(0x703, 0xC100);
1185         wm8994_write(0x704, 0xC100);
1186         wm8994_write(0x706, 0x4100);
1187         wm8994_write(0x204, 0x0011);
1188         wm8994_write(0x211, 0x0009);
1189         #ifdef TD688_MODE
1190         wm8994_write(0x310, 0x4108); ///0x4118);  ///interface dsp mode 16bit
1191         #endif
1192         #ifdef CHONGY_MODE
1193         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1194         #endif
1195         #ifdef MU301_MODE
1196         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1197         wm8994_write(0x241, 0x2f04);
1198         wm8994_write(0x242, 0x0000);
1199         wm8994_write(0x243, 0x0300);
1200         wm8994_write(0x240, 0x0004);
1201         msleep(40);
1202         wm8994_write(0x240, 0x0005);
1203         wm8994_write(0x204, 0x0019);
1204         wm8994_write(0x211, 0x0003);
1205         wm8994_write(0x244, 0x0c83);
1206         wm8994_write(0x620, 0x0000);
1207         #endif
1208         #ifdef THINKWILL_M800_MODE
1209         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1210         #endif
1211         wm8994_write(0x313, 0x00F0);
1212         wm8994_write(0x314, 0x0020);
1213         wm8994_write(0x315, 0x0020);
1214         wm8994_write(0x603, 0x018c);  ///0x000C);  //Rev.D ADCL SideTone
1215         wm8994_write(0x604, 0x0010); //XX
1216         wm8994_write(0x605, 0x0010); //XX
1217         wm8994_write(0x621, 0x0000);  //0x0001);   ///0x0000);
1218         wm8994_write(0x317, 0x0003);
1219         wm8994_write(0x312, 0x0000); /// as slave  ///0x4000);  //AIF2 SET AS MASTER
1220
1221         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1222 }
1223
1224 void handsetMIC_to_baseband_to_headset_and_record(void) //pcmbaseband
1225 {
1226         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1227
1228         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record)return;
1229         wm8994_current_mode=wm8994_handsetMIC_to_baseband_to_headset_and_record;
1230         wm8994_reset();
1231         msleep(50);
1232
1233         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1234         msleep(50);
1235         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1236         wm8994_write(0x222, 0x3127);
1237         wm8994_write(0x223, 0x0100);
1238         wm8994_write(0x220, 0x0004);
1239         msleep(50);
1240         wm8994_write(0x220, 0x0005);
1241
1242         wm8994_write(0x01,  0x0303|wm8994_mic_VCC);
1243         wm8994_write(0x02,  0x0240);
1244         wm8994_write(0x03,  0x0030);
1245         wm8994_write(0x04,  0x3003);
1246         wm8994_write(0x05,  0x3003);
1247         wm8994_write(0x18,  0x010B);  // 0x011F=+30dB for MIC
1248         wm8994_write(0x28,  0x0030);
1249         wm8994_write(0x29,  0x0020);
1250         wm8994_write(0x2D,  0x0100);
1251         wm8994_write(0x2E,  0x0100);
1252         wm8994_write(0x4C,  0x9F25);
1253         wm8994_write(0x60,  0x00EE);
1254         wm8994_write(0x200, 0x0001);
1255         wm8994_write(0x204, 0x0001);
1256         wm8994_write(0x208, 0x0007);
1257         wm8994_write(0x520, 0x0000);
1258         wm8994_write(0x601, 0x0004);
1259         wm8994_write(0x602, 0x0004);
1260
1261         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1262         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1263         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1264         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1265
1266         wm8994_write(0x700, 0x8141);  //SYNC issue, AIF1 ADCLRC1 from LRCK1
1267         wm8994_write(0x702, 0xC100);
1268         wm8994_write(0x703, 0xC100);
1269         wm8994_write(0x704, 0xC100);
1270         wm8994_write(0x706, 0x4100);
1271         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1272         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1273         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1274         wm8994_write(0x313, 0x00F0);
1275         wm8994_write(0x314, 0x0020);
1276         wm8994_write(0x315, 0x0020);
1277
1278         wm8994_write(0x603, 0x018c);  ///0x000C);  //Rev.D ADCL SideTone
1279         wm8994_write(0x604, 0x0010);
1280         wm8994_write(0x605, 0x0010);
1281         wm8994_write(0x621, 0x0000);
1282         //wm8994_write(0x317, 0x0003);
1283         //wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1284 ////AIF1
1285         wm8994_write(0x04,   0x3303);
1286         wm8994_write(0x200,  0x0001);
1287         wm8994_write(0x208,  0x000F);
1288         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1289         wm8994_write(0x300,  0x0118);  //DSP/PCM 16bits, R ADC = L ADC
1290         wm8994_write(0x606,  0x0003);
1291         wm8994_write(0x607,  0x0003);
1292
1293 ////AIF1 Master Clock(SR=8KHz)
1294         wm8994_write(0x200,  0x0011);
1295         wm8994_write(0x302,  0x4000);
1296         wm8994_write(0x303,  0x00F0);
1297         wm8994_write(0x304,  0x0020);
1298         wm8994_write(0x305,  0x0020);
1299
1300 ////AIF1 DAC1 HP
1301         wm8994_write(0x05,   0x3303);
1302         wm8994_write(0x420,  0x0000);
1303         wm8994_write(0x601,  0x0001);
1304         wm8994_write(0x602,  0x0001);
1305         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1306
1307         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1308 }
1309
1310 void mainMIC_to_baseband_to_earpiece(void) //pcmbaseband
1311 {
1312         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1313
1314         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)return;
1315         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece;
1316         wm8994_reset();
1317         msleep(50);
1318
1319         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1320         msleep(50);
1321         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1322         wm8994_write(0x222, 0x3127);
1323         wm8994_write(0x223, 0x0100);
1324         wm8994_write(0x220, 0x0004);
1325         msleep(50);
1326         wm8994_write(0x220, 0x0005);
1327
1328         wm8994_write(0x01,  0x0803|wm8994_mic_VCC);   ///0x0813);
1329         wm8994_write(0x02,  0x0240);   ///0x0110);
1330         wm8994_write(0x03,  0x00F0);
1331         wm8994_write(0x04,  0x3003);
1332         wm8994_write(0x05,  0x3003);
1333         wm8994_write(0x18,  0x011F);
1334         //wm8994_write(0x1A,  0x010B);
1335         wm8994_write(0x1F,  0x0000);
1336         wm8994_write(0x28,  0x0030);  ///0x0003);
1337         wm8994_write(0x29,  0x0020);
1338         //wm8994_write(0x2A,  0x0020);
1339         wm8994_write(0x2D,  0x0001);
1340         wm8994_write(0x2E,  0x0001);
1341         wm8994_write(0x33,  0x0018);
1342         //wm8994_write(0x4C,  0x9F25);
1343         //wm8994_write(0x60,  0x00EE);
1344         wm8994_write(0x200, 0x0001);
1345         wm8994_write(0x204, 0x0001);
1346         wm8994_write(0x208, 0x0007);
1347         wm8994_write(0x520, 0x0000);
1348         wm8994_write(0x601, 0x0004);
1349         wm8994_write(0x602, 0x0004);
1350
1351         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1352         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1353         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1354         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1355
1356         //wm8994_write(0x700, 0x8141);
1357         wm8994_write(0x702, 0xC100);
1358         wm8994_write(0x703, 0xC100);
1359         wm8994_write(0x704, 0xC100);
1360         wm8994_write(0x706, 0x4100);
1361         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1362         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1363         ///wm8994_write(0x310, 0x4108); /// 0x4118);  ///0x4118);  //DSP/PCM 16bits
1364         #ifdef TD688_MODE
1365         wm8994_write(0x310, 0x4108); ///0x4118);  ///interface dsp mode 16bit
1366         #endif
1367         #ifdef CHONGY_MODE
1368         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1369         #endif
1370         #ifdef MU301_MODE
1371         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1372         wm8994_write(0x241, 0x2f04);
1373         wm8994_write(0x242, 0x0000);
1374         wm8994_write(0x243, 0x0300);
1375         wm8994_write(0x240, 0x0004);
1376         msleep(40);
1377         wm8994_write(0x240, 0x0005);
1378         wm8994_write(0x204, 0x0019);
1379         wm8994_write(0x211, 0x0003);
1380         wm8994_write(0x244, 0x0c83);
1381         wm8994_write(0x620, 0x0000);
1382         #endif
1383         #ifdef THINKWILL_M800_MODE
1384         wm8994_write(0x310, 0x4118); ///0x4118);  ///interface dsp mode 16bit
1385         #endif
1386         wm8994_write(0x313, 0x00F0);
1387         wm8994_write(0x314, 0x0020);
1388         wm8994_write(0x315, 0x0020);
1389
1390         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1391         wm8994_write(0x604, 0x0010);
1392         wm8994_write(0x605, 0x0010);
1393         wm8994_write(0x621, 0x0000);  ///0x0001);
1394         wm8994_write(0x317, 0x0003);
1395         wm8994_write(0x312, 0x0000);  //AIF2 SET AS MASTER
1396
1397         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1398 }
1399
1400 void mainMIC_to_baseband_to_earpiece_and_record(void) //pcmbaseband
1401 {
1402         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1403
1404         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)return;
1405         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_earpiece_and_record;
1406         wm8994_reset();
1407         msleep(50);
1408
1409         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1410         msleep(50);
1411         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1412         wm8994_write(0x222, 0x3127);
1413         wm8994_write(0x223, 0x0100);
1414         wm8994_write(0x220, 0x0004);
1415         msleep(50);
1416         wm8994_write(0x220, 0x0005);
1417
1418         wm8994_write(0x01,  0x0803|wm8994_mic_VCC);
1419         wm8994_write(0x02,  0x0110);
1420         wm8994_write(0x03,  0x00F0);
1421         wm8994_write(0x04,  0x3003);
1422         wm8994_write(0x05,  0x3003);
1423         wm8994_write(0x1A,  0x010B);
1424         wm8994_write(0x1F,  0x0000);
1425         wm8994_write(0x28,  0x0003);
1426         wm8994_write(0x2A,  0x0020);
1427         wm8994_write(0x2D,  0x0001);
1428         wm8994_write(0x2E,  0x0001);
1429         wm8994_write(0x33,  0x0018);
1430         //wm8994_write(0x4C,  0x9F25);
1431         //wm8994_write(0x60,  0x00EE);
1432         wm8994_write(0x200, 0x0001);
1433         wm8994_write(0x204, 0x0001);
1434         wm8994_write(0x208, 0x0007);
1435         wm8994_write(0x520, 0x0000);
1436         wm8994_write(0x601, 0x0004);
1437         wm8994_write(0x602, 0x0004);
1438
1439         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1440         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1441         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1442         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1443
1444         wm8994_write(0x702, 0xC100);
1445         wm8994_write(0x703, 0xC100);
1446         wm8994_write(0x704, 0xC100);
1447         wm8994_write(0x706, 0x4100);
1448         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1449         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1450         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1451         wm8994_write(0x313, 0x00F0);
1452         wm8994_write(0x314, 0x0020);
1453         wm8994_write(0x315, 0x0020);
1454
1455         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1456         wm8994_write(0x604, 0x0010);
1457         wm8994_write(0x605, 0x0010);
1458         wm8994_write(0x621, 0x0001);
1459         //wm8994_write(0x317, 0x0003);
1460         //wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1461
1462 ////AIF1
1463         wm8994_write(0x04,   0x3303);
1464         wm8994_write(0x200,  0x0001);
1465         wm8994_write(0x208,  0x000F);
1466         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1467         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1468         wm8994_write(0x606,  0x0003);
1469         wm8994_write(0x607,  0x0003);
1470
1471 ////AIF1 Master Clock(SR=8KHz)
1472         wm8994_write(0x200,  0x0011);
1473         wm8994_write(0x302,  0x4000);
1474         wm8994_write(0x303,  0x00F0);
1475         wm8994_write(0x304,  0x0020);
1476         wm8994_write(0x305,  0x0020);
1477
1478 ////AIF1 DAC1 HP
1479         wm8994_write(0x05,   0x3303);
1480         wm8994_write(0x420,  0x0000);
1481         wm8994_write(0x601,  0x0001);
1482         wm8994_write(0x602,  0x0001);
1483         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1484
1485         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1486 }
1487
1488 void mainMIC_to_baseband_to_speakers(void) //pcmbaseband
1489 {
1490         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1491
1492         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers)return;
1493         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers;
1494         wm8994_reset();
1495         msleep(50);
1496
1497         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);  //0x0013);
1498         msleep(50);
1499         wm8994_write(0x221, 0x0700);  //MCLK=12MHz   //FLL1 CONTRLO(2)
1500         wm8994_write(0x222, 0x3127);  //FLL1 CONTRLO(3)
1501         wm8994_write(0x223, 0x0100);  //FLL1 CONTRLO(4)
1502         wm8994_write(0x220, 0x0004);  //FLL1 CONTRLO(1)
1503         msleep(50);
1504         wm8994_write(0x220, 0x0005);  //FLL1 CONTRLO(1)
1505
1506         wm8994_write(0x01,  0x3003|wm8994_mic_VCC);
1507         wm8994_write(0x02,  0x0110);
1508         wm8994_write(0x03,  0x0030);  ///0x0330);
1509         wm8994_write(0x04,  0x3003);
1510         wm8994_write(0x05,  0x3003);
1511         wm8994_write(0x1A,  0x011F);
1512         wm8994_write(0x22,  0x0000);
1513         wm8994_write(0x23,  0x0100);  ///0x0000);
1514         wm8994_write(0x25,  0x0152);
1515         wm8994_write(0x28,  0x0003);
1516         wm8994_write(0x2A,  0x0020);
1517         wm8994_write(0x2D,  0x0001);
1518         wm8994_write(0x2E,  0x0001);
1519         wm8994_write(0x36,  0x000C);  //MIXOUTL_TO_SPKMIXL  MIXOUTR_TO_SPKMIXR
1520         //wm8994_write(0x4C,  0x9F25);
1521         //wm8994_write(0x60,  0x00EE);
1522         wm8994_write(0x200, 0x0001);  //AIF1 CLOCKING(1)
1523         wm8994_write(0x204, 0x0001);  //AIF2 CLOCKING(1)
1524         wm8994_write(0x208, 0x0007);  //CLOCKING(1)
1525         wm8994_write(0x520, 0x0000);  //AIF2 DAC FILTERS(1)
1526         wm8994_write(0x601, 0x0004);  //AIF2DACL_DAC1L
1527         wm8994_write(0x602, 0x0004);  //AIF2DACR_DAC1R
1528
1529         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1530         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1531         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1532         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1533
1534         wm8994_write(0x702, 0xC100);  //GPIO3
1535         wm8994_write(0x703, 0xC100);  //GPIO4
1536         wm8994_write(0x704, 0xC100);  //GPIO5
1537         wm8994_write(0x706, 0x4100);  //GPIO7
1538         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1539         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1540         #ifdef TD688_MODE
1541         wm8994_write(0x310, 0xc108); ///0x4118);  ///interface dsp mode 16bit
1542         #endif
1543         #ifdef CHONGY_MODE
1544         wm8994_write(0x310, 0xc018); ///0x4118);  ///interface dsp mode 16bit
1545         #endif
1546         #ifdef MU301_MODE
1547         wm8994_write(0x310, 0xc118); ///0x4118);  ///interface dsp mode 16bit
1548         wm8994_write(0x241, 0x2f04);
1549         wm8994_write(0x242, 0x0000);
1550         wm8994_write(0x243, 0x0300);
1551         wm8994_write(0x240, 0x0004);
1552         msleep(40);
1553         wm8994_write(0x240, 0x0005);
1554         wm8994_write(0x204, 0x0019);
1555         wm8994_write(0x211, 0x0003);
1556         wm8994_write(0x244, 0x0c83);
1557         wm8994_write(0x620, 0x0000);
1558         #endif
1559         #ifdef THINKWILL_M800_MODE
1560         wm8994_write(0x310, 0xc118); ///0x4118);  ///interface dsp mode 16bit
1561         #endif
1562         //wm8994_write(0x310, 0xc008);  //0xC018);//  //4118);  //DSP/PCM 16bits
1563         wm8994_write(0x313, 0x00F0);  //AIF2BCLK
1564         wm8994_write(0x314, 0x0020);  //AIF2ADCLRCK
1565         wm8994_write(0x315, 0x0020);  //AIF2DACLRCLK
1566
1567         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1568         wm8994_write(0x604, 0x0020);  ///0x0010);  //ADC2_TO_DAC2L
1569         wm8994_write(0x605, 0x0020);  //0x0010);  //ADC2_TO_DAC2R
1570         wm8994_write(0x621, 0x0000);  ///0x0001);
1571         wm8994_write(0x317, 0x0003);
1572         wm8994_write(0x312, 0x0000);  //AIF2 SET AS MASTER
1573
1574         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1575 }
1576
1577 void mainMIC_to_baseband_to_speakers_and_record(void) //pcmbaseband
1578 {
1579         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1580
1581         if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record)return;
1582         wm8994_current_mode=wm8994_mainMIC_to_baseband_to_speakers_and_record;
1583         wm8994_reset();
1584         msleep(50);
1585
1586         wm8994_write(0x01,  0x0003|wm8994_mic_VCC);
1587         msleep(50);
1588         wm8994_write(0x221, 0x0700);  //MCLK=12MHz
1589         wm8994_write(0x222, 0x3127);
1590         wm8994_write(0x223, 0x0100);
1591         wm8994_write(0x220, 0x0004);
1592         msleep(50);
1593         wm8994_write(0x220, 0x0005);
1594
1595         wm8994_write(0x02,  0x0110);
1596         wm8994_write(0x03,  0x0330);
1597         wm8994_write(0x04,  0x3003);
1598         wm8994_write(0x05,  0x3003);
1599         wm8994_write(0x1A,  0x010B);
1600         wm8994_write(0x22,  0x0000);
1601         wm8994_write(0x23,  0x0000);
1602         wm8994_write(0x28,  0x0003);
1603         wm8994_write(0x2A,  0x0020);
1604         wm8994_write(0x2D,  0x0001);
1605         wm8994_write(0x2E,  0x0001);
1606         wm8994_write(0x36,  0x000C);
1607         //wm8994_write(0x4C,  0x9F25);
1608         //wm8994_write(0x60,  0x00EE);
1609         wm8994_write(0x200, 0x0001);
1610         wm8994_write(0x204, 0x0001);
1611         wm8994_write(0x208, 0x0007);
1612         wm8994_write(0x520, 0x0000);
1613         wm8994_write(0x601, 0x0004);
1614         wm8994_write(0x602, 0x0004);
1615
1616         wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1617         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1618         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1619         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1620
1621         wm8994_write(0x700, 0x8141);
1622         wm8994_write(0x702, 0xC100);
1623         wm8994_write(0x703, 0xC100);
1624         wm8994_write(0x704, 0xC100);
1625         wm8994_write(0x706, 0x4100);
1626         wm8994_write(0x204, 0x0011);  //AIF2 MCLK=FLL1
1627         wm8994_write(0x211, 0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1628         wm8994_write(0x310, 0x4118);  //DSP/PCM 16bits
1629         wm8994_write(0x313, 0x00F0);
1630         wm8994_write(0x314, 0x0020);
1631         wm8994_write(0x315, 0x0020);
1632
1633         wm8994_write(0x603, 0x018C);  //Rev.D ADCL SideTone
1634         wm8994_write(0x604, 0x0010);
1635         wm8994_write(0x605, 0x0010);
1636         wm8994_write(0x621, 0x0001);
1637         //wm8994_write(0x317, 0x0003);
1638         //wm8994_write(0x312, 0x4000);  //AIF2 SET AS MASTER
1639
1640 ////AIF1
1641         wm8994_write(0x04,   0x3303);
1642         wm8994_write(0x200,  0x0001);
1643         wm8994_write(0x208,  0x000F);
1644         wm8994_write(0x210,  0x0009);  //LRCK=8KHz, Rate=MCLK/1536
1645         wm8994_write(0x300,  0xC118);  //DSP/PCM 16bits, R ADC = L ADC
1646         wm8994_write(0x606,  0x0003);
1647         wm8994_write(0x607,  0x0003);
1648
1649 ////AIF1 Master Clock(SR=8KHz)
1650         wm8994_write(0x200,  0x0011);
1651         wm8994_write(0x302,  0x4000);
1652         wm8994_write(0x303,  0x00F0);
1653         wm8994_write(0x304,  0x0020);
1654         wm8994_write(0x305,  0x0020);
1655
1656 ////AIF1 DAC1 HP
1657         wm8994_write(0x05,   0x3303);
1658         wm8994_write(0x420,  0x0000);
1659         wm8994_write(0x601,  0x0001);
1660         wm8994_write(0x602,  0x0001);
1661         wm8994_write(0x700,  0x8140);//SYNC issue, AIF1 ADCLRC1 from FLL after AIF1 MASTER!!!
1662
1663         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1664 }
1665
1666 void BT_baseband(void) //pcmbaseband
1667 {
1668         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1669
1670         if(wm8994_current_mode==wm8994_BT_baseband)return;
1671         wm8994_current_mode=wm8994_BT_baseband;
1672         wm8994_reset();
1673         msleep(50);
1674
1675         wm8994_write(0x01 ,0x0003);
1676         msleep (50);
1677
1678         wm8994_write(0x200 ,0x0001);
1679         wm8994_write(0x221 ,0x0700);//MCLK=12MHz
1680         wm8994_write(0x222 ,0x3127);
1681         wm8994_write(0x223 ,0x0100);
1682         wm8994_write(0x220 ,0x0004);
1683         msleep (50);
1684         wm8994_write(0x220 ,0x0005);
1685
1686         wm8994_write(0x02 ,0x0000);
1687         wm8994_write(0x200 ,0x0011);// AIF1 MCLK=FLL1
1688         wm8994_write(0x210 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1689         wm8994_write(0x300 ,0x4018);// DSP/PCM 16bits
1690
1691         wm8994_write(0x204 ,0x0011);// AIF2 MCLK=FLL1
1692         wm8994_write(0x211 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1693         wm8994_write(0x310 ,0x4118);// DSP/PCM 16bits
1694         wm8994_write(0x208 ,0x000F);
1695
1696 /////AIF1
1697         wm8994_write(0x700 ,0x8101);
1698 /////AIF2
1699         wm8994_write(0x702 ,0xC100);
1700         wm8994_write(0x703 ,0xC100);
1701         wm8994_write(0x704 ,0xC100);
1702         wm8994_write(0x706 ,0x4100);
1703 /////AIF3
1704         wm8994_write(0x707 ,0xA100);
1705         wm8994_write(0x708 ,0xA100);
1706         wm8994_write(0x709 ,0xA100);
1707         wm8994_write(0x70A ,0xA100);
1708
1709         wm8994_write(0x06 ,0x0001);
1710
1711         wm8994_write(0x02 ,0x0300);
1712         wm8994_write(0x03 ,0x0030);
1713         wm8994_write(0x04 ,0x3301);//ADCL off
1714         wm8994_write(0x05 ,0x3301);//DACL off
1715
1716 //      wm8994_write(0x29 ,0x0005);
1717         wm8994_write(0x2A ,0x0005);
1718
1719         wm8994_write(0x313 ,0x00F0);
1720         wm8994_write(0x314 ,0x0020);
1721         wm8994_write(0x315 ,0x0020);
1722
1723 //      wm8994_write(0x2D ,0x0001);
1724         wm8994_write(0x2E ,0x0001);
1725         wm8994_write(0x420 ,0x0000);
1726         wm8994_write(0x520 ,0x0000);
1727         wm8994_write(0x601 ,0x0001);
1728         wm8994_write(0x602 ,0x0001);
1729         wm8994_write(0x604 ,0x0001);
1730         wm8994_write(0x605 ,0x0001);
1731 //      wm8994_write(0x606 ,0x0002);
1732         wm8994_write(0x607 ,0x0002);
1733 //      wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1734         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1735         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1736         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1737
1738
1739         wm8994_write(0x312 ,0x4000);
1740
1741         wm8994_write(0x606 ,0x0001);
1742         wm8994_write(0x607 ,0x0003);//R channel for data mix/CPU record data
1743
1744
1745 ////////////HP output test
1746         wm8994_write(0x01 ,0x0303);
1747         wm8994_write(0x4C ,0x9F25);
1748         wm8994_write(0x60 ,0x00EE);
1749 ///////////end HP test
1750
1751         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1752 }
1753
1754 void BT_baseband_and_record(void) //pcmbaseband
1755 {
1756         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1757
1758         if(wm8994_current_mode==wm8994_BT_baseband_and_record)return;
1759         wm8994_current_mode=wm8994_BT_baseband_and_record;
1760         wm8994_reset();
1761         msleep(50);
1762
1763         wm8994_write(0x01  ,0x0003);
1764         msleep (50);
1765
1766         wm8994_write(0x200 ,0x0001);
1767         wm8994_write(0x221 ,0x0700);//MCLK=12MHz
1768         wm8994_write(0x222 ,0x3127);
1769         wm8994_write(0x223 ,0x0100);
1770         wm8994_write(0x220 ,0x0004);
1771         msleep (50);
1772         wm8994_write(0x220 ,0x0005);
1773
1774         wm8994_write(0x02 ,0x0000);
1775         wm8994_write(0x200 ,0x0011);// AIF1 MCLK=FLL1
1776         wm8994_write(0x210 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1777         wm8994_write(0x300 ,0x4018);// DSP/PCM 16bits
1778
1779         wm8994_write(0x204 ,0x0011);// AIF2 MCLK=FLL1
1780         wm8994_write(0x211 ,0x0009);// LRCK=8KHz, Rate=MCLK/1536
1781         wm8994_write(0x310 ,0x4118);// DSP/PCM 16bits
1782         wm8994_write(0x208 ,0x000F);
1783
1784 /////AIF1
1785         wm8994_write(0x700 ,0x8101);
1786 /////AIF2
1787         wm8994_write(0x702 ,0xC100);
1788         wm8994_write(0x703 ,0xC100);
1789         wm8994_write(0x704 ,0xC100);
1790         wm8994_write(0x706 ,0x4100);
1791 /////AIF3
1792         wm8994_write(0x707 ,0xA100);
1793         wm8994_write(0x708 ,0xA100);
1794         wm8994_write(0x709 ,0xA100);
1795         wm8994_write(0x70A ,0xA100);
1796
1797         wm8994_write(0x06 ,0x0001);
1798
1799         wm8994_write(0x02 ,0x0300);
1800         wm8994_write(0x03 ,0x0030);
1801         wm8994_write(0x04 ,0x3301);//ADCL off
1802         wm8994_write(0x05 ,0x3301);//DACL off
1803
1804 //   wm8994_write(0x29 ,0x0005);
1805         wm8994_write(0x2A ,0x0005);
1806
1807         wm8994_write(0x313 ,0x00F0);
1808         wm8994_write(0x314 ,0x0020);
1809         wm8994_write(0x315 ,0x0020);
1810
1811 //   wm8994_write(0x2D ,0x0001);
1812         wm8994_write(0x2E ,0x0001);
1813         wm8994_write(0x420 ,0x0000);
1814         wm8994_write(0x520 ,0x0000);
1815 //  wm8994_write(0x601 ,0x0001);
1816         wm8994_write(0x602 ,0x0001);
1817         wm8994_write(0x604 ,0x0001);
1818         wm8994_write(0x605 ,0x0001);
1819 //  wm8994_write(0x606 ,0x0002);
1820         wm8994_write(0x607 ,0x0002);
1821 //      wm8994_write(0x610, 0x01C0);  //DAC1 Left Volume bit0~7
1822         wm8994_write(0x611, 0x01C0);  //DAC1 Right Volume bit0~7
1823         wm8994_write(0x612, 0x01C0);  //DAC2 Left Volume bit0~7
1824         wm8994_write(0x613, 0x01C0);  //DAC2 Right Volume bit0~7
1825
1826
1827         wm8994_write(0x312 ,0x4000);
1828
1829         wm8994_write(0x606 ,0x0001);
1830         wm8994_write(0x607 ,0x0003);//R channel for data mix/CPU record data
1831
1832
1833 ////////////HP output test
1834         wm8994_write(0x01 ,0x0303);
1835         wm8994_write(0x4C ,0x9F25);
1836         wm8994_write(0x60 ,0x00EE);
1837 ///////////end HP test
1838
1839         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1840 }
1841 #endif //PCM_BB
1842
1843
1844 typedef void (wm8994_codec_fnc_t) (void);
1845
1846 wm8994_codec_fnc_t *wm8994_codec_sequence[] = {
1847         AP_to_headset,
1848         AP_to_speakers,
1849         recorder_and_AP_to_headset,
1850         recorder_and_AP_to_speakers,
1851         FM_to_headset,
1852         FM_to_headset_and_record,
1853         FM_to_speakers,
1854         FM_to_speakers_and_record,
1855         handsetMIC_to_baseband_to_headset,
1856         handsetMIC_to_baseband_to_headset_and_record,
1857         mainMIC_to_baseband_to_earpiece,
1858         mainMIC_to_baseband_to_earpiece_and_record,
1859         mainMIC_to_baseband_to_speakers,
1860         mainMIC_to_baseband_to_speakers_and_record,
1861         BT_baseband,
1862         BT_baseband_and_record,
1863 };
1864
1865 /********************set wm8994 volume*****volume=0\1\2\3\4\5\6\7*******************/
1866
1867 void wm8994_codec_set_volume(unsigned char system_type,unsigned char volume)
1868 {
1869         DBG("%s::%d\n",__FUNCTION__,__LINE__);
1870
1871         if(system_type == VOICE_CALL||system_type == BLUETOOTH_SCO )
1872         {
1873                 if(volume<=call_maxvol)
1874                         call_vol=volume;
1875                 else{
1876                         printk("%s----%d::call volume more than max value 7\n",__FUNCTION__,__LINE__);
1877                         call_vol=call_maxvol;
1878                 }
1879                 if(wm8994_current_mode<null&&wm8994_current_mode>=wm8994_handsetMIC_to_baseband_to_headset)
1880                         wm8994_set_volume(wm8994_current_mode,call_vol,call_maxvol);
1881         }
1882         else
1883                 printk("%s----%d::system type error!\n",__FUNCTION__,__LINE__);
1884 }
1885
1886 void wm8994_set_volume(unsigned char wm8994_mode,unsigned char volume,unsigned char max_volume)
1887 {
1888         unsigned short lvol=0,rvol=0;
1889
1890         if(volume>max_volume)volume=max_volume;
1891
1892         if(wm8994_mode==wm8994_handsetMIC_to_baseband_to_headset_and_record||
1893         wm8994_mode==wm8994_handsetMIC_to_baseband_to_headset)
1894         {
1895                 wm8994_read(0x001C, &lvol);
1896                 wm8994_read(0x001D, &rvol);
1897                 //HPOUT1L_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1898                 wm8994_write(0x001C, (lvol&~0x003f)|headset_vol_table[volume]);
1899                 //HPOUT1R_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1900                 wm8994_write(0x001D, (lvol&~0x003f)|headset_vol_table[volume]);
1901         }
1902         else if(wm8994_mode==wm8994_mainMIC_to_baseband_to_speakers_and_record||
1903         wm8994_mode==wm8994_mainMIC_to_baseband_to_speakers||
1904         wm8994_mode==wm8994_mainMIC_to_baseband_with_AP_to_speakers)
1905         {
1906                 wm8994_read(0x0026, &lvol);
1907                 wm8994_read(0x0027, &rvol);
1908                 //SPKOUTL_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1909                 wm8994_write(0x0026, (lvol&~0x003f)|speakers_vol_table[volume]);
1910                 //SPKOUTR_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1911                 wm8994_write(0x0027, (lvol&~0x003f)|speakers_vol_table[volume]);
1912         }
1913         else if(wm8994_mode==wm8994_mainMIC_to_baseband_to_earpiece||
1914         wm8994_mode==wm8994_mainMIC_to_baseband_to_earpiece_and_record)
1915         {
1916                 wm8994_read(0x0020, &lvol);
1917                 wm8994_read(0x0021, &rvol);
1918                 //MIXOUTL_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1919                 wm8994_write(0x0020, (lvol&~0x003f)|earpiece_vol_table[volume]);
1920                 //MIXOUTR_VOL bit 0~5 /-57dB to +6dB in 1dB steps
1921                 wm8994_write(0x0021, (lvol&~0x003f)|earpiece_vol_table[volume]);
1922         }
1923         else if(wm8994_mode==wm8994_BT_baseband||wm8994_mode==wm8994_BT_baseband_and_record)
1924         {
1925                 wm8994_read(0x0019, &lvol);
1926                 wm8994_read(0x001b, &rvol);
1927                 //bit 0~4 /-16.5dB to +30dB in 1.5dB steps
1928                 wm8994_write(0x0019, (lvol&~0x000f)|BT_vol_table[volume]);
1929                 //bit 0~4 /-16.5dB to +30dB in 1.5dB steps
1930                 wm8994_write(0x001b, (lvol&~0x000f)|BT_vol_table[volume]);
1931         }
1932 }
1933
1934 #define SOC_DOUBLE_SWITCH_WM8994CODEC(xname, route) \
1935 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
1936         .info = snd_soc_info_route, \
1937         .get = snd_soc_get_route, .put = snd_soc_put_route, \
1938         .private_value = route }
1939
1940 int snd_soc_info_route(struct snd_kcontrol *kcontrol,
1941         struct snd_ctl_elem_info *uinfo)
1942 {
1943         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1944
1945         uinfo->count = 1;
1946         uinfo->value.integer.min = 0;
1947         uinfo->value.integer.max = 0;
1948         return 0;
1949 }
1950
1951 int snd_soc_get_route(struct snd_kcontrol *kcontrol,
1952         struct snd_ctl_elem_value *ucontrol)
1953 {
1954         return 0;
1955 }
1956
1957 int snd_soc_put_route(struct snd_kcontrol *kcontrol,
1958         struct snd_ctl_elem_value *ucontrol)
1959 {
1960         int route = kcontrol->private_value & 0xff;
1961
1962         switch(route)
1963         {
1964                 /* Speaker*/
1965                 case SPEAKER_NORMAL: //AP-> 8994Codec -> Speaker
1966                         recorder_and_AP_to_speakers();
1967                         break;
1968                 case SPEAKER_INCALL: //BB-> 8994Codec -> Speaker
1969                         mainMIC_to_baseband_to_speakers();
1970                         break;
1971
1972                 /* Headset */
1973                 case HEADSET_NORMAL:    //AP-> 8994Codec -> Headset
1974                         recorder_and_AP_to_headset();
1975                         break;
1976                 case HEADSET_INCALL:    //AP-> 8994Codec -> Headset
1977                         handsetMIC_to_baseband_to_headset();
1978                         break;
1979
1980                 /* Earpiece*/
1981                 case EARPIECE_INCALL:   //:BB-> 8994Codec -> EARPIECE
1982                         mainMIC_to_baseband_to_earpiece();
1983                         break;
1984
1985                 case EARPIECE_NORMAL:   //:BB-> 8994Codec -> EARPIECE
1986                         if(wm8994_current_mode==wm8994_handsetMIC_to_baseband_to_headset)
1987                                 recorder_and_AP_to_headset();
1988                         else if(wm8994_current_mode==wm8994_mainMIC_to_baseband_to_speakers||
1989                                 wm8994_current_mode==wm8994_mainMIC_to_baseband_to_earpiece)
1990                                 recorder_and_AP_to_speakers();
1991                         else if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers||
1992                                 wm8994_current_mode==wm8994_recorder_and_AP_to_speakers)
1993                                 break;
1994                         else{
1995                                 recorder_and_AP_to_speakers();
1996                                 printk("%s--%d--: wm8994 with null mode\n",__FUNCTION__,__LINE__);
1997                         }
1998                         break;
1999
2000
2001                 /* BLUETOOTH_SCO*/
2002                 case BLUETOOTH_SCO_INCALL:      //BB-> 8994Codec -> BLUETOOTH_SCO
2003                         BT_baseband();
2004                         break;
2005
2006                 /* BLUETOOTH_A2DP*/
2007                 case BLUETOOTH_A2DP_NORMAL:     //AP-> 8994Codec -> BLUETOOTH_A2DP
2008                         break;
2009
2010                 case MIC_CAPTURE:
2011                         if(wm8994_current_mode==wm8994_AP_to_headset)
2012                                 recorder_and_AP_to_headset();
2013                         else if(wm8994_current_mode==wm8994_AP_to_speakers)
2014                                 recorder_and_AP_to_speakers();
2015                         else if(wm8994_current_mode==wm8994_recorder_and_AP_to_speakers||
2016                                 wm8994_current_mode==wm8994_recorder_and_AP_to_headset)
2017                                 break;
2018                         else{
2019                                 recorder_and_AP_to_speakers();
2020                                 printk("%s--%d--: wm8994 with null mode\n",__FUNCTION__,__LINE__);
2021                         }
2022                         break;
2023
2024                 case EARPIECE_RINGTONE:
2025                         AP_to_speakers();
2026                         break;
2027
2028                 case HEADSET_RINGTONE:
2029                         AP_to_headset();
2030                         break;
2031
2032                 case SPEAKER_RINGTONE:
2033                         AP_to_speakers();
2034                         break;
2035
2036                 default:
2037                         //codec_daout_route();
2038                         break;
2039         }
2040         return 0;
2041 }
2042 /*
2043  * WM8994 Controls
2044  */
2045
2046 static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
2047 static const struct soc_enum bass_boost =
2048         SOC_ENUM_SINGLE(WM8994_BASS, 7, 2, bass_boost_txt);
2049
2050 static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
2051 static const struct soc_enum bass_filter =
2052         SOC_ENUM_SINGLE(WM8994_BASS, 6, 2, bass_filter_txt);
2053
2054 static const char *treble_txt[] = {"8kHz", "4kHz"};
2055 static const struct soc_enum treble =
2056         SOC_ENUM_SINGLE(WM8994_TREBLE, 6, 2, treble_txt);
2057
2058 static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
2059 static const struct soc_enum stereo_3d_lc =
2060         SOC_ENUM_SINGLE(WM8994_3D, 5, 2, stereo_3d_lc_txt);
2061
2062 static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
2063 static const struct soc_enum stereo_3d_uc =
2064         SOC_ENUM_SINGLE(WM8994_3D, 6, 2, stereo_3d_uc_txt);
2065
2066 static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
2067 static const struct soc_enum stereo_3d_func =
2068         SOC_ENUM_SINGLE(WM8994_3D, 7, 2, stereo_3d_func_txt);
2069
2070 static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
2071 static const struct soc_enum alc_func =
2072         SOC_ENUM_SINGLE(WM8994_ALC1, 7, 4, alc_func_txt);
2073
2074 static const char *ng_type_txt[] = {"Constant PGA Gain",
2075                                     "Mute ADC Output"};
2076 static const struct soc_enum ng_type =
2077         SOC_ENUM_SINGLE(WM8994_NGATE, 1, 2, ng_type_txt);
2078
2079 static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
2080 static const struct soc_enum deemph =
2081         SOC_ENUM_SINGLE(WM8994_ADCDAC, 1, 4, deemph_txt);
2082
2083 static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
2084                                    "L + R Invert"};
2085 static const struct soc_enum adcpol =
2086         SOC_ENUM_SINGLE(WM8994_ADCDAC, 5, 4, adcpol_txt);
2087
2088 static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
2089 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
2090 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
2091 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
2092 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
2093
2094 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
2095
2096 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker incall Switch", SPEAKER_INCALL),
2097 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker normal Switch", SPEAKER_NORMAL),
2098
2099 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece incall Switch", EARPIECE_INCALL),
2100 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece normal Switch", EARPIECE_NORMAL),
2101
2102 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset incall Switch", HEADSET_INCALL),
2103 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset normal Switch", HEADSET_NORMAL),
2104
2105 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth incall Switch", BLUETOOTH_SCO_INCALL),
2106 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth normal Switch", BLUETOOTH_SCO_NORMAL),
2107
2108 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP incall Switch", BLUETOOTH_A2DP_INCALL),
2109 SOC_DOUBLE_SWITCH_WM8994CODEC("Bluetooth-A2DP normal Switch", BLUETOOTH_A2DP_NORMAL),
2110
2111 SOC_DOUBLE_SWITCH_WM8994CODEC("Capture Switch", MIC_CAPTURE),
2112
2113 SOC_DOUBLE_SWITCH_WM8994CODEC("Earpiece ringtone Switch",EARPIECE_RINGTONE),
2114 SOC_DOUBLE_SWITCH_WM8994CODEC("Speaker ringtone Switch",SPEAKER_RINGTONE),
2115 SOC_DOUBLE_SWITCH_WM8994CODEC("Headset ringtone Switch",HEADSET_RINGTONE),
2116 };
2117
2118 /*
2119  * DAPM Controls
2120  */
2121
2122 static int wm8994_lrc_control(struct snd_soc_dapm_widget *w,
2123                               struct snd_kcontrol *kcontrol, int event)
2124 {
2125         return 0;
2126 }
2127
2128 static const char *wm8994_line_texts[] = {
2129         "Line 1", "Line 2", "PGA", "Differential"};
2130
2131 static const unsigned int wm8994_line_values[] = {
2132         0, 1, 3, 4};
2133
2134 static const struct soc_enum wm8994_lline_enum =
2135         SOC_VALUE_ENUM_SINGLE(WM8994_LOUTM1, 0, 7,
2136                               ARRAY_SIZE(wm8994_line_texts),
2137                               wm8994_line_texts,
2138                               wm8994_line_values);
2139 static const struct snd_kcontrol_new wm8994_left_line_controls =
2140         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
2141
2142 static const struct soc_enum wm8994_rline_enum =
2143         SOC_VALUE_ENUM_SINGLE(WM8994_ROUTM1, 0, 7,
2144                               ARRAY_SIZE(wm8994_line_texts),
2145                               wm8994_line_texts,
2146                               wm8994_line_values);
2147 static const struct snd_kcontrol_new wm8994_right_line_controls =
2148         SOC_DAPM_VALUE_ENUM("Route", wm8994_lline_enum);
2149
2150 /* Left Mixer */
2151 static const struct snd_kcontrol_new wm8994_left_mixer_controls[] = {
2152         SOC_DAPM_SINGLE("Playback Switch", WM8994_LOUTM1, 8, 1, 0),
2153         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_LOUTM1, 7, 1, 0),
2154         SOC_DAPM_SINGLE("Right Playback Switch", WM8994_LOUTM2, 8, 1, 0),
2155         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_LOUTM2, 7, 1, 0),
2156 };
2157
2158 /* Right Mixer */
2159 static const struct snd_kcontrol_new wm8994_right_mixer_controls[] = {
2160         SOC_DAPM_SINGLE("Left Playback Switch", WM8994_ROUTM1, 8, 1, 0),
2161         SOC_DAPM_SINGLE("Left Bypass Switch", WM8994_ROUTM1, 7, 1, 0),
2162         SOC_DAPM_SINGLE("Playback Switch", WM8994_ROUTM2, 8, 1, 0),
2163         SOC_DAPM_SINGLE("Right Bypass Switch", WM8994_ROUTM2, 7, 1, 0),
2164 };
2165
2166 static const char *wm8994_pga_sel[] = {"Line 1", "Line 2", "Differential"};
2167 static const unsigned int wm8994_pga_val[] = { 0, 1, 3 };
2168
2169 /* Left PGA Mux */
2170 static const struct soc_enum wm8994_lpga_enum =
2171         SOC_VALUE_ENUM_SINGLE(WM8994_LADCIN, 6, 3,
2172                               ARRAY_SIZE(wm8994_pga_sel),
2173                               wm8994_pga_sel,
2174                               wm8994_pga_val);
2175 static const struct snd_kcontrol_new wm8994_left_pga_controls =
2176         SOC_DAPM_VALUE_ENUM("Route", wm8994_lpga_enum);
2177
2178 /* Right PGA Mux */
2179 static const struct soc_enum wm8994_rpga_enum =
2180         SOC_VALUE_ENUM_SINGLE(WM8994_RADCIN, 6, 3,
2181                               ARRAY_SIZE(wm8994_pga_sel),
2182                               wm8994_pga_sel,
2183                               wm8994_pga_val);
2184 static const struct snd_kcontrol_new wm8994_right_pga_controls =
2185         SOC_DAPM_VALUE_ENUM("Route", wm8994_rpga_enum);
2186
2187 /* Differential Mux */
2188 static const char *wm8994_diff_sel[] = {"Line 1", "Line 2"};
2189 static const struct soc_enum diffmux =
2190         SOC_ENUM_SINGLE(WM8994_ADCIN, 8, 2, wm8994_diff_sel);
2191 static const struct snd_kcontrol_new wm8994_diffmux_controls =
2192         SOC_DAPM_ENUM("Route", diffmux);
2193
2194 /* Mono ADC Mux */
2195 static const char *wm8994_mono_mux[] = {"Stereo", "Mono (Left)",
2196         "Mono (Right)", "Digital Mono"};
2197 static const struct soc_enum monomux =
2198         SOC_ENUM_SINGLE(WM8994_ADCIN, 6, 4, wm8994_mono_mux);
2199 static const struct snd_kcontrol_new wm8994_monomux_controls =
2200         SOC_DAPM_ENUM("Route", monomux);
2201
2202 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
2203         SND_SOC_DAPM_MICBIAS("Mic Bias", WM8994_PWR1, 1, 0),
2204
2205         SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
2206                 &wm8994_diffmux_controls),
2207         SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
2208                 &wm8994_monomux_controls),
2209         SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
2210                 &wm8994_monomux_controls),
2211
2212         SND_SOC_DAPM_MUX("Left PGA Mux", WM8994_PWR1, 5, 0,
2213                 &wm8994_left_pga_controls),
2214         SND_SOC_DAPM_MUX("Right PGA Mux", WM8994_PWR1, 4, 0,
2215                 &wm8994_right_pga_controls),
2216
2217         SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
2218                 &wm8994_left_line_controls),
2219         SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
2220                 &wm8994_right_line_controls),
2221
2222         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8994_PWR1, 2, 0),
2223         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8994_PWR1, 3, 0),
2224
2225         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8994_PWR2, 7, 0),
2226         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8994_PWR2, 8, 0),
2227
2228         SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
2229                 &wm8994_left_mixer_controls[0],
2230                 ARRAY_SIZE(wm8994_left_mixer_controls)),
2231         SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
2232                 &wm8994_right_mixer_controls[0],
2233                 ARRAY_SIZE(wm8994_right_mixer_controls)),
2234
2235         SND_SOC_DAPM_PGA("Right Out 2", WM8994_PWR2, 3, 0, NULL, 0),
2236         SND_SOC_DAPM_PGA("Left Out 2", WM8994_PWR2, 4, 0, NULL, 0),
2237         SND_SOC_DAPM_PGA("Right Out 1", WM8994_PWR2, 5, 0, NULL, 0),
2238         SND_SOC_DAPM_PGA("Left Out 1", WM8994_PWR2, 6, 0, NULL, 0),
2239
2240         SND_SOC_DAPM_POST("LRC control", wm8994_lrc_control),
2241
2242         SND_SOC_DAPM_OUTPUT("LOUT1"),
2243         SND_SOC_DAPM_OUTPUT("ROUT1"),
2244         SND_SOC_DAPM_OUTPUT("LOUT2"),
2245         SND_SOC_DAPM_OUTPUT("ROUT2"),
2246         SND_SOC_DAPM_OUTPUT("VREF"),
2247
2248         SND_SOC_DAPM_INPUT("LINPUT1"),
2249         SND_SOC_DAPM_INPUT("LINPUT2"),
2250         SND_SOC_DAPM_INPUT("RINPUT1"),
2251         SND_SOC_DAPM_INPUT("RINPUT2"),
2252 };
2253
2254 static const struct snd_soc_dapm_route audio_map[] = {
2255
2256         { "Left Line Mux", "Line 1", "LINPUT1" },
2257         { "Left Line Mux", "Line 2", "LINPUT2" },
2258         { "Left Line Mux", "PGA", "Left PGA Mux" },
2259         { "Left Line Mux", "Differential", "Differential Mux" },
2260
2261         { "Right Line Mux", "Line 1", "RINPUT1" },
2262         { "Right Line Mux", "Line 2", "RINPUT2" },
2263         { "Right Line Mux", "PGA", "Right PGA Mux" },
2264         { "Right Line Mux", "Differential", "Differential Mux" },
2265
2266         { "Left PGA Mux", "Line 1", "LINPUT1" },
2267         { "Left PGA Mux", "Line 2", "LINPUT2" },
2268         { "Left PGA Mux", "Differential", "Differential Mux" },
2269
2270         { "Right PGA Mux", "Line 1", "RINPUT1" },
2271         { "Right PGA Mux", "Line 2", "RINPUT2" },
2272         { "Right PGA Mux", "Differential", "Differential Mux" },
2273
2274         { "Differential Mux", "Line 1", "LINPUT1" },
2275         { "Differential Mux", "Line 1", "RINPUT1" },
2276         { "Differential Mux", "Line 2", "LINPUT2" },
2277         { "Differential Mux", "Line 2", "RINPUT2" },
2278
2279         { "Left ADC Mux", "Stereo", "Left PGA Mux" },
2280         { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
2281         { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
2282
2283         { "Right ADC Mux", "Stereo", "Right PGA Mux" },
2284         { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
2285         { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
2286
2287         { "Left ADC", NULL, "Left ADC Mux" },
2288         { "Right ADC", NULL, "Right ADC Mux" },
2289
2290         { "Left Line Mux", "Line 1", "LINPUT1" },
2291         { "Left Line Mux", "Line 2", "LINPUT2" },
2292         { "Left Line Mux", "PGA", "Left PGA Mux" },
2293         { "Left Line Mux", "Differential", "Differential Mux" },
2294
2295         { "Right Line Mux", "Line 1", "RINPUT1" },
2296         { "Right Line Mux", "Line 2", "RINPUT2" },
2297         { "Right Line Mux", "PGA", "Right PGA Mux" },
2298         { "Right Line Mux", "Differential", "Differential Mux" },
2299
2300         { "Left Mixer", "Playback Switch", "Left DAC" },
2301         { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
2302         { "Left Mixer", "Right Playback Switch", "Right DAC" },
2303         { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
2304
2305         { "Right Mixer", "Left Playback Switch", "Left DAC" },
2306         { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
2307         { "Right Mixer", "Playback Switch", "Right DAC" },
2308         { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
2309
2310         { "Left Out 1", NULL, "Left Mixer" },
2311         { "LOUT1", NULL, "Left Out 1" },
2312         { "Right Out 1", NULL, "Right Mixer" },
2313         { "ROUT1", NULL, "Right Out 1" },
2314
2315         { "Left Out 2", NULL, "Left Mixer" },
2316         { "LOUT2", NULL, "Left Out 2" },
2317         { "Right Out 2", NULL, "Right Mixer" },
2318         { "ROUT2", NULL, "Right Out 2" },
2319 };
2320
2321 struct _coeff_div {
2322         u32 mclk;
2323         u32 rate;
2324         u16 fs;
2325         u8 sr:5;
2326         u8 usb:1;
2327 };
2328
2329 /* codec hifi mclk clock divider coefficients */
2330 static const struct _coeff_div coeff_div[] = {
2331         /* 8k */
2332         {12288000, 8000, 1536, 0x6, 0x0},
2333         {11289600, 8000, 1408, 0x16, 0x0},
2334         {18432000, 8000, 2304, 0x7, 0x0},
2335         {16934400, 8000, 2112, 0x17, 0x0},
2336         {12000000, 8000, 1500, 0x6, 0x1},
2337
2338         /* 11.025k */
2339         {11289600, 11025, 1024, 0x18, 0x0},
2340         {16934400, 11025, 1536, 0x19, 0x0},
2341         {12000000, 11025, 1088, 0x19, 0x1},
2342
2343         /* 16k */
2344         {12288000, 16000, 768, 0xa, 0x0},
2345         {18432000, 16000, 1152, 0xb, 0x0},
2346         {12000000, 16000, 750, 0xa, 0x1},
2347
2348         /* 22.05k */
2349         {11289600, 22050, 512, 0x1a, 0x0},
2350         {16934400, 22050, 768, 0x1b, 0x0},
2351         {12000000, 22050, 544, 0x1b, 0x1},
2352
2353         /* 32k */
2354         {12288000, 32000, 384, 0xc, 0x0},
2355         {18432000, 32000, 576, 0xd, 0x0},
2356         {12000000, 32000, 375, 0xa, 0x1},
2357
2358         /* 44.1k */
2359         {11289600, 44100, 256, 0x10, 0x0},
2360         {16934400, 44100, 384, 0x11, 0x0},
2361         {12000000, 44100, 272, 0x11, 0x1},
2362
2363         /* 48k */
2364         {12288000, 48000, 256, 0x0, 0x0},
2365         {18432000, 48000, 384, 0x1, 0x0},
2366         {12000000, 48000, 250, 0x0, 0x1},
2367
2368         /* 88.2k */
2369         {11289600, 88200, 128, 0x1e, 0x0},
2370         {16934400, 88200, 192, 0x1f, 0x0},
2371         {12000000, 88200, 136, 0x1f, 0x1},
2372
2373         /* 96k */
2374         {12288000, 96000, 128, 0xe, 0x0},
2375         {18432000, 96000, 192, 0xf, 0x0},
2376         {12000000, 96000, 125, 0xe, 0x1},
2377 };
2378
2379
2380 static inline int get_coeff(int mclk, int rate)
2381 {
2382         int i;
2383
2384         for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
2385                 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
2386                         return i;
2387         }
2388
2389         return -EINVAL;
2390 }
2391
2392 /* The set of rates we can generate from the above for each SYSCLK */
2393
2394 static unsigned int rates_12288[] = {
2395         8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
2396 };
2397
2398 static struct snd_pcm_hw_constraint_list constraints_12288 = {
2399         .count  = ARRAY_SIZE(rates_12288),
2400         .list   = rates_12288,
2401 };
2402
2403 static unsigned int rates_112896[] = {
2404         8000, 11025, 22050, 44100,
2405 };
2406
2407 static struct snd_pcm_hw_constraint_list constraints_112896 = {
2408         .count  = ARRAY_SIZE(rates_112896),
2409         .list   = rates_112896,
2410 };
2411
2412 static unsigned int rates_12[] = {
2413         8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
2414         48000, 88235, 96000,
2415 };
2416
2417 static struct snd_pcm_hw_constraint_list constraints_12 = {
2418         .count  = ARRAY_SIZE(rates_12),
2419         .list   = rates_12,
2420 };
2421
2422 /*
2423  * Note that this should be called from init rather than from hw_params.
2424  */
2425 static int wm8994_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2426                 int clk_id, unsigned int freq, int dir)
2427 {
2428         struct snd_soc_codec *codec = codec_dai->codec;
2429         struct wm8994_priv *wm8994 = codec->private_data;
2430
2431         DBG("%s----%d\n",__FUNCTION__,__LINE__);
2432
2433         switch (freq) {
2434         case 11289600:
2435         case 18432000:
2436         case 22579200:
2437         case 36864000:
2438                 wm8994->sysclk_constraints = &constraints_112896;
2439                 wm8994->sysclk = freq;
2440                 return 0;
2441
2442         case 12288000:
2443         case 16934400:
2444         case 24576000:
2445         case 33868800:
2446                 wm8994->sysclk_constraints = &constraints_12288;
2447                 wm8994->sysclk = freq;
2448                 return 0;
2449
2450         case 12000000:
2451         case 24000000:
2452                 wm8994->sysclk_constraints = &constraints_12;
2453                 wm8994->sysclk = freq;
2454                 return 0;
2455         }
2456         return -EINVAL;
2457 }
2458
2459 static int wm8994_set_dai_fmt(struct snd_soc_dai *codec_dai,
2460                 unsigned int fmt)
2461 {
2462         return 0;
2463 }
2464
2465 static int wm8994_pcm_startup(struct snd_pcm_substream *substream,
2466                               struct snd_soc_dai *dai)
2467 {
2468         struct snd_soc_codec *codec = dai->codec;
2469         struct wm8994_priv *wm8994 = codec->private_data;
2470
2471         /* The set of sample rates that can be supported depends on the
2472          * MCLK supplied to the CODEC - enforce this.
2473          */
2474
2475         if (!wm8994->sysclk) {
2476                 dev_err(codec->dev,
2477                         "No MCLK configured, call set_sysclk() on init\n");
2478                 return -EINVAL;
2479         }
2480
2481         snd_pcm_hw_constraint_list(substream->runtime, 0,
2482                                    SNDRV_PCM_HW_PARAM_RATE,
2483                                    wm8994->sysclk_constraints);
2484
2485         return 0;
2486 }
2487
2488 static int wm8994_pcm_hw_params(struct snd_pcm_substream *substream,
2489                                 struct snd_pcm_hw_params *params,
2490                                 struct snd_soc_dai *dai)
2491 {
2492         struct snd_soc_pcm_runtime *rtd = substream->private_data;
2493         struct snd_soc_device *socdev = rtd->socdev;
2494         struct snd_soc_codec *codec = socdev->card->codec;
2495         struct wm8994_priv *wm8994 = codec->private_data;
2496         int coeff;
2497
2498         coeff = get_coeff(wm8994->sysclk, params_rate(params));
2499         if (coeff < 0) {
2500                 coeff = get_coeff(wm8994->sysclk / 2, params_rate(params));
2501         }
2502         if (coeff < 0) {
2503                 dev_err(codec->dev,
2504                         "Unable to configure sample rate %dHz with %dHz MCLK\n",
2505                         params_rate(params), wm8994->sysclk);
2506                 return coeff;
2507         }
2508         params_format(params);
2509
2510         return 0;
2511 }
2512
2513 static int wm8994_mute(struct snd_soc_dai *dai, int mute)
2514 {
2515         return 0;
2516 }
2517
2518 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2519                                  enum snd_soc_bias_level level)
2520 {
2521
2522         codec->bias_level = level;
2523         return 0;
2524 }
2525
2526 #define WM8994_RATES SNDRV_PCM_RATE_48000
2527
2528 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2529         SNDRV_PCM_FMTBIT_S24_LE)
2530
2531 static struct snd_soc_dai_ops wm8994_ops = {
2532         .startup = wm8994_pcm_startup,
2533         .hw_params = wm8994_pcm_hw_params,
2534         .set_fmt = wm8994_set_dai_fmt,
2535         .set_sysclk = wm8994_set_dai_sysclk,
2536         .digital_mute = wm8994_mute,
2537         /*add by qiuen for volume*/
2538         .set_volume = wm8994_codec_set_volume,
2539 };
2540
2541 struct snd_soc_dai wm8994_dai = {
2542         .name = "WM8994",
2543         .playback = {
2544                 .stream_name = "Playback",
2545                 .channels_min = 1,
2546                 .channels_max = 2,
2547                 .rates = WM8994_RATES,
2548                 .formats = WM8994_FORMATS,
2549         },
2550         .capture = {
2551                 .stream_name = "Capture",
2552                 .channels_min = 2,
2553                 .channels_max = 2,
2554                 .rates = WM8994_RATES,
2555                 .formats = WM8994_FORMATS,
2556          },
2557         .ops = &wm8994_ops,
2558         .symmetric_rates = 1,
2559 };
2560 EXPORT_SYMBOL_GPL(wm8994_dai);
2561
2562 static int wm8994_suspend(struct platform_device *pdev, pm_message_t state)
2563 {
2564         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2565         struct snd_soc_codec *codec = socdev->card->codec;
2566
2567         wm8994_set_bias_level(codec,SND_SOC_BIAS_OFF);
2568         wm8994_reset();
2569         msleep(WM8994_DELAY);
2570         return 0;
2571 }
2572
2573 static int wm8994_resume(struct platform_device *pdev)
2574 {
2575         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2576         struct snd_soc_codec *codec = socdev->card->codec;
2577         wm8994_codec_fnc_t **wm8994_fnc_ptr=wm8994_codec_sequence;
2578         unsigned char wm8994_resume_mode=wm8994_current_mode;
2579         wm8994_current_mode=null;
2580
2581         wm8994_set_bias_level(codec,SND_SOC_BIAS_STANDBY);
2582         if(wm8994_resume_mode<=wm8994_recorder_and_AP_to_speakers)
2583         {
2584                 wm8994_fnc_ptr+=wm8994_resume_mode;
2585                 (*wm8994_fnc_ptr)() ;
2586         }
2587         else if(wm8994_resume_mode>wm8994_BT_baseband_and_record)
2588         {
2589                 printk("%s--%d--: Wm8994 resume with null mode\n",__FUNCTION__,__LINE__);
2590         }
2591         else
2592         {
2593                 wm8994_fnc_ptr+=wm8994_resume_mode;
2594                 (*wm8994_fnc_ptr)();
2595                 printk("%s--%d--: Wm8994 resume with error mode\n",__FUNCTION__,__LINE__);
2596         }
2597
2598         return 0;
2599 }
2600
2601 static struct snd_soc_codec *wm8994_codec;
2602
2603 static int wm8994_probe(struct platform_device *pdev)
2604 {
2605         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2606         struct snd_soc_codec *codec;
2607         int ret = 0;
2608
2609         if (wm8994_codec == NULL) {
2610                 dev_err(&pdev->dev, "Codec device not registered\n");
2611                 return -ENODEV;
2612         }
2613
2614         socdev->card->codec = wm8994_codec;
2615         codec = wm8994_codec;
2616
2617         /* register pcms */
2618         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2619         if (ret < 0) {
2620                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
2621                 goto pcm_err;
2622         }
2623
2624         snd_soc_add_controls(codec,wm8994_snd_controls,
2625                                 ARRAY_SIZE(wm8994_snd_controls));
2626         snd_soc_dapm_new_controls(codec,wm8994_dapm_widgets,
2627                                   ARRAY_SIZE(wm8994_dapm_widgets));
2628         snd_soc_dapm_add_routes(codec,audio_map, ARRAY_SIZE(audio_map));
2629         snd_soc_dapm_new_widgets(codec);
2630
2631         ret = snd_soc_init_card(socdev);
2632         if (ret < 0) {
2633                 dev_err(codec->dev, "failed to register card: %d\n", ret);
2634                 goto card_err;
2635         }
2636
2637         return ret;
2638
2639 card_err:
2640         snd_soc_free_pcms(socdev);
2641         snd_soc_dapm_free(socdev);
2642 pcm_err:
2643         return ret;
2644 }
2645
2646 static int wm8994_remove(struct platform_device *pdev)
2647 {
2648         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2649
2650         snd_soc_free_pcms(socdev);
2651         snd_soc_dapm_free(socdev);
2652
2653         return 0;
2654 }
2655
2656 struct snd_soc_codec_device soc_codec_dev_wm8994 = {
2657         .probe =        wm8994_probe,
2658         .remove =       wm8994_remove,
2659         .suspend =      wm8994_suspend,
2660         .resume =       wm8994_resume,
2661 };
2662 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8994);
2663
2664 static int wm8994_register(struct wm8994_priv *wm8994,
2665                            enum snd_soc_control_type control)
2666 {
2667         struct snd_soc_codec *codec = &wm8994->codec;
2668         int ret;
2669
2670         if (wm8994_codec) {
2671                 dev_err(codec->dev, "Another WM8994 is registered\n");
2672                 ret = -EINVAL;
2673                 goto err;
2674         }
2675
2676         mutex_init(&codec->mutex);
2677         INIT_LIST_HEAD(&codec->dapm_widgets);
2678         INIT_LIST_HEAD(&codec->dapm_paths);
2679
2680         codec->private_data = wm8994;
2681         codec->name = "WM8994";
2682         codec->owner = THIS_MODULE;
2683         codec->dai = &wm8994_dai;
2684         codec->num_dai = 1;
2685         codec->reg_cache_size = ARRAY_SIZE(wm8994->reg_cache);
2686         codec->reg_cache = &wm8994->reg_cache;
2687         codec->bias_level = SND_SOC_BIAS_OFF;
2688         codec->set_bias_level = wm8994_set_bias_level;
2689
2690         memcpy(codec->reg_cache, wm8994_reg,
2691                sizeof(wm8994_reg));
2692
2693         ret = snd_soc_codec_set_cache_io(codec,7, 9, control);
2694         if (ret < 0) {
2695                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2696                 goto err;
2697         }
2698
2699         ret = 0;//wm8994_reset(); cjq
2700         if (ret < 0) {
2701                 dev_err(codec->dev, "Failed to issue reset\n");
2702                 goto err;
2703         }
2704
2705         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_STANDBY);
2706
2707         wm8994_dai.dev = codec->dev;
2708
2709         wm8994_codec = codec;
2710
2711         ret = snd_soc_register_codec(codec);
2712         if (ret != 0) {
2713                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
2714                 goto err;
2715         }
2716
2717         ret = snd_soc_register_dai(&wm8994_dai);
2718         if (ret != 0) {
2719                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
2720                 snd_soc_unregister_codec(codec);
2721                 goto err_codec;
2722         }
2723         return 0;
2724
2725 err_codec:
2726         snd_soc_unregister_codec(codec);
2727 err:
2728         kfree(wm8994);
2729         return ret;
2730 }
2731
2732 static void wm8994_unregister(struct wm8994_priv *wm8994)
2733 {
2734         wm8994_set_bias_level(&wm8994->codec, SND_SOC_BIAS_OFF);
2735         snd_soc_unregister_dai(&wm8994_dai);
2736         snd_soc_unregister_codec(&wm8994->codec);
2737         kfree(wm8994);
2738         wm8994_codec = NULL;
2739 }
2740
2741 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2742 static int wm8994_i2c_probe(struct i2c_client *i2c,
2743                             const struct i2c_device_id *id)
2744 {
2745         struct wm8994_priv *wm8994;
2746         struct snd_soc_codec *codec;
2747         wm8994_client=i2c;
2748
2749         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2750         if (wm8994 == NULL)
2751                 return -ENOMEM;
2752
2753         codec = &wm8994->codec;
2754
2755         i2c_set_clientdata(i2c, wm8994);
2756         codec->control_data = i2c;
2757
2758         codec->dev = &i2c->dev;
2759
2760         return wm8994_register(wm8994, SND_SOC_I2C);
2761 }
2762
2763 static int wm8994_i2c_remove(struct i2c_client *client)
2764 {
2765         struct wm8994_priv *wm8994 = i2c_get_clientdata(client);
2766         wm8994_unregister(wm8994);
2767         return 0;
2768 }
2769
2770 #ifdef CONFIG_PM
2771 static int wm8994_i2c_suspend(struct i2c_client *client, pm_message_t msg)
2772 {
2773         return snd_soc_suspend_device(&client->dev);
2774 }
2775
2776 static int wm8994_i2c_resume(struct i2c_client *client)
2777 {
2778         return snd_soc_resume_device(&client->dev);
2779 }
2780 #else
2781 #define wm8994_i2c_suspend NULL
2782 #define wm8994_i2c_resume NULL
2783 #endif
2784
2785 static const struct i2c_device_id wm8994_i2c_id[] = {
2786         { "wm8994", 0 },
2787         { }
2788 };
2789 MODULE_DEVICE_TABLE(i2c, wm8994_i2c_id);
2790
2791 static struct i2c_driver wm8994_i2c_driver = {
2792         .driver = {
2793                 .name = "WM8994",
2794                 .owner = THIS_MODULE,
2795         },
2796         .probe = wm8994_i2c_probe,
2797         .remove = wm8994_i2c_remove,
2798         .suspend = wm8994_i2c_suspend,
2799         .resume = wm8994_i2c_resume,
2800         .id_table = wm8994_i2c_id,
2801 };
2802
2803 int reg_send_data(struct i2c_client *client, unsigned short *reg, unsigned short *data, u32 scl_rate)
2804 {
2805         int ret;
2806         struct i2c_adapter *adap = client->adapter;
2807         struct i2c_msg msg;
2808         char tx_buf[4];
2809
2810         memcpy(tx_buf, reg, 2);
2811         memcpy(tx_buf+2, data, 2);
2812         msg.addr = client->addr;
2813         msg.buf = tx_buf;
2814         msg.len = 4;
2815         msg.flags = client->flags;
2816         msg.scl_rate = scl_rate;
2817         msg.read_type = I2C_NORMAL;
2818         ret = i2c_transfer(adap, &msg, 1);
2819
2820         return ret;
2821 }
2822
2823 int reg_recv_data(struct i2c_client *client, unsigned short *reg, unsigned short *buf, u32 scl_rate)
2824 {
2825         int ret;
2826         struct i2c_adapter *adap = client->adapter;
2827         struct i2c_msg msgs[2];
2828
2829         msgs[0].addr = client->addr;
2830         msgs[0].buf = (char *)reg;
2831         msgs[0].flags = client->flags;
2832         msgs[0].len = 2;
2833         msgs[0].scl_rate = scl_rate;
2834         msgs[0].read_type = I2C_NO_STOP;
2835
2836         msgs[1].addr = client->addr;
2837         msgs[1].buf = (char *)buf;
2838         msgs[1].flags = client->flags | I2C_M_RD;
2839         msgs[1].len = 2;
2840         msgs[1].scl_rate = scl_rate;
2841         msgs[1].read_type = I2C_NO_STOP;
2842
2843         ret = i2c_transfer(adap, msgs, 2);
2844
2845         return ret;
2846 }
2847
2848 #endif
2849
2850 #if defined(CONFIG_SPI_MASTER)
2851 static int __devinit wm8994_spi_probe(struct spi_device *spi)
2852 {
2853         struct wm8994_priv *wm8994;
2854         struct snd_soc_codec *codec;
2855
2856         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2857         if (wm8994 == NULL)
2858                 return -ENOMEM;
2859
2860         codec = &wm8994->codec;
2861         codec->control_data = spi;
2862         codec->dev = &spi->dev;
2863
2864         dev_set_drvdata(&spi->dev, wm8994);
2865
2866         return wm8994_register(wm8994, SND_SOC_SPI);
2867 }
2868
2869 static int __devexit wm8994_spi_remove(struct spi_device *spi)
2870 {
2871         struct wm8994_priv *wm8994 = dev_get_drvdata(&spi->dev);
2872
2873         wm8994_unregister(wm8994);
2874
2875         return 0;
2876 }
2877
2878 #ifdef CONFIG_PM
2879 static int wm8994_spi_suspend(struct spi_device *spi, pm_message_t msg)
2880 {
2881         return snd_soc_suspend_device(&spi->dev);
2882 }
2883
2884 static int wm8994_spi_resume(struct spi_device *spi)
2885 {
2886         return snd_soc_resume_device(&spi->dev);
2887 }
2888 #else
2889 #define wm8994_spi_suspend NULL
2890 #define wm8994_spi_resume NULL
2891 #endif
2892
2893 static struct spi_driver wm8994_spi_driver = {
2894         .driver = {
2895                 .name   = "wm8994",
2896                 .bus    = &spi_bus_type,
2897                 .owner  = THIS_MODULE,
2898         },
2899         .probe          = wm8994_spi_probe,
2900         .remove         = __devexit_p(wm8994_spi_remove),
2901         .suspend        = wm8994_spi_suspend,
2902         .resume         = wm8994_spi_resume,
2903 };
2904 #endif
2905
2906 static int __init wm8994_modinit(void)
2907 {
2908         int ret;
2909
2910 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2911         ret = i2c_add_driver(&wm8994_i2c_driver);
2912         if (ret != 0)
2913                 pr_err("WM8994: Unable to register I2C driver: %d\n", ret);
2914 #endif
2915 #if defined(CONFIG_SPI_MASTER)
2916         ret = spi_register_driver(&wm8994_spi_driver);
2917         if (ret != 0)
2918                 pr_err("WM8994: Unable to register SPI driver: %d\n", ret);
2919 #endif
2920         return ret;
2921 }
2922 module_init(wm8994_modinit);
2923
2924 static void __exit wm8994_exit(void)
2925 {
2926 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2927         i2c_del_driver(&wm8994_i2c_driver);
2928 #endif
2929 #if defined(CONFIG_SPI_MASTER)
2930         spi_unregister_driver(&wm8994_spi_driver);
2931 #endif
2932 }
2933 module_exit(wm8994_exit);
2934
2935
2936 MODULE_DESCRIPTION("ASoC WM8994 driver");
2937 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2938 MODULE_LICENSE("GPL");