2 * wm8994.c -- WM8994 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <sound/core.h>
25 #include <sound/jack.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
31 #include <trace/events/asoc.h>
33 #include <linux/mfd/wm8994/core.h>
34 #include <linux/mfd/wm8994/registers.h>
35 #include <linux/mfd/wm8994/pdata.h>
36 #include <linux/mfd/wm8994/gpio.h>
41 #define WM8994_NUM_DRC 3
42 #define WM8994_NUM_EQ 3
44 static int wm8994_drc_base[] = {
50 static int wm8994_retune_mobile_base[] = {
51 WM8994_AIF1_DAC1_EQ_GAINS_1,
52 WM8994_AIF1_DAC2_EQ_GAINS_1,
53 WM8994_AIF2_EQ_GAINS_1,
56 static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
58 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
59 struct wm8994 *control = wm8994->control_data;
73 case WM8994_INTERRUPT_STATUS_1:
74 case WM8994_INTERRUPT_STATUS_2:
75 case WM8994_INTERRUPT_RAW_STATUS_2:
78 case WM8958_DSP2_PROGRAM:
79 case WM8958_DSP2_CONFIG:
80 case WM8958_DSP2_EXECCONTROL:
81 if (control->type == WM8958)
90 if (reg >= WM8994_CACHE_SIZE)
92 return wm8994_access_masks[reg].readable != 0;
95 static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
97 if (reg >= WM8994_CACHE_SIZE)
101 case WM8994_SOFTWARE_RESET:
102 case WM8994_CHIP_REVISION:
103 case WM8994_DC_SERVO_1:
104 case WM8994_DC_SERVO_READBACK:
105 case WM8994_RATE_STATUS:
108 case WM8958_DSP2_EXECCONTROL:
109 case WM8958_MIC_DETECT_3:
116 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
121 BUG_ON(reg > WM8994_MAX_REGISTER);
123 if (!wm8994_volatile(codec, reg)) {
124 ret = snd_soc_cache_write(codec, reg, value);
126 dev_err(codec->dev, "Cache write to %x failed: %d\n",
130 return wm8994_reg_write(codec->control_data, reg, value);
133 static unsigned int wm8994_read(struct snd_soc_codec *codec,
139 BUG_ON(reg > WM8994_MAX_REGISTER);
141 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
142 reg < codec->driver->reg_cache_size) {
143 ret = snd_soc_cache_read(codec, reg, &val);
147 dev_err(codec->dev, "Cache read from %x failed: %d\n",
151 return wm8994_reg_read(codec->control_data, reg);
154 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
156 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
166 switch (wm8994->sysclk[aif]) {
167 case WM8994_SYSCLK_MCLK1:
168 rate = wm8994->mclk[0];
171 case WM8994_SYSCLK_MCLK2:
173 rate = wm8994->mclk[1];
176 case WM8994_SYSCLK_FLL1:
178 rate = wm8994->fll[0].out;
181 case WM8994_SYSCLK_FLL2:
183 rate = wm8994->fll[1].out;
190 if (rate >= 13500000) {
192 reg1 |= WM8994_AIF1CLK_DIV;
194 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
198 wm8994->aifclk[aif] = rate;
200 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
201 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
207 static int configure_clock(struct snd_soc_codec *codec)
209 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
212 /* Bring up the AIF clocks first */
213 configure_aif_clock(codec, 0);
214 configure_aif_clock(codec, 1);
216 /* Then switch CLK_SYS over to the higher of them; a change
217 * can only happen as a result of a clocking change which can
218 * only be made outside of DAPM so we can safely redo the
222 /* If they're equal it doesn't matter which is used */
223 if (wm8994->aifclk[0] == wm8994->aifclk[1])
226 if (wm8994->aifclk[0] < wm8994->aifclk[1])
227 new = WM8994_SYSCLK_SRC;
231 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
233 /* If there's no change then we're done. */
237 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
239 snd_soc_dapm_sync(&codec->dapm);
244 static int check_clk_sys(struct snd_soc_dapm_widget *source,
245 struct snd_soc_dapm_widget *sink)
247 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
250 /* Check what we're currently using for CLK_SYS */
251 if (reg & WM8994_SYSCLK_SRC)
256 return strcmp(source->name, clk) == 0;
259 static const char *sidetone_hpf_text[] = {
260 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
263 static const struct soc_enum sidetone_hpf =
264 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
266 static const char *adc_hpf_text[] = {
267 "HiFi", "Voice 1", "Voice 2", "Voice 3"
270 static const struct soc_enum aif1adc1_hpf =
271 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
273 static const struct soc_enum aif1adc2_hpf =
274 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
276 static const struct soc_enum aif2adc_hpf =
277 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
279 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
280 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
281 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
282 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
283 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
285 #define WM8994_DRC_SWITCH(xname, reg, shift) \
286 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
287 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
288 .put = wm8994_put_drc_sw, \
289 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
291 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
292 struct snd_ctl_elem_value *ucontrol)
294 struct soc_mixer_control *mc =
295 (struct soc_mixer_control *)kcontrol->private_value;
296 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
299 /* Can't enable both ADC and DAC paths simultaneously */
300 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
301 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
302 WM8994_AIF1ADC1R_DRC_ENA_MASK;
304 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
306 ret = snd_soc_read(codec, mc->reg);
312 return snd_soc_put_volsw(kcontrol, ucontrol);
315 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
317 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
318 struct wm8994_pdata *pdata = wm8994->pdata;
319 int base = wm8994_drc_base[drc];
320 int cfg = wm8994->drc_cfg[drc];
323 /* Save any enables; the configuration should clear them. */
324 save = snd_soc_read(codec, base);
325 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
326 WM8994_AIF1ADC1R_DRC_ENA;
328 for (i = 0; i < WM8994_DRC_REGS; i++)
329 snd_soc_update_bits(codec, base + i, 0xffff,
330 pdata->drc_cfgs[cfg].regs[i]);
332 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
333 WM8994_AIF1ADC1L_DRC_ENA |
334 WM8994_AIF1ADC1R_DRC_ENA, save);
337 /* Icky as hell but saves code duplication */
338 static int wm8994_get_drc(const char *name)
340 if (strcmp(name, "AIF1DRC1 Mode") == 0)
342 if (strcmp(name, "AIF1DRC2 Mode") == 0)
344 if (strcmp(name, "AIF2DRC Mode") == 0)
349 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
350 struct snd_ctl_elem_value *ucontrol)
352 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
353 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
354 struct wm8994_pdata *pdata = wm8994->pdata;
355 int drc = wm8994_get_drc(kcontrol->id.name);
356 int value = ucontrol->value.integer.value[0];
361 if (value >= pdata->num_drc_cfgs)
364 wm8994->drc_cfg[drc] = value;
366 wm8994_set_drc(codec, drc);
371 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
372 struct snd_ctl_elem_value *ucontrol)
374 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
375 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
376 int drc = wm8994_get_drc(kcontrol->id.name);
378 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
383 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
385 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
386 struct wm8994_pdata *pdata = wm8994->pdata;
387 int base = wm8994_retune_mobile_base[block];
388 int iface, best, best_val, save, i, cfg;
390 if (!pdata || !wm8994->num_retune_mobile_texts)
405 /* Find the version of the currently selected configuration
406 * with the nearest sample rate. */
407 cfg = wm8994->retune_mobile_cfg[block];
410 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
411 if (strcmp(pdata->retune_mobile_cfgs[i].name,
412 wm8994->retune_mobile_texts[cfg]) == 0 &&
413 abs(pdata->retune_mobile_cfgs[i].rate
414 - wm8994->dac_rates[iface]) < best_val) {
416 best_val = abs(pdata->retune_mobile_cfgs[i].rate
417 - wm8994->dac_rates[iface]);
421 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
423 pdata->retune_mobile_cfgs[best].name,
424 pdata->retune_mobile_cfgs[best].rate,
425 wm8994->dac_rates[iface]);
427 /* The EQ will be disabled while reconfiguring it, remember the
428 * current configuration.
430 save = snd_soc_read(codec, base);
431 save &= WM8994_AIF1DAC1_EQ_ENA;
433 for (i = 0; i < WM8994_EQ_REGS; i++)
434 snd_soc_update_bits(codec, base + i, 0xffff,
435 pdata->retune_mobile_cfgs[best].regs[i]);
437 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
440 /* Icky as hell but saves code duplication */
441 static int wm8994_get_retune_mobile_block(const char *name)
443 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
445 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
447 if (strcmp(name, "AIF2 EQ Mode") == 0)
452 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
453 struct snd_ctl_elem_value *ucontrol)
455 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
456 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
457 struct wm8994_pdata *pdata = wm8994->pdata;
458 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
459 int value = ucontrol->value.integer.value[0];
464 if (value >= pdata->num_retune_mobile_cfgs)
467 wm8994->retune_mobile_cfg[block] = value;
469 wm8994_set_retune_mobile(codec, block);
474 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
475 struct snd_ctl_elem_value *ucontrol)
477 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
478 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
479 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
481 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
486 static const char *aif_chan_src_text[] = {
490 static const struct soc_enum aif1adcl_src =
491 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
493 static const struct soc_enum aif1adcr_src =
494 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
496 static const struct soc_enum aif2adcl_src =
497 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
499 static const struct soc_enum aif2adcr_src =
500 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
502 static const struct soc_enum aif1dacl_src =
503 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
505 static const struct soc_enum aif1dacr_src =
506 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
508 static const struct soc_enum aif2dacl_src =
509 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
511 static const struct soc_enum aif2dacr_src =
512 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
514 static const char *osr_text[] = {
515 "Low Power", "High Performance",
518 static const struct soc_enum dac_osr =
519 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
521 static const struct soc_enum adc_osr =
522 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
524 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
525 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
526 WM8994_AIF1_ADC1_RIGHT_VOLUME,
527 1, 119, 0, digital_tlv),
528 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
529 WM8994_AIF1_ADC2_RIGHT_VOLUME,
530 1, 119, 0, digital_tlv),
531 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
532 WM8994_AIF2_ADC_RIGHT_VOLUME,
533 1, 119, 0, digital_tlv),
535 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
536 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
537 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
538 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
540 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
541 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
542 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
543 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
545 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
546 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
547 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
548 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
549 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
550 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
552 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
553 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
555 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
556 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
557 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
559 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
560 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
561 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
563 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
564 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
565 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
567 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
568 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
569 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
571 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
573 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
575 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
577 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
579 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
580 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
582 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
583 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
585 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
586 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
588 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
589 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
591 SOC_ENUM("ADC OSR", adc_osr),
592 SOC_ENUM("DAC OSR", dac_osr),
594 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
595 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
596 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
597 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
599 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
600 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
601 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
602 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
604 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
605 6, 1, 1, wm_hubs_spkmix_tlv),
606 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
607 2, 1, 1, wm_hubs_spkmix_tlv),
609 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
610 6, 1, 1, wm_hubs_spkmix_tlv),
611 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
612 2, 1, 1, wm_hubs_spkmix_tlv),
614 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
615 10, 15, 0, wm8994_3d_tlv),
616 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
618 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
619 10, 15, 0, wm8994_3d_tlv),
620 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
622 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
623 10, 15, 0, wm8994_3d_tlv),
624 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
628 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
629 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
631 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
633 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
635 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
637 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
640 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
642 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
644 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
646 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
648 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
651 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
653 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
655 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
657 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
659 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
663 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
664 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
667 static int clk_sys_event(struct snd_soc_dapm_widget *w,
668 struct snd_kcontrol *kcontrol, int event)
670 struct snd_soc_codec *codec = w->codec;
673 case SND_SOC_DAPM_PRE_PMU:
674 return configure_clock(codec);
676 case SND_SOC_DAPM_POST_PMD:
677 configure_clock(codec);
684 static void wm8994_update_class_w(struct snd_soc_codec *codec)
686 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688 int source = 0; /* GCC flow analysis can't track enable */
691 /* Only support direct DAC->headphone paths */
692 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
693 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
694 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
698 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
699 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
700 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
704 /* We also need the same setting for L/R and only one path */
705 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
707 case WM8994_AIF2DACL_TO_DAC1L:
708 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
709 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
711 case WM8994_AIF1DAC2L_TO_DAC1L:
712 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
713 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
715 case WM8994_AIF1DAC1L_TO_DAC1L:
716 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
717 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
720 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
725 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
727 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
732 dev_dbg(codec->dev, "Class W enabled\n");
733 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
735 WM8994_CP_DYN_SRC_SEL_MASK,
736 source | WM8994_CP_DYN_PWR);
737 wm8994->hubs.class_w = true;
740 dev_dbg(codec->dev, "Class W disabled\n");
741 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
742 WM8994_CP_DYN_PWR, 0);
743 wm8994->hubs.class_w = false;
747 static int late_enable_ev(struct snd_soc_dapm_widget *w,
748 struct snd_kcontrol *kcontrol, int event)
750 struct snd_soc_codec *codec = w->codec;
751 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
754 case SND_SOC_DAPM_PRE_PMU:
755 if (wm8994->aif1clk_enable) {
756 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
757 WM8994_AIF1CLK_ENA_MASK,
759 wm8994->aif1clk_enable = 0;
761 if (wm8994->aif2clk_enable) {
762 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
763 WM8994_AIF2CLK_ENA_MASK,
765 wm8994->aif2clk_enable = 0;
770 /* We may also have postponed startup of DSP, handle that. */
771 wm8958_aif_ev(w, kcontrol, event);
776 static int late_disable_ev(struct snd_soc_dapm_widget *w,
777 struct snd_kcontrol *kcontrol, int event)
779 struct snd_soc_codec *codec = w->codec;
780 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
783 case SND_SOC_DAPM_POST_PMD:
784 if (wm8994->aif1clk_disable) {
785 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
786 WM8994_AIF1CLK_ENA_MASK, 0);
787 wm8994->aif1clk_disable = 0;
789 if (wm8994->aif2clk_disable) {
790 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
791 WM8994_AIF2CLK_ENA_MASK, 0);
792 wm8994->aif2clk_disable = 0;
800 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
801 struct snd_kcontrol *kcontrol, int event)
803 struct snd_soc_codec *codec = w->codec;
804 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
807 case SND_SOC_DAPM_PRE_PMU:
808 wm8994->aif1clk_enable = 1;
810 case SND_SOC_DAPM_POST_PMD:
811 wm8994->aif1clk_disable = 1;
818 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
819 struct snd_kcontrol *kcontrol, int event)
821 struct snd_soc_codec *codec = w->codec;
822 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
825 case SND_SOC_DAPM_PRE_PMU:
826 wm8994->aif2clk_enable = 1;
828 case SND_SOC_DAPM_POST_PMD:
829 wm8994->aif2clk_disable = 1;
836 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
837 struct snd_kcontrol *kcontrol, int event)
839 late_enable_ev(w, kcontrol, event);
843 static int micbias_ev(struct snd_soc_dapm_widget *w,
844 struct snd_kcontrol *kcontrol, int event)
846 late_enable_ev(w, kcontrol, event);
850 static int dac_ev(struct snd_soc_dapm_widget *w,
851 struct snd_kcontrol *kcontrol, int event)
853 struct snd_soc_codec *codec = w->codec;
854 unsigned int mask = 1 << w->shift;
856 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
861 static const char *hp_mux_text[] = {
866 #define WM8994_HP_ENUM(xname, xenum) \
867 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
868 .info = snd_soc_info_enum_double, \
869 .get = snd_soc_dapm_get_enum_double, \
870 .put = wm8994_put_hp_enum, \
871 .private_value = (unsigned long)&xenum }
873 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
874 struct snd_ctl_elem_value *ucontrol)
876 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
877 struct snd_soc_dapm_widget *w = wlist->widgets[0];
878 struct snd_soc_codec *codec = w->codec;
881 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
883 wm8994_update_class_w(codec);
888 static const struct soc_enum hpl_enum =
889 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
891 static const struct snd_kcontrol_new hpl_mux =
892 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
894 static const struct soc_enum hpr_enum =
895 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
897 static const struct snd_kcontrol_new hpr_mux =
898 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
900 static const char *adc_mux_text[] = {
905 static const struct soc_enum adc_enum =
906 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
908 static const struct snd_kcontrol_new adcl_mux =
909 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
911 static const struct snd_kcontrol_new adcr_mux =
912 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
914 static const struct snd_kcontrol_new left_speaker_mixer[] = {
915 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
916 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
917 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
918 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
919 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
922 static const struct snd_kcontrol_new right_speaker_mixer[] = {
923 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
924 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
925 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
926 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
927 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
930 /* Debugging; dump chip status after DAPM transitions */
931 static int post_ev(struct snd_soc_dapm_widget *w,
932 struct snd_kcontrol *kcontrol, int event)
934 struct snd_soc_codec *codec = w->codec;
935 dev_dbg(codec->dev, "SRC status: %x\n",
937 WM8994_RATE_STATUS));
941 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
942 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
944 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
948 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
949 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
951 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
955 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
956 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
958 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
962 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
963 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
965 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
969 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
970 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
972 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
974 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
976 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
978 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
982 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
983 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
985 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
987 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
989 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
991 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
995 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
996 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
997 .info = snd_soc_info_volsw, \
998 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
999 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1001 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1002 struct snd_ctl_elem_value *ucontrol)
1004 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1005 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1006 struct snd_soc_codec *codec = w->codec;
1009 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1011 wm8994_update_class_w(codec);
1016 static const struct snd_kcontrol_new dac1l_mix[] = {
1017 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1019 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1021 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1023 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1025 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1029 static const struct snd_kcontrol_new dac1r_mix[] = {
1030 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1032 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1034 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1036 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1038 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1042 static const char *sidetone_text[] = {
1043 "ADC/DMIC1", "DMIC2",
1046 static const struct soc_enum sidetone1_enum =
1047 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1049 static const struct snd_kcontrol_new sidetone1_mux =
1050 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1052 static const struct soc_enum sidetone2_enum =
1053 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1055 static const struct snd_kcontrol_new sidetone2_mux =
1056 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1058 static const char *aif1dac_text[] = {
1059 "AIF1DACDAT", "AIF3DACDAT",
1062 static const struct soc_enum aif1dac_enum =
1063 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1065 static const struct snd_kcontrol_new aif1dac_mux =
1066 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1068 static const char *aif2dac_text[] = {
1069 "AIF2DACDAT", "AIF3DACDAT",
1072 static const struct soc_enum aif2dac_enum =
1073 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1075 static const struct snd_kcontrol_new aif2dac_mux =
1076 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1078 static const char *aif2adc_text[] = {
1079 "AIF2ADCDAT", "AIF3DACDAT",
1082 static const struct soc_enum aif2adc_enum =
1083 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1085 static const struct snd_kcontrol_new aif2adc_mux =
1086 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1088 static const char *aif3adc_text[] = {
1089 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1092 static const struct soc_enum wm8994_aif3adc_enum =
1093 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1095 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1096 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1098 static const struct soc_enum wm8958_aif3adc_enum =
1099 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1101 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1102 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1104 static const char *mono_pcm_out_text[] = {
1105 "None", "AIF2ADCL", "AIF2ADCR",
1108 static const struct soc_enum mono_pcm_out_enum =
1109 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1111 static const struct snd_kcontrol_new mono_pcm_out_mux =
1112 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1114 static const char *aif2dac_src_text[] = {
1118 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1119 static const struct soc_enum aif2dacl_src_enum =
1120 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1122 static const struct snd_kcontrol_new aif2dacl_src_mux =
1123 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1125 static const struct soc_enum aif2dacr_src_enum =
1126 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1128 static const struct snd_kcontrol_new aif2dacr_src_mux =
1129 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1131 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1132 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1133 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1134 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1135 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1137 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1138 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1139 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1140 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1141 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1142 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1143 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1144 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1145 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1146 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1148 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1149 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1150 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1151 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1152 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1153 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1154 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1155 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1156 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1157 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1159 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1162 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1163 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1164 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1165 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1166 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1167 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1168 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1169 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1170 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1171 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1174 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1175 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1176 dac_ev, SND_SOC_DAPM_PRE_PMU),
1177 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1178 dac_ev, SND_SOC_DAPM_PRE_PMU),
1179 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1180 dac_ev, SND_SOC_DAPM_PRE_PMU),
1181 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1182 dac_ev, SND_SOC_DAPM_PRE_PMU),
1185 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1186 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1187 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1188 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1189 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1192 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1193 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1194 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1195 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1196 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1199 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1200 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1201 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1204 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1205 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1206 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1207 SND_SOC_DAPM_INPUT("Clock"),
1209 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1210 SND_SOC_DAPM_PRE_PMU),
1212 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1213 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1215 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1216 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1217 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1219 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1220 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1221 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1222 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1223 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1224 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1225 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1226 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1227 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1228 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1230 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1231 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1232 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1233 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1234 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1235 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1236 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1237 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1238 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1239 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1241 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1242 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1243 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1244 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1246 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1247 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1248 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1249 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1251 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1252 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1253 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1254 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1256 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1257 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1259 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1260 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1261 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1262 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1264 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1265 WM8994_POWER_MANAGEMENT_4, 13, 0),
1266 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1267 WM8994_POWER_MANAGEMENT_4, 12, 0),
1268 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1269 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1270 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1271 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1272 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1273 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1275 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1276 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1277 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1278 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1280 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1281 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1282 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1284 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1285 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1287 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1289 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1290 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1291 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1292 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1294 /* Power is done with the muxes since the ADC power also controls the
1295 * downsampling chain, the chip will automatically manage the analogue
1296 * specific portions.
1298 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1299 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1301 SND_SOC_DAPM_POST("Debug log", post_ev),
1304 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1305 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1308 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1309 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1310 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1311 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1312 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1315 static const struct snd_soc_dapm_route intercon[] = {
1316 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1317 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1319 { "DSP1CLK", NULL, "CLK_SYS" },
1320 { "DSP2CLK", NULL, "CLK_SYS" },
1321 { "DSPINTCLK", NULL, "CLK_SYS" },
1323 { "AIF1ADC1L", NULL, "AIF1CLK" },
1324 { "AIF1ADC1L", NULL, "DSP1CLK" },
1325 { "AIF1ADC1R", NULL, "AIF1CLK" },
1326 { "AIF1ADC1R", NULL, "DSP1CLK" },
1327 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1329 { "AIF1DAC1L", NULL, "AIF1CLK" },
1330 { "AIF1DAC1L", NULL, "DSP1CLK" },
1331 { "AIF1DAC1R", NULL, "AIF1CLK" },
1332 { "AIF1DAC1R", NULL, "DSP1CLK" },
1333 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1335 { "AIF1ADC2L", NULL, "AIF1CLK" },
1336 { "AIF1ADC2L", NULL, "DSP1CLK" },
1337 { "AIF1ADC2R", NULL, "AIF1CLK" },
1338 { "AIF1ADC2R", NULL, "DSP1CLK" },
1339 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1341 { "AIF1DAC2L", NULL, "AIF1CLK" },
1342 { "AIF1DAC2L", NULL, "DSP1CLK" },
1343 { "AIF1DAC2R", NULL, "AIF1CLK" },
1344 { "AIF1DAC2R", NULL, "DSP1CLK" },
1345 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1347 { "AIF2ADCL", NULL, "AIF2CLK" },
1348 { "AIF2ADCL", NULL, "DSP2CLK" },
1349 { "AIF2ADCR", NULL, "AIF2CLK" },
1350 { "AIF2ADCR", NULL, "DSP2CLK" },
1351 { "AIF2ADCR", NULL, "DSPINTCLK" },
1353 { "AIF2DACL", NULL, "AIF2CLK" },
1354 { "AIF2DACL", NULL, "DSP2CLK" },
1355 { "AIF2DACR", NULL, "AIF2CLK" },
1356 { "AIF2DACR", NULL, "DSP2CLK" },
1357 { "AIF2DACR", NULL, "DSPINTCLK" },
1359 { "DMIC1L", NULL, "DMIC1DAT" },
1360 { "DMIC1L", NULL, "CLK_SYS" },
1361 { "DMIC1R", NULL, "DMIC1DAT" },
1362 { "DMIC1R", NULL, "CLK_SYS" },
1363 { "DMIC2L", NULL, "DMIC2DAT" },
1364 { "DMIC2L", NULL, "CLK_SYS" },
1365 { "DMIC2R", NULL, "DMIC2DAT" },
1366 { "DMIC2R", NULL, "CLK_SYS" },
1368 { "ADCL", NULL, "AIF1CLK" },
1369 { "ADCL", NULL, "DSP1CLK" },
1370 { "ADCL", NULL, "DSPINTCLK" },
1372 { "ADCR", NULL, "AIF1CLK" },
1373 { "ADCR", NULL, "DSP1CLK" },
1374 { "ADCR", NULL, "DSPINTCLK" },
1376 { "ADCL Mux", "ADC", "ADCL" },
1377 { "ADCL Mux", "DMIC", "DMIC1L" },
1378 { "ADCR Mux", "ADC", "ADCR" },
1379 { "ADCR Mux", "DMIC", "DMIC1R" },
1381 { "DAC1L", NULL, "AIF1CLK" },
1382 { "DAC1L", NULL, "DSP1CLK" },
1383 { "DAC1L", NULL, "DSPINTCLK" },
1385 { "DAC1R", NULL, "AIF1CLK" },
1386 { "DAC1R", NULL, "DSP1CLK" },
1387 { "DAC1R", NULL, "DSPINTCLK" },
1389 { "DAC2L", NULL, "AIF2CLK" },
1390 { "DAC2L", NULL, "DSP2CLK" },
1391 { "DAC2L", NULL, "DSPINTCLK" },
1393 { "DAC2R", NULL, "AIF2DACR" },
1394 { "DAC2R", NULL, "AIF2CLK" },
1395 { "DAC2R", NULL, "DSP2CLK" },
1396 { "DAC2R", NULL, "DSPINTCLK" },
1398 { "TOCLK", NULL, "CLK_SYS" },
1401 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1402 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1403 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1405 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1406 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1407 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1409 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1410 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1411 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1413 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1414 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1415 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1417 /* Pin level routing for AIF3 */
1418 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1419 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1420 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1421 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1423 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1424 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1425 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1426 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1427 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1428 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1429 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1432 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1433 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1434 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1435 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1436 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1438 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1439 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1440 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1441 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1442 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1444 /* DAC2/AIF2 outputs */
1445 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1446 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1447 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1448 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1449 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1450 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1452 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1453 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1454 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1455 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1456 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1457 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1459 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1460 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1461 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1462 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1464 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1467 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1468 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1469 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1470 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1471 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1472 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1473 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1474 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1477 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1478 { "Left Sidetone", "DMIC2", "DMIC2L" },
1479 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1480 { "Right Sidetone", "DMIC2", "DMIC2R" },
1483 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1484 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1486 { "SPKL", "DAC1 Switch", "DAC1L" },
1487 { "SPKL", "DAC2 Switch", "DAC2L" },
1489 { "SPKR", "DAC1 Switch", "DAC1R" },
1490 { "SPKR", "DAC2 Switch", "DAC2R" },
1492 { "Left Headphone Mux", "DAC", "DAC1L" },
1493 { "Right Headphone Mux", "DAC", "DAC1R" },
1496 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1497 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1498 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1499 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1500 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1501 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1502 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1503 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1504 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1507 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1508 { "DAC1L", NULL, "DAC1L Mixer" },
1509 { "DAC1R", NULL, "DAC1R Mixer" },
1510 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1511 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1514 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1515 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1516 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1517 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1518 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1519 { "MICBIAS1", NULL, "CLK_SYS" },
1520 { "MICBIAS1", NULL, "MICBIAS Supply" },
1521 { "MICBIAS2", NULL, "CLK_SYS" },
1522 { "MICBIAS2", NULL, "MICBIAS Supply" },
1525 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1526 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1527 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1530 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1531 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1532 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1534 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1535 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1536 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1537 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1539 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1540 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1542 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1545 /* The size in bits of the FLL divide multiplied by 10
1546 * to allow rounding later */
1547 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1557 static int wm8994_get_fll_config(struct fll_div *fll,
1558 int freq_in, int freq_out)
1561 unsigned int K, Ndiv, Nmod;
1563 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1565 /* Scale the input frequency down to <= 13.5MHz */
1566 fll->clk_ref_div = 0;
1567 while (freq_in > 13500000) {
1571 if (fll->clk_ref_div > 3)
1574 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1576 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1578 while (freq_out * (fll->outdiv + 1) < 90000000) {
1580 if (fll->outdiv > 63)
1583 freq_out *= fll->outdiv + 1;
1584 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1586 if (freq_in > 1000000) {
1587 fll->fll_fratio = 0;
1588 } else if (freq_in > 256000) {
1589 fll->fll_fratio = 1;
1591 } else if (freq_in > 128000) {
1592 fll->fll_fratio = 2;
1594 } else if (freq_in > 64000) {
1595 fll->fll_fratio = 3;
1598 fll->fll_fratio = 4;
1601 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1603 /* Now, calculate N.K */
1604 Ndiv = freq_out / freq_in;
1607 Nmod = freq_out % freq_in;
1608 pr_debug("Nmod=%d\n", Nmod);
1610 /* Calculate fractional part - scale up so we can round. */
1611 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1613 do_div(Kpart, freq_in);
1615 K = Kpart & 0xFFFFFFFF;
1620 /* Move down to proper range now rounding is done */
1623 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1628 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1629 unsigned int freq_in, unsigned int freq_out)
1631 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1632 int reg_offset, ret;
1634 u16 reg, aif1, aif2;
1635 unsigned long timeout;
1637 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1638 & WM8994_AIF1CLK_ENA;
1640 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1641 & WM8994_AIF2CLK_ENA;
1658 /* Allow no source specification when stopping */
1661 src = wm8994->fll[id].src;
1663 case WM8994_FLL_SRC_MCLK1:
1664 case WM8994_FLL_SRC_MCLK2:
1665 case WM8994_FLL_SRC_LRCLK:
1666 case WM8994_FLL_SRC_BCLK:
1672 /* Are we changing anything? */
1673 if (wm8994->fll[id].src == src &&
1674 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1677 /* If we're stopping the FLL redo the old config - no
1678 * registers will actually be written but we avoid GCC flow
1679 * analysis bugs spewing warnings.
1682 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1684 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1685 wm8994->fll[id].out);
1689 /* Gate the AIF clocks while we reclock */
1690 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1691 WM8994_AIF1CLK_ENA, 0);
1692 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1693 WM8994_AIF2CLK_ENA, 0);
1695 /* We always need to disable the FLL while reconfiguring */
1696 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1697 WM8994_FLL1_ENA, 0);
1699 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1700 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1701 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1702 WM8994_FLL1_OUTDIV_MASK |
1703 WM8994_FLL1_FRATIO_MASK, reg);
1705 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1707 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1709 fll.n << WM8994_FLL1_N_SHIFT);
1711 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1712 WM8994_FLL1_REFCLK_DIV_MASK |
1713 WM8994_FLL1_REFCLK_SRC_MASK,
1714 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1717 /* Clear any pending completion from a previous failure */
1718 try_wait_for_completion(&wm8994->fll_locked[id]);
1720 /* Enable (with fractional mode if required) */
1723 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1725 reg = WM8994_FLL1_ENA;
1726 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1727 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1730 if (wm8994->fll_locked_irq) {
1731 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1732 msecs_to_jiffies(10));
1734 dev_warn(codec->dev,
1735 "Timed out waiting for FLL lock\n");
1741 wm8994->fll[id].in = freq_in;
1742 wm8994->fll[id].out = freq_out;
1743 wm8994->fll[id].src = src;
1745 /* Enable any gated AIF clocks */
1746 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1747 WM8994_AIF1CLK_ENA, aif1);
1748 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1749 WM8994_AIF2CLK_ENA, aif2);
1751 configure_clock(codec);
1756 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1758 struct completion *completion = data;
1760 complete(completion);
1765 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1767 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1768 unsigned int freq_in, unsigned int freq_out)
1770 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1773 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1774 int clk_id, unsigned int freq, int dir)
1776 struct snd_soc_codec *codec = dai->codec;
1777 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1786 /* AIF3 shares clocking with AIF1/2 */
1791 case WM8994_SYSCLK_MCLK1:
1792 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1793 wm8994->mclk[0] = freq;
1794 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1798 case WM8994_SYSCLK_MCLK2:
1799 /* TODO: Set GPIO AF */
1800 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1801 wm8994->mclk[1] = freq;
1802 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1806 case WM8994_SYSCLK_FLL1:
1807 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1808 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1811 case WM8994_SYSCLK_FLL2:
1812 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1813 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1816 case WM8994_SYSCLK_OPCLK:
1817 /* Special case - a division (times 10) is given and
1818 * no effect on main clocking.
1821 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1822 if (opclk_divs[i] == freq)
1824 if (i == ARRAY_SIZE(opclk_divs))
1826 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1827 WM8994_OPCLK_DIV_MASK, i);
1828 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1829 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1831 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1832 WM8994_OPCLK_ENA, 0);
1839 configure_clock(codec);
1844 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1845 enum snd_soc_bias_level level)
1847 struct wm8994 *control = codec->control_data;
1848 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1851 case SND_SOC_BIAS_ON:
1854 case SND_SOC_BIAS_PREPARE:
1856 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1857 WM8994_VMID_SEL_MASK, 0x2);
1860 case SND_SOC_BIAS_STANDBY:
1861 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1862 pm_runtime_get_sync(codec->dev);
1864 switch (control->type) {
1866 if (wm8994->revision < 4) {
1867 /* Tweak DC servo and DSP
1868 * configuration for improved
1870 snd_soc_write(codec, 0x102, 0x3);
1871 snd_soc_write(codec, 0x56, 0x3);
1872 snd_soc_write(codec, 0x817, 0);
1873 snd_soc_write(codec, 0x102, 0);
1878 if (wm8994->revision == 0) {
1879 /* Optimise performance for rev A */
1880 snd_soc_write(codec, 0x102, 0x3);
1881 snd_soc_write(codec, 0xcb, 0x81);
1882 snd_soc_write(codec, 0x817, 0);
1883 snd_soc_write(codec, 0x102, 0);
1885 snd_soc_update_bits(codec,
1886 WM8958_CHARGE_PUMP_2,
1893 /* Discharge LINEOUT1 & 2 */
1894 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1895 WM8994_LINEOUT1_DISCH |
1896 WM8994_LINEOUT2_DISCH,
1897 WM8994_LINEOUT1_DISCH |
1898 WM8994_LINEOUT2_DISCH);
1900 /* Startup bias, VMID ramp & buffer */
1901 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1902 WM8994_STARTUP_BIAS_ENA |
1903 WM8994_VMID_BUF_ENA |
1904 WM8994_VMID_RAMP_MASK,
1905 WM8994_STARTUP_BIAS_ENA |
1906 WM8994_VMID_BUF_ENA |
1907 (0x11 << WM8994_VMID_RAMP_SHIFT));
1909 /* Main bias enable, VMID=2x40k */
1910 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1912 WM8994_VMID_SEL_MASK,
1913 WM8994_BIAS_ENA | 0x2);
1919 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1920 WM8994_VMID_SEL_MASK, 0x4);
1924 case SND_SOC_BIAS_OFF:
1925 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1926 /* Switch over to startup biases */
1927 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1929 WM8994_STARTUP_BIAS_ENA |
1930 WM8994_VMID_BUF_ENA |
1931 WM8994_VMID_RAMP_MASK,
1933 WM8994_STARTUP_BIAS_ENA |
1934 WM8994_VMID_BUF_ENA |
1935 (1 << WM8994_VMID_RAMP_SHIFT));
1937 /* Disable main biases */
1938 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1940 WM8994_VMID_SEL_MASK, 0);
1942 /* Discharge line */
1943 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1944 WM8994_LINEOUT1_DISCH |
1945 WM8994_LINEOUT2_DISCH,
1946 WM8994_LINEOUT1_DISCH |
1947 WM8994_LINEOUT2_DISCH);
1951 /* Switch off startup biases */
1952 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1954 WM8994_STARTUP_BIAS_ENA |
1955 WM8994_VMID_BUF_ENA |
1956 WM8994_VMID_RAMP_MASK, 0);
1958 wm8994->cur_fw = NULL;
1960 pm_runtime_put(codec->dev);
1964 codec->dapm.bias_level = level;
1968 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1970 struct snd_soc_codec *codec = dai->codec;
1971 struct wm8994 *control = codec->control_data;
1979 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1980 aif1_reg = WM8994_AIF1_CONTROL_1;
1983 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1984 aif1_reg = WM8994_AIF2_CONTROL_1;
1990 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1991 case SND_SOC_DAIFMT_CBS_CFS:
1993 case SND_SOC_DAIFMT_CBM_CFM:
1994 ms = WM8994_AIF1_MSTR;
2000 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2001 case SND_SOC_DAIFMT_DSP_B:
2002 aif1 |= WM8994_AIF1_LRCLK_INV;
2003 case SND_SOC_DAIFMT_DSP_A:
2006 case SND_SOC_DAIFMT_I2S:
2009 case SND_SOC_DAIFMT_RIGHT_J:
2011 case SND_SOC_DAIFMT_LEFT_J:
2018 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2019 case SND_SOC_DAIFMT_DSP_A:
2020 case SND_SOC_DAIFMT_DSP_B:
2021 /* frame inversion not valid for DSP modes */
2022 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2023 case SND_SOC_DAIFMT_NB_NF:
2025 case SND_SOC_DAIFMT_IB_NF:
2026 aif1 |= WM8994_AIF1_BCLK_INV;
2033 case SND_SOC_DAIFMT_I2S:
2034 case SND_SOC_DAIFMT_RIGHT_J:
2035 case SND_SOC_DAIFMT_LEFT_J:
2036 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2037 case SND_SOC_DAIFMT_NB_NF:
2039 case SND_SOC_DAIFMT_IB_IF:
2040 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2042 case SND_SOC_DAIFMT_IB_NF:
2043 aif1 |= WM8994_AIF1_BCLK_INV;
2045 case SND_SOC_DAIFMT_NB_IF:
2046 aif1 |= WM8994_AIF1_LRCLK_INV;
2056 /* The AIF2 format configuration needs to be mirrored to AIF3
2057 * on WM8958 if it's in use so just do it all the time. */
2058 if (control->type == WM8958 && dai->id == 2)
2059 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2060 WM8994_AIF1_LRCLK_INV |
2061 WM8958_AIF3_FMT_MASK, aif1);
2063 snd_soc_update_bits(codec, aif1_reg,
2064 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2065 WM8994_AIF1_FMT_MASK,
2067 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2089 static int fs_ratios[] = {
2090 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2093 static int bclk_divs[] = {
2094 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2095 640, 880, 960, 1280, 1760, 1920
2098 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2099 struct snd_pcm_hw_params *params,
2100 struct snd_soc_dai *dai)
2102 struct snd_soc_codec *codec = dai->codec;
2103 struct wm8994 *control = codec->control_data;
2104 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2115 int id = dai->id - 1;
2117 int i, cur_val, best_val, bclk_rate, best;
2121 aif1_reg = WM8994_AIF1_CONTROL_1;
2122 aif2_reg = WM8994_AIF1_CONTROL_2;
2123 bclk_reg = WM8994_AIF1_BCLK;
2124 rate_reg = WM8994_AIF1_RATE;
2125 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2126 wm8994->lrclk_shared[0]) {
2127 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2129 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2130 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2134 aif1_reg = WM8994_AIF2_CONTROL_1;
2135 aif2_reg = WM8994_AIF2_CONTROL_2;
2136 bclk_reg = WM8994_AIF2_BCLK;
2137 rate_reg = WM8994_AIF2_RATE;
2138 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2139 wm8994->lrclk_shared[1]) {
2140 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2142 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2143 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2147 switch (control->type) {
2149 aif1_reg = WM8958_AIF3_CONTROL_1;
2158 bclk_rate = params_rate(params) * 2;
2159 switch (params_format(params)) {
2160 case SNDRV_PCM_FORMAT_S16_LE:
2163 case SNDRV_PCM_FORMAT_S20_3LE:
2167 case SNDRV_PCM_FORMAT_S24_LE:
2171 case SNDRV_PCM_FORMAT_S32_LE:
2179 /* Try to find an appropriate sample rate; look for an exact match. */
2180 for (i = 0; i < ARRAY_SIZE(srs); i++)
2181 if (srs[i].rate == params_rate(params))
2183 if (i == ARRAY_SIZE(srs))
2185 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2187 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2188 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2189 dai->id, wm8994->aifclk[id], bclk_rate);
2191 if (params_channels(params) == 1 &&
2192 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2193 aif2 |= WM8994_AIF1_MONO;
2195 if (wm8994->aifclk[id] == 0) {
2196 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2200 /* AIFCLK/fs ratio; look for a close match in either direction */
2202 best_val = abs((fs_ratios[0] * params_rate(params))
2203 - wm8994->aifclk[id]);
2204 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2205 cur_val = abs((fs_ratios[i] * params_rate(params))
2206 - wm8994->aifclk[id]);
2207 if (cur_val >= best_val)
2212 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2213 dai->id, fs_ratios[best]);
2216 /* We may not get quite the right frequency if using
2217 * approximate clocks so look for the closest match that is
2218 * higher than the target (we need to ensure that there enough
2219 * BCLKs to clock out the samples).
2222 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2223 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2224 if (cur_val < 0) /* BCLK table is sorted */
2228 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2229 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2230 bclk_divs[best], bclk_rate);
2231 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2233 lrclk = bclk_rate / params_rate(params);
2234 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2235 lrclk, bclk_rate / lrclk);
2237 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2238 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2239 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2240 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2242 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2243 WM8994_AIF1CLK_RATE_MASK, rate_val);
2245 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2248 wm8994->dac_rates[0] = params_rate(params);
2249 wm8994_set_retune_mobile(codec, 0);
2250 wm8994_set_retune_mobile(codec, 1);
2253 wm8994->dac_rates[1] = params_rate(params);
2254 wm8994_set_retune_mobile(codec, 2);
2262 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2263 struct snd_pcm_hw_params *params,
2264 struct snd_soc_dai *dai)
2266 struct snd_soc_codec *codec = dai->codec;
2267 struct wm8994 *control = codec->control_data;
2273 switch (control->type) {
2275 aif1_reg = WM8958_AIF3_CONTROL_1;
2284 switch (params_format(params)) {
2285 case SNDRV_PCM_FORMAT_S16_LE:
2287 case SNDRV_PCM_FORMAT_S20_3LE:
2290 case SNDRV_PCM_FORMAT_S24_LE:
2293 case SNDRV_PCM_FORMAT_S32_LE:
2300 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2303 static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2304 struct snd_soc_dai *dai)
2306 struct snd_soc_codec *codec = dai->codec;
2311 rate_reg = WM8994_AIF1_RATE;
2314 rate_reg = WM8994_AIF1_RATE;
2320 /* If the DAI is idle then configure the divider tree for the
2321 * lowest output rate to save a little power if the clock is
2322 * still active (eg, because it is system clock).
2324 if (rate_reg && !dai->playback_active && !dai->capture_active)
2325 snd_soc_update_bits(codec, rate_reg,
2326 WM8994_AIF1_SR_MASK |
2327 WM8994_AIF1CLK_RATE_MASK, 0x9);
2330 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2332 struct snd_soc_codec *codec = codec_dai->codec;
2336 switch (codec_dai->id) {
2338 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2341 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2348 reg = WM8994_AIF1DAC1_MUTE;
2352 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2357 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2359 struct snd_soc_codec *codec = codec_dai->codec;
2362 switch (codec_dai->id) {
2364 reg = WM8994_AIF1_MASTER_SLAVE;
2365 mask = WM8994_AIF1_TRI;
2368 reg = WM8994_AIF2_MASTER_SLAVE;
2369 mask = WM8994_AIF2_TRI;
2372 reg = WM8994_POWER_MANAGEMENT_6;
2373 mask = WM8994_AIF3_TRI;
2384 return snd_soc_update_bits(codec, reg, mask, val);
2387 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2389 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2390 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2392 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2393 .set_sysclk = wm8994_set_dai_sysclk,
2394 .set_fmt = wm8994_set_dai_fmt,
2395 .hw_params = wm8994_hw_params,
2396 .shutdown = wm8994_aif_shutdown,
2397 .digital_mute = wm8994_aif_mute,
2398 .set_pll = wm8994_set_fll,
2399 .set_tristate = wm8994_set_tristate,
2402 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2403 .set_sysclk = wm8994_set_dai_sysclk,
2404 .set_fmt = wm8994_set_dai_fmt,
2405 .hw_params = wm8994_hw_params,
2406 .shutdown = wm8994_aif_shutdown,
2407 .digital_mute = wm8994_aif_mute,
2408 .set_pll = wm8994_set_fll,
2409 .set_tristate = wm8994_set_tristate,
2412 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2413 .hw_params = wm8994_aif3_hw_params,
2414 .set_tristate = wm8994_set_tristate,
2417 static struct snd_soc_dai_driver wm8994_dai[] = {
2419 .name = "wm8994-aif1",
2422 .stream_name = "AIF1 Playback",
2425 .rates = WM8994_RATES,
2426 .formats = WM8994_FORMATS,
2429 .stream_name = "AIF1 Capture",
2432 .rates = WM8994_RATES,
2433 .formats = WM8994_FORMATS,
2435 .ops = &wm8994_aif1_dai_ops,
2438 .name = "wm8994-aif2",
2441 .stream_name = "AIF2 Playback",
2444 .rates = WM8994_RATES,
2445 .formats = WM8994_FORMATS,
2448 .stream_name = "AIF2 Capture",
2451 .rates = WM8994_RATES,
2452 .formats = WM8994_FORMATS,
2454 .ops = &wm8994_aif2_dai_ops,
2457 .name = "wm8994-aif3",
2460 .stream_name = "AIF3 Playback",
2463 .rates = WM8994_RATES,
2464 .formats = WM8994_FORMATS,
2467 .stream_name = "AIF3 Capture",
2470 .rates = WM8994_RATES,
2471 .formats = WM8994_FORMATS,
2473 .ops = &wm8994_aif3_dai_ops,
2478 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2480 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2481 struct wm8994 *control = codec->control_data;
2484 switch (control->type) {
2486 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2489 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2490 WM8958_MICD_ENA, 0);
2494 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2495 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2496 sizeof(struct wm8994_fll_config));
2497 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2499 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2503 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2508 static int wm8994_resume(struct snd_soc_codec *codec)
2510 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2511 struct wm8994 *control = codec->control_data;
2513 unsigned int val, mask;
2515 if (wm8994->revision < 4) {
2516 /* force a HW read */
2517 val = wm8994_reg_read(codec->control_data,
2518 WM8994_POWER_MANAGEMENT_5);
2520 /* modify the cache only */
2521 codec->cache_only = 1;
2522 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2523 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2525 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2527 codec->cache_only = 0;
2530 /* Restore the registers */
2531 ret = snd_soc_cache_sync(codec);
2533 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2535 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2537 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2538 if (!wm8994->fll_suspend[i].out)
2541 ret = _wm8994_set_fll(codec, i + 1,
2542 wm8994->fll_suspend[i].src,
2543 wm8994->fll_suspend[i].in,
2544 wm8994->fll_suspend[i].out);
2546 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2550 switch (control->type) {
2552 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2553 snd_soc_update_bits(codec, WM8994_MICBIAS,
2554 WM8994_MICD_ENA, WM8994_MICD_ENA);
2557 if (wm8994->jack_cb)
2558 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2559 WM8958_MICD_ENA, WM8958_MICD_ENA);
2566 #define wm8994_suspend NULL
2567 #define wm8994_resume NULL
2570 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2572 struct snd_soc_codec *codec = wm8994->codec;
2573 struct wm8994_pdata *pdata = wm8994->pdata;
2574 struct snd_kcontrol_new controls[] = {
2575 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2576 wm8994->retune_mobile_enum,
2577 wm8994_get_retune_mobile_enum,
2578 wm8994_put_retune_mobile_enum),
2579 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2580 wm8994->retune_mobile_enum,
2581 wm8994_get_retune_mobile_enum,
2582 wm8994_put_retune_mobile_enum),
2583 SOC_ENUM_EXT("AIF2 EQ Mode",
2584 wm8994->retune_mobile_enum,
2585 wm8994_get_retune_mobile_enum,
2586 wm8994_put_retune_mobile_enum),
2591 /* We need an array of texts for the enum API but the number
2592 * of texts is likely to be less than the number of
2593 * configurations due to the sample rate dependency of the
2594 * configurations. */
2595 wm8994->num_retune_mobile_texts = 0;
2596 wm8994->retune_mobile_texts = NULL;
2597 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2598 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2599 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2600 wm8994->retune_mobile_texts[j]) == 0)
2604 if (j != wm8994->num_retune_mobile_texts)
2607 /* Expand the array... */
2608 t = krealloc(wm8994->retune_mobile_texts,
2610 (wm8994->num_retune_mobile_texts + 1),
2615 /* ...store the new entry... */
2616 t[wm8994->num_retune_mobile_texts] =
2617 pdata->retune_mobile_cfgs[i].name;
2619 /* ...and remember the new version. */
2620 wm8994->num_retune_mobile_texts++;
2621 wm8994->retune_mobile_texts = t;
2624 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2625 wm8994->num_retune_mobile_texts);
2627 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2628 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2630 ret = snd_soc_add_controls(wm8994->codec, controls,
2631 ARRAY_SIZE(controls));
2633 dev_err(wm8994->codec->dev,
2634 "Failed to add ReTune Mobile controls: %d\n", ret);
2637 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2639 struct snd_soc_codec *codec = wm8994->codec;
2640 struct wm8994_pdata *pdata = wm8994->pdata;
2646 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2647 pdata->lineout2_diff,
2652 pdata->micbias1_lvl,
2653 pdata->micbias2_lvl);
2655 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2657 if (pdata->num_drc_cfgs) {
2658 struct snd_kcontrol_new controls[] = {
2659 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2660 wm8994_get_drc_enum, wm8994_put_drc_enum),
2661 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2662 wm8994_get_drc_enum, wm8994_put_drc_enum),
2663 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2664 wm8994_get_drc_enum, wm8994_put_drc_enum),
2667 /* We need an array of texts for the enum API */
2668 wm8994->drc_texts = kmalloc(sizeof(char *)
2669 * pdata->num_drc_cfgs, GFP_KERNEL);
2670 if (!wm8994->drc_texts) {
2671 dev_err(wm8994->codec->dev,
2672 "Failed to allocate %d DRC config texts\n",
2673 pdata->num_drc_cfgs);
2677 for (i = 0; i < pdata->num_drc_cfgs; i++)
2678 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2680 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2681 wm8994->drc_enum.texts = wm8994->drc_texts;
2683 ret = snd_soc_add_controls(wm8994->codec, controls,
2684 ARRAY_SIZE(controls));
2686 dev_err(wm8994->codec->dev,
2687 "Failed to add DRC mode controls: %d\n", ret);
2689 for (i = 0; i < WM8994_NUM_DRC; i++)
2690 wm8994_set_drc(codec, i);
2693 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2694 pdata->num_retune_mobile_cfgs);
2696 if (pdata->num_retune_mobile_cfgs)
2697 wm8994_handle_retune_mobile_pdata(wm8994);
2699 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2700 ARRAY_SIZE(wm8994_eq_controls));
2702 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2703 if (pdata->micbias[i]) {
2704 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2705 pdata->micbias[i] & 0xffff);
2711 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2713 * @codec: WM8994 codec
2714 * @jack: jack to report detection events on
2715 * @micbias: microphone bias to detect on
2716 * @det: value to report for presence detection
2717 * @shrt: value to report for short detection
2719 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2720 * being used to bring out signals to the processor then only platform
2721 * data configuration is needed for WM8994 and processor GPIOs should
2722 * be configured using snd_soc_jack_add_gpios() instead.
2724 * Configuration of detection levels is available via the micbias1_lvl
2725 * and micbias2_lvl platform data members.
2727 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2728 int micbias, int det, int shrt)
2730 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2731 struct wm8994_micdet *micdet;
2732 struct wm8994 *control = codec->control_data;
2735 if (control->type != WM8994)
2740 micdet = &wm8994->micdet[0];
2743 micdet = &wm8994->micdet[1];
2749 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2750 micbias, det, shrt);
2752 /* Store the configuration */
2753 micdet->jack = jack;
2755 micdet->shrt = shrt;
2757 /* If either of the jacks is set up then enable detection */
2758 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2759 reg = WM8994_MICD_ENA;
2763 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2767 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2769 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2771 struct wm8994_priv *priv = data;
2772 struct snd_soc_codec *codec = priv->codec;
2776 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2777 trace_snd_soc_jack_irq(dev_name(codec->dev));
2780 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2782 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2787 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2790 if (reg & WM8994_MIC1_DET_STS)
2791 report |= priv->micdet[0].det;
2792 if (reg & WM8994_MIC1_SHRT_STS)
2793 report |= priv->micdet[0].shrt;
2794 snd_soc_jack_report(priv->micdet[0].jack, report,
2795 priv->micdet[0].det | priv->micdet[0].shrt);
2798 if (reg & WM8994_MIC2_DET_STS)
2799 report |= priv->micdet[1].det;
2800 if (reg & WM8994_MIC2_SHRT_STS)
2801 report |= priv->micdet[1].shrt;
2802 snd_soc_jack_report(priv->micdet[1].jack, report,
2803 priv->micdet[1].det | priv->micdet[1].shrt);
2808 /* Default microphone detection handler for WM8958 - the user can
2809 * override this if they wish.
2811 static void wm8958_default_micdet(u16 status, void *data)
2813 struct snd_soc_codec *codec = data;
2814 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2817 /* If nothing present then clear our statuses */
2818 if (!(status & WM8958_MICD_STS))
2821 report = SND_JACK_MICROPHONE;
2823 /* Everything else is buttons; just assign slots */
2825 report |= SND_JACK_BTN_0;
2828 snd_soc_jack_report(wm8994->micdet[0].jack, report,
2829 SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2833 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2835 * @codec: WM8958 codec
2836 * @jack: jack to report detection events on
2838 * Enable microphone detection functionality for the WM8958. By
2839 * default simple detection which supports the detection of up to 6
2840 * buttons plus video and microphone functionality is supported.
2842 * The WM8958 has an advanced jack detection facility which is able to
2843 * support complex accessory detection, especially when used in
2844 * conjunction with external circuitry. In order to provide maximum
2845 * flexiblity a callback is provided which allows a completely custom
2846 * detection algorithm.
2848 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2849 wm8958_micdet_cb cb, void *cb_data)
2851 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2852 struct wm8994 *control = codec->control_data;
2854 if (control->type != WM8958)
2859 dev_dbg(codec->dev, "Using default micdet callback\n");
2860 cb = wm8958_default_micdet;
2864 wm8994->micdet[0].jack = jack;
2865 wm8994->jack_cb = cb;
2866 wm8994->jack_cb_data = cb_data;
2868 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2869 WM8958_MICD_ENA, WM8958_MICD_ENA);
2871 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2872 WM8958_MICD_ENA, 0);
2877 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2879 static irqreturn_t wm8958_mic_irq(int irq, void *data)
2881 struct wm8994_priv *wm8994 = data;
2882 struct snd_soc_codec *codec = wm8994->codec;
2885 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2887 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2892 if (!(reg & WM8958_MICD_VALID)) {
2893 dev_dbg(codec->dev, "Mic detect data not valid\n");
2897 #ifndef CONFIG_SND_SOC_WM8994_MODULE
2898 trace_snd_soc_jack_irq(dev_name(codec->dev));
2901 if (wm8994->jack_cb)
2902 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2904 dev_warn(codec->dev, "Accessory detection with no callback\n");
2910 static irqreturn_t wm8994_fifo_error(int irq, void *data)
2912 struct snd_soc_codec *codec = data;
2914 dev_err(codec->dev, "FIFO error\n");
2919 static int wm8994_codec_probe(struct snd_soc_codec *codec)
2921 struct wm8994 *control;
2922 struct wm8994_priv *wm8994;
2923 struct snd_soc_dapm_context *dapm = &codec->dapm;
2926 codec->control_data = dev_get_drvdata(codec->dev->parent);
2927 control = codec->control_data;
2929 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2932 snd_soc_codec_set_drvdata(codec, wm8994);
2934 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2935 wm8994->codec = codec;
2937 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2938 init_completion(&wm8994->fll_locked[i]);
2940 if (wm8994->pdata && wm8994->pdata->micdet_irq)
2941 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2942 else if (wm8994->pdata && wm8994->pdata->irq_base)
2943 wm8994->micdet_irq = wm8994->pdata->irq_base +
2944 WM8994_IRQ_MIC1_DET;
2946 pm_runtime_enable(codec->dev);
2947 pm_runtime_resume(codec->dev);
2949 /* Read our current status back from the chip - we don't want to
2950 * reset as this may interfere with the GPIO or LDO operation. */
2951 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2952 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
2955 ret = wm8994_reg_read(codec->control_data, i);
2959 ret = snd_soc_cache_write(codec, i, ret);
2962 "Failed to initialise cache for 0x%x: %d\n",
2968 /* Set revision-specific configuration */
2969 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2970 switch (control->type) {
2972 switch (wm8994->revision) {
2975 wm8994->hubs.dcs_codes = -5;
2976 wm8994->hubs.hp_startup_mode = 1;
2977 wm8994->hubs.dcs_readback_mode = 1;
2978 wm8994->hubs.series_startup = 1;
2981 wm8994->hubs.dcs_readback_mode = 1;
2986 wm8994->hubs.dcs_readback_mode = 1;
2993 wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
2994 wm8994_fifo_error, "FIFO error", codec);
2996 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
2997 wm_hubs_dcs_done, "DC servo done",
3000 wm8994->hubs.dcs_done_irq = true;
3002 switch (control->type) {
3004 if (wm8994->micdet_irq) {
3005 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3007 IRQF_TRIGGER_RISING,
3011 dev_warn(codec->dev,
3012 "Failed to request Mic1 detect IRQ: %d\n",
3016 ret = wm8994_request_irq(codec->control_data,
3017 WM8994_IRQ_MIC1_SHRT,
3018 wm8994_mic_irq, "Mic 1 short",
3021 dev_warn(codec->dev,
3022 "Failed to request Mic1 short IRQ: %d\n",
3025 ret = wm8994_request_irq(codec->control_data,
3026 WM8994_IRQ_MIC2_DET,
3027 wm8994_mic_irq, "Mic 2 detect",
3030 dev_warn(codec->dev,
3031 "Failed to request Mic2 detect IRQ: %d\n",
3034 ret = wm8994_request_irq(codec->control_data,
3035 WM8994_IRQ_MIC2_SHRT,
3036 wm8994_mic_irq, "Mic 2 short",
3039 dev_warn(codec->dev,
3040 "Failed to request Mic2 short IRQ: %d\n",
3045 if (wm8994->micdet_irq) {
3046 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3048 IRQF_TRIGGER_RISING,
3052 dev_warn(codec->dev,
3053 "Failed to request Mic detect IRQ: %d\n",
3058 wm8994->fll_locked_irq = true;
3059 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3060 ret = wm8994_request_irq(codec->control_data,
3061 WM8994_IRQ_FLL1_LOCK + i,
3062 wm8994_fll_locked_irq, "FLL lock",
3063 &wm8994->fll_locked[i]);
3065 wm8994->fll_locked_irq = false;
3068 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3069 * configured on init - if a system wants to do this dynamically
3070 * at runtime we can deal with that then.
3072 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3074 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3077 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3078 wm8994->lrclk_shared[0] = 1;
3079 wm8994_dai[0].symmetric_rates = 1;
3081 wm8994->lrclk_shared[0] = 0;
3084 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3086 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3089 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3090 wm8994->lrclk_shared[1] = 1;
3091 wm8994_dai[1].symmetric_rates = 1;
3093 wm8994->lrclk_shared[1] = 0;
3096 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3098 /* Latch volume updates (right only; we always do left then right). */
3099 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3100 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3101 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3102 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3103 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3104 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3105 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3106 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3107 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3108 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3109 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3110 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3111 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3112 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3113 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3114 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3115 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3116 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3117 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3118 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3119 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3120 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3121 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3122 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3123 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3124 WM8994_DAC1_VU, WM8994_DAC1_VU);
3125 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3126 WM8994_DAC1_VU, WM8994_DAC1_VU);
3127 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3128 WM8994_DAC2_VU, WM8994_DAC2_VU);
3129 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3130 WM8994_DAC2_VU, WM8994_DAC2_VU);
3132 /* Set the low bit of the 3D stereo depth so TLV matches */
3133 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3134 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3135 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3136 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3137 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3138 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3139 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3140 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3141 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3143 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3144 * use this; it only affects behaviour on idle TDM clock
3146 switch (control->type) {
3149 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3150 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3156 wm8994_update_class_w(codec);
3158 wm8994_handle_pdata(wm8994);
3160 wm_hubs_add_analogue_controls(codec);
3161 snd_soc_add_controls(codec, wm8994_snd_controls,
3162 ARRAY_SIZE(wm8994_snd_controls));
3163 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3164 ARRAY_SIZE(wm8994_dapm_widgets));
3166 switch (control->type) {
3168 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3169 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3170 if (wm8994->revision < 4) {
3171 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3172 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3173 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3174 ARRAY_SIZE(wm8994_adc_revd_widgets));
3175 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3176 ARRAY_SIZE(wm8994_dac_revd_widgets));
3178 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3179 ARRAY_SIZE(wm8994_lateclk_widgets));
3180 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3181 ARRAY_SIZE(wm8994_adc_widgets));
3182 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3183 ARRAY_SIZE(wm8994_dac_widgets));
3187 snd_soc_add_controls(codec, wm8958_snd_controls,
3188 ARRAY_SIZE(wm8958_snd_controls));
3189 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3190 ARRAY_SIZE(wm8958_dapm_widgets));
3191 if (wm8994->revision < 1) {
3192 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3193 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3194 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3195 ARRAY_SIZE(wm8994_adc_revd_widgets));
3196 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3197 ARRAY_SIZE(wm8994_dac_revd_widgets));
3199 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3200 ARRAY_SIZE(wm8994_lateclk_widgets));
3201 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3202 ARRAY_SIZE(wm8994_adc_widgets));
3203 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3204 ARRAY_SIZE(wm8994_dac_widgets));
3210 wm_hubs_add_analogue_routes(codec, 0, 0);
3211 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3213 switch (control->type) {
3215 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3216 ARRAY_SIZE(wm8994_intercon));
3218 if (wm8994->revision < 4) {
3219 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3220 ARRAY_SIZE(wm8994_revd_intercon));
3221 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3222 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3224 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3225 ARRAY_SIZE(wm8994_lateclk_intercon));
3229 if (wm8994->revision < 1) {
3230 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3231 ARRAY_SIZE(wm8994_revd_intercon));
3232 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3233 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3235 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3236 ARRAY_SIZE(wm8994_lateclk_intercon));
3237 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3238 ARRAY_SIZE(wm8958_intercon));
3241 wm8958_dsp2_init(codec);
3248 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3249 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3250 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3251 if (wm8994->micdet_irq)
3252 free_irq(wm8994->micdet_irq, wm8994);
3253 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3254 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3255 &wm8994->fll_locked[i]);
3256 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3258 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3264 static int wm8994_codec_remove(struct snd_soc_codec *codec)
3266 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3267 struct wm8994 *control = codec->control_data;
3270 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3272 pm_runtime_disable(codec->dev);
3274 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3275 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3276 &wm8994->fll_locked[i]);
3278 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3280 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3282 switch (control->type) {
3284 if (wm8994->micdet_irq)
3285 free_irq(wm8994->micdet_irq, wm8994);
3286 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3288 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3290 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3295 if (wm8994->micdet_irq)
3296 free_irq(wm8994->micdet_irq, wm8994);
3300 release_firmware(wm8994->mbc);
3301 if (wm8994->mbc_vss)
3302 release_firmware(wm8994->mbc_vss);
3304 release_firmware(wm8994->enh_eq);
3305 kfree(wm8994->retune_mobile_texts);
3306 kfree(wm8994->drc_texts);
3312 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3313 .probe = wm8994_codec_probe,
3314 .remove = wm8994_codec_remove,
3315 .suspend = wm8994_suspend,
3316 .resume = wm8994_resume,
3317 .read = wm8994_read,
3318 .write = wm8994_write,
3319 .readable_register = wm8994_readable,
3320 .volatile_register = wm8994_volatile,
3321 .set_bias_level = wm8994_set_bias_level,
3323 .reg_cache_size = WM8994_CACHE_SIZE,
3324 .reg_cache_default = wm8994_reg_defaults,
3326 .compress_type = SND_SOC_RBTREE_COMPRESSION,
3329 static int __devinit wm8994_probe(struct platform_device *pdev)
3331 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3332 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3335 static int __devexit wm8994_remove(struct platform_device *pdev)
3337 snd_soc_unregister_codec(&pdev->dev);
3341 static struct platform_driver wm8994_codec_driver = {
3343 .name = "wm8994-codec",
3344 .owner = THIS_MODULE,
3346 .probe = wm8994_probe,
3347 .remove = __devexit_p(wm8994_remove),
3350 static __init int wm8994_init(void)
3352 return platform_driver_register(&wm8994_codec_driver);
3354 module_init(wm8994_init);
3356 static __exit void wm8994_exit(void)
3358 platform_driver_unregister(&wm8994_codec_driver);
3360 module_exit(wm8994_exit);
3363 MODULE_DESCRIPTION("ASoC WM8994 driver");
3364 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3365 MODULE_LICENSE("GPL");
3366 MODULE_ALIAS("platform:wm8994-codec");